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MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_led_controller_0_0/ip_design_led_controller_0_0_sim_netlist.vhdl | 1 | 66,664 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:28 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_led_controller_0_0/ip_design_led_controller_0_0_sim_netlist.vhdl
-- Design : ip_design_led_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_led_controller_0_0_led_controller_v1_0_S00_AXI is
port (
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_bvalid : out STD_LOGIC;
s00_axi_arvalid : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_aresetn : in STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_led_controller_0_0_led_controller_v1_0_S00_AXI : entity is "led_controller_v1_0_S00_AXI";
end ip_design_led_controller_0_0_led_controller_v1_0_S00_AXI;
architecture STRUCTURE of ip_design_led_controller_0_0_led_controller_v1_0_S00_AXI is
signal \^leds_out\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal aw_en_i_1_n_0 : STD_LOGIC;
signal aw_en_reg_n_0 : STD_LOGIC;
signal axi_araddr : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \axi_araddr[2]_i_1_n_0\ : STD_LOGIC;
signal \axi_araddr[3]_i_1_n_0\ : STD_LOGIC;
signal axi_arready_i_1_n_0 : STD_LOGIC;
signal \axi_awaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \axi_awaddr[3]_i_1_n_0\ : STD_LOGIC;
signal axi_awready0 : STD_LOGIC;
signal axi_bvalid_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_i_1_n_0 : STD_LOGIC;
signal axi_wready0 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 7 );
signal reg_data_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s00_axi_bvalid\ : STD_LOGIC;
signal \^s00_axi_rvalid\ : STD_LOGIC;
signal slv_reg0 : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \slv_reg0[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg1[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg2 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg2[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg3 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg3[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[7]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg_rden__0\ : STD_LOGIC;
signal \slv_reg_wren__0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axi_araddr[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_arready_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_wready_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \slv_reg0[7]_i_3\ : label is "soft_lutpair0";
begin
LEDs_out(7 downto 0) <= \^leds_out\(7 downto 0);
S_AXI_ARREADY <= \^s_axi_arready\;
S_AXI_AWREADY <= \^s_axi_awready\;
S_AXI_WREADY <= \^s_axi_wready\;
s00_axi_bvalid <= \^s00_axi_bvalid\;
s00_axi_rvalid <= \^s00_axi_rvalid\;
aw_en_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFC4CCC4CCC4CC"
)
port map (
I0 => s00_axi_wvalid,
I1 => aw_en_reg_n_0,
I2 => \^s_axi_awready\,
I3 => s00_axi_awvalid,
I4 => s00_axi_bready,
I5 => \^s00_axi_bvalid\,
O => aw_en_i_1_n_0
);
aw_en_reg: unisim.vcomponents.FDSE
port map (
C => s00_axi_aclk,
CE => '1',
D => aw_en_i_1_n_0,
Q => aw_en_reg_n_0,
S => \slv_reg0[7]_i_1_n_0\
);
\axi_araddr[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s00_axi_araddr(0),
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
I3 => axi_araddr(2),
O => \axi_araddr[2]_i_1_n_0\
);
\axi_araddr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s00_axi_araddr(1),
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
I3 => axi_araddr(3),
O => \axi_araddr[3]_i_1_n_0\
);
\axi_araddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_araddr[2]_i_1_n_0\,
Q => axi_araddr(2),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_araddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_araddr[3]_i_1_n_0\,
Q => axi_araddr(3),
R => \slv_reg0[7]_i_1_n_0\
);
axi_arready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s00_axi_arvalid,
I1 => \^s_axi_arready\,
O => axi_arready_i_1_n_0
);
axi_arready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_arready_i_1_n_0,
Q => \^s_axi_arready\,
R => \slv_reg0[7]_i_1_n_0\
);
\axi_awaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s00_axi_awaddr(0),
I1 => s00_axi_awvalid,
I2 => \^s_axi_awready\,
I3 => aw_en_reg_n_0,
I4 => s00_axi_wvalid,
I5 => p_0_in(0),
O => \axi_awaddr[2]_i_1_n_0\
);
\axi_awaddr[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s00_axi_awaddr(1),
I1 => s00_axi_awvalid,
I2 => \^s_axi_awready\,
I3 => aw_en_reg_n_0,
I4 => s00_axi_wvalid,
I5 => p_0_in(1),
O => \axi_awaddr[3]_i_1_n_0\
);
\axi_awaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_awaddr[2]_i_1_n_0\,
Q => p_0_in(0),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_awaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_awaddr[3]_i_1_n_0\,
Q => p_0_in(1),
R => \slv_reg0[7]_i_1_n_0\
);
axi_awready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => s00_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => aw_en_reg_n_0,
I3 => s00_axi_wvalid,
O => axi_awready0
);
axi_awready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_awready0,
Q => \^s_axi_awready\,
R => \slv_reg0[7]_i_1_n_0\
);
axi_bvalid_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF80008000"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_awready\,
I2 => s00_axi_awvalid,
I3 => s00_axi_wvalid,
I4 => s00_axi_bready,
I5 => \^s00_axi_bvalid\,
O => axi_bvalid_i_1_n_0
);
axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_bvalid_i_1_n_0,
Q => \^s00_axi_bvalid\,
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(0),
I1 => \^leds_out\(0),
I2 => slv_reg3(0),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(0),
O => reg_data_out(0)
);
\axi_rdata[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(10),
I1 => slv_reg0(10),
I2 => slv_reg3(10),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(10),
O => reg_data_out(10)
);
\axi_rdata[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(11),
I1 => slv_reg0(11),
I2 => slv_reg3(11),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(11),
O => reg_data_out(11)
);
\axi_rdata[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(12),
I1 => slv_reg0(12),
I2 => slv_reg3(12),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(12),
O => reg_data_out(12)
);
\axi_rdata[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(13),
I1 => slv_reg0(13),
I2 => slv_reg3(13),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(13),
O => reg_data_out(13)
);
\axi_rdata[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(14),
I1 => slv_reg0(14),
I2 => slv_reg3(14),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(14),
O => reg_data_out(14)
);
\axi_rdata[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(15),
I1 => slv_reg0(15),
I2 => slv_reg3(15),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(15),
O => reg_data_out(15)
);
\axi_rdata[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(16),
I1 => slv_reg0(16),
I2 => slv_reg3(16),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(16),
O => reg_data_out(16)
);
\axi_rdata[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(17),
I1 => slv_reg0(17),
I2 => slv_reg3(17),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(17),
O => reg_data_out(17)
);
\axi_rdata[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(18),
I1 => slv_reg0(18),
I2 => slv_reg3(18),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(18),
O => reg_data_out(18)
);
\axi_rdata[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(19),
I1 => slv_reg0(19),
I2 => slv_reg3(19),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(19),
O => reg_data_out(19)
);
\axi_rdata[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(1),
I1 => \^leds_out\(1),
I2 => slv_reg3(1),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(1),
O => reg_data_out(1)
);
\axi_rdata[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(20),
I1 => slv_reg0(20),
I2 => slv_reg3(20),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(20),
O => reg_data_out(20)
);
\axi_rdata[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(21),
I1 => slv_reg0(21),
I2 => slv_reg3(21),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(21),
O => reg_data_out(21)
);
\axi_rdata[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(22),
I1 => slv_reg0(22),
I2 => slv_reg3(22),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(22),
O => reg_data_out(22)
);
\axi_rdata[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(23),
I1 => slv_reg0(23),
I2 => slv_reg3(23),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(23),
O => reg_data_out(23)
);
\axi_rdata[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(24),
I1 => slv_reg0(24),
I2 => slv_reg3(24),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(24),
O => reg_data_out(24)
);
\axi_rdata[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(25),
I1 => slv_reg0(25),
I2 => slv_reg3(25),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(25),
O => reg_data_out(25)
);
\axi_rdata[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(26),
I1 => slv_reg0(26),
I2 => slv_reg3(26),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(26),
O => reg_data_out(26)
);
\axi_rdata[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(27),
I1 => slv_reg0(27),
I2 => slv_reg3(27),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(27),
O => reg_data_out(27)
);
\axi_rdata[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(28),
I1 => slv_reg0(28),
I2 => slv_reg3(28),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(28),
O => reg_data_out(28)
);
\axi_rdata[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(29),
I1 => slv_reg0(29),
I2 => slv_reg3(29),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(29),
O => reg_data_out(29)
);
\axi_rdata[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(2),
I1 => \^leds_out\(2),
I2 => slv_reg3(2),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(2),
O => reg_data_out(2)
);
\axi_rdata[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(30),
I1 => slv_reg0(30),
I2 => slv_reg3(30),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(30),
O => reg_data_out(30)
);
\axi_rdata[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(31),
I1 => slv_reg0(31),
I2 => slv_reg3(31),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(31),
O => reg_data_out(31)
);
\axi_rdata[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(3),
I1 => \^leds_out\(3),
I2 => slv_reg3(3),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(3),
O => reg_data_out(3)
);
\axi_rdata[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(4),
I1 => \^leds_out\(4),
I2 => slv_reg3(4),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(4),
O => reg_data_out(4)
);
\axi_rdata[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(5),
I1 => \^leds_out\(5),
I2 => slv_reg3(5),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(5),
O => reg_data_out(5)
);
\axi_rdata[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(6),
I1 => \^leds_out\(6),
I2 => slv_reg3(6),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(6),
O => reg_data_out(6)
);
\axi_rdata[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(7),
I1 => \^leds_out\(7),
I2 => slv_reg3(7),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(7),
O => reg_data_out(7)
);
\axi_rdata[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(8),
I1 => slv_reg0(8),
I2 => slv_reg3(8),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(8),
O => reg_data_out(8)
);
\axi_rdata[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(9),
I1 => slv_reg0(9),
I2 => slv_reg3(9),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(9),
O => reg_data_out(9)
);
\axi_rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(0),
Q => s00_axi_rdata(0),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(10),
Q => s00_axi_rdata(10),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(11),
Q => s00_axi_rdata(11),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(12),
Q => s00_axi_rdata(12),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(13),
Q => s00_axi_rdata(13),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(14),
Q => s00_axi_rdata(14),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(15),
Q => s00_axi_rdata(15),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(16),
Q => s00_axi_rdata(16),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(17),
Q => s00_axi_rdata(17),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(18),
Q => s00_axi_rdata(18),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(19),
Q => s00_axi_rdata(19),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(1),
Q => s00_axi_rdata(1),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(20),
Q => s00_axi_rdata(20),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(21),
Q => s00_axi_rdata(21),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(22),
Q => s00_axi_rdata(22),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(23),
Q => s00_axi_rdata(23),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(24),
Q => s00_axi_rdata(24),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(25),
Q => s00_axi_rdata(25),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(26),
Q => s00_axi_rdata(26),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(27),
Q => s00_axi_rdata(27),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(28),
Q => s00_axi_rdata(28),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(29),
Q => s00_axi_rdata(29),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(2),
Q => s00_axi_rdata(2),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(30),
Q => s00_axi_rdata(30),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(31),
Q => s00_axi_rdata(31),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(3),
Q => s00_axi_rdata(3),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(4),
Q => s00_axi_rdata(4),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(5),
Q => s00_axi_rdata(5),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(6),
Q => s00_axi_rdata(6),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(7),
Q => s00_axi_rdata(7),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(8),
Q => s00_axi_rdata(8),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(9),
Q => s00_axi_rdata(9),
R => \slv_reg0[7]_i_1_n_0\
);
axi_rvalid_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"08F8"
)
port map (
I0 => \^s_axi_arready\,
I1 => s00_axi_arvalid,
I2 => \^s00_axi_rvalid\,
I3 => s00_axi_rready,
O => axi_rvalid_i_1_n_0
);
axi_rvalid_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_rvalid_i_1_n_0,
Q => \^s00_axi_rvalid\,
R => \slv_reg0[7]_i_1_n_0\
);
axi_wready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \^s_axi_wready\,
I1 => s00_axi_wvalid,
I2 => s00_axi_awvalid,
I3 => aw_en_reg_n_0,
O => axi_wready0
);
axi_wready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_wready0,
Q => \^s_axi_wready\,
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(1),
O => p_1_in(15)
);
\slv_reg0[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(2),
O => p_1_in(23)
);
\slv_reg0[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(3),
O => p_1_in(31)
);
\slv_reg0[7]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s00_axi_aresetn,
O => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(0),
O => p_1_in(7)
);
\slv_reg0[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_awready\,
I2 => s00_axi_awvalid,
I3 => s00_axi_wvalid,
O => \slv_reg_wren__0\
);
\slv_reg0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(0),
Q => \^leds_out\(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(10),
Q => slv_reg0(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(11),
Q => slv_reg0(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(12),
Q => slv_reg0(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(13),
Q => slv_reg0(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(14),
Q => slv_reg0(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(15),
Q => slv_reg0(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(16),
Q => slv_reg0(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(17),
Q => slv_reg0(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(18),
Q => slv_reg0(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(19),
Q => slv_reg0(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(1),
Q => \^leds_out\(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(20),
Q => slv_reg0(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(21),
Q => slv_reg0(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(22),
Q => slv_reg0(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(23),
Q => slv_reg0(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(24),
Q => slv_reg0(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(25),
Q => slv_reg0(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(26),
Q => slv_reg0(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(27),
Q => slv_reg0(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(28),
Q => slv_reg0(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(29),
Q => slv_reg0(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(2),
Q => \^leds_out\(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(30),
Q => slv_reg0(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(31),
Q => slv_reg0(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(3),
Q => \^leds_out\(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(4),
Q => \^leds_out\(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(5),
Q => \^leds_out\(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(6),
Q => \^leds_out\(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(7),
Q => \^leds_out\(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(8),
Q => slv_reg0(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(9),
Q => slv_reg0(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(1),
I3 => p_0_in(0),
O => \slv_reg1[15]_i_1_n_0\
);
\slv_reg1[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(2),
I3 => p_0_in(0),
O => \slv_reg1[23]_i_1_n_0\
);
\slv_reg1[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(3),
I3 => p_0_in(0),
O => \slv_reg1[31]_i_1_n_0\
);
\slv_reg1[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(0),
I3 => p_0_in(0),
O => \slv_reg1[7]_i_1_n_0\
);
\slv_reg1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg1(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg1(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg1(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg1(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg1(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg1(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg1(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg1(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg1(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg1(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg1(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg1(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg1(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg1(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg1(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg1(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg1(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg1(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg1(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg1(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg1(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg1(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg1(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg1(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg1(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg1(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg1(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg1(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg1(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg1(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg1(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg1(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(1),
I3 => p_0_in(0),
O => \slv_reg2[15]_i_1_n_0\
);
\slv_reg2[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(2),
I3 => p_0_in(0),
O => \slv_reg2[23]_i_1_n_0\
);
\slv_reg2[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(3),
I3 => p_0_in(0),
O => \slv_reg2[31]_i_1_n_0\
);
\slv_reg2[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(0),
I3 => p_0_in(0),
O => \slv_reg2[7]_i_1_n_0\
);
\slv_reg2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg2(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg2(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg2(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg2(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg2(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg2(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg2(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg2(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg2(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg2(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg2(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg2(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg2(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg2(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg2(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg2(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg2(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg2(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg2(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg2(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg2(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg2(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg2(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg2(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg2(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg2(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg2(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg2(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg2(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg2(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg2(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg2(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(1),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[15]_i_1_n_0\
);
\slv_reg3[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(2),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[23]_i_1_n_0\
);
\slv_reg3[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(3),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[31]_i_1_n_0\
);
\slv_reg3[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(0),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[7]_i_1_n_0\
);
\slv_reg3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg3(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg3(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg3(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg3(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg3(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg3(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg3(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg3(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg3(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg3(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg3(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg3(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg3(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg3(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg3(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg3(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg3(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg3(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg3(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg3(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg3(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg3(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg3(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg3(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg3(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg3(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg3(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg3(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg3(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg3(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg3(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg3(9),
R => \slv_reg0[7]_i_1_n_0\
);
slv_reg_rden: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^s00_axi_rvalid\,
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
O => \slv_reg_rden__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_led_controller_0_0_led_controller_v1_0 is
port (
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_bvalid : out STD_LOGIC;
s00_axi_arvalid : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_aresetn : in STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_led_controller_0_0_led_controller_v1_0 : entity is "led_controller_v1_0";
end ip_design_led_controller_0_0_led_controller_v1_0;
architecture STRUCTURE of ip_design_led_controller_0_0_led_controller_v1_0 is
begin
led_controller_v1_0_S00_AXI_inst: entity work.ip_design_led_controller_0_0_led_controller_v1_0_S00_AXI
port map (
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WREADY => S_AXI_WREADY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_araddr(1 downto 0) => s00_axi_araddr(1 downto 0),
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(1 downto 0),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
s00_axi_rready => s00_axi_rready,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
s00_axi_wvalid => s00_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_led_controller_0_0 is
port (
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ip_design_led_controller_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of ip_design_led_controller_0_0 : entity is "ip_design_led_controller_0_0,led_controller_v1_0,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of ip_design_led_controller_0_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of ip_design_led_controller_0_0 : entity is "led_controller_v1_0,Vivado 2017.3";
end ip_design_led_controller_0_0;
architecture STRUCTURE of ip_design_led_controller_0_0 is
signal \<const0>\ : STD_LOGIC;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of s00_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of s00_axi_aclk : signal is "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of s00_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
attribute X_INTERFACE_PARAMETER of s00_axi_aresetn : signal is "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of s00_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
attribute X_INTERFACE_INFO of s00_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
attribute X_INTERFACE_INFO of s00_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
attribute X_INTERFACE_INFO of s00_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
attribute X_INTERFACE_INFO of s00_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
attribute X_INTERFACE_INFO of s00_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
attribute X_INTERFACE_INFO of s00_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s00_axi_rready : signal is "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s00_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
attribute X_INTERFACE_INFO of s00_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
attribute X_INTERFACE_INFO of s00_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
attribute X_INTERFACE_INFO of s00_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
attribute X_INTERFACE_INFO of s00_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
attribute X_INTERFACE_INFO of s00_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
attribute X_INTERFACE_INFO of s00_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
attribute X_INTERFACE_INFO of s00_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
attribute X_INTERFACE_INFO of s00_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
attribute X_INTERFACE_INFO of s00_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
attribute X_INTERFACE_INFO of s00_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
attribute X_INTERFACE_INFO of s00_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
begin
s00_axi_bresp(1) <= \<const0>\;
s00_axi_bresp(0) <= \<const0>\;
s00_axi_rresp(1) <= \<const0>\;
s00_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst: entity work.ip_design_led_controller_0_0_led_controller_v1_0
port map (
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
S_AXI_ARREADY => s00_axi_arready,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WREADY => s00_axi_wready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_araddr(1 downto 0) => s00_axi_araddr(3 downto 2),
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(3 downto 2),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
s00_axi_rready => s00_axi_rready,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
s00_axi_wvalid => s00_axi_wvalid
);
end STRUCTURE;
| mit | f9ef2c15d99b2284b4daa5845b3c84ac | 0.513186 | 2.528887 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/872e0473ecb52965/ip_design_axi_gpio_0_0_sim_netlist.vhdl | 1 | 66,862 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:10 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_axi_gpio_0_0_sim_netlist.vhdl
-- Design : ip_design_axi_gpio_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
rst_reg : in STD_LOGIC;
bus2ip_rnw_i_reg : in STD_LOGIC;
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
reg2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal Bus_RNW_reg : STD_LOGIC;
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \ip2bus_data_i_D1[30]_i_2_n_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[30]_i_2\ : label is "soft_lutpair0";
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => Q,
I2 => Bus_RNW_reg,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => Bus_RNW_reg,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(0),
I1 => \bus2ip_addr_i_reg[8]\(1),
O => ce_expnd_i_3
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_3,
Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(0),
I1 => \bus2ip_addr_i_reg[8]\(1),
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_2,
Q => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(0),
O => ce_expnd_i_1
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_1,
Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_arready\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(0),
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
R => cs_ce_clr
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => Q,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => gpio_xferAck_Reg,
I3 => GPIO_xferAck_i,
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(2),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAABAA"
)
port map (
I0 => rst_reg,
I1 => bus2ip_rnw_i_reg,
I2 => \bus2ip_addr_i_reg[8]\(0),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(2),
I5 => \bus2ip_addr_i_reg[8]\(1),
O => \Not_Dual.gpio_Data_Out_reg[0]\
);
\Not_Dual.gpio_OE[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAABAAAAA"
)
port map (
I0 => rst_reg,
I1 => bus2ip_rnw_i_reg,
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => \bus2ip_addr_i_reg[8]\(1),
O => \Not_Dual.gpio_OE_reg[0]\
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => Bus_RNW_reg,
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => D(2)
);
\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F0AC000000000"
)
port map (
I0 => reg2(1),
I1 => reg1(1),
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I5 => \ip2bus_data_i_D1[30]_i_2_n_0\,
O => D(1)
);
\ip2bus_data_i_D1[30]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Bus_RNW_reg,
I1 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => \ip2bus_data_i_D1[30]_i_2_n_0\
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F0AC000000000"
)
port map (
I0 => reg2(0),
I1 => reg1(0),
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I5 => \ip2bus_data_i_D1[30]_i_2_n_0\,
O => D(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
port (
reg1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
reg2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gpio_io_t[0]\ : out STD_LOGIC;
\gpio_io_t[1]\ : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
bus2ip_rnw_i_reg : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC;
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
rst_reg : in STD_LOGIC;
rst_reg_0 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2_n_0\ : STD_LOGIC;
signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_Data_Out[0]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_Data_Out[1]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_OE[0]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_OE[1]_i_1_n_0\ : STD_LOGIC;
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 1 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 1 );
signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^gpio_io_t[0]\ : STD_LOGIC;
signal \^gpio_io_t[1]\ : STD_LOGIC;
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal \^reg2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair8";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_io_o(1 downto 0) <= \^gpio_io_o\(1 downto 0);
\gpio_io_t[0]\ <= \^gpio_io_t[0]\;
\gpio_io_t[1]\ <= \^gpio_io_t[1]\;
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
reg2(1 downto 0) <= \^reg2\(1 downto 0);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C2E22222C222222"
)
port map (
I0 => \^gpio_io_o\(1),
I1 => \^gpio_io_t[1]\,
I2 => Q(1),
I3 => Q(0),
I4 => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
I5 => gpio_Data_In(0),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1_n_0\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1_n_0\,
Q => reg1(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C2E22222C222222"
)
port map (
I0 => \^reg2\(1),
I1 => \^gpio_io_t[1]\,
I2 => Q(1),
I3 => Q(0),
I4 => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
I5 => gpio_Data_In(0),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1_n_0\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1_n_0\,
Q => \^reg2\(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C2E22222C222222"
)
port map (
I0 => \^gpio_io_o\(0),
I1 => \^gpio_io_t[0]\,
I2 => Q(1),
I3 => Q(0),
I4 => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
I5 => gpio_Data_In(1),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2_n_0\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2_n_0\,
Q => reg1(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C2E22222C222222"
)
port map (
I0 => \^reg2\(0),
I1 => \^gpio_io_t[0]\,
I2 => Q(1),
I3 => Q(0),
I4 => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
I5 => gpio_Data_In(1),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1_n_0\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1_n_0\,
Q => \^reg2\(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
gpio_io_i(1 downto 0) => gpio_io_i(1 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(1) => gpio_io_i_d2(0),
scndry_vect_out(0) => gpio_io_i_d2(1)
);
\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => gpio_Data_In(0),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => gpio_Data_In(1),
R => '0'
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FFFFFB080000"
)
port map (
I0 => s_axi_wdata(1),
I1 => bus2ip_cs,
I2 => Q(1),
I3 => s_axi_wdata(3),
I4 => rst_reg,
I5 => \^gpio_io_o\(1),
O => \Not_Dual.gpio_Data_Out[0]_i_1_n_0\
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FFFFFB080000"
)
port map (
I0 => s_axi_wdata(0),
I1 => bus2ip_cs,
I2 => Q(1),
I3 => s_axi_wdata(2),
I4 => rst_reg,
I5 => \^gpio_io_o\(0),
O => \Not_Dual.gpio_Data_Out[1]_i_1_n_0\
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_Data_Out[0]_i_1_n_0\,
Q => \^gpio_io_o\(1),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_Data_Out[1]_i_1_n_0\,
Q => \^gpio_io_o\(0),
R => bus2ip_reset
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FFFFFB080000"
)
port map (
I0 => s_axi_wdata(1),
I1 => bus2ip_cs,
I2 => Q(1),
I3 => s_axi_wdata(3),
I4 => rst_reg_0,
I5 => \^gpio_io_t[1]\,
O => \Not_Dual.gpio_OE[0]_i_1_n_0\
);
\Not_Dual.gpio_OE[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FFFFFB080000"
)
port map (
I0 => s_axi_wdata(0),
I1 => bus2ip_cs,
I2 => Q(1),
I3 => s_axi_wdata(2),
I4 => rst_reg_0,
I5 => \^gpio_io_t[0]\,
O => \Not_Dual.gpio_OE[1]_i_1_n_0\
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE[0]_i_1_n_0\,
Q => \^gpio_io_t[1]\,
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE[1]_i_1_n_0\,
Q => \^gpio_io_t[0]\,
S => bus2ip_reset
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => bus2ip_reset
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => bus2ip_reset
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
SR : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
reg2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.allout0_nd.read_reg_gen[0].reg1_reg[30]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 0 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst_i_1_n_0 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \s_axi_rdata_i[0]_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \bus2ip_addr_i[8]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair4";
begin
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ <= \^not_dual.allout0_nd.read_reg_gen[0].reg1_reg[30]\;
Q(1 downto 0) <= \^q\(1 downto 0);
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rdata(2 downto 0) <= \^s_axi_rdata\(2 downto 0);
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(2 downto 0) => D(2 downto 0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0\,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => \Not_Dual.gpio_Data_Out_reg[0]\,
\Not_Dual.gpio_OE_reg[0]\ => \Not_Dual.gpio_OE_reg[0]\,
Q => start2,
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(1 downto 0) => \^q\(1 downto 0),
bus2ip_rnw_i_reg => \^not_dual.allout0_nd.read_reg_gen[0].reg1_reg[30]\,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
reg1(1 downto 0) => reg1(1 downto 0),
reg2(1 downto 0) => reg2(1 downto 0),
rst_reg => \^sr\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wready => \^s_axi_wready\
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => \^q\(0),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => \^q\(1),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => s_axi_arvalid,
Q => \^not_dual.allout0_nd.read_reg_gen[0].reg1_reg[30]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => rst_i_1_n_0
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rst_i_1_n_0,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \ip2bus_data_i_D1_reg[0]\(0),
I1 => state(0),
I2 => state(1),
I3 => \^s_axi_rdata\(0),
O => \s_axi_rdata_i[0]_i_1_n_0\
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \ip2bus_data_i_D1_reg[0]\(1),
I1 => state(0),
I2 => state(1),
I3 => \^s_axi_rdata\(1),
O => \s_axi_rdata_i[1]_i_1_n_0\
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \ip2bus_data_i_D1_reg[0]\(2),
I1 => state(0),
I2 => state(1),
I3 => \^s_axi_rdata\(2),
O => \s_axi_rdata_i[31]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_rdata_i[0]_i_1_n_0\,
Q => \^s_axi_rdata\(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_rdata_i[1]_i_1_n_0\,
Q => \^s_axi_rdata\(1),
R => \^sr\
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_rdata_i[31]_i_1_n_0\,
Q => \^s_axi_rdata\(2),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => p_0_out(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
reg2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
D(2 downto 0) => D(2 downto 0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ => bus2ip_rnw,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => \Not_Dual.gpio_Data_Out_reg[0]\,
\Not_Dual.gpio_OE_reg[0]\ => \Not_Dual.gpio_OE_reg[0]\,
Q(1 downto 0) => Q(1 downto 0),
SR => bus2ip_reset,
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[0]\(2 downto 0) => \ip2bus_data_i_D1_reg[0]\(2 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
reg1(1 downto 0) => reg1(1 downto 0),
reg2(1 downto 0) => reg2(1 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(2 downto 0) => s_axi_rdata(2 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 2;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "LOGICORE";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_10 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 5 to 6 );
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_core_1_n_11 : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal reg1 : STD_LOGIC_VECTOR ( 30 to 31 );
signal reg2 : STD_LOGIC_VECTOR ( 30 to 31 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 30 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
attribute max_fanout : string;
attribute max_fanout of s_axi_aclk : signal is "10000";
attribute sigis of s_axi_aclk : signal is "Clk";
attribute max_fanout of s_axi_aresetn : signal is "10000";
attribute sigis of s_axi_aresetn : signal is "Rst";
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(30);
s_axi_rdata(30) <= \^s_axi_rdata\(30);
s_axi_rdata(29) <= \^s_axi_rdata\(30);
s_axi_rdata(28) <= \^s_axi_rdata\(30);
s_axi_rdata(27) <= \^s_axi_rdata\(30);
s_axi_rdata(26) <= \^s_axi_rdata\(30);
s_axi_rdata(25) <= \^s_axi_rdata\(30);
s_axi_rdata(24) <= \^s_axi_rdata\(30);
s_axi_rdata(23) <= \^s_axi_rdata\(30);
s_axi_rdata(22) <= \^s_axi_rdata\(30);
s_axi_rdata(21) <= \^s_axi_rdata\(30);
s_axi_rdata(20) <= \^s_axi_rdata\(30);
s_axi_rdata(19) <= \^s_axi_rdata\(30);
s_axi_rdata(18) <= \^s_axi_rdata\(30);
s_axi_rdata(17) <= \^s_axi_rdata\(30);
s_axi_rdata(16) <= \^s_axi_rdata\(30);
s_axi_rdata(15) <= \^s_axi_rdata\(30);
s_axi_rdata(14) <= \^s_axi_rdata\(30);
s_axi_rdata(13) <= \^s_axi_rdata\(30);
s_axi_rdata(12) <= \^s_axi_rdata\(30);
s_axi_rdata(11) <= \^s_axi_rdata\(30);
s_axi_rdata(10) <= \^s_axi_rdata\(30);
s_axi_rdata(9) <= \^s_axi_rdata\(30);
s_axi_rdata(8) <= \^s_axi_rdata\(30);
s_axi_rdata(7) <= \^s_axi_rdata\(30);
s_axi_rdata(6) <= \^s_axi_rdata\(30);
s_axi_rdata(5) <= \^s_axi_rdata\(30);
s_axi_rdata(4) <= \^s_axi_rdata\(30);
s_axi_rdata(3) <= \^s_axi_rdata\(30);
s_axi_rdata(2) <= \^s_axi_rdata\(30);
s_axi_rdata(1 downto 0) <= \^s_axi_rdata\(1 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
D(2) => ip2bus_data(0),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ => AXI_LITE_IPIF_I_n_11,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ => AXI_LITE_IPIF_I_n_12,
\Not_Dual.gpio_Data_Out_reg[0]\ => AXI_LITE_IPIF_I_n_7,
\Not_Dual.gpio_OE_reg[0]\ => AXI_LITE_IPIF_I_n_10,
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[0]\(2) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg2(1) => reg2(30),
reg2(0) => reg2(31),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(2) => \^s_axi_rdata\(30),
s_axi_rdata(1 downto 0) => \^s_axi_rdata\(1 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
gpio_core_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
port map (
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_12,
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_11,
gpio_io_i(1 downto 0) => gpio_io_i(1 downto 0),
gpio_io_o(1 downto 0) => gpio_io_o(1 downto 0),
\gpio_io_t[0]\ => gpio_io_t(0),
\gpio_io_t[1]\ => gpio_io_t(1),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_11,
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg2(1) => reg2(30),
reg2(0) => reg2(31),
rst_reg => AXI_LITE_IPIF_I_n_7,
rst_reg_0 => AXI_LITE_IPIF_I_n_10,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(3 downto 2) => s_axi_wdata(31 downto 30),
s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0)
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_11,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_axi_gpio_0_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_gpio,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 2;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
attribute x_interface_info : string;
attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute x_interface_info of gpio_io_i : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
attribute x_interface_parameter of gpio_io_i : signal is "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
attribute x_interface_info of gpio_io_o : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
attribute x_interface_info of gpio_io_t : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(1 downto 0) => gpio_io_i(1 downto 0),
gpio_io_o(1 downto 0) => gpio_io_o(1 downto 0),
gpio_io_t(1 downto 0) => gpio_io_t(1 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | d95b0d426d9867c92ef8658f2b6f6376 | 0.590261 | 2.62905 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/sim/phy.vhd | 1 | 24,601 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
----------------------------------------------------------------------------
-- Entity: phy
-- File: phy.vhd
-- Description: Simulation model of an Ethernet PHY
-- Author: Marko Isomaki
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
entity phy is
generic(
address : integer range 0 to 31 := 0;
extended_regs : integer range 0 to 1 := 1;
aneg : integer range 0 to 1 := 1;
base100_t4 : integer range 0 to 1 := 0;
base100_x_fd : integer range 0 to 1 := 1;
base100_x_hd : integer range 0 to 1 := 1;
fd_10 : integer range 0 to 1 := 1;
hd_10 : integer range 0 to 1 := 1;
base100_t2_fd : integer range 0 to 1 := 1;
base100_t2_hd : integer range 0 to 1 := 1;
base1000_x_fd : integer range 0 to 1 := 0;
base1000_x_hd : integer range 0 to 1 := 0;
base1000_t_fd : integer range 0 to 1 := 1;
base1000_t_hd : integer range 0 to 1 := 1;
rmii : integer range 0 to 1 := 0;
rgmii : integer range 0 to 1 := 0
);
port(
rstn : in std_logic;
mdio : inout std_logic;
tx_clk : out std_logic;
rx_clk : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
mdc : in std_logic;
gtx_clk : in std_logic
);
end;
architecture behavioral of phy is
type mdio_state_type is (idle, start_of_frame, start_of_frame2, op, phyad, regad,
ta, rdata, wdata);
type ctrl_reg_type is record
reset : std_ulogic;
loopback : std_ulogic;
speedsel : std_logic_vector(1 downto 0);
anegen : std_ulogic;
powerdown : std_ulogic;
isolate : std_ulogic;
restartaneg : std_ulogic;
duplexmode : std_ulogic;
coltest : std_ulogic;
end record;
type status_reg_type is record
base100_t4 : std_ulogic;
base100_x_fd : std_ulogic;
base100_x_hd : std_ulogic;
fd_10 : std_ulogic;
hd_10 : std_ulogic;
base100_t2_fd : std_ulogic;
base100_t2_hd : std_ulogic;
extstat : std_ulogic;
mfpreamblesup : std_ulogic;
anegcmpt : std_ulogic;
remfault : std_ulogic;
anegability : std_ulogic;
linkstat : std_ulogic;
jabdetect : std_ulogic;
extcap : std_ulogic;
end record;
type aneg_ab_type is record
next_page : std_ulogic;
remote_fault : std_ulogic;
tech_ability : std_logic_vector(7 downto 0);
selector : std_logic_vector(4 downto 0);
end record;
type aneg_exp_type is record
par_detct_flt : std_ulogic;
lp_np_able : std_ulogic;
np_able : std_ulogic;
page_rx : std_ulogic;
lp_aneg_able : std_ulogic;
end record;
type aneg_nextpage_type is record
next_page : std_ulogic;
message_page : std_ulogic;
ack2 : std_ulogic;
toggle : std_ulogic;
message : std_logic_vector(10 downto 0);
end record;
type mst_slv_ctrl_type is record
tmode : std_logic_vector(2 downto 0);
manualcfgen : std_ulogic;
cfgval : std_ulogic;
porttype : std_ulogic;
base1000_t_fd : std_ulogic;
base1000_t_hd : std_ulogic;
end record;
type mst_slv_status_type is record
cfgfault : std_ulogic;
cfgres : std_ulogic;
locrxstate : std_ulogic;
remrxstate : std_ulogic;
lpbase1000_t_fd : std_ulogic;
lpbase1000_t_hd : std_ulogic;
idlerrcnt : std_logic_vector(7 downto 0);
end record;
type extended_status_reg_type is record
base1000_x_fd : std_ulogic;
base1000_x_hd : std_ulogic;
base1000_t_fd : std_ulogic;
base1000_t_hd : std_ulogic;
end record;
type reg_type is record
state : mdio_state_type;
cnt : integer;
op : std_logic_vector(1 downto 0);
phyad : std_logic_vector(4 downto 0);
regad : std_logic_vector(4 downto 0);
wr : std_ulogic;
regtmp : std_logic_vector(15 downto 0);
-- MII management registers
ctrl : ctrl_reg_type;
status : status_reg_type;
anegadv : aneg_ab_type;
aneglp : aneg_ab_type;
anegexp : aneg_exp_type;
anegnptx : aneg_nextpage_type;
anegnplp : aneg_nextpage_type;
mstslvctrl : mst_slv_ctrl_type;
mstslvstat : mst_slv_status_type;
extstatus : extended_status_reg_type;
rstcnt : integer;
anegcnt : integer;
end record;
signal r, rin : reg_type;
signal int_clk : std_ulogic := '0';
signal clkslow : std_ulogic := '0';
signal rcnt : integer;
signal anegact : std_ulogic;
begin
--mdio signal pull-up
int_clk <= not int_clk after 10 ns when rmii = 1 else
not int_clk after 4 ns when r.ctrl.speedsel = "01" else
not int_clk after 20 ns when r.ctrl.speedsel = "10" else
not int_clk after 200 ns when r.ctrl.speedsel = "00";
clkslow <= not clkslow after 20 ns when r.ctrl.speedsel = "10" else
not clkslow after 200 ns;
-- rstdelay : process
-- begin
-- loop
-- rstd <= '0';
-- while r.ctrl.reset /= '1' loop
-- wait on r.ctrl.reset;
-- end loop;
-- rstd <= '1';
-- while rstn = '0' loop
-- wait on rstn;
-- end loop;
-- wait on rstn for 3 us;
-- rstd <= '0';
-- wait on rstn until r.ctrl.reset = '0' for 5 us;
-- end loop;
-- end process;
anegproc : process is
begin
loop
anegact <= '0';
while rstn /= '1' loop
wait on rstn;
end loop;
while rstn = '1' loop
if r.ctrl.anegen = '0' then
anegact <= '0';
wait on rstn, r.ctrl.anegen, r.ctrl.restartaneg;
else
if r.ctrl.restartaneg = '1' then
anegact <= '1';
wait on rstn, r.ctrl.restartaneg, r.ctrl.anegen for 2 us;
anegact <= '0';
wait on rstn, r.ctrl.anegen until r.ctrl.restartaneg = '0';
if (rstn and r.ctrl.anegen) = '1' then
wait on rstn, r.ctrl.anegen, r.ctrl.restartaneg;
end if;
else
anegact <= '0';
wait on rstn, r.ctrl.restartaneg, r.ctrl.anegen;
end if;
end if;
end loop;
end loop;
end process;
mdiocomb : process(rstn, r, anegact, mdio) is
variable v : reg_type;
begin
v := r;
if anegact = '0' then
v.ctrl.restartaneg := '0';
end if;
case r.state is
when idle =>
mdio <= 'Z';
if to_X01(mdio) = '1' then
v.cnt := v.cnt + 1;
if v.cnt = 31 then
v.state := start_of_frame; v.cnt := 0;
end if;
else
v.cnt := 0;
end if;
when start_of_frame =>
if to_X01(mdio) = '0' then
v.state := start_of_frame2;
elsif to_X01(mdio) /= '1' then
v.state := idle;
end if;
when start_of_frame2 =>
if to_X01(mdio) = '1' then
v.state := op;
else
v.state := idle;
end if;
when op =>
v.cnt := v.cnt + 1;
v.op := r.op(0) & to_X01(mdio);
if r.cnt = 1 then
if (v.op = "01") or (v.op = "10") then
v.state := phyad; v.cnt := 0;
else
v.state := idle; v.cnt := 0;
end if;
end if;
when phyad =>
v.phyad := r.phyad(3 downto 0) & to_X01(mdio);
v.cnt := v.cnt + 1;
if r.cnt = 4 then
v.state := regad; v.cnt := 0;
end if;
when regad =>
v.regad := r.regad(3 downto 0) & to_X01(mdio);
v.cnt := v.cnt + 1;
if r.cnt = 4 then
v.cnt := 0;
if conv_integer(r.phyad) = address then
v.state := ta;
else
v.state := idle;
end if;
end if;
when ta =>
v.cnt := r.cnt + 1;
if r.cnt = 0 then
if (r.op = "01") and to_X01(mdio) /= '1' then
v.cnt := 0; v.state := idle;
end if;
else
if r.op = "10" then
mdio <= '0'; v.cnt := 0; v.state := rdata;
case r.regad is
when "00000" => --ctrl (basic)
v.regtmp := r.ctrl.reset & r.ctrl.loopback &
r.ctrl.speedsel(1) & r.ctrl.anegen & r.ctrl.powerdown &
r.ctrl.isolate & r.ctrl.restartaneg & r.ctrl.duplexmode &
r.ctrl.coltest & r.ctrl.speedsel(0) & "000000";
when "00001" => --statuc (basic)
v.regtmp := r.status.base100_t4 & r.status.base100_x_fd &
r.status.base100_x_hd & r.status.fd_10 & r.status.hd_10 &
r.status.base100_t2_fd & r.status.base100_t2_hd &
r.status.extstat & '0' & r.status.mfpreamblesup &
r.status.anegcmpt & r.status.remfault & r.status.anegability &
r.status.linkstat & r.status.jabdetect & r.status.extcap;
when "00010" => --PHY ID (extended)
if extended_regs = 1 then
v.regtmp := X"BBCD";
else
v.cnt := 0; v.state := idle;
end if;
when "00011" => --PHY ID (extended)
if extended_regs = 1 then
v.regtmp := X"9C83";
else
v.cnt := 0; v.state := idle;
end if;
when "00100" => --Auto-neg adv. (extended)
if extended_regs = 1 then
v.regtmp := r.anegadv.next_page & '0' & r.anegadv.remote_fault &
r.anegadv.tech_ability & r.anegadv.selector;
else
v.cnt := 0; v.state := idle;
end if;
when "00101" => --Auto-neg link partner ability (extended)
if extended_regs = 1 then
v.regtmp := r.aneglp.next_page & '0' & r.aneglp.remote_fault &
r.aneglp.tech_ability & r.aneglp.selector;
else
v.cnt := 0; v.state := idle;
end if;
when "00110" => --Auto-neg expansion (extended)
if extended_regs = 1 then
v.regtmp := "00000000000" & r.anegexp.par_detct_flt &
r.anegexp.lp_np_able & r.anegexp.np_able & r.anegexp.page_rx &
r.anegexp.lp_aneg_able;
else
v.cnt := 0; v.state := idle;
end if;
when "00111" => --Auto-neg next page (extended)
if extended_regs = 1 then
v.regtmp := r.anegnptx.next_page & '0' & r.anegnptx.message_page &
r.anegnptx.ack2 & r.anegnptx.toggle & r.anegnptx.message;
else
v.cnt := 0; v.state := idle;
end if;
when "01000" => --Auto-neg link partner received next page (extended)
if extended_regs = 1 then
v.regtmp := r.anegnplp.next_page & '0' & r.anegnplp.message_page &
r.anegnplp.ack2 & r.anegnplp.toggle & r.anegnplp.message;
else
v.cnt := 0; v.state := idle;
end if;
when "01001" => --Master-slave control (extended)
if extended_regs = 1 then
v.regtmp := r.mstslvctrl.tmode & r.mstslvctrl.manualcfgen &
r.mstslvctrl.cfgval & r.mstslvctrl.porttype &
r.mstslvctrl.base1000_t_fd & r.mstslvctrl.base1000_t_hd &
"00000000";
else
v.cnt := 0; v.state := idle;
end if;
when "01010" => --Master-slave status (extended)
if extended_regs = 1 then
v.regtmp := r.mstslvstat.cfgfault & r.mstslvstat.cfgres &
r.mstslvstat.locrxstate & r.mstslvstat.remrxstate &
r.mstslvstat.lpbase1000_t_fd & r.mstslvstat.lpbase1000_t_hd &
"00" & r.mstslvstat.idlerrcnt;
else
v.cnt := 0; v.state := idle;
end if;
when "01111" =>
if (base1000_x_fd = 1) or (base1000_x_hd = 1) or
(base1000_t_fd = 1) or (base1000_t_hd = 1) then
v.regtmp := r.extstatus.base1000_x_fd &
r.extstatus.base1000_x_hd &
r.extstatus.base1000_t_fd &
r.extstatus.base1000_t_hd & X"000";
else
v.regtmp := (others => '0');
end if;
when others =>
--PHY shall not drive MDIO when unimplemented registers
--are accessed
v.cnt := 0; v.state := idle;
v.regtmp := (others => '0');
end case;
if r.ctrl.reset = '1' then
if r.regad = "00000" then
v.regtmp := X"8000";
else
v.regtmp := X"0000";
end if;
end if;
else
if to_X01(mdio) /= '0'then
v.cnt := 0; v.state := idle;
else
v.cnt := 0; v.state := wdata;
end if;
end if;
end if;
when rdata =>
v.cnt := r.cnt + 1;
mdio <= r.regtmp(15-r.cnt);
if r.cnt = 15 then
v.state := idle; v.cnt := 0;
end if;
when wdata =>
v.cnt := r.cnt + 1;
v.regtmp := r.regtmp(14 downto 0) & to_X01(mdio);
if r.cnt = 15 then
v.state := idle; v.cnt := 0;
if r.ctrl.reset = '0' then
case r.regad is
when "00000" =>
v.ctrl.reset := v.regtmp(15);
v.ctrl.loopback := v.regtmp(14);
v.ctrl.speedsel(1) := v.regtmp(13);
v.ctrl.anegen := v.regtmp(12);
v.ctrl.powerdown := v.regtmp(11);
v.ctrl.isolate := v.regtmp(10);
v.ctrl.restartaneg := v.regtmp(9);
v.ctrl.duplexmode := v.regtmp(8);
v.ctrl.coltest := v.regtmp(7);
v.ctrl.speedsel(0) := v.regtmp(6);
when "00100" =>
if extended_regs = 1 then
v.anegadv.remote_fault := r.regtmp(13);
v.anegadv.tech_ability := r.regtmp(12 downto 5);
v.anegadv.selector := r.regtmp(4 downto 0);
end if;
when "00111" =>
if extended_regs = 1 then
v.anegnptx.next_page := r.regtmp(15);
v.anegnptx.message_page := r.regtmp(13);
v.anegnptx.ack2 := r.regtmp(12);
v.anegnptx.message := r.regtmp(10 downto 0);
end if;
when "01001" =>
if extended_regs = 1 then
v.mstslvctrl.tmode := r.regtmp(15 downto 13);
v.mstslvctrl.manualcfgen := r.regtmp(12);
v.mstslvctrl.cfgval := r.regtmp(11);
v.mstslvctrl.porttype := r.regtmp(10);
v.mstslvctrl.base1000_t_fd := r.regtmp(9);
v.mstslvctrl.base1000_t_hd := r.regtmp(8);
end if;
when others => --no writable bits for other regs
null;
end case;
end if;
end if;
when others =>
null;
end case;
if r.rstcnt > 19 then
v.ctrl.reset := '0'; v.rstcnt := 0;
else
v.rstcnt := r.rstcnt + 1;
end if;
if (v.ctrl.reset and not r.ctrl.reset) = '1' then
v.rstcnt := 0;
end if;
if r.ctrl.anegen = '1' then
if r.anegcnt < 10 then
v.anegcnt := r.anegcnt + 1;
else
v.status.anegcmpt := '1';
if (base1000_x_fd = 1) or (base1000_x_hd = 1) or
(r.mstslvctrl.base1000_t_fd = '1') or
(r.mstslvctrl.base1000_t_hd = '1') then
v.ctrl.speedsel(1 downto 0) := "01";
elsif (r.anegadv.tech_ability(4) = '1') or
(r.anegadv.tech_ability(3) = '1') or
(r.anegadv.tech_ability(2) = '1') or
(base100_t2_fd = 1) or (base100_t2_hd = 1) then
v.ctrl.speedsel(1 downto 0) := "10";
else
v.ctrl.speedsel(1 downto 0) := "00";
end if;
if ((base1000_x_fd = 1) or (r.mstslvctrl.base1000_t_fd = '1')) or
(((base100_t2_fd = 1) or (r.anegadv.tech_ability(3) = '1')) and
(r.mstslvctrl.base1000_t_hd = '0') and (base1000_x_hd = 0)) or
((r.anegadv.tech_ability(1) = '1') and (base100_t2_hd = 0) and
(r.anegadv.tech_ability(4) = '0') and
(r.anegadv.tech_ability(2) = '0')) then
v.ctrl.duplexmode := '1';
else
v.ctrl.duplexmode := '0';
end if;
end if;
end if;
if r.ctrl.restartaneg = '1' then
v.anegcnt := 0;
v.status.anegcmpt := '0';
v.ctrl.restartaneg := '0';
end if;
rin <= v;
end process;
reg : process(rstn, mdc) is
begin
if rising_edge(mdc) then
r <= rin;
end if;
-- -- RESET DELAY
-- if rstd = '1' then
-- r.ctrl.reset <= '1';
-- else
-- r.ctrl.reset <= '0';
-- end if;
-- RESET
if (r.ctrl.reset or not rstn) = '1' then
r.ctrl.loopback <= '1'; r.anegcnt <= 0;
if (base1000_x_hd = 1) or (base1000_x_fd = 1) or (base1000_t_hd = 1) or
(base1000_t_fd = 1) then
r.ctrl.speedsel <= "01";
elsif (base100_x_hd = 1) or (base100_t2_hd = 1) or (base100_x_fd = 1) or
(base100_t2_fd = 1) or (base100_t4 = 1) then
r.ctrl.speedsel <= "10";
else
r.ctrl.speedsel <= "00";
end if;
r.ctrl.anegen <= conv_std_logic(aneg = 1);
r.ctrl.powerdown <= '0';
r.ctrl.isolate <= '0';
r.ctrl.restartaneg <= '0';
if (base100_x_hd = 0) and (hd_10 = 0) and (base100_t2_hd = 0) and
(base1000_x_hd = 0) and (base1000_t_hd = 0) then
r.ctrl.duplexmode <= '1';
else
r.ctrl.duplexmode <= '0';
end if;
r.ctrl.coltest <= '0';
r.status.base100_t4 <= conv_std_logic(base100_t4 = 1);
r.status.base100_x_fd <= conv_std_logic(base100_x_fd = 1);
r.status.base100_x_hd <= conv_std_logic(base100_x_hd = 1);
r.status.fd_10 <= conv_std_logic(fd_10 = 1);
r.status.hd_10 <= conv_std_logic(hd_10 = 1);
r.status.base100_t2_fd <= conv_std_logic(base100_t2_fd = 1);
r.status.base100_t2_hd <= conv_std_logic(base100_t2_hd = 1);
r.status.extstat <= conv_std_logic((base1000_x_fd = 1) or
(base1000_x_hd = 1) or
(base1000_t_fd = 1) or
(base1000_t_hd = 1));
r.status.mfpreamblesup <= '0';
r.status.anegcmpt <= '0';
r.status.remfault <= '0';
r.status.anegability <= conv_std_logic(aneg = 1);
r.status.linkstat <= '0';
r.status.jabdetect <= '0';
r.status.extcap <= conv_std_logic(extended_regs = 1);
r.anegadv.next_page <= '0';
r.anegadv.remote_fault <= '0';
r.anegadv.tech_ability <= "000" & conv_std_logic(base100_t4 = 1) &
conv_std_logic(base100_x_fd = 1) & conv_std_logic(base100_x_hd = 1) &
conv_std_logic(fd_10 = 1) & conv_std_logic(hd_10 = 1);
r.anegadv.selector <= "00001";
r.aneglp.next_page <= '0';
r.aneglp.remote_fault <= '0';
r.aneglp.tech_ability <= "000" & conv_std_logic(base100_t4 = 1) &
conv_std_logic(base100_x_fd = 1) & conv_std_logic(base100_x_hd = 1) &
conv_std_logic(fd_10 = 1) & conv_std_logic(hd_10 = 1);
r.aneglp.selector <= "00001";
r.anegexp.par_detct_flt <= '0';
r.anegexp.lp_np_able <= '0';
r.anegexp.np_able <= '0';
r.anegexp.page_rx <= '0';
r.anegexp.lp_aneg_able <= '0';
r.anegnptx.next_page <= '0';
r.anegnptx.message_page <= '1';
r.anegnptx.ack2 <= '0';
r.anegnptx.toggle <= '0';
r.anegnptx.message <= "00000000001";
r.anegnplp.next_page <= '0';
r.anegnplp.message_page <= '1';
r.anegnplp.ack2 <= '0';
r.anegnplp.toggle <= '0';
r.anegnplp.message <= "00000000001";
r.mstslvctrl.tmode <= (others => '0');
r.mstslvctrl.manualcfgen <= '0';
r.mstslvctrl.cfgval <= '0';
r.mstslvctrl.porttype <= '0';
r.mstslvctrl.base1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvctrl.base1000_t_hd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.cfgfault <= '0';
r.mstslvstat.cfgres <= '1';
r.mstslvstat.locrxstate <= '1';
r.mstslvstat.remrxstate <= '1';
r.mstslvstat.lpbase1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.lpbase1000_t_hd <= conv_std_logic(base1000_t_fd = 1);
r.mstslvstat.idlerrcnt <= (others => '0');
r.extstatus.base1000_x_fd <= conv_std_logic(base1000_x_fd = 1);
r.extstatus.base1000_x_hd <= conv_std_logic(base1000_x_hd = 1);
r.extstatus.base1000_t_fd <= conv_std_logic(base1000_t_fd = 1);
r.extstatus.base1000_t_hd <= conv_std_logic(base1000_t_hd = 1);
end if;
if rstn = '0' then
r.cnt <= 0; r.state <= idle; r.rstcnt <= 0;
r.ctrl.reset <= '1';
end if;
end process;
loopback_sel : process(r.ctrl.loopback, int_clk, gtx_clk, r.ctrl.speedsel, txd, tx_en) is
begin
if r.ctrl.loopback = '1' then
if rmii = 0 then
rx_col <= '0'; rx_crs <= tx_en; rx_dv <= tx_en; rx_er <= tx_er;
rxd <= txd;
if r.ctrl.speedsel /= "01" then
rx_clk <= int_clk; tx_clk <= int_clk;
else
rx_clk <= gtx_clk; tx_clk <= clkslow;
end if;
else
rx_dv <= '1'; rx_er <= '1'; --unused should not affect anything
rx_col <= '0'; rx_crs <= tx_en;
if tx_en = '0' then
rxd(1 downto 0) <= "00";
else
rxd(1 downto 0) <= txd(1 downto 0);
end if;
if rgmii = 1 then
if (gtx_clk = '1' and tx_en = '0') then
rxd(3 downto 0) <= r.ctrl.duplexmode & r.ctrl.speedsel & r.status.linkstat;
end if;
end if;
rx_clk <= '0'; tx_clk <= '0';
end if;
else
rx_col <= '0'; rx_crs <= '0'; rx_dv <= '0'; rx_er <= '0';
rxd <= (others => '0');
if rgmii = 1 then
if (gtx_clk = '1') then
rxd(3 downto 0) <= r.ctrl.duplexmode & r.ctrl.speedsel & r.status.linkstat;
end if;
end if;
if rmii = 0 then
if r.ctrl.speedsel /= "01" then
rx_clk <= int_clk; tx_clk <= int_clk after 3 ns;
else
rx_clk <= gtx_clk; tx_clk <= clkslow;
end if;
else
rx_clk <= int_clk; tx_clk <= int_clk after 3 ns;
end if;
end if;
end process;
end;
-- pragma translate_on
| gpl-2.0 | 62924c4e5e8d01fa59c2cff3dfda0535 | 0.492297 | 3.384838 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-7/src/Testbenches/max_finder_t.vhd | 1 | 973 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity max_finder_t is
end max_finder_t;
architecture Beh of max_finder_t is
component MaxFinder
port (
CLK, RST, Start: in std_logic;
Stop: out std_logic
);
end component;
signal clk: std_logic := '0';
signal rst: std_logic := '0';
signal start: std_logic := '0';
signal stop: std_logic := '0';
constant CLK_period: time := 10 ns;
begin
UMAXFINDER: MaxFinder port map (
CLK => clk,
RST => rst,
START => start,
STOP => stop
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
main: process
begin
rst <= '1';
wait for 1 * CLK_PERIOD;
rst <= '0';
start <= '1';
wait for 100 * CLK_PERIOD;
wait;
end process;
end Beh;
configuration config of max_finder_t is
for Beh
for UMAXFINDER : MaxFinder
use entity work.MaxFinder(Beh);
end for;
end for;
end config; | mit | 15f8584c74f48feb3242a9e3da744f8a | 0.634121 | 2.72549 | false | true | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/eth/core/eth_rstgen.vhd | 1 | 1,946 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: eth_rstgen
-- File: eth_rstgen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Reset generation with glitch filter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity eth_rstgen is
generic (acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end;
architecture rtl of eth_rstgen is
signal r : std_logic_vector(4 downto 0);
signal rst : std_ulogic;
begin
rst <= not rstin when acthigh = 1 else rstin;
rstoutraw <= rst;
reg1 : process (clk, rst) begin
if rising_edge(clk) then
r <= r(3 downto 0) & clklock;
rstout <= r(4) and r(3) and r(2);
end if;
if rst = '0' then r <= "00000"; rstout <= '0'; end if;
end process;
end;
| gpl-2.0 | 52d741876e62e299209716ef39eddcbb | 0.595581 | 4.037344 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ipshared/ee5e/hdl/xbip_pipe_v3_0_vh_rfs.vhd | 7 | 30,625 | `protect begin_protected
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`protect end_protected
| mit | df8de30d822b63054d02d1df4f927692 | 0.941616 | 1.846771 | false | false | false | false |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/bsp.vhd | 2 | 14,803 | -------------------------------------------------------------------------------
---
--- FPGA TX - FPGA Based Radio Transmitter
---
--- :Author: Jonathan P Dawson
--- :Date: 04/04/2014
--- :email: [email protected]
--- :license: MIT
--- :Copyright: Copyright (C) Jonathan P Dawson 2014
---
--------------------------------------------------------------------------------
---
--- +--------------+
--- | CLOCK TREE |
--- +--------------+
--- | >-- CLK1 (50MHz) ---> CLK
--- CLK_IN >--> |
--- | >-- CLK2 (100MHz)
--- | | +-------+
--- | +-- CLK3 (125MHz) ->+ ODDR2 +-->[GTXCLK]
--- | | | |
--- | +-- CLK3_N (125MHZ) ->+ |
--- | | +-------+
--- RST >-----> >-- CLK4 (200MHz)
--- | |
--- | |
--- | | CLK >--+--------+
--- | | | |
--- | | +--v-+ +--v-+
--- | | | | | |
--- | LOCKED >------> >---> >-------> INTERNAL_RESET
--- | | | | | |
--- +--------------+ +----+ +----+
---
--- +-------------+
--- | USER DESIGN |
--- +-------------+
--- | |
--- | >-------> RF OUT
--- | |
--- | | +--------------+
--- | | | UART |
--- | | +--------------+
--- | >-----> >-----> RS232-TX
--- | | | |
--- | | | <-------< RS232-RX
--- +-------------+ +--------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity bsp is
port(
clk_in : in std_logic;
rst : in std_logic;
rf_out : out std_logic;
leds : out std_logic_vector(7 downto 0);
gps_tx : in std_logic;
gps_rx : out std_logic;
pps : in std_logic;
tx_rx : out std_logic;
tx_pa : out std_logic;
--rs232 interface
rs232_rx : in std_logic;
rs232_tx : out std_logic
);
end entity bsp;
architecture rtl of bsp is
component transmitter is
port(
clk : in std_logic;
rst : in std_logic;
frequency : in std_logic_vector(31 downto 0);
frequency_stb : in std_logic;
frequency_ack : out std_logic;
control : in std_logic_vector(31 downto 0);
control_stb : in std_logic;
control_ack : out std_logic;
amplitude : in std_logic_vector(31 downto 0);
amplitude_stb : in std_logic;
amplitude_ack : out std_logic;
rf : out std_logic;
tx_rx : out std_logic;
tx_pa : out std_logic
);
end component transmitter;
component user_design is
port(
clk : in std_logic;
rst : in std_logic;
output_tx_freq : out std_logic_vector(31 downto 0);
output_tx_freq_stb : out std_logic;
output_tx_freq_ack : in std_logic;
output_tx_am : out std_logic_vector(31 downto 0);
output_tx_am_stb : out std_logic;
output_tx_am_ack : in std_logic;
output_tx_ctl : out std_logic_vector(31 downto 0);
output_tx_ctl_stb : out std_logic;
output_tx_ctl_ack : in std_logic;
output_leds : out std_logic_vector(31 downto 0);
output_leds_stb : out std_logic;
output_leds_ack : in std_logic;
--gps pps count
input_gps_count : in std_logic_vector(31 downto 0);
input_gps_count_stb : in std_logic;
input_gps_count_ack : out std_logic;
--gps rx stream
input_gps_rx : in std_logic_vector(31 downto 0);
input_gps_rx_stb : in std_logic;
input_gps_rx_ack : out std_logic;
--gps tx stream
output_gps_tx : out std_logic_vector(31 downto 0);
output_gps_tx_stb : out std_logic;
output_gps_tx_ack : in std_logic;
--rs232 rx stream
input_rs232_rx : in std_logic_vector(31 downto 0);
input_rs232_rx_stb : in std_logic;
input_rs232_rx_ack : out std_logic;
--rs232 tx stream
output_rs232_tx : out std_logic_vector(31 downto 0);
output_rs232_tx_stb : out std_logic;
output_rs232_tx_ack : in std_logic
);
end component;
component serial_input is
generic(
clock_frequency : integer;
baud_rate : integer
);
port(
clk : in std_logic;
rst : in std_logic;
rx : in std_logic;
out1 : out std_logic_vector(7 downto 0);
out1_stb : out std_logic;
out1_ack : in std_logic
);
end component serial_input;
component serial_output is
generic(
clock_frequency : integer;
baud_rate : integer
);
port(
clk : in std_logic;
rst : in std_logic;
tx : out std_logic;
in1 : in std_logic_vector(7 downto 0);
in1_stb : in std_logic;
in1_ack : out std_logic
);
end component serial_output;
component gps_pps
port(
clk : in std_logic;
pps : in std_logic;
pps_count : out std_logic_vector(31 downto 0);
pps_count_stb : out std_logic;
pps_count_ack : in std_logic);
end component gps_pps;
--clock tree signals
signal clk : std_logic;
signal clkin1 : std_logic;
-- output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clk2x : std_logic;
signal clkfx : std_logic;
signal clkfx180 : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
signal clk_out1 : std_logic;
signal clk_out2 : std_logic;
signal clk_out3 : std_logic;
signal clk_out3_n : std_logic;
signal clk_out4 : std_logic;
signal not_locked : std_logic;
signal rst_inv : std_logic;
signal internal_rst : std_logic;
--tx interface
signal output_tx_freq : std_logic_vector(31 downto 0);
signal output_tx_freq_stb : std_logic;
signal output_tx_freq_ack : std_logic;
signal output_tx_am : std_logic_vector(31 downto 0);
signal output_tx_am_stb : std_logic;
signal output_tx_am_ack : std_logic;
signal output_tx_ctl : std_logic_vector(31 downto 0);
signal output_tx_ctl_stb : std_logic;
signal output_tx_ctl_ack : std_logic;
signal input_gps_count : std_logic_vector(31 downto 0);
signal input_gps_count_stb : std_logic;
signal input_gps_count_ack : std_logic;
--rs232 rx stream
signal input_rs232_rx : std_logic_vector(31 downto 0);
signal input_rs232_rx_stb : std_logic;
signal input_rs232_rx_ack : std_logic;
--rs232 tx stream
signal output_rs232_tx : std_logic_vector(31 downto 0);
signal output_rs232_tx_stb : std_logic;
signal output_rs232_tx_ack : std_logic;
--gps rx stream
signal input_gps_rx : std_logic_vector(31 downto 0);
signal input_gps_rx_stb : std_logic;
signal input_gps_rx_ack : std_logic;
--gps tx stream
signal output_gps_tx : std_logic_vector(31 downto 0);
signal output_gps_tx_stb : std_logic;
signal output_gps_tx_ack : std_logic;
signal s_test_1 : std_logic := '0';
signal s_test_2 : std_logic := '0';
signal output_leds : std_logic_vector(31 downto 0);
signal output_leds_stb : std_logic;
signal output_leds_ack : std_logic;
begin
transmitter_inst_1 : transmitter port map(
clk => clk,
rst => internal_rst,
frequency => output_tx_freq,
frequency_stb => output_tx_freq_stb,
frequency_ack => output_tx_freq_ack,
control => output_tx_ctl,
control_stb => output_tx_ctl_stb,
control_ack => output_tx_ctl_ack,
amplitude => output_tx_am,
amplitude_stb => output_tx_am_stb,
amplitude_ack => output_tx_am_ack,
tx_rx => tx_rx,
tx_pa => tx_pa,
rf => rf_out
);
process
begin
wait until rising_edge(clk);
if output_tx_freq_stb = '1' then
s_test_1 <= not s_test_1;
end if;
if output_tx_am_stb = '1' then
s_test_2 <= not s_test_2;
end if;
end process;
user_design_inst_1 : user_design port map(
clk => clk,
rst => internal_rst,
--rs232 rx stream
input_rs232_rx => input_rs232_rx,
input_rs232_rx_stb => input_rs232_rx_stb,
input_rs232_rx_ack => input_rs232_rx_ack,
--rs232 tx stream
output_rs232_tx => output_rs232_tx,
output_rs232_tx_stb => output_rs232_tx_stb,
output_rs232_tx_ack => output_rs232_tx_ack,
--gps rx stream
input_gps_rx => input_gps_rx,
input_gps_rx_stb => input_gps_rx_stb,
input_gps_rx_ack => input_gps_rx_ack,
--gps tx stream
output_gps_tx => output_gps_tx,
output_gps_tx_stb => output_gps_tx_stb,
output_gps_tx_ack => output_gps_tx_ack,
input_gps_count => input_gps_count,
input_gps_count_stb => input_gps_count_stb,
input_gps_count_ack => input_gps_count_ack,
output_leds => output_leds,
output_leds_stb => output_leds_stb,
output_leds_ack => output_leds_ack,
--transmit interface
output_tx_freq => output_tx_freq,
output_tx_freq_stb => output_tx_freq_stb,
output_tx_freq_ack => output_tx_freq_ack,
output_tx_am => output_tx_am,
output_tx_am_stb => output_tx_am_stb,
output_tx_am_ack => output_tx_am_ack,
output_tx_ctl => output_tx_ctl,
output_tx_ctl_stb => output_tx_ctl_stb,
output_tx_ctl_ack => output_tx_ctl_ack
);
pps1 : gps_pps port map(
clk => clk,
pps => pps,
pps_count => input_gps_count,
pps_count_stb => input_gps_count_stb,
pps_count_ack => input_gps_count_ack
);
serial_output_inst_1 : serial_output generic map(
clock_frequency => 100000000,
baud_rate => 12000000
)port map(
clk => clk,
rst => internal_rst,
tx => rs232_tx,
in1 => output_rs232_tx(7 downto 0),
in1_stb => output_rs232_tx_stb,
in1_ack => output_rs232_tx_ack
);
serial_input_inst_1 : serial_input generic map(
clock_frequency => 100000000,
baud_rate => 12000000
) port map (
clk => clk,
rst => internal_rst,
rx => rs232_rx,
out1 => input_rs232_rx(7 downto 0),
out1_stb => input_rs232_rx_stb,
out1_ack => input_rs232_rx_ack
);
input_rs232_rx(15 downto 8) <= (others => '0');
serial_output_inst_2 : serial_output generic map(
clock_frequency => 100000000,
baud_rate => 9600
)port map(
clk => clk,
rst => internal_rst,
tx => gps_rx,
in1 => output_gps_tx(7 downto 0),
in1_stb => output_gps_tx_stb,
in1_ack => output_gps_tx_ack
);
serial_input_inst_2 : serial_input generic map(
clock_frequency => 100000000,
baud_rate => 9600
) port map (
clk => clk,
rst => internal_rst,
rx => gps_tx,
out1 => input_gps_rx(7 downto 0),
out1_stb => input_gps_rx_stb,
out1_ack => input_gps_rx_ack
);
input_gps_rx(15 downto 8) <= (others => '0');
process
begin
wait until rising_edge(clk);
if output_leds_stb = '1' then
leds <= output_leds(7 downto 0);
end if;
end process;
output_leds_ack <= '1';
-------------------------
-- output output
-- clock freq (mhz)
-------------------------
-- clk_out1 50.000
-- clk_out2 100.000
-- clk_out3 125.000
-- clk_out4 200.000
----------------------------------
-- input clock input freq (mhz)
----------------------------------
-- primary 100.000
-- input buffering
--------------------------------------
clkin1_buf : ibufg
port map
(o => clkin1,
i => clk_in);
-- clocking primitive
--------------------------------------
-- instantiation of the dcm primitive
-- * unused inputs are tied off
-- * unused outputs are labeled unused
dcm_sp_inst: dcm_sp
generic map
(clkdv_divide => 2.000,
clkfx_divide => 4,
clkfx_multiply => 5,
clkin_divide_by_2 => false,
clkin_period => 10.0,
clkout_phase_shift => "none",
clk_feedback => "1x",
deskew_adjust => "system_synchronous",
phase_shift => 0,
startup_wait => false)
port map
-- input clock
(clkin => clkin1,
clkfb => clkfb,
-- output clocks
clk0 => clk0,
clk90 => open,
clk180 => open,
clk270 => open,
clk2x => clk2x,
clk2x180 => open,
clkfx => clkfx,
clkfx180 => clkfx180,
clkdv => clkdv,
-- ports for dynamic phase shift
psclk => '0',
psen => '0',
psincdec => '0',
psdone => open,
-- other control and status signals
locked => locked_internal,
status => status_internal,
rst => rst_inv,
-- unused pin, tie low
dssen => '0');
process
begin
wait until rising_edge(clk);
not_locked <= not locked_internal;
internal_rst <= not_locked;
end process;
-- output buffering
-------------------------------------
clkfb <= clk_out2;
bufg_inst1 : bufg
port map
(o => clk_out1,
i => clkdv);
bufg_inst2 : bufg
port map
(o => clk_out2,
i => clk0);
bufg_inst3 : bufg
port map
(o => clk_out3,
i => clkfx);
bufg_inst4 : bufg
port map
(o => clk_out3_n,
i => clkfx180);
bufg_inst5 : bufg
port map
(o => clk_out4,
i => clk2x);
rst_inv <= not rst;
-- chips clk frequency selection
-------------------------------------
--clk <= clk_out1; --50 mhz
clk <= clk_out2; --100 mhz
--clk <= clk_out3; --125 mhz
--clk <= clk_out4; --200 mhz
end architecture rtl;
| mit | 722312aa04cbf14ed300b4db0922d241 | 0.485239 | 3.545629 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-5/src/FinSM4.vhd | 1 | 1,167 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity Task4 is
port (
CLK: in STD_LOGIC;
IP: in STD_LOGIC_VECTOR (3 downto 0);
RST: in STD_LOGIC;
OP: out STD_LOGIC_VECTOR (1 downto 0));
end Task4;
architecture Beh of Task4 is
type state_type is (
S0, S1, S2, S3, S4
);
signal state: state_type;
begin
state_machine: process (CLK)
begin
if CLK'event and CLK = '1' then
if RST='1' then
state <= S0;
else
case state is
when S0 =>
if IP="0011" then
state <= S1;
else
state <= S4;
end if;
when S2 =>
if IP="1100" then
state <= S1;
elsif IP="1111" then
state <= S4;
end if;
when S3 =>
if IP="0000" then
state <= S2;
end if;
when S4 =>
if IP="1101" then
state <= S3;
end if;
when others =>
state <=S0;
end case;
end if;
end if;
end process;
OP_assignment:
OP <= "00" when (state = S0) else
"01" when (state = S1) else
"10" when (state = S2) else
"00" when (state = S3) else
"11" when (state = S4) else
"00";
end Beh;
| mit | 714f1a7b384445ec8eb470c651bf28e2 | 0.551842 | 2.634312 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-ztex-ufm-111/testbench.vhd | 1 | 7,123 | -------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all;
library micron;
use micron.components.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
signal reset : std_ulogic := '1';
signal clk48 : std_ulogic := '0';
signal errorn : std_logic;
signal mcb3_dram_dq : std_logic_vector(15 downto 0);
signal mcb3_rzq : std_logic;
signal mcb3_dram_dqs : std_logic_vector(1 downto 0);
signal mcb3_dram_a : std_logic_vector(12 downto 0);
signal mcb3_dram_ba : std_logic_vector(1 downto 0);
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_dm : std_logic_vector(1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal dsubre : std_ulogic; -- Debug Unit break (connect to button)
signal dsuact : std_ulogic; -- Debug Unit break (connect to button)
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
signal rxd1 : std_ulogic;
signal txd1 : std_ulogic;
signal sd_dat : std_logic;
signal sd_cmd : std_logic;
signal sd_sck : std_logic;
signal sd_dat3 : std_logic;
signal csb : std_logic := '0'; -- dummy
begin
-- clock and reset
clk48 <= not clk48 after 10.417 ns;
reset <= '1', '0' after 300 ns;
dsubre <= '0';
sd_dat <= 'H';
sd_cmd <= 'H';
sd_sck <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => reset,
clk48 => clk48,
-- Processor error output
errorn => errorn,
-- DDR SDRAM
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_dram_udqs => mcb3_dram_dqs(1),
mcb3_dram_dqs => mcb3_dram_dqs(0),
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm(0),
mcb3_dram_udm => mcb3_dram_dm(1),
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
-- Debug support unit
dsubre => dsubre,
dsuact => dsuact,
-- AHB UART (debug link)
dsurx => dsurx,
dsutx => dsutx,
-- UART
rxd1 => rxd1,
txd1 => txd1,
-- SD card
sd_dat => sd_dat,
sd_cmd => sd_cmd,
sd_sck => sd_sck,
sd_dat3 => sd_dat3
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>4, lddelay => 15 us)
port map (ck => mcb3_dram_ck, cke => mcb3_dram_cke, csn => csb,
rasn => mcb3_dram_ras_n, casn => mcb3_dram_cas_n, wen => mcb3_dram_we_n,
dm => mcb3_dram_dm, ba => mcb3_dram_ba, a => mcb3_dram_a,
dq => mcb3_dram_dq, dqs => mcb3_dram_dqs);
end generate;
--spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
--end generate spimem0;
iuerr : process
begin
wait for 5 us;
assert (to_X01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 | 41979581363306a02b3317497528b947 | 0.551453 | 3.359906 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/111e5b5bdee7fef3/ip_design_axi_gpio_0_0_sim_netlist.vhdl | 1 | 66,862 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:28 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_axi_gpio_0_0_sim_netlist.vhdl
-- Design : ip_design_axi_gpio_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
rst_reg : in STD_LOGIC;
bus2ip_rnw_i_reg : in STD_LOGIC;
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
reg2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal Bus_RNW_reg : STD_LOGIC;
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \ip2bus_data_i_D1[30]_i_2_n_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[30]_i_2\ : label is "soft_lutpair0";
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => Q,
I2 => Bus_RNW_reg,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => Bus_RNW_reg,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(0),
I1 => \bus2ip_addr_i_reg[8]\(1),
O => ce_expnd_i_3
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_3,
Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(0),
I1 => \bus2ip_addr_i_reg[8]\(1),
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_2,
Q => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(0),
O => ce_expnd_i_1
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_1,
Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_arready\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(0),
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
R => cs_ce_clr
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => Q,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => gpio_xferAck_Reg,
I3 => GPIO_xferAck_i,
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(2),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAABAA"
)
port map (
I0 => rst_reg,
I1 => bus2ip_rnw_i_reg,
I2 => \bus2ip_addr_i_reg[8]\(0),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(2),
I5 => \bus2ip_addr_i_reg[8]\(1),
O => \Not_Dual.gpio_Data_Out_reg[0]\
);
\Not_Dual.gpio_OE[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAABAAAAA"
)
port map (
I0 => rst_reg,
I1 => bus2ip_rnw_i_reg,
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => \bus2ip_addr_i_reg[8]\(1),
O => \Not_Dual.gpio_OE_reg[0]\
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => Bus_RNW_reg,
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => D(2)
);
\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F0AC000000000"
)
port map (
I0 => reg2(1),
I1 => reg1(1),
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I5 => \ip2bus_data_i_D1[30]_i_2_n_0\,
O => D(1)
);
\ip2bus_data_i_D1[30]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Bus_RNW_reg,
I1 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => \ip2bus_data_i_D1[30]_i_2_n_0\
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F0AC000000000"
)
port map (
I0 => reg2(0),
I1 => reg1(0),
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I5 => \ip2bus_data_i_D1[30]_i_2_n_0\,
O => D(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
port (
reg1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
reg2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gpio_io_t[0]\ : out STD_LOGIC;
\gpio_io_t[1]\ : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
bus2ip_rnw_i_reg : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC;
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
rst_reg : in STD_LOGIC;
rst_reg_0 : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2_n_0\ : STD_LOGIC;
signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_Data_Out[0]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_Data_Out[1]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_OE[0]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_OE[1]_i_1_n_0\ : STD_LOGIC;
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 1 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 1 );
signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^gpio_io_t[0]\ : STD_LOGIC;
signal \^gpio_io_t[1]\ : STD_LOGIC;
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal \^reg2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair8";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_io_o(1 downto 0) <= \^gpio_io_o\(1 downto 0);
\gpio_io_t[0]\ <= \^gpio_io_t[0]\;
\gpio_io_t[1]\ <= \^gpio_io_t[1]\;
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
reg2(1 downto 0) <= \^reg2\(1 downto 0);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C2E22222C222222"
)
port map (
I0 => \^gpio_io_o\(1),
I1 => \^gpio_io_t[1]\,
I2 => Q(1),
I3 => Q(0),
I4 => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
I5 => gpio_Data_In(0),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1_n_0\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1_n_0\,
Q => reg1(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C2E22222C222222"
)
port map (
I0 => \^reg2\(1),
I1 => \^gpio_io_t[1]\,
I2 => Q(1),
I3 => Q(0),
I4 => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
I5 => gpio_Data_In(0),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1_n_0\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1_n_0\,
Q => \^reg2\(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C2E22222C222222"
)
port map (
I0 => \^gpio_io_o\(0),
I1 => \^gpio_io_t[0]\,
I2 => Q(1),
I3 => Q(0),
I4 => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
I5 => gpio_Data_In(1),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2_n_0\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2_n_0\,
Q => reg1(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C2E22222C222222"
)
port map (
I0 => \^reg2\(0),
I1 => \^gpio_io_t[0]\,
I2 => Q(1),
I3 => Q(0),
I4 => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
I5 => gpio_Data_In(1),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1_n_0\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1_n_0\,
Q => \^reg2\(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
gpio_io_i(1 downto 0) => gpio_io_i(1 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(1) => gpio_io_i_d2(0),
scndry_vect_out(0) => gpio_io_i_d2(1)
);
\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => gpio_Data_In(0),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => gpio_Data_In(1),
R => '0'
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FFFFFB080000"
)
port map (
I0 => s_axi_wdata(1),
I1 => bus2ip_cs,
I2 => Q(1),
I3 => s_axi_wdata(3),
I4 => rst_reg,
I5 => \^gpio_io_o\(1),
O => \Not_Dual.gpio_Data_Out[0]_i_1_n_0\
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FFFFFB080000"
)
port map (
I0 => s_axi_wdata(0),
I1 => bus2ip_cs,
I2 => Q(1),
I3 => s_axi_wdata(2),
I4 => rst_reg,
I5 => \^gpio_io_o\(0),
O => \Not_Dual.gpio_Data_Out[1]_i_1_n_0\
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_Data_Out[0]_i_1_n_0\,
Q => \^gpio_io_o\(1),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_Data_Out[1]_i_1_n_0\,
Q => \^gpio_io_o\(0),
R => bus2ip_reset
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FFFFFB080000"
)
port map (
I0 => s_axi_wdata(1),
I1 => bus2ip_cs,
I2 => Q(1),
I3 => s_axi_wdata(3),
I4 => rst_reg_0,
I5 => \^gpio_io_t[1]\,
O => \Not_Dual.gpio_OE[0]_i_1_n_0\
);
\Not_Dual.gpio_OE[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FFFFFB080000"
)
port map (
I0 => s_axi_wdata(0),
I1 => bus2ip_cs,
I2 => Q(1),
I3 => s_axi_wdata(2),
I4 => rst_reg_0,
I5 => \^gpio_io_t[0]\,
O => \Not_Dual.gpio_OE[1]_i_1_n_0\
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE[0]_i_1_n_0\,
Q => \^gpio_io_t[1]\,
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE[1]_i_1_n_0\,
Q => \^gpio_io_t[0]\,
S => bus2ip_reset
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => bus2ip_reset
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => bus2ip_reset
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
SR : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
reg2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.allout0_nd.read_reg_gen[0].reg1_reg[30]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 0 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst_i_1_n_0 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \s_axi_rdata_i[0]_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \bus2ip_addr_i[8]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair4";
begin
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ <= \^not_dual.allout0_nd.read_reg_gen[0].reg1_reg[30]\;
Q(1 downto 0) <= \^q\(1 downto 0);
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rdata(2 downto 0) <= \^s_axi_rdata\(2 downto 0);
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(2 downto 0) => D(2 downto 0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0\,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => \Not_Dual.gpio_Data_Out_reg[0]\,
\Not_Dual.gpio_OE_reg[0]\ => \Not_Dual.gpio_OE_reg[0]\,
Q => start2,
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(1 downto 0) => \^q\(1 downto 0),
bus2ip_rnw_i_reg => \^not_dual.allout0_nd.read_reg_gen[0].reg1_reg[30]\,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
reg1(1 downto 0) => reg1(1 downto 0),
reg2(1 downto 0) => reg2(1 downto 0),
rst_reg => \^sr\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wready => \^s_axi_wready\
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => \^q\(0),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => \^q\(1),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => s_axi_arvalid,
Q => \^not_dual.allout0_nd.read_reg_gen[0].reg1_reg[30]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => rst_i_1_n_0
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rst_i_1_n_0,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \ip2bus_data_i_D1_reg[0]\(0),
I1 => state(0),
I2 => state(1),
I3 => \^s_axi_rdata\(0),
O => \s_axi_rdata_i[0]_i_1_n_0\
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \ip2bus_data_i_D1_reg[0]\(1),
I1 => state(0),
I2 => state(1),
I3 => \^s_axi_rdata\(1),
O => \s_axi_rdata_i[1]_i_1_n_0\
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \ip2bus_data_i_D1_reg[0]\(2),
I1 => state(0),
I2 => state(1),
I3 => \^s_axi_rdata\(2),
O => \s_axi_rdata_i[31]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_rdata_i[0]_i_1_n_0\,
Q => \^s_axi_rdata\(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_rdata_i[1]_i_1_n_0\,
Q => \^s_axi_rdata\(1),
R => \^sr\
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_rdata_i[31]_i_1_n_0\,
Q => \^s_axi_rdata\(2),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => p_0_out(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
reg2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
D(2 downto 0) => D(2 downto 0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ => bus2ip_rnw,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => \Not_Dual.gpio_Data_Out_reg[0]\,
\Not_Dual.gpio_OE_reg[0]\ => \Not_Dual.gpio_OE_reg[0]\,
Q(1 downto 0) => Q(1 downto 0),
SR => bus2ip_reset,
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[0]\(2 downto 0) => \ip2bus_data_i_D1_reg[0]\(2 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
reg1(1 downto 0) => reg1(1 downto 0),
reg2(1 downto 0) => reg2(1 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(2 downto 0) => s_axi_rdata(2 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 2;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "LOGICORE";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_10 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 5 to 6 );
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_core_1_n_11 : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal reg1 : STD_LOGIC_VECTOR ( 30 to 31 );
signal reg2 : STD_LOGIC_VECTOR ( 30 to 31 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 30 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
attribute max_fanout : string;
attribute max_fanout of s_axi_aclk : signal is "10000";
attribute sigis of s_axi_aclk : signal is "Clk";
attribute max_fanout of s_axi_aresetn : signal is "10000";
attribute sigis of s_axi_aresetn : signal is "Rst";
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(30);
s_axi_rdata(30) <= \^s_axi_rdata\(30);
s_axi_rdata(29) <= \^s_axi_rdata\(30);
s_axi_rdata(28) <= \^s_axi_rdata\(30);
s_axi_rdata(27) <= \^s_axi_rdata\(30);
s_axi_rdata(26) <= \^s_axi_rdata\(30);
s_axi_rdata(25) <= \^s_axi_rdata\(30);
s_axi_rdata(24) <= \^s_axi_rdata\(30);
s_axi_rdata(23) <= \^s_axi_rdata\(30);
s_axi_rdata(22) <= \^s_axi_rdata\(30);
s_axi_rdata(21) <= \^s_axi_rdata\(30);
s_axi_rdata(20) <= \^s_axi_rdata\(30);
s_axi_rdata(19) <= \^s_axi_rdata\(30);
s_axi_rdata(18) <= \^s_axi_rdata\(30);
s_axi_rdata(17) <= \^s_axi_rdata\(30);
s_axi_rdata(16) <= \^s_axi_rdata\(30);
s_axi_rdata(15) <= \^s_axi_rdata\(30);
s_axi_rdata(14) <= \^s_axi_rdata\(30);
s_axi_rdata(13) <= \^s_axi_rdata\(30);
s_axi_rdata(12) <= \^s_axi_rdata\(30);
s_axi_rdata(11) <= \^s_axi_rdata\(30);
s_axi_rdata(10) <= \^s_axi_rdata\(30);
s_axi_rdata(9) <= \^s_axi_rdata\(30);
s_axi_rdata(8) <= \^s_axi_rdata\(30);
s_axi_rdata(7) <= \^s_axi_rdata\(30);
s_axi_rdata(6) <= \^s_axi_rdata\(30);
s_axi_rdata(5) <= \^s_axi_rdata\(30);
s_axi_rdata(4) <= \^s_axi_rdata\(30);
s_axi_rdata(3) <= \^s_axi_rdata\(30);
s_axi_rdata(2) <= \^s_axi_rdata\(30);
s_axi_rdata(1 downto 0) <= \^s_axi_rdata\(1 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
D(2) => ip2bus_data(0),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ => AXI_LITE_IPIF_I_n_11,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ => AXI_LITE_IPIF_I_n_12,
\Not_Dual.gpio_Data_Out_reg[0]\ => AXI_LITE_IPIF_I_n_7,
\Not_Dual.gpio_OE_reg[0]\ => AXI_LITE_IPIF_I_n_10,
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[0]\(2) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg2(1) => reg2(30),
reg2(0) => reg2(31),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(2) => \^s_axi_rdata\(30),
s_axi_rdata(1 downto 0) => \^s_axi_rdata\(1 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
gpio_core_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
port map (
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_12,
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_11,
gpio_io_i(1 downto 0) => gpio_io_i(1 downto 0),
gpio_io_o(1 downto 0) => gpio_io_o(1 downto 0),
\gpio_io_t[0]\ => gpio_io_t(0),
\gpio_io_t[1]\ => gpio_io_t(1),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_11,
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg2(1) => reg2(30),
reg2(0) => reg2(31),
rst_reg => AXI_LITE_IPIF_I_n_7,
rst_reg_0 => AXI_LITE_IPIF_I_n_10,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(3 downto 2) => s_axi_wdata(31 downto 30),
s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0)
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_11,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_axi_gpio_0_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_gpio,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 2;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
attribute x_interface_info : string;
attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute x_interface_info of gpio_io_i : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
attribute x_interface_parameter of gpio_io_i : signal is "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
attribute x_interface_info of gpio_io_o : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
attribute x_interface_info of gpio_io_t : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(1 downto 0) => gpio_io_i(1 downto 0),
gpio_io_o(1 downto 0) => gpio_io_o(1 downto 0),
gpio_io_t(1 downto 0) => gpio_io_t(1 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 8fd615d947a07cc95bb4d2200d5e9d77 | 0.590261 | 2.62905 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/spi/spi2ahb.vhd | 1 | 2,940 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb
-- File: spi2ahb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.conv_std_logic_vector;
library gaisler;
use gaisler.spi.all;
entity spi2ahb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb;
architecture rtl of spi2ahb is
signal spi2ahbi : spi2ahb_in_type;
begin
bridge : spi2ahbx
generic map (
hindex => hindex,
oepol => oepol,
filter => filter,
cpol => cpol,
cpha => cpha)
port map (
rstn => rstn,
clk => clk,
ahbi => ahbi,
ahbo => ahbo,
spii => spii,
spio => spio,
spi2ahbi => spi2ahbi,
spi2ahbo => open);
spi2ahbi.en <= '1';
spi2ahbi.haddr <= conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
spi2ahbi.hmask <= conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
end architecture rtl;
| gpl-2.0 | 881b5b742ef50cc984e96e87abbd38f2 | 0.567687 | 3.89404 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-gr-xc6s/testbench.vhd | 1 | 12,915 | ----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(31 downto 24);
signal pio : std_logic_vector(17 downto 0);
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal wdogn,wdogn_local : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal erx_dv, erx_dv_d, etx_en: std_logic:='0';
signal erxd, erxd_d, etxd: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdint : std_ulogic;
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic := '0';
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal clk2 : std_ulogic := '0';
signal clk125 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(9 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
signal erx_er : std_logic := '0';
signal erx_col : std_logic := '0';
signal erx_crs : std_logic := '1';
signal etx_er : std_logic := '0';
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 10 ns;
--erx_clk <= not erx_clk after 4 ns;
clk2 <= '0'; --not clk2 after 5 ns;
rst <= dsurst and wdogn_local;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
ps2clk <= "HH"; ps2data <= "HH";
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
wdogn <= 'H';
wdogn_local <= 'H';
switch(7) <= '1';
switch(8) <= '0';
emdio <= 'H';
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, clk2, clk125, wdogn, address(24 downto 0), data,
oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_we, ddr_ras, ddr_csb ,ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, txd2, rxd2, ctsn2, rtsn2, pio, genio,
switch, led, erx_clk, emdio, erxd(3 downto 0)'delayed(1 ns), erx_dv'delayed(1 ns), emdint,
etx_clk, etxd(3 downto 0), etx_en, emdc,
ps2clk, ps2data, iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spw_clk, spw_rxdp, spw_rxdn,
spw_rxsp, spw_rxsn, spw_txdp, spw_txdn, spw_txsp, spw_txsn,
spi_sel_n, spi_clk, spi_mosi
);
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
ddr2mem : if (CFG_MIG_DDR2 = 1) generate
u1: ddr2ram
generic map (width => 16, abits => 13, babits => 3,
colbits => 10, rowbits => 13, implbanks => 1,
fname => sdramfile, lddelay => (340 us),
speedbin => 1)
port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn);
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(
address => 1,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(rst, emdio, open, erx_clk, erxd_d, erx_dv_d,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, clk125);
end generate;
rcxclkp : process(erx_clk) is
begin
erxd <= erxd_d;
erx_dv <= erx_dv_d;
end process;
wdognp : process
begin
wdogn_local <= 'H';
if wdogn = '0' then
wdogn_local <= '0';
wait for 1 ms;
end if;
wait for 20 ns;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 201 us;
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
iuerr : process
begin
wait until dsurst = '1';
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
| gpl-2.0 | b720c4a64984580a4e31a9c8bc93afae | 0.568331 | 2.997215 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/toutpad.vhd | 1 | 6,917 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: toutpad
-- File: toutpad.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: tri-state output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity toutpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of toutpad is
signal oen : std_ulogic;
signal padx, gnd : std_ulogic;
begin
gnd <= '0';
oen <= not en when oepol /= padoen_polarity(tech) else en;
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when oen = '0'
-- pragma translate_off
else 'X' after 2 ns when is_x(en)
-- pragma translate_on
else 'Z'
-- pragma translate_off
after 2 ns
-- pragma translate_on
;
end generate;
xcv : if (is_unisim(tech) = 1) generate
u0 : unisim_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
axc : if (tech = axcel) or (tech = axdsp) generate
u0 : axcel_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
pa3 : if (tech = proasic) or (tech = apa3) generate
u0 : apa3_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
pa3e : if (tech = apa3e) generate
u0 : apa3e_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
pa3l : if (tech = apa3l) generate
u0 : apa3l_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
fus : if (tech = actfus) generate
u0 : fusion_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atc : if (tech = atc18s) generate
u0 : atc18_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
atcrh : if (tech = atc18rha) generate
u0 : atc18rha_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
um : if (tech = umc) generate
u0 : umc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
rhu : if (tech = rhumc) generate
u0 : rhumc_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
saed : if (tech = saed32) generate
u0 : saed32_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
dar : if (tech = dare) generate
u0 : dare_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
ihp : if (tech = ihp25) generate
u0 : ihp25_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
ihprh : if (tech = ihp25rh) generate
u0 : ihp25rh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
rh18t : if (tech = rhlib18t) generate
u0 : rh_lib18t_iopad generic map (strength) port map (padx, i, oen, open);
pad <= padx;
end generate;
ut025 : if (tech = ut25) generate
u0 : ut025crh_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
ut13 : if (tech = ut130) generate
u0 : ut130hbd_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
pere : if (tech = peregrine) generate
u0 : peregrine_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen);
end generate;
nex : if (tech = easic90) generate
u0 : nextreme_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen);
end generate;
n2x : if (tech = easic45) generate
u0 : n2x_toutpad generic map (level, slew, voltage, strength)
port map (pad, i, oen, cfgi(0), cfgi(1),
cfgi(19 downto 15), cfgi(14 downto 10), cfgi(9 downto 6), cfgi(5 downto 2));
end generate;
ut90nhbd : if (tech = ut90) generate
u0 : ut90nhbd_toutpad generic map (level, slew, voltage, strength)
port map(pad, i, oen, cfgi(0));
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000"
);
end;
architecture rtl of toutpadv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en, cfgi);
end generate;
end;
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
entity toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end;
architecture rtl of toutpadvv is
begin
v : for j in width-1 downto 0 generate
u0 : toutpad generic map (tech, level, slew, voltage, strength, oepol)
port map (pad(j), i(j), en(j), cfgi);
end generate;
end;
| gpl-2.0 | 80d967582d213f02863706a567da5d0c | 0.640596 | 3.477627 | false | false | false | false |
khaledhassan/vhdl-examples | clock_divider/clk_div_tb.vhd | 1 | 2,249 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Testbench for the parameterized clock divider
library ieee;
use ieee.std_logic_1164.all;
entity clk_div_tb is
end clk_div_tb;
architecture TB of clk_div_tb is
signal clk_in, clk_out, rst : std_logic;
constant clk_period : time := 20 ns; -- for a 50MHz clock
begin
-- Instantiate the Unit Under Test (UUT)
UUT : entity work.clk_div
generic map (
clk_in_freq => 50,
clk_out_freq => 25
)
port map (
rst => rst,
clk_in => clk_in,
clk_out => clk_out
);
-- Clock process
process
begin
clk_in <= '0';
wait for clk_period/2;
clk_in <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
process
begin
-- Hold reset state
rst <= '1';
wait for clk_period;
-- Release reset
rst <= '0';
-- Perform the simulation
wait for clk_period*20;
wait;
end process;
end TB; | mit | 7778da72fffda1b7f9de083ba5e5b748 | 0.649622 | 4.195896 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-terasic-de4/ddr2sim.vhd | 1 | 10,025 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
entity ddr2ctrl is
port (
pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
global_reset_n : in std_logic := '0'; -- global_reset.reset_n
soft_reset_n : in std_logic := '0'; -- soft_reset.reset_n
afi_clk : out std_logic; -- afi_clk.clk
afi_half_clk : out std_logic; -- afi_half_clk.clk
afi_reset_n : out std_logic; -- afi_reset.reset_n
afi_reset_export_n : out std_logic; -- afi_reset_export.reset_n
mem_a : out std_logic_vector(13 downto 0); -- memory.mem_a
mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke
mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n
mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n
mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n
mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n
mem_dq : inout std_logic_vector(63 downto 0) := (others => '0'); -- .mem_dq
mem_dqs : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs
mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => '0'); -- .mem_dqs_n
mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt
avl_ready : out std_logic; -- avl.waitrequest_n
avl_burstbegin : in std_logic := '0'; -- .beginbursttransfer
avl_addr : in std_logic_vector(24 downto 0) := (others => '0'); -- .address
avl_rdata_valid : out std_logic; -- .readdatavalid
avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
avl_wdata : in std_logic_vector(255 downto 0) := (others => '0'); -- .writedata
avl_be : in std_logic_vector(31 downto 0) := (others => '0'); -- .byteenable
avl_read_req : in std_logic := '0'; -- .read
avl_write_req : in std_logic := '0'; -- .write
avl_size : in std_logic_vector(3 downto 0) := (others => '0'); -- .burstcount
local_init_done : out std_logic; -- status.local_init_done
local_cal_success : out std_logic; -- .local_cal_success
local_cal_fail : out std_logic; -- .local_cal_fail
oct_rdn : in std_logic := '0'; -- oct.rdn
oct_rup : in std_logic := '0' -- .rup
);
end ddr2ctrl;
architecture sim of ddr2ctrl is
signal lafi_clk, lafi_rst_n: std_ulogic;
signal lafi_half_clk: std_ulogic;
begin
afi_clk <= lafi_clk;
afi_half_clk <= lafi_half_clk;
afi_reset_n <= lafi_rst_n;
mem_a <= (others => '0');
mem_ba <= (others => '0');
mem_ck <= (others => '0');
mem_ck_n <= (others => '1');
mem_cke <= (others => '0');
mem_cs_n <= (others => '1');
mem_dm <= (others => '0');
mem_ras_n <= (others => '1');
mem_cas_n <= (others => '1');
mem_we_n <= (others => '1');
mem_dq <= (others => 'Z');
mem_dqs <= (others => 'Z');
mem_dqs_n <= (others => 'Z');
mem_odt <= (others => '0');
avl_ready <= '1';
local_init_done <= '1';
local_cal_success <= '1';
local_cal_fail <= '0';
-- 200 MHz clock
clkproc: process
begin
lafi_clk <= '0';
lafi_half_clk <= '0';
loop
wait for 2.5 ns;
lafi_clk <= not lafi_clk;
if lafi_clk='0' then
lafi_half_clk <= not lafi_half_clk;
end if;
end loop;
end process;
rstproc: process
begin
lafi_rst_n <= '0';
wait for 10 ns;
loop
if global_reset_n='0' then
lafi_rst_n <= '0';
wait until global_reset_n/='0';
wait until rising_edge(lafi_clk);
end if;
lafi_rst_n <= '1';
wait until global_reset_n='0';
end loop;
end process;
avlproc: process
subtype BYTE is std_logic_vector(7 downto 0);
type MEM is array(0 to ((2**20)-1)) of BYTE;
variable MEMA: MEM;
procedure load_srec is
file TCF : text open read_mode is "ram.srec";
variable L1: line;
variable CH: character;
variable ai: integer;
variable rectype: std_logic_vector(3 downto 0);
variable recaddr: std_logic_vector(31 downto 0);
variable reclen: std_logic_vector(7 downto 0);
variable recdata: std_logic_vector(0 to 16*8-1);
variable len: integer;
begin
L1:= new string'(""); --'
while not endfile(TCF) loop
readline(TCF,L1);
if (L1'length /= 0) then --'
while (not (L1'length=0)) and (L1(L1'left) = ' ') loop
std.textio.read(L1,CH);
end loop;
if L1'length > 0 then --'
read(L1, ch);
if (ch = 'S') or (ch = 's') then
hread(L1, rectype);
hread(L1, reclen);
len := conv_integer(reclen)-1;
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(L1, recaddr(15 downto 0));
len := len-2;
when "0010" =>
hread(L1, recaddr(23 downto 0));
len := len-3;
when "0011" =>
hread(L1, recaddr);
len := len-4;
when others => next;
end case;
hread(L1, recdata(0 to 8*len-1));
recaddr(31 downto 20) := (others => '0');
ai := conv_integer(recaddr);
-- print("Setting " & tost(len) & "bytes at " & tost(recaddr));
for i in 0 to len-1 loop
MEMA(ai+i) := recdata((i*8) to (i*8+7));
end loop;
end if;
end if;
end if;
end loop;
end load_srec;
constant avldbits: integer := 256;
variable outqueue: std_logic_vector(0 to 4*avldbits-1) := (others => 'X');
variable outqueue_valid: std_logic_vector(0 to 3) := (others => '0');
variable ai,p: integer;
variable wbleft: integer := 0;
begin
load_srec;
loop
wait until rising_edge(lafi_clk);
avl_rdata_valid <= outqueue_valid(0);
avl_rdata <= outqueue(0 to avldbits-1);
outqueue(0 to 3*avldbits-1) := outqueue(avldbits to 4*avldbits-1);
outqueue(3*avldbits to 4*avldbits-1) := (others => 'X');
outqueue_valid := outqueue_valid(1 to 3) & '0';
if avl_burstbegin='1' then wbleft:=0; end if;
if lafi_rst_n='0' then
outqueue_valid := (others => '0');
elsif avl_read_req='1' then
ai := conv_integer(avl_addr(16 downto 0));
p := 0;
while outqueue_valid(p)='1' loop p:=p+1; end loop;
for x in 0 to conv_integer(avl_size)-1 loop
for y in 0 to avldbits/8-1 loop
outqueue((p+x)*avldbits+y*8 to (p+x)*avldbits+y*8+7) := MEMA((ai+x)*avldbits/8+y);
end loop;
outqueue_valid(p+x) := '1';
end loop;
elsif avl_write_req='1' then
if wbleft=0 then
wbleft := conv_integer(avl_size);
ai := conv_integer(avl_addr(16 downto 0));
end if;
for y in 0 to avldbits/8-1 loop
if avl_be(avldbits/8-1-y)='1' then
MEMA(ai*avldbits/8+y) := avl_wdata(avldbits-8*y-1 downto avldbits-8*y-8);
end if;
end loop;
wbleft := wbleft-1;
ai := ai+1;
end if;
end loop;
end process;
end;
| gpl-2.0 | bb0a968160dfe71986e5389235d7f6e9 | 0.460349 | 3.737882 | false | false | false | false |
eamadio/fpgaMSP430 | fmsp430/per/fmsp_timerA.vhd | 1 | 28,312 | ------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_timerA.vhd
--!
--! @brief fpgaMSP430 Timer A top-level
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use ieee.math_real.all;
use work.fmsp_misc_package.all;
use work.fmsp_per_package.all;
use work.fmsp_functions.all;
entity fmsp_timerA is
port (
mclk : in std_logic; --! Main system clock
mrst : in std_logic; --! Main system reset
--! INPUTs
aclk_en : in std_logic; --! ACLK enable (from CPU)
smclk_en : in std_logic; --! SMCLK enable (from CPU)
dbg_freeze : in std_logic; --! Freeze Timer A counter
inclk : in std_logic; --! INCLK external timer clock (SLOW)
irq_ta0_acc : in std_logic; --! Interrupt request TACCR0 accepted
per_addr : in std_logic_vector(13 downto 0); --! Peripheral address
per_din : in std_logic_vector(15 downto 0); --! Peripheral data input
per_en : in std_logic; --! Peripheral enable (high active)
per_we : in std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
ta_cci0a : in std_logic; --! Timer A capture 0 input A
ta_cci0b : in std_logic; --! Timer A capture 0 input B
ta_cci1a : in std_logic; --! Timer A capture 1 input A
ta_cci1b : in std_logic; --! Timer A capture 1 input B
ta_cci2a : in std_logic; --! Timer A capture 2 input A
ta_cci2b : in std_logic; --! Timer A capture 2 input B
taclk : in std_logic; --! TACLK external timer clock (SLOW)
--! OUTPUTs
irq_ta0 : out std_logic; --! Timer A interrupt: TACCR0
irq_ta1 : out std_logic; --! Timer A interrupt: TAIV, TACCR1, TACCR2
per_dout : out std_logic_vector(15 downto 0); --! Peripheral data output
ta_out0 : out std_logic; --! Timer A output 0
ta_out0_en : out std_logic; --! Timer A output 0 enable
ta_out1 : out std_logic; --! Timer A output 1
ta_out1_en : out std_logic; --! Timer A output 1 enable
ta_out2 : out std_logic; --! Timer A output 2
ta_out2_en : out std_logic --! Timer A output 2 enable
);
end entity fmsp_timerA;
architecture RTL of fmsp_timerA is
--=============================================================================
--! 1) PARAMETER DECLARATION
--=============================================================================
--! Register base address (must be aligned to decoder bit width)
constant BASE_ADDR : std_logic_vector(14 downto 0) := "000000100000000";
--! Decoder bit width (defines how many bits are considered for address decoding)
constant DEC_WD : integer := 7;
--! Register addresses offset
constant TACTL : integer := 096; --! 'h60,
constant TAR : integer := 112; --! 'h70,
constant TACCTL0 : integer := 098; --! 'h62,
constant TACCR0 : integer := 114; --! 'h72,
constant TACCTL1 : integer := 100; --! 'h64,
constant TACCR1 : integer := 116; --! 'h74,
constant TACCTL2 : integer := 102; --! 'h66,
constant TACCR2 : integer := 118; --! 'h76,
constant TAIV : integer := 046; --! 'h2E;
--! Register one-hot decoder utilities
constant DEC_SZ : integer := (2**DEC_WD);
--! Timer A: TACCTLx Capture/Compare Control Register
constant TACLR : integer := 2;
constant TAIE : integer := 1;
constant TAIFG : integer := 0;
--! constant TACMx 15 downto 14
--! constant TACCISx 13 downto 12
constant TASCS : integer := 11;
constant TASCCI : integer := 10;
constant TACAP : integer := 8;
--! constant TAOUTMODx 7 downto 5
constant TACCIE : integer := 4;
constant TACCI : integer := 3;
constant TAOUT : integer := 2;
constant TACOV : integer := 1;
constant TACCIFG : integer := 0;
constant capture_unit_nb : integer := 3;
type array_ofregisters is array(0 to capture_unit_nb-1) of std_logic_vector(15 downto 0);
type array_ofunsigneds is array(0 to capture_unit_nb-1) of unsigned(15 downto 0);
type fmsp_timerA_in_type is record
aclk_en : std_logic; --! ACLK enable (from CPU)
smclk_en : std_logic; --! SMCLK enable (from CPU)
dbg_freeze : std_logic; --! Freeze Timer A counter
irq_ta0_acc : std_logic; --! Interrupt request TACCR0 accepted
per_addr : std_logic_vector(13 downto 0); --! Peripheral address
per_din : std_logic_vector(15 downto 0); --! Peripheral data input
per_en : std_logic; --! Peripheral enable (high active)
per_we : std_logic_vector(1 downto 0); --! Peripheral write enable (high active)
taclk_s : std_logic;
inclk_s : std_logic;
--! Shared
ta_ccixa : std_logic_vector(2 downto 0); --! Timer capture input A
ta_ccixb : std_logic_vector(2 downto 0); --! Timer capture input B
ccix_s : std_logic_vector(2 downto 0);
end record;
type reg_type is record
tactl : std_logic_vector(9 downto 0);
tar : unsigned(15 downto 0);
taclk_dly : std_logic;
inclk_dly : std_logic;
clk_div : unsigned(2 downto 0);
tar_dir : std_logic;
--! Shared
tacctlx : array_ofregisters;
taccrx : array_ofunsigneds;
sccix : std_logic_vector(2 downto 0);
ccix_dly : std_logic_vector(2 downto 0);
ccix_evt_s : std_logic_vector(2 downto 0);
ccix_sync : std_logic_vector(2 downto 0);
capx_taken : std_logic_vector(2 downto 0);
ta_outx : std_logic_vector(2 downto 0);
end record;
signal d : fmsp_timerA_in_type;
signal r : reg_type := ( tactl => "0000000000",
tar => x"0000",
taclk_dly => '0',
inclk_dly => '0',
clk_div => "000",
tar_dir => '0',
tacctlx => (Others => x"0000"),
taccrx => (Others => x"0000"),
sccix => "000",
ccix_dly => "000",
ccix_evt_s => "000",
ccix_sync => "000",
capx_taken => "000",
ta_outx => "000"
);
signal rin : reg_type;
signal cci : std_logic_vector(2 downto 0) := "000";
begin
d.aclk_en <= aclk_en;
d.smclk_en <= smclk_en;
d.dbg_freeze <= dbg_freeze;
d.irq_ta0_acc <= irq_ta0_acc;
-- d.taclk <= taclk;
-- d.inclk <= inclk;
d.per_addr <= per_addr;
d.per_din <= per_din;
d.per_en <= per_en;
d.per_we <= per_we;
d.ta_ccixa(0) <= ta_cci0a;
d.ta_ccixb(0) <= ta_cci0b;
d.ta_ccixa(1) <= ta_cci1a;
d.ta_ccixb(1) <= ta_cci1b;
d.ta_ccixa(2) <= ta_cci2a;
d.ta_ccixb(2) <= ta_cci2b;
COMB : process (d, r)
variable v : reg_type;
--! Local register selection
variable v_reg_sel : std_logic;
--! Register local address
variable v_reg_addr : std_logic_vector(DEC_WD-2 downto 0);
--! Register address decode
variable v_reg_dec : std_logic_vector((DEC_SZ/2)-1 downto 0);
--! Read/Write probes
variable v_reg_write : std_logic;
variable v_reg_read : std_logic;
--! Read/Write vectors
variable v_reg_wr : std_logic_vector(DEC_SZ-1 downto 0);
variable v_reg_rd : std_logic_vector(DEC_SZ-1 downto 0);
variable v_tactl_wr : std_logic;
variable v_ta_clr : std_logic;
variable v_taifg_set : std_logic;
variable v_taifg_clr : std_logic;
--! TAR Register
variable v_tar_wr : std_logic;
variable v_tar_clk : std_logic;
variable v_tar_clr : std_logic;
variable v_tar_inc : std_logic;
variable v_tar_dec : std_logic;
variable v_tar_add : unsigned(15 downto 0);
variable v_tar_nxt : unsigned(15 downto 0);
--! TACCTL0 Register
variable v_tacctlx_wr : std_logic_vector(2 downto 0);
variable v_ccifgx_set : std_logic_vector(2 downto 0);
variable v_covx_set : std_logic_vector(2 downto 0);
variable v_ccix : std_logic_vector(2 downto 0);
variable v_tacctlx_full : array_ofregisters;
--! TACCR0 Register
variable v_taccrx_wr : std_logic_vector(2 downto 0);
variable v_ccix_cap : std_logic_vector(2 downto 0);
variable v_equx : std_logic_vector(2 downto 0);
--! Input selection
-- variable v_ccix : std_logic_vector(2 downto 0);
--! Capture mode
variable v_ccix_evt : std_logic_vector(2 downto 0);
--! Generate final capture command
-- variable v_ccix_cap : std_logic_vector(2 downto 0);
--! Generate capture overflow flag
variable v_capx_taken_clr : std_logic_vector(2 downto 0);
-- variable v_covx_set : std_logic_vector(2 downto 0);
--! Output unit 0
variable v_ta_outx_mode0 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode1 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode2 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode3 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode4 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode5 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode6 : std_logic_vector(2 downto 0);
variable v_ta_outx_mode7 : std_logic_vector(2 downto 0);
variable v_ta_outx_nxt : std_logic_vector(2 downto 0);
variable v_ta_outx_en : std_logic_vector(2 downto 0);
--! 9) Timer A interrupt generation
-- variable v_ccifgx_set : std_logic_vector(2 downto 0);
--! TAIV Register
variable v_taiv : std_logic_vector(3 downto 0);
variable v_ccifg1_clr : std_logic;
variable v_ccifg2_clr : std_logic;
variable v_ccifgx_clr : std_logic_vector(2 downto 0);
-- variable v_taifg_clr : std_logic;
--! Data output mux
variable v_tactl_rd : std_logic_vector(15 downto 0);
variable v_tar_rd : std_logic_vector(15 downto 0);
variable v_tacctl0_rd : std_logic_vector(15 downto 0);
variable v_taccr0_rd : std_logic_vector(15 downto 0);
variable v_tacctl1_rd : std_logic_vector(15 downto 0);
variable v_taccr1_rd : std_logic_vector(15 downto 0);
variable v_tacctl2_rd : std_logic_vector(15 downto 0);
variable v_taccr2_rd : std_logic_vector(15 downto 0);
variable v_taiv_rd : std_logic_vector(15 downto 0);
variable v_per_dout : std_logic_vector(15 downto 0);
--! Clock edge detection (TACLK & INCLK)
variable v_taclk_en : std_logic;
variable v_inclk_en : std_logic;
--! Timer clock input mux
variable v_sel_clk : std_logic;
--! Generate update pluse for the counter (<=> divided clock)
-- variable v_tar_clk : std_logic;
-- --! Time counter control signals
-- variable v_tar_clr : std_logic;
-- variable v_tar_inc : std_logic;
-- variable v_tar_dec : std_logic;
--! 9) Timer A interrupt generation
-- variable v_taifg_set : std_logic;
variable v_irq_ta0 : std_logic;
variable v_irq_ta1 : std_logic;
--! Timer A: TACTL Control Register
alias a_TACTL_TASSELx : std_logic_vector(1 downto 0) is r.tactl(9 downto 8);
alias a_TACTL_TAIDx : std_logic_vector(1 downto 0) is r.tactl(7 downto 6);
alias a_TACTL_TAMCx : std_logic_vector(1 downto 0) is r.tactl(5 downto 4);
alias a_TACTL_TACLR : std_logic is r.tactl(2);
alias a_TACTL_TAIE : std_logic is r.tactl(1);
alias a_TACTL_TAIFG : std_logic is r.tactl(0);
begin
--! default assignment
v := r;
--! overriding assignments
--============================================================================
--! 1) REGISTER DECODER
--============================================================================
--! Local register selection
if ( d.per_addr(13 downto DEC_WD-1) = BASE_ADDR(14 downto DEC_WD) ) then
v_reg_sel := d.per_en;
else
v_reg_sel := '0';
end if;
--! Register local address
v_reg_addr := d.per_addr(DEC_WD-2 downto 0);
--! Register address decode
v_reg_dec := onehot(v_reg_addr);
--! Read/Write probes
v_reg_write := v_reg_sel and (d.per_we(0) or d.per_we(1));
v_reg_read := v_reg_sel and not(d.per_we(0) or d.per_we(1));
--! Read/Write vectors
for i in 0 to (DEC_SZ/2)-1 loop
v_reg_wr((i*2)+0) := v_reg_dec(i) and v_reg_write;
v_reg_wr((i*2)+1) := v_reg_dec(i) and v_reg_write;
v_reg_rd((i*2)+0) := v_reg_dec(i) and v_reg_read;
v_reg_rd((i*2)+1) := v_reg_dec(i) and v_reg_read;
end loop;
--============================================================================
--! 3) REGISTERS
--============================================================================
v_tactl_wr := v_reg_wr(TACTL);
v_ta_clr := v_tactl_wr and d.per_din(TACLR);
v_tar_wr := v_reg_wr(TAR);
--! TAIV Register
--------------------
if ( (r.tacctlx(1)(TACCIFG) = '1') and (r.tacctlx(1)(TACCIE) = '1') ) then
v_taiv := x"2";
elsif ( (r.tacctlx(2)(TACCIFG) = '1') and (r.tacctlx(2)(TACCIE) = '1') ) then
v_taiv := x"4";
elsif ( (r.tactl(TAIFG) = '1') and (r.tactl(TAIE) = '1') ) then
v_taiv := x"A";
else
v_taiv := x"0";
end if;
v_ccifg1_clr := '0';
v_ccifg2_clr := '0';
v_taifg_clr := '0';
if (v_taiv = x"2") then
v_ccifg1_clr := v_reg_rd(TAIV) or v_reg_wr(TAIV);
end if;
if (v_taiv = x"4") then
v_ccifg2_clr := v_reg_rd(TAIV) or v_reg_wr(TAIV);
end if;
if (v_taiv = x"A") then
v_taifg_clr := v_reg_rd(TAIV) or v_reg_wr(TAIV);
end if;
--============================================================================
--! 5) Timer A counter control
--============================================================================
--! Clock edge detection (TACLK & INCLK)
-------------------------------------------------------------
v.taclk_dly := d.taclk_s;
v_taclk_en := d.taclk_s and not(r.taclk_dly);
v.inclk_dly := d.inclk_s;
v_inclk_en := d.inclk_s and not(r.inclk_dly);
--! Timer clock input mux
-------------------------------------------------------------
if (r.tactl(9 downto 8) = "00") then
v_sel_clk := v_taclk_en;
elsif (r.tactl(9 downto 8) = "01") then
v_sel_clk := d.aclk_en;
elsif (r.tactl(9 downto 8) = "10") then
v_sel_clk := d.smclk_en;
else
v_sel_clk := v_inclk_en;
end if;
--! Generate update pulse for the counter (<=> divided clock)
-------------------------------------------------------------
if (r.tactl(7 downto 6) = "00") then
v_tar_clk := v_sel_clk;
elsif (r.tactl(7 downto 6) = "01") then
v_tar_clk := v_sel_clk and r.clk_div(0);
elsif (r.tactl(7 downto 6) = "10") then
v_tar_clk := v_sel_clk and r.clk_div(0) and r.clk_div(1);
else
v_tar_clk := v_sel_clk and r.clk_div(0) and r.clk_div(1) and r.clk_div(2);
end if;
--! Time counter control signals
-------------------------------------------------------------
v_tar_clr := '0';
if ( ( (r.tactl(5 downto 4) = "01") and (r.tar >= r.taccrx(0)) )
or ( (r.tactl(5 downto 4) = "11") and (r.taccrx(0) = x"0000") ) ) then
v_tar_clr := '1';
end if;
v_tar_dec := '0';
if ( (r.tar_dir = '1')
or ( (r.tactl(5 downto 4) = "11") and (r.tar >= r.taccrx(0)) ) ) then
v_tar_dec := '1';
end if;
v_tar_inc := '0';
if ( (r.tactl(5 downto 4) = "01")
or (r.tactl(5 downto 4) = "01")
or ( (r.tactl(5 downto 4) = "11") and (not(v_tar_dec) = '1') ) ) then
v_tar_inc := '1';
end if;
if ( (v_tar_clk or v_ta_clr) = '1' ) then
v.clk_div := "000";
elsif ( (r.tactl(5 downto 4) /= "00") and (v_sel_clk = '1') ) then
v.clk_div := r.clk_div + TO_UNSIGNED(1,3);
end if;
if ( v_ta_clr = '1' ) then
v.tar_dir := '0';
elsif (r.tactl(5 downto 4) = "11") then
if ( (r.tar = x"0001") and (not(v_tar_clk) = '1') ) then
v.tar_dir := '0';
elsif (r.tar >= r.taccrx(0)) then
v.tar_dir := '1';
end if;
else
v.tar_dir := '0';
end if;
--! TAR Register
-------------------
if (v_tar_inc = '1') then
v_tar_add := x"0001";
elsif (v_tar_dec = '1') then
v_tar_add := x"FFFF";
else
v_tar_add := x"0000";
end if;
if (v_tar_clr = '1') then
v_tar_nxt := x"0000";
else
v_tar_nxt := r.tar + v_tar_add;
end if;
if (v_tar_wr = '1') then
v.tar := UNSIGNED(d.per_din);
elsif ((v_tar_clk and not(d.dbg_freeze)) = '1') then
v.tar := v_tar_nxt;
end if;
--============================================================================
--! 9) Timer A interrupt generation
--============================================================================
if ( ( (r.tactl(5 downto 4) = "01") and (r.tar = r.taccrx(0)) ) or
( (r.tactl(5 downto 4) = "10") and (r.tar = x"ffff") ) or
( (r.tactl(5 downto 4) = "11") and (v_tar_nxt = x"0000") and (v_tar_dec = '1') ) ) then
v_taifg_set := v_tar_clk;
else
v_taifg_set := '0';
end if;
--! TACTL Register
-------------------
if (v_tactl_wr = '1') then
v.tactl := ( (d.per_din(9 downto 0) and "1111110011") or ("000000000" & v_taifg_set) )
and ("111111111" & not(v_taifg_clr));
else
v.tactl := ( r.tactl or ("000000000" & v_taifg_set) )
and ("111111111" & not(v_taifg_clr));
end if;
--============================================================================
--! 7) Timer A capture logic
--============================================================================
for i in 0 to capture_unit_nb-1 loop
--! Input selection
--------------------
if (r.tacctlx(i)(13 downto 12) = "00") then
v_ccix(i) := d.ta_ccixa(i);
elsif (r.tacctlx(i)(13 downto 12) = "01") then
v_ccix(i) := d.ta_ccixb(i);
elsif (r.tacctlx(i)(13 downto 12) = "10") then
v_ccix(i) := '0';
else
v_ccix(i) := '1';
end if;
v.ccix_dly(i) := d.ccix_s(i);
--! Timer A comparator
v_equx(i) := '0';
if ( (v_tar_nxt = r.taccrx(i)) and (r.tar /= r.taccrx(i)) ) then
v_equx(i) := '1';
end if;
--! Generate SCCIx
--------------------
if ((v_tar_clk and v_equx(i)) = '1') then
v.sccix(i) := d.ccix_s(i);
end if;
--! Capture mode
--------------------
if (r.tacctlx(i)(15 downto 14) = "00") then
v_ccix_evt(i) := '0';
elsif (r.tacctlx(i)(15 downto 14) = "01") then
v_ccix_evt(i) := d.ccix_s(i) and not( r.ccix_dly(i)); --! Rising edge
elsif (r.tacctlx(i)(15 downto 14) = "10") then
v_ccix_evt(i) := not( d.ccix_s(i) ) and r.ccix_dly(i); --! Falling edge
else
v_ccix_evt(i) := d.ccix_s(i) xor r.ccix_dly(i); --! Both edges
end if;
--! Event Synchronization
-------------------------
if (v_tar_clk = '1') then
v.ccix_evt_s(i) := '0';
elsif (v_ccix_evt(i) = '1') then
v.ccix_evt_s(i) := '1';
end if;
if (v_tar_clk = '1') then
v.ccix_sync(i) := (v_tar_clk and r.ccix_evt_s(i)) or (v_tar_clk and v_ccix_evt(i) and not(r.ccix_evt_s(i)));
end if;
--! Generate final capture command
-------------------------------------
if (r.tacctlx(i)(TASCS) = '1') then
v_ccix_cap(i) := r.ccix_sync(i);
else
v_ccix_cap(i) := r.ccix_evt_s(i);
end if;
--! Generate capture overflow flag
-------------------------------------
v_capx_taken_clr(i) := v_reg_rd(TACCR0+(i*2)) or (v_tacctlx_wr(i) and v.tacctlx(i)(TACOV) and not(d.per_din(TACOV)));
if (v_ccix_cap(i) = '1') then
v.capx_taken(i) := '1';
elsif (v_capx_taken_clr(i) = '1') then
v.capx_taken(i) := '0';
end if;
v_covx_set(i) := r.capx_taken(i) and v_ccix_cap(i) and not(v_reg_rd(TACCR0+(i*2)));
if (r.tacctlx(i)(TACAP) = '1') then
v_ccifgx_set(i) := v_ccix_cap(i);
elsif (r.tactl(5 downto 4) /= "00") then
v_ccifgx_set(i) := v_tar_clk and v_equx(i);
else
v_ccifgx_set(i) := '0';
end if;
end loop;
v_ccifgx_clr(0) := d.irq_ta0_acc;
v_ccifgx_clr(1) := v_ccifg1_clr;
v_ccifgx_clr(2) := v_ccifg2_clr;
for i in 0 to capture_unit_nb-1 loop
v_tacctlx_wr(i) := v_reg_wr((TACCTL0+(i*2)));
--! TACCTLx Registers
if (v_tacctlx_wr(i) = '1') then
v.tacctlx(i) := ( (d.per_din and x"F9F7") or ("00000000000000" & v_covx_set(i) & v_ccifgx_set(i)) )
and ("111111111111111" & not(v_ccifgx_clr(i)));
else
v.tacctlx(i) := ( r.tacctlx(i) or ("00000000000000" & v_covx_set(i) & v_ccifgx_set(i)) )
and ("111111111111111" & not(v_ccifgx_clr(i)));
end if;
v_tacctlx_full(i) := r.tacctlx(i) or ("00000" & r.sccix(i) & "000000" & d.ccix_s(i) & "000");
--! TACCRx Registers
--------------------
v_taccrx_wr(i) := v_reg_wr((TACCR0+(i*2)));
if (v_taccrx_wr(i) = '1') then
v.taccrx(i) := UNSIGNED(d.per_din);
elsif (v_ccix_cap(i) = '1') then
v.taccrx(i) := r.tar;
end if;
end loop;
--============================================================================
--! 9) Timer A interrupt generation
--============================================================================
v_irq_ta0 := r.tacctlx(0)(TACCIFG) and r.tacctlx(0)(TACCIE);
v_irq_ta1 := (r.tactl(TAIFG) and r.tactl(TAIE))
or (r.tacctlx(1)(TACCIFG) and r.tacctlx(1)(TACCIE))
or (r.tacctlx(2)(TACCIFG) and r.tacctlx(2)(TACCIE));
--============================================================================
--! 8) Timer A output unit
--============================================================================
for i in 0 to capture_unit_nb-1 loop
v_ta_outx_mode0(i) := r.tacctlx(i)(TAOUT); --! Output
if (v_equx(i) = '1') then --! Set
v_ta_outx_mode1(i) := '1';
else
v_ta_outx_mode1(i) := r.ta_outx(i);
end if;
if (v_equx(i) = '1') then --! Toggle/Reset
v_ta_outx_mode2(i) := not(r.ta_outx(i));
elsif (v_equx(0) = '1') then
v_ta_outx_mode2(i) := '0';
else
v_ta_outx_mode2(i) := r.ta_outx(i);
end if;
if (v_equx(i) = '1') then --! Set/Reset
v_ta_outx_mode3(i) := '1';
elsif (v_equx(0) = '1') then
v_ta_outx_mode3(i) := '0';
else
v_ta_outx_mode3(i) := r.ta_outx(i);
end if;
if (v_equx(i) = '1') then --! Toggle
v_ta_outx_mode4(i) := not(r.ta_outx(i));
else
v_ta_outx_mode4(i) := r.ta_outx(i);
end if;
if (v_equx(i) = '1') then --! Reset
v_ta_outx_mode5(i) := '0';
else
v_ta_outx_mode5(i) := r.ta_outx(i);
end if;
if (v_equx(i) = '1') then --! Toggle/Set
v_ta_outx_mode6(i) := not(r.ta_outx(i));
elsif (v_equx(0) = '1') then
v_ta_outx_mode6(i) := '1';
else
v_ta_outx_mode6(i) := r.ta_outx(i);
end if;
if (v_equx(i) = '1') then --! Reset/Set
v_ta_outx_mode7(i) := '0';
elsif (v_equx(0) = '1') then
v_ta_outx_mode7(i) := '1';
else
v_ta_outx_mode7(i) := r.ta_outx(i);
end if;
if (r.tacctlx(i)(7 downto 5) = "000") then
v_ta_outx_nxt(i) := v_ta_outx_mode0(i);
elsif (r.tacctlx(i)(7 downto 5) = "001") then
v_ta_outx_nxt(i) := v_ta_outx_mode1(i);
elsif (r.tacctlx(i)(7 downto 5) = "010") then
v_ta_outx_nxt(i) := v_ta_outx_mode2(i);
elsif (r.tacctlx(i)(7 downto 5) = "011") then
v_ta_outx_nxt(i) := v_ta_outx_mode3(i);
elsif (r.tacctlx(i)(7 downto 5) = "100") then
v_ta_outx_nxt(i) := v_ta_outx_mode4(i);
elsif (r.tacctlx(i)(7 downto 5) = "101") then
v_ta_outx_nxt(i) := v_ta_outx_mode5(i);
elsif (r.tacctlx(i)(7 downto 5) = "110") then
v_ta_outx_nxt(i) := v_ta_outx_mode6(i);
else
v_ta_outx_nxt(i) := v_ta_outx_mode7(i);
end if;
if ( (r.tacctlx(i)(7 downto 5) = "001") and (v_ta_clr = '1') ) then
v.ta_outx(i) := '0';
elsif (v_tar_clk = '1') then
v.ta_outx(i) := v_ta_outx_nxt(i);
end if;
v_ta_outx_en(i) := not(r.tacctlx(i)(TACAP));
end loop;
--============================================================================
--! 4) DATA OUTPUT GENERATION
--============================================================================
--! Data output mux
v_tactl_rd := word_per_select_dout( TACTL, v_reg_rd, ("000000" & r.tactl) );
v_tar_rd := word_per_select_dout( TAR, v_reg_rd, STD_LOGIC_VECTOR(r.tar) );
v_tacctl0_rd := word_per_select_dout( TACCTL0, v_reg_rd, v_tacctlx_full(0) );
v_taccr0_rd := word_per_select_dout( TACCR0, v_reg_rd, STD_LOGIC_VECTOR(r.taccrx(0)) );
v_tacctl1_rd := word_per_select_dout( TACCTL1, v_reg_rd, v_tacctlx_full(1) );
v_taccr1_rd := word_per_select_dout( TACCR1, v_reg_rd, STD_LOGIC_VECTOR(r.taccrx(1)) );
v_tacctl2_rd := word_per_select_dout( TACCTL2, v_reg_rd, v_tacctlx_full(2) );
v_taccr2_rd := word_per_select_dout( TACCR2, v_reg_rd, STD_LOGIC_VECTOR(r.taccrx(2)) );
v_taiv_rd := word_per_select_dout( TAIV, v_reg_rd, (x"000" & v_taiv) );
v_per_dout := v_tactl_rd or
v_tar_rd or
v_tacctl0_rd or
v_taccr0_rd or
v_tacctl1_rd or
v_taccr1_rd or
v_tacctl2_rd or
v_taccr2_rd or
v_taiv_rd;
--! drive register inputs
rin <= v;
--! drive module outputs
cci <= v_ccix;
irq_ta0 <= v_irq_ta0; --! Timer A interrupt: TACCR0
irq_ta1 <= v_irq_ta1; --! Timer A interrupt: TAIV, TACCR1, TACCR2
per_dout <= v_per_dout; --! Peripheral data output
ta_out0 <= r.ta_outx(0); --! Timer A output 0
ta_out0_en <= v_ta_outx_en(0); --! Timer A output 0 enable
ta_out1 <= r.ta_outx(1); --! Timer A output 1
ta_out1_en <= v_ta_outx_en(1); --! Timer A output 1 enable
ta_out2 <= r.ta_outx(2); --! Timer A output 2
ta_out2_en <= v_ta_outx_en(2); --! Timer A output 2 enable
end process COMB;
REGS : process (mclk,mrst)
begin
if (mrst = '1') then
r <= ( tactl => "0000000000",
tar => x"0000",
taclk_dly => '0',
inclk_dly => '0',
clk_div => "000",
tar_dir => '0',
tacctlx => (Others => x"0000"),
taccrx => (Others => x"0000"),
sccix => "000",
ccix_dly => "000",
ccix_evt_s => "000",
ccix_sync => "000",
capx_taken => "000",
ta_outx => "000"
);
elsif rising_edge(mclk) then
r <= rin;
end if;
end process REGS;
--! CCIx synchronization
sync_cell_cci0 : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => cci(0),
data_out => d.ccix_s(0)
);
sync_cell_cci1 : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => cci(1),
data_out => d.ccix_s(1)
);
sync_cell_cci2 : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => cci(2),
data_out => d.ccix_s(2)
);
--! Synchronization
sync_cell_taclk : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => taclk,
data_out => d.taclk_s
);
sync_cell_inclk : fmsp_sync_cell
port map(
clk => mclk,
rst => mrst,
data_in => inclk,
data_out => d.inclk_s
);
end RTL; --! fmsp_timerA
| bsd-3-clause | 710d5359d6a23c1a792977276d219ab0 | 0.541113 | 2.505043 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/lvds_combo.vhd | 1 | 3,878 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: lvds_combo.vhd
-- File: lvds_combo.vhd.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Differential input/output pads with IREF/OREF logic wrapper
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity lvds_combo is
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
oepol : integer := 0; term : integer := 0);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
powerdown : in std_logic_vector(0 to width-1) := (others => '0');
powerdownrx : in std_logic_vector(0 to width-1) := (others => '0');
lvdsref : in std_logic := '1';
lvdsrefo : out std_logic
);
end ;
architecture rtl of lvds_combo is
signal gnd : std_ulogic;
signal oen : std_logic_vector(0 to width-1);
constant level : integer := lvds;
begin
gnd <= '0';
gen0 : if has_ds_combo(tech) = 0 generate
swloop : for i in 0 to width-1 generate
od0 : outpad_ds generic map (tech, level, voltage, oepol) port map (odpadp(i), odpadn(i), odval(i), en(i));
os0 : outpad_ds generic map (tech, level, voltage, oepol) port map (ospadp(i), ospadn(i), osval(i), en(i));
id0 : inpad_ds generic map (tech, level, voltage) port map (idpadp(i), idpadn(i), idval(i));
is0 : inpad_ds generic map (tech, level, voltage) port map (ispadp(i), ispadn(i), isval(i));
end generate;
end generate;
combo : if has_ds_combo(tech) /= 0 generate
oen <= not en when oepol /= padoen_polarity(tech) else en;
ut025 : if tech = ut25 generate
u0: ut025crh_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval);
end generate;
ut13 : if tech = ut130 generate
u0: ut130hbd_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, powerdown, powerdownrx, lvdsrefo);
end generate;
um : if tech = umc generate
u0: umc_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, lvdsref);
end generate;
rhu : if tech = rhumc generate
u0: rhumc_lvds_combo generic map (voltage, width)
port map (odpadp, odpadn, ospadp, ospadn, odval, osval, oen,
idpadp, idpadn, ispadp, ispadn, idval, isval, powerdown, powerdownrx, lvdsrefo);
end generate;
end generate;
end;
| gpl-2.0 | ebcc7ee15253204eba89c42d9c3a0a2f | 0.633574 | 3.700382 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/i2c/i2c2ahb_gen.vhd | 1 | 4,161 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_gen
-- File: i2c2ahb_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Generic wrapper for I2C-slave, see i2c2ahb.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb_gen is
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(AHBDW-1 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(AHBDW-1 downto 0);
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2c2ahb_gen;
architecture rtl of i2c2ahb_gen is
-- AHB signals
signal ahbi : ahb_mst_in_type;
signal ahbo : ahb_mst_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
ahbi.hgrant(0) <= ahbi_hgrant;
ahbi.hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi.hready <= ahbi_hready;
ahbi.hresp <= ahbi_hresp;
ahbi.hrdata <= ahbi_hrdata;
ahbo_hbusreq <= ahbo.hbusreq;
ahbo_hlock <= ahbo.hlock;
ahbo_htrans <= ahbo.htrans;
ahbo_haddr <= ahbo.haddr;
ahbo_hwrite <= ahbo.hwrite;
ahbo_hsize <= ahbo.hsize;
ahbo_hburst <= ahbo.hburst;
ahbo_hprot <= ahbo.hprot;
ahbo_hwdata <= ahbo.hwdata;
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2c2ahb
generic map (
hindex => 0,
ahbaddrh => ahbaddrh, ahbaddrl => ahbaddrl,
ahbmaskh => ahbmaskh, ahbmaskl => ahbmaskl,
i2cslvaddr => i2cslvaddr, i2ccfgaddr => i2ccfgaddr,
oepol => oepol, filter => filter)
port map (rstn, clk, ahbi, ahbo, i2ci, i2co);
end architecture rtl;
| gpl-2.0 | 2373a851a87e44ab6d5694583ef2dee7 | 0.597212 | 3.315538 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Accum/src/MRAM.vhd | 1 | 2,045 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library accum;
use accum.OneHotAccum.all;
entity MRAM is
port (
CLK: in std_logic;
RW: in std_logic;
ADDR: in mem_addr;
DIN: in operand;
DOUT: out operand
);
end MRAM;
architecture Beh of MRAM is
type tRAM is array (0 to 31) of operand;
signal RAM: tRAM:= (
-- | BIN | ADR BIN
"0000000000000000", -- | 00000 |
"0000000000000000", -- | 00001 |
"0000000000000000", -- | 00010 |
"0000000000000000", -- | 00011 |
"0000000000000000", -- | 00100 |
"0000000000000000", -- | 00101 |
"0000000000000000", -- | 00110 |
"0000000000000000", -- | 00111 |
"0000000000000000", -- | 01000 |
"0000000000000000", -- | 01001 |
"0000000000000000", -- | 01010 |
"0000000000000000", -- | 01011 |
"0000000000000000", -- | 01100 |
"0000000000000000", -- | 01101 |
"0000000000000000", -- | 01110 |
"0000000000000000", -- | 01111 |
"0000000000001000", -- | 10000 |
"0000000000000000", -- | 10001 |
"0000000000000000", -- | 10010 |
"0000000000000001", -- | 10011 |
"0000000000000000", -- | 10100 |
"0000000000000001", -- | 10101 |
others => "0000000000000000"
);
signal data_in: operand;
signal data_out: operand;
Begin
data_in <= Din;
WRITE: process (CLK, RW, ADDR, data_in)
begin
if (RW = '0') then
if (rising_edge(CLK)) then
RAM(conv_integer(ADDR)) <= data_in;
end if;
end if;
end process;
data_out <= RAM (conv_integer(ADDR));
RDP: process (RW, RAM, data_out)
begin
if (RW = '1') then
DOUT <= data_out;
else
DOUT <= (others => 'Z');
end if;
end process;
end Beh; | mit | 57749ad73ee73725ccce901fefb0b41f | 0.490465 | 3.773063 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-ztex-ufm-115/testbench.vhd | 1 | 7,474 | -------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2011 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
constant lresp : boolean := false;
signal reset : std_ulogic := '1';
signal clk48 : std_ulogic := '0';
signal errorn : std_logic;
signal mcb3_dram_dq : std_logic_vector(15 downto 0);
signal mcb3_rzq : std_logic;
signal mcb3_zio : std_logic;
signal mcb3_dram_dqs : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n : std_logic_vector(1 downto 0);
signal mcb3_dram_a : std_logic_vector(12 downto 0);
signal mcb3_dram_ba : std_logic_vector(2 downto 0);
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_dm : std_logic_vector(1 downto 0);
signal mcb3_dram_udm : std_logic;
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal dsubre : std_ulogic; -- Debug Unit break (connect to button)
signal dsuact : std_ulogic; -- Debug Unit break (connect to button)
signal dsurx : std_ulogic;
signal dsutx : std_ulogic;
signal rxd1 : std_ulogic;
signal txd1 : std_ulogic;
signal sd_dat : std_logic;
signal sd_cmd : std_logic;
signal sd_sck : std_logic;
signal sd_dat3 : std_logic;
signal csb : std_logic := '0'; -- dummy
begin
-- clock and reset
clk48 <= not clk48 after 10.417 ns;
reset <= '1', '0' after 300 ns;
dsubre <= '0';
sd_dat <= 'H';
sd_cmd <= 'H';
sd_sck <= 'H';
d3 : entity work.leon3mp
generic map (fabtech, memtech, padtech, clktech, disas, dbguart, pclow)
port map (
reset => reset,
clk48 => clk48,
-- Processor error output
errorn => errorn,
-- DDR SDRAM
mcb3_dram_dq => mcb3_dram_dq,
mcb3_rzq => mcb3_rzq,
mcb3_zio => mcb3_zio,
mcb3_dram_udqs => mcb3_dram_dqs(1),
mcb3_dram_udqs_n => mcb3_dram_dqs_n(1),
mcb3_dram_dqs => mcb3_dram_dqs(0),
mcb3_dram_dqs_n => mcb3_dram_dqs_n(0),
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_dm => mcb3_dram_dm(0),
mcb3_dram_udm => mcb3_dram_dm(1),
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
-- Debug support unit
dsubre => dsubre,
dsuact => dsuact,
-- AHB UART (debug link)
dsurx => dsurx,
dsutx => dsutx,
-- UART
rxd1 => rxd1,
txd1 => txd1,
-- SD card
sd_dat => sd_dat,
sd_cmd => sd_cmd,
sd_sck => sd_sck,
sd_dat3 => sd_dat3
);
migddr2mem : if (CFG_MIG_DDR2 = 1) generate
ddr0 : ddr2ram
generic map(width => 16, abits => 13, babits => 3, colbits => 10, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin=>9, density => 2,
lddelay => 115 us)
port map (ck => mcb3_dram_ck, ckn => mcb3_dram_ck_n, cke => mcb3_dram_cke, csn => csb,
odt => '0', rasn => mcb3_dram_ras_n, casn => mcb3_dram_cas_n, wen => mcb3_dram_we_n,
dm => mcb3_dram_dm, ba => mcb3_dram_ba, a => mcb3_dram_a(12 downto 0),
dq => mcb3_dram_dq, dqs => mcb3_dram_dqs, dqsn => mcb3_dram_dqs_n);
end generate;
--spimem0: if CFG_SPIMCTRL = 1 generate
-- s0 : spi_flash generic map (ftype => 4, debug => 0, fname => promfile,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => 0) -- Dual output is not supported in this design
-- port map (spi_clk, spi_mosi, data(24), spi_sel_n);
--end generate spimem0;
iuerr : process
begin
wait for 5 us;
assert (to_X01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
| gpl-2.0 | 44370cb6a2d44bcf927b774afac436ee | 0.544421 | 3.33066 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/mmu_acache.vhd | 1 | 14,456 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_acache
-- File: mmu_acache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Interface module between (MMU,I/D cache controllers) and Amba AHB
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.leon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
entity mmu_acache is
generic (
hindex : integer range 0 to NAHBMST-1 := 0;
ilinesize : integer range 4 to 8 := 4;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0
);
port (
rst : in std_logic;
clk : in std_logic;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
mcmmi : in memory_mm_in_type;
mcmmo : out memory_mm_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbso : in ahb_slv_out_vector;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_acache is
type reg_type is record -- cache control register type
bg : std_logic; -- bus grant
bo : std_logic_vector(1 downto 0); -- bus owner
ba : std_logic; -- bus active
lb : std_ulogic; -- last burst cycle
retry : std_logic; -- retry/split pending
retry2 : std_ulogic; -- retry/split pending
werr : std_logic; -- write error
hlocken : std_ulogic; -- ready to perform locked transaction
hcache : std_logic; -- cacheable access
nba : std_ulogic;
nbo : std_logic_vector(1 downto 0); -- bus owner
end record;
type reg2_type is record
reqmsk : std_logic_vector(2 downto 0);
hclken2 : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RRES : reg_type := (
bg => '0',
bo => (others => '0'),
ba => '0',
lb => '0',
retry => '0',
retry2 => '0',
werr => '0',
hlocken => '0',
hcache => '0',
nba => '0',
nbo => (others => '0')
);
constant R2RES : reg2_type := (
reqmsk => (others => '0'), hclken2 => '0'
);
constant L3DI :integer := GAISLER_LEON3
;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, L3DI, 0, LEON3_VERSION, 0),
others => zero32);
constant ctbl : std_logic_vector(15 downto 0) := conv_std_logic_vector(cached, 16);
function dec_fixed(haddr : std_logic_vector(3 downto 0);
cached : integer)
return std_ulogic is
begin
if (cached /= 0) then return ctbl(conv_integer(haddr(3 downto 0)));
else return('1'); end if;
end;
signal r, rin : reg_type;
signal r2, r2in : reg2_type;
begin
comb : process(ahbi, r, rst, mcii, mcdi, mcmmi, ahbso, hclken, r2)
variable v : reg_type;
variable v2 : reg2_type;
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_logic; -- read/write
variable hlock : std_logic; -- bus lock
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_logic; -- bus request
variable iready, dready, mmready : std_logic;
variable igrant, dgrant, mmgrant : std_logic;
variable iretry, dretry, mmretry : std_logic;
variable ihcache, dhcache, mmhcache, dec_hcache : std_logic;
variable imexc, dmexc, mmmexc : std_logic;
variable dreq : std_logic;
variable nbo : std_logic_vector(1 downto 0);
variable su, nb, bo_icache : std_ulogic;
variable scanen : std_ulogic;
variable vreqmsk: std_ulogic;
variable burst : std_ulogic;
begin
-- initialisation
htrans := HTRANS_IDLE;
v := r; v.werr := '0'; v2 := r2;
iready := '0'; dready := '0'; mmready := '0';
igrant := '0'; dgrant := '0'; mmgrant := '0';
imexc := '0'; dmexc := '0'; mmmexc := '0'; hlock := '0';
iretry := '0'; dretry := '0'; mmretry := '0';
ihcache := '0'; dhcache := '0'; mmhcache := '0'; su := '0';
if (r.bo = "00") then bo_icache := '1'; else bo_icache := '0'; end if;
haddr := (others => '0');
hwrite := '0';
hsize := (others => '0');
hlock := '0';
hburst := (others => '0');
if ahbi.hready = '1' then v.lb := '0'; end if;
if scantest = 1 then scanen := ahbi.scanen; else scanen := '0'; end if;
v.retry2 := (r.retry or r.retry2) and not (r.ba and not r.retry);
vreqmsk := orv(r2.reqmsk);
-- generate AHB signals
dreq := mcdi.req;
hwdata := mcdi.data;
hbusreq := '0';
if (mcii.req = '1') and ((clk2x = 0) or (r2.reqmsk(2) = '1')) and (r.hlocken = '0') and
not (( ((r.ba and dreq) = '1') and (r.bo = "01")) or
( ((r.ba and mcmmi.req) = '1') and (r.bo = "10"))) then
nbo := "00";
hbusreq := '1'; burst := mcii.burst;
htrans := HTRANS_NONSEQ;
elsif (dreq = '1') and ((clk2x = 0) or (r2.reqmsk(1) = '1')) and
not (( ((r.ba and mcii.req) = '1') and (r.bo = "00")) or
( ((r.ba and mcmmi.req) = '1') and (r.bo = "10"))) then
nbo := "01";
hbusreq := '1'; burst := mcdi.burst;
if (not mcdi.lock or r.hlocken) = '1' then htrans := HTRANS_NONSEQ; end if;
elsif (mcmmi.req = '1') and ((clk2x = 0) or (r2.reqmsk(0) = '1')) and (r.hlocken = '0') and
not (( ((r.ba and mcii.req) = '1') and (r.bo = "00")) or
( ((r.ba and dreq) = '1') and (r.bo = "01"))) then
nbo := "10";
hbusreq := '1'; burst := '0';
htrans := HTRANS_NONSEQ;
else
nbo := "11"; burst := '0';
end if;
-- dont change bus master if we have started driving htrans
if r.nba = '1' then
nbo := r.nbo; hbusreq := '1'; htrans := HTRANS_NONSEQ;
end if;
-- dont change bus master on retry
if (r.retry2 and not r.ba) = '1' then
nbo := r.bo; hbusreq := '1'; htrans := HTRANS_NONSEQ;
end if;
dec_hcache := ahb_slv_dec_cache(mcdi.address, ahbso, cached);
if nbo = "10" then
haddr := mcmmi.address; hwrite := not mcmmi.read; hsize := '0' & mcmmi.size;
hlock := mcmmi.lock;
htrans := HTRANS_NONSEQ; hburst := HBURST_SINGLE;
if (mcmmi.req and r.bg and ahbi.hready and not r.retry) = '1'
then mmgrant := '1'; v.hcache := dec_fixed(haddr(31 downto 28), cached); end if;
elsif nbo = "00" then
haddr := mcii.address; hwrite := '0'; hsize := HSIZE_WORD; hlock := '0';
su := mcii.su;
if ((mcii.req and r.ba) = '1') and (r.bo = "00") and ((not r.retry) = '1') then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
if (((ilinesize = 4) and haddr(3 downto 2) = "10")
or ((ilinesize = 8) and haddr(4 downto 2) = "110")) and (ahbi.hready = '1')
then v.lb := '1'; end if;
end if;
if mcii.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (mcii.req and r.bg and ahbi.hready and not r.retry) = '1'
then igrant := '1'; v.hcache := dec_fixed(haddr(31 downto 28), cached); end if;
elsif nbo = "01" then
haddr := mcdi.address; hwrite := not mcdi.read; hsize := '0' & mcdi.size;
hlock := mcdi.lock;
if mcdi.asi /= "1010" then su := '1'; else su := '0'; end if; --ASI_UDATA
if mcdi.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if ((dreq and r.ba) = '1') and (r.bo = "01") and ((not r.retry) = '1') then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
hburst := HBURST_INCR;
end if;
if (dreq and r.bg and ahbi.hready and not r.retry) = '1' then
dgrant := (not mcdi.lock or r.hlocken) or (r.retry2 and (not r.bo(1) and r.bo(0)));
v.hcache := dec_hcache;
end if;
end if;
if (hclken = '1') or (clk2x = 0) then
if (r.ba = '1') and ((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT))
then v.retry := not ahbi.hready; else v.retry := '0'; end if;
end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if r.bo = "10" then
hwdata := mcmmi.data;
if r.ba = '1' then
mmhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => mmready := '1';
when HRESP_RETRY | HRESP_SPLIT=> mmretry := '1';
when others => mmready := '1'; mmmexc := '1'; v.werr := not mcmmi.read;
end case;
end if;
end if;
elsif r.bo = "00" then
if r.ba = '1' then
ihcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => iready := '1';
when HRESP_RETRY | HRESP_SPLIT=> iretry := '1';
when others => iready := '1'; imexc := '1';
end case;
end if;
end if;
elsif r.bo = "01" then
if r.ba = '1' then
dhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => dready := '1';
when HRESP_RETRY | HRESP_SPLIT=> dretry := '1';
when others => dready := '1'; dmexc := '1'; v.werr := not mcdi.read;
end case;
end if;
end if;
hlock := mcdi.lock or ((r.retry or (r.retry2 and not r.ba)) and r.hlocken);
end if;
if nbo = "01" and ((hsize = "011") or ((mcdi.read and mcdi.cache) = '1')) then
hsize := "010";
end if;
if (r.bo = "01") and (hlock = '1') then nbo := "01"; end if;
if ahbi.hready = '1' then
if r.retry = '0' then v.bo := nbo; end if;
v.bg := ahbi.hgrant(hindex);
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else v.ba := '0'; end if;
v.hlocken := hlock and ahbi.hgrant(hindex);
if (clk2x /= 0) then
igrant := igrant and vreqmsk;
dgrant := dgrant and vreqmsk;
mmgrant := mmgrant and vreqmsk;
if (r.bo = nbo) then v.ba := v.ba and vreqmsk; end if;
end if;
end if;
if hburst = HBURST_SINGLE then nb := '1'; else nb := '0'; end if;
v.nbo := nbo; v.nba := orv(htrans) and not v.ba;
-- parity generation
if (clk2x /= 0) then
v2.hclken2 := hclken;
if hclken = '1' then
v2.reqmsk := mcii.req & mcdi.req & mcmmi.req;
if (clk2x > 8) and (r2.hclken2 = '1') then v2.reqmsk := "111"; end if;
end if;
end if;
-- reset operation
if (not RESET_ALL) and (rst = '0') then
v.bg := '0'; v.bo := "00"; v.ba := '0'; v.retry := '0'; v.werr := '0'; v.lb := '0';
v.hcache := '0'; v.hlocken := '0'; v.nba := '0'; v.nbo := "00";
v.retry2 := '0';
end if;
-- drive ports
ahbo.haddr <= haddr ;
ahbo.htrans <= htrans;
-- ahbo.hbusreq <= hbusreq and not r.lb and not ((((not bo_icache) and r.ba) or nb) and r.bg);
-- ahbo.hbusreq <= hbusreq and not r.lb and not((not burst) and r.bg);
ahbo.hbusreq <= hbusreq and (not r.lb or orv(nbo)) and (burst or not r.bg);
ahbo.hwdata <= ahbdrivedata(hwdata);
ahbo.hlock <= hlock;
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hindex <= hindex;
if nbo = "00" then ahbo.hprot <= "11" & su & '0';
else ahbo.hprot <= "11" & su & '1'; end if;
mcio.grant <= igrant;
mcio.ready <= iready;
mcio.mexc <= imexc;
mcio.retry <= iretry;
mcio.cache <= ihcache;
mcdo.grant <= dgrant;
mcdo.ready <= dready;
mcdo.mexc <= dmexc;
mcdo.retry <= dretry;
mcdo.werr <= r.werr;
mcdo.cache <= dhcache;
mcdo.ba <= r.ba;
mcdo.bg <= r.bg and not v.bo(1);
mcmmo.grant <= mmgrant;
mcmmo.ready <= mmready;
mcmmo.mexc <= mmmexc;
mcmmo.retry <= mmretry;
mcmmo.werr <= r.werr;
mcmmo.cache <= mmhcache;
mcio.scanen <= scanen;
mcdo.scanen <= scanen;
mcdo.testen <= ahbi.testen;
rin <= v; r2in <= v2;
end process;
mcio.data <= ahbreadword(ahbi.hrdata);
mcdo.data <= ahbreadword(ahbi.hrdata);
mcmmo.data <= ahbreadword(ahbi.hrdata);
ahbo.hirq <= (others => '0');
ahbo.hconfig <= hconfig;
reg : process(clk)
begin
if rising_edge(clk) then
r <= rin;
if RESET_ALL and (rst = '0') then r <= RRES; end if;
end if;
end process;
reg2gen : if (clk2x /= 0) generate
reg2 : process(clk)
begin
if rising_edge(clk) then
r2 <= r2in;
if RESET_ALL and (rst = '0') then r2 <= R2RES; end if;
end if;
end process;
end generate;
noreg2gen : if (clk2x = 0) generate
r2.reqmsk <= "000";
end generate;
end;
| gpl-2.0 | cca10f5d0555f10673728cf095762190 | 0.53611 | 3.318641 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.cache/ip/2017.2/387128e4034068b3/zynq_design_1_processing_system7_0_2_sim_netlist.vhdl | 1 | 197,337 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:29:48 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_processing_system7_0_2_sim_netlist.vhdl
-- Design : zynq_design_1_processing_system7_0_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "zynq_design_1_processing_system7_0_2.hwdef";
attribute POWER : string;
attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1) => FCLK_CLK1,
FCLKCLK(0) => FCLK_CLK_unbuffered(0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zynq_design_1_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C0_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "zynq_design_1_processing_system7_0_2.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => '0',
I2C0_SCL_O => NLW_inst_I2C0_SCL_O_UNCONNECTED,
I2C0_SCL_T => NLW_inst_I2C0_SCL_T_UNCONNECTED,
I2C0_SDA_I => '0',
I2C0_SDA_O => NLW_inst_I2C0_SDA_O_UNCONNECTED,
I2C0_SDA_T => NLW_inst_I2C0_SDA_T_UNCONNECTED,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | bcdd7e32fe16bbad13f6787ed887ce7d | 0.634438 | 2.756488 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-gr-pci-xc2v3000/leon3mp.vhd | 1 | 26,983 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_logic;
clk : in std_logic;
pllref : in std_logic;
errorn : out std_logic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
sdclk : out std_logic;
sdcke : out std_logic_vector (1 downto 0); -- sdram clock enable
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_logic; -- sdram write enable
sdrasn : out std_logic; -- sdram ras
sdcasn : out std_logic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_logic; -- DSU tx data
dsurx : in std_logic; -- DSU rx data
dsuen : in std_logic;
dsubre : in std_logic;
dsuact : out std_logic;
txd1 : out std_logic; -- UART1 tx data
rxd1 : in std_logic; -- UART1 rx data
txd2 : out std_logic; -- UART2 tx data
rxd2 : in std_logic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_logic;
writen : out std_logic;
read : out std_logic;
iosn : out std_logic;
romsn : out std_logic_vector (1 downto 0);
gpio : inout std_logic_vector(7 downto 0); -- I/O port
emdio : inout std_logic; -- ethernet PHY interface
etx_clk : in std_logic;
erx_clk : in std_logic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_logic;
erx_er : in std_logic;
erx_col : in std_logic;
erx_crs : in std_logic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_logic;
etx_er : out std_logic;
emdc : out std_logic;
pci_rst : inout std_logic; -- PCI bus
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic;
pci_arb_req : in std_logic_vector(0 to 3);
pci_arb_gnt : out std_logic_vector(0 to 3);
spw_rxd : in std_logic_vector(0 to 1);
spw_rxs : in std_logic_vector(0 to 1);
spw_txd : out std_logic_vector(0 to 1);
spw_txs : out std_logic_vector(0 to 1)
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
CFG_GRETH+CFG_AHB_JTAG+log2x(CFG_PCI);
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal sdo2 : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal lclk, pci_lclk : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal tck, tms, tdi, tdo : std_logic;
signal resetnl, clk2x, spw_clkl : std_logic;
signal spwi : grspw_in_type_vector(0 to 2);
signal spwo : grspw_out_type_vector(0 to 2);
signal spw_rxclk : std_logic_vector(0 to CFG_SPW_NUM-1);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxtxclk : std_ulogic;
signal spw_rxclkn : std_ulogic;
constant IOAEN : integer := 0;
constant sysfreq : integer := (CFG_CLKMUL*40000/CFG_CLKDIV);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
pllref_pad : clkpad generic map (tech => padtech) port map (pllref, cgi.pllref);
clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, sysfreq)
port map (lclk, pci_lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech)
port map (sdclk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (resetn, resetnl);
rst0 : rstgen -- reset generator
port map (resetnl, clkm, cgo.clklock, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mctrl2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 2, sden => CFG_MCTRL_SDEN, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, invclk => CFG_MCTRL_INVCLK)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- SDRAM controller
sdwen_pad : outpad generic map (tech => padtech)
port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (sdrasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (sdcasn, sdo.casn);
sddqm_pad : outpadv generic map (width =>4, tech => padtech)
port map (sddqm, sdo.dqm(3 downto 0));
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, sdo.sdcke);
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, sdo.sdcsn);
end generate;
addr_pad : outpadv generic map (width => 28, tech => padtech)
port map (address, memo.address(27 downto 0));
rams_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramsn, memo.ramsn(4 downto 0));
roms_pad : outpadv generic map (width => 2, tech => padtech)
port map (romsn, memo.romsn(1 downto 0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (rwen, memo.wrn);
roen_pad : outpadv generic map (width => 5, tech => padtech)
port map (ramoen, memo.ramoen(4 downto 0));
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
read_pad : outpad generic map (tech => padtech)
port map (read, memo.read);
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (tech => padtech, width => 8)
port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcke, vcc(1 downto 0));
sdcsn_pad : outpadv generic map (width =>2, tech => padtech)
port map (sdcsn, vcc(1 downto 0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 8, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(8));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(8) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 3, fifosize => CFG_UART2_FIFO)
port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 8)
port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 4, paddr => 4, haddr => 16#E00#, irq => 4,
ioaddr => 16#400#, nsync => 2)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 4, apbaddr => 4, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 2, irq => 4)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clkm, pciclk, pcii, apbi, apbo(8));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 10, paddr => 10,
apb_en => CFG_PCI_ARBAPB)
port map ( clk => pciclk, rst_n => pcii.rst,
req_n => pci_arb_req_n, frame_n => pcii.frame,
gnt_n => pci_arb_gnt_n, pclk => clkm,
prst_n => rstn, apbi => apbi, apbo => apbo(10)
);
pgnt_pad : outpadv generic map (tech => padtech, width => 4)
port map (pci_arb_gnt, pci_arb_gnt_n);
preq_pad : inpadv generic map (tech => padtech, width => 4)
port map (pci_arb_req, pci_arb_req_n);
end generate;
pcipads0 : pcipads generic map (padtech => padtech, host => 0)-- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
end generate;
nop1 : if CFG_PCI <= 1 generate apbo(4) <= apb_none; end generate;
nop2 : if CFG_PCI <= 2 generate apbo(5) <= apb_none; end generate;
nop3 : if CFG_PCI <= 1 generate ahbso(4) <= ahbs_none; end generate;
notrc : if CFG_PCITBUFEN = 0 generate apbo(8) <= apb_none; end generate;
noarb : if CFG_PCI_ARB = 0 generate apbo(10) <= apb_none; end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 7, memtech => memtech,
mdcscaler => sysfreq/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG), apbi => apbi,
apbo => apbo(15), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 1)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw_clkl <= clk2x;
spw : if CFG_SPW_EN > 0 generate
spw_rxtxclk <= spw_clkl;
spw_rxclkn <= not spw_rxtxclk;
swloop : for i in 0 to CFG_SPW_NUM-1 generate
-- GRSPW2 PHY
spw2_input : if CFG_SPW_GRSPW = 2 generate
spw_phy0 : grspw2_phy
generic map(
scantest => 0,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => rstn,
rxclki => spw_rxtxclk,
rxclkin => spw_rxclkn,
nrxclki => spw_rxtxclk,
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => spw_rxclk(i));
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
end generate spw2_input;
-- GRSPW PHY
spw1_input: if CFG_SPW_GRSPW = 1 generate
spw_phy0 : grspw_phy
generic map(
tech => fabtech,
rxclkbuftype => 1,
scantest => 0)
port map(
rxrst => spwo(i).rxrst,
di => dtmp(i),
si => stmp(i),
rxclko => spw_rxclk(i),
do => spwi(i).d(0),
ndo => spwi(i).nd(4 downto 0),
dconnect => spwi(i).dconnect(1 downto 0));
spwi(i).d(1) <= '0';
spwi(i).dv <= (others => '0'); -- Only used in GRSPW2
spwi(i).nd(9 downto 5) <= "00000"; -- For second port
end generate spw1_input;
spwi(i).d(3 downto 2) <= "00"; -- For second port
spwi(i).dconnect(3 downto 2) <= "00"; -- For second port
spwi(i).s(1 downto 0) <= "00"; -- Only used in PHY
sw0 : grspwm generic map(tech => memtech,
hindex => maxahbmsp+i, pindex => 12+i, paddr => 12+i, pirq => 10+i,
sysfreq => sysfreq, nsync => 1, rmap => CFG_SPW_RMAP,
fifosize1 => CFG_SPW_AHBFIFO, fifosize2 => CFG_SPW_RXFIFO,
rxclkbuftype => 1, rmapbufs => CFG_SPW_RMAPBUF, ft => CFG_SPW_FT,
netlist => CFG_SPW_NETLIST, ports => 1, dmachan => CFG_SPW_DMACHAN,
spwcore => CFG_SPW_GRSPW,
input_type => CFG_SPW_INPUT, output_type => CFG_SPW_OUTPUT,
rxtx_sameclk => CFG_SPW_RTSAME, rxunaligned => CFG_SPW_RXUNAL)
port map(rstn, clkm, spw_rxclk(i), spw_rxclk(i), spw_rxtxclk, spw_rxtxclk,
ahbmi, ahbmo(maxahbmsp+i),
apbi, apbo(12+i), spwi(i), spwo(i));
spwi(i).tickin <= '0'; spwi(i).rmapen <= '1';
spwi(i).clkdiv10 <= conv_std_logic_vector(2*sysfreq/10000-1, 8);
spwi(i).dcrstval <= (others => '0');
spwi(i).timerrstval <= (others => '0');
spw_rxd_pad : inpad generic map (padtech)
port map (spw_rxd(i), dtmp(i));
spw_rxs_pad : inpad generic map (padtech)
port map (spw_rxs(i), stmp(i));
spw_txd_pad : outpad generic map (padtech)
port map (spw_txd(i), spwo(i).d(0));
spw_txs_pad : outpad generic map (padtech)
port map (spw_txs(i), spwo(i).s(0));
end generate;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in maxahbm to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nam2 : if CFG_PCI > 1 generate
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_PCI-1) <= ahbm_none;
-- end generate;
-- nap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1-CFG_GRETH generate apbo(i) <= apb_none; end generate;
-- apbo(6) <= apb_none;
-- nah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 GR-PCI-XC2V3000 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | fe87edd033f2cbd4d2e46673399b01e5 | 0.557129 | 3.482127 | false | false | false | false |
cesar-avalos3/C8VHDL | sources/vhdl/mem_controller.vhd | 1 | 12,451 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity mem_controller is
Port ( memAddress : in STD_LOGIC_VECTOR (35 downto 0);
dataIn : in STD_LOGIC_VECTOR (23 downto 0);
dataOut : out STD_LOGIC_VECTOR (23 downto 0);
valid : in STD_LOGIC_VECTOR (2 downto 0);
done : out STD_LOGIC_VECTOR (2 downto 0);
write : in STD_LOGIC_VECTOR (2 downto 0);
hold : in STD_LOGIC_VECTOR (2 downto 0);
gameSelect : in STD_LOGIC_VECTOR (3 downto 0);
gameSelected : out STD_LOGIC_VECTOR (3 downto 0);
mapped_out : out STD_LOGIC_VECTOR( 7 downto 0 );
mem_state : out STD_LOGIC_VECTOR( 7 downto 0 );
debug_read_data : out STD_LOGIC_VECTOR( 7 downto 0 );
sys_reset : out STD_LOGIC;
cpu_reset : out STD_LOGIC;
active : out STD_LOGIC;
step : in STD_LOGIC;
clk, reset : in STD_LOGIC );
end mem_controller;
architecture Behavioral of mem_controller is
signal s_address : STD_LOGIC_VECTOR (16 downto 0);
signal s_clock : STD_LOGIC;
signal s_we : STD_LOGIC;
signal s_dataIn : STD_LOGIC_VECTOR (7 downto 0);
signal s_dataOut : STD_LOGIC_VECTOR (7 downto 0);
component mem_mod
port( address : in STD_LOGIC_VECTOR (12 downto 0);
clock : in STD_LOGIC;
we : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal s_mem_clock : STD_LOGIC;
signal s_mem_we : STD_LOGIC;
signal s_mem_dataOut : STD_LOGIC_VECTOR (7 downto 0);
component game_rom
port( address : in STD_LOGIC_VECTOR (15 downto 0);
clock : in STD_LOGIC;
we : in STD_LOGIC;
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0));
end component;
signal s_rom_clock : STD_LOGIC;
signal s_rom_we : STD_LOGIC;
signal s_rom_dataOut : STD_LOGIC_VECTOR (7 downto 0);
type memState is ( initA, initB, initC, waiting, ownedWaiting, copy_key_map,
copy_init_low, copy_init_high, copy_read, copy_write,
normMemAccess, memAccess, memClock, memGet,
normMemGet, raiseDone, waitFinish, pad1, pad2 );
signal currentGame : STD_LOGIC_VECTOR (3 downto 0);
signal owner : STD_LOGIC_VECTOR (2 downto 0);
signal current_state, memReturn, copy_return : memState;
signal copy_start : STD_LOGIC_VECTOR (16 downto 0);
signal copy_end : STD_LOGIC_VECTOR (16 downto 0);
signal copy_to : STD_LOGIC_VECTOR (16 downto 0);
signal step_active : STD_LOGIC;
signal init_times : STD_LOGIC_VECTOR (7 downto 0);
begin
MEM : mem_mod
port map ( address => s_address( 12 downto 0 ),
clock => s_mem_clock,
we => s_mem_we,
dataIn => s_dataIn,
dataOut => s_mem_dataOut);
ROM : game_rom
port map ( address => s_address( 15 downto 0 ),
clock => s_rom_clock,
we => s_rom_we,
dataIn => s_dataIn,
dataOut => s_rom_dataOut);
gameSelected <= currentGame;
process( clk, reset )
variable cur_address : STD_LOGIC_VECTOR (11 downto 0);
variable data : STD_LOGIC_VECTOR (7 downto 0);
variable dataA : STD_LOGIC_VECTOR (7 downto 0);
begin
if ( reset = '1' ) then
current_state <= initA;
sys_reset <= '1';
-- cpu_reset <= '1'; -- simulation
cpu_reset <= '0'; -- board
init_times <= x"00";
mapped_out <= x"AA";
active <= '0';
elsif ( rising_edge( clk ) ) then
current_state <= current_state;
case current_state is
when initA =>
mem_state <= x"01";
active <= '1';
done <= "000";
current_state <= initB;
s_address <= "00000000000000000";
s_clock <= '0';
s_we <= '0';
s_dataIn <= "00000000";
s_mem_clock <= '0';
s_mem_we <= '0';
s_rom_clock <= '0';
s_rom_we <= '0';
step_active <= '0';
init_times <= init_times + x"01";
mapped_out <= init_times;
when initB =>
mem_state <= x"02";
currentGame <= gameSelect;
current_state <= copy_init_low;
dataOut <= x"000000";
when copy_init_low =>
mem_state <= x"03";
copy_start <= '1' & x"0000";
copy_end <= '1' & x"01FF";
copy_to <= '1' & x"1000";
copy_return <= copy_key_map;
current_state <= copy_read;
--step_active <= '1'; -- for debugging memory early
when copy_key_map =>
copy_start <= '0' & currentGame & x"080";
copy_end <= '0' & currentGame & x"08A";
copy_to <= '1' & x"1080";
copy_return <= copy_init_high;
current_state <= copy_read;
when copy_init_high =>
mem_state <= x"04";
copy_start <= '0' & currentGame & x"200";
copy_end <= '0' & currentGame & x"FFF";
copy_to <= '1' & x"1200";
copy_return <= initC;
current_state <= copy_read;
--step_active <= '1'; -- for debugging rom early
when copy_read =>
mem_state <= x"05";
s_address <= copy_start;
s_we <= '0';
memReturn <= copy_write;
current_state <= memAccess;
when copy_write =>
mem_state <= x"06";
s_address <= copy_to;
s_dataIn <= s_dataOut;
s_we <= '1';
copy_start <= copy_start + ( '0' & x"0001");
copy_to <= copy_to + ( '0' & x"0001");
current_state <= memAccess;
if( copy_start = copy_end) then
memReturn <= copy_return;
else
memReturn <= copy_read;
end if;
when initC =>
mem_state <= x"07";
owner <= "000";
current_state <= waiting;
sys_reset <= '0';
-- cpu_reset <= '0'; -- simulation
cpu_reset <= '1'; -- board
-- step_active <= '1'; -- for debugging normal memory
when waiting =>
mem_state <= x"08";
if ( valid(0) = '1' ) then
owner <= "001";
current_state <= normMemAccess;
elsif ( valid(1) = '1' ) then
owner <= "010";
current_state <= normMemAccess;
elsif ( valid(2) = '1' ) then
owner <= "100";
current_state <= normMemAccess;
end if;
when ownedWaiting =>
mem_state <= x"09";
if ( ( owner and hold ) = "000" ) then
owner <= "000";
current_state <= waiting;
elsif ( ( owner and valid ) = owner ) then
current_state <= normMemAccess;
end if;
when normMemAccess =>
mem_state <= x"0A";
if ( owner = "001" ) then
s_address <= '1' & "0001" & memAddress( 11 downto 0 );
s_dataIn <= dataIn( 7 downto 0 );
s_we <= write(0);
elsif ( owner = "010" ) then
s_address <= '1' & "0001" & memAddress( 23 downto 12 );
s_dataIn <= dataIn( 15 downto 8 );
s_we <= write(1);
elsif ( owner = "100" ) then
s_address <= '1' & "0001" & memAddress( 35 downto 24 );
s_dataIn <= dataIn( 23 downto 16 );
s_we <= write(2);
end if;
memReturn <= normMemGet;
current_state <= memAccess;
when memAccess =>
mem_state <= x"0B";
if( s_address(16) = '1' ) then
s_mem_clock <= '0';
s_mem_we <= s_we;
if( ( s_address( 15 downto 0 ) = x"11FF" ) and ( s_we = '1' ) ) then
mapped_out <= s_dataIn;
end if;
else
s_rom_clock <= '0';
s_rom_we <= s_we;
end if;
current_state <= memClock;
when memClock =>
mem_state <= x"0C";
if( s_address(16) = '1' ) then
s_mem_clock <= '1';
else
s_rom_clock <= '1';
end if;
current_state <= memGet;
when memGet =>
mem_state <= x"0D";
if( s_address(16) = '1' ) then
s_dataOut <= s_mem_dataOut;
debug_read_data <= s_mem_dataOut;
else
s_dataOut <= s_rom_dataOut;
debug_read_data <= s_rom_dataOut;
end if;
if( step_active = '1' ) then
current_state <= pad1;
else
current_state <= memReturn;
end if;
when pad1 =>
if( step_active = '1' and step = '0' ) then
current_state <= pad1;
else
current_state <= pad2;
end if;
when pad2 =>
if( step_active = '1' and step = '1' ) then
current_state <= pad2;
else
current_state <= memReturn;
end if;
when normMemGet =>
mem_state <= x"0E";
if ( owner = "001" ) then
dataOut( 7 downto 0 ) <= s_dataOut;
elsif ( owner = "010" ) then
dataOut( 15 downto 8 ) <= s_dataOut;
elsif ( owner = "100" ) then
dataOut( 23 downto 16 ) <= s_dataOut;
end if;
current_state <= raiseDone;
when raiseDone =>
mem_state <= x"0F";
done <= owner;
current_state <= waitFinish;
when waitFinish =>
mem_state <= x"10";
if ( ( owner and valid ) = "000") then
done <= "000";
if ( ( owner and hold ) = owner ) then
current_state <= ownedWaiting;
else
owner <= "000";
current_state <= waiting;
end if;
end if;
when others =>
mapped_out <= x"0F";
end case;
end if;
end process;
end Behavioral;
| mit | 0a45c2dd91481d99aa149f358aa373f3 | 0.395631 | 4.633792 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_sim_netlist.vhdl | 1 | 29,735 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:40:17 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_sim_netlist.vhdl
-- Design : zynq_design_1_auto_pc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter";
attribute P_AXI3 : integer;
attribute P_AXI3 of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_arready\ : STD_LOGIC;
signal \^m_axi_awready\ : STD_LOGIC;
signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_buser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_rlast\ : STD_LOGIC;
signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_rvalid\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_aruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_arvalid\ : STD_LOGIC;
signal \^s_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_awburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_awlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_awvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
signal \^s_axi_rready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC;
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_arready\ <= m_axi_arready;
\^m_axi_awready\ <= m_axi_awready;
\^m_axi_bid\(11 downto 0) <= m_axi_bid(11 downto 0);
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_buser\(0) <= m_axi_buser(0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^m_axi_rdata\(31 downto 0) <= m_axi_rdata(31 downto 0);
\^m_axi_rid\(11 downto 0) <= m_axi_rid(11 downto 0);
\^m_axi_rlast\ <= m_axi_rlast;
\^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0);
\^m_axi_ruser\(0) <= m_axi_ruser(0);
\^m_axi_rvalid\ <= m_axi_rvalid;
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_araddr\(31 downto 0) <= s_axi_araddr(31 downto 0);
\^s_axi_arburst\(1 downto 0) <= s_axi_arburst(1 downto 0);
\^s_axi_arcache\(3 downto 0) <= s_axi_arcache(3 downto 0);
\^s_axi_arid\(11 downto 0) <= s_axi_arid(11 downto 0);
\^s_axi_arlen\(3 downto 0) <= s_axi_arlen(3 downto 0);
\^s_axi_arlock\(0) <= s_axi_arlock(0);
\^s_axi_arprot\(2 downto 0) <= s_axi_arprot(2 downto 0);
\^s_axi_arqos\(3 downto 0) <= s_axi_arqos(3 downto 0);
\^s_axi_arsize\(2 downto 0) <= s_axi_arsize(2 downto 0);
\^s_axi_aruser\(0) <= s_axi_aruser(0);
\^s_axi_arvalid\ <= s_axi_arvalid;
\^s_axi_awaddr\(31 downto 0) <= s_axi_awaddr(31 downto 0);
\^s_axi_awburst\(1 downto 0) <= s_axi_awburst(1 downto 0);
\^s_axi_awcache\(3 downto 0) <= s_axi_awcache(3 downto 0);
\^s_axi_awid\(11 downto 0) <= s_axi_awid(11 downto 0);
\^s_axi_awlen\(3 downto 0) <= s_axi_awlen(3 downto 0);
\^s_axi_awlock\(0) <= s_axi_awlock(0);
\^s_axi_awprot\(2 downto 0) <= s_axi_awprot(2 downto 0);
\^s_axi_awqos\(3 downto 0) <= s_axi_awqos(3 downto 0);
\^s_axi_awsize\(2 downto 0) <= s_axi_awsize(2 downto 0);
\^s_axi_awuser\(0) <= s_axi_awuser(0);
\^s_axi_awvalid\ <= s_axi_awvalid;
\^s_axi_bready\ <= s_axi_bready;
\^s_axi_rready\ <= s_axi_rready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\ <= s_axi_wlast;
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wuser\(0) <= s_axi_wuser(0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_araddr(31 downto 0) <= \^s_axi_araddr\(31 downto 0);
m_axi_arburst(1 downto 0) <= \^s_axi_arburst\(1 downto 0);
m_axi_arcache(3 downto 0) <= \^s_axi_arcache\(3 downto 0);
m_axi_arid(11 downto 0) <= \^s_axi_arid\(11 downto 0);
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3 downto 0) <= \^s_axi_arlen\(3 downto 0);
m_axi_arlock(0) <= \^s_axi_arlock\(0);
m_axi_arprot(2 downto 0) <= \^s_axi_arprot\(2 downto 0);
m_axi_arqos(3 downto 0) <= \^s_axi_arqos\(3 downto 0);
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2 downto 0) <= \^s_axi_arsize\(2 downto 0);
m_axi_aruser(0) <= \^s_axi_aruser\(0);
m_axi_arvalid <= \^s_axi_arvalid\;
m_axi_awaddr(31 downto 0) <= \^s_axi_awaddr\(31 downto 0);
m_axi_awburst(1 downto 0) <= \^s_axi_awburst\(1 downto 0);
m_axi_awcache(3 downto 0) <= \^s_axi_awcache\(3 downto 0);
m_axi_awid(11 downto 0) <= \^s_axi_awid\(11 downto 0);
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3 downto 0) <= \^s_axi_awlen\(3 downto 0);
m_axi_awlock(0) <= \^s_axi_awlock\(0);
m_axi_awprot(2 downto 0) <= \^s_axi_awprot\(2 downto 0);
m_axi_awqos(3 downto 0) <= \^s_axi_awqos\(3 downto 0);
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2 downto 0) <= \^s_axi_awsize\(2 downto 0);
m_axi_awuser(0) <= \^s_axi_awuser\(0);
m_axi_awvalid <= \^s_axi_awvalid\;
m_axi_bready <= \^s_axi_bready\;
m_axi_rready <= \^s_axi_rready\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \^s_axi_wlast\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \^s_axi_wuser\(0);
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_arready <= \^m_axi_arready\;
s_axi_awready <= \^m_axi_awready\;
s_axi_bid(11 downto 0) <= \^m_axi_bid\(11 downto 0);
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_buser(0) <= \^m_axi_buser\(0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rdata(31 downto 0) <= \^m_axi_rdata\(31 downto 0);
s_axi_rid(11 downto 0) <= \^m_axi_rid\(11 downto 0);
s_axi_rlast <= \^m_axi_rlast\;
s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0);
s_axi_ruser(0) <= \^m_axi_ruser\(0);
s_axi_rvalid <= \^m_axi_rvalid\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_auto_pc_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_auto_pc_1 : entity is "zynq_design_1_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_auto_pc_1 : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end zynq_design_1_auto_pc_1;
architecture STRUCTURE of zynq_design_1_auto_pc_1 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(11 downto 0) => m_axi_arid(11 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(11 downto 0) => m_axi_awid(11 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => m_axi_bid(11 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 5d2f61896d8ca8cda156a87e3313360a | 0.640995 | 2.884653 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/iu3.vhd | 1 | 131,748 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: iu3
-- File: iu3.vhd
-- Author: Jiri Gaisler, Edvin Catovic, Gaisler Research
-- Description: LEON3 7-stage integer pipline
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.sparc.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libfpu.all;
use gaisler.arith.all;
-- pragma translate_off
use grlib.sparc_disas.all;
-- pragma translate_on
entity iu3 is
generic (
nwin : integer range 2 to 32 := 8;
isets : integer range 1 to 4 := 1;
dsets : integer range 1 to 4 := 1;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp, mac : integer range 0 to 1 := 0;
dsu : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
index : integer range 0 to 15:= 0;
lddel : integer range 1 to 2 := 2;
irfwt : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0; -- trace buf size in kB (0 - no trace buffer)
pwd : integer range 0 to 2 := 0; -- power-down
svt : integer range 0 to 1 := 0; -- single-vector trapping
rstaddr : integer := 16#00000#; -- reset vector MSB address
smp : integer range 0 to 15 := 0; -- support SMP systems
fabtech : integer range 0 to NTECH := 0;
clk2x : integer := 0;
bp : integer range 0 to 2 := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : in std_ulogic;
ici : out icache_in_type;
ico : in icache_out_type;
dci : out dcache_in_type;
dco : in dcache_out_type;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
muli : out mul32_in_type;
mulo : in mul32_out_type;
divi : out div32_in_type;
divo : in div32_out_type;
fpo : in fpc_out_type;
fpi : out fpc_in_type;
cpo : in fpc_out_type;
cpi : out fpc_in_type;
tbo : in tracebuf_out_type;
tbi : out tracebuf_in_type;
sclk : in std_ulogic
);
attribute sync_set_reset of rstn : signal is "true";
end;
architecture rtl of iu3 is
constant ISETMSB : integer := log2x(isets)-1;
constant DSETMSB : integer := log2x(dsets)-1;
constant RFBITS : integer range 6 to 10 := log2(NWIN+1) + 4;
constant NWINLOG2 : integer range 1 to 5 := log2(NWIN);
constant CWPOPT : boolean := (NWIN = (2**NWINLOG2));
constant CWPMIN : std_logic_vector(NWINLOG2-1 downto 0) := (others => '0');
constant CWPMAX : std_logic_vector(NWINLOG2-1 downto 0) :=
conv_std_logic_vector(NWIN-1, NWINLOG2);
constant FPEN : boolean := (fpu /= 0);
constant CPEN : boolean := (cp = 1);
constant MULEN : boolean := (v8 /= 0);
constant MULTYPE: integer := (v8 / 16);
constant DIVEN : boolean := (v8 /= 0);
constant MACEN : boolean := (mac = 1);
constant MACPIPE: boolean := (mac = 1) and (v8/2 = 1);
constant IMPL : integer := 15;
constant VER : integer := 3;
constant DBGUNIT : boolean := (dsu = 1);
constant TRACEBUF : boolean := (tbuf /= 0);
constant TBUFBITS : integer := 10 + log2(tbuf) - 4;
constant PWRD1 : boolean := false; --(pwd = 1) and not (index /= 0);
constant PWRD2 : boolean := (pwd /= 0); --(pwd = 2) or (index /= 0);
constant RS1OPT : boolean := (is_fpga(FABTECH) /= 0);
constant DYNRST : boolean := (rstaddr = 16#FFFFF#);
constant CASAEN : boolean := (notag = 0) and (lddel = 1);
signal BPRED : std_logic;
subtype word is std_logic_vector(31 downto 0);
subtype pctype is std_logic_vector(31 downto PCLOW);
subtype rfatype is std_logic_vector(RFBITS-1 downto 0);
subtype cwptype is std_logic_vector(NWINLOG2-1 downto 0);
type icdtype is array (0 to isets-1) of word;
type dcdtype is array (0 to dsets-1) of word;
type dc_in_type is record
signed, enaddr, read, write, lock, dsuen : std_ulogic;
size : std_logic_vector(1 downto 0);
asi : std_logic_vector(7 downto 0);
end record;
type pipeline_ctrl_type is record
pc : pctype;
inst : word;
cnt : std_logic_vector(1 downto 0);
rd : rfatype;
tt : std_logic_vector(5 downto 0);
trap : std_ulogic;
annul : std_ulogic;
wreg : std_ulogic;
wicc : std_ulogic;
wy : std_ulogic;
ld : std_ulogic;
pv : std_ulogic;
rett : std_ulogic;
end record;
type fetch_reg_type is record
pc : pctype;
branch : std_ulogic;
end record;
type decode_reg_type is record
pc : pctype;
inst : icdtype;
cwp : cwptype;
set : std_logic_vector(ISETMSB downto 0);
mexc : std_ulogic;
cnt : std_logic_vector(1 downto 0);
pv : std_ulogic;
annul : std_ulogic;
inull : std_ulogic;
step : std_ulogic;
divrdy: std_ulogic;
end record;
type regacc_reg_type is record
ctrl : pipeline_ctrl_type;
rs1 : std_logic_vector(4 downto 0);
rfa1, rfa2 : rfatype;
rsel1, rsel2 : std_logic_vector(2 downto 0);
rfe1, rfe2 : std_ulogic;
cwp : cwptype;
imm : word;
ldcheck1 : std_ulogic;
ldcheck2 : std_ulogic;
ldchkra : std_ulogic;
ldchkex : std_ulogic;
su : std_ulogic;
et : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
jmpl : std_ulogic;
step : std_ulogic;
mulstart : std_ulogic;
divstart : std_ulogic;
bp, nobp : std_ulogic;
end record;
type execute_reg_type is record
ctrl : pipeline_ctrl_type;
op1 : word;
op2 : word;
aluop : std_logic_vector(2 downto 0); -- Alu operation
alusel : std_logic_vector(1 downto 0); -- Alu result select
aluadd : std_ulogic;
alucin : std_ulogic;
ldbp1, ldbp2 : std_ulogic;
invop2 : std_ulogic;
shcnt : std_logic_vector(4 downto 0); -- shift count
sari : std_ulogic; -- shift msb
shleft : std_ulogic; -- shift left/right
ymsb : std_ulogic; -- shift left/right
rd : std_logic_vector(4 downto 0);
jmpl : std_ulogic;
su : std_ulogic;
et : std_ulogic;
cwp : cwptype;
icc : std_logic_vector(3 downto 0);
mulstep: std_ulogic;
mul : std_ulogic;
mac : std_ulogic;
bp : std_ulogic;
rfe1, rfe2 : std_ulogic;
end record;
type memory_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector(3 downto 0);
nalign : std_ulogic;
dci : dc_in_type;
werr : std_ulogic;
wcwp : std_ulogic;
irqen : std_ulogic;
irqen2 : std_ulogic;
mac : std_ulogic;
divz : std_ulogic;
su : std_ulogic;
mul : std_ulogic;
casa : std_ulogic;
casaz : std_ulogic;
end record;
type exception_state is (run, trap, dsu1, dsu2);
type exception_reg_type is record
ctrl : pipeline_ctrl_type;
result : word;
y : word;
icc : std_logic_vector( 3 downto 0);
annul_all : std_ulogic;
data : dcdtype;
set : std_logic_vector(DSETMSB downto 0);
mexc : std_ulogic;
dci : dc_in_type;
laddr : std_logic_vector(1 downto 0);
rstate : exception_state;
npc : std_logic_vector(2 downto 0);
intack : std_ulogic;
ipend : std_ulogic;
mac : std_ulogic;
debug : std_ulogic;
nerror : std_ulogic;
ipmask : std_ulogic;
end record;
type dsu_registers is record
tt : std_logic_vector(7 downto 0);
err : std_ulogic;
tbufcnt : std_logic_vector(TBUFBITS-1 downto 0);
asi : std_logic_vector(7 downto 0);
crdy : std_logic_vector(2 downto 1); -- diag cache access ready
end record;
type irestart_register is record
addr : pctype;
pwd : std_ulogic;
end record;
type pwd_register_type is record
pwd : std_ulogic;
error : std_ulogic;
end record;
type special_register_type is record
cwp : cwptype; -- current window pointer
icc : std_logic_vector(3 downto 0); -- integer condition codes
tt : std_logic_vector(7 downto 0); -- trap type
tba : std_logic_vector(19 downto 0); -- trap base address
wim : std_logic_vector(NWIN-1 downto 0); -- window invalid mask
pil : std_logic_vector(3 downto 0); -- processor interrupt level
ec : std_ulogic; -- enable CP
ef : std_ulogic; -- enable FP
ps : std_ulogic; -- previous supervisor flag
s : std_ulogic; -- supervisor flag
et : std_ulogic; -- enable traps
y : word;
asr18 : word;
svt : std_ulogic; -- enable traps
dwt : std_ulogic; -- disable write error trap
dbp : std_ulogic; -- disable branch prediction
end record;
type write_reg_type is record
s : special_register_type;
result : word;
wa : rfatype;
wreg : std_ulogic;
except : std_ulogic;
end record;
type registers is record
f : fetch_reg_type;
d : decode_reg_type;
a : regacc_reg_type;
e : execute_reg_type;
m : memory_reg_type;
x : exception_reg_type;
w : write_reg_type;
end record;
type exception_type is record
pri : std_ulogic;
ill : std_ulogic;
fpdis : std_ulogic;
cpdis : std_ulogic;
wovf : std_ulogic;
wunf : std_ulogic;
ticc : std_ulogic;
end record;
type watchpoint_register is record
addr : std_logic_vector(31 downto 2); -- watchpoint address
mask : std_logic_vector(31 downto 2); -- watchpoint mask
exec : std_ulogic; -- trap on instruction
load : std_ulogic; -- trap on load
store : std_ulogic; -- trap on store
end record;
type watchpoint_registers is array (0 to 3) of watchpoint_register;
function dbgexc(r : registers; dbgi : l3_debug_in_type; trap : std_ulogic; tt : std_logic_vector(7 downto 0)) return std_ulogic is
variable dmode : std_ulogic;
begin
dmode := '0';
if (not r.x.ctrl.annul and trap) = '1' then
if (((tt = "00" & TT_WATCH) and (dbgi.bwatch = '1')) or
((dbgi.bsoft = '1') and (tt = "10000001")) or
(dbgi.btrapa = '1') or
((dbgi.btrape = '1') and not ((tt(5 downto 0) = TT_PRIV) or
(tt(5 downto 0) = TT_FPDIS) or (tt(5 downto 0) = TT_WINOF) or
(tt(5 downto 0) = TT_WINUF) or (tt(5 downto 4) = "01") or (tt(7) = '1'))) or
(((not r.w.s.et) and dbgi.berror) = '1')) then
dmode := '1';
end if;
end if;
return(dmode);
end;
function dbgerr(r : registers; dbgi : l3_debug_in_type;
tt : std_logic_vector(7 downto 0))
return std_ulogic is
variable err : std_ulogic;
begin
err := not r.w.s.et;
if (((dbgi.dbreak = '1') and (tt = ("00" & TT_WATCH))) or
((dbgi.bsoft = '1') and (tt = ("10000001")))) then
err := '0';
end if;
return(err);
end;
procedure diagwr(r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
dbg : in l3_debug_in_type;
wpr : in watchpoint_registers;
s : out special_register_type;
vwpr : out watchpoint_registers;
asi : out std_logic_vector(7 downto 0);
pc, npc : out pctype;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
wr : out std_ulogic;
addr : out std_logic_vector(9 downto 0);
data : out word;
fpcwr : out std_ulogic) is
variable i : integer range 0 to 3;
begin
s := r.w.s; pc := r.f.pc; npc := ir.addr; wr := '0';
vwpr := wpr; asi := dsur.asi; addr := (others => '0');
data := dbg.ddata;
tbufcnt := dsur.tbufcnt; fpcwr := '0';
if (dbg.dsuen and dbg.denable and dbg.dwrite) = '1' then
case dbg.daddr(23 downto 20) is
when "0001" =>
if (dbg.daddr(16) = '1') and TRACEBUF then -- trace buffer control reg
tbufcnt := dbg.ddata(TBUFBITS-1 downto 0);
end if;
when "0011" => -- IU reg file
if dbg.daddr(12) = '0' then
wr := '1';
addr := (others => '0');
addr(RFBITS-1 downto 0) := dbg.daddr(RFBITS+1 downto 2);
else -- FPC
fpcwr := '1';
end if;
when "0100" => -- IU special registers
case dbg.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbg.daddr(5 downto 2) is
when "0000" => -- Y
s.y := dbg.ddata;
when "0001" => -- PSR
s.cwp := dbg.ddata(NWINLOG2-1 downto 0);
s.icc := dbg.ddata(23 downto 20);
s.ec := dbg.ddata(13);
if FPEN then s.ef := dbg.ddata(12); end if;
s.pil := dbg.ddata(11 downto 8);
s.s := dbg.ddata(7);
s.ps := dbg.ddata(6);
s.et := dbg.ddata(5);
when "0010" => -- WIM
s.wim := dbg.ddata(NWIN-1 downto 0);
when "0011" => -- TBR
s.tba := dbg.ddata(31 downto 12);
s.tt := dbg.ddata(11 downto 4);
when "0100" => -- PC
pc := dbg.ddata(31 downto PCLOW);
when "0101" => -- NPC
npc := dbg.ddata(31 downto PCLOW);
when "0110" => --FSR
fpcwr := '1';
when "0111" => --CFSR
when "1001" => -- ASI reg
asi := dbg.ddata(7 downto 0);
when others =>
end case;
when "01" => -- ASR16 - ASR31
case dbg.daddr(5 downto 2) is
when "0001" => -- %ASR17
if bp = 2 then s.dbp := dbg.ddata(27); end if;
s.dwt := dbg.ddata(14);
s.svt := dbg.ddata(13);
when "0010" => -- %ASR18
if MACEN then s.asr18 := dbg.ddata; end if;
when "1000" => -- %ASR24 - %ASR31
vwpr(0).addr := dbg.ddata(31 downto 2);
vwpr(0).exec := dbg.ddata(0);
when "1001" =>
vwpr(0).mask := dbg.ddata(31 downto 2);
vwpr(0).load := dbg.ddata(1);
vwpr(0).store := dbg.ddata(0);
when "1010" =>
vwpr(1).addr := dbg.ddata(31 downto 2);
vwpr(1).exec := dbg.ddata(0);
when "1011" =>
vwpr(1).mask := dbg.ddata(31 downto 2);
vwpr(1).load := dbg.ddata(1);
vwpr(1).store := dbg.ddata(0);
when "1100" =>
vwpr(2).addr := dbg.ddata(31 downto 2);
vwpr(2).exec := dbg.ddata(0);
when "1101" =>
vwpr(2).mask := dbg.ddata(31 downto 2);
vwpr(2).load := dbg.ddata(1);
vwpr(2).store := dbg.ddata(0);
when "1110" =>
vwpr(3).addr := dbg.ddata(31 downto 2);
vwpr(3).exec := dbg.ddata(0);
when "1111" => --
vwpr(3).mask := dbg.ddata(31 downto 2);
vwpr(3).load := dbg.ddata(1);
vwpr(3).store := dbg.ddata(0);
when others => --
end case;
-- disabled due to bug in XST
-- i := conv_integer(dbg.daddr(4 downto 3));
-- if dbg.daddr(2) = '0' then
-- vwpr(i).addr := dbg.ddata(31 downto 2);
-- vwpr(i).exec := dbg.ddata(0);
-- else
-- vwpr(i).mask := dbg.ddata(31 downto 2);
-- vwpr(i).load := dbg.ddata(1);
-- vwpr(i).store := dbg.ddata(0);
-- end if;
when others =>
end case;
when others =>
end case;
end if;
end;
function asr17_gen ( r : in registers) return word is
variable asr17 : word;
variable fpu2 : integer range 0 to 3;
begin
asr17 := zero32;
asr17(31 downto 28) := conv_std_logic_vector(index, 4);
if bp = 2 then asr17(27) := r.w.s.dbp; end if;
if notag = 0 then asr17(26) := '1'; end if; -- CASA and tagged arith
if (clk2x > 8) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x-8, 2);
asr17(17) := '1';
elsif (clk2x > 0) then
asr17(16 downto 15) := conv_std_logic_vector(clk2x, 2);
end if;
asr17(14) := r.w.s.dwt;
if svt = 1 then asr17(13) := r.w.s.svt; end if;
if lddel = 2 then asr17(12) := '1'; end if;
if (fpu > 0) and (fpu < 8) then fpu2 := 1;
elsif (fpu >= 8) and (fpu < 15) then fpu2 := 3;
elsif fpu = 15 then fpu2 := 2;
else fpu2 := 0; end if;
asr17(11 downto 10) := conv_std_logic_vector(fpu2, 2);
if mac = 1 then asr17(9) := '1'; end if;
if v8 /= 0 then asr17(8) := '1'; end if;
asr17(7 downto 5) := conv_std_logic_vector(nwp, 3);
asr17(4 downto 0) := conv_std_logic_vector(nwin-1, 5);
return(asr17);
end;
procedure diagread(dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
ir : in irestart_register;
wpr : in watchpoint_registers;
dco : in dcache_out_type;
tbufo : in tracebuf_out_type;
data : out word) is
variable cwp : std_logic_vector(4 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
data := (others => '0'); cwp := (others => '0');
cwp(NWINLOG2-1 downto 0) := r.w.s.cwp;
case dbgi.daddr(22 downto 20) is
when "001" => -- trace buffer
if TRACEBUF then
if dbgi.daddr(16) = '1' then -- trace buffer control reg
data(TBUFBITS-1 downto 0) := dsur.tbufcnt;
else
case dbgi.daddr(3 downto 2) is
when "00" => data := tbufo.data(127 downto 96);
when "01" => data := tbufo.data(95 downto 64);
when "10" => data := tbufo.data(63 downto 32);
when others => data := tbufo.data(31 downto 0);
end case;
end if;
end if;
when "011" => -- IU reg file
if dbgi.daddr(12) = '0' then
if dbgi.daddr(11) = '0' then
data := rfo.data1(31 downto 0);
else data := rfo.data2(31 downto 0); end if;
else
data := fpo.dbg.data;
end if;
when "100" => -- IU regs
case dbgi.daddr(7 downto 6) is
when "00" => -- IU regs Y - TBUF ctrl reg
case dbgi.daddr(5 downto 2) is
when "0000" =>
data := r.w.s.y;
when "0001" =>
data := conv_std_logic_vector(IMPL, 4) & conv_std_logic_vector(VER, 4) &
r.w.s.icc & "000000" & r.w.s.ec & r.w.s.ef & r.w.s.pil &
r.w.s.s & r.w.s.ps & r.w.s.et & cwp;
when "0010" =>
data(NWIN-1 downto 0) := r.w.s.wim;
when "0011" =>
data := r.w.s.tba & r.w.s.tt & "0000";
when "0100" =>
data(31 downto PCLOW) := r.f.pc;
when "0101" =>
data(31 downto PCLOW) := ir.addr;
when "0110" => -- FSR
data := fpo.dbg.data;
when "0111" => -- CPSR
when "1000" => -- TT reg
data(12 downto 4) := dsur.err & dsur.tt;
when "1001" => -- ASI reg
data(7 downto 0) := dsur.asi;
when others =>
end case;
when "01" =>
if dbgi.daddr(5) = '0' then
if dbgi.daddr(4 downto 2) = "001" then -- %ASR17
data := asr17_gen(r);
elsif MACEN and dbgi.daddr(4 downto 2) = "010" then -- %ASR18
data := r.w.s.asr18;
end if;
else -- %ASR24 - %ASR31
i := conv_integer(dbgi.daddr(4 downto 3)); --
if dbgi.daddr(2) = '0' then
data(31 downto 2) := wpr(i).addr;
data(0) := wpr(i).exec;
else
data(31 downto 2) := wpr(i).mask;
data(1) := wpr(i).load;
data(0) := wpr(i).store;
end if;
end if;
when others =>
end case;
when "111" =>
data := r.x.data(conv_integer(r.x.set));
when others =>
end case;
end;
procedure itrace(r : in registers;
dsur : in dsu_registers;
vdsu : in dsu_registers;
res : in word;
exc : in std_ulogic;
dbgi : in l3_debug_in_type;
error : in std_ulogic;
trap : in std_ulogic;
tbufcnt : out std_logic_vector(TBUFBITS-1 downto 0);
di : out tracebuf_in_type;
ierr : in std_ulogic;
derr : in std_ulogic
) is
variable meminst : std_ulogic;
begin
di.addr := (others => '0'); di.data := (others => '0');
di.enable := '0'; di.write := (others => '0');
tbufcnt := vdsu.tbufcnt;
meminst := r.x.ctrl.inst(31) and r.x.ctrl.inst(30);
if TRACEBUF then
di.addr(TBUFBITS-1 downto 0) := dsur.tbufcnt;
di.data(127) := '0';
di.data(126) := not r.x.ctrl.pv;
di.data(125 downto 96) := dbgi.timer(29 downto 0);
di.data(95 downto 64) := res;
di.data(63 downto 34) := r.x.ctrl.pc(31 downto 2);
di.data(33) := trap;
di.data(32) := error;
di.data(31 downto 0) := r.x.ctrl.inst;
if (dbgi.tenable = '0') or (r.x.rstate = dsu2) then
if ((dbgi.dsuen and dbgi.denable) = '1') and (dbgi.daddr(23 downto 20) & dbgi.daddr(16) = "00010") then
di.enable := '1';
di.addr(TBUFBITS-1 downto 0) := dbgi.daddr(TBUFBITS-1+4 downto 4);
if dbgi.dwrite = '1' then
case dbgi.daddr(3 downto 2) is
when "00" => di.write(3) := '1';
when "01" => di.write(2) := '1';
when "10" => di.write(1) := '1';
when others => di.write(0) := '1';
end case;
di.data := dbgi.ddata & dbgi.ddata & dbgi.ddata & dbgi.ddata;
end if;
end if;
elsif (not r.x.ctrl.annul and (r.x.ctrl.pv or meminst) and not r.x.debug) = '1' then
di.enable := '1'; di.write := (others => '1');
tbufcnt := dsur.tbufcnt + 1;
end if;
di.diag := dco.testen & dco.scanen & "00";
if dco.scanen = '1' then di.enable := '0'; end if;
end if;
end;
procedure dbg_cache(holdn : in std_ulogic;
dbgi : in l3_debug_in_type;
r : in registers;
dsur : in dsu_registers;
mresult : in word;
dci : in dc_in_type;
mresult2 : out word;
dci2 : out dc_in_type
) is
begin
mresult2 := mresult; dci2 := dci; dci2.dsuen := '0';
if DBGUNIT then
if (r.x.rstate = dsu2)
then
dci2.asi := dsur.asi;
if (dbgi.daddr(22 downto 20) = "111") and (dbgi.dsuen = '1') then
dci2.dsuen := (dbgi.denable or r.m.dci.dsuen) and not dsur.crdy(2);
dci2.enaddr := dbgi.denable;
dci2.size := "10"; dci2.read := '1'; dci2.write := '0';
if (dbgi.denable and not r.m.dci.enaddr) = '1' then
mresult2 := (others => '0'); mresult2(19 downto 2) := dbgi.daddr(19 downto 2);
else
mresult2 := dbgi.ddata;
end if;
if dbgi.dwrite = '1' then
dci2.read := '0'; dci2.write := '1';
end if;
end if;
end if;
end if;
end;
procedure fpexack(r : in registers; fpexc : out std_ulogic) is
begin
fpexc := '0';
if FPEN then
if r.x.ctrl.tt = TT_FPEXC then fpexc := '1'; end if;
end if;
end;
procedure diagrdy(denable : in std_ulogic;
dsur : in dsu_registers;
dci : in dc_in_type;
mds : in std_ulogic;
ico : in icache_out_type;
crdy : out std_logic_vector(2 downto 1)) is
begin
crdy := dsur.crdy(1) & '0';
if dci.dsuen = '1' then
case dsur.asi(4 downto 0) is
when ASI_ITAG | ASI_IDATA | ASI_UINST | ASI_SINST =>
crdy(2) := ico.diagrdy and not dsur.crdy(2);
when ASI_DTAG | ASI_MMUSNOOP_DTAG | ASI_DDATA | ASI_UDATA | ASI_SDATA =>
crdy(1) := not denable and dci.enaddr and not dsur.crdy(1);
when others =>
crdy(2) := dci.enaddr and denable;
end case;
end if;
end;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant dc_in_res : dc_in_type := (
signed => '0',
enaddr => '0',
read => '0',
write => '0',
lock => '0',
dsuen => '0',
size => (others => '0'),
asi => (others => '0'));
constant pipeline_ctrl_res : pipeline_ctrl_type := (
pc => (others => '0'),
inst => (others => '0'),
cnt => (others => '0'),
rd => (others => '0'),
tt => (others => '0'),
trap => '0',
annul => '1',
wreg => '0',
wicc => '0',
wy => '0',
ld => '0',
pv => '0',
rett => '0');
constant fpc_res : pctype := conv_std_logic_vector(rstaddr, 20) & zero32(11 downto PCLOW);
constant fetch_reg_res : fetch_reg_type := (
pc => fpc_res, -- Needs special handling
branch => '0'
);
constant decode_reg_res : decode_reg_type := (
pc => (others => '0'),
inst => (others => (others => '0')),
cwp => (others => '0'),
set => (others => '0'),
mexc => '0',
cnt => (others => '0'),
pv => '0',
annul => '1',
inull => '0',
step => '0',
divrdy => '0'
);
constant regacc_reg_res : regacc_reg_type := (
ctrl => pipeline_ctrl_res,
rs1 => (others => '0'),
rfa1 => (others => '0'),
rfa2 => (others => '0'),
rsel1 => (others => '0'),
rsel2 => (others => '0'),
rfe1 => '0',
rfe2 => '0',
cwp => (others => '0'),
imm => (others => '0'),
ldcheck1 => '0',
ldcheck2 => '0',
ldchkra => '1',
ldchkex => '1',
su => '1',
et => '0',
wovf => '0',
wunf => '0',
ticc => '0',
jmpl => '0',
step => '0',
mulstart => '0',
divstart => '0',
bp => '0',
nobp => '0'
);
constant execute_reg_res : execute_reg_type := (
ctrl => pipeline_ctrl_res,
op1 => (others => '0'),
op2 => (others => '0'),
aluop => (others => '0'),
alusel => "11",
aluadd => '1',
alucin => '0',
ldbp1 => '0',
ldbp2 => '0',
invop2 => '0',
shcnt => (others => '0'),
sari => '0',
shleft => '0',
ymsb => '0',
rd => (others => '0'),
jmpl => '0',
su => '0',
et => '0',
cwp => (others => '0'),
icc => (others => '0'),
mulstep => '0',
mul => '0',
mac => '0',
bp => '0',
rfe1 => '0',
rfe2 => '0'
);
constant memory_reg_res : memory_reg_type := (
ctrl => pipeline_ctrl_res,
result => (others => '0'),
y => (others => '0'),
icc => (others => '0'),
nalign => '0',
dci => dc_in_res,
werr => '0',
wcwp => '0',
irqen => '0',
irqen2 => '0',
mac => '0',
divz => '0',
su => '0',
mul => '0',
casa => '0',
casaz => '0'
);
function xnpc_res return std_logic_vector is
begin
if v8 /= 0 then return "100"; end if;
return "011";
end function xnpc_res;
constant exception_reg_res : exception_reg_type := (
ctrl => pipeline_ctrl_res,
result => (others => '0'),
y => (others => '0'),
icc => (others => '0'),
annul_all => '1',
data => (others => (others => '0')),
set => (others => '0'),
mexc => '0',
dci => dc_in_res,
laddr => (others => '0'),
rstate => run, -- Has special handling
npc => xnpc_res,
intack => '0',
ipend => '0',
mac => '0',
debug => '0', -- Has special handling
nerror => '0',
ipmask => '0'
);
constant DRES : dsu_registers := (
tt => (others => '0'),
err => '0',
tbufcnt => (others => '0'),
asi => (others => '0'),
crdy => (others => '0')
);
constant IRES : irestart_register := (
addr => (others => '0'), pwd => '0'
);
constant PRES : pwd_register_type := (
pwd => '0', -- Needs special handling
error => '0'
);
--constant special_register_res : special_register_type := (
-- cwp => zero32(NWINLOG2-1 downto 0),
-- icc => (others => '0'),
-- tt => (others => '0'),
-- tba => fpc_res(31 downto 12),
-- wim => (others => '0'),
-- pil => (others => '0'),
-- ec => '0',
-- ef => '0',
-- ps => '1',
-- s => '1',
-- et => '0',
-- y => (others => '0'),
-- asr18 => (others => '0'),
-- svt => '0',
-- dwt => '0',
-- dbp => '0'
-- );
--XST workaround:
function special_register_res return special_register_type is
variable s : special_register_type;
begin
s.cwp := zero32(NWINLOG2-1 downto 0);
s.icc := (others => '0');
s.tt := (others => '0');
s.tba := fpc_res(31 downto 12);
s.wim := (others => '0');
s.pil := (others => '0');
s.ec := '0';
s.ef := '0';
s.ps := '1';
s.s := '1';
s.et := '0';
s.y := (others => '0');
s.asr18 := (others => '0');
s.svt := '0';
s.dwt := '0';
s.dbp := '0';
return s;
end function special_register_res;
--constant write_reg_res : write_reg_type := (
-- s => special_register_res,
-- result => (others => '0'),
-- wa => (others => '0'),
-- wreg => '0',
-- except => '0'
-- );
-- XST workaround:
function write_reg_res return write_reg_type is
variable w : write_reg_type;
begin
w.s := special_register_res;
w.result := (others => '0');
w.wa := (others => '0');
w.wreg := '0';
w.except := '0';
return w;
end function write_reg_res;
constant RRES : registers := (
f => fetch_reg_res,
d => decode_reg_res,
a => regacc_reg_res,
e => execute_reg_res,
m => memory_reg_res,
x => exception_reg_res,
w => write_reg_res
);
constant exception_res : exception_type := (
pri => '0',
ill => '0',
fpdis => '0',
cpdis => '0',
wovf => '0',
wunf => '0',
ticc => '0'
);
constant wpr_none : watchpoint_register := (
addr => zero32(31 downto 2),
mask => zero32(31 downto 2),
exec => '0',
load => '0',
store => '0');
signal r, rin : registers;
signal wpr, wprin : watchpoint_registers;
signal dsur, dsuin : dsu_registers;
signal ir, irin : irestart_register;
signal rp, rpin : pwd_register_type;
-- execute stage operations
constant EXE_AND : std_logic_vector(2 downto 0) := "000";
constant EXE_XOR : std_logic_vector(2 downto 0) := "001"; -- must be equal to EXE_PASS2
constant EXE_OR : std_logic_vector(2 downto 0) := "010";
constant EXE_XNOR : std_logic_vector(2 downto 0) := "011";
constant EXE_ANDN : std_logic_vector(2 downto 0) := "100";
constant EXE_ORN : std_logic_vector(2 downto 0) := "101";
constant EXE_DIV : std_logic_vector(2 downto 0) := "110";
constant EXE_PASS1 : std_logic_vector(2 downto 0) := "000";
constant EXE_PASS2 : std_logic_vector(2 downto 0) := "001";
constant EXE_STB : std_logic_vector(2 downto 0) := "010";
constant EXE_STH : std_logic_vector(2 downto 0) := "011";
constant EXE_ONES : std_logic_vector(2 downto 0) := "100";
constant EXE_RDY : std_logic_vector(2 downto 0) := "101";
constant EXE_SPR : std_logic_vector(2 downto 0) := "110";
constant EXE_LINK : std_logic_vector(2 downto 0) := "111";
constant EXE_SLL : std_logic_vector(2 downto 0) := "001";
constant EXE_SRL : std_logic_vector(2 downto 0) := "010";
constant EXE_SRA : std_logic_vector(2 downto 0) := "100";
constant EXE_NOP : std_logic_vector(2 downto 0) := "000";
-- EXE result select
constant EXE_RES_ADD : std_logic_vector(1 downto 0) := "00";
constant EXE_RES_SHIFT : std_logic_vector(1 downto 0) := "01";
constant EXE_RES_LOGIC : std_logic_vector(1 downto 0) := "10";
constant EXE_RES_MISC : std_logic_vector(1 downto 0) := "11";
-- Load types
constant SZBYTE : std_logic_vector(1 downto 0) := "00";
constant SZHALF : std_logic_vector(1 downto 0) := "01";
constant SZWORD : std_logic_vector(1 downto 0) := "10";
constant SZDBL : std_logic_vector(1 downto 0) := "11";
-- calculate register file address
procedure regaddr(cwp : std_logic_vector; reg : std_logic_vector(4 downto 0);
rao : out rfatype) is
variable ra : rfatype;
constant globals : std_logic_vector(RFBITS-5 downto 0) :=
conv_std_logic_vector(NWIN, RFBITS-4);
begin
ra := (others => '0'); ra(4 downto 0) := reg;
if reg(4 downto 3) = "00" then ra(RFBITS -1 downto 4) := globals;
else
ra(NWINLOG2+3 downto 4) := cwp + ra(4);
if ra(RFBITS-1 downto 4) = globals then
ra(RFBITS-1 downto 4) := (others => '0');
end if;
end if;
rao := ra;
end;
-- branch adder
function branch_address(inst : word; pc : pctype) return std_logic_vector is
variable baddr, caddr, tmp : pctype;
begin
caddr := (others => '0'); caddr(31 downto 2) := inst(29 downto 0);
caddr(31 downto 2) := caddr(31 downto 2) + pc(31 downto 2);
baddr := (others => '0'); baddr(31 downto 24) := (others => inst(21));
baddr(23 downto 2) := inst(21 downto 0);
baddr(31 downto 2) := baddr(31 downto 2) + pc(31 downto 2);
if inst(30) = '1' then tmp := caddr; else tmp := baddr; end if;
return(tmp);
end;
-- evaluate branch condition
function branch_true(icc : std_logic_vector(3 downto 0); inst : word)
return std_ulogic is
variable n, z, v, c, branch : std_ulogic;
begin
n := icc(3); z := icc(2); v := icc(1); c := icc(0);
case inst(27 downto 25) is
when "000" => branch := inst(28) xor '0'; -- bn, ba
when "001" => branch := inst(28) xor z; -- be, bne
when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
when "011" => branch := inst(28) xor (n xor v); -- bl, bge
when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
when "101" => branch := inst(28) xor c; -- bcs, bcc
when "110" => branch := inst(28) xor n; -- bneg, bpos
when others => branch := inst(28) xor v; -- bvs, bvc
end case;
return(branch);
end;
-- detect RETT instruction in the pipeline and set the local psr.su and psr.et
procedure su_et_select(r : in registers; xc_ps, xc_s, xc_et : in std_ulogic;
su, et : out std_ulogic) is
begin
if ((r.a.ctrl.rett or r.e.ctrl.rett or r.m.ctrl.rett or r.x.ctrl.rett) = '1')
and (r.x.annul_all = '0')
then su := xc_ps; et := '1';
else su := xc_s; et := xc_et; end if;
end;
-- detect watchpoint trap
function wphit(r : registers; wpr : watchpoint_registers; debug : l3_debug_in_type)
return std_ulogic is
variable exc : std_ulogic;
begin
exc := '0';
for i in 1 to NWP loop
if ((wpr(i-1).exec and r.a.ctrl.pv and not r.a.ctrl.annul) = '1') then
if (((wpr(i-1).addr xor r.a.ctrl.pc(31 downto 2)) and wpr(i-1).mask) = Zero32(31 downto 2)) then
exc := '1';
end if;
end if;
end loop;
if DBGUNIT then
if (debug.dsuen and not r.a.ctrl.annul) = '1' then
exc := exc or (r.a.ctrl.pv and ((debug.dbreak and debug.bwatch) or r.a.step));
end if;
end if;
return(exc);
end;
-- 32-bit shifter
function shift3(r : registers; aluin1, aluin2 : word) return word is
variable shiftin : unsigned(63 downto 0);
variable shiftout : unsigned(63 downto 0);
variable cnt : natural range 0 to 31;
begin
cnt := conv_integer(r.e.shcnt);
if r.e.shleft = '1' then
shiftin(30 downto 0) := (others => '0');
shiftin(63 downto 31) := '0' & unsigned(aluin1);
else
shiftin(63 downto 32) := (others => r.e.sari);
shiftin(31 downto 0) := unsigned(aluin1);
end if;
shiftout := SHIFT_RIGHT(shiftin, cnt);
return(std_logic_vector(shiftout(31 downto 0)));
end;
function shift2(r : registers; aluin1, aluin2 : word) return word is
variable ushiftin : unsigned(31 downto 0);
variable sshiftin : signed(32 downto 0);
variable cnt : natural range 0 to 31;
variable resleft, resright : word;
begin
cnt := conv_integer(r.e.shcnt);
ushiftin := unsigned(aluin1);
sshiftin := signed('0' & aluin1);
if r.e.shleft = '1' then
resleft := std_logic_vector(SHIFT_LEFT(ushiftin, cnt));
return(resleft);
else
if r.e.sari = '1' then sshiftin(32) := aluin1(31); end if;
sshiftin := SHIFT_RIGHT(sshiftin, cnt);
resright := std_logic_vector(sshiftin(31 downto 0));
return(resright);
end if;
end;
function shift(r : registers; aluin1, aluin2 : word;
shiftcnt : std_logic_vector(4 downto 0); sari : std_ulogic ) return word is
variable shiftin : std_logic_vector(63 downto 0);
begin
shiftin := zero32 & aluin1;
if r.e.shleft = '1' then
shiftin(31 downto 0) := zero32; shiftin(63 downto 31) := '0' & aluin1;
else shiftin(63 downto 32) := (others => sari); end if;
if shiftcnt (4) = '1' then shiftin(47 downto 0) := shiftin(63 downto 16); end if;
if shiftcnt (3) = '1' then shiftin(39 downto 0) := shiftin(47 downto 8); end if;
if shiftcnt (2) = '1' then shiftin(35 downto 0) := shiftin(39 downto 4); end if;
if shiftcnt (1) = '1' then shiftin(33 downto 0) := shiftin(35 downto 2); end if;
if shiftcnt (0) = '1' then shiftin(31 downto 0) := shiftin(32 downto 1); end if;
return(shiftin(31 downto 0));
end;
-- Check for illegal and privileged instructions
procedure exception_detect(r : registers; wpr : watchpoint_registers; dbgi : l3_debug_in_type;
trapin : in std_ulogic; ttin : in std_logic_vector(5 downto 0);
trap : out std_ulogic; tt : out std_logic_vector(5 downto 0)) is
variable illegal_inst, privileged_inst : std_ulogic;
variable cp_disabled, fp_disabled, fpop : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable inst : word;
variable wph : std_ulogic;
begin
inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
if r.a.ctrl.annul = '0' then
op := inst(31 downto 30); op2 := inst(24 downto 22);
op3 := inst(24 downto 19); rd := inst(29 downto 25);
illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
fp_disabled := '0'; fpop := '0';
case op is
when CALL => null;
when FMT2 =>
case op2 is
when SETHI | BICC => null;
when FBFCC =>
if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
when CBCCC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when FMT3 =>
case op3 is
when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
SAVE | RESTORE | RDY => null;
when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
if notag = 1 then illegal_inst := '1'; end if;
when UMAC | SMAC =>
if not MACEN then illegal_inst := '1'; end if;
when UMUL | SMUL | UMULCC | SMULCC =>
if not MULEN then illegal_inst := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if not DIVEN then illegal_inst := '1'; end if;
when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
when WRY =>
if rd(4) = '1' and rd(3 downto 0) /= "0010" then -- %ASR16-17, %ASR19-31
privileged_inst := not r.a.su;
end if;
when WRPSR =>
privileged_inst := not r.a.su;
when WRWIM | WRTBR => privileged_inst := not r.a.su;
when FPOP1 | FPOP2 =>
if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
else fp_disabled := '1'; fpop := '0'; end if;
when CPOP1 | CPOP2 =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
when others => -- LDST
case op3 is
when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
null;
when LDDA | STDA =>
illegal_inst := inst(13) or rd(0); privileged_inst := not r.a.su;
when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
SWAPA =>
illegal_inst := inst(13); privileged_inst := not r.a.su;
when CASA =>
if CASAEN then
illegal_inst := inst(13);
if (inst(12 downto 5) /= X"0A") then privileged_inst := not r.a.su; end if;
else illegal_inst := '1'; end if;
when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
if FPEN then fp_disabled := not r.w.s.ef;
else fp_disabled := '1'; end if;
when STDFQ =>
privileged_inst := not r.a.su;
if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
when STDCQ =>
privileged_inst := not r.a.su;
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
when others => illegal_inst := '1';
end case;
end case;
wph := wphit(r, wpr, dbgi);
trap := '1';
if r.a.ctrl.trap = '1' then tt := r.a.ctrl.tt;
elsif privileged_inst = '1' then tt := TT_PRIV;
elsif illegal_inst = '1' then tt := TT_IINST;
elsif fp_disabled = '1' then tt := TT_FPDIS;
elsif cp_disabled = '1' then tt := TT_CPDIS;
elsif wph = '1' then tt := TT_WATCH;
elsif r.a.wovf= '1' then tt := TT_WINOF;
elsif r.a.wunf= '1' then tt := TT_WINUF;
elsif r.a.ticc= '1' then tt := TT_TICC;
else trap := '0'; tt:= (others => '0'); end if;
end if;
end;
-- instructions that write the condition codes (psr.icc)
procedure wicc_y_gen(inst : word; wicc, wy : out std_ulogic) is
begin
wicc := '0'; wy := '0';
if inst(31 downto 30) = FMT3 then
case inst(24 downto 19) is
when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
wicc := '1';
when WRY =>
if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
when MULSCC =>
wicc := '1'; wy := '1';
when UMAC | SMAC =>
if MACEN then wy := '1'; end if;
when UMULCC | SMULCC =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wicc := '1'; wy := '1';
end if;
when UMUL | SMUL =>
if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
wy := '1';
end if;
when UDIVCC | SDIVCC =>
if DIVEN and (divo.nready = '1') and (r.d.cnt /= "00") then
wicc := '1';
end if;
when others =>
end case;
end if;
end;
-- select cwp
procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
cwp : out cwptype) is
begin
if (r.x.rstate = trap) or
(r.x.rstate = dsu2)
or (rstn = '0') then cwp := v.w.s.cwp;
elsif (wcwp = '1') and (annul = '0') then cwp := ncwp;
elsif r.m.wcwp = '1' then cwp := r.m.result(NWINLOG2-1 downto 0);
else cwp := r.d.cwp; end if;
end;
-- generate wcwp in ex stage
procedure cwp_ex(r : in registers; wcwp : out std_ulogic) is
begin
if (r.e.ctrl.inst(31 downto 30) = FMT3) and
(r.e.ctrl.inst(24 downto 19) = WRPSR)
then wcwp := not r.e.ctrl.annul; else wcwp := '0'; end if;
end;
-- generate next cwp & window under- and overflow traps
procedure cwp_ctrl(r : in registers; xc_wim : in std_logic_vector(NWIN-1 downto 0);
inst : word; de_cwp : out cwptype; wovf_exc, wunf_exc, wcwp : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable wim : word;
variable ncwp : cwptype;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
wim(NWIN-1 downto 0) := xc_wim; ncwp := r.d.cwp; wcwp := '0';
if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
wcwp := '1';
if (op3 = SAVE) then
if (not CWPOPT) and (r.d.cwp = CWPMIN) then ncwp := CWPMAX;
else ncwp := r.d.cwp - 1 ; end if;
else
if (not CWPOPT) and (r.d.cwp = CWPMAX) then ncwp := CWPMIN;
else ncwp := r.d.cwp + 1; end if;
end if;
if wim(conv_integer(ncwp)) = '1' then
if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
end if;
end if;
de_cwp := ncwp;
end;
-- generate register read address 1
procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 downto 0);
rs1mod : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
rs1 := inst(18 downto 14); rs1mod := '0';
if (op = LDST) then
if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
(r.d.cnt = "10")
then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
rs1(0) := '1';
end if;
end if;
end;
-- load/icc interlock detection
function icc_valid(r : registers) return std_logic is
variable not_valid : std_logic;
begin
not_valid := '0';
if MULEN or DIVEN then
not_valid := r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul);
end if;
not_valid := not_valid or (r.a.ctrl.wicc or r.e.ctrl.wicc);
return(not not_valid);
end;
procedure bp_miss_ex(r : registers; icc : std_logic_vector(3 downto 0);
ex_bpmiss, ra_bpannul : out std_logic) is
variable miss : std_logic;
begin
miss := (not r.e.ctrl.annul) and r.e.bp and not branch_true(icc, r.e.ctrl.inst);
ra_bpannul := miss and r.e.ctrl.inst(29);
ex_bpmiss := miss;
end;
procedure bp_miss_ra(r : registers; ra_bpmiss, de_bpannul : out std_logic) is
variable miss : std_logic;
begin
miss := ((not r.a.ctrl.annul) and r.a.bp and icc_valid(r) and not branch_true(r.m.icc, r.a.ctrl.inst));
de_bpannul := miss and r.a.ctrl.inst(29);
ra_bpmiss := miss;
end;
procedure lock_gen(r : registers; rs2, rd : std_logic_vector(4 downto 0);
rfa1, rfa2, rfrd : rfatype; inst : word; fpc_lock, mulinsn, divinsn, de_wcwp : std_ulogic;
lldcheck1, lldcheck2, lldlock, lldchkra, lldchkex, bp, nobp, de_fins_hold : out std_ulogic;
iperr : std_logic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable rs1 : std_logic_vector(4 downto 0);
variable i, ldcheck1, ldcheck2, ldchkra, ldchkex, ldcheck3 : std_ulogic;
variable ldlock, icc_check, bicc_hold, chkmul, y_check : std_logic;
variable icc_check_bp, y_hold, mul_hold, bicc_hold_bp, fins, call_hold : std_ulogic;
variable de_fins_holdx : std_ulogic;
begin
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
rs1 := inst(18 downto 14); i := inst(13);
ldcheck1 := '0'; ldcheck2 := '0'; ldcheck3 := '0'; ldlock := '0';
ldchkra := '1'; ldchkex := '1'; icc_check := '0'; bicc_hold := '0';
y_check := '0'; y_hold := '0'; bp := '0'; mul_hold := '0';
icc_check_bp := '0'; nobp := '0'; fins := '0'; call_hold := '0';
if (r.d.annul = '0')
then
case op is
when CALL =>
call_hold := '1'; nobp := BPRED;
when FMT2 =>
if (op2 = BICC) and (cond(2 downto 0) /= "000") then
icc_check_bp := '1';
end if;
if (op2 = BICC) then nobp := BPRED; end if;
when FMT3 =>
ldcheck1 := '1'; ldcheck2 := not i;
case op3 is
when TICC =>
if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
nobp := BPRED;
when RDY =>
ldcheck1 := '0'; ldcheck2 := '0';
if MACPIPE then y_check := '1'; end if;
when RDWIM | RDTBR =>
ldcheck1 := '0'; ldcheck2 := '0';
when RDPSR =>
ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
when SDIV | SDIVCC | UDIV | UDIVCC =>
if DIVEN then y_check := '1'; nobp := op3(4); end if; -- no BP on divcc
when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0'; fins := BPRED;
when JMPL => call_hold := '1'; nobp := BPRED;
when others =>
end case;
when LDST =>
ldcheck1 := '1'; ldchkra := '0';
case r.d.cnt is
when "00" =>
if (lddel = 2) and (op3(2) = '1') and (op3(5) = '0') then ldcheck3 := '1'; end if;
ldcheck2 := not i; ldchkra := '1';
when "01" =>
ldcheck2 := not i;
if (op3(5) and op3(2) and not op3(3)) = '1' then ldcheck1 := '0'; ldcheck2 := '0'; end if; -- STF/STC
when others => ldchkex := '0';
if CASAEN and (op3(5 downto 3) = "111") then
ldcheck2 := '1';
elsif (op3(5) = '1') or ((op3(5) & op3(3 downto 1)) = "0110") -- LDST
then ldcheck1 := '0'; ldcheck2 := '0'; end if;
end case;
if op3(5) = '1' then fins := BPRED; end if; -- no BP on FPU/CP LD/ST
when others => null;
end case;
end if;
if MULEN or DIVEN then
chkmul := mulinsn;
mul_hold := (r.a.mulstart and r.a.ctrl.wicc) or (r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
if (MULTYPE = 0) and ((icc_check_bp and BPRED and r.a.ctrl.wicc and r.a.ctrl.wy) = '1')
then mul_hold := '1'; end if;
else chkmul := '0'; end if;
if DIVEN then
y_hold := y_check and (r.a.ctrl.wy or r.e.ctrl.wy);
chkmul := chkmul or divinsn;
end if;
bicc_hold := icc_check and not icc_valid(r);
bicc_hold_bp := icc_check_bp and not icc_valid(r);
if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.a.ctrl.rd = rfa2)) or
((ldcheck3 = '1') and (r.a.ctrl.rd = rfrd)))
then ldlock := '1'; end if;
if (((r.e.ctrl.ld or r.e.mac) and r.e.ctrl.wreg and ldchkex) = '1') and
((lddel = 2) or (MACPIPE and (r.e.mac = '1')) or ((MULTYPE = 3) and (r.e.mul = '1'))) and
(((ldcheck1 = '1') and (r.e.ctrl.rd = rfa1)) or
((ldcheck2 = '1') and (r.e.ctrl.rd = rfa2)))
then ldlock := '1'; end if;
de_fins_holdx := BPRED and fins and (r.a.bp or r.e.bp); -- skip BP on FPU inst in branch target address
de_fins_hold := de_fins_holdx;
ldlock := ldlock or y_hold or fpc_lock or (BPRED and r.a.bp and r.a.ctrl.inst(29) and de_wcwp) or de_fins_holdx;
if ((icc_check_bp and BPRED) = '1') and ((r.a.nobp or mul_hold) = '0') then
bp := bicc_hold_bp;
else ldlock := ldlock or bicc_hold or bicc_hold_bp; end if;
lldcheck1 := ldcheck1; lldcheck2:= ldcheck2; lldlock := ldlock;
lldchkra := ldchkra; lldchkex := ldchkex;
end;
procedure fpbranch(inst : in word; fcc : in std_logic_vector(1 downto 0);
branch : out std_ulogic) is
variable cond : std_logic_vector(3 downto 0);
variable fbres : std_ulogic;
begin
cond := inst(28 downto 25);
case cond(2 downto 0) is
when "000" => fbres := '0'; -- fba, fbn
when "001" => fbres := fcc(1) or fcc(0);
when "010" => fbres := fcc(1) xor fcc(0);
when "011" => fbres := fcc(0);
when "100" => fbres := (not fcc(1)) and fcc(0);
when "101" => fbres := fcc(1);
when "110" => fbres := fcc(1) and not fcc(0);
when others => fbres := fcc(1) and fcc(0);
end case;
branch := cond(3) xor fbres;
end;
-- PC generation
procedure ic_ctrl(r : registers; inst : word; annul_all, ldlock, branch_true,
fbranch_true, cbranch_true, fccv, cccv : in std_ulogic;
cnt : out std_logic_vector(1 downto 0);
de_pc : out pctype; de_branch, ctrl_annul, de_annul, jmpl_inst, inull,
de_pv, ctrl_pv, de_hold_pc, ticc_exception, rett_inst, mulstart,
divstart : out std_ulogic; rabpmiss, exbpmiss, iperr : std_logic) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable cond : std_logic_vector(3 downto 0);
variable hold_pc, annul_current, annul_next, branch, annul, pv : std_ulogic;
variable de_jmpl, inhibit_current : std_ulogic;
begin
branch := '0'; annul_next := '0'; annul_current := '0'; pv := '1';
hold_pc := '0'; ticc_exception := '0'; rett_inst := '0';
op := inst(31 downto 30); op3 := inst(24 downto 19);
op2 := inst(24 downto 22); cond := inst(28 downto 25);
annul := inst(29); de_jmpl := '0'; cnt := "00";
mulstart := '0'; divstart := '0'; inhibit_current := '0';
if (r.d.annul = '0')
then
case inst(31 downto 30) is
when CALL =>
branch := '1';
if r.d.inull = '1' then
hold_pc := '1'; annul_current := '1';
end if;
when FMT2 =>
if (op2 = BICC) or (FPEN and (op2 = FBFCC)) or (CPEN and (op2 = CBCCC)) then
if (FPEN and (op2 = FBFCC)) then
branch := fbranch_true;
if fccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
elsif (CPEN and (op2 = CBCCC)) then
branch := cbranch_true;
if cccv /= '1' then hold_pc := '1'; annul_current := '1'; end if;
else branch := branch_true or (BPRED and orv(cond) and not icc_valid(r)); end if;
if hold_pc = '0' then
if (branch = '1') then
if (cond = BA) and (annul = '1') then annul_next := '1'; end if;
else annul_next := annul_next or annul; end if;
if r.d.inull = '1' then -- contention with JMPL
hold_pc := '1'; annul_current := '1'; annul_next := '0';
end if;
end if;
end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN and (MULTYPE /= 0) then mulstart := '1'; end if;
if MULEN and (MULTYPE = 0) then
case r.d.cnt is
when "00" =>
cnt := "01"; hold_pc := '1'; pv := '0'; mulstart := '1';
when "01" =>
if mulo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
case r.d.cnt is
when "00" =>
hold_pc := '1'; pv := '0';
if r.d.divrdy = '0' then
cnt := "01"; divstart := '1';
end if;
when "01" =>
if divo.nready = '1' then cnt := "00";
else cnt := "01"; pv := '0'; hold_pc := '1'; end if;
when others => null;
end case;
end if;
when TICC =>
if branch_true = '1' then ticc_exception := '1'; end if;
when RETT =>
rett_inst := '1'; --su := sregs.ps;
when JMPL =>
de_jmpl := '1';
when WRY =>
if PWRD1 then
if inst(29 downto 25) = "10011" then -- %ASR19
case r.d.cnt is
when "00" =>
pv := '0'; cnt := "00"; hold_pc := '1';
if r.x.ipend = '1' then cnt := "01"; end if;
when "01" =>
cnt := "00";
when others =>
end case;
end if;
end if;
when others => null;
end case;
when others => -- LDST
case r.d.cnt is
when "00" =>
if (op3(2) = '1') or (op3(1 downto 0) = "11") then -- ST/LDST/SWAP/LDD/CASA
cnt := "01"; hold_pc := '1'; pv := '0';
end if;
when "01" =>
if (op3(2 downto 0) = "111") or (op3(3 downto 0) = "1101") or
(CASAEN and (op3(5 downto 4) = "11")) or -- CASA
((CPEN or FPEN) and ((op3(5) & op3(2 downto 0)) = "1110"))
then -- LDD/STD/LDSTUB/SWAP
cnt := "10"; pv := '0'; hold_pc := '1';
else
cnt := "00";
end if;
when "10" =>
cnt := "00";
when others => null;
end case;
end case;
end if;
if ldlock = '1' then
cnt := r.d.cnt; annul_next := '0'; pv := '1';
end if;
hold_pc := (hold_pc or ldlock) and not annul_all;
if ((exbpmiss and r.a.ctrl.annul and r.d.pv and not hold_pc) = '1') then
annul_next := '1'; pv := '0';
end if;
if ((exbpmiss and not r.a.ctrl.annul and r.d.pv) = '1') then
annul_next := '1'; pv := '0'; annul_current := '1';
end if;
if ((exbpmiss and not r.a.ctrl.annul and not r.d.pv and not hold_pc) = '1') then
annul_next := '1'; pv := '0';
end if;
if ((exbpmiss and r.e.ctrl.inst(29) and not r.a.ctrl.annul and not r.d.pv ) = '1')
and (r.d.cnt = "01") then
annul_next := '1'; annul_current := '1'; pv := '0';
end if;
if (exbpmiss and r.e.ctrl.inst(29) and r.a.ctrl.annul and r.d.pv) = '1' then
annul_next := '1'; pv := '0'; inhibit_current := '1';
end if;
if (rabpmiss and not r.a.ctrl.inst(29) and not r.d.annul and r.d.pv and not hold_pc) = '1' then
annul_next := '1'; pv := '0';
end if;
if (rabpmiss and r.a.ctrl.inst(29) and not r.d.annul and r.d.pv ) = '1' then
annul_next := '1'; pv := '0'; inhibit_current := '1';
end if;
if hold_pc = '1' then de_pc := r.d.pc; else de_pc := r.f.pc; end if;
annul_current := (annul_current or (ldlock and not inhibit_current) or annul_all);
ctrl_annul := r.d.annul or annul_all or annul_current or inhibit_current;
pv := pv and not ((r.d.inull and not hold_pc) or annul_all);
jmpl_inst := de_jmpl and not annul_current and not inhibit_current;
annul_next := (r.d.inull and not hold_pc) or annul_next or annul_all;
if (annul_next = '1') or (rstn = '0') then
cnt := (others => '0');
end if;
de_hold_pc := hold_pc; de_branch := branch; de_annul := annul_next;
de_pv := pv; ctrl_pv := r.d.pv and
not ((r.d.annul and not r.d.pv) or annul_all or annul_current);
inull := (not rstn) or r.d.inull or hold_pc or annul_all;
end;
-- register write address generation
procedure rd_gen(r : registers; inst : word; wreg, ld : out std_ulogic;
rdo : out std_logic_vector(4 downto 0)) is
variable write_reg : std_ulogic;
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
begin
op := inst(31 downto 30);
op2 := inst(24 downto 22);
op3 := inst(24 downto 19);
write_reg := '0'; rd := inst(29 downto 25); ld := '0';
case op is
when CALL =>
write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
when FMT2 =>
if (op2 = SETHI) then write_reg := '1'; end if;
when FMT3 =>
case op3 is
when UMUL | SMUL | UMULCC | SMULCC =>
if MULEN then
if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if (divo.nready = '1') and (r.d.cnt /= "00") then
write_reg := '1';
end if;
else write_reg := '1'; end if;
when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
when FPOP1 | FPOP2 => null;
when CPOP1 | CPOP2 => null;
when others => write_reg := '1';
end case;
when others => -- LDST
ld := not op3(2);
if (op3(2) = '0') and not ((CPEN or FPEN) and (op3(5) = '1'))
then write_reg := '1'; end if;
case op3 is
when SWAP | SWAPA | LDSTUB | LDSTUBA | CASA =>
if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
when others => null;
end case;
if r.d.cnt = "01" then
case op3 is
when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
when others =>
end case;
end if;
end case;
if (rd = "00000") then write_reg := '0'; end if;
wreg := write_reg; rdo := rd;
end;
-- immediate data generation
function imm_data (r : registers; insn : word)
return word is
variable immediate_data, inst : word;
begin
immediate_data := (others => '0'); inst := insn;
case inst(31 downto 30) is
when FMT2 =>
immediate_data := inst(21 downto 0) & "0000000000";
when others => -- LDST
immediate_data(31 downto 13) := (others => inst(12));
immediate_data(12 downto 0) := inst(12 downto 0);
end case;
return(immediate_data);
end;
-- read special registers
function get_spr (r : registers) return word is
variable spr : word;
begin
spr := (others => '0');
case r.e.ctrl.inst(24 downto 19) is
when RDPSR => spr(31 downto 5) := conv_std_logic_vector(IMPL,4) &
conv_std_logic_vector(VER,4) & r.m.icc & "000000" & r.w.s.ec & r.w.s.ef &
r.w.s.pil & r.e.su & r.w.s.ps & r.e.et;
spr(NWINLOG2-1 downto 0) := r.e.cwp;
when RDTBR => spr(31 downto 4) := r.w.s.tba & r.w.s.tt;
when RDWIM => spr(NWIN-1 downto 0) := r.w.s.wim;
when others =>
end case;
return(spr);
end;
-- immediate data select
function imm_select(inst : word) return boolean is
variable imm : boolean;
begin
imm := false;
case inst(31 downto 30) is
when FMT2 =>
case inst(24 downto 22) is
when SETHI => imm := true;
when others =>
end case;
when FMT3 =>
case inst(24 downto 19) is
when RDWIM | RDPSR | RDTBR => imm := true;
when others => if (inst(13) = '1') then imm := true; end if;
end case;
when LDST =>
if (inst(13) = '1') then imm := true; end if;
when others =>
end case;
return(imm);
end;
-- EXE operation
procedure alu_op(r : in registers; iop1, iop2 : in word; me_icc : std_logic_vector(3 downto 0);
my, ldbp : std_ulogic; aop1, aop2 : out word; aluop : out std_logic_vector(2 downto 0);
alusel : out std_logic_vector(1 downto 0); aluadd : out std_ulogic;
shcnt : out std_logic_vector(4 downto 0); sari, shleft, ymsb,
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_logic
) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable y0, i : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30);
op2 := r.a.ctrl.inst(24 downto 22);
op3 := r.a.ctrl.inst(24 downto 19);
rs1 := r.a.ctrl.inst(18 downto 14); i := r.a.ctrl.inst(13);
rs2 := r.a.ctrl.inst(4 downto 0); rd := r.a.ctrl.inst(29 downto 25);
aop1 := iop1; aop2 := iop2; ldbp2 := ldbp;
aluop := EXE_NOP; alusel := EXE_RES_MISC; aluadd := '1';
shcnt := iop2(4 downto 0); sari := '0'; shleft := '0'; invop2 := '0';
ymsb := iop1(0); mulins := '0'; divins := '0'; mulstep := '0';
macins := '0';
if r.e.ctrl.wy = '1' then y0 := my;
elsif r.m.ctrl.wy = '1' then y0 := r.m.y(0);
elsif r.x.ctrl.wy = '1' then y0 := r.x.y(0);
else y0 := r.w.s.y(0); end if;
if r.e.ctrl.wicc = '1' then icc := me_icc;
elsif r.m.ctrl.wicc = '1' then icc := r.m.icc;
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
else icc := r.w.s.icc; end if;
case op is
when CALL =>
aluop := EXE_LINK;
when FMT2 =>
case op2 is
when SETHI => aluop := EXE_PASS2;
when others =>
end case;
when FMT3 =>
case op3 is
when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
TICC | JMPL | RETT => alusel := EXE_RES_ADD;
when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
when MULSCC => alusel := EXE_RES_ADD;
aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
mulstep := '1';
when UMUL | UMULCC | SMUL | SMULCC =>
if MULEN then mulins := '1'; end if;
when UMAC | SMAC =>
if MACEN then mulins := '1'; macins := '1'; end if;
when UDIV | UDIVCC | SDIV | SDIVCC =>
if DIVEN then
aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
end if;
when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
when RDY => aluop := EXE_RDY;
when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
shcnt := not iop2(4 downto 0); invop2 := '1';
when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
when FPOP1 | FPOP2 =>
when others =>
end case;
when others => -- LDST
case r.a.ctrl.cnt is
when "00" =>
alusel := EXE_RES_ADD;
when "01" =>
case op3 is
when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
when LDDF => alusel := EXE_RES_ADD;
when SWAP | SWAPA | LDSTUB | LDSTUBA | CASA => alusel := EXE_RES_ADD;
when STF | STDF =>
when others =>
aluop := EXE_PASS1;
if op3(2) = '1' then
if op3(1 downto 0) = "01" then aluop := EXE_STB;
elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
end if;
end case;
when "10" =>
aluop := EXE_PASS1;
if op3(2) = '1' then -- ST
if (op3(3) and not op3(5) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB
end if;
if CASAEN and (r.m.casa = '1') then
alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
end if;
when others =>
end case;
end case;
end;
function ra_inull_gen(r, v : registers) return std_ulogic is
variable de_inull : std_ulogic;
begin
de_inull := '0';
if ((v.e.jmpl or v.e.ctrl.rett) and not v.e.ctrl.annul and not (r.e.jmpl and not r.e.ctrl.annul)) = '1' then de_inull := '1'; end if;
if ((v.a.jmpl or v.a.ctrl.rett) and not v.a.ctrl.annul and not (r.a.jmpl and not r.a.ctrl.annul)) = '1' then de_inull := '1'; end if;
return(de_inull);
end;
-- operand generation
procedure op_mux(r : in registers; rfd, ed, md, xd, im : in word;
rsel : in std_logic_vector(2 downto 0);
ldbp : out std_ulogic; d : out word; id : std_logic) is
begin
ldbp := '0';
case rsel is
when "000" => d := rfd;
when "001" => d := ed;
when "010" => d := md; if lddel = 1 then ldbp := r.m.ctrl.ld; end if;
when "011" => d := xd;
when "100" => d := im;
when "101" => d := (others => '0');
when "110" => d := r.w.result;
when others => d := (others => '-');
end case;
if CASAEN and (r.a.ctrl.cnt = "10") and ((r.m.casa and not id) = '1') then ldbp := '1'; end if;
end;
procedure op_find(r : in registers; ldchkra : std_ulogic; ldchkex : std_ulogic;
rs1 : std_logic_vector(4 downto 0); ra : rfatype; im : boolean; rfe : out std_ulogic;
osel : out std_logic_vector(2 downto 0); ldcheck : std_ulogic) is
begin
rfe := '0';
if im then osel := "100";
elsif rs1 = "00000" then osel := "101"; -- %g0
elsif ((r.a.ctrl.wreg and ldchkra) = '1') and (ra = r.a.ctrl.rd) then osel := "001";
elsif ((r.e.ctrl.wreg and ldchkex) = '1') and (ra = r.e.ctrl.rd) then osel := "010";
elsif (r.m.ctrl.wreg = '1') and (ra = r.m.ctrl.rd) then osel := "011";
elsif (irfwt = 0) and (r.x.ctrl.wreg = '1') and (ra = r.x.ctrl.rd) then osel := "110";
else osel := "000"; rfe := ldcheck; end if;
end;
-- generate carry-in for alu
procedure cin_gen(r : registers; me_cin : in std_ulogic; cin : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable ncin : std_ulogic;
begin
op := r.a.ctrl.inst(31 downto 30); op3 := r.a.ctrl.inst(24 downto 19);
if r.e.ctrl.wicc = '1' then ncin := me_cin;
else ncin := r.m.icc(0); end if;
cin := '0';
case op is
when FMT3 =>
case op3 is
when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
when ADDX | ADDXCC => cin := ncin;
when SUBX | SUBXCC => cin := not ncin;
when others => null;
end case;
when LDST =>
if CASAEN and (r.m.casa = '1') and (r.a.ctrl.cnt = "10") then
cin := '1';
end if;
when others => null;
end case;
end;
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
ymsb : std_ulogic; logicres, y : out word) is
variable logicout : word;
begin
case r.e.aluop is
when EXE_AND => logicout := aluin1 and aluin2;
when EXE_ANDN => logicout := aluin1 and not aluin2;
when EXE_OR => logicout := aluin1 or aluin2;
when EXE_ORN => logicout := aluin1 or not aluin2;
when EXE_XOR => logicout := aluin1 xor aluin2;
when EXE_XNOR => logicout := aluin1 xor not aluin2;
when EXE_DIV =>
if DIVEN then logicout := aluin2;
else logicout := (others => '-'); end if;
when others => logicout := (others => '-');
end case;
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
y := ymsb & r.m.y(31 downto 1);
elsif r.e.ctrl.wy = '1' then y := logicout;
elsif r.m.ctrl.wy = '1' then y := mey;
elsif MACPIPE and (r.x.mac = '1') then y := mulo.result(63 downto 32);
elsif r.x.ctrl.wy = '1' then y := r.x.y;
else y := r.w.s.y; end if;
logicres := logicout;
end;
function st_align(size : std_logic_vector(1 downto 0); bpdata : word) return word is
variable edata : word;
begin
case size is
when "01" => edata := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
when "10" => edata := bpdata(15 downto 0) & bpdata(15 downto 0);
when others => edata := bpdata;
end case;
return(edata);
end;
procedure misc_op(r : registers; wpr : watchpoint_registers;
aluin1, aluin2, ldata, mey : word;
mout, edata : out word) is
variable miscout, bpdata, stdata : word;
variable wpi : integer;
begin
wpi := 0; miscout := r.e.ctrl.pc(31 downto 2) & "00";
edata := aluin1; bpdata := aluin1;
if ((r.x.ctrl.wreg and r.x.ctrl.ld and not r.x.ctrl.annul) = '1') and
(r.x.ctrl.rd = r.e.ctrl.rd) and (r.e.ctrl.inst(31 downto 30) = LDST) and
(r.e.ctrl.cnt /= "10")
then bpdata := ldata; end if;
case r.e.aluop is
when EXE_STB => miscout := bpdata(7 downto 0) & bpdata(7 downto 0) &
bpdata(7 downto 0) & bpdata(7 downto 0);
edata := miscout;
when EXE_STH => miscout := bpdata(15 downto 0) & bpdata(15 downto 0);
edata := miscout;
when EXE_PASS1 => miscout := bpdata; edata := miscout;
when EXE_PASS2 => miscout := aluin2;
when EXE_ONES => miscout := (others => '1');
edata := miscout;
when EXE_RDY =>
if MULEN and (r.m.ctrl.wy = '1') then miscout := mey;
else miscout := r.m.y; end if;
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
end if;
if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
miscout := asr17_gen(r);
end if;
if MACEN then
if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(31 downto 0); -- data forward of asr18
else miscout := r.w.s.asr18; end if;
else
if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
miscout := mulo.result(63 downto 32); -- data forward Y
end if;
end if;
end if;
when EXE_SPR =>
miscout := get_spr(r);
when others => null;
end case;
mout := miscout;
end;
procedure alu_select(r : registers; addout : std_logic_vector(32 downto 0);
op1, op2 : word; shiftout, logicout, miscout : word; res : out word;
me_icc : std_logic_vector(3 downto 0);
icco : out std_logic_vector(3 downto 0); divz, mzero : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable icc : std_logic_vector(3 downto 0);
variable aluresult : word;
variable azero : std_logic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
icc := (others => '0');
if addout(32 downto 1) = zero32 then azero := '1'; else azero := '0'; end if;
mzero := azero;
case r.e.alusel is
when EXE_RES_ADD =>
aluresult := addout(32 downto 1);
if r.e.aluadd = '0' then
icc(0) := ((not op1(31)) and not op2(31)) or -- Carry
(addout(32) and ((not op1(31)) or not op2(31)));
icc(1) := (op1(31) and (op2(31)) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and not op2(31));
else
icc(0) := (op1(31) and op2(31)) or -- Carry
((not addout(32)) and (op1(31) or op2(31)));
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
(addout(32) and (not op1(31)) and (not op2(31)));
end if;
if notag = 0 then
case op is
when FMT3 =>
case op3 is
when TADDCC | TADDCCTV =>
icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
when TSUBCC | TSUBCCTV =>
icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
when others => null;
end case;
when others => null;
end case;
end if;
-- if aluresult = zero32 then icc(2) := '1'; end if;
icc(2) := azero;
when EXE_RES_SHIFT => aluresult := shiftout;
when EXE_RES_LOGIC => aluresult := logicout;
if aluresult = zero32 then icc(2) := '1'; end if;
when others => aluresult := miscout;
end case;
if r.e.jmpl = '1' then aluresult := r.e.ctrl.pc(31 downto 2) & "00"; end if;
icc(3) := aluresult(31); divz := icc(2);
if r.e.ctrl.wicc = '1' then
if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
else icco := icc; end if;
elsif r.m.ctrl.wicc = '1' then icco := me_icc;
elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
else icco := r.w.s.icc; end if;
res := aluresult;
end;
procedure dcache_gen(r, v : registers; dci : out dc_in_type;
link_pc, jump, force_a2, load, mcasa : out std_ulogic) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable su, lock : std_ulogic;
begin
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
dci.signed := '0'; dci.lock := '0'; dci.dsuen := '0'; dci.size := SZWORD;
mcasa := '0';
if op = LDST then
case op3 is
when LDUB | LDUBA => dci.size := SZBYTE;
when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
when LDUH | LDUHA => dci.size := SZHALF;
when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
when LD | LDA | LDF | LDC => dci.size := SZWORD;
when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
when CASA => if CASAEN then dci.size := SZWORD; dci.lock := '1'; end if;
when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
when STB | STBA => dci.size := SZBYTE;
when STH | STHA => dci.size := SZHALF;
when ST | STA | STF => dci.size := SZWORD;
when ISTD | STDA => dci.size := SZDBL;
when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
when STDC | STDCQ => if CPEN then dci.size := SZDBL; end if;
when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
end case;
end if;
link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
-- load/store control decoding
if (r.e.ctrl.annul or r.e.ctrl.trap) = '0' then
case op is
when CALL => link_pc := '1';
when FMT3 =>
if r.e.ctrl.trap = '0' then
case op3 is
when JMPL => jump := '1'; link_pc := '1';
when RETT => jump := '1';
when others => null;
end case;
end if;
when LDST =>
case r.e.ctrl.cnt is
when "00" =>
dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP/CASA
load := op3(3) or not op3(2);
--dci.enaddr := '1';
dci.enaddr := (not op3(2)) or op3(2)
or (op3(3) and op3(2));
when "01" =>
force_a2 := not op3(2); -- LDD
load := not op3(2); dci.enaddr := not op3(2);
if op3(3 downto 2) = "01" then -- ST/STD
dci.write := '1';
end if;
if (CASAEN and (op3(5 downto 4) = "11")) or -- CASA
(op3(3 downto 2) = "11") then -- LDST/SWAP
dci.enaddr := '1';
end if;
when "10" => -- STD/LDST/SWAP/CASA
dci.write := '1';
when others => null;
end case;
if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
dci.enaddr := '0';
end if;
if (CASAEN and (op3(5 downto 4) = "11")) then mcasa := '1'; end if;
when others => null;
end case;
end if;
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
else su := r.w.s.s; end if;
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
if (op3(4) = '1') and ((op3(5) = '0') or not CPEN) then
dci.asi := r.e.ctrl.inst(12 downto 5);
end if;
end;
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
edata2, eres2 : out word) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
edata2 := edata; eres2 := eres;
op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
if FPEN then
if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
edata2 := fpstdata; eres2 := fpstdata;
end if;
end if;
if CASAEN and (r.m.casa = '1') and (r.e.ctrl.cnt = "10") then
edata2 := r.e.op1; eres2 := r.e.op1;
end if;
end;
function ld_align(data : dcdtype; set : std_logic_vector(DSETMSB downto 0);
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
variable align_data, rdata : word;
begin
align_data := data(conv_integer(set)); rdata := (others => '0');
case size is
when "00" => -- byte read
case laddr is
when "00" =>
rdata(7 downto 0) := align_data(31 downto 24);
if signed = '1' then rdata(31 downto 8) := (others => align_data(31)); end if;
when "01" =>
rdata(7 downto 0) := align_data(23 downto 16);
if signed = '1' then rdata(31 downto 8) := (others => align_data(23)); end if;
when "10" =>
rdata(7 downto 0) := align_data(15 downto 8);
if signed = '1' then rdata(31 downto 8) := (others => align_data(15)); end if;
when others =>
rdata(7 downto 0) := align_data(7 downto 0);
if signed = '1' then rdata(31 downto 8) := (others => align_data(7)); end if;
end case;
when "01" => -- half-word read
if laddr(1) = '1' then
rdata(15 downto 0) := align_data(15 downto 0);
if signed = '1' then rdata(31 downto 15) := (others => align_data(15)); end if;
else
rdata(15 downto 0) := align_data(31 downto 16);
if signed = '1' then rdata(31 downto 15) := (others => align_data(31)); end if;
end if;
when others => -- single and double word read
rdata := align_data;
end case;
return(rdata);
end;
procedure mem_trap(r : registers; wpr : watchpoint_registers;
annul, holdn : in std_ulogic;
trapout, iflush, nullify, werrout : out std_ulogic;
tt : out std_logic_vector(5 downto 0)) is
variable cwp : std_logic_vector(NWINLOG2-1 downto 0);
variable cwpx : std_logic_vector(5 downto NWINLOG2);
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable nalign_d : std_ulogic;
variable trap, werr : std_ulogic;
begin
op := r.m.ctrl.inst(31 downto 30); op2 := r.m.ctrl.inst(24 downto 22);
op3 := r.m.ctrl.inst(24 downto 19);
cwpx := r.m.result(5 downto NWINLOG2); cwpx(5) := '0';
iflush := '0'; trap := r.m.ctrl.trap; nullify := annul;
tt := r.m.ctrl.tt; werr := (dco.werr or r.m.werr) and not r.w.s.dwt;
nalign_d := r.m.nalign or r.m.result(2);
if (trap = '1') and (r.m.ctrl.pv = '1') then
if op = LDST then nullify := '1'; end if;
end if;
if ((annul or trap) /= '1') and (r.m.ctrl.pv = '1') then
if (werr and holdn) = '1' then
trap := '1'; tt := TT_DSEX; werr := '0';
if op = LDST then nullify := '1'; end if;
end if;
end if;
if ((annul or trap) /= '1') then
case op is
when FMT2 =>
case op2 is
when FBFCC =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CBCCC =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when FMT3 =>
case op3 is
when WRPSR =>
if (orv(cwpx) = '1') then trap := '1'; tt := TT_IINST; end if;
when UDIV | SDIV | UDIVCC | SDIVCC =>
if DIVEN then
if r.m.divz = '1' then trap := '1'; tt := TT_DIV; end if;
end if;
when JMPL | RETT =>
if r.m.nalign = '1' then trap := '1'; tt := TT_UNALA; end if;
when TADDCCTV | TSUBCCTV =>
if (notag = 0) and (r.m.icc(1) = '1') then
trap := '1'; tt := TT_TAG;
end if;
when FLUSH => iflush := '1';
when FPOP1 | FPOP2 =>
if FPEN and (fpo.exc = '1') then trap := '1'; tt := TT_FPEXC; end if;
when CPOP1 | CPOP2 =>
if CPEN and (cpo.exc = '1') then trap := '1'; tt := TT_CPEXC; end if;
when others => null;
end case;
when LDST =>
if r.m.ctrl.cnt = "00" then
case op3 is
when LDDF | STDF | STDFQ =>
if FPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif (fpo.exc and r.m.ctrl.pv) = '1'
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
end if;
when LDDC | STDC | STDCQ =>
if CPEN then
if nalign_d = '1' then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
end if;
when LDD | ISTD | LDDA | STDA =>
if r.m.result(2 downto 0) /= "000" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDF | LDFSR | STFSR | STF =>
if FPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif FPEN and ((fpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_FPEXC; nullify := '1'; end if;
when LDC | LDCSR | STCSR | STC =>
if CPEN and (r.m.nalign = '1') then
trap := '1'; tt := TT_UNALA; nullify := '1';
elsif CPEN and ((cpo.exc and r.m.ctrl.pv) = '1')
then trap := '1'; tt := TT_CPEXC; nullify := '1'; end if;
when LD | LDA | ST | STA | SWAP | SWAPA | CASA =>
if r.m.result(1 downto 0) /= "00" then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when LDUH | LDUHA | LDSH | LDSHA | STH | STHA =>
if r.m.result(0) /= '0' then
trap := '1'; tt := TT_UNALA; nullify := '1';
end if;
when others => null;
end case;
for i in 1 to NWP loop
if ((((wpr(i-1).load and not op3(2)) or (wpr(i-1).store and op3(2))) = '1') and
(((wpr(i-1).addr xor r.m.result(31 downto 2)) and wpr(i-1).mask) = zero32(31 downto 2)))
then trap := '1'; tt := TT_WATCH; nullify := '1'; end if;
end loop;
end if;
when others => null;
end case;
end if;
if (rstn = '0') or (r.x.rstate = dsu2) then werr := '0'; end if;
trapout := trap; werrout := werr;
end;
procedure irq_trap(r : in registers;
ir : in irestart_register;
irl : in std_logic_vector(3 downto 0);
annul : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
tt : in std_logic_vector(5 downto 0);
nullify : in std_ulogic;
irqen : out std_ulogic;
irqen2 : out std_ulogic;
nullify2 : out std_ulogic;
trap2, ipend : out std_ulogic;
tt2 : out std_logic_vector(5 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable pend : std_ulogic;
begin
nullify2 := nullify; trap2 := trap; tt2 := tt;
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
irqen := '1'; irqen2 := r.m.irqen;
if (annul or trap) = '0' then
if ((op = FMT3) and (op3 = WRPSR)) then irqen := '0'; end if;
end if;
if (irl = "1111") or (irl > r.w.s.pil) then
pend := r.m.irqen and r.m.irqen2 and r.w.s.et and not ir.pwd
;
else pend := '0'; end if;
ipend := pend;
if ((not annul) and pv and (not trap) and pend) = '1' then
trap2 := '1'; tt2 := "01" & irl;
if op = LDST then nullify2 := '1'; end if;
end if;
end;
procedure irq_intack(r : in registers; holdn : in std_ulogic; intack: out std_ulogic) is
begin
intack := '0';
if r.x.rstate = trap then
if r.w.s.tt(7 downto 4) = "0001" then intack := '1'; end if;
end if;
end;
-- write special registers
procedure sp_write (r : registers; wpr : watchpoint_registers;
s : out special_register_type; vwpr : out watchpoint_registers) is
variable op : std_logic_vector(1 downto 0);
variable op2 : std_logic_vector(2 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable i : integer range 0 to 3;
begin
op := r.x.ctrl.inst(31 downto 30);
op2 := r.x.ctrl.inst(24 downto 22);
op3 := r.x.ctrl.inst(24 downto 19);
s := r.w.s;
rd := r.x.ctrl.inst(29 downto 25);
vwpr := wpr;
case op is
when FMT3 =>
case op3 is
when WRY =>
if rd = "00000" then
s.y := r.x.result;
elsif MACEN and (rd = "10010") then
s.asr18 := r.x.result;
elsif (rd = "10001") then
if bp = 2 then s.dbp := r.x.result(27); end if;
s.dwt := r.x.result(14);
if (svt = 1) then s.svt := r.x.result(13); end if;
elsif rd(4 downto 3) = "11" then -- %ASR24 - %ASR31
case rd(2 downto 0) is
when "000" =>
vwpr(0).addr := r.x.result(31 downto 2);
vwpr(0).exec := r.x.result(0);
when "001" =>
vwpr(0).mask := r.x.result(31 downto 2);
vwpr(0).load := r.x.result(1);
vwpr(0).store := r.x.result(0);
when "010" =>
vwpr(1).addr := r.x.result(31 downto 2);
vwpr(1).exec := r.x.result(0);
when "011" =>
vwpr(1).mask := r.x.result(31 downto 2);
vwpr(1).load := r.x.result(1);
vwpr(1).store := r.x.result(0);
when "100" =>
vwpr(2).addr := r.x.result(31 downto 2);
vwpr(2).exec := r.x.result(0);
when "101" =>
vwpr(2).mask := r.x.result(31 downto 2);
vwpr(2).load := r.x.result(1);
vwpr(2).store := r.x.result(0);
when "110" =>
vwpr(3).addr := r.x.result(31 downto 2);
vwpr(3).exec := r.x.result(0);
when others => -- "111"
vwpr(3).mask := r.x.result(31 downto 2);
vwpr(3).load := r.x.result(1);
vwpr(3).store := r.x.result(0);
end case;
end if;
when WRPSR =>
s.cwp := r.x.result(NWINLOG2-1 downto 0);
s.icc := r.x.result(23 downto 20);
s.ec := r.x.result(13);
if FPEN then s.ef := r.x.result(12); end if;
s.pil := r.x.result(11 downto 8);
s.s := r.x.result(7);
s.ps := r.x.result(6);
s.et := r.x.result(5);
when WRWIM =>
s.wim := r.x.result(NWIN-1 downto 0);
when WRTBR =>
s.tba := r.x.result(31 downto 12);
when SAVE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then s.cwp := CWPMAX;
else s.cwp := r.w.s.cwp - 1 ; end if;
when RESTORE =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
when RETT =>
if (not CWPOPT) and (r.w.s.cwp = CWPMAX) then s.cwp := CWPMIN;
else s.cwp := r.w.s.cwp + 1; end if;
s.s := r.w.s.ps;
s.et := '1';
when others => null;
end case;
when others => null;
end case;
if r.x.ctrl.wicc = '1' then s.icc := r.x.icc; end if;
if r.x.ctrl.wy = '1' then s.y := r.x.y; end if;
if MACPIPE and (r.x.mac = '1') then
s.asr18 := mulo.result(31 downto 0);
s.y := mulo.result(63 downto 32);
end if;
end;
function npc_find (r : registers) return std_logic_vector is
variable npc : std_logic_vector(2 downto 0);
begin
npc := "011";
if r.m.ctrl.pv = '1' then npc := "000";
elsif r.e.ctrl.pv = '1' then npc := "001";
elsif r.a.ctrl.pv = '1' then npc := "010";
elsif r.d.pv = '1' then npc := "011";
elsif v8 /= 0 then npc := "100"; end if;
return(npc);
end;
function npc_gen (r : registers) return word is
variable npc : std_logic_vector(31 downto 0);
begin
npc := r.a.ctrl.pc(31 downto 2) & "00";
case r.x.npc is
when "000" => npc(31 downto 2) := r.x.ctrl.pc(31 downto 2);
when "001" => npc(31 downto 2) := r.m.ctrl.pc(31 downto 2);
when "010" => npc(31 downto 2) := r.e.ctrl.pc(31 downto 2);
when "011" => npc(31 downto 2) := r.a.ctrl.pc(31 downto 2);
when others =>
if v8 /= 0 then npc(31 downto 2) := r.d.pc(31 downto 2); end if;
end case;
return(npc);
end;
procedure mul_res(r : registers; asr18in : word; result, y, asr18 : out word;
icc : out std_logic_vector(3 downto 0)) is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
begin
op := r.m.ctrl.inst(31 downto 30); op3 := r.m.ctrl.inst(24 downto 19);
result := r.m.result; y := r.m.y; icc := r.m.icc; asr18 := asr18in;
case op is
when FMT3 =>
case op3 is
when UMUL | SMUL =>
if MULEN then
result := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UMULCC | SMULCC =>
if MULEN then
result := mulo.result(31 downto 0); icc := mulo.icc;
y := mulo.result(63 downto 32);
end if;
when UMAC | SMAC =>
if MACEN and not MACPIPE then
result := mulo.result(31 downto 0);
asr18 := mulo.result(31 downto 0);
y := mulo.result(63 downto 32);
end if;
when UDIV | SDIV =>
if DIVEN then
result := divo.result(31 downto 0);
end if;
when UDIVCC | SDIVCC =>
if DIVEN then
result := divo.result(31 downto 0); icc := divo.icc;
end if;
when others => null;
end case;
when others => null;
end case;
end;
function powerdwn(r : registers; trap : std_ulogic; rp : pwd_register_type) return std_ulogic is
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable rd : std_logic_vector(4 downto 0);
variable pd : std_ulogic;
begin
op := r.x.ctrl.inst(31 downto 30);
op3 := r.x.ctrl.inst(24 downto 19);
rd := r.x.ctrl.inst(29 downto 25);
pd := '0';
if (not (r.x.ctrl.annul or trap) and r.x.ctrl.pv) = '1' then
if ((op = FMT3) and (op3 = WRY) and (rd = "10011")) then pd := '1'; end if;
pd := pd or rp.pwd;
end if;
return(pd);
end;
signal dummy : std_ulogic;
signal cpu_index : std_logic_vector(3 downto 0);
signal disasen : std_ulogic;
begin
BPRED <= '0' when bp = 0 else '1' when bp = 1 else not r.w.s.dbp;
comb : process(ico, dco, rfo, r, wpr, ir, dsur, rstn, holdn, irqi, dbgi, fpo, cpo, tbo,
mulo, divo, dummy, rp, BPRED)
variable v : registers;
variable vp : pwd_register_type;
variable vwpr : watchpoint_registers;
variable vdsu : dsu_registers;
variable fe_pc, fe_npc : std_logic_vector(31 downto PCLOW);
variable npc : std_logic_vector(31 downto PCLOW);
variable de_raddr1, de_raddr2 : std_logic_vector(9 downto 0);
variable de_rs2, de_rd : std_logic_vector(4 downto 0);
variable de_hold_pc, de_branch, de_ldlock : std_ulogic;
variable de_cwp, de_cwp2 : cwptype;
variable de_inull : std_ulogic;
variable de_ren1, de_ren2 : std_ulogic;
variable de_wcwp : std_ulogic;
variable de_inst : word;
variable de_icc : std_logic_vector(3 downto 0);
variable de_fbranch, de_cbranch : std_ulogic;
variable de_rs1mod : std_ulogic;
variable de_bpannul : std_ulogic;
variable de_fins_hold : std_ulogic;
variable de_iperr : std_ulogic;
variable ra_op1, ra_op2 : word;
variable ra_div : std_ulogic;
variable ra_bpmiss : std_ulogic;
variable ra_bpannul : std_ulogic;
variable ex_jump, ex_link_pc : std_ulogic;
variable ex_jump_address : pctype;
variable ex_add_res : std_logic_vector(32 downto 0);
variable ex_shift_res, ex_logic_res, ex_misc_res : word;
variable ex_edata, ex_edata2 : word;
variable ex_dci : dc_in_type;
variable ex_force_a2, ex_load, ex_ymsb : std_ulogic;
variable ex_op1, ex_op2, ex_result, ex_result2, ex_result3, mul_op2 : word;
variable ex_shcnt : std_logic_vector(4 downto 0);
variable ex_dsuen : std_ulogic;
variable ex_ldbp2 : std_ulogic;
variable ex_sari : std_ulogic;
variable ex_bpmiss : std_ulogic;
variable ex_cdata : std_logic_vector(31 downto 0);
variable ex_mulop1, ex_mulop2 : std_logic_vector(32 downto 0);
variable me_bp_res : word;
variable me_inull, me_nullify, me_nullify2 : std_ulogic;
variable me_iflush : std_ulogic;
variable me_newtt : std_logic_vector(5 downto 0);
variable me_asr18 : word;
variable me_signed : std_ulogic;
variable me_size, me_laddr : std_logic_vector(1 downto 0);
variable me_icc : std_logic_vector(3 downto 0);
variable xc_result : word;
variable xc_df_result : word;
variable xc_waddr : std_logic_vector(9 downto 0);
variable xc_exception, xc_wreg : std_ulogic;
variable xc_trap_address : pctype;
variable xc_newtt, xc_vectt : std_logic_vector(7 downto 0);
variable xc_trap : std_ulogic;
variable xc_fpexack : std_ulogic;
variable xc_rstn, xc_halt : std_ulogic;
variable diagdata : word;
variable tbufi : tracebuf_in_type;
variable dbgm : std_ulogic;
variable fpcdbgwr : std_ulogic;
variable vfpi : fpc_in_type;
variable dsign : std_ulogic;
variable pwrd, sidle : std_ulogic;
variable vir : irestart_register;
variable xc_dflushl : std_ulogic;
variable xc_dcperr : std_ulogic;
variable st : std_ulogic;
variable icnt, fcnt : std_ulogic;
variable tbufcntx : std_logic_vector(TBUFBITS-1 downto 0);
variable bpmiss : std_ulogic;
begin
v := r; vwpr := wpr; vdsu := dsur; vp := rp;
xc_fpexack := '0'; sidle := '0';
fpcdbgwr := '0'; vir := ir; xc_rstn := rstn;
-----------------------------------------------------------------------
-- EXCEPTION STAGE
-----------------------------------------------------------------------
xc_exception := '0'; xc_halt := '0'; icnt := '0'; fcnt := '0';
xc_waddr := (others => '0');
xc_waddr(RFBITS-1 downto 0) := r.x.ctrl.rd(RFBITS-1 downto 0);
xc_trap := r.x.mexc or r.x.ctrl.trap;
v.x.nerror := rp.error; xc_dflushl := '0';
if r.x.mexc = '1' then xc_vectt := "00" & TT_DAEX;
elsif r.x.ctrl.tt = TT_TICC then
xc_vectt := '1' & r.x.result(6 downto 0);
else xc_vectt := "00" & r.x.ctrl.tt; end if;
if r.w.s.svt = '0' then
xc_trap_address(31 downto 2) := r.w.s.tba & xc_vectt & "00";
else
xc_trap_address(31 downto 2) := r.w.s.tba & "00000000" & "00";
end if;
xc_trap_address(2 downto PCLOW) := (others => '0');
xc_wreg := '0'; v.x.annul_all := '0';
if (not r.x.ctrl.annul and r.x.ctrl.ld) = '1' then
if (lddel = 2) then
xc_result := ld_align(r.x.data, r.x.set, r.x.dci.size, r.x.laddr, r.x.dci.signed);
else
xc_result := r.x.data(0);
end if;
elsif MACEN and MACPIPE and ((not r.x.ctrl.annul and r.x.mac) = '1') then
xc_result := mulo.result(31 downto 0);
else xc_result := r.x.result; end if;
xc_df_result := xc_result;
if DBGUNIT
then
dbgm := dbgexc(r, dbgi, xc_trap, xc_vectt);
if (dbgi.dsuen and dbgi.dbreak) = '0'then v.x.debug := '0'; end if;
else dbgm := '0'; v.x.debug := '0'; end if;
if PWRD2 then pwrd := powerdwn(r, xc_trap, rp); else pwrd := '0'; end if;
case r.x.rstate is
when run =>
if (dbgm
) /= '0' then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1;
v.x.debug := '1';
v.x.npc := npc_find(r);
vdsu.tt := xc_vectt; vdsu.err := dbgerr(r, dbgi, xc_vectt);
elsif (pwrd = '1') and (ir.pwd = '0') then
v.x.annul_all := '1'; vir.addr := r.x.ctrl.pc;
v.x.rstate := dsu1; v.x.npc := npc_find(r); vp.pwd := '1';
elsif (r.x.ctrl.annul or xc_trap) = '0' then
xc_wreg := r.x.ctrl.wreg;
sp_write (r, wpr, v.w.s, vwpr);
vir.pwd := '0';
if (r.x.ctrl.pv and not r.x.debug) = '1' then
icnt := holdn;
if (r.x.ctrl.inst(31 downto 30) = FMT3) and
((r.x.ctrl.inst(24 downto 19) = FPOP1) or
(r.x.ctrl.inst(24 downto 19) = FPOP2))
then fcnt := holdn; end if;
end if;
elsif ((not r.x.ctrl.annul) and xc_trap) = '1' then
xc_exception := '1'; xc_result := r.x.ctrl.pc(31 downto 2) & "00";
xc_wreg := '1'; v.w.s.tt := xc_vectt; v.w.s.ps := r.w.s.s;
v.w.s.s := '1'; v.x.annul_all := '1'; v.x.rstate := trap;
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0001";
v.x.npc := npc_find(r);
fpexack(r, xc_fpexack);
if r.w.s.et = '0' then
-- v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
xc_wreg := '0';
end if;
end if;
when trap =>
xc_result := npc_gen(r); xc_wreg := '1';
xc_waddr := (others => '0');
xc_waddr(NWINLOG2 + 3 downto 0) := r.w.s.cwp & "0010";
if r.w.s.et = '1' then
v.w.s.et := '0'; v.x.rstate := run;
if (not CWPOPT) and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := CWPMAX;
else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
else
v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
end if;
when dsu1 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0)
then
xc_trap_address(31 downto PCLOW) := ir.addr;
vir.addr := npc_gen(r)(31 downto PCLOW);
v.x.rstate := dsu2;
end if;
if DBGUNIT then v.x.debug := r.x.debug; end if;
when dsu2 =>
xc_exception := '1'; v.x.annul_all := '1';
xc_trap_address(31 downto PCLOW) := r.f.pc;
if DBGUNIT or PWRD2 or (smp /= 0)
then
sidle := (rp.pwd or rp.error) and ico.idle and dco.idle and not r.x.debug;
if DBGUNIT then
if dbgi.reset = '1' then
if smp /=0 then vp.pwd := not irqi.run; else vp.pwd := '0'; end if;
vp.error := '0';
end if;
if (dbgi.dsuen and dbgi.dbreak) = '1'then v.x.debug := '1'; end if;
diagwr(r, dsur, ir, dbgi, wpr, v.w.s, vwpr, vdsu.asi, xc_trap_address,
vir.addr, vdsu.tbufcnt, xc_wreg, xc_waddr, xc_result, fpcdbgwr);
xc_halt := dbgi.halt;
end if;
if r.x.ipend = '1' then vp.pwd := '0'; end if;
if (rp.error or rp.pwd or r.x.debug or xc_halt) = '0' then
v.x.rstate := run; v.x.annul_all := '0'; vp.error := '0';
xc_trap_address(31 downto PCLOW) := ir.addr; v.x.debug := '0';
vir.pwd := '1';
end if;
if (smp /= 0) and (irqi.rst = '1') then
vp.pwd := '0'; vp.error := '0';
end if;
end if;
when others =>
end case;
dci.flushl <= xc_dflushl;
irq_intack(r, holdn, v.x.intack);
itrace(r, dsur, vdsu, xc_result, xc_exception, dbgi, rp.error, xc_trap, tbufcntx, tbufi, '0', xc_dcperr);
vdsu.tbufcnt := tbufcntx;
v.w.except := xc_exception; v.w.result := xc_result;
if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
v.w.wa := xc_waddr(RFBITS-1 downto 0); v.w.wreg := xc_wreg and holdn;
rfi.diag <= dco.testen & dco.scanen & "00";
rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
irqo.intack <= r.x.intack and holdn;
irqo.irl <= r.w.s.tt(3 downto 0);
irqo.pwd <= rp.pwd;
irqo.fpen <= r.w.s.ef;
irqo.idle <= '0';
dbgo.halt <= xc_halt;
dbgo.pwd <= rp.pwd;
dbgo.idle <= sidle;
dbgo.icnt <= icnt;
dbgo.fcnt <= fcnt;
dbgo.optype <= r.x.ctrl.inst(31 downto 30) & r.x.ctrl.inst(24 downto 21);
dci.intack <= r.x.intack and holdn;
if (not RESET_ALL) and (xc_rstn = '0') then
v.w.except := RRES.w.except; v.w.s.et := RRES.w.s.et;
v.w.s.svt := RRES.w.s.svt; v.w.s.dwt := RRES.w.s.dwt;
v.w.s.ef := RRES.w.s.ef;
if need_extra_sync_reset(fabtech) /= 0 then
v.w.s.cwp := RRES.w.s.cwp;
v.w.s.icc := RRES.w.s.icc;
end if;
v.w.s.dbp := RRES.w.s.dbp;
v.x.ipmask := RRES.x.ipmask;
v.w.s.tba := RRES.w.s.tba;
v.x.annul_all := RRES.x.annul_all;
v.x.rstate := RRES.x.rstate; vir.pwd := IRES.pwd;
vp.pwd := PRES.pwd; v.x.debug := RRES.x.debug;
v.x.nerror := RRES.x.nerror;
if svt = 1 then v.w.s.tt := RRES.w.s.tt; end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
v.x.rstate := dsu1; v.x.debug := '1';
end if;
end if;
if (index /= 0) and (irqi.run = '0') and (rstn = '0') then
v.x.rstate := dsu1; vp.pwd := '1';
end if;
v.x.npc := "100";
end if;
-- kill off unused regs
if not FPEN then v.w.s.ef := '0'; end if;
if not CPEN then v.w.s.ec := '0'; end if;
-----------------------------------------------------------------------
-- MEMORY STAGE
-----------------------------------------------------------------------
v.x.ctrl := r.m.ctrl; v.x.dci := r.m.dci;
v.x.ctrl.rett := r.m.ctrl.rett and not r.m.ctrl.annul;
v.x.mac := r.m.mac; v.x.laddr := r.m.result(1 downto 0);
v.x.ctrl.annul := r.m.ctrl.annul or v.x.annul_all;
st := '0';
if CASAEN and (r.m.casa = '1') and (r.m.ctrl.cnt = "00") then
v.x.ctrl.inst(4 downto 0) := r.a.ctrl.inst(4 downto 0); -- restore rs2 for trace log
end if;
mul_res(r, v.w.s.asr18, v.x.result, v.x.y, me_asr18, me_icc);
mem_trap(r, wpr, v.x.ctrl.annul, holdn, v.x.ctrl.trap, me_iflush,
me_nullify, v.m.werr, v.x.ctrl.tt);
me_newtt := v.x.ctrl.tt;
irq_trap(r, ir, irqi.irl, v.x.ctrl.annul, v.x.ctrl.pv, v.x.ctrl.trap, me_newtt, me_nullify,
v.m.irqen, v.m.irqen2, me_nullify2, v.x.ctrl.trap,
v.x.ipend, v.x.ctrl.tt);
if (r.m.ctrl.ld or st or not dco.mds) = '1' then
for i in 0 to dsets-1 loop
v.x.data(i) := dco.data(i);
end loop;
v.x.set := dco.set(DSETMSB downto 0);
if dco.mds = '0' then
me_size := r.x.dci.size; me_laddr := r.x.laddr; me_signed := r.x.dci.signed;
else
me_size := v.x.dci.size; me_laddr := v.x.laddr; me_signed := v.x.dci.signed;
end if;
if (lddel /= 2) then
v.x.data(0) := ld_align(v.x.data, v.x.set, me_size, me_laddr, me_signed);
end if;
end if;
if (not RESET_ALL) and (is_fpga(fabtech) = 0) and (xc_rstn = '0') then
v.x.data := (others => (others => '0')); --v.x.ldc := '0';
end if;
v.x.mexc := dco.mexc;
v.x.icc := me_icc;
v.x.ctrl.wicc := r.m.ctrl.wicc and not v.x.annul_all;
if MACEN and ((v.x.ctrl.annul or v.x.ctrl.trap) = '0') then
v.w.s.asr18 := me_asr18;
end if;
if (r.x.rstate = dsu2)
then
me_nullify2 := '0'; v.x.set := dco.set(DSETMSB downto 0);
end if;
if (not RESET_ALL) and (xc_rstn = '0') then
v.x.ctrl.trap := '0'; v.x.ctrl.annul := '1';
end if;
dci.maddress <= r.m.result;
dci.enaddr <= r.m.dci.enaddr;
dci.asi <= r.m.dci.asi;
dci.size <= r.m.dci.size;
dci.lock <= (r.m.dci.lock and not r.m.ctrl.annul);
dci.read <= r.m.dci.read;
dci.write <= r.m.dci.write;
dci.flush <= me_iflush;
dci.dsuen <= r.m.dci.dsuen;
dci.msu <= r.m.su;
dci.esu <= r.e.su;
dbgo.ipend <= v.x.ipend;
-----------------------------------------------------------------------
-- EXECUTE STAGE
-----------------------------------------------------------------------
v.m.ctrl := r.e.ctrl; ex_op1 := r.e.op1; ex_op2 := r.e.op2;
v.m.ctrl.rett := r.e.ctrl.rett and not r.e.ctrl.annul;
v.m.ctrl.wreg := r.e.ctrl.wreg and not v.x.annul_all;
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
v.m.su := r.e.su;
if MULTYPE = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
if lddel = 1 then
if r.e.ldbp1 = '1' then
ex_op1 := r.x.data(0);
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
end if;
if r.e.ldbp2 = '1' then
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
if r.e.invop2 = '1' then
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
end if;
end if;
end if;
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
else v.m.nalign := '1'; end if;
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load, v.m.casa);
ex_jump_address := ex_add_res(32 downto PCLOW+1);
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, ex_misc_res, ex_edata);
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz, v.m.casaz);
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, ex_result3);
v.m.result := ex_result3;
cwp_ex(r, v.m.wcwp);
if CASAEN and (r.e.ctrl.cnt = "10") and ((r.m.casa and not v.m.casaz) = '1') then
me_nullify2 := '1';
end if;
dci.nullify <= me_nullify2;
ex_mulop1 := (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
ex_mulop2 := (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
if is_fpga(fabtech) = 0 and (r.e.mul = '0') then -- power-save for mul
-- if (r.e.mul = '0') then
ex_mulop1 := (others => '0'); ex_mulop2 := (others => '0');
end if;
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
v.m.mac := r.e.mac;
if (DBGUNIT and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
dci.eenaddr <= v.m.dci.enaddr;
dci.eaddress <= ex_add_res(32 downto 1);
dci.edata <= ex_edata2;
bp_miss_ex(r, r.m.icc, ex_bpmiss, ra_bpannul);
-----------------------------------------------------------------------
-- REGFILE STAGE
-----------------------------------------------------------------------
v.e.ctrl := r.a.ctrl; v.e.jmpl := r.a.jmpl and not r.a.ctrl.trap;
v.e.ctrl.annul := r.a.ctrl.annul or ra_bpannul or v.x.annul_all;
v.e.ctrl.rett := r.a.ctrl.rett and not r.a.ctrl.annul and not r.a.ctrl.trap;
v.e.ctrl.wreg := r.a.ctrl.wreg and not (ra_bpannul or v.x.annul_all);
v.e.su := r.a.su; v.e.et := r.a.et;
v.e.ctrl.wicc := r.a.ctrl.wicc and not (ra_bpannul or v.x.annul_all);
v.e.rfe1 := r.a.rfe1; v.e.rfe2 := r.a.rfe2;
exception_detect(r, wpr, dbgi, r.a.ctrl.trap, r.a.ctrl.tt,
v.e.ctrl.trap, v.e.ctrl.tt);
op_mux(r, rfo.data1, ex_result3, v.x.result, xc_df_result, zero32,
r.a.rsel1, v.e.ldbp1, ra_op1, '0');
op_mux(r, rfo.data2, ex_result3, v.x.result, xc_df_result, r.a.imm,
r.a.rsel2, ex_ldbp2, ra_op2, '1');
alu_op(r, ra_op1, ra_op2, v.m.icc, v.m.y(0), ex_ldbp2, v.e.op1, v.e.op2,
v.e.aluop, v.e.alusel, v.e.aluadd, v.e.shcnt, v.e.sari, v.e.shleft,
v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2
);
cin_gen(r, v.m.icc(0), v.e.alucin);
bp_miss_ra(r, ra_bpmiss, de_bpannul);
v.e.bp := r.a.bp and not ra_bpmiss;
-----------------------------------------------------------------------
-- DECODE STAGE
-----------------------------------------------------------------------
if ISETS > 1 then de_inst := r.d.inst(conv_integer(r.d.set));
else de_inst := r.d.inst(0); end if;
de_icc := r.m.icc; v.a.cwp := r.d.cwp;
su_et_select(r, v.w.s.ps, v.w.s.s, v.w.s.et, v.a.su, v.a.et);
wicc_y_gen(de_inst, v.a.ctrl.wicc, v.a.ctrl.wy);
cwp_ctrl(r, v.w.s.wim, de_inst, de_cwp, v.a.wovf, v.a.wunf, de_wcwp);
if CASAEN and (de_inst(31 downto 30) = LDST) and (de_inst(24 downto 19) = CASA) then
case r.d.cnt is
when "00" | "01" => de_inst(4 downto 0) := "00000"; -- rs2=0
when others =>
end case;
end if;
rs1_gen(r, de_inst, v.a.rs1, de_rs1mod);
de_rs2 := de_inst(4 downto 0);
de_raddr1 := (others => '0'); de_raddr2 := (others => '0');
if RS1OPT then
if de_rs1mod = '1' then
regaddr(r.d.cwp, de_inst(29 downto 26) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
else
regaddr(r.d.cwp, de_inst(18 downto 15) & v.a.rs1(0), de_raddr1(RFBITS-1 downto 0));
end if;
else
regaddr(r.d.cwp, v.a.rs1, de_raddr1(RFBITS-1 downto 0));
end if;
regaddr(r.d.cwp, de_rs2, de_raddr2(RFBITS-1 downto 0));
v.a.rfa1 := de_raddr1(RFBITS-1 downto 0);
v.a.rfa2 := de_raddr2(RFBITS-1 downto 0);
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd);
regaddr(de_cwp, de_rd, v.a.ctrl.rd);
fpbranch(de_inst, fpo.cc, de_fbranch);
fpbranch(de_inst, cpo.cc, de_cbranch);
v.a.imm := imm_data(r, de_inst);
de_iperr := '0';
lock_gen(r, de_rs2, de_rd, v.a.rfa1, v.a.rfa2, v.a.ctrl.rd, de_inst,
fpo.ldlock, v.e.mul, ra_div, de_wcwp, v.a.ldcheck1, v.a.ldcheck2, de_ldlock,
v.a.ldchkra, v.a.ldchkex, v.a.bp, v.a.nobp, de_fins_hold, de_iperr);
ic_ctrl(r, de_inst, v.x.annul_all, de_ldlock, branch_true(de_icc, de_inst),
de_fbranch, de_cbranch, fpo.ccv, cpo.ccv, v.d.cnt, v.d.pc, de_branch,
v.a.ctrl.annul, v.d.annul, v.a.jmpl, de_inull, v.d.pv, v.a.ctrl.pv,
de_hold_pc, v.a.ticc, v.a.ctrl.rett, v.a.mulstart, v.a.divstart,
ra_bpmiss, ex_bpmiss, de_iperr);
v.a.bp := v.a.bp and not v.a.ctrl.annul;
v.a.nobp := v.a.nobp and not v.a.ctrl.annul;
v.a.ctrl.inst := de_inst;
cwp_gen(r, v, v.a.ctrl.annul, de_wcwp, de_cwp, v.d.cwp);
v.d.inull := ra_inull_gen(r, v);
op_find(r, v.a.ldchkra, v.a.ldchkex, v.a.rs1, v.a.rfa1,
false, v.a.rfe1, v.a.rsel1, v.a.ldcheck1);
op_find(r, v.a.ldchkra, v.a.ldchkex, de_rs2, v.a.rfa2,
imm_select(de_inst), v.a.rfe2, v.a.rsel2, v.a.ldcheck2);
v.a.ctrl.wicc := v.a.ctrl.wicc and (not v.a.ctrl.annul)
;
v.a.ctrl.wreg := v.a.ctrl.wreg and (not v.a.ctrl.annul)
;
v.a.ctrl.rett := v.a.ctrl.rett and (not v.a.ctrl.annul)
;
v.a.ctrl.wy := v.a.ctrl.wy and (not v.a.ctrl.annul)
;
v.a.ctrl.trap := r.d.mexc
;
v.a.ctrl.tt := "000000";
if r.d.mexc = '1' then
v.a.ctrl.tt := "000001";
end if;
v.a.ctrl.pc := r.d.pc;
v.a.ctrl.cnt := r.d.cnt;
v.a.step := r.d.step;
if holdn = '0' then
de_raddr1(RFBITS-1 downto 0) := r.a.rfa1;
de_raddr2(RFBITS-1 downto 0) := r.a.rfa2;
de_ren1 := r.a.rfe1; de_ren2 := r.a.rfe2;
else
de_ren1 := v.a.rfe1; de_ren2 := v.a.rfe2;
end if;
if DBGUNIT then
if (dbgi.denable = '1') and (r.x.rstate = dsu2) then
de_raddr1(RFBITS-1 downto 0) := dbgi.daddr(RFBITS+1 downto 2); de_ren1 := '1';
de_raddr2 := de_raddr1; de_ren2 := '1';
end if;
v.d.step := dbgi.step and not r.d.annul;
end if;
rfi.wren <= (xc_wreg and holdn) and not dco.scanen;
rfi.raddr1 <= de_raddr1; rfi.raddr2 <= de_raddr2;
rfi.ren1 <= de_ren1 and not dco.scanen;
rfi.ren2 <= de_ren2 and not dco.scanen;
ici.inull <= de_inull
;
ici.flush <= me_iflush;
v.d.divrdy := divo.nready;
ici.fline <= r.x.ctrl.pc(31 downto 3);
dbgo.bpmiss <= bpmiss and holdn;
if (xc_rstn = '0') then
v.d.cnt := (others => '0');
if need_extra_sync_reset(fabtech) /= 0 then
v.d.cwp := (others => '0');
end if;
end if;
-----------------------------------------------------------------------
-- FETCH STAGE
-----------------------------------------------------------------------
bpmiss := ex_bpmiss or ra_bpmiss;
npc := r.f.pc; fe_pc := r.f.pc;
if ra_bpmiss = '1' then fe_pc := r.d.pc; end if;
if ex_bpmiss = '1' then fe_pc := r.a.ctrl.pc; end if;
fe_npc := zero32(31 downto PCLOW);
fe_npc(31 downto 2) := fe_pc(31 downto 2) + 1; -- Address incrementer
if (xc_rstn = '0') then
if (not RESET_ALL) then
v.f.pc := (others => '0'); v.f.branch := '0';
if DYNRST then v.f.pc(31 downto 12) := irqi.rstvec;
else
v.f.pc(31 downto 12) := conv_std_logic_vector(rstaddr, 20);
end if;
end if;
elsif xc_exception = '1' then -- exception
v.f.branch := '1'; v.f.pc := xc_trap_address;
npc := v.f.pc;
elsif de_hold_pc = '1' then
v.f.pc := r.f.pc; v.f.branch := r.f.branch;
if bpmiss = '1' then
v.f.pc := fe_npc; v.f.branch := '1';
npc := v.f.pc;
elsif ex_jump = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
end if;
elsif (ex_jump and not bpmiss) = '1' then
v.f.pc := ex_jump_address; v.f.branch := '1';
npc := v.f.pc;
elsif (de_branch and not bpmiss
) = '1'
then
v.f.pc := branch_address(de_inst, r.d.pc); v.f.branch := '1';
npc := v.f.pc;
else
v.f.branch := bpmiss; v.f.pc := fe_npc; npc := v.f.pc;
end if;
ici.dpc <= r.d.pc(31 downto 2) & "00";
ici.fpc <= r.f.pc(31 downto 2) & "00";
ici.rpc <= npc(31 downto 2) & "00";
ici.fbranch <= r.f.branch;
ici.rbranch <= v.f.branch;
ici.su <= v.a.su;
if (ico.mds and de_hold_pc) = '0' then
for i in 0 to isets-1 loop
v.d.inst(i) := ico.data(i); -- latch instruction
end loop;
v.d.set := ico.set(ISETMSB downto 0); -- latch instruction
v.d.mexc := ico.mexc; -- latch instruction
end if;
-----------------------------------------------------------------------
-----------------------------------------------------------------------
if DBGUNIT then -- DSU diagnostic read
diagread(dbgi, r, dsur, ir, wpr, dco, tbo, diagdata);
diagrdy(dbgi.denable, dsur, r.m.dci, dco.mds, ico, vdsu.crdy);
end if;
-----------------------------------------------------------------------
-- OUTPUTS
-----------------------------------------------------------------------
rin <= v; wprin <= vwpr; dsuin <= vdsu; irin <= vir;
muli.start <= r.a.mulstart and not r.a.ctrl.annul and
not r.a.ctrl.trap and not ra_bpannul;
muli.signed <= r.e.ctrl.inst(19);
muli.op1 <= ex_mulop1; --(ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
muli.op2 <= ex_mulop2; --(mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
muli.mac <= r.e.ctrl.inst(24);
if MACPIPE then muli.acc(39 downto 32) <= r.w.s.y(7 downto 0);
else muli.acc(39 downto 32) <= r.x.y(7 downto 0); end if;
muli.acc(31 downto 0) <= r.w.s.asr18;
muli.flush <= r.x.annul_all;
divi.start <= r.a.divstart and not r.a.ctrl.annul and
not r.a.ctrl.trap and not ra_bpannul;
divi.signed <= r.e.ctrl.inst(19);
divi.flush <= r.x.annul_all;
divi.op1 <= (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
divi.op2 <= (ex_op2(31) and r.e.ctrl.inst(19)) & ex_op2;
if (r.a.divstart and not r.a.ctrl.annul) = '1' then
dsign := r.a.ctrl.inst(19);
else dsign := r.e.ctrl.inst(19); end if;
divi.y <= (r.m.y(31) and dsign) & r.m.y;
rpin <= vp;
if DBGUNIT then
dbgo.dsu <= '1'; dbgo.dsumode <= r.x.debug; dbgo.crdy <= dsur.crdy(2);
dbgo.data <= diagdata;
if TRACEBUF then tbi <= tbufi; else
tbi.addr <= (others => '0'); tbi.data <= (others => '0');
tbi.enable <= '0'; tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
else
dbgo.dsu <= '0'; dbgo.data <= (others => '0'); dbgo.crdy <= '0';
dbgo.dsumode <= '0'; tbi.addr <= (others => '0');
tbi.data <= (others => '0'); tbi.enable <= '0';
tbi.write <= (others => '0'); tbi.diag <= "0000";
end if;
dbgo.error <= dummy and not r.x.nerror;
dbgo.wbhold <= '0'; --dco.wbhold;
dbgo.su <= r.w.s.s;
dbgo.istat <= ('0', '0', '0', '0');
dbgo.dstat <= ('0', '0', '0', '0');
if FPEN then
if (r.x.rstate = dsu2) then vfpi.flush := '1'; else vfpi.flush := v.x.annul_all and holdn; end if;
vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
vfpi.d.cnt := r.d.cnt;
vfpi.d.annul := v.x.annul_all or de_bpannul or r.d.annul or de_fins_hold
;
vfpi.d.trap := r.d.mexc;
vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto PCLOW) := r.d.pc(31 downto PCLOW);
vfpi.d.pv := r.d.pv;
vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto PCLOW) := r.a.ctrl.pc(31 downto PCLOW);
vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
vfpi.a.annul := r.a.ctrl.annul or (ex_bpmiss and r.e.ctrl.inst(29))
;
vfpi.a.pv := r.a.ctrl.pv;
vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
vfpi.e.pv := r.e.ctrl.pv;
vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto PCLOW) := r.m.ctrl.pc(31 downto PCLOW);
vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
vfpi.m.pv := r.m.ctrl.pv;
vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto PCLOW) := r.x.ctrl.pc(31 downto PCLOW);
vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv;
if (lddel = 2) then vfpi.lddata := r.x.data(conv_integer(r.x.set)); else vfpi.lddata := r.x.data(0); end if;
if (r.x.rstate = dsu2)
then vfpi.dbg.enable := dbgi.denable;
else vfpi.dbg.enable := '0'; end if;
vfpi.dbg.write := fpcdbgwr;
vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
vfpi.dbg.addr := dbgi.daddr(6 downto 2);
vfpi.dbg.data := dbgi.ddata;
fpi <= vfpi;
cpi <= vfpi; -- dummy, just to kill some warnings ...
end if;
end process;
preg : process (sclk)
begin
if rising_edge(sclk) then
rp <= rpin;
if rstn = '0' then
rp.error <= PRES.error;
if RESET_ALL then
if (index /= 0) and (irqi.run = '0') then
rp.pwd <= '1';
else
rp.pwd <= '0';
end if;
end if;
end if;
end if;
end process;
reg : process (clk)
begin
if rising_edge(clk) then
if (holdn = '1') then
r <= rin;
else
r.x.ipend <= rin.x.ipend;
r.m.werr <= rin.m.werr;
if (holdn or ico.mds) = '0' then
r.d.inst <= rin.d.inst; r.d.mexc <= rin.d.mexc;
r.d.set <= rin.d.set;
end if;
if (holdn or dco.mds) = '0' then
r.x.data <= rin.x.data; r.x.mexc <= rin.x.mexc;
r.x.set <= rin.x.set;
end if;
end if;
if rstn = '0' then
if RESET_ALL then
r <= RRES;
if DYNRST then
r.f.pc(31 downto 12) <= irqi.rstvec;
r.w.s.tba <= irqi.rstvec;
end if;
if DBGUNIT then
if (dbgi.dsuen and dbgi.dbreak) = '1' then
r.x.rstate <= dsu1; r.x.debug <= '1';
end if;
end if;
if (index /= 0) and irqi.run = '0' then
r.x.rstate <= dsu1;
end if;
else
r.w.s.s <= '1'; r.w.s.ps <= '1';
if need_extra_sync_reset(fabtech) /= 0 then
r.d.inst <= (others => (others => '0'));
r.x.mexc <= '0';
end if;
end if;
end if;
end if;
end process;
dsugen : if DBGUNIT generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then
dsur <= dsuin;
else
dsur.crdy <= dsuin.crdy;
end if;
if rstn = '0' then
if RESET_ALL then
dsur <= DRES;
elsif need_extra_sync_reset(fabtech) /= 0 then
dsur.err <= '0'; dsur.tbufcnt <= (others => '0'); dsur.tt <= (others => '0');
dsur.asi <= (others => '0'); dsur.crdy <= (others => '0');
end if;
end if;
end if;
end process;
end generate;
nodsugen : if not DBGUNIT generate
dsur.err <= '0'; dsur.tbufcnt <= (others => '0'); dsur.tt <= (others => '0');
dsur.asi <= (others => '0'); dsur.crdy <= (others => '0');
end generate;
irreg : if DBGUNIT or PWRD2
generate
dsureg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then ir <= irin; end if;
if RESET_ALL and rstn = '0' then ir <= IRES; end if;
end if;
end process;
end generate;
nirreg : if not (DBGUNIT or PWRD2
)
generate
ir.pwd <= '0'; ir.addr <= (others => '0');
end generate;
wpgen : for i in 0 to 3 generate
wpg0 : if nwp > i generate
wpreg : process(clk) begin
if rising_edge(clk) then
if holdn = '1' then wpr(i) <= wprin(i); end if;
if rstn = '0' then
if RESET_ALL then
wpr(i) <= wpr_none;
else
wpr(i).exec <= '0'; wpr(i).load <= '0'; wpr(i).store <= '0';
end if;
end if;
end if;
end process;
end generate;
wpg1 : if nwp <= i generate
wpr(i) <= wpr_none;
end generate;
end generate;
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
begin
if (fpu /= 0) then
op := r.x.ctrl.inst(31 downto 30); op3 := r.x.ctrl.inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
else
fpins := false; fpld := false;
end if;
valid := (((not r.x.ctrl.annul) and r.x.ctrl.pv) = '1') and (not ((fpins or fpld) and (r.x.ctrl.trap = '0')));
valid := valid and (holdn = '1');
if (disas = 1) and rising_edge(clk) and (rstn = '1') then
print_insn (index, r.x.ctrl.pc(31 downto 2) & "00", r.x.ctrl.inst,
rin.w.result, valid, r.x.ctrl.trap = '1', rin.w.wreg = '1',
rin.x.ipmask = '1');
end if;
end process;
-- pragma translate_on
dis0 : if disas < 2 generate dummy <= '1'; end generate;
dis2 : if disas > 1 generate
disasen <= '1' when disas /= 0 else '0';
cpu_index <= conv_std_logic_vector(index, 4);
x0 : cpu_disasx
port map (clk, rstn, dummy, r.x.ctrl.inst, r.x.ctrl.pc(31 downto 2),
rin.w.result, cpu_index, rin.w.wreg, r.x.ctrl.annul, holdn,
r.x.ctrl.pv, r.x.ctrl.trap, disasen);
end generate;
end;
| gpl-2.0 | b118aba2ea90eba63d770d25d380ca2e | 0.513632 | 3.126139 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/6d4b02c9ba6a5d75/zqynq_lab_1_design_axi_gpio_1_0_sim_netlist.vhdl | 1 | 72,745 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:07:51 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_gpio_1_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_gpio_1_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
rst_reg : in STD_LOGIC;
bus2ip_rnw_i_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
\Not_Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
start2_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder is
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => start2_reg,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000E000000020"
)
port map (
I0 => \Not_Dual.gpio_Data_In_reg[0]\(4),
I1 => Q(0),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => Q(2),
I4 => Q(1),
I5 => gpio_io_t(4),
O => GPIO_DBus_i(0)
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000E000000020"
)
port map (
I0 => \Not_Dual.gpio_Data_In_reg[0]\(3),
I1 => Q(0),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => Q(2),
I4 => Q(1),
I5 => gpio_io_t(3),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000E000000020"
)
port map (
I0 => \Not_Dual.gpio_Data_In_reg[0]\(2),
I1 => Q(0),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => Q(2),
I4 => Q(1),
I5 => gpio_io_t(2),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000E000000020"
)
port map (
I0 => \Not_Dual.gpio_Data_In_reg[0]\(1),
I1 => Q(0),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => Q(2),
I4 => Q(1),
I5 => gpio_io_t(1),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => gpio_xferAck_Reg,
I3 => GPIO_xferAck_i,
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000E000000020"
)
port map (
I0 => \Not_Dual.gpio_Data_In_reg[0]\(0),
I1 => Q(0),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => Q(2),
I4 => Q(1),
I5 => gpio_io_t(0),
O => \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAABAA"
)
port map (
I0 => rst_reg,
I1 => bus2ip_rnw_i_reg,
I2 => Q(0),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => Q(2),
I5 => Q(1),
O => E(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(9),
O => D(4)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(8),
O => D(3)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(7),
O => D(2)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(6),
O => D(1)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(5),
O => D(0)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAABAAAAA"
)
port map (
I0 => rst_reg,
I1 => bus2ip_rnw_i_reg,
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => Q(2),
I4 => Q(0),
I5 => Q(1),
O => \Not_Dual.gpio_OE_reg[0]\(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => scndry_vect_out(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
port (
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 4 downto 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
\Not_Dual.gpio_Data_In_reg[4]_0\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\Not_Dual.gpio_Data_In_reg[3]_0\ : in STD_LOGIC;
\Not_Dual.gpio_Data_In_reg[2]_0\ : in STD_LOGIC;
\Not_Dual.gpio_Data_In_reg[1]_0\ : in STD_LOGIC;
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 0 to 0 );
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
rst_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 4 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair4";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus_i(0),
Q => D(4),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_Data_In_reg[1]_0\,
Q => D(3),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_Data_In_reg[2]_0\,
Q => D(2),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_Data_In_reg[3]_0\,
Q => D(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_Data_In_reg[4]_0\,
Q => D(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(4) => gpio_io_i_d2(0),
scndry_vect_out(3) => gpio_io_i_d2(1),
scndry_vect_out(2) => gpio_io_i_d2(2),
scndry_vect_out(1) => gpio_io_i_d2(3),
scndry_vect_out(0) => gpio_io_i_d2(4)
);
\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => Q(4),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => Q(3),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => Q(2),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => Q(1),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(4),
Q => Q(0),
R => '0'
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => gpio_io_o(4),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => gpio_io_o(3),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => gpio_io_o(2),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => gpio_io_o(1),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => gpio_io_o(0),
R => SS(0)
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => gpio_io_t(4),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => gpio_io_t(3),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => gpio_io_t(2),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => gpio_io_t(1),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => gpio_io_t(0),
S => SS(0)
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
port (
SR : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[27]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_data_out_reg[0]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \s_axi_rdata_i[4]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair1";
begin
\Not_Dual.gpio_Data_Out_reg[0]\ <= \^not_dual.gpio_data_out_reg[0]\;
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_address_decoder
port map (
D(4 downto 0) => D(4 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\,
\Not_Dual.gpio_Data_In_reg[0]\(4 downto 0) => Q(4 downto 0),
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(2) => bus2ip_addr(0),
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^not_dual.gpio_data_out_reg[0]\,
gpio_io_t(4 downto 0) => gpio_io_t(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
rst_reg => \^sr\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
s_axi_wready => \^s_axi_wready\,
start2_reg => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(5),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_data_out_reg[0]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_in,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[4]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[4]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[4]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[27]\(0),
Q => s_axi_rdata(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[4]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[27]\(1),
Q => s_axi_rdata(1),
R => \^sr\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[4]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[27]\(2),
Q => s_axi_rdata(2),
R => \^sr\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[4]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[27]\(3),
Q => s_axi_rdata(3),
R => \^sr\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[4]_i_1_n_0\,
D => \ip2bus_data_i_D1_reg[27]\(4),
Q => s_axi_rdata(4),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => p_0_out(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 4 downto 0 );
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[27]\ : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_slave_attachment
port map (
D(4 downto 0) => D(4 downto 0),
E(0) => E(0),
GPIO_DBus_i(0) => GPIO_DBus_i(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ => \Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => bus2ip_rnw,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(4 downto 0) => Q(4 downto 0),
SR => bus2ip_reset,
gpio_io_t(4 downto 0) => gpio_io_t(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[27]\(4 downto 0) => \ip2bus_data_i_D1_reg[27]\(4 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(4 downto 0) => s_axi_rdata(4 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 5;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is -1;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio : entity is "LOGICORE";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_10 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_19 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_6 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 4 );
signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 27 to 27 );
signal GPIO_xferAck_i : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 4 );
signal gpio_core_1_n_8 : STD_LOGIC;
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 27 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 27 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
gpio_io_t(4 downto 0) <= \^gpio_io_t\(4 downto 0);
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4 downto 0) <= \^s_axi_rdata\(4 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_lite_ipif
port map (
D(4) => DBus_Reg(0),
D(3) => DBus_Reg(1),
D(2) => DBus_Reg(2),
D(1) => DBus_Reg(3),
D(0) => DBus_Reg(4),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_DBus_i(0) => GPIO_DBus_i(27),
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[27]\ => AXI_LITE_IPIF_I_n_19,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[28]\ => AXI_LITE_IPIF_I_n_10,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[29]\ => AXI_LITE_IPIF_I_n_11,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[30]\ => AXI_LITE_IPIF_I_n_12,
\Not_Dual.ALLIN1_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[31]\ => AXI_LITE_IPIF_I_n_13,
\Not_Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_7,
Q(4) => gpio_Data_In(0),
Q(3) => gpio_Data_In(1),
Q(2) => gpio_Data_In(2),
Q(1) => gpio_Data_In(3),
Q(0) => gpio_Data_In(4),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_io_t(4 downto 0) => \^gpio_io_t\(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[27]\(4) => ip2bus_data_i_D1(27),
\ip2bus_data_i_D1_reg[27]\(3) => ip2bus_data_i_D1(28),
\ip2bus_data_i_D1_reg[27]\(2) => ip2bus_data_i_D1(29),
\ip2bus_data_i_D1_reg[27]\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[27]\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(4 downto 0) => \^s_axi_rdata\(4 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(9 downto 5) => s_axi_wdata(31 downto 27),
s_axi_wdata(4 downto 0) => s_axi_wdata(4 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
gpio_core_1: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_GPIO_Core
port map (
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_DBus_i(0) => GPIO_DBus_i(27),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4) => DBus_Reg(0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3) => DBus_Reg(1),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2) => DBus_Reg(2),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1) => DBus_Reg(3),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0) => DBus_Reg(4),
\Not_Dual.gpio_Data_In_reg[1]_0\ => AXI_LITE_IPIF_I_n_10,
\Not_Dual.gpio_Data_In_reg[2]_0\ => AXI_LITE_IPIF_I_n_11,
\Not_Dual.gpio_Data_In_reg[3]_0\ => AXI_LITE_IPIF_I_n_12,
\Not_Dual.gpio_Data_In_reg[4]_0\ => AXI_LITE_IPIF_I_n_13,
Q(4) => gpio_Data_In(0),
Q(3) => gpio_Data_In(1),
Q(2) => gpio_Data_In(2),
Q(1) => gpio_Data_In(3),
Q(0) => gpio_Data_In(4),
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_19,
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
gpio_io_o(4 downto 0) => gpio_io_o(4 downto 0),
gpio_io_t(4 downto 0) => \^gpio_io_t\(4 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_8,
rst_reg(0) => AXI_LITE_IPIF_I_n_7,
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_8,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_gpio_1_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_gpio,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 1;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 5;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(4 downto 0) => gpio_io_i(4 downto 0),
gpio_io_o(4 downto 0) => NLW_U0_gpio_io_o_UNCONNECTED(4 downto 0),
gpio_io_t(4 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(4 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 55864aae5d4f31a214008a3b6a149fab | 0.589814 | 2.600265 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/984e004bd8bf2d97/ip_design_processing_system7_0_0_sim_netlist.vhdl | 1 | 207,211 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:33 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_processing_system7_0_0_sim_netlist.vhdl
-- Design : ip_design_processing_system7_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
port (
CAN0_PHY_TX : out STD_LOGIC;
CAN0_PHY_RX : in STD_LOGIC;
CAN1_PHY_TX : out STD_LOGIC;
CAN1_PHY_RX : in STD_LOGIC;
ENET0_GMII_TX_EN : out STD_LOGIC;
ENET0_GMII_TX_ER : out STD_LOGIC;
ENET0_MDIO_MDC : out STD_LOGIC;
ENET0_MDIO_O : out STD_LOGIC;
ENET0_MDIO_T : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET0_GMII_COL : in STD_LOGIC;
ENET0_GMII_CRS : in STD_LOGIC;
ENET0_GMII_RX_CLK : in STD_LOGIC;
ENET0_GMII_RX_DV : in STD_LOGIC;
ENET0_GMII_RX_ER : in STD_LOGIC;
ENET0_GMII_TX_CLK : in STD_LOGIC;
ENET0_MDIO_I : in STD_LOGIC;
ENET0_EXT_INTIN : in STD_LOGIC;
ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_TX_EN : out STD_LOGIC;
ENET1_GMII_TX_ER : out STD_LOGIC;
ENET1_MDIO_MDC : out STD_LOGIC;
ENET1_MDIO_O : out STD_LOGIC;
ENET1_MDIO_T : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET1_SOF_RX : out STD_LOGIC;
ENET1_SOF_TX : out STD_LOGIC;
ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 );
ENET1_GMII_COL : in STD_LOGIC;
ENET1_GMII_CRS : in STD_LOGIC;
ENET1_GMII_RX_CLK : in STD_LOGIC;
ENET1_GMII_RX_DV : in STD_LOGIC;
ENET1_GMII_RX_ER : in STD_LOGIC;
ENET1_GMII_TX_CLK : in STD_LOGIC;
ENET1_MDIO_I : in STD_LOGIC;
ENET1_EXT_INTIN : in STD_LOGIC;
ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
PJTAG_TCK : in STD_LOGIC;
PJTAG_TMS : in STD_LOGIC;
PJTAG_TDI : in STD_LOGIC;
PJTAG_TDO : out STD_LOGIC;
SDIO0_CLK : out STD_LOGIC;
SDIO0_CLK_FB : in STD_LOGIC;
SDIO0_CMD_O : out STD_LOGIC;
SDIO0_CMD_I : in STD_LOGIC;
SDIO0_CMD_T : out STD_LOGIC;
SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO0_LED : out STD_LOGIC;
SDIO0_CDN : in STD_LOGIC;
SDIO0_WP : in STD_LOGIC;
SDIO0_BUSPOW : out STD_LOGIC;
SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SDIO1_CLK : out STD_LOGIC;
SDIO1_CLK_FB : in STD_LOGIC;
SDIO1_CMD_O : out STD_LOGIC;
SDIO1_CMD_I : in STD_LOGIC;
SDIO1_CMD_T : out STD_LOGIC;
SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 );
SDIO1_LED : out STD_LOGIC;
SDIO1_CDN : in STD_LOGIC;
SDIO1_WP : in STD_LOGIC;
SDIO1_BUSPOW : out STD_LOGIC;
SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 );
SPI0_SCLK_I : in STD_LOGIC;
SPI0_SCLK_O : out STD_LOGIC;
SPI0_SCLK_T : out STD_LOGIC;
SPI0_MOSI_I : in STD_LOGIC;
SPI0_MOSI_O : out STD_LOGIC;
SPI0_MOSI_T : out STD_LOGIC;
SPI0_MISO_I : in STD_LOGIC;
SPI0_MISO_O : out STD_LOGIC;
SPI0_MISO_T : out STD_LOGIC;
SPI0_SS_I : in STD_LOGIC;
SPI0_SS_O : out STD_LOGIC;
SPI0_SS1_O : out STD_LOGIC;
SPI0_SS2_O : out STD_LOGIC;
SPI0_SS_T : out STD_LOGIC;
SPI1_SCLK_I : in STD_LOGIC;
SPI1_SCLK_O : out STD_LOGIC;
SPI1_SCLK_T : out STD_LOGIC;
SPI1_MOSI_I : in STD_LOGIC;
SPI1_MOSI_O : out STD_LOGIC;
SPI1_MOSI_T : out STD_LOGIC;
SPI1_MISO_I : in STD_LOGIC;
SPI1_MISO_O : out STD_LOGIC;
SPI1_MISO_T : out STD_LOGIC;
SPI1_SS_I : in STD_LOGIC;
SPI1_SS_O : out STD_LOGIC;
SPI1_SS1_O : out STD_LOGIC;
SPI1_SS2_O : out STD_LOGIC;
SPI1_SS_T : out STD_LOGIC;
UART0_DTRN : out STD_LOGIC;
UART0_RTSN : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_CTSN : in STD_LOGIC;
UART0_DCDN : in STD_LOGIC;
UART0_DSRN : in STD_LOGIC;
UART0_RIN : in STD_LOGIC;
UART0_RX : in STD_LOGIC;
UART1_DTRN : out STD_LOGIC;
UART1_RTSN : out STD_LOGIC;
UART1_TX : out STD_LOGIC;
UART1_CTSN : in STD_LOGIC;
UART1_DCDN : in STD_LOGIC;
UART1_DSRN : in STD_LOGIC;
UART1_RIN : in STD_LOGIC;
UART1_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
TTC0_CLK0_IN : in STD_LOGIC;
TTC0_CLK1_IN : in STD_LOGIC;
TTC0_CLK2_IN : in STD_LOGIC;
TTC1_WAVE0_OUT : out STD_LOGIC;
TTC1_WAVE1_OUT : out STD_LOGIC;
TTC1_WAVE2_OUT : out STD_LOGIC;
TTC1_CLK0_IN : in STD_LOGIC;
TTC1_CLK1_IN : in STD_LOGIC;
TTC1_CLK2_IN : in STD_LOGIC;
WDT_CLK_IN : in STD_LOGIC;
WDT_RST_OUT : out STD_LOGIC;
TRACE_CLK : in STD_LOGIC;
TRACE_CTL : out STD_LOGIC;
TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 );
TRACE_CLK_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB1_VBUS_PWRSELECT : out STD_LOGIC;
USB1_VBUS_PWRFAULT : in STD_LOGIC;
SRAM_INTIN : in STD_LOGIC;
M_AXI_GP0_ARESETN : out STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARESETN : out STD_LOGIC;
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARESETN : out STD_LOGIC;
S_AXI_GP0_ARREADY : out STD_LOGIC;
S_AXI_GP0_AWREADY : out STD_LOGIC;
S_AXI_GP0_BVALID : out STD_LOGIC;
S_AXI_GP0_RLAST : out STD_LOGIC;
S_AXI_GP0_RVALID : out STD_LOGIC;
S_AXI_GP0_WREADY : out STD_LOGIC;
S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_ACLK : in STD_LOGIC;
S_AXI_GP0_ARVALID : in STD_LOGIC;
S_AXI_GP0_AWVALID : in STD_LOGIC;
S_AXI_GP0_BREADY : in STD_LOGIC;
S_AXI_GP0_RREADY : in STD_LOGIC;
S_AXI_GP0_WLAST : in STD_LOGIC;
S_AXI_GP0_WVALID : in STD_LOGIC;
S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ARESETN : out STD_LOGIC;
S_AXI_GP1_ARREADY : out STD_LOGIC;
S_AXI_GP1_AWREADY : out STD_LOGIC;
S_AXI_GP1_BVALID : out STD_LOGIC;
S_AXI_GP1_RLAST : out STD_LOGIC;
S_AXI_GP1_RVALID : out STD_LOGIC;
S_AXI_GP1_WREADY : out STD_LOGIC;
S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_ACLK : in STD_LOGIC;
S_AXI_GP1_ARVALID : in STD_LOGIC;
S_AXI_GP1_AWVALID : in STD_LOGIC;
S_AXI_GP1_BREADY : in STD_LOGIC;
S_AXI_GP1_RREADY : in STD_LOGIC;
S_AXI_GP1_WLAST : in STD_LOGIC;
S_AXI_GP1_WVALID : in STD_LOGIC;
S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_ACP_ARESETN : out STD_LOGIC;
S_AXI_ACP_ARREADY : out STD_LOGIC;
S_AXI_ACP_AWREADY : out STD_LOGIC;
S_AXI_ACP_BVALID : out STD_LOGIC;
S_AXI_ACP_RLAST : out STD_LOGIC;
S_AXI_ACP_RVALID : out STD_LOGIC;
S_AXI_ACP_WREADY : out STD_LOGIC;
S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_ACLK : in STD_LOGIC;
S_AXI_ACP_ARVALID : in STD_LOGIC;
S_AXI_ACP_AWVALID : in STD_LOGIC;
S_AXI_ACP_BREADY : in STD_LOGIC;
S_AXI_ACP_RREADY : in STD_LOGIC;
S_AXI_ACP_WLAST : in STD_LOGIC;
S_AXI_ACP_WVALID : in STD_LOGIC;
S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 );
S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_ARESETN : out STD_LOGIC;
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_ARESETN : out STD_LOGIC;
S_AXI_HP1_ARREADY : out STD_LOGIC;
S_AXI_HP1_AWREADY : out STD_LOGIC;
S_AXI_HP1_BVALID : out STD_LOGIC;
S_AXI_HP1_RLAST : out STD_LOGIC;
S_AXI_HP1_RVALID : out STD_LOGIC;
S_AXI_HP1_WREADY : out STD_LOGIC;
S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_ACLK : in STD_LOGIC;
S_AXI_HP1_ARVALID : in STD_LOGIC;
S_AXI_HP1_AWVALID : in STD_LOGIC;
S_AXI_HP1_BREADY : in STD_LOGIC;
S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_RREADY : in STD_LOGIC;
S_AXI_HP1_WLAST : in STD_LOGIC;
S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP1_WVALID : in STD_LOGIC;
S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_ARESETN : out STD_LOGIC;
S_AXI_HP2_ARREADY : out STD_LOGIC;
S_AXI_HP2_AWREADY : out STD_LOGIC;
S_AXI_HP2_BVALID : out STD_LOGIC;
S_AXI_HP2_RLAST : out STD_LOGIC;
S_AXI_HP2_RVALID : out STD_LOGIC;
S_AXI_HP2_WREADY : out STD_LOGIC;
S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_ACLK : in STD_LOGIC;
S_AXI_HP2_ARVALID : in STD_LOGIC;
S_AXI_HP2_AWVALID : in STD_LOGIC;
S_AXI_HP2_BREADY : in STD_LOGIC;
S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_RREADY : in STD_LOGIC;
S_AXI_HP2_WLAST : in STD_LOGIC;
S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP2_WVALID : in STD_LOGIC;
S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_ARESETN : out STD_LOGIC;
S_AXI_HP3_ARREADY : out STD_LOGIC;
S_AXI_HP3_AWREADY : out STD_LOGIC;
S_AXI_HP3_BVALID : out STD_LOGIC;
S_AXI_HP3_RLAST : out STD_LOGIC;
S_AXI_HP3_RVALID : out STD_LOGIC;
S_AXI_HP3_WREADY : out STD_LOGIC;
S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_ACLK : in STD_LOGIC;
S_AXI_HP3_ARVALID : in STD_LOGIC;
S_AXI_HP3_AWVALID : in STD_LOGIC;
S_AXI_HP3_BREADY : in STD_LOGIC;
S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_RREADY : in STD_LOGIC;
S_AXI_HP3_WLAST : in STD_LOGIC;
S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP3_WVALID : in STD_LOGIC;
S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_P2F_DMAC_ABORT : out STD_LOGIC;
IRQ_P2F_DMAC0 : out STD_LOGIC;
IRQ_P2F_DMAC1 : out STD_LOGIC;
IRQ_P2F_DMAC2 : out STD_LOGIC;
IRQ_P2F_DMAC3 : out STD_LOGIC;
IRQ_P2F_DMAC4 : out STD_LOGIC;
IRQ_P2F_DMAC5 : out STD_LOGIC;
IRQ_P2F_DMAC6 : out STD_LOGIC;
IRQ_P2F_DMAC7 : out STD_LOGIC;
IRQ_P2F_SMC : out STD_LOGIC;
IRQ_P2F_QSPI : out STD_LOGIC;
IRQ_P2F_CTI : out STD_LOGIC;
IRQ_P2F_GPIO : out STD_LOGIC;
IRQ_P2F_USB0 : out STD_LOGIC;
IRQ_P2F_ENET0 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE0 : out STD_LOGIC;
IRQ_P2F_SDIO0 : out STD_LOGIC;
IRQ_P2F_I2C0 : out STD_LOGIC;
IRQ_P2F_SPI0 : out STD_LOGIC;
IRQ_P2F_UART0 : out STD_LOGIC;
IRQ_P2F_CAN0 : out STD_LOGIC;
IRQ_P2F_USB1 : out STD_LOGIC;
IRQ_P2F_ENET1 : out STD_LOGIC;
IRQ_P2F_ENET_WAKE1 : out STD_LOGIC;
IRQ_P2F_SDIO1 : out STD_LOGIC;
IRQ_P2F_I2C1 : out STD_LOGIC;
IRQ_P2F_SPI1 : out STD_LOGIC;
IRQ_P2F_UART1 : out STD_LOGIC;
IRQ_P2F_CAN1 : out STD_LOGIC;
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
Core0_nFIQ : in STD_LOGIC;
Core0_nIRQ : in STD_LOGIC;
Core1_nFIQ : in STD_LOGIC;
Core1_nIRQ : in STD_LOGIC;
DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA0_DAVALID : out STD_LOGIC;
DMA0_DRREADY : out STD_LOGIC;
DMA0_RSTN : out STD_LOGIC;
DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DAVALID : out STD_LOGIC;
DMA1_DRREADY : out STD_LOGIC;
DMA1_RSTN : out STD_LOGIC;
DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DAVALID : out STD_LOGIC;
DMA2_DRREADY : out STD_LOGIC;
DMA2_RSTN : out STD_LOGIC;
DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DAVALID : out STD_LOGIC;
DMA3_DRREADY : out STD_LOGIC;
DMA3_RSTN : out STD_LOGIC;
DMA0_ACLK : in STD_LOGIC;
DMA0_DAREADY : in STD_LOGIC;
DMA0_DRLAST : in STD_LOGIC;
DMA0_DRVALID : in STD_LOGIC;
DMA1_ACLK : in STD_LOGIC;
DMA1_DAREADY : in STD_LOGIC;
DMA1_DRLAST : in STD_LOGIC;
DMA1_DRVALID : in STD_LOGIC;
DMA2_ACLK : in STD_LOGIC;
DMA2_DAREADY : in STD_LOGIC;
DMA2_DRLAST : in STD_LOGIC;
DMA2_DRVALID : in STD_LOGIC;
DMA3_ACLK : in STD_LOGIC;
DMA3_DAREADY : in STD_LOGIC;
DMA3_DRLAST : in STD_LOGIC;
DMA3_DRVALID : in STD_LOGIC;
DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 );
FCLK_CLK3 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLKTRIG3_N : in STD_LOGIC;
FCLK_CLKTRIG2_N : in STD_LOGIC;
FCLK_CLKTRIG1_N : in STD_LOGIC;
FCLK_CLKTRIG0_N : in STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMD_TRACEIN_VALID : in STD_LOGIC;
FTMD_TRACEIN_CLK : in STD_LOGIC;
FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 );
FTMT_F2P_TRIG_0 : in STD_LOGIC;
FTMT_F2P_TRIGACK_0 : out STD_LOGIC;
FTMT_F2P_TRIG_1 : in STD_LOGIC;
FTMT_F2P_TRIGACK_1 : out STD_LOGIC;
FTMT_F2P_TRIG_2 : in STD_LOGIC;
FTMT_F2P_TRIGACK_2 : out STD_LOGIC;
FTMT_F2P_TRIG_3 : in STD_LOGIC;
FTMT_F2P_TRIGACK_3 : out STD_LOGIC;
FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 );
FTMT_P2F_TRIGACK_0 : in STD_LOGIC;
FTMT_P2F_TRIG_0 : out STD_LOGIC;
FTMT_P2F_TRIGACK_1 : in STD_LOGIC;
FTMT_P2F_TRIG_1 : out STD_LOGIC;
FTMT_P2F_TRIGACK_2 : in STD_LOGIC;
FTMT_P2F_TRIG_2 : out STD_LOGIC;
FTMT_P2F_TRIGACK_3 : in STD_LOGIC;
FTMT_P2F_TRIG_3 : out STD_LOGIC;
FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 );
FPGA_IDLE_N : in STD_LOGIC;
EVENT_EVENTO : out STD_LOGIC;
EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 );
EVENT_EVENTI : in STD_LOGIC;
DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 );
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "ip_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal ENET0_MDIO_T_n : STD_LOGIC;
signal ENET1_MDIO_T_n : STD_LOGIC;
signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 1 downto 0 );
signal I2C0_SCL_T_n : STD_LOGIC;
signal I2C0_SDA_T_n : STD_LOGIC;
signal I2C1_SCL_T_n : STD_LOGIC;
signal I2C1_SDA_T_n : STD_LOGIC;
signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal SDIO0_CMD_T_n : STD_LOGIC;
signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SDIO1_CMD_T_n : STD_LOGIC;
signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal SPI0_MISO_T_n : STD_LOGIC;
signal SPI0_MOSI_T_n : STD_LOGIC;
signal SPI0_SCLK_T_n : STD_LOGIC;
signal SPI0_SS_T_n : STD_LOGIC;
signal SPI1_MISO_T_n : STD_LOGIC;
signal SPI1_MOSI_T_n : STD_LOGIC;
signal SPI1_SCLK_T_n : STD_LOGIC;
signal SPI1_SS_T_n : STD_LOGIC;
signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true";
signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true";
signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true";
signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true";
signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true";
signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true";
signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true";
signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC;
attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true";
signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true";
signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true";
signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true";
signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true";
signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true";
signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true";
signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true";
signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true";
signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 );
signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal buffered_DDR_CAS_n : STD_LOGIC;
signal buffered_DDR_CKE : STD_LOGIC;
signal buffered_DDR_CS_n : STD_LOGIC;
signal buffered_DDR_Clk : STD_LOGIC;
signal buffered_DDR_Clk_n : STD_LOGIC;
signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 );
signal buffered_DDR_DRSTB : STD_LOGIC;
signal buffered_DDR_ODT : STD_LOGIC;
signal buffered_DDR_RAS_n : STD_LOGIC;
signal buffered_DDR_VRN : STD_LOGIC;
signal buffered_DDR_VRP : STD_LOGIC;
signal buffered_DDR_WEB : STD_LOGIC;
signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal buffered_PS_CLK : STD_LOGIC;
signal buffered_PS_PORB : STD_LOGIC;
signal buffered_PS_SRSTB : STD_LOGIC;
signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC;
signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS7_i : label is "PRIMITIVE";
attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \buffer_fclk_clk_1.FCLK_CLK_1_BUFG\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE";
begin
ENET0_GMII_TXD(7) <= \<const0>\;
ENET0_GMII_TXD(6) <= \<const0>\;
ENET0_GMII_TXD(5) <= \<const0>\;
ENET0_GMII_TXD(4) <= \<const0>\;
ENET0_GMII_TXD(3) <= \<const0>\;
ENET0_GMII_TXD(2) <= \<const0>\;
ENET0_GMII_TXD(1) <= \<const0>\;
ENET0_GMII_TXD(0) <= \<const0>\;
ENET0_GMII_TX_EN <= \<const0>\;
ENET0_GMII_TX_ER <= \<const0>\;
ENET1_GMII_TXD(7) <= \<const0>\;
ENET1_GMII_TXD(6) <= \<const0>\;
ENET1_GMII_TXD(5) <= \<const0>\;
ENET1_GMII_TXD(4) <= \<const0>\;
ENET1_GMII_TXD(3) <= \<const0>\;
ENET1_GMII_TXD(2) <= \<const0>\;
ENET1_GMII_TXD(1) <= \<const0>\;
ENET1_GMII_TXD(0) <= \<const0>\;
ENET1_GMII_TX_EN <= \<const0>\;
ENET1_GMII_TX_ER <= \<const0>\;
M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2);
M_AXI_GP0_ARCACHE(1) <= \<const1>\;
M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0);
M_AXI_GP0_ARSIZE(2) <= \<const0>\;
M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0);
M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2);
M_AXI_GP0_AWCACHE(1) <= \<const1>\;
M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0);
M_AXI_GP0_AWSIZE(2) <= \<const0>\;
M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0);
M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2);
M_AXI_GP1_ARCACHE(1) <= \<const1>\;
M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0);
M_AXI_GP1_ARSIZE(2) <= \<const0>\;
M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0);
M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2);
M_AXI_GP1_AWCACHE(1) <= \<const1>\;
M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0);
M_AXI_GP1_AWSIZE(2) <= \<const0>\;
M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0);
PJTAG_TDO <= \<const0>\;
TRACE_CLK_OUT <= \<const0>\;
TRACE_CTL <= \TRACE_CTL_PIPE[0]\;
TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0);
DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CAS_n,
PAD => DDR_CAS_n
);
DDR_CKE_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CKE,
PAD => DDR_CKE
);
DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_CS_n,
PAD => DDR_CS_n
);
DDR_Clk_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk,
PAD => DDR_Clk
);
DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Clk_n,
PAD => DDR_Clk_n
);
DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DRSTB,
PAD => DDR_DRSTB
);
DDR_ODT_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_ODT,
PAD => DDR_ODT
);
DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_RAS_n,
PAD => DDR_RAS_n
);
DDR_VRN_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRN,
PAD => DDR_VRN
);
DDR_VRP_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_VRP,
PAD => DDR_VRP
);
DDR_WEB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_WEB,
PAD => DDR_WEB
);
ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET0_MDIO_T_n,
O => ENET0_MDIO_T
);
ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ENET1_MDIO_T_n,
O => ENET1_MDIO_T
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(0),
O => GPIO_T(0)
);
\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(10),
O => GPIO_T(10)
);
\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(11),
O => GPIO_T(11)
);
\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(12),
O => GPIO_T(12)
);
\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(13),
O => GPIO_T(13)
);
\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(14),
O => GPIO_T(14)
);
\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(15),
O => GPIO_T(15)
);
\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(16),
O => GPIO_T(16)
);
\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(17),
O => GPIO_T(17)
);
\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(18),
O => GPIO_T(18)
);
\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(19),
O => GPIO_T(19)
);
\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(1),
O => GPIO_T(1)
);
\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(20),
O => GPIO_T(20)
);
\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(21),
O => GPIO_T(21)
);
\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(22),
O => GPIO_T(22)
);
\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(23),
O => GPIO_T(23)
);
\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(24),
O => GPIO_T(24)
);
\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(25),
O => GPIO_T(25)
);
\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(26),
O => GPIO_T(26)
);
\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(27),
O => GPIO_T(27)
);
\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(28),
O => GPIO_T(28)
);
\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(29),
O => GPIO_T(29)
);
\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(2),
O => GPIO_T(2)
);
\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(30),
O => GPIO_T(30)
);
\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(31),
O => GPIO_T(31)
);
\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(32),
O => GPIO_T(32)
);
\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(33),
O => GPIO_T(33)
);
\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(34),
O => GPIO_T(34)
);
\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(35),
O => GPIO_T(35)
);
\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(36),
O => GPIO_T(36)
);
\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(37),
O => GPIO_T(37)
);
\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(38),
O => GPIO_T(38)
);
\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(39),
O => GPIO_T(39)
);
\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(3),
O => GPIO_T(3)
);
\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(40),
O => GPIO_T(40)
);
\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(41),
O => GPIO_T(41)
);
\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(42),
O => GPIO_T(42)
);
\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(43),
O => GPIO_T(43)
);
\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(44),
O => GPIO_T(44)
);
\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(45),
O => GPIO_T(45)
);
\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(46),
O => GPIO_T(46)
);
\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(47),
O => GPIO_T(47)
);
\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(48),
O => GPIO_T(48)
);
\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(49),
O => GPIO_T(49)
);
\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(4),
O => GPIO_T(4)
);
\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(50),
O => GPIO_T(50)
);
\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(51),
O => GPIO_T(51)
);
\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(52),
O => GPIO_T(52)
);
\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(53),
O => GPIO_T(53)
);
\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(54),
O => GPIO_T(54)
);
\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(55),
O => GPIO_T(55)
);
\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(56),
O => GPIO_T(56)
);
\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(57),
O => GPIO_T(57)
);
\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(58),
O => GPIO_T(58)
);
\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(59),
O => GPIO_T(59)
);
\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(5),
O => GPIO_T(5)
);
\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(60),
O => GPIO_T(60)
);
\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(61),
O => GPIO_T(61)
);
\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(62),
O => GPIO_T(62)
);
\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(63),
O => GPIO_T(63)
);
\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(6),
O => GPIO_T(6)
);
\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(7),
O => GPIO_T(7)
);
\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(8),
O => GPIO_T(8)
);
\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => gpio_out_t_n(9),
O => GPIO_T(9)
);
I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SCL_T_n,
O => I2C0_SCL_T
);
I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C0_SDA_T_n,
O => I2C0_SDA_T
);
I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SCL_T_n,
O => I2C1_SCL_T
);
I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => I2C1_SDA_T_n,
O => I2C1_SDA_T
);
PS7_i: unisim.vcomponents.PS7
port map (
DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0),
DDRARB(3 downto 0) => DDR_ARB(3 downto 0),
DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0),
DDRCASB => buffered_DDR_CAS_n,
DDRCKE => buffered_DDR_CKE,
DDRCKN => buffered_DDR_Clk_n,
DDRCKP => buffered_DDR_Clk,
DDRCSB => buffered_DDR_CS_n,
DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0),
DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0),
DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0),
DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0),
DDRDRSTB => buffered_DDR_DRSTB,
DDRODT => buffered_DDR_ODT,
DDRRASB => buffered_DDR_RAS_n,
DDRVRN => buffered_DDR_VRN,
DDRVRP => buffered_DDR_VRP,
DDRWEB => buffered_DDR_WEB,
DMA0ACLK => DMA0_ACLK,
DMA0DAREADY => DMA0_DAREADY,
DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0),
DMA0DAVALID => DMA0_DAVALID,
DMA0DRLAST => DMA0_DRLAST,
DMA0DRREADY => DMA0_DRREADY,
DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0),
DMA0DRVALID => DMA0_DRVALID,
DMA0RSTN => DMA0_RSTN,
DMA1ACLK => DMA1_ACLK,
DMA1DAREADY => DMA1_DAREADY,
DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0),
DMA1DAVALID => DMA1_DAVALID,
DMA1DRLAST => DMA1_DRLAST,
DMA1DRREADY => DMA1_DRREADY,
DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0),
DMA1DRVALID => DMA1_DRVALID,
DMA1RSTN => DMA1_RSTN,
DMA2ACLK => DMA2_ACLK,
DMA2DAREADY => DMA2_DAREADY,
DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0),
DMA2DAVALID => DMA2_DAVALID,
DMA2DRLAST => DMA2_DRLAST,
DMA2DRREADY => DMA2_DRREADY,
DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0),
DMA2DRVALID => DMA2_DRVALID,
DMA2RSTN => DMA2_RSTN,
DMA3ACLK => DMA3_ACLK,
DMA3DAREADY => DMA3_DAREADY,
DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0),
DMA3DAVALID => DMA3_DAVALID,
DMA3DRLAST => DMA3_DRLAST,
DMA3DRREADY => DMA3_DRREADY,
DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0),
DMA3DRVALID => DMA3_DRVALID,
DMA3RSTN => DMA3_RSTN,
EMIOCAN0PHYRX => CAN0_PHY_RX,
EMIOCAN0PHYTX => CAN0_PHY_TX,
EMIOCAN1PHYRX => CAN1_PHY_RX,
EMIOCAN1PHYTX => CAN1_PHY_TX,
EMIOENET0EXTINTIN => ENET0_EXT_INTIN,
EMIOENET0GMIICOL => '0',
EMIOENET0GMIICRS => '0',
EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK,
EMIOENET0GMIIRXD(7 downto 0) => B"00000000",
EMIOENET0GMIIRXDV => '0',
EMIOENET0GMIIRXER => '0',
EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK,
EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED,
EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED,
EMIOENET0MDIOI => ENET0_MDIO_I,
EMIOENET0MDIOMDC => ENET0_MDIO_MDC,
EMIOENET0MDIOO => ENET0_MDIO_O,
EMIOENET0MDIOTN => ENET0_MDIO_T_n,
EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX,
EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX,
EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX,
EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX,
EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX,
EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX,
EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX,
EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX,
EMIOENET0SOFRX => ENET0_SOF_RX,
EMIOENET0SOFTX => ENET0_SOF_TX,
EMIOENET1EXTINTIN => ENET1_EXT_INTIN,
EMIOENET1GMIICOL => '0',
EMIOENET1GMIICRS => '0',
EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK,
EMIOENET1GMIIRXD(7 downto 0) => B"00000000",
EMIOENET1GMIIRXDV => '0',
EMIOENET1GMIIRXER => '0',
EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK,
EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0),
EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED,
EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED,
EMIOENET1MDIOI => ENET1_MDIO_I,
EMIOENET1MDIOMDC => ENET1_MDIO_MDC,
EMIOENET1MDIOO => ENET1_MDIO_O,
EMIOENET1MDIOTN => ENET1_MDIO_T_n,
EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX,
EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX,
EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX,
EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX,
EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX,
EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX,
EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX,
EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX,
EMIOENET1SOFRX => ENET1_SOF_RX,
EMIOENET1SOFTX => ENET1_SOF_TX,
EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0),
EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0),
EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0),
EMIOI2C0SCLI => I2C0_SCL_I,
EMIOI2C0SCLO => I2C0_SCL_O,
EMIOI2C0SCLTN => I2C0_SCL_T_n,
EMIOI2C0SDAI => I2C0_SDA_I,
EMIOI2C0SDAO => I2C0_SDA_O,
EMIOI2C0SDATN => I2C0_SDA_T_n,
EMIOI2C1SCLI => I2C1_SCL_I,
EMIOI2C1SCLO => I2C1_SCL_O,
EMIOI2C1SCLTN => I2C1_SCL_T_n,
EMIOI2C1SDAI => I2C1_SDA_I,
EMIOI2C1SDAO => I2C1_SDA_O,
EMIOI2C1SDATN => I2C1_SDA_T_n,
EMIOPJTAGTCK => PJTAG_TCK,
EMIOPJTAGTDI => PJTAG_TDI,
EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED,
EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED,
EMIOPJTAGTMS => PJTAG_TMS,
EMIOSDIO0BUSPOW => SDIO0_BUSPOW,
EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0),
EMIOSDIO0CDN => SDIO0_CDN,
EMIOSDIO0CLK => SDIO0_CLK,
EMIOSDIO0CLKFB => SDIO0_CLK_FB,
EMIOSDIO0CMDI => SDIO0_CMD_I,
EMIOSDIO0CMDO => SDIO0_CMD_O,
EMIOSDIO0CMDTN => SDIO0_CMD_T_n,
EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0),
EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0),
EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0),
EMIOSDIO0LED => SDIO0_LED,
EMIOSDIO0WP => SDIO0_WP,
EMIOSDIO1BUSPOW => SDIO1_BUSPOW,
EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0),
EMIOSDIO1CDN => SDIO1_CDN,
EMIOSDIO1CLK => SDIO1_CLK,
EMIOSDIO1CLKFB => SDIO1_CLK_FB,
EMIOSDIO1CMDI => SDIO1_CMD_I,
EMIOSDIO1CMDO => SDIO1_CMD_O,
EMIOSDIO1CMDTN => SDIO1_CMD_T_n,
EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0),
EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0),
EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0),
EMIOSDIO1LED => SDIO1_LED,
EMIOSDIO1WP => SDIO1_WP,
EMIOSPI0MI => SPI0_MISO_I,
EMIOSPI0MO => SPI0_MOSI_O,
EMIOSPI0MOTN => SPI0_MOSI_T_n,
EMIOSPI0SCLKI => SPI0_SCLK_I,
EMIOSPI0SCLKO => SPI0_SCLK_O,
EMIOSPI0SCLKTN => SPI0_SCLK_T_n,
EMIOSPI0SI => SPI0_MOSI_I,
EMIOSPI0SO => SPI0_MISO_O,
EMIOSPI0SSIN => SPI0_SS_I,
EMIOSPI0SSNTN => SPI0_SS_T_n,
EMIOSPI0SSON(2) => SPI0_SS2_O,
EMIOSPI0SSON(1) => SPI0_SS1_O,
EMIOSPI0SSON(0) => SPI0_SS_O,
EMIOSPI0STN => SPI0_MISO_T_n,
EMIOSPI1MI => SPI1_MISO_I,
EMIOSPI1MO => SPI1_MOSI_O,
EMIOSPI1MOTN => SPI1_MOSI_T_n,
EMIOSPI1SCLKI => SPI1_SCLK_I,
EMIOSPI1SCLKO => SPI1_SCLK_O,
EMIOSPI1SCLKTN => SPI1_SCLK_T_n,
EMIOSPI1SI => SPI1_MOSI_I,
EMIOSPI1SO => SPI1_MISO_O,
EMIOSPI1SSIN => SPI1_SS_I,
EMIOSPI1SSNTN => SPI1_SS_T_n,
EMIOSPI1SSON(2) => SPI1_SS2_O,
EMIOSPI1SSON(1) => SPI1_SS1_O,
EMIOSPI1SSON(0) => SPI1_SS_O,
EMIOSPI1STN => SPI1_MISO_T_n,
EMIOSRAMINTIN => SRAM_INTIN,
EMIOTRACECLK => TRACE_CLK,
EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED,
EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0),
EMIOTTC0CLKI(2) => TTC0_CLK2_IN,
EMIOTTC0CLKI(1) => TTC0_CLK1_IN,
EMIOTTC0CLKI(0) => TTC0_CLK0_IN,
EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT,
EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT,
EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT,
EMIOTTC1CLKI(2) => TTC1_CLK2_IN,
EMIOTTC1CLKI(1) => TTC1_CLK1_IN,
EMIOTTC1CLKI(0) => TTC1_CLK0_IN,
EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT,
EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT,
EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT,
EMIOUART0CTSN => UART0_CTSN,
EMIOUART0DCDN => UART0_DCDN,
EMIOUART0DSRN => UART0_DSRN,
EMIOUART0DTRN => UART0_DTRN,
EMIOUART0RIN => UART0_RIN,
EMIOUART0RTSN => UART0_RTSN,
EMIOUART0RX => UART0_RX,
EMIOUART0TX => UART0_TX,
EMIOUART1CTSN => UART1_CTSN,
EMIOUART1DCDN => UART1_DCDN,
EMIOUART1DSRN => UART1_DSRN,
EMIOUART1DTRN => UART1_DTRN,
EMIOUART1RIN => UART1_RIN,
EMIOUART1RTSN => UART1_RTSN,
EMIOUART1RX => UART1_RX,
EMIOUART1TX => UART1_TX,
EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT,
EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT,
EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0),
EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT,
EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT,
EMIOWDTCLKI => WDT_CLK_IN,
EMIOWDTRSTO => WDT_RST_OUT,
EVENTEVENTI => EVENT_EVENTI,
EVENTEVENTO => EVENT_EVENTO,
EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0),
EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0),
FCLKCLK(3) => FCLK_CLK3,
FCLKCLK(2) => FCLK_CLK2,
FCLKCLK(1 downto 0) => FCLK_CLK_unbuffered(1 downto 0),
FCLKCLKTRIGN(3 downto 0) => B"0000",
FCLKRESETN(3) => FCLK_RESET3_N,
FCLKRESETN(2) => FCLK_RESET2_N,
FCLKRESETN(1) => FCLK_RESET1_N,
FCLKRESETN(0) => FCLK_RESET0_N,
FPGAIDLEN => FPGA_IDLE_N,
FTMDTRACEINATID(3 downto 0) => B"0000",
FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK,
FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000",
FTMDTRACEINVALID => '0',
FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0),
FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3,
FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2,
FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1,
FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0,
FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3,
FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2,
FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1,
FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0,
FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0),
FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3,
FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2,
FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1,
FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0,
FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3,
FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2,
FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1,
FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0,
IRQF2P(19) => Core1_nFIQ,
IRQF2P(18) => Core0_nFIQ,
IRQF2P(17) => Core1_nIRQ,
IRQF2P(16) => Core0_nIRQ,
IRQF2P(15 downto 1) => B"000000000000000",
IRQF2P(0) => IRQ_F2P(0),
IRQP2F(28) => IRQ_P2F_DMAC_ABORT,
IRQP2F(27) => IRQ_P2F_DMAC7,
IRQP2F(26) => IRQ_P2F_DMAC6,
IRQP2F(25) => IRQ_P2F_DMAC5,
IRQP2F(24) => IRQ_P2F_DMAC4,
IRQP2F(23) => IRQ_P2F_DMAC3,
IRQP2F(22) => IRQ_P2F_DMAC2,
IRQP2F(21) => IRQ_P2F_DMAC1,
IRQP2F(20) => IRQ_P2F_DMAC0,
IRQP2F(19) => IRQ_P2F_SMC,
IRQP2F(18) => IRQ_P2F_QSPI,
IRQP2F(17) => IRQ_P2F_CTI,
IRQP2F(16) => IRQ_P2F_GPIO,
IRQP2F(15) => IRQ_P2F_USB0,
IRQP2F(14) => IRQ_P2F_ENET0,
IRQP2F(13) => IRQ_P2F_ENET_WAKE0,
IRQP2F(12) => IRQ_P2F_SDIO0,
IRQP2F(11) => IRQ_P2F_I2C0,
IRQP2F(10) => IRQ_P2F_SPI0,
IRQP2F(9) => IRQ_P2F_UART0,
IRQP2F(8) => IRQ_P2F_CAN0,
IRQP2F(7) => IRQ_P2F_USB1,
IRQP2F(6) => IRQ_P2F_ENET1,
IRQP2F(5) => IRQ_P2F_ENET_WAKE1,
IRQP2F(4) => IRQ_P2F_SDIO1,
IRQP2F(3) => IRQ_P2F_I2C1,
IRQP2F(2) => IRQ_P2F_SPI1,
IRQP2F(1) => IRQ_P2F_UART1,
IRQP2F(0) => IRQ_P2F_CAN1,
MAXIGP0ACLK => M_AXI_GP0_ACLK,
MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2),
MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1),
MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0),
MAXIGP0ARESETN => M_AXI_GP0_ARESETN,
MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
MAXIGP0ARREADY => M_AXI_GP0_ARREADY,
MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0),
MAXIGP0ARVALID => M_AXI_GP0_ARVALID,
MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2),
MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1),
MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0),
MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
MAXIGP0AWREADY => M_AXI_GP0_AWREADY,
MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0),
MAXIGP0AWVALID => M_AXI_GP0_AWVALID,
MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
MAXIGP0BREADY => M_AXI_GP0_BREADY,
MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
MAXIGP0BVALID => M_AXI_GP0_BVALID,
MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
MAXIGP0RLAST => M_AXI_GP0_RLAST,
MAXIGP0RREADY => M_AXI_GP0_RREADY,
MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
MAXIGP0RVALID => M_AXI_GP0_RVALID,
MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
MAXIGP0WLAST => M_AXI_GP0_WLAST,
MAXIGP0WREADY => M_AXI_GP0_WREADY,
MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
MAXIGP0WVALID => M_AXI_GP0_WVALID,
MAXIGP1ACLK => M_AXI_GP1_ACLK,
MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0),
MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0),
MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2),
MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1),
MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0),
MAXIGP1ARESETN => M_AXI_GP1_ARESETN,
MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0),
MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0),
MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0),
MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0),
MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0),
MAXIGP1ARREADY => M_AXI_GP1_ARREADY,
MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0),
MAXIGP1ARVALID => M_AXI_GP1_ARVALID,
MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0),
MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0),
MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2),
MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1),
MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0),
MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0),
MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0),
MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0),
MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0),
MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0),
MAXIGP1AWREADY => M_AXI_GP1_AWREADY,
MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0),
MAXIGP1AWVALID => M_AXI_GP1_AWVALID,
MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0),
MAXIGP1BREADY => M_AXI_GP1_BREADY,
MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0),
MAXIGP1BVALID => M_AXI_GP1_BVALID,
MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0),
MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0),
MAXIGP1RLAST => M_AXI_GP1_RLAST,
MAXIGP1RREADY => M_AXI_GP1_RREADY,
MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0),
MAXIGP1RVALID => M_AXI_GP1_RVALID,
MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0),
MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0),
MAXIGP1WLAST => M_AXI_GP1_WLAST,
MAXIGP1WREADY => M_AXI_GP1_WREADY,
MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0),
MAXIGP1WVALID => M_AXI_GP1_WVALID,
MIO(53 downto 0) => buffered_MIO(53 downto 0),
PSCLK => buffered_PS_CLK,
PSPORB => buffered_PS_PORB,
PSSRSTB => buffered_PS_SRSTB,
SAXIACPACLK => S_AXI_ACP_ACLK,
SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0),
SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0),
SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0),
SAXIACPARESETN => S_AXI_ACP_ARESETN,
SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0),
SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0),
SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0),
SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0),
SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0),
SAXIACPARREADY => S_AXI_ACP_ARREADY,
SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0),
SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0),
SAXIACPARVALID => S_AXI_ACP_ARVALID,
SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0),
SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0),
SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0),
SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0),
SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0),
SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0),
SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0),
SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0),
SAXIACPAWREADY => S_AXI_ACP_AWREADY,
SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0),
SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0),
SAXIACPAWVALID => S_AXI_ACP_AWVALID,
SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0),
SAXIACPBREADY => S_AXI_ACP_BREADY,
SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0),
SAXIACPBVALID => S_AXI_ACP_BVALID,
SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0),
SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0),
SAXIACPRLAST => S_AXI_ACP_RLAST,
SAXIACPRREADY => S_AXI_ACP_RREADY,
SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0),
SAXIACPRVALID => S_AXI_ACP_RVALID,
SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0),
SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0),
SAXIACPWLAST => S_AXI_ACP_WLAST,
SAXIACPWREADY => S_AXI_ACP_WREADY,
SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0),
SAXIACPWVALID => S_AXI_ACP_WVALID,
SAXIGP0ACLK => S_AXI_GP0_ACLK,
SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0),
SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0),
SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0),
SAXIGP0ARESETN => S_AXI_GP0_ARESETN,
SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0),
SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0),
SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0),
SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0),
SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0),
SAXIGP0ARREADY => S_AXI_GP0_ARREADY,
SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0),
SAXIGP0ARVALID => S_AXI_GP0_ARVALID,
SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0),
SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0),
SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0),
SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0),
SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0),
SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0),
SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0),
SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0),
SAXIGP0AWREADY => S_AXI_GP0_AWREADY,
SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0),
SAXIGP0AWVALID => S_AXI_GP0_AWVALID,
SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0),
SAXIGP0BREADY => S_AXI_GP0_BREADY,
SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0),
SAXIGP0BVALID => S_AXI_GP0_BVALID,
SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0),
SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0),
SAXIGP0RLAST => S_AXI_GP0_RLAST,
SAXIGP0RREADY => S_AXI_GP0_RREADY,
SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0),
SAXIGP0RVALID => S_AXI_GP0_RVALID,
SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0),
SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0),
SAXIGP0WLAST => S_AXI_GP0_WLAST,
SAXIGP0WREADY => S_AXI_GP0_WREADY,
SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0),
SAXIGP0WVALID => S_AXI_GP0_WVALID,
SAXIGP1ACLK => S_AXI_GP1_ACLK,
SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0),
SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0),
SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0),
SAXIGP1ARESETN => S_AXI_GP1_ARESETN,
SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0),
SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0),
SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0),
SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0),
SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0),
SAXIGP1ARREADY => S_AXI_GP1_ARREADY,
SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0),
SAXIGP1ARVALID => S_AXI_GP1_ARVALID,
SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0),
SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0),
SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0),
SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0),
SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0),
SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0),
SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0),
SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0),
SAXIGP1AWREADY => S_AXI_GP1_AWREADY,
SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0),
SAXIGP1AWVALID => S_AXI_GP1_AWVALID,
SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0),
SAXIGP1BREADY => S_AXI_GP1_BREADY,
SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0),
SAXIGP1BVALID => S_AXI_GP1_BVALID,
SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0),
SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0),
SAXIGP1RLAST => S_AXI_GP1_RLAST,
SAXIGP1RREADY => S_AXI_GP1_RREADY,
SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0),
SAXIGP1RVALID => S_AXI_GP1_RVALID,
SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0),
SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0),
SAXIGP1WLAST => S_AXI_GP1_WLAST,
SAXIGP1WREADY => S_AXI_GP1_WREADY,
SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0),
SAXIGP1WVALID => S_AXI_GP1_WVALID,
SAXIHP0ACLK => S_AXI_HP0_ACLK,
SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0),
SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0),
SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0),
SAXIHP0ARESETN => S_AXI_HP0_ARESETN,
SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0),
SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0),
SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0),
SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0),
SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0),
SAXIHP0ARREADY => S_AXI_HP0_ARREADY,
SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0),
SAXIHP0ARVALID => S_AXI_HP0_ARVALID,
SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0),
SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0),
SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0),
SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0),
SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0),
SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0),
SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0),
SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0),
SAXIHP0AWREADY => S_AXI_HP0_AWREADY,
SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0),
SAXIHP0AWVALID => S_AXI_HP0_AWVALID,
SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0),
SAXIHP0BREADY => S_AXI_HP0_BREADY,
SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0),
SAXIHP0BVALID => S_AXI_HP0_BVALID,
SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0),
SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0),
SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0),
SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN,
SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0),
SAXIHP0RLAST => S_AXI_HP0_RLAST,
SAXIHP0RREADY => S_AXI_HP0_RREADY,
SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0),
SAXIHP0RVALID => S_AXI_HP0_RVALID,
SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0),
SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0),
SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0),
SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0),
SAXIHP0WLAST => S_AXI_HP0_WLAST,
SAXIHP0WREADY => S_AXI_HP0_WREADY,
SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN,
SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0),
SAXIHP0WVALID => S_AXI_HP0_WVALID,
SAXIHP1ACLK => S_AXI_HP1_ACLK,
SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0),
SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0),
SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0),
SAXIHP1ARESETN => S_AXI_HP1_ARESETN,
SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0),
SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0),
SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0),
SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0),
SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0),
SAXIHP1ARREADY => S_AXI_HP1_ARREADY,
SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0),
SAXIHP1ARVALID => S_AXI_HP1_ARVALID,
SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0),
SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0),
SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0),
SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0),
SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0),
SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0),
SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0),
SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0),
SAXIHP1AWREADY => S_AXI_HP1_AWREADY,
SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0),
SAXIHP1AWVALID => S_AXI_HP1_AWVALID,
SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0),
SAXIHP1BREADY => S_AXI_HP1_BREADY,
SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0),
SAXIHP1BVALID => S_AXI_HP1_BVALID,
SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0),
SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0),
SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0),
SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN,
SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0),
SAXIHP1RLAST => S_AXI_HP1_RLAST,
SAXIHP1RREADY => S_AXI_HP1_RREADY,
SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0),
SAXIHP1RVALID => S_AXI_HP1_RVALID,
SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0),
SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0),
SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0),
SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0),
SAXIHP1WLAST => S_AXI_HP1_WLAST,
SAXIHP1WREADY => S_AXI_HP1_WREADY,
SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN,
SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0),
SAXIHP1WVALID => S_AXI_HP1_WVALID,
SAXIHP2ACLK => S_AXI_HP2_ACLK,
SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0),
SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0),
SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0),
SAXIHP2ARESETN => S_AXI_HP2_ARESETN,
SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0),
SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0),
SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0),
SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0),
SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0),
SAXIHP2ARREADY => S_AXI_HP2_ARREADY,
SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0),
SAXIHP2ARVALID => S_AXI_HP2_ARVALID,
SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0),
SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0),
SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0),
SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0),
SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0),
SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0),
SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0),
SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0),
SAXIHP2AWREADY => S_AXI_HP2_AWREADY,
SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0),
SAXIHP2AWVALID => S_AXI_HP2_AWVALID,
SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0),
SAXIHP2BREADY => S_AXI_HP2_BREADY,
SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0),
SAXIHP2BVALID => S_AXI_HP2_BVALID,
SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0),
SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0),
SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0),
SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN,
SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0),
SAXIHP2RLAST => S_AXI_HP2_RLAST,
SAXIHP2RREADY => S_AXI_HP2_RREADY,
SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0),
SAXIHP2RVALID => S_AXI_HP2_RVALID,
SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0),
SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0),
SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0),
SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0),
SAXIHP2WLAST => S_AXI_HP2_WLAST,
SAXIHP2WREADY => S_AXI_HP2_WREADY,
SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN,
SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0),
SAXIHP2WVALID => S_AXI_HP2_WVALID,
SAXIHP3ACLK => S_AXI_HP3_ACLK,
SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0),
SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0),
SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0),
SAXIHP3ARESETN => S_AXI_HP3_ARESETN,
SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0),
SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0),
SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0),
SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0),
SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0),
SAXIHP3ARREADY => S_AXI_HP3_ARREADY,
SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0),
SAXIHP3ARVALID => S_AXI_HP3_ARVALID,
SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0),
SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0),
SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0),
SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0),
SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0),
SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0),
SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0),
SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0),
SAXIHP3AWREADY => S_AXI_HP3_AWREADY,
SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0),
SAXIHP3AWVALID => S_AXI_HP3_AWVALID,
SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0),
SAXIHP3BREADY => S_AXI_HP3_BREADY,
SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0),
SAXIHP3BVALID => S_AXI_HP3_BVALID,
SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0),
SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0),
SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0),
SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN,
SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0),
SAXIHP3RLAST => S_AXI_HP3_RLAST,
SAXIHP3RREADY => S_AXI_HP3_RREADY,
SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0),
SAXIHP3RVALID => S_AXI_HP3_RVALID,
SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0),
SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0),
SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0),
SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0),
SAXIHP3WLAST => S_AXI_HP3_WLAST,
SAXIHP3WREADY => S_AXI_HP3_WREADY,
SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN,
SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0),
SAXIHP3WVALID => S_AXI_HP3_WVALID
);
PS_CLK_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_CLK,
PAD => PS_CLK
);
PS_PORB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_PORB,
PAD => PS_PORB
);
PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF
port map (
IO => buffered_PS_SRSTB,
PAD => PS_SRSTB
);
SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_CMD_T_n,
O => SDIO0_CMD_T
);
\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(0),
O => SDIO0_DATA_T(0)
);
\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(1),
O => SDIO0_DATA_T(1)
);
\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(2),
O => SDIO0_DATA_T(2)
);
\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO0_DATA_T_n(3),
O => SDIO0_DATA_T(3)
);
SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_CMD_T_n,
O => SDIO1_CMD_T
);
\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(0),
O => SDIO1_DATA_T(0)
);
\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(1),
O => SDIO1_DATA_T(1)
);
\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(2),
O => SDIO1_DATA_T(2)
);
\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SDIO1_DATA_T_n(3),
O => SDIO1_DATA_T(3)
);
SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MISO_T_n,
O => SPI0_MISO_T
);
SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_MOSI_T_n,
O => SPI0_MOSI_T
);
SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SCLK_T_n,
O => SPI0_SCLK_T
);
SPI0_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI0_SS_T_n,
O => SPI0_SS_T
);
SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MISO_T_n,
O => SPI1_MISO_T
);
SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_MOSI_T_n,
O => SPI1_MOSI_T
);
SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SCLK_T_n,
O => SPI1_SCLK_T
);
SPI1_SS_T_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => SPI1_SS_T_n,
O => SPI1_SS_T
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(0),
O => FCLK_CLK0
);
\buffer_fclk_clk_1.FCLK_CLK_1_BUFG\: unisim.vcomponents.BUFG
port map (
I => FCLK_CLK_unbuffered(1),
O => FCLK_CLK1
);
\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(0),
PAD => MIO(0)
);
\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(10),
PAD => MIO(10)
);
\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(11),
PAD => MIO(11)
);
\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(12),
PAD => MIO(12)
);
\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(13),
PAD => MIO(13)
);
\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(14),
PAD => MIO(14)
);
\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(15),
PAD => MIO(15)
);
\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(16),
PAD => MIO(16)
);
\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(17),
PAD => MIO(17)
);
\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(18),
PAD => MIO(18)
);
\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(19),
PAD => MIO(19)
);
\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(1),
PAD => MIO(1)
);
\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(20),
PAD => MIO(20)
);
\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(21),
PAD => MIO(21)
);
\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(22),
PAD => MIO(22)
);
\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(23),
PAD => MIO(23)
);
\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(24),
PAD => MIO(24)
);
\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(25),
PAD => MIO(25)
);
\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(26),
PAD => MIO(26)
);
\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(27),
PAD => MIO(27)
);
\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(28),
PAD => MIO(28)
);
\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(29),
PAD => MIO(29)
);
\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(2),
PAD => MIO(2)
);
\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(30),
PAD => MIO(30)
);
\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(31),
PAD => MIO(31)
);
\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(32),
PAD => MIO(32)
);
\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(33),
PAD => MIO(33)
);
\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(34),
PAD => MIO(34)
);
\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(35),
PAD => MIO(35)
);
\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(36),
PAD => MIO(36)
);
\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(37),
PAD => MIO(37)
);
\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(38),
PAD => MIO(38)
);
\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(39),
PAD => MIO(39)
);
\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(3),
PAD => MIO(3)
);
\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(40),
PAD => MIO(40)
);
\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(41),
PAD => MIO(41)
);
\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(42),
PAD => MIO(42)
);
\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(43),
PAD => MIO(43)
);
\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(44),
PAD => MIO(44)
);
\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(45),
PAD => MIO(45)
);
\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(46),
PAD => MIO(46)
);
\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(47),
PAD => MIO(47)
);
\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(48),
PAD => MIO(48)
);
\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(49),
PAD => MIO(49)
);
\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(4),
PAD => MIO(4)
);
\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(50),
PAD => MIO(50)
);
\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(51),
PAD => MIO(51)
);
\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(52),
PAD => MIO(52)
);
\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(53),
PAD => MIO(53)
);
\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(5),
PAD => MIO(5)
);
\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(6),
PAD => MIO(6)
);
\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(7),
PAD => MIO(7)
);
\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(8),
PAD => MIO(8)
);
\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_MIO(9),
PAD => MIO(9)
);
\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(0),
PAD => DDR_BankAddr(0)
);
\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(1),
PAD => DDR_BankAddr(1)
);
\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_BankAddr(2),
PAD => DDR_BankAddr(2)
);
\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(0),
PAD => DDR_Addr(0)
);
\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(10),
PAD => DDR_Addr(10)
);
\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(11),
PAD => DDR_Addr(11)
);
\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(12),
PAD => DDR_Addr(12)
);
\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(13),
PAD => DDR_Addr(13)
);
\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(14),
PAD => DDR_Addr(14)
);
\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(1),
PAD => DDR_Addr(1)
);
\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(2),
PAD => DDR_Addr(2)
);
\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(3),
PAD => DDR_Addr(3)
);
\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(4),
PAD => DDR_Addr(4)
);
\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(5),
PAD => DDR_Addr(5)
);
\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(6),
PAD => DDR_Addr(6)
);
\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(7),
PAD => DDR_Addr(7)
);
\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(8),
PAD => DDR_Addr(8)
);
\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_Addr(9),
PAD => DDR_Addr(9)
);
\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(0),
PAD => DDR_DM(0)
);
\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(1),
PAD => DDR_DM(1)
);
\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(2),
PAD => DDR_DM(2)
);
\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DM(3),
PAD => DDR_DM(3)
);
\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(0),
PAD => DDR_DQ(0)
);
\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(10),
PAD => DDR_DQ(10)
);
\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(11),
PAD => DDR_DQ(11)
);
\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(12),
PAD => DDR_DQ(12)
);
\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(13),
PAD => DDR_DQ(13)
);
\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(14),
PAD => DDR_DQ(14)
);
\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(15),
PAD => DDR_DQ(15)
);
\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(16),
PAD => DDR_DQ(16)
);
\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(17),
PAD => DDR_DQ(17)
);
\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(18),
PAD => DDR_DQ(18)
);
\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(19),
PAD => DDR_DQ(19)
);
\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(1),
PAD => DDR_DQ(1)
);
\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(20),
PAD => DDR_DQ(20)
);
\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(21),
PAD => DDR_DQ(21)
);
\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(22),
PAD => DDR_DQ(22)
);
\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(23),
PAD => DDR_DQ(23)
);
\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(24),
PAD => DDR_DQ(24)
);
\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(25),
PAD => DDR_DQ(25)
);
\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(26),
PAD => DDR_DQ(26)
);
\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(27),
PAD => DDR_DQ(27)
);
\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(28),
PAD => DDR_DQ(28)
);
\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(29),
PAD => DDR_DQ(29)
);
\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(2),
PAD => DDR_DQ(2)
);
\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(30),
PAD => DDR_DQ(30)
);
\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(31),
PAD => DDR_DQ(31)
);
\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(3),
PAD => DDR_DQ(3)
);
\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(4),
PAD => DDR_DQ(4)
);
\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(5),
PAD => DDR_DQ(5)
);
\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(6),
PAD => DDR_DQ(6)
);
\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(7),
PAD => DDR_DQ(7)
);
\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(8),
PAD => DDR_DQ(8)
);
\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQ(9),
PAD => DDR_DQ(9)
);
\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(0),
PAD => DDR_DQS_n(0)
);
\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(1),
PAD => DDR_DQS_n(1)
);
\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(2),
PAD => DDR_DQS_n(2)
);
\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS_n(3),
PAD => DDR_DQS_n(3)
);
\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(0),
PAD => DDR_DQS(0)
);
\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(1),
PAD => DDR_DQS(1)
);
\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(2),
PAD => DDR_DQS(2)
);
\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF
port map (
IO => buffered_DDR_DQS(3),
PAD => DDR_DQS(3)
);
i_0: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[0]\
);
i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(1)
);
i_10: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(1)
);
i_11: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[7]\(0)
);
i_12: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(1)
);
i_13: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[6]\(0)
);
i_14: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(1)
);
i_15: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[5]\(0)
);
i_16: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(1)
);
i_17: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[4]\(0)
);
i_18: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(1)
);
i_19: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[3]\(0)
);
i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[0]\(0)
);
i_20: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(1)
);
i_21: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[2]\(0)
);
i_22: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(1)
);
i_23: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_DATA_PIPE[1]\(0)
);
i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[7]\
);
i_4: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[6]\
);
i_5: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[5]\
);
i_6: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[4]\
);
i_7: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[3]\
);
i_8: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[2]\
);
i_9: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => '0',
O => \TRACE_CTL_PIPE[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC;
signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC;
signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC;
signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC;
signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC;
signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_DM_WIDTH : integer;
attribute C_DM_WIDTH of inst : label is 4;
attribute C_DQS_WIDTH : integer;
attribute C_DQS_WIDTH of inst : label is 4;
attribute C_DQ_WIDTH : integer;
attribute C_DQ_WIDTH of inst : label is 32;
attribute C_EMIO_GPIO_WIDTH : integer;
attribute C_EMIO_GPIO_WIDTH of inst : label is 64;
attribute C_EN_EMIO_ENET0 : integer;
attribute C_EN_EMIO_ENET0 of inst : label is 0;
attribute C_EN_EMIO_ENET1 : integer;
attribute C_EN_EMIO_ENET1 of inst : label is 0;
attribute C_EN_EMIO_PJTAG : integer;
attribute C_EN_EMIO_PJTAG of inst : label is 0;
attribute C_EN_EMIO_TRACE : integer;
attribute C_EN_EMIO_TRACE of inst : label is 0;
attribute C_FCLK_CLK0_BUF : string;
attribute C_FCLK_CLK0_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK1_BUF : string;
attribute C_FCLK_CLK1_BUF of inst : label is "TRUE";
attribute C_FCLK_CLK2_BUF : string;
attribute C_FCLK_CLK2_BUF of inst : label is "FALSE";
attribute C_FCLK_CLK3_BUF : string;
attribute C_FCLK_CLK3_BUF of inst : label is "FALSE";
attribute C_GP0_EN_MODIFIABLE_TXN : integer;
attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_GP1_EN_MODIFIABLE_TXN : integer;
attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1;
attribute C_INCLUDE_ACP_TRANS_CHECK : integer;
attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0;
attribute C_INCLUDE_TRACE_BUFFER : integer;
attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0;
attribute C_IRQ_F2P_MODE : string;
attribute C_IRQ_F2P_MODE of inst : label is "DIRECT";
attribute C_MIO_PRIMITIVE : integer;
attribute C_MIO_PRIMITIVE of inst : label is 54;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP0_ID_WIDTH : integer;
attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer;
attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0;
attribute C_M_AXI_GP1_ID_WIDTH : integer;
attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer;
attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12;
attribute C_NUM_F2P_INTR_INPUTS : integer;
attribute C_NUM_F2P_INTR_INPUTS of inst : label is 1;
attribute C_PACKAGE_NAME : string;
attribute C_PACKAGE_NAME of inst : label is "clg484";
attribute C_PS7_SI_REV : string;
attribute C_PS7_SI_REV of inst : label is "PRODUCTION";
attribute C_S_AXI_ACP_ARUSER_VAL : integer;
attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_AWUSER_VAL : integer;
attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31;
attribute C_S_AXI_ACP_ID_WIDTH : integer;
attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3;
attribute C_S_AXI_GP0_ID_WIDTH : integer;
attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_GP1_ID_WIDTH : integer;
attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP0_DATA_WIDTH : integer;
attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP0_ID_WIDTH : integer;
attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP1_DATA_WIDTH : integer;
attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP1_ID_WIDTH : integer;
attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP2_DATA_WIDTH : integer;
attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP2_ID_WIDTH : integer;
attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6;
attribute C_S_AXI_HP3_DATA_WIDTH : integer;
attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64;
attribute C_S_AXI_HP3_ID_WIDTH : integer;
attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6;
attribute C_TRACE_BUFFER_CLOCK_DELAY : integer;
attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12;
attribute C_TRACE_BUFFER_FIFO_SIZE : integer;
attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128;
attribute C_TRACE_INTERNAL_WIDTH : integer;
attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2;
attribute C_TRACE_PIPELINE_WIDTH : integer;
attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8;
attribute C_USE_AXI_NONSECURE : integer;
attribute C_USE_AXI_NONSECURE of inst : label is 0;
attribute C_USE_DEFAULT_ACP_USER_VAL : integer;
attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0;
attribute C_USE_M_AXI_GP0 : integer;
attribute C_USE_M_AXI_GP0 of inst : label is 1;
attribute C_USE_M_AXI_GP1 : integer;
attribute C_USE_M_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_ACP : integer;
attribute C_USE_S_AXI_ACP of inst : label is 0;
attribute C_USE_S_AXI_GP0 : integer;
attribute C_USE_S_AXI_GP0 of inst : label is 0;
attribute C_USE_S_AXI_GP1 : integer;
attribute C_USE_S_AXI_GP1 of inst : label is 0;
attribute C_USE_S_AXI_HP0 : integer;
attribute C_USE_S_AXI_HP0 of inst : label is 0;
attribute C_USE_S_AXI_HP1 : integer;
attribute C_USE_S_AXI_HP1 of inst : label is 0;
attribute C_USE_S_AXI_HP2 : integer;
attribute C_USE_S_AXI_HP2 of inst : label is 0;
attribute C_USE_S_AXI_HP3 : integer;
attribute C_USE_S_AXI_HP3 of inst : label is 0;
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of inst : label is "ip_design_processing_system7_0_0.hwdef";
attribute POWER : string;
attribute POWER of inst : label is "<PROCESSOR name={system} numA9Cores={2} clockFreq={666.666667} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={533.333313} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={10} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={Timer} ioStandard={} bidis={0} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={111.111115} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={8} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200.000000} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>";
attribute USE_TRACE_DATA_EDGE_DETECTOR : integer;
attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of FCLK_CLK1 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK1 CLK";
attribute X_INTERFACE_PARAMETER of FCLK_CLK1 : signal is "XIL_INTERFACENAME FCLK_CLK1, FREQ_HZ 10000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK1";
attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST";
attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of I2C0_SCL_I : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_I";
attribute X_INTERFACE_INFO of I2C0_SCL_O : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_O";
attribute X_INTERFACE_INFO of I2C0_SCL_T : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_T";
attribute X_INTERFACE_INFO of I2C0_SDA_I : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_I";
attribute X_INTERFACE_INFO of I2C0_SDA_O : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_O";
attribute X_INTERFACE_INFO of I2C0_SDA_T : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_T";
attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST";
attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY";
attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID";
attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT";
attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT";
attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11";
attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS";
attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE";
attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID";
attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA";
attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 100000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID";
attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP";
attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA";
attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID";
attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB";
attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
port map (
CAN0_PHY_RX => '0',
CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED,
CAN1_PHY_RX => '0',
CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED,
Core0_nFIQ => '0',
Core0_nIRQ => '0',
Core1_nFIQ => '0',
Core1_nIRQ => '0',
DDR_ARB(3 downto 0) => B"0000",
DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0),
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM(3 downto 0) => DDR_DM(3 downto 0),
DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0),
DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0),
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
DDR_WEB => DDR_WEB,
DMA0_ACLK => '0',
DMA0_DAREADY => '0',
DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0),
DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED,
DMA0_DRLAST => '0',
DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED,
DMA0_DRTYPE(1 downto 0) => B"00",
DMA0_DRVALID => '0',
DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED,
DMA1_ACLK => '0',
DMA1_DAREADY => '0',
DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0),
DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED,
DMA1_DRLAST => '0',
DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED,
DMA1_DRTYPE(1 downto 0) => B"00",
DMA1_DRVALID => '0',
DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED,
DMA2_ACLK => '0',
DMA2_DAREADY => '0',
DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0),
DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED,
DMA2_DRLAST => '0',
DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED,
DMA2_DRTYPE(1 downto 0) => B"00",
DMA2_DRVALID => '0',
DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED,
DMA3_ACLK => '0',
DMA3_DAREADY => '0',
DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0),
DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED,
DMA3_DRLAST => '0',
DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED,
DMA3_DRTYPE(1 downto 0) => B"00",
DMA3_DRVALID => '0',
DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED,
ENET0_EXT_INTIN => '0',
ENET0_GMII_COL => '0',
ENET0_GMII_CRS => '0',
ENET0_GMII_RXD(7 downto 0) => B"00000000",
ENET0_GMII_RX_CLK => '0',
ENET0_GMII_RX_DV => '0',
ENET0_GMII_RX_ER => '0',
ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0),
ENET0_GMII_TX_CLK => '0',
ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED,
ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED,
ENET0_MDIO_I => '0',
ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED,
ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED,
ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED,
ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED,
ENET1_EXT_INTIN => '0',
ENET1_GMII_COL => '0',
ENET1_GMII_CRS => '0',
ENET1_GMII_RXD(7 downto 0) => B"00000000",
ENET1_GMII_RX_CLK => '0',
ENET1_GMII_RX_DV => '0',
ENET1_GMII_RX_ER => '0',
ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0),
ENET1_GMII_TX_CLK => '0',
ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED,
ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED,
ENET1_MDIO_I => '0',
ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED,
ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED,
ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED,
ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED,
ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED,
EVENT_EVENTI => '0',
EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED,
EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0),
EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0),
FCLK_CLK0 => FCLK_CLK0,
FCLK_CLK1 => FCLK_CLK1,
FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED,
FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED,
FCLK_CLKTRIG0_N => '0',
FCLK_CLKTRIG1_N => '0',
FCLK_CLKTRIG2_N => '0',
FCLK_CLKTRIG3_N => '0',
FCLK_RESET0_N => FCLK_RESET0_N,
FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED,
FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED,
FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED,
FPGA_IDLE_N => '0',
FTMD_TRACEIN_ATID(3 downto 0) => B"0000",
FTMD_TRACEIN_CLK => '0',
FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000",
FTMD_TRACEIN_VALID => '0',
FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000",
FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED,
FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED,
FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED,
FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED,
FTMT_F2P_TRIG_0 => '0',
FTMT_F2P_TRIG_1 => '0',
FTMT_F2P_TRIG_2 => '0',
FTMT_F2P_TRIG_3 => '0',
FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0),
FTMT_P2F_TRIGACK_0 => '0',
FTMT_P2F_TRIGACK_1 => '0',
FTMT_P2F_TRIGACK_2 => '0',
FTMT_P2F_TRIGACK_3 => '0',
FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED,
FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED,
FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED,
FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED,
GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0),
GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0),
I2C0_SCL_I => I2C0_SCL_I,
I2C0_SCL_O => I2C0_SCL_O,
I2C0_SCL_T => I2C0_SCL_T,
I2C0_SDA_I => I2C0_SDA_I,
I2C0_SDA_O => I2C0_SDA_O,
I2C0_SDA_T => I2C0_SDA_T,
I2C1_SCL_I => '0',
I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED,
I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED,
I2C1_SDA_I => '0',
I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED,
I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED,
IRQ_F2P(0) => '0',
IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED,
IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED,
IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED,
IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED,
IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED,
IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED,
IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED,
IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED,
IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED,
IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED,
IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED,
IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED,
IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED,
IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED,
IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED,
IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED,
IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED,
IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED,
IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED,
IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED,
IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED,
IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED,
IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED,
IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED,
IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED,
IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED,
IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED,
IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED,
IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED,
MIO(53 downto 0) => MIO(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK,
M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED,
M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => '0',
M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED,
M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_ARREADY => '0',
M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED,
M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP1_AWREADY => '0',
M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED,
M_AXI_GP1_BID(11 downto 0) => B"000000000000",
M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED,
M_AXI_GP1_BRESP(1 downto 0) => B"00",
M_AXI_GP1_BVALID => '0',
M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP1_RID(11 downto 0) => B"000000000000",
M_AXI_GP1_RLAST => '0',
M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED,
M_AXI_GP1_RRESP(1 downto 0) => B"00",
M_AXI_GP1_RVALID => '0',
M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0),
M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED,
M_AXI_GP1_WREADY => '0',
M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED,
PJTAG_TCK => '0',
PJTAG_TDI => '0',
PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED,
PJTAG_TMS => '0',
PS_CLK => PS_CLK,
PS_PORB => PS_PORB,
PS_SRSTB => PS_SRSTB,
SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED,
SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO0_CDN => '0',
SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED,
SDIO0_CLK_FB => '0',
SDIO0_CMD_I => '0',
SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED,
SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED,
SDIO0_DATA_I(3 downto 0) => B"0000",
SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0),
SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0),
SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED,
SDIO0_WP => '0',
SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED,
SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0),
SDIO1_CDN => '0',
SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED,
SDIO1_CLK_FB => '0',
SDIO1_CMD_I => '0',
SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED,
SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED,
SDIO1_DATA_I(3 downto 0) => B"0000",
SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0),
SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0),
SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED,
SDIO1_WP => '0',
SPI0_MISO_I => '0',
SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED,
SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED,
SPI0_MOSI_I => '0',
SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED,
SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED,
SPI0_SCLK_I => '0',
SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED,
SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED,
SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED,
SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED,
SPI0_SS_I => '0',
SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED,
SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED,
SPI1_MISO_I => '0',
SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED,
SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED,
SPI1_MOSI_I => '0',
SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED,
SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED,
SPI1_SCLK_I => '0',
SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED,
SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED,
SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED,
SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED,
SPI1_SS_I => '0',
SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED,
SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED,
SRAM_INTIN => '0',
S_AXI_ACP_ACLK => '0',
S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_ARBURST(1 downto 0) => B"00",
S_AXI_ACP_ARCACHE(3 downto 0) => B"0000",
S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED,
S_AXI_ACP_ARID(2 downto 0) => B"000",
S_AXI_ACP_ARLEN(3 downto 0) => B"0000",
S_AXI_ACP_ARLOCK(1 downto 0) => B"00",
S_AXI_ACP_ARPROT(2 downto 0) => B"000",
S_AXI_ACP_ARQOS(3 downto 0) => B"0000",
S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED,
S_AXI_ACP_ARSIZE(2 downto 0) => B"000",
S_AXI_ACP_ARUSER(4 downto 0) => B"00000",
S_AXI_ACP_ARVALID => '0',
S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_ACP_AWBURST(1 downto 0) => B"00",
S_AXI_ACP_AWCACHE(3 downto 0) => B"0000",
S_AXI_ACP_AWID(2 downto 0) => B"000",
S_AXI_ACP_AWLEN(3 downto 0) => B"0000",
S_AXI_ACP_AWLOCK(1 downto 0) => B"00",
S_AXI_ACP_AWPROT(2 downto 0) => B"000",
S_AXI_ACP_AWQOS(3 downto 0) => B"0000",
S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED,
S_AXI_ACP_AWSIZE(2 downto 0) => B"000",
S_AXI_ACP_AWUSER(4 downto 0) => B"00000",
S_AXI_ACP_AWVALID => '0',
S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0),
S_AXI_ACP_BREADY => '0',
S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED,
S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0),
S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0),
S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED,
S_AXI_ACP_RREADY => '0',
S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0),
S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED,
S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_ACP_WID(2 downto 0) => B"000",
S_AXI_ACP_WLAST => '0',
S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED,
S_AXI_ACP_WSTRB(7 downto 0) => B"00000000",
S_AXI_ACP_WVALID => '0',
S_AXI_GP0_ACLK => '0',
S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_ARBURST(1 downto 0) => B"00",
S_AXI_GP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED,
S_AXI_GP0_ARID(5 downto 0) => B"000000",
S_AXI_GP0_ARLEN(3 downto 0) => B"0000",
S_AXI_GP0_ARLOCK(1 downto 0) => B"00",
S_AXI_GP0_ARPROT(2 downto 0) => B"000",
S_AXI_GP0_ARQOS(3 downto 0) => B"0000",
S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED,
S_AXI_GP0_ARSIZE(2 downto 0) => B"000",
S_AXI_GP0_ARVALID => '0',
S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_AWBURST(1 downto 0) => B"00",
S_AXI_GP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP0_AWID(5 downto 0) => B"000000",
S_AXI_GP0_AWLEN(3 downto 0) => B"0000",
S_AXI_GP0_AWLOCK(1 downto 0) => B"00",
S_AXI_GP0_AWPROT(2 downto 0) => B"000",
S_AXI_GP0_AWQOS(3 downto 0) => B"0000",
S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED,
S_AXI_GP0_AWSIZE(2 downto 0) => B"000",
S_AXI_GP0_AWVALID => '0',
S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0),
S_AXI_GP0_BREADY => '0',
S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED,
S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0),
S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED,
S_AXI_GP0_RREADY => '0',
S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED,
S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP0_WID(5 downto 0) => B"000000",
S_AXI_GP0_WLAST => '0',
S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED,
S_AXI_GP0_WSTRB(3 downto 0) => B"0000",
S_AXI_GP0_WVALID => '0',
S_AXI_GP1_ACLK => '0',
S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_ARBURST(1 downto 0) => B"00",
S_AXI_GP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED,
S_AXI_GP1_ARID(5 downto 0) => B"000000",
S_AXI_GP1_ARLEN(3 downto 0) => B"0000",
S_AXI_GP1_ARLOCK(1 downto 0) => B"00",
S_AXI_GP1_ARPROT(2 downto 0) => B"000",
S_AXI_GP1_ARQOS(3 downto 0) => B"0000",
S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED,
S_AXI_GP1_ARSIZE(2 downto 0) => B"000",
S_AXI_GP1_ARVALID => '0',
S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_AWBURST(1 downto 0) => B"00",
S_AXI_GP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_GP1_AWID(5 downto 0) => B"000000",
S_AXI_GP1_AWLEN(3 downto 0) => B"0000",
S_AXI_GP1_AWLOCK(1 downto 0) => B"00",
S_AXI_GP1_AWPROT(2 downto 0) => B"000",
S_AXI_GP1_AWQOS(3 downto 0) => B"0000",
S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED,
S_AXI_GP1_AWSIZE(2 downto 0) => B"000",
S_AXI_GP1_AWVALID => '0',
S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0),
S_AXI_GP1_BREADY => '0',
S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED,
S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0),
S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0),
S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED,
S_AXI_GP1_RREADY => '0',
S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED,
S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_GP1_WID(5 downto 0) => B"000000",
S_AXI_GP1_WLAST => '0',
S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED,
S_AXI_GP1_WSTRB(3 downto 0) => B"0000",
S_AXI_GP1_WVALID => '0',
S_AXI_HP0_ACLK => '0',
S_AXI_HP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_ARBURST(1 downto 0) => B"00",
S_AXI_HP0_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED,
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => B"0000",
S_AXI_HP0_ARLOCK(1 downto 0) => B"00",
S_AXI_HP0_ARPROT(2 downto 0) => B"000",
S_AXI_HP0_ARQOS(3 downto 0) => B"0000",
S_AXI_HP0_ARREADY => NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED,
S_AXI_HP0_ARSIZE(2 downto 0) => B"000",
S_AXI_HP0_ARVALID => '0',
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_inst_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_inst_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED,
S_AXI_HP0_RREADY => '0',
S_AXI_HP0_RRESP(1 downto 0) => NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_RVALID => NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0',
S_AXI_HP1_ACLK => '0',
S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_ARBURST(1 downto 0) => B"00",
S_AXI_HP1_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED,
S_AXI_HP1_ARID(5 downto 0) => B"000000",
S_AXI_HP1_ARLEN(3 downto 0) => B"0000",
S_AXI_HP1_ARLOCK(1 downto 0) => B"00",
S_AXI_HP1_ARPROT(2 downto 0) => B"000",
S_AXI_HP1_ARQOS(3 downto 0) => B"0000",
S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED,
S_AXI_HP1_ARSIZE(2 downto 0) => B"000",
S_AXI_HP1_ARVALID => '0',
S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP1_AWBURST(1 downto 0) => B"00",
S_AXI_HP1_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP1_AWID(5 downto 0) => B"000000",
S_AXI_HP1_AWLEN(3 downto 0) => B"0000",
S_AXI_HP1_AWLOCK(1 downto 0) => B"00",
S_AXI_HP1_AWPROT(2 downto 0) => B"000",
S_AXI_HP1_AWQOS(3 downto 0) => B"0000",
S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED,
S_AXI_HP1_AWSIZE(2 downto 0) => B"000",
S_AXI_HP1_AWVALID => '0',
S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0),
S_AXI_HP1_BREADY => '0',
S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED,
S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP1_RDISSUECAP1_EN => '0',
S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0),
S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED,
S_AXI_HP1_RREADY => '0',
S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED,
S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP1_WID(5 downto 0) => B"000000",
S_AXI_HP1_WLAST => '0',
S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED,
S_AXI_HP1_WRISSUECAP1_EN => '0',
S_AXI_HP1_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP1_WVALID => '0',
S_AXI_HP2_ACLK => '0',
S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_ARBURST(1 downto 0) => B"00",
S_AXI_HP2_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED,
S_AXI_HP2_ARID(5 downto 0) => B"000000",
S_AXI_HP2_ARLEN(3 downto 0) => B"0000",
S_AXI_HP2_ARLOCK(1 downto 0) => B"00",
S_AXI_HP2_ARPROT(2 downto 0) => B"000",
S_AXI_HP2_ARQOS(3 downto 0) => B"0000",
S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED,
S_AXI_HP2_ARSIZE(2 downto 0) => B"000",
S_AXI_HP2_ARVALID => '0',
S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP2_AWBURST(1 downto 0) => B"00",
S_AXI_HP2_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP2_AWID(5 downto 0) => B"000000",
S_AXI_HP2_AWLEN(3 downto 0) => B"0000",
S_AXI_HP2_AWLOCK(1 downto 0) => B"00",
S_AXI_HP2_AWPROT(2 downto 0) => B"000",
S_AXI_HP2_AWQOS(3 downto 0) => B"0000",
S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED,
S_AXI_HP2_AWSIZE(2 downto 0) => B"000",
S_AXI_HP2_AWVALID => '0',
S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0),
S_AXI_HP2_BREADY => '0',
S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED,
S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP2_RDISSUECAP1_EN => '0',
S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0),
S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED,
S_AXI_HP2_RREADY => '0',
S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED,
S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP2_WID(5 downto 0) => B"000000",
S_AXI_HP2_WLAST => '0',
S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED,
S_AXI_HP2_WRISSUECAP1_EN => '0',
S_AXI_HP2_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP2_WVALID => '0',
S_AXI_HP3_ACLK => '0',
S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_ARBURST(1 downto 0) => B"00",
S_AXI_HP3_ARCACHE(3 downto 0) => B"0000",
S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED,
S_AXI_HP3_ARID(5 downto 0) => B"000000",
S_AXI_HP3_ARLEN(3 downto 0) => B"0000",
S_AXI_HP3_ARLOCK(1 downto 0) => B"00",
S_AXI_HP3_ARPROT(2 downto 0) => B"000",
S_AXI_HP3_ARQOS(3 downto 0) => B"0000",
S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED,
S_AXI_HP3_ARSIZE(2 downto 0) => B"000",
S_AXI_HP3_ARVALID => '0',
S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP3_AWBURST(1 downto 0) => B"00",
S_AXI_HP3_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP3_AWID(5 downto 0) => B"000000",
S_AXI_HP3_AWLEN(3 downto 0) => B"0000",
S_AXI_HP3_AWLOCK(1 downto 0) => B"00",
S_AXI_HP3_AWPROT(2 downto 0) => B"000",
S_AXI_HP3_AWQOS(3 downto 0) => B"0000",
S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED,
S_AXI_HP3_AWSIZE(2 downto 0) => B"000",
S_AXI_HP3_AWVALID => '0',
S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0),
S_AXI_HP3_BREADY => '0',
S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED,
S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0),
S_AXI_HP3_RDISSUECAP1_EN => '0',
S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0),
S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED,
S_AXI_HP3_RREADY => '0',
S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0),
S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED,
S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP3_WID(5 downto 0) => B"000000",
S_AXI_HP3_WLAST => '0',
S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED,
S_AXI_HP3_WRISSUECAP1_EN => '0',
S_AXI_HP3_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP3_WVALID => '0',
TRACE_CLK => '0',
TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED,
TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED,
TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0),
TTC0_CLK0_IN => '0',
TTC0_CLK1_IN => '0',
TTC0_CLK2_IN => '0',
TTC0_WAVE0_OUT => TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT => TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT => TTC0_WAVE2_OUT,
TTC1_CLK0_IN => '0',
TTC1_CLK1_IN => '0',
TTC1_CLK2_IN => '0',
TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED,
TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED,
TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED,
UART0_CTSN => '0',
UART0_DCDN => '0',
UART0_DSRN => '0',
UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED,
UART0_RIN => '0',
UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED,
UART0_RX => '1',
UART0_TX => NLW_inst_UART0_TX_UNCONNECTED,
UART1_CTSN => '0',
UART1_DCDN => '0',
UART1_DSRN => '0',
UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED,
UART1_RIN => '0',
UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED,
UART1_RX => '1',
UART1_TX => NLW_inst_UART1_TX_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0),
USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT,
USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT,
USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB1_VBUS_PWRFAULT => '0',
USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED,
WDT_CLK_IN => '0',
WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED
);
end STRUCTURE;
| mit | 3203fa06c73ac44cc8fdcc99aa74b885 | 0.639696 | 2.763956 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-digilent-nexys4/config.vhd | 1 | 7,716 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := artix7;
constant CFG_MEMTECH : integer := artix7;
constant CFG_PADTECH : integer := artix7;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := artix7;
constant CFG_CLKMUL : integer := (10);
constant CFG_CLKDIV : integer := (20);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 4;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 1 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 1;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000000#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 4;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 1;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 1;
end;
| gpl-2.0 | 531a2fa82d4d4ce2d46bf8aca5a85f22 | 0.653836 | 3.577191 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/ip_repo/ac.uk_user_lms_pcore_1.0/hdl/vhdl/lms_pcore_axi_lite.vhd | 2 | 10,041 | -- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\lms_pcore_axi_lite.vhd
-- Created: 2015-06-19 16:39:46
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: lms_pcore_axi_lite
-- Source Path: lms_pcore/lms_pcore_axi_lite
-- Hierarchy Level: 1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY lms_pcore_axi_lite IS
PORT( reset : IN std_logic;
AXI4_Lite_ACLK : IN std_logic; -- ufix1
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
read_cop_out_ready : IN std_logic; -- ufix1
cop_reg_strobe : IN std_logic; -- ufix1
read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic; -- ufix1
write_axi_enable : OUT std_logic; -- ufix1
strobe_cop_in_strobe : OUT std_logic; -- ufix1
write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
write_d_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
reset_internal : OUT std_logic -- ufix1
);
END lms_pcore_axi_lite;
ARCHITECTURE rtl OF lms_pcore_axi_lite IS
-- Component Declarations
COMPONENT lms_pcore_addr_decoder
PORT( clk : IN std_logic; -- ufix1
reset : IN std_logic;
data_write : IN std_logic_vector(31 DOWNTO 0); -- ufix32
addr_sel : IN std_logic_vector(13 DOWNTO 0); -- ufix14
wr_enb : IN std_logic; -- ufix1
rd_enb : IN std_logic; -- ufix1
read_cop_out_ready : IN std_logic; -- ufix1
cop_reg_strobe : IN std_logic; -- ufix1
read_e_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
data_read : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
write_axi_enable : OUT std_logic; -- ufix1
strobe_cop_in_strobe : OUT std_logic; -- ufix1
write_x_k : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En14
write_d_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END COMPONENT;
COMPONENT lms_pcore_axi_lite_module
PORT( clk : IN std_logic; -- ufix1
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
data_read : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic; -- ufix1
data_write : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
addr_sel : OUT std_logic_vector(13 DOWNTO 0); -- ufix14
wr_enb : OUT std_logic; -- ufix1
rd_enb : OUT std_logic; -- ufix1
reset_internal : OUT std_logic -- ufix1
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : lms_pcore_addr_decoder
USE ENTITY work.lms_pcore_addr_decoder(rtl);
FOR ALL : lms_pcore_axi_lite_module
USE ENTITY work.lms_pcore_axi_lite_module(rtl);
-- Signals
SIGNAL top_data_write : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL top_addr_sel : std_logic_vector(13 DOWNTO 0); -- ufix14
SIGNAL top_wr_enb : std_logic; -- ufix1
SIGNAL top_rd_enb : std_logic; -- ufix1
SIGNAL top_data_read : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL write_x_k_tmp : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL write_d_k_tmp : std_logic_vector(15 DOWNTO 0); -- ufix16
SIGNAL AXI4_Lite_BRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL AXI4_Lite_RDATA_tmp : std_logic_vector(31 DOWNTO 0); -- ufix32
SIGNAL AXI4_Lite_RRESP_tmp : std_logic_vector(1 DOWNTO 0); -- ufix2
SIGNAL top_reset_internal : std_logic; -- ufix1
BEGIN
u_lms_pcore_addr_decoder_inst : lms_pcore_addr_decoder
PORT MAP( clk => AXI4_Lite_ACLK, -- ufix1
reset => reset,
data_write => top_data_write, -- ufix32
addr_sel => top_addr_sel, -- ufix14
wr_enb => top_wr_enb, -- ufix1
rd_enb => top_rd_enb, -- ufix1
read_cop_out_ready => read_cop_out_ready, -- ufix1
cop_reg_strobe => cop_reg_strobe, -- ufix1
read_e_k => read_e_k, -- sfix16_En14
data_read => top_data_read, -- ufix32
write_axi_enable => write_axi_enable, -- ufix1
strobe_cop_in_strobe => strobe_cop_in_strobe, -- ufix1
write_x_k => write_x_k_tmp, -- sfix16_En14
write_d_k => write_d_k_tmp -- sfix16_En14
);
u_lms_pcore_axi_lite_module_inst : lms_pcore_axi_lite_module
PORT MAP( clk => AXI4_Lite_ACLK, -- ufix1
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN, -- ufix1
AXI4_Lite_AWADDR => AXI4_Lite_AWADDR, -- ufix16
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID, -- ufix1
AXI4_Lite_WDATA => AXI4_Lite_WDATA, -- ufix32
AXI4_Lite_WSTRB => AXI4_Lite_WSTRB, -- ufix4
AXI4_Lite_WVALID => AXI4_Lite_WVALID, -- ufix1
AXI4_Lite_BREADY => AXI4_Lite_BREADY, -- ufix1
AXI4_Lite_ARADDR => AXI4_Lite_ARADDR, -- ufix16
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID, -- ufix1
AXI4_Lite_RREADY => AXI4_Lite_RREADY, -- ufix1
data_read => top_data_read, -- ufix32
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY, -- ufix1
AXI4_Lite_WREADY => AXI4_Lite_WREADY, -- ufix1
AXI4_Lite_BRESP => AXI4_Lite_BRESP_tmp, -- ufix2
AXI4_Lite_BVALID => AXI4_Lite_BVALID, -- ufix1
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY, -- ufix1
AXI4_Lite_RDATA => AXI4_Lite_RDATA_tmp, -- ufix32
AXI4_Lite_RRESP => AXI4_Lite_RRESP_tmp, -- ufix2
AXI4_Lite_RVALID => AXI4_Lite_RVALID, -- ufix1
data_write => top_data_write, -- ufix32
addr_sel => top_addr_sel, -- ufix14
wr_enb => top_wr_enb, -- ufix1
rd_enb => top_rd_enb, -- ufix1
reset_internal => top_reset_internal -- ufix1
);
reset_internal <= top_reset_internal;
AXI4_Lite_BRESP <= AXI4_Lite_BRESP_tmp;
AXI4_Lite_RDATA <= AXI4_Lite_RDATA_tmp;
AXI4_Lite_RRESP <= AXI4_Lite_RRESP_tmp;
write_x_k <= write_x_k_tmp;
write_d_k <= write_d_k_tmp;
END rtl;
| mit | 2c780162acad7add881f7b79197b6034 | 0.464197 | 3.555595 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/tech/cycloneiii/simprims/cycloneiii_atoms.vhd | 2 | 367,411 | -- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 9.0 Build 235 03/01/2009
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
package cycloneiii_atom_pack is
function str_to_bin (lut_mask : string ) return std_logic_vector;
function product(list : std_logic_vector) return std_logic ;
function alt_conv_integer(arg : in std_logic_vector) return integer;
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- Declare array types for CAM_SLICE
TYPE cycloneiii_mem_data IS ARRAY (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
function int2str( value : integer ) return string;
function map_x_to_0 (value : std_logic) return std_logic;
function SelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function int2bit (arg : boolean) return std_logic;
function int2bit (arg : integer) return std_logic;
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function calc_sum_len( widtha : integer; widthb : integer) return integer;
end cycloneiii_atom_pack;
library IEEE;
use IEEE.std_logic_1164.all;
package body cycloneiii_atom_pack is
type masklength is array (4 downto 1) of std_logic_vector(3 downto 0);
function str_to_bin (lut_mask : string) return std_logic_vector is
variable slice : masklength := (OTHERS => "0000");
variable mask : std_logic_vector(15 downto 0);
begin
for i in 1 to lut_mask'length loop
case lut_mask(i) is
when '0' => slice(i) := "0000";
when '1' => slice(i) := "0001";
when '2' => slice(i) := "0010";
when '3' => slice(i) := "0011";
when '4' => slice(i) := "0100";
when '5' => slice(i) := "0101";
when '6' => slice(i) := "0110";
when '7' => slice(i) := "0111";
when '8' => slice(i) := "1000";
when '9' => slice(i) := "1001";
when 'a' => slice(i) := "1010";
when 'A' => slice(i) := "1010";
when 'b' => slice(i) := "1011";
when 'B' => slice(i) := "1011";
when 'c' => slice(i) := "1100";
when 'C' => slice(i) := "1100";
when 'd' => slice(i) := "1101";
when 'D' => slice(i) := "1101";
when 'e' => slice(i) := "1110";
when 'E' => slice(i) := "1110";
when others => slice(i) := "1111";
end case;
end loop;
mask := (slice(1) & slice(2) & slice(3) & slice(4));
return (mask);
end str_to_bin;
function product (list: std_logic_vector) return std_logic is
begin
for i in 0 to 31 loop
if list(i) = '0' then
return ('0');
end if;
end loop;
return ('1');
end product;
function alt_conv_integer(arg : in std_logic_vector) return integer is
variable result : integer;
begin
result := 0;
for i in arg'range loop
if arg(i) = '1' then
result := result + 2**i;
end if;
end loop;
return result;
end alt_conv_integer;
function int2str( value : integer ) return string is
variable ivalue,index : integer;
variable digit : integer;
variable line_no: string(8 downto 1) := " ";
begin
ivalue := value;
index := 1;
if (ivalue = 0) then
line_no := " 0";
end if;
while (ivalue > 0) loop
digit := ivalue MOD 10;
ivalue := ivalue/10;
case digit is
when 0 =>
line_no(index) := '0';
when 1 =>
line_no(index) := '1';
when 2 =>
line_no(index) := '2';
when 3 =>
line_no(index) := '3';
when 4 =>
line_no(index) := '4';
when 5 =>
line_no(index) := '5';
when 6 =>
line_no(index) := '6';
when 7 =>
line_no(index) := '7';
when 8 =>
line_no(index) := '8';
when 9 =>
line_no(index) := '9';
when others =>
ASSERT FALSE
REPORT "Illegal number!"
SEVERITY ERROR;
end case;
index := index + 1;
end loop;
return line_no;
end;
function map_x_to_0 (value : std_logic) return std_logic is
begin
if (Is_X (value) = TRUE) then
return '0';
else
return value;
end if;
end;
function SelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function calc_sum_len( widtha : integer; widthb : integer) return integer is
variable result: integer;
begin
if(widtha >= widthb) then
result := widtha + 1;
else
result := widthb + 1;
end if;
return result;
end calc_sum_len;
end cycloneiii_atom_pack;
Library ieee;
use ieee.std_logic_1164.all;
Package cycloneiii_pllpack is
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer);
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer );
function gcd (X: integer; Y: integer) return integer;
function count_digit (X: integer) return integer;
function scale_num (X: integer; Y: integer) return integer;
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer) return integer;
function output_counter_value (clk_divide: integer; clk_mult : integer ;
M: integer; N: integer ) return integer;
function counter_mode (duty_cycle: integer; output_counter_value: integer) return string;
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer;
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer;
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer;
function counter_time_delay ( clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer;
function get_phase_degree (phase_shift: integer; clk_period: integer) return integer;
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer;
function counter_ph (tap_phase: integer; m : integer; n: integer) return integer;
function ph_adjust (tap_phase: integer; ph_base : integer) return integer;
function translate_string (mode : string) return string;
function str2int (s : string) return integer;
function dqs_str2int (s : string) return integer;
end cycloneiii_pllpack;
package body cycloneiii_pllpack is
-- finds the closest integer fraction of a given pair of numerator and denominator.
procedure find_simple_integer_fraction( numerator : in integer;
denominator : in integer;
max_denom : in integer;
fraction_num : out integer;
fraction_div : out integer) is
constant MAX_ITER : integer := 20;
type INT_ARRAY is array ((MAX_ITER-1) downto 0) of integer;
variable quotient_array : INT_ARRAY;
variable int_loop_iter : integer;
variable int_quot : integer;
variable m_value : integer;
variable d_value : integer;
variable old_m_value : integer;
variable swap : integer;
variable loop_iter : integer;
variable num : integer;
variable den : integer;
variable i_max_iter : integer;
begin
loop_iter := 0;
if (numerator = 0) then
num := 1;
else
num := numerator;
end if;
if (denominator = 0) then
den := 1;
else
den := denominator;
end if;
i_max_iter := max_iter;
while (loop_iter < i_max_iter) loop
int_quot := num / den;
quotient_array(loop_iter) := int_quot;
num := num - (den*int_quot);
loop_iter := loop_iter+1;
if ((num = 0) or (max_denom /= -1) or (loop_iter = i_max_iter)) then
-- calculate the numerator and denominator if there is a restriction on the
-- max denom value or if the loop is ending
m_value := 0;
d_value := 1;
-- get the rounded value at this stage for the remaining fraction
if (den /= 0) then
m_value := (2*num/den);
end if;
-- calculate the fraction numerator and denominator at this stage
for int_loop_iter in (loop_iter-1) downto 0 loop
if (m_value = 0) then
m_value := quotient_array(int_loop_iter);
d_value := 1;
else
old_m_value := m_value;
m_value := (quotient_array(int_loop_iter)*m_value) + d_value;
d_value := old_m_value;
end if;
end loop;
-- if the denominator is less than the maximum denom_value or if there is no restriction save it
if ((d_value <= max_denom) or (max_denom = -1)) then
if ((m_value = 0) or (d_value = 0)) then
fraction_num := numerator;
fraction_div := denominator;
else
fraction_num := m_value;
fraction_div := d_value;
end if;
end if;
-- end the loop if the denomitor has overflown or the numerator is zero (no remainder during this round)
if (((d_value > max_denom) and (max_denom /= -1)) or (num = 0)) then
i_max_iter := loop_iter;
end if;
end if;
-- swap the numerator and denominator for the next round
swap := den;
den := num;
num := swap;
end loop;
end find_simple_integer_fraction;
-- find the M and N values for Manual phase based on the following 5 criterias:
-- 1. The PFD frequency (i.e. Fin / N) must be in the range 5 MHz to 720 MHz
-- 2. The VCO frequency (i.e. Fin * M / N) must be in the range 300 MHz to 1300 MHz
-- 3. M is less than 512
-- 4. N is less than 512
-- 5. It's the smallest M/N which satisfies all the above constraints, and is within 2ps
-- of the desired vco-phase-shift-step
procedure find_m_and_n_4_manual_phase ( inclock_period : in integer;
vco_phase_shift_step : in integer;
clk0_mult: in integer; clk1_mult: in integer;
clk2_mult: in integer; clk3_mult: in integer;
clk4_mult: in integer; clk5_mult: in integer;
clk6_mult: in integer; clk7_mult: in integer;
clk8_mult: in integer; clk9_mult: in integer;
clk0_div : in integer; clk1_div : in integer;
clk2_div : in integer; clk3_div : in integer;
clk4_div : in integer; clk5_div : in integer;
clk6_div : in integer; clk7_div : in integer;
clk8_div : in integer; clk9_div : in integer;
clk0_used : in string; clk1_used : in string;
clk2_used : in string; clk3_used : in string;
clk4_used : in string; clk5_used : in string;
clk6_used : in string; clk7_used : in string;
clk8_used : in string; clk9_used : in string;
m : out integer;
n : out integer ) is
constant MAX_M : integer := 511;
constant MAX_N : integer := 511;
constant MAX_PFD : integer := 720;
constant MIN_PFD : integer := 5;
constant MAX_VCO : integer := 1300;
constant MIN_VCO : integer := 300;
constant MAX_OFFSET : real := 0.004;
variable vco_period : integer;
variable pfd_freq : integer;
variable vco_freq : integer;
variable vco_ps_step_value : integer;
variable i_m : integer;
variable i_n : integer;
variable i_pre_m : integer;
variable i_pre_n : integer;
variable closest_vco_step_value : integer;
variable i_max_iter : integer;
variable loop_iter : integer;
variable clk0_div_factor_real : real;
variable clk1_div_factor_real : real;
variable clk2_div_factor_real : real;
variable clk3_div_factor_real : real;
variable clk4_div_factor_real : real;
variable clk5_div_factor_real : real;
variable clk6_div_factor_real : real;
variable clk7_div_factor_real : real;
variable clk8_div_factor_real : real;
variable clk9_div_factor_real : real;
variable clk0_div_factor_int : integer;
variable clk1_div_factor_int : integer;
variable clk2_div_factor_int : integer;
variable clk3_div_factor_int : integer;
variable clk4_div_factor_int : integer;
variable clk5_div_factor_int : integer;
variable clk6_div_factor_int : integer;
variable clk7_div_factor_int : integer;
variable clk8_div_factor_int : integer;
variable clk9_div_factor_int : integer;
begin
vco_period := vco_phase_shift_step * 8;
i_pre_m := 0;
i_pre_n := 0;
closest_vco_step_value := 0;
LOOP_1 : for i_n_out in 1 to MAX_N loop
for i_m_out in 1 to MAX_M loop
clk0_div_factor_real := real(clk0_div * i_m_out) / real(clk0_mult * i_n_out);
clk1_div_factor_real := real(clk1_div * i_m_out) / real(clk1_mult * i_n_out);
clk2_div_factor_real := real(clk2_div * i_m_out) / real(clk2_mult * i_n_out);
clk3_div_factor_real := real(clk3_div * i_m_out) / real(clk3_mult * i_n_out);
clk4_div_factor_real := real(clk4_div * i_m_out) / real(clk4_mult * i_n_out);
clk5_div_factor_real := real(clk5_div * i_m_out) / real(clk5_mult * i_n_out);
clk6_div_factor_real := real(clk6_div * i_m_out) / real(clk6_mult * i_n_out);
clk7_div_factor_real := real(clk7_div * i_m_out) / real(clk7_mult * i_n_out);
clk8_div_factor_real := real(clk8_div * i_m_out) / real(clk8_mult * i_n_out);
clk9_div_factor_real := real(clk9_div * i_m_out) / real(clk9_mult * i_n_out);
clk0_div_factor_int := integer(clk0_div_factor_real);
clk1_div_factor_int := integer(clk1_div_factor_real);
clk2_div_factor_int := integer(clk2_div_factor_real);
clk3_div_factor_int := integer(clk3_div_factor_real);
clk4_div_factor_int := integer(clk4_div_factor_real);
clk5_div_factor_int := integer(clk5_div_factor_real);
clk6_div_factor_int := integer(clk6_div_factor_real);
clk7_div_factor_int := integer(clk7_div_factor_real);
clk8_div_factor_int := integer(clk8_div_factor_real);
clk9_div_factor_int := integer(clk9_div_factor_real);
if (((abs(clk0_div_factor_real - real(clk0_div_factor_int)) < MAX_OFFSET) or (clk0_used = "unused")) and
((abs(clk1_div_factor_real - real(clk1_div_factor_int)) < MAX_OFFSET) or (clk1_used = "unused")) and
((abs(clk2_div_factor_real - real(clk2_div_factor_int)) < MAX_OFFSET) or (clk2_used = "unused")) and
((abs(clk3_div_factor_real - real(clk3_div_factor_int)) < MAX_OFFSET) or (clk3_used = "unused")) and
((abs(clk4_div_factor_real - real(clk4_div_factor_int)) < MAX_OFFSET) or (clk4_used = "unused")) and
((abs(clk5_div_factor_real - real(clk5_div_factor_int)) < MAX_OFFSET) or (clk5_used = "unused")) and
((abs(clk6_div_factor_real - real(clk6_div_factor_int)) < MAX_OFFSET) or (clk6_used = "unused")) and
((abs(clk7_div_factor_real - real(clk7_div_factor_int)) < MAX_OFFSET) or (clk7_used = "unused")) and
((abs(clk8_div_factor_real - real(clk8_div_factor_int)) < MAX_OFFSET) or (clk8_used = "unused")) and
((abs(clk9_div_factor_real - real(clk9_div_factor_int)) < MAX_OFFSET) or (clk9_used = "unused")) )
then
if ((i_m_out /= 0) and (i_n_out /= 0))
then
pfd_freq := 1000000 / (inclock_period * i_n_out);
vco_freq := (1000000 * i_m_out) / (inclock_period * i_n_out);
vco_ps_step_value := (inclock_period * i_n_out) / (8 * i_m_out);
if ( (i_m_out < max_m) and (i_n_out < max_n) and (pfd_freq >= min_pfd) and (pfd_freq <= max_pfd) and
(vco_freq >= min_vco) and (vco_freq <= max_vco) )
then
if (abs(vco_ps_step_value - vco_phase_shift_step) <= 2)
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
exit LOOP_1;
else
if (abs(vco_ps_step_value - vco_phase_shift_step) < abs(closest_vco_step_value - vco_phase_shift_step))
then
i_pre_m := i_m_out;
i_pre_n := i_n_out;
closest_vco_step_value := vco_ps_step_value;
end if;
end if;
end if;
end if;
end if;
end loop;
end loop;
if ((i_pre_m /= 0) and (i_pre_n /= 0))
then
find_simple_integer_fraction(i_pre_m, i_pre_n,
MAX_N, m, n);
else
n := 1;
m := lcm (clk0_mult, clk1_mult, clk2_mult, clk3_mult,
clk4_mult, clk5_mult, clk6_mult,
clk7_mult, clk8_mult, clk9_mult, inclock_period);
end if;
end find_m_and_n_4_manual_phase;
-- find the greatest common denominator of X and Y
function gcd (X: integer; Y: integer) return integer is
variable L, S, R, G : integer := 1;
begin
if (X < Y) then -- find which is smaller.
S := X;
L := Y;
else
S := Y;
L := X;
end if;
R := S;
while ( R > 1) loop
S := L;
L := R;
R := S rem L; -- divide bigger number by smaller.
-- remainder becomes smaller number.
end loop;
if (R = 0) then -- if evenly divisible then L is gcd else it is 1.
G := L;
else
G := R;
end if;
return G;
end gcd;
-- count the number of digits in the given integer
function count_digit (X: integer)
return integer is
variable count, result: integer := 0;
begin
result := X;
while (result /= 0) loop
result := (result / 10);
count := count + 1;
end loop;
return count;
end count_digit;
-- reduce the given huge number to Y significant digits
function scale_num (X: integer; Y: integer)
return integer is
variable count : integer := 0;
variable lc, fac_ten, result: integer := 1;
begin
count := count_digit(X);
for lc in 1 to (count-Y) loop
fac_ten := fac_ten * 10;
end loop;
result := (X / fac_ten);
return result;
end scale_num;
-- find the least common multiple of A1 to A10
function lcm (A1: integer; A2: integer; A3: integer; A4: integer;
A5: integer; A6: integer; A7: integer;
A8: integer; A9: integer; A10: integer; P: integer)
return integer is
variable M1, M2, M3, M4, M5 , M6, M7, M8, M9, R: integer := 1;
begin
M1 := (A1 * A2)/gcd(A1, A2);
M2 := (M1 * A3)/gcd(M1, A3);
M3 := (M2 * A4)/gcd(M2, A4);
M4 := (M3 * A5)/gcd(M3, A5);
M5 := (M4 * A6)/gcd(M4, A6);
M6 := (M5 * A7)/gcd(M5, A7);
M7 := (M6 * A8)/gcd(M6, A8);
M8 := (M7 * A9)/gcd(M7, A9);
M9 := (M8 * A10)/gcd(M8, A10);
if (M9 < 3) then
R := 10;
elsif (M9 = 3) then
R := 9;
elsif ((M9 <= 10) and (M9 > 3)) then
R := 4 * M9;
elsif (M9 > 1000) then
R := scale_num(M9,3);
else
R := M9 ;
end if;
return R;
end lcm;
-- find the factor of division of the output clock frequency compared to the VCO
function output_counter_value (clk_divide: integer; clk_mult: integer ;
M: integer; N: integer ) return integer is
variable r_real : real := 1.0;
variable r: integer := 1;
begin
r_real := real(clk_divide * M)/ real(clk_mult * N);
r := integer(r_real);
return R;
end output_counter_value;
-- find the mode of each PLL counter - bypass, even or odd
function counter_mode (duty_cycle: integer; output_counter_value: integer)
return string is
variable R: string (1 to 6) := " ";
variable counter_value: integer := 1;
begin
counter_value := (2*duty_cycle*output_counter_value)/100;
if output_counter_value = 1 then
R := "bypass";
elsif (counter_value REM 2) = 0 then
R := " even";
else
R := " odd";
end if;
return R;
end counter_mode;
-- find the number of VCO clock cycles to hold the output clock high
function counter_high (output_counter_value: integer := 1; duty_cycle: integer)
return integer is
variable R: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value *2)/100 ;
if (half_cycle_high REM 2 = 0) then
R := half_cycle_high/2 ;
else
R := (half_cycle_high/2) + 1;
end if;
return R;
end;
-- find the number of VCO clock cycles to hold the output clock low
function counter_low (output_counter_value: integer; duty_cycle: integer)
return integer is
variable R, R1: integer := 1;
variable half_cycle_high : integer := 1;
begin
half_cycle_high := (duty_cycle * output_counter_value*2)/100 ;
if (half_cycle_high REM 2 = 0) then
R1 := half_cycle_high/2 ;
else
R1 := (half_cycle_high/2) + 1;
end if;
R := output_counter_value - R1;
if (R = 0) then
R := 1;
end if;
return R;
end;
-- find the smallest time delay amongst t1 to t10
function mintimedelay (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 > 0) then return m9; else return 0; end if;
end;
-- find the numerically largest negative number, and return its absolute value
function maxnegabs (t1: integer; t2: integer; t3: integer; t4: integer;
t5: integer; t6: integer; t7: integer; t8: integer;
t9: integer; t10: integer) return integer is
variable m1,m2,m3,m4,m5,m6,m7,m8,m9 : integer := 0;
begin
if (t1 < t2) then m1 := t1; else m1 := t2; end if;
if (m1 < t3) then m2 := m1; else m2 := t3; end if;
if (m2 < t4) then m3 := m2; else m3 := t4; end if;
if (m3 < t5) then m4 := m3; else m4 := t5; end if;
if (m4 < t6) then m5 := m4; else m5 := t6; end if;
if (m5 < t7) then m6 := m5; else m6 := t7; end if;
if (m6 < t8) then m7 := m6; else m7 := t8; end if;
if (m7 < t9) then m8 := m7; else m8 := t9; end if;
if (m8 < t10) then m9 := m8; else m9 := t10; end if;
if (m9 < 0) then return (0 - m9); else return 0; end if;
end;
-- adjust the phase (tap_phase) with the largest negative number (ph_base)
function ph_adjust (tap_phase: integer; ph_base : integer) return integer is
begin
return (tap_phase + ph_base);
end;
-- find the time delay for each PLL counter
function counter_time_delay (clk_time_delay: integer;
m_time_delay: integer; n_time_delay: integer)
return integer is
variable R: integer := 0;
begin
R := clk_time_delay + m_time_delay - n_time_delay;
return R;
end;
-- calculate the given phase shift (in ps) in terms of degrees
function get_phase_degree (phase_shift: integer; clk_period: integer)
return integer is
variable result: integer := 0;
begin
result := ( phase_shift * 360 ) / clk_period;
-- to round up the calculation result
if (result > 0) then
result := result + 1;
elsif (result < 0) then
result := result - 1;
else
result := 0;
end if;
return result;
end;
-- find the number of VCO clock cycles to wait initially before the first rising
-- edge of the output clock
function counter_initial (tap_phase: integer; m: integer; n: integer)
return integer is
variable R: integer;
variable R1: real;
begin
R1 := (real(abs(tap_phase)) * real(m))/(360.0 * real(n)) + 0.6;
-- Note NCSim VHDL had problem in rounding up for 0.5 - 0.99.
-- This checking will ensure that the rounding up is done.
if (R1 >= 0.5) and (R1 <= 1.0) then
R1 := 1.0;
end if;
R := integer(R1);
return R;
end;
-- find which VCO phase tap (0 to 7) to align the rising edge of the output clock to
function counter_ph (tap_phase: integer; m: integer; n: integer) return integer is
variable R: integer := 0;
begin
-- 0.5 is added for proper rounding of the tap_phase.
R := integer(real(integer(real(tap_phase * m / n)+ 0.5) REM 360)/45.0) rem 8;
return R;
end;
-- convert given string to length 6 by padding with spaces
function translate_string (mode : string) return string is
variable new_mode : string (1 to 6) := " ";
begin
if (mode = "bypass") then
new_mode := "bypass";
elsif (mode = "even") then
new_mode := " even";
elsif (mode = "odd") then
new_mode := " odd";
end if;
return new_mode;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! "
SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function dqs_str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
variable err : boolean := false;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & " in string parameter! "
SEVERITY ERROR;
err := true;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
-- set error flag
err := true;
end case;
if (err) then
err := false;
else
newdigit := newdigit * 10 + digit;
end if;
end loop;
return (sign*newdigit);
end;
end cycloneiii_pllpack;
--
--
-- DFFE Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_dffe is
generic(
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
port(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC;
CLRN : in STD_LOGIC;
PRN : in STD_LOGIC;
CLK : in STD_LOGIC;
ENA : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_dffe : entity is TRUE;
end cycloneiii_dffe;
-- architecture body --
architecture behave of cycloneiii_dffe is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal D_ipd : STD_ULOGIC := 'U';
signal CLRN_ipd : STD_ULOGIC := 'U';
signal PRN_ipd : STD_ULOGIC := 'U';
signal CLK_ipd : STD_ULOGIC := 'U';
signal ENA_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (D_ipd, D, tipd_D);
VitalWireDelay (CLRN_ipd, CLRN, tipd_CLRN);
VitalWireDelay (PRN_ipd, PRN, tipd_PRN);
VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
VitalWireDelay (ENA_ipd, ENA, tipd_ENA);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (D_ipd, CLRN_ipd, PRN_ipd, CLK_ipd, ENA_ipd)
-- timing check results
VARIABLE Tviol_D_CLK : STD_ULOGIC := '0';
VARIABLE Tviol_ENA_CLK : STD_ULOGIC := '0';
VARIABLE TimingData_D_CLK : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_ENA_CLK : VitalTimingDataType := VitalTimingDataInit;
-- functionality results
VARIABLE Violation : STD_ULOGIC := '0';
VARIABLE PrevData_Q : STD_LOGIC_VECTOR(0 to 7);
VARIABLE D_delayed : STD_ULOGIC := 'U';
VARIABLE CLK_delayed : STD_ULOGIC := 'U';
VARIABLE ENA_delayed : STD_ULOGIC := 'U';
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => '0');
-- output glitch detection variables
VARIABLE Q_VitalGlitchData : VitalGlitchDataType;
CONSTANT dffe_Q_tab : VitalStateTableType := (
( L, L, x, x, x, x, x, x, x, L ),
( L, H, L, H, H, x, x, H, x, H ),
( L, H, L, H, x, L, x, H, x, H ),
( L, H, L, x, H, H, x, H, x, H ),
( L, H, H, x, x, x, H, x, x, S ),
( L, H, x, x, x, x, L, x, x, H ),
( L, H, x, x, x, x, H, L, x, S ),
( L, x, L, L, L, x, H, H, x, L ),
( L, x, L, L, x, L, H, H, x, L ),
( L, x, L, x, L, H, H, H, x, L ),
( L, x, x, x, x, x, x, x, x, S ));
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_D_CLK,
TimingData => TimingData_D_CLK,
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_D_CLK_noedge_posedge,
SetupLow => tsetup_D_CLK_noedge_posedge,
HoldHigh => thold_D_CLK_noedge_posedge,
HoldLow => thold_D_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) OR ( (NOT ENA_ipd) )) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ENA_CLK,
TimingData => TimingData_ENA_CLK,
TestSignal => ENA_ipd,
TestSignalName => "ENA",
RefSignal => CLK_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ENA_CLK_noedge_posedge,
SetupLow => tsetup_ENA_CLK_noedge_posedge,
HoldHigh => thold_ENA_CLK_noedge_posedge,
HoldLow => thold_ENA_CLK_noedge_posedge,
CheckEnabled => TO_X01(( (NOT PRN_ipd) ) OR ( (NOT CLRN_ipd) ) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/DFFE",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
-------------------------
-- Functionality Section
-------------------------
Violation := Tviol_D_CLK or Tviol_ENA_CLK;
VitalStateTable(
StateTable => dffe_Q_tab,
DataIn => (
Violation, CLRN_ipd, CLK_delayed, Results(1), D_delayed, ENA_delayed, PRN_ipd, CLK_ipd),
Result => Results,
NumStates => 1,
PreviousDataIn => PrevData_Q);
D_delayed := D_ipd;
CLK_delayed := CLK_ipd;
ENA_delayed := ENA_ipd;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Results(1),
Paths => ( 0 => (PRN_ipd'last_event, tpd_PRN_Q_negedge, TRUE),
1 => (CLRN_ipd'last_event, tpd_CLRN_Q_negedge, TRUE),
2 => (CLK_ipd'last_event, tpd_CLK_Q_posedge, TRUE)),
GlitchData => Q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--
--
-- cycloneiii_mux21 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux21 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic);
attribute VITAL_LEVEL0 of cycloneiii_mux21 : entity is TRUE;
end cycloneiii_mux21;
architecture AltVITAL of cycloneiii_mux21 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal A_ipd, B_ipd, S_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (A_ipd, A, tipd_A);
VitalWireDelay (B_ipd, B, tipd_B);
VitalWireDelay (S_ipd, S, tipd_S);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (A_ipd, B_ipd, S_ipd)
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if (S_ipd = '1') then
tmp_MO := B_ipd;
else
tmp_MO := A_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (A_ipd'last_event, tpd_A_MO, TRUE),
1 => (B_ipd'last_event, tpd_B_MO, TRUE),
2 => (S_ipd'last_event, tpd_S_MO, TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_mux41 Model
--
--
LIBRARY IEEE;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_mux41 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN0_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN1_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN2_MO : VitalDelayType01 := DefPropDelay01;
tpd_IN3_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_IN0 : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01;
tipd_IN2 : VitalDelayType01 := DefPropDelay01;
tipd_IN3 : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01)
);
port (
IN0 : in std_logic := '0';
IN1 : in std_logic := '0';
IN2 : in std_logic := '0';
IN3 : in std_logic := '0';
S : in std_logic_vector(1 downto 0) := (OTHERS => '0');
MO : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_mux41 : entity is TRUE;
end cycloneiii_mux41;
architecture AltVITAL of cycloneiii_mux41 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
signal IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd : std_logic;
signal S_ipd : std_logic_vector(1 downto 0);
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN0_ipd, IN0, tipd_IN0);
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
VitalWireDelay (IN2_ipd, IN2, tipd_IN2);
VitalWireDelay (IN3_ipd, IN3, tipd_IN3);
VitalWireDelay (S_ipd(0), S(0), tipd_S(0));
VitalWireDelay (S_ipd(1), S(1), tipd_S(1));
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN0_ipd, IN1_ipd, IN2_ipd, IN3_ipd, S_ipd(0), S_ipd(1))
-- output glitch detection variables
VARIABLE MO_GlitchData : VitalGlitchDataType;
variable tmp_MO : std_logic;
begin
-------------------------
-- Functionality Section
-------------------------
if ((S_ipd(1) = '1') AND (S_ipd(0) = '1')) then
tmp_MO := IN3_ipd;
elsif ((S_ipd(1) = '1') AND (S_ipd(0) = '0')) then
tmp_MO := IN2_ipd;
elsif ((S_ipd(1) = '0') AND (S_ipd(0) = '1')) then
tmp_MO := IN1_ipd;
else
tmp_MO := IN0_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => MO,
OutSignalName => "MO",
OutTemp => tmp_MO,
Paths => ( 0 => (IN0_ipd'last_event, tpd_IN0_MO, TRUE),
1 => (IN1_ipd'last_event, tpd_IN1_MO, TRUE),
2 => (IN2_ipd'last_event, tpd_IN2_MO, TRUE),
3 => (IN3_ipd'last_event, tpd_IN3_MO, TRUE),
4 => (S_ipd(0)'last_event, tpd_S_MO(0), TRUE),
5 => (S_ipd(1)'last_event, tpd_S_MO(1), TRUE)),
GlitchData => MO_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
--
--
-- cycloneiii_and1 Model
--
--
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.cycloneiii_atom_pack.all;
-- entity declaration --
entity cycloneiii_and1 is
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01);
port(
Y : out STD_LOGIC;
IN1 : in STD_LOGIC);
attribute VITAL_LEVEL0 of cycloneiii_and1 : entity is TRUE;
end cycloneiii_and1;
-- architecture body --
architecture AltVITAL of cycloneiii_and1 is
attribute VITAL_LEVEL0 of AltVITAL : architecture is TRUE;
SIGNAL IN1_ipd : STD_ULOGIC := 'U';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (IN1_ipd, IN1, tipd_IN1);
end block;
--------------------
-- BEHAVIOR SECTION
--------------------
VITALBehavior : process (IN1_ipd)
-- functionality results
VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X');
ALIAS Y_zd : STD_ULOGIC is Results(1);
-- output glitch detection variables
VARIABLE Y_GlitchData : VitalGlitchDataType;
begin
-------------------------
-- Functionality Section
-------------------------
Y_zd := TO_X01(IN1_ipd);
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => Y,
OutSignalName => "Y",
OutTemp => Y_zd,
Paths => (0 => (IN1_ipd'last_event, tpd_IN1_Y, TRUE)),
GlitchData => Y_GlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end AltVITAL;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_lcell_comb
--
-- Description : Cyclone II LCELL_COMB VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_lcell_comb is
generic (
lut_mask : std_logic_vector(15 downto 0) := (OTHERS => '1');
sum_lutc_input : string := "datac";
dont_touch : string := "off";
lpm_type : string := "cycloneiii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_cin_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '1';
datab : in std_logic := '1';
datac : in std_logic := '1';
datad : in std_logic := '1';
cin : in std_logic := '0';
combout : out std_logic;
cout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_lcell_comb : entity is TRUE;
end cycloneiii_lcell_comb;
architecture vital_lcell_comb of cycloneiii_lcell_comb is
attribute VITAL_LEVEL0 of vital_lcell_comb : architecture is TRUE;
signal dataa_ipd : std_logic;
signal datab_ipd : std_logic;
signal datac_ipd : std_logic;
signal datad_ipd : std_logic;
signal cin_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (dataa_ipd, dataa, tipd_dataa);
VitalWireDelay (datab_ipd, datab, tipd_datab);
VitalWireDelay (datac_ipd, datac, tipd_datac);
VitalWireDelay (datad_ipd, datad, tipd_datad);
VitalWireDelay (cin_ipd, cin, tipd_cin);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, datac_ipd, datad_ipd,
cin_ipd)
variable combout_VitalGlitchData : VitalGlitchDataType;
variable cout_VitalGlitchData : VitalGlitchDataType;
-- output variables
variable combout_tmp : std_logic;
variable cout_tmp : std_logic;
begin
-- lut_mask_var := lut_mask;
------------------------
-- Timing Check Section
------------------------
if (sum_lutc_input = "datac") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
datac_ipd,
datab_ipd,
dataa_ipd));
elsif (sum_lutc_input = "cin") then
-- combout
combout_tmp := VitalMUX(data => lut_mask,
dselect => (datad_ipd,
cin_ipd,
datab_ipd,
dataa_ipd));
end if;
-- cout
cout_tmp := VitalMUX(data => lut_mask,
dselect => ('0',
cin_ipd,
datab_ipd,
dataa_ipd));
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => combout,
OutSignalName => "COMBOUT",
OutTemp => combout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_combout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_combout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_combout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_combout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_combout, TRUE)),
GlitchData => combout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => cout,
OutSignalName => "COUT",
OutTemp => cout_tmp,
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_cout, TRUE),
1 => (datab_ipd'last_event, tpd_datab_cout, TRUE),
2 => (datac_ipd'last_event, tpd_datac_cout, TRUE),
3 => (datad_ipd'last_event, tpd_datad_cout, TRUE),
4 => (cin_ipd'last_event, tpd_cin_cout, TRUE)),
GlitchData => cout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_comb;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_routing_wire
--
-- Description : Cyclone III Routing Wire VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_routing_wire is
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_routing_wire : entity is TRUE;
end cycloneiii_routing_wire;
ARCHITECTURE behave of cycloneiii_routing_wire is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal datain_ipd : std_logic;
signal datainglitch_inert : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (datain_ipd, datain, tipd_datain);
end block;
VITAL: process(datain_ipd, datainglitch_inert)
variable datain_inert_VitalGlitchData : VitalGlitchDataType;
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => datainglitch_inert,
OutSignalName => "datainglitch_inert",
OutTemp => datain_ipd,
Paths => (1 => (datain_ipd'last_event, tpd_datainglitch_dataout, TRUE)),
GlitchData => datain_inert_VitalGlitchData,
Mode => VitalInertial,
XOn => XOn,
MsgOn => MsgOn );
VitalPathDelay01 (
OutSignal => dataout,
OutSignalName => "dataout",
OutTemp => datainglitch_inert,
Paths => (1 => (datain_ipd'last_event, tpd_datain_dataout, TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_mn_cntr
--
-- Description : Timing simulation model for the M and N counter. This is a
-- common model for the input counter and the loop feedback
-- counter of the Cyclone III PLL.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_mn_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END cycloneiii_mn_cntr;
ARCHITECTURE behave of cycloneiii_mn_cntr is
begin
process (clk, reset)
variable count : integer := 1;
variable first_rising_edge : boolean := true;
variable tmp_cout : std_logic;
begin
if (reset = '1') then
count := 1;
tmp_cout := '0';
first_rising_edge := true;
elsif (clk'event) then
if (clk = '1' and first_rising_edge) then
first_rising_edge := false;
tmp_cout := clk;
elsif (not first_rising_edge) then
if (count < modulus) then
count := count + 1;
else
count := 1;
tmp_cout := not tmp_cout;
end if;
end if;
end if;
cout <= transport tmp_cout after time_delay * 1 ps;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_scale_cntr
--
-- Description : Timing simulation model for the output scale-down counters.
-- This is a common model for the C0, C1, C2, C3, C4 and C5
-- output counters of the Cyclone III PLL.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_scale_cntr is
PORT( clk : IN std_logic;
reset : IN std_logic := '0';
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0;
cout : OUT std_logic
);
END cycloneiii_scale_cntr;
ARCHITECTURE behave of cycloneiii_scale_cntr is
begin
process (clk, reset)
variable tmp_cout : std_logic := '0';
variable count : integer := 1;
variable output_shift_count : integer := 1;
variable first_rising_edge : boolean := false;
begin
if (reset = '1') then
count := 1;
output_shift_count := 1;
tmp_cout := '0';
first_rising_edge := false;
elsif (clk'event) then
if (mode = " off") then
tmp_cout := '0';
elsif (mode = "bypass") then
tmp_cout := clk;
first_rising_edge := true;
elsif (not first_rising_edge) then
if (clk = '1') then
if (output_shift_count = initial) then
tmp_cout := clk;
first_rising_edge := true;
else
output_shift_count := output_shift_count + 1;
end if;
end if;
elsif (output_shift_count < initial) then
if (clk = '1') then
output_shift_count := output_shift_count + 1;
end if;
else
count := count + 1;
if (mode = " even" and (count = (high*2) + 1)) then
tmp_cout := '0';
elsif (mode = " odd" and (count = high*2)) then
tmp_cout := '0';
elsif (count = (high + low)*2 + 1) then
tmp_cout := '1';
count := 1; -- reset count
end if;
end if;
end if;
cout <= transport tmp_cout;
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll_reg
--
-- Description : Simulation model for a simple DFF.
-- This is required for the generation of the bit slip-signals.
-- No timing, powers upto 0.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY cycloneiii_pll_reg is
PORT( clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end cycloneiii_pll_reg;
ARCHITECTURE behave of cycloneiii_pll_reg is
begin
process (clk, prn, clrn)
variable q_reg : std_logic := '0';
begin
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk'event and clk = '1' and (ena = '1')) then
q_reg := D;
end if;
Q <= q_reg;
end process;
end behave;
--///////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_pll
--
-- Description : Timing simulation model for the Cyclone III PLL.
-- In the functional mode, it is also the model for the altpll
-- megafunction.
--
-- Limitations : Does not support Spread Spectrum and Bandwidth.
--
-- Outputs : Up to 10 output clocks, each defined by its own set of
-- parameters. Locked output (active high) indicates when the
-- PLL locks. clkbad and activeclock are used for
-- clock switchover to indicate which input clock has gone
-- bad, when the clock switchover initiates and which input
-- clock is being used as the reference, respectively.
-- scandataout is the data output of the serial scan chain.
--
--///////////////////////////////////////////////////////////////////////////
LIBRARY IEEE, std;
USE IEEE.std_logic_1164.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE STD.TEXTIO.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_pllpack.all;
USE work.cycloneiii_mn_cntr;
USE work.cycloneiii_scale_cntr;
USE work.cycloneiii_dffe;
USE work.cycloneiii_pll_reg;
-- New Features : The list below outlines key new features in CYCLONEIII:
-- 1. Dynamic Phase Reconfiguration
-- 2. Dynamic PLL Reconfiguration (different protocol)
-- 3. More output counters
ENTITY cycloneiii_pll is
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- AUTO/FAST/ENHANCED/LEFT_RIGHT/TOP_BOTTOM
compensate_clock : string := "clock0";
inclk0_input_frequency : integer := 0;
inclk1_input_frequency : integer := 0;
self_reset_on_loss_lock : string := "off";
switch_over_type : string := "auto";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "off";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_c : integer := 4;
sim_gate_lock_device_behavior : string := "off";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
lock_window : time := 5 ps;
test_bypass_lock_detect : string := "off";
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
-- ADVANCED USER PARAMETERS
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control : string := "auto";
vco_phase_shift_step : integer := 0;
charge_pump_current : integer := 10;
loop_filter_r : string := " 1.0";
loop_filter_c : integer := 0;
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "cycloneiii_pll";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
-- Test only
init_block_reset_a_count : integer := 1;
init_block_reset_b_count : integer := 1;
charge_pump_current_bits : integer := 0;
lock_window_ui_bits : integer := 0;
loop_filter_c_bits : integer := 0;
loop_filter_r_bits : integer := 0;
test_counter_c0_delay_chain_bits : integer := 0;
test_counter_c1_delay_chain_bits : integer := 0;
test_counter_c2_delay_chain_bits : integer := 0;
test_counter_c3_delay_chain_bits : integer := 0;
test_counter_c4_delay_chain_bits : integer := 0;
test_counter_c5_delay_chain_bits : integer := 0;
test_counter_m_delay_chain_bits : integer := 0;
test_counter_n_delay_chain_bits : integer := 0;
test_feedback_comp_delay_chain_bits : integer := 0;
test_input_comp_delay_chain_bits : integer := 0;
test_volt_reg_output_mode_bits : integer := 0;
test_volt_reg_output_voltage_bits : integer := 0;
test_volt_reg_test_mode : string := "false";
vco_range_detector_high_bits : integer := -1;
vco_range_detector_low_bits : integer := -1;
scan_chain_mif_file : string := "";
auto_settings : string := "true";
-- Simulation only generics
family_name : string := "Cyclone III";
-- VITAL generics
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanclkena : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_configupdate : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tipd_phaseupdown : VitalDelayType01 := DefPropDelay01;
tipd_phasecounterselect : VitalDelayArrayType01(2 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_phasestep : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_scanclkena_scanclk_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
use_vco_bypass : string := "false"
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
fbout : out std_logic;
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
scanclkena : in std_logic := '1';
configupdate : in std_logic := '0';
clk : out std_logic_vector(4 downto 0);
phasecounterselect : in std_logic_vector(2 downto 0) := "000";
phaseupdown : in std_logic := '0';
phasestep : in std_logic := '0';
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
phasedone : out std_logic;
vcooverrange : out std_logic;
vcounderrange : out std_logic
);
END cycloneiii_pll;
ARCHITECTURE vital_pll of cycloneiii_pll is
TYPE int_array is ARRAY(NATURAL RANGE <>) of integer;
TYPE str_array is ARRAY(NATURAL RANGE <>) of string(1 to 6);
TYPE str_array1 is ARRAY(NATURAL RANGE <>) of string(1 to 9);
TYPE std_logic_array is ARRAY(NATURAL RANGE <>) of std_logic;
-- internal advanced parameter signals
signal i_vco_min : integer := vco_min * (vco_post_scale/2);
signal i_vco_max : integer := vco_max * (vco_post_scale/2);
signal i_vco_center : integer;
signal i_pfd_min : integer;
signal i_pfd_max : integer;
signal c_ph_val : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_high_val : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val : int_array(0 to 4) := (OTHERS => 1);
signal c_initial_val : int_array(0 to 4) := (OTHERS => 1);
signal c_mode_val : str_array(0 to 4);
signal clk_num : str_array(0 to 4);
-- old values
signal c_high_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_old : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_old : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_old : str_array(0 to 4);
-- hold registers
signal c_high_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_low_val_hold : int_array(0 to 4) := (OTHERS => 1);
signal c_ph_val_hold : int_array(0 to 4) := (OTHERS => 0);
signal c_mode_val_hold : str_array(0 to 4);
-- temp registers
signal sig_c_ph_val_tmp : int_array(0 to 4) := (OTHERS => 0);
signal c_ph_val_orig : int_array(0 to 4) := (OTHERS => 0);
signal real_lock_high : integer := 0;
signal i_clk4_counter : integer := 4;
signal i_clk3_counter : integer := 3;
signal i_clk2_counter : integer := 2;
signal i_clk1_counter : integer := 1;
signal i_clk0_counter : integer := 0;
signal i_charge_pump_current : integer;
signal i_loop_filter_r : integer;
-- end internal advanced parameter signals
-- CONSTANTS
CONSTANT SCAN_CHAIN : integer := 144;
CONSTANT GPP_SCAN_CHAIN : integer := 234;
CONSTANT FAST_SCAN_CHAIN : integer := 180;
CONSTANT cntrs : str_array(4 downto 0) := (" C4", " C3", " C2", " C1", " C0");
CONSTANT ss_cntrs : str_array(0 to 3) := (" M", " M2", " N", " N2");
CONSTANT loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT fpll_loop_filter_c_arr : int_array(0 to 3) := (0,0,0,0);
CONSTANT charge_pump_curr_arr : int_array(0 to 15) := (0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0);
CONSTANT num_phase_taps : integer := 8;
-- signals
signal vcc : std_logic := '1';
signal fbclk : std_logic;
signal refclk : std_logic;
signal vco_over : std_logic := '0';
signal vco_under : std_logic := '1';
signal pll_locked : boolean := false;
signal c_clk : std_logic_array(0 to 4);
signal vco_out : std_logic_vector(7 downto 0) := (OTHERS => '0');
-- signals to assign values to counter params
signal m_val : integer := 1;
signal n_val : integer := 1;
signal m_ph_val : integer := 0;
signal m_ph_initial : integer := 0;
signal m_ph_val_tmp : integer := 0;
signal m_initial_val : integer := m_initial;
signal m_mode_val : string(1 to 6) := " ";
signal n_mode_val : string(1 to 6) := " ";
signal lfc_val : integer := 0;
signal vco_cur : integer := vco_post_scale;
signal cp_curr_val : integer := 0;
signal lfr_val : string(1 to 2) := " ";
signal cp_curr_old_bit_setting : integer := charge_pump_current_bits;
signal cp_curr_val_bit_setting : std_logic_vector(2 downto 0) := (OTHERS => '0');
signal lfr_old_bit_setting : integer := loop_filter_r_bits;
signal lfr_val_bit_setting : std_logic_vector(4 downto 0) := (OTHERS => '0');
signal lfc_old_bit_setting : integer := loop_filter_c_bits;
signal lfc_val_bit_setting : std_logic_vector(1 downto 0) := (OTHERS => '0');
signal pll_reconfig_display_full_setting : boolean := FALSE; -- display full setting, change to true
-- old values
signal m_val_old : integer := 1;
signal n_val_old : integer := 1;
signal m_mode_val_old : string(1 to 6) := " ";
signal n_mode_val_old : string(1 to 6) := " ";
signal m_ph_val_old : integer := 0;
signal lfc_old : integer := 0;
signal vco_old : integer := 0;
signal cp_curr_old : integer := 0;
signal lfr_old : string(1 to 2) := " ";
signal num_output_cntrs : integer := 5;
signal scanclk_period : time := 1 ps;
signal scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
signal clk_pfd : std_logic_vector(0 to 4);
signal clk0_tmp : std_logic;
signal clk1_tmp : std_logic;
signal clk2_tmp : std_logic;
signal clk3_tmp : std_logic;
signal clk4_tmp : std_logic;
signal update_conf_latches : std_logic := '0';
signal update_conf_latches_reg : std_logic := '0';
signal clkin : std_logic := '0';
signal gate_locked : std_logic := '0';
signal pfd_locked : std_logic := '0';
signal lock : std_logic := '0';
signal about_to_lock : boolean := false;
signal reconfig_err : boolean := false;
signal inclk_c0 : std_logic;
signal inclk_c1 : std_logic;
signal inclk_c2 : std_logic;
signal inclk_c3 : std_logic;
signal inclk_c4 : std_logic;
signal inclk_m : std_logic;
signal devpor : std_logic;
signal devclrn : std_logic;
signal inclk0_ipd : std_logic;
signal inclk1_ipd : std_logic;
signal pfdena_ipd : std_logic;
signal areset_ipd : std_logic;
signal fbin_ipd : std_logic;
signal scanclk_ipd : std_logic;
signal scanclkena_ipd, scanclkena_reg : std_logic;
signal scandata_ipd : std_logic;
signal clkswitch_ipd : std_logic;
signal phasecounterselect_ipd : std_logic_vector(2 downto 0);
signal phaseupdown_ipd : std_logic;
signal phasestep_ipd : std_logic;
signal configupdate_ipd : std_logic;
-- registered signals
signal sig_offset : time := 0 ps;
signal sig_refclk_time : time := 0 ps;
signal sig_fbclk_period : time := 0 ps;
signal sig_vco_period_was_phase_adjusted : boolean := false;
signal sig_phase_adjust_was_scheduled : boolean := false;
signal sig_stop_vco : std_logic := '0';
signal sig_m_times_vco_period : time := 0 ps;
signal sig_new_m_times_vco_period : time := 0 ps;
signal sig_got_refclk_posedge : boolean := false;
signal sig_got_fbclk_posedge : boolean := false;
signal sig_got_second_refclk : boolean := false;
signal m_delay : integer := 0;
signal n_delay : integer := 0;
signal inclk1_tmp : std_logic := '0';
signal reset_low : std_logic := '0';
-- Phase Reconfig
SIGNAL phasecounterselect_reg : std_logic_vector(2 DOWNTO 0);
SIGNAL phaseupdown_reg : std_logic := '0';
SIGNAL phasestep_reg : std_logic := '0';
SIGNAL phasestep_high_count : integer := 0;
SIGNAL update_phase : std_logic := '0';
signal scandataout_tmp : std_logic := '0';
signal scandata_in : std_logic := '0';
signal scandata_out : std_logic := '0';
signal scandone_tmp : std_logic := '1';
signal initiate_reconfig : std_logic := '0';
signal sig_refclk_period : time := (inclk0_input_frequency * 1 ps) * n;
signal schedule_vco : std_logic := '0';
signal areset_ena_sig : std_logic := '0';
signal pll_in_test_mode : boolean := false;
signal pll_has_just_been_reconfigured : boolean := false;
signal inclk_c_from_vco : std_logic_array(0 to 4);
signal inclk_m_from_vco : std_logic;
SIGNAL inclk0_period : time := 0 ps;
SIGNAL last_inclk0_period : time := 0 ps;
SIGNAL last_inclk0_edge : time := 0 ps;
SIGNAL first_inclk0_edge_detect : STD_LOGIC := '0';
SIGNAL inclk1_period : time := 0 ps;
SIGNAL last_inclk1_period : time := 0 ps;
SIGNAL last_inclk1_edge : time := 0 ps;
SIGNAL first_inclk1_edge_detect : STD_LOGIC := '0';
COMPONENT cycloneiii_mn_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial_value : IN integer := 1;
modulus : IN integer := 1;
time_delay : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_scale_cntr
PORT (
clk : IN std_logic;
reset : IN std_logic := '0';
cout : OUT std_logic;
initial : IN integer := 1;
high : IN integer := 1;
low : IN integer := 1;
mode : IN string := "bypass";
ph_tap : IN integer := 0
);
END COMPONENT;
COMPONENT cycloneiii_dffe
GENERIC(
TimingChecksOn: Boolean := true;
InstancePath: STRING := "*";
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
tpd_PRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLRN_Q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_CLK_Q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_ENA_Q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_D_CLK_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
thold_ENA_CLK_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tipd_D : VitalDelayType01 := DefPropDelay01;
tipd_CLRN : VitalDelayType01 := DefPropDelay01;
tipd_PRN : VitalDelayType01 := DefPropDelay01;
tipd_CLK : VitalDelayType01 := DefPropDelay01;
tipd_ENA : VitalDelayType01 := DefPropDelay01);
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
COMPONENT cycloneiii_pll_reg
PORT(
Q : out STD_LOGIC := '0';
D : in STD_LOGIC := '1';
CLRN : in STD_LOGIC := '1';
PRN : in STD_LOGIC := '1';
CLK : in STD_LOGIC := '0';
ENA : in STD_LOGIC := '1');
END COMPONENT;
begin
----------------------
-- INPUT PATH DELAYs
----------------------
WireDelay : block
begin
VitalWireDelay (inclk0_ipd, inclk(0), tipd_inclk(0));
VitalWireDelay (inclk1_ipd, inclk(1), tipd_inclk(1));
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (pfdena_ipd, pfdena, tipd_pfdena);
VitalWireDelay (scanclk_ipd, scanclk, tipd_scanclk);
VitalWireDelay (scanclkena_ipd, scanclkena, tipd_scanclkena);
VitalWireDelay (scandata_ipd, scandata, tipd_scandata);
VitalWireDelay (configupdate_ipd, configupdate, tipd_configupdate);
VitalWireDelay (clkswitch_ipd, clkswitch, tipd_clkswitch);
VitalWireDelay (phaseupdown_ipd, phaseupdown, tipd_phaseupdown);
VitalWireDelay (phasestep_ipd, phasestep, tipd_phasestep);
VitalWireDelay (phasecounterselect_ipd(0), phasecounterselect(0), tipd_phasecounterselect(0));
VitalWireDelay (phasecounterselect_ipd(1), phasecounterselect(1), tipd_phasecounterselect(1));
VitalWireDelay (phasecounterselect_ipd(2), phasecounterselect(2), tipd_phasecounterselect(2));
end block;
inclk_m <= fbclk when m_test_source = 0 else
refclk when m_test_source = 1 else
inclk_m_from_vco;
areset_ena_sig <= areset_ipd or sig_stop_vco;
pll_in_test_mode <= true when (m_test_source /= -1 or c0_test_source /= -1 or
c1_test_source /= -1 or c2_test_source /= -1 or
c3_test_source /= -1 or c4_test_source /= -1)
else false;
real_lock_high <= lock_high WHEN (sim_gate_lock_device_behavior = "on") ELSE 0;
m1 : cycloneiii_mn_cntr
port map ( clk => inclk_m,
reset => areset_ena_sig,
cout => fbclk,
initial_value => m_initial_val,
modulus => m_val,
time_delay => m_delay
);
-- add delta delay to inclk1 to ensure inclk0 and inclk1 are processed
-- in different simulation deltas.
inclk1_tmp <= inclk1_ipd;
-- Calculate the inclk0 period
PROCESS
VARIABLE inclk0_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk0_ipd'EVENT AND inclk0_ipd = '1');
IF (first_inclk0_edge_detect = '0') THEN
first_inclk0_edge_detect <= '1';
ELSE
last_inclk0_period <= inclk0_period;
inclk0_period_tmp := NOW - last_inclk0_edge;
END IF;
last_inclk0_edge <= NOW;
inclk0_period <= inclk0_period_tmp;
END PROCESS;
-- Calculate the inclk1 period
PROCESS
VARIABLE inclk1_period_tmp : time := 0 ps;
BEGIN
WAIT UNTIL (inclk1_ipd'EVENT AND inclk1_ipd = '1');
IF (first_inclk1_edge_detect = '0') THEN
first_inclk1_edge_detect <= '1';
ELSE
last_inclk1_period <= inclk1_period;
inclk1_period_tmp := NOW - last_inclk1_edge;
END IF;
last_inclk1_edge <= NOW;
inclk1_period <= inclk1_period_tmp;
END PROCESS;
process (inclk0_ipd, inclk1_tmp, clkswitch_ipd)
variable input_value : std_logic := '0';
variable current_clock : integer := 0;
variable clk0_count, clk1_count : integer := 0;
variable clk0_is_bad, clk1_is_bad : std_logic := '0';
variable primary_clk_is_bad : boolean := false;
variable current_clk_is_bad : boolean := false;
variable got_curr_clk_falling_edge_after_clkswitch : boolean := false;
variable switch_over_count : integer := 0;
variable active_clock : std_logic := '0';
variable external_switch : boolean := false;
variable diff_percent_period : integer := 0;
variable buf : line;
variable switch_clock : boolean := false;
begin
if (now = 0 ps) then
if (switch_over_type = "manual" and clkswitch_ipd = '1') then
current_clock := 1;
active_clock := '1';
end if;
end if;
if (clkswitch_ipd'event and clkswitch_ipd = '1' and switch_over_type = "auto") then
external_switch := true;
elsif (switch_over_type = "manual") then
if (clkswitch_ipd'event and clkswitch_ipd = '1') then
switch_clock := true;
elsif (clkswitch_ipd'event and clkswitch_ipd = '0') then
switch_clock := false;
end if;
end if;
if (switch_clock = true) then
if (inclk0_ipd'event or inclk1_tmp'event) then
if (current_clock = 0) then
current_clock := 1;
active_clock := '1';
clkin <= transport inclk1_tmp;
elsif (current_clock = 1) then
current_clock := 0;
active_clock := '0';
clkin <= transport inclk0_ipd;
end if;
switch_clock := false;
end if;
end if;
-- save the current inclk event value
if (inclk0_ipd'event) then
input_value := inclk0_ipd;
elsif (inclk1_tmp'event) then
input_value := inclk1_tmp;
end if;
-- check if either input clk is bad
if (inclk0_ipd'event and inclk0_ipd = '1') then
clk0_count := clk0_count + 1;
clk0_is_bad := '0';
clk1_count := 0;
if (clk0_count > 2) then
-- no event on other clk for 2 cycles
clk1_is_bad := '1';
if (current_clock = 1) then
current_clk_is_bad := true;
end if;
end if;
end if;
if (inclk1_tmp'event and inclk1_tmp = '1') then
clk1_count := clk1_count + 1;
clk1_is_bad := '0';
clk0_count := 0;
if (clk1_count > 2) then
-- no event on other clk for 2 cycles
clk0_is_bad := '1';
if (current_clock = 0) then
current_clk_is_bad := true;
end if;
end if;
end if;
-- check if the bad clk is the primary clock
if (clk0_is_bad = '1') then
primary_clk_is_bad := true;
else
primary_clk_is_bad := false;
end if;
-- actual switching
if (inclk0_ipd'event and current_clock = 0) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk0_ipd = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk0_ipd;
end if;
else
clkin <= transport inclk0_ipd;
end if;
elsif (inclk1_tmp'event and current_clock = 1) then
if (external_switch) then
if (not got_curr_clk_falling_edge_after_clkswitch) then
if (inclk1_tmp = '0') then
got_curr_clk_falling_edge_after_clkswitch := true;
end if;
clkin <= transport inclk1_tmp;
end if;
else
clkin <= transport inclk1_tmp;
end if;
else
if (input_value = '1' and enable_switch_over_counter = "on" and primary_clk_is_bad) then
switch_over_count := switch_over_count + 1;
end if;
if ((input_value = '0')) then
if (external_switch and (got_curr_clk_falling_edge_after_clkswitch or current_clk_is_bad)) or (primary_clk_is_bad and clkswitch_ipd /= '1' and (enable_switch_over_counter = "off" or switch_over_count = switch_over_counter)) then
got_curr_clk_falling_edge_after_clkswitch := false;
if(inclk0_period > inclk1_period) then
diff_percent_period := (( inclk0_period - inclk1_period ) * 100) / inclk1_period;
else
diff_percent_period := (( inclk1_period - inclk0_period ) * 100) / inclk0_period;
end if;
if((diff_percent_period > 20)and ( switch_over_type = "auto")) then
WRITE(buf,string'("Warning : The input clock frequencies specified for the specified PLL are too far apart for auto-switch-over feature to work properly. Please make sure that the clock frequencies are 20 percent apart for correct functionality."));
writeline(output, buf);
end if;
if (current_clock = 0) then
current_clock := 1;
else
current_clock := 0;
end if;
active_clock := not active_clock;
switch_over_count := 0;
external_switch := false;
current_clk_is_bad := false;
else
if(switch_over_type = "auto") then
if(current_clock = 0 and clk0_is_bad = '1' and clk1_is_bad = '0' ) then
current_clock := 1;
active_clock := not active_clock;
end if;
if(current_clock = 1 and clk0_is_bad = '0' and clk1_is_bad = '1' ) then
current_clock := 0;
active_clock := not active_clock;
end if;
end if;
end if;
end if;
end if;
-- schedule outputs
clkbad(0) <= clk0_is_bad;
clkbad(1) <= clk1_is_bad;
activeclock <= active_clock;
end process;
n1 : cycloneiii_mn_cntr
port map (
clk => clkin,
reset => areset_ipd,
cout => refclk,
initial_value => n_val,
modulus => n_val);
inclk_c0 <= refclk when c0_test_source = 1 else
fbclk when c0_test_source = 0 else
inclk_c_from_vco(0);
c0 : cycloneiii_scale_cntr
port map (
clk => inclk_c0,
reset => areset_ena_sig,
cout => c_clk(0),
initial => c_initial_val(0),
high => c_high_val(0),
low => c_low_val(0),
mode => c_mode_val(0),
ph_tap => c_ph_val(0));
inclk_c1 <= refclk when c1_test_source = 1 else
fbclk when c1_test_source = 0 else
c_clk(0) when c1_use_casc_in = "on" else
inclk_c_from_vco(1);
c1 : cycloneiii_scale_cntr
port map (
clk => inclk_c1,
reset => areset_ena_sig,
cout => c_clk(1),
initial => c_initial_val(1),
high => c_high_val(1),
low => c_low_val(1),
mode => c_mode_val(1),
ph_tap => c_ph_val(1));
inclk_c2 <= refclk when c2_test_source = 1 else
fbclk when c2_test_source = 0 else
c_clk(1) when c2_use_casc_in = "on" else
inclk_c_from_vco(2);
c2 : cycloneiii_scale_cntr
port map (
clk => inclk_c2,
reset => areset_ena_sig,
cout => c_clk(2),
initial => c_initial_val(2),
high => c_high_val(2),
low => c_low_val(2),
mode => c_mode_val(2),
ph_tap => c_ph_val(2));
inclk_c3 <= refclk when c3_test_source = 1 else
fbclk when c3_test_source = 0 else
c_clk(2) when c3_use_casc_in = "on" else
inclk_c_from_vco(3);
c3 : cycloneiii_scale_cntr
port map (
clk => inclk_c3,
reset => areset_ena_sig,
cout => c_clk(3),
initial => c_initial_val(3),
high => c_high_val(3),
low => c_low_val(3),
mode => c_mode_val(3),
ph_tap => c_ph_val(3));
inclk_c4 <= refclk when c4_test_source = 1 else
fbclk when c4_test_source = 0 else
c_clk(3) when (c4_use_casc_in = "on") else
inclk_c_from_vco(4);
c4 : cycloneiii_scale_cntr
port map (
clk => inclk_c4,
reset => areset_ena_sig,
cout => c_clk(4),
initial => c_initial_val(4),
high => c_high_val(4),
low => c_low_val(4),
mode => c_mode_val(4),
ph_tap => c_ph_val(4));
process(scandone_tmp, lock)
begin
if (scandone_tmp'event and (scandone_tmp = '1')) then
pll_has_just_been_reconfigured <= true;
elsif (lock'event and (lock = '1')) then
pll_has_just_been_reconfigured <= false;
end if;
end process;
process(inclk_c0, inclk_c1, areset_ipd, sig_stop_vco)
variable c0_got_first_rising_edge : boolean := false;
variable c0_count : integer := 2;
variable c0_initial_count : integer := 1;
variable c0_tmp, c1_tmp : std_logic := '0';
variable c1_got_first_rising_edge : boolean := false;
variable c1_count : integer := 2;
variable c1_initial_count : integer := 1;
begin
if (areset_ipd = '1' or sig_stop_vco = '1') then
c0_count := 2;
c1_count := 2;
c0_initial_count := 1;
c1_initial_count := 1;
c0_got_first_rising_edge := false;
c1_got_first_rising_edge := false;
else
if (not c0_got_first_rising_edge) then
if (inclk_c0'event and inclk_c0 = '1') then
if (c0_initial_count = c_initial_val(0)) then
c0_got_first_rising_edge := true;
else
c0_initial_count := c0_initial_count + 1;
end if;
end if;
elsif (inclk_c0'event) then
c0_count := c0_count + 1;
if (c0_count = (c_high_val(0) + c_low_val(0)) * 2) then
c0_count := 1;
end if;
end if;
if (inclk_c0'event and inclk_c0 = '0') then
if (c0_count = 1) then
c0_tmp := '1';
c0_got_first_rising_edge := false;
else
c0_tmp := '0';
end if;
end if;
if (not c1_got_first_rising_edge) then
if (inclk_c1'event and inclk_c1 = '1') then
if (c1_initial_count = c_initial_val(1)) then
c1_got_first_rising_edge := true;
else
c1_initial_count := c1_initial_count + 1;
end if;
end if;
elsif (inclk_c1'event) then
c1_count := c1_count + 1;
if (c1_count = (c_high_val(1) + c_low_val(1)) * 2) then
c1_count := 1;
end if;
end if;
if (inclk_c1'event and inclk_c1 = '0') then
if (c1_count = 1) then
c1_tmp := '1';
c1_got_first_rising_edge := false;
else
c1_tmp := '0';
end if;
end if;
end if;
end process;
locked <= pfd_locked WHEN (test_bypass_lock_detect = "on") ELSE
lock;
process (scandone_tmp)
variable buf : line;
begin
if (scandone_tmp'event and scandone_tmp = '1') then
if (reconfig_err = false) then
ASSERT false REPORT "PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :" severity note;
write (buf, string'(" N modulus = "));
write (buf, n_val);
write (buf, string'(" ( "));
write (buf, n_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M modulus = "));
write (buf, m_val);
write (buf, string'(" ( "));
write (buf, m_val_old);
write (buf, string'(" )"));
writeline (output, buf);
write (buf, string'(" M ph_tap = "));
write (buf, m_ph_val);
write (buf, string'(" ( "));
write (buf, m_ph_val_old);
write (buf, string'(" )"));
writeline (output, buf);
for i in 0 to (num_output_cntrs-1) loop
write (buf, clk_num(i));
write (buf, string'(" : "));
write (buf, cntrs(i));
write (buf, string'(" : high = "));
write (buf, c_high_val(i));
write (buf, string'(" ("));
write (buf, c_high_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , low = "));
write (buf, c_low_val(i));
write (buf, string'(" ("));
write (buf, c_low_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , mode = "));
write (buf, c_mode_val(i));
write (buf, string'(" ("));
write (buf, c_mode_val_old(i));
write (buf, string'(") "));
write (buf, string'(" , phase tap = "));
write (buf, c_ph_val(i));
write (buf, string'(" ("));
write (buf, c_ph_val_old(i));
write (buf, string'(") "));
writeline(output, buf);
end loop;
IF (pll_reconfig_display_full_setting) THEN
write (buf, string'(" Charge Pump Current (uA) = "));
write (buf, cp_curr_val);
write (buf, string'(" ( "));
write (buf, cp_curr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (pF) = "));
write (buf, lfc_val);
write (buf, string'(" ( "));
write (buf, lfc_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (Kohm) = "));
write (buf, lfr_val);
write (buf, string'(" ( "));
write (buf, lfr_old);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
ELSE
write (buf, string'(" Charge Pump Current (bit setting) = "));
write (buf, alt_conv_integer(cp_curr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, cp_curr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Capacitor (bit setting) = "));
write (buf, alt_conv_integer(lfc_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfc_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" Loop Filter Resistor (bit setting) = "));
write (buf, alt_conv_integer(lfr_val_bit_setting));
write (buf, string'(" ( "));
write (buf, lfr_old_bit_setting);
write (buf, string'(" ) "));
writeline (output, buf);
write (buf, string'(" VCO_Post_Scale = "));
write (buf, vco_cur);
write (buf, string'(" ( "));
write (buf, vco_old);
write (buf, string'(" ) "));
writeline (output, buf);
END IF;
cp_curr_old_bit_setting <= alt_conv_integer(cp_curr_val_bit_setting);
lfc_old_bit_setting <= alt_conv_integer(lfc_val_bit_setting);
lfr_old_bit_setting <= alt_conv_integer(lfr_val_bit_setting);
else ASSERT false REPORT "Errors were encountered during PLL reprogramming. Please refer to error/warning messages above." severity warning;
end if;
end if;
end process;
update_conf_latches <= configupdate_ipd;
process (scandone_tmp,areset_ipd,update_conf_latches, c_clk(0), c_clk(1), c_clk(2), c_clk(3), c_clk(4), vco_out, fbclk, scanclk_ipd)
variable init : boolean := true;
variable low, high : std_logic_vector(7 downto 0);
variable low_fast, high_fast : std_logic_vector(3 downto 0);
variable mode : string(1 to 6) := "bypass";
variable is_error : boolean := false;
variable m_tmp, n_tmp : std_logic_vector(8 downto 0);
variable lfr_val_tmp : string(1 to 2) := " ";
variable c_high_val_tmp,c_hval : int_array(0 to 4) := (OTHERS => 1);
variable c_low_val_tmp,c_lval : int_array(0 to 4) := (OTHERS => 1);
variable c_mode_val_tmp : str_array(0 to 4);
variable m_val_tmp : integer := 0;
variable c0_rising_edge_transfer_done : boolean := false;
variable c1_rising_edge_transfer_done : boolean := false;
variable c2_rising_edge_transfer_done : boolean := false;
variable c3_rising_edge_transfer_done : boolean := false;
variable c4_rising_edge_transfer_done : boolean := false;
-- variables for scaling of multiply_by and divide_by values
variable i_clk0_mult_by : integer := 1;
variable i_clk0_div_by : integer := 1;
variable i_clk1_mult_by : integer := 1;
variable i_clk1_div_by : integer := 1;
variable i_clk2_mult_by : integer := 1;
variable i_clk2_div_by : integer := 1;
variable i_clk3_mult_by : integer := 1;
variable i_clk3_div_by : integer := 1;
variable i_clk4_mult_by : integer := 1;
variable i_clk4_div_by : integer := 1;
variable max_d_value : integer := 1;
variable new_multiplier : integer := 1;
-- internal variables for storing the phase shift number.(used in lvds mode only)
variable i_clk0_phase_shift : integer := 1;
variable i_clk1_phase_shift : integer := 1;
variable i_clk2_phase_shift : integer := 1;
-- user to advanced variables
variable max_neg_abs : integer := 0;
variable i_m_initial : integer;
variable i_m : integer := 1;
variable i_n : integer := 1;
variable i_c_high : int_array(0 to 4);
variable i_c_low : int_array(0 to 4);
variable i_c_initial : int_array(0 to 4);
variable i_c_ph : int_array(0 to 4);
variable i_c_mode : str_array(0 to 4);
variable i_m_ph : integer;
variable output_count : integer;
variable new_divisor : integer;
variable clk0_cntr : string(1 to 6) := " c0";
variable clk1_cntr : string(1 to 6) := " c1";
variable clk2_cntr : string(1 to 6) := " c2";
variable clk3_cntr : string(1 to 6) := " c3";
variable clk4_cntr : string(1 to 6) := " c4";
variable fbk_cntr : string(1 to 2);
variable fbk_cntr_index : integer;
variable start_bit : integer;
variable quiet_time : time := 0 ps;
variable slowest_clk_old : time := 0 ps;
variable slowest_clk_new : time := 0 ps;
variable i : integer := 0;
variable j : integer := 0;
variable scanread_active_edge : time := 0 ps;
variable got_first_scanclk : boolean := false;
variable scanclk_last_rising_edge : time := 0 ps;
variable current_scan_data : std_logic_vector(0 to 143) := (OTHERS => '0');
variable index : integer := 0;
variable Tviol_scandata_scanclk : std_ulogic := '0';
variable TimingData_scandata_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_scanclkena_scanclk : std_ulogic := '0';
variable TimingData_scanclkena_scanclk : VitalTimingDataType := VitalTimingDataInit;
variable scan_chain_length : integer := GPP_SCAN_CHAIN;
variable tmp_rem : integer := 0;
variable scanclk_cycles : integer := 0;
variable lfc_tmp : std_logic_vector(1 downto 0);
variable lfr_tmp : std_logic_vector(5 downto 0);
variable lfr_int : integer := 0;
variable n_hi,n_lo,m_hi,m_lo : std_logic_vector(7 downto 0);
variable buf : line;
variable buf_scan_data : STD_LOGIC_VECTOR(0 TO 1) := (OTHERS => '0');
variable buf_scan_data_2 : STD_LOGIC_VECTOR(0 TO 2) := (OTHERS => '0');
function slowest_clk (
C0 : integer; C0_mode : string(1 to 6);
C1 : integer; C1_mode : string(1 to 6);
C2 : integer; C2_mode : string(1 to 6);
C3 : integer; C3_mode : string(1 to 6);
C4 : integer; C4_mode : string(1 to 6);
C5 : integer; C5_mode : string(1 to 6);
C6 : integer; C6_mode : string(1 to 6);
C7 : integer; C7_mode : string(1 to 6);
C8 : integer; C8_mode : string(1 to 6);
C9 : integer; C9_mode : string(1 to 6);
refclk : time; m_mod : integer) return time is
variable max_modulus : integer := 1;
variable q_period : time := 0 ps;
variable refclk_int : integer := 0;
begin
if (C0_mode /= "bypass" and C0_mode /= " off") then
max_modulus := C0;
end if;
if (C1 > max_modulus and C1_mode /= "bypass" and C1_mode /= " off") then
max_modulus := C1;
end if;
if (C2 > max_modulus and C2_mode /= "bypass" and C2_mode /= " off") then
max_modulus := C2;
end if;
if (C3 > max_modulus and C3_mode /= "bypass" and C3_mode /= " off") then
max_modulus := C3;
end if;
if (C4 > max_modulus and C4_mode /= "bypass" and C4_mode /= " off") then
max_modulus := C4;
end if;
if (C5 > max_modulus and C5_mode /= "bypass" and C5_mode /= " off") then
max_modulus := C5;
end if;
if (C6 > max_modulus and C6_mode /= "bypass" and C6_mode /= " off") then
max_modulus := C6;
end if;
if (C7 > max_modulus and C7_mode /= "bypass" and C7_mode /= " off") then
max_modulus := C7;
end if;
if (C8 > max_modulus and C8_mode /= "bypass" and C8_mode /= " off") then
max_modulus := C8;
end if;
if (C9 > max_modulus and C9_mode /= "bypass" and C9_mode /= " off") then
max_modulus := C9;
end if;
refclk_int := refclk / 1 ps;
if (m_mod /= 0) then
q_period := (refclk_int * max_modulus / m_mod) * 1 ps;
end if;
return (2*q_period);
end slowest_clk;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function extract_cntr_string (arg:string) return string is
variable str : string(1 to 6) := " c0";
begin
if (arg = "c0") then
str := " c0";
elsif (arg = "c1") then
str := " c1";
elsif (arg = "c2") then
str := " c2";
elsif (arg = "c3") then
str := " c3";
elsif (arg = "c4") then
str := " c4";
elsif (arg = "c5") then
str := " c5";
elsif (arg = "c6") then
str := " c6";
elsif (arg = "c7") then
str := " c7";
elsif (arg = "c8") then
str := " c8";
elsif (arg = "c9") then
str := " c9";
else str := " c0";
end if;
return str;
end extract_cntr_string;
function extract_cntr_index (arg:string) return integer is
variable index : integer := 0;
begin
if (arg(6) = '0') then
index := 0;
elsif (arg(6) = '1') then
index := 1;
elsif (arg(6) = '2') then
index := 2;
elsif (arg(6) = '3') then
index := 3;
elsif (arg(6) = '4') then
index := 4;
elsif (arg(6) = '5') then
index := 5;
elsif (arg(6) = '6') then
index := 6;
elsif (arg(6) = '7') then
index := 7;
elsif (arg(6) = '8') then
index := 8;
else index := 9;
end if;
return index;
end extract_cntr_index;
function output_cntr_num (arg:string) return string is
variable str : string(1 to 6) := "unused";
begin
if (arg = "c0") then
str := " clk0";
elsif (arg = "c1") then
str := " clk1";
elsif (arg = "c2") then
str := " clk2";
elsif (arg = "c3") then
str := " clk3";
elsif (arg = "c4") then
str := " clk4";
elsif (arg = "c5") then
str := " clk5";
elsif (arg = "c6") then
str := " clk6";
elsif (arg = "c7") then
str := " clk7";
elsif (arg = "c8") then
str := " clk8";
elsif (arg = "c9") then
str := " clk9";
else str := "unused";
end if;
return str;
end output_cntr_num;
begin
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val <= i_c_ph;
END IF;
if (init) then
if (m = 0) then
clk4_cntr := " c4";
clk3_cntr := " c3";
clk2_cntr := " c2";
clk1_cntr := " c1";
clk0_cntr := " c0";
else
clk4_cntr := extract_cntr_string(clk4_counter);
clk3_cntr := extract_cntr_string(clk3_counter);
clk2_cntr := extract_cntr_string(clk2_counter);
clk1_cntr := extract_cntr_string(clk1_counter);
clk0_cntr := extract_cntr_string(clk0_counter);
end if;
clk_num(4) <= output_cntr_num(clk4_counter);
clk_num(3) <= output_cntr_num(clk3_counter);
clk_num(2) <= output_cntr_num(clk2_counter);
clk_num(1) <= output_cntr_num(clk1_counter);
clk_num(0) <= output_cntr_num(clk0_counter);
i_clk0_counter <= extract_cntr_index(clk0_cntr);
i_clk1_counter <= extract_cntr_index(clk1_cntr);
i_clk2_counter <= extract_cntr_index(clk2_cntr);
i_clk3_counter <= extract_cntr_index(clk3_cntr);
i_clk4_counter <= extract_cntr_index(clk4_cntr);
if (m = 0) then -- convert user parameters to advanced
-- set the limit of the divide_by value that can be returned by
-- the following function.
max_d_value := 500;
-- scale down the multiply_by and divide_by values provided by the design
-- before attempting to use them in the calculations below
find_simple_integer_fraction(clk0_multiply_by, clk0_divide_by,
max_d_value, i_clk0_mult_by, i_clk0_div_by);
find_simple_integer_fraction(clk1_multiply_by, clk1_divide_by,
max_d_value, i_clk1_mult_by, i_clk1_div_by);
find_simple_integer_fraction(clk2_multiply_by, clk2_divide_by,
max_d_value, i_clk2_mult_by, i_clk2_div_by);
find_simple_integer_fraction(clk3_multiply_by, clk3_divide_by,
max_d_value, i_clk3_mult_by, i_clk3_div_by);
find_simple_integer_fraction(clk4_multiply_by, clk4_divide_by,
max_d_value, i_clk4_mult_by, i_clk4_div_by);
if (vco_frequency_control = "manual_phase") then
find_m_and_n_4_manual_phase(inclk0_input_frequency, vco_phase_shift_step,
i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
i_clk0_div_by, i_clk1_div_by,
i_clk2_div_by, i_clk3_div_by,
i_clk4_div_by,
1,1,1,1,1,
clk0_counter, clk1_counter,
clk2_counter, clk3_counter,
clk4_counter,
"unused","unused","unused","unused","unused",
i_m, i_n);
elsif (((pll_type = "fast") or (pll_type = "lvds") OR (pll_type = "left_right")) and ((vco_multiply_by /= 0) and (vco_divide_by /= 0))) then
i_n := vco_divide_by;
i_m := vco_multiply_by;
else
i_n := 1;
if (((pll_type = "fast") or (pll_type = "left_right")) and (compensate_clock = "lvdsclk")) then
i_m := i_clk0_mult_by;
else
i_m := lcm (i_clk0_mult_by, i_clk1_mult_by,
i_clk2_mult_by, i_clk3_mult_by,
i_clk4_mult_by,
1,1,1,1,1,
inclk0_input_frequency);
end if;
end if;
if (pll_type = "flvds") then
-- Need to readjust phase shift values when the clock multiply value has been readjusted.
new_multiplier := clk0_multiply_by / i_clk0_mult_by;
i_clk0_phase_shift := str2int(clk0_phase_shift) * new_multiplier;
i_clk1_phase_shift := str2int(clk1_phase_shift) * new_multiplier;
i_clk2_phase_shift := str2int(clk2_phase_shift) * new_multiplier;
else
i_clk0_phase_shift := str2int(clk0_phase_shift);
i_clk1_phase_shift := str2int(clk1_phase_shift);
i_clk2_phase_shift := str2int(clk2_phase_shift);
end if;
max_neg_abs := maxnegabs(i_clk0_phase_shift,
i_clk1_phase_shift,
i_clk2_phase_shift,
str2int(clk3_phase_shift),
str2int(clk4_phase_shift),
0,
0,
0,
0,
0
);
i_m_ph := counter_ph(get_phase_degree(max_neg_abs,inclk0_input_frequency), i_m, i_n);
i_c_ph(0) := counter_ph(get_phase_degree(ph_adjust(i_clk0_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(1) := counter_ph(get_phase_degree(ph_adjust(i_clk1_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(2) := counter_ph(get_phase_degree(ph_adjust(i_clk2_phase_shift,max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(3) := counter_ph(get_phase_degree(ph_adjust(str2int(clk3_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_ph(4) := counter_ph(get_phase_degree(ph_adjust(str2int(clk4_phase_shift),max_neg_abs),inclk0_input_frequency), i_m, i_n);
i_c_high(0) := counter_high(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_high(1) := counter_high(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_high(2) := counter_high(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_high(3) := counter_high(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_high(4) := counter_high(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_c_low(0) := counter_low(output_counter_value(i_clk0_div_by,
i_clk0_mult_by, i_m, i_n), clk0_duty_cycle);
i_c_low(1) := counter_low(output_counter_value(i_clk1_div_by,
i_clk1_mult_by, i_m, i_n), clk1_duty_cycle);
i_c_low(2) := counter_low(output_counter_value(i_clk2_div_by,
i_clk2_mult_by, i_m, i_n), clk2_duty_cycle);
i_c_low(3) := counter_low(output_counter_value(i_clk3_div_by,
i_clk3_mult_by, i_m, i_n), clk3_duty_cycle);
i_c_low(4) := counter_low(output_counter_value(i_clk4_div_by,
i_clk4_mult_by, i_m, i_n), clk4_duty_cycle);
i_m_initial := counter_initial(get_phase_degree(max_neg_abs, inclk0_input_frequency), i_m,i_n);
i_c_initial(0) := counter_initial(get_phase_degree(ph_adjust(i_clk0_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(1) := counter_initial(get_phase_degree(ph_adjust(i_clk1_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(2) := counter_initial(get_phase_degree(ph_adjust(i_clk2_phase_shift, max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(3) := counter_initial(get_phase_degree(ph_adjust(str2int(clk3_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_initial(4) := counter_initial(get_phase_degree(ph_adjust(str2int(clk4_phase_shift), max_neg_abs), inclk0_input_frequency), i_m, i_n);
i_c_mode(0) := counter_mode(clk0_duty_cycle, output_counter_value(i_clk0_div_by, i_clk0_mult_by, i_m, i_n));
i_c_mode(1) := counter_mode(clk1_duty_cycle, output_counter_value(i_clk1_div_by, i_clk1_mult_by, i_m, i_n));
i_c_mode(2) := counter_mode(clk2_duty_cycle, output_counter_value(i_clk2_div_by, i_clk2_mult_by, i_m, i_n));
i_c_mode(3) := counter_mode(clk3_duty_cycle, output_counter_value(i_clk3_div_by, i_clk3_mult_by, i_m, i_n));
i_c_mode(4) := counter_mode(clk4_duty_cycle, output_counter_value(i_clk4_div_by, i_clk4_mult_by, i_m, i_n));
else -- m /= 0
i_n := n;
i_m := m;
i_m_initial := m_initial;
i_m_ph := m_ph;
i_c_ph(0) := c0_ph;
i_c_ph(1) := c1_ph;
i_c_ph(2) := c2_ph;
i_c_ph(3) := c3_ph;
i_c_ph(4) := c4_ph;
i_c_high(0) := c0_high;
i_c_high(1) := c1_high;
i_c_high(2) := c2_high;
i_c_high(3) := c3_high;
i_c_high(4) := c4_high;
i_c_low(0) := c0_low;
i_c_low(1) := c1_low;
i_c_low(2) := c2_low;
i_c_low(3) := c3_low;
i_c_low(4) := c4_low;
i_c_initial(0) := c0_initial;
i_c_initial(1) := c1_initial;
i_c_initial(2) := c2_initial;
i_c_initial(3) := c3_initial;
i_c_initial(4) := c4_initial;
i_c_mode(0) := translate_string(c0_mode);
i_c_mode(1) := translate_string(c1_mode);
i_c_mode(2) := translate_string(c2_mode);
i_c_mode(3) := translate_string(c3_mode);
i_c_mode(4) := translate_string(c4_mode);
end if; -- user to advanced conversion.
m_initial_val <= i_m_initial;
n_val <= i_n;
m_val <= i_m;
if (i_m = 1) then
m_mode_val <= "bypass";
else
m_mode_val <= " ";
end if;
if (i_n = 1) then
n_mode_val <= "bypass";
else
n_mode_val <= " ";
end if;
m_ph_val <= i_m_ph;
m_ph_initial <= i_m_ph;
m_val_tmp := i_m;
for i in 0 to 4 loop
if (i_c_mode(i) = "bypass") then
if (pll_type = "fast" or pll_type = "lvds" OR (pll_type = "left_right")) then
i_c_high(i) := 16;
i_c_low(i) := 16;
else
i_c_high(i) := 256;
i_c_low(i) := 256;
end if;
end if;
c_ph_val(i) <= i_c_ph(i);
c_initial_val(i) <= i_c_initial(i);
c_high_val(i) <= i_c_high(i);
c_low_val(i) <= i_c_low(i);
c_mode_val(i) <= i_c_mode(i);
c_high_val_tmp(i) := i_c_high(i);
c_hval(i) := i_c_high(i);
c_low_val_tmp(i) := i_c_low(i);
c_lval(i) := i_c_low(i);
c_mode_val_tmp(i) := i_c_mode(i);
c_ph_val_orig(i) <= i_c_ph(i);
c_high_val_hold(i) <= i_c_high(i);
c_low_val_hold(i) <= i_c_low(i);
c_mode_val_hold(i) <= i_c_mode(i);
end loop;
scan_chain_length := SCAN_CHAIN;
num_output_cntrs <= 5;
init := false;
elsif (scandone_tmp'EVENT AND scandone_tmp = '1') then
c0_rising_edge_transfer_done := false;
c1_rising_edge_transfer_done := false;
c2_rising_edge_transfer_done := false;
c3_rising_edge_transfer_done := false;
c4_rising_edge_transfer_done := false;
update_conf_latches_reg <= '0';
elsif (update_conf_latches'event and update_conf_latches = '1') then
initiate_reconfig <= '1';
elsif (areset_ipd'event AND areset_ipd = '1') then
if (scandone_tmp = '0') then scandone_tmp <= '1' AFTER scanclk_period; end if;
elsif (scanclk_ipd'event and scanclk_ipd = '1') then
IF (initiate_reconfig = '1') THEN
initiate_reconfig <= '0';
ASSERT false REPORT "PLL Reprogramming Initiated" severity note;
update_conf_latches_reg <= update_conf_latches;
reconfig_err <= false;
scandone_tmp <= '0';
cp_curr_old <= cp_curr_val;
lfc_old <= lfc_val;
lfr_old <= lfr_val;
vco_old <= vco_cur;
-- LF unused : bit 0,1
-- LF Capacitance : bits 2,3 : all values are legal
buf_scan_data := scan_data(2 TO 3);
IF ((pll_type = "fast") OR (pll_type = "lvds") OR (pll_type = "left_right")) THEN
lfc_val <= fpll_loop_filter_c_arr(alt_conv_integer(buf_scan_data));
ELSE
lfc_val <= loop_filter_c_arr(alt_conv_integer(buf_scan_data));
END IF;
-- LF Resistance : bits 4-8
-- valid values - 00000,00100,10000,10100,11000,11011,11100,11110
IF (scan_data(4 TO 8) = "00000") THEN
lfr_val <= "20";
ELSIF (scan_data(4 TO 8) = "00100") THEN
lfr_val <= "16";
ELSIF (scan_data(4 TO 8) = "10000") THEN
lfr_val <= "12";
ELSIF (scan_data(4 TO 8) = "10100") THEN
lfr_val <= "08";
ELSIF (scan_data(4 TO 8) = "11000") THEN
lfr_val <= "06";
ELSIF (scan_data(4 TO 8) = "11011") THEN
lfr_val <= "04";
ELSIF (scan_data(4 TO 8) = "11100") THEN
lfr_val <= "02";
ELSE
lfr_val <= "01";
END IF;
-- VCO post scale assignment
if (scan_data(9) = '1') then -- vco_post_scale = 1
i_vco_max <= vco_max/2;
i_vco_min <= vco_min/2;
vco_cur <= 1;
else
i_vco_max <= vco_max;
i_vco_min <= vco_min;
vco_cur <= 2;
end if;
-- CP
-- Bit 9 : CRBYPASS
-- Bit 10-14 : unused
-- Bits 15-17 : all values are legal
buf_scan_data_2 := scan_data(15 TO 17);
cp_curr_val <= charge_pump_curr_arr(alt_conv_integer(buf_scan_data_2));
-- save old values for display info.
cp_curr_val_bit_setting <= scan_data(15 TO 17);
lfc_val_bit_setting <= scan_data(2 TO 3);
lfr_val_bit_setting <= scan_data(4 TO 8);
m_val_old <= m_val;
n_val_old <= n_val;
m_mode_val_old <= m_mode_val;
n_mode_val_old <= n_mode_val;
WHILE (i < num_output_cntrs) LOOP
c_high_val_old(i) <= c_high_val(i);
c_low_val_old(i) <= c_low_val(i);
c_mode_val_old(i) <= c_mode_val(i);
i := i + 1;
END LOOP;
-- M counter
-- 1. Mode - bypass (bit 18)
IF (scan_data(18) = '1') THEN
n_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 27)
ELSIF (scan_data(27) = '1') THEN
n_mode_val <= " odd";
ELSE
n_mode_val <= " even";
END IF;
-- 2. High (bit 19-26)
n_hi := scan_data(19 TO 26);
-- 4. Low (bit 28-35)
n_lo := scan_data(28 TO 35);
-- N counter
-- 1. Mode - bypass (bit 36)
IF (scan_data(36) = '1') THEN
m_mode_val <= "bypass";
-- 3. Mode - odd/even (bit 45)
ELSIF (scan_data(45) = '1') THEN
m_mode_val <= " odd";
ELSE
m_mode_val <= " even";
END IF;
-- 2. High (bit 37-44)
m_hi := scan_data(37 TO 44);
-- 4. Low (bit 46-53)
m_lo := scan_data(46 TO 53);
-- C counters (start bit 54) bit 1:mode(bypass),bit 2-9:high,bit 10:mode(odd/even),bit 11-18:low
i := 0;
WHILE (i < num_output_cntrs) LOOP
-- 1. Mode - bypass
IF (scan_data(54 + i * 18 + 0) = '1') THEN
c_mode_val_tmp(i) := "bypass";
-- 3. Mode - odd/even
ELSIF (scan_data(54 + i * 18 + 9) = '1') THEN
c_mode_val_tmp(i) := " odd";
ELSE
c_mode_val_tmp(i) := " even";
END IF;
-- 2. Hi
high := scan_data(54 + i * 18 + 1 TO 54 + i * 18 + 8);
c_hval(i) := alt_conv_integer(high);
IF (c_hval(i) /= 0) THEN
c_high_val_tmp(i) := c_hval(i);
ELSE
c_high_val_tmp(i) := alt_conv_integer("000000001");
END IF;
-- 4. Low
low := scan_data(54 + i * 18 + 10 TO 54 + i * 18 + 17);
c_lval(i) := alt_conv_integer(low);
IF (c_lval(i) /= 0) THEN
c_low_val_tmp(i) := c_lval(i);
ELSE
c_low_val_tmp(i) := alt_conv_integer("000000001");
END IF;
i := i + 1;
END LOOP;
-- Legality Checks
-- M counter value
IF(scan_data(36) /= '1') THEN
IF ((m_hi /= m_lo) and (scan_data(45) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The M counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (m_hi /= "00000000") THEN
m_val_tmp := alt_conv_integer(m_hi) + alt_conv_integer(m_lo);
ELSE
m_val_tmp := alt_conv_integer("000000001");
END IF;
ELSE
m_val_tmp := alt_conv_integer("10000000");
END IF;
-- N counter value
IF(scan_data(18) /= '1') THEN
IF ((n_hi /= n_lo)and (scan_data(27) /= '1')) THEN
reconfig_err <= TRUE;
WRITE(buf,string'("Warning : The N counter of the " & family_name & " Fast PLL should be configured for 50%% duty cycle only. In this case the HIGH and LOW moduli programmed will result in a duty cycle other than 50%%, which is illegal. Reconfiguration may not work"));
writeline(output, buf);
ELSIF (n_hi /= "00000000") THEN
n_val <= alt_conv_integer(n_hi) + alt_conv_integer(n_lo);
ELSE
n_val <= alt_conv_integer("000000001");
END IF;
ELSE
n_val <= alt_conv_integer("10000000");
END IF;
-- TODO : Give warnings/errors in the following cases?
-- 1. Illegal counter values (error)
-- 2. Change of mode (warning)
-- 3. Only 50% duty cycle allowed for M counter (odd mode - hi-lo=1,even - hi-lo=0)
END IF;
end if;
if (fbclk'event and fbclk = '1') then
m_val <= m_val_tmp;
end if;
if (update_conf_latches_reg = '1') then
if (scanclk_ipd'event and scanclk_ipd = '1') then
c0_rising_edge_transfer_done := true;
c_high_val(0) <= c_high_val_tmp(0);
c_mode_val(0) <= c_mode_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c1_rising_edge_transfer_done := true;
c_high_val(1) <= c_high_val_tmp(1);
c_mode_val(1) <= c_mode_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c2_rising_edge_transfer_done := true;
c_high_val(2) <= c_high_val_tmp(2);
c_mode_val(2) <= c_mode_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(3) <= c_high_val_tmp(3);
c_mode_val(3) <= c_mode_val_tmp(3);
c3_rising_edge_transfer_done := true;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1') then
c_high_val(4) <= c_high_val_tmp(4);
c_mode_val(4) <= c_mode_val_tmp(4);
c4_rising_edge_transfer_done := true;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c0_rising_edge_transfer_done) then
c_low_val(0) <= c_low_val_tmp(0);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c1_rising_edge_transfer_done) then
c_low_val(1) <= c_low_val_tmp(1);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c2_rising_edge_transfer_done) then
c_low_val(2) <= c_low_val_tmp(2);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c3_rising_edge_transfer_done) then
c_low_val(3) <= c_low_val_tmp(3);
end if;
if (scanclk_ipd'event and scanclk_ipd = '0' and c4_rising_edge_transfer_done) then
c_low_val(4) <= c_low_val_tmp(4);
end if;
if (update_phase = '1') then
if (vco_out(0)'event and vco_out(0) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 0) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(1)'event and vco_out(1) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 1) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(2)'event and vco_out(2) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 2) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(3)'event and vco_out(3) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 3) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(4)'event and vco_out(4) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 4) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(5)'event and vco_out(5) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 5) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(6)'event and vco_out(6) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 6) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
if (vco_out(7)'event and vco_out(7) = '0') then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
c_ph_val(i) <= c_ph_val_tmp(i);
end if;
end loop;
if (m_ph_val = 7) then
m_ph_val <= m_ph_val_tmp;
end if;
end if;
end if;
if (vco_out(0)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 0) then
inclk_c_from_vco(i) <= vco_out(0);
end if;
end loop;
if (m_ph_val = 0) then
inclk_m_from_vco <= vco_out(0);
end if;
end if;
if (vco_out(1)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 1) then
inclk_c_from_vco(i) <= vco_out(1);
end if;
end loop;
if (m_ph_val = 1) then
inclk_m_from_vco <= vco_out(1);
end if;
end if;
if (vco_out(2)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 2) then
inclk_c_from_vco(i) <= vco_out(2);
end if;
end loop;
if (m_ph_val = 2) then
inclk_m_from_vco <= vco_out(2);
end if;
end if;
if (vco_out(3)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 3) then
inclk_c_from_vco(i) <= vco_out(3);
end if;
end loop;
if (m_ph_val = 3) then
inclk_m_from_vco <= vco_out(3);
end if;
end if;
if (vco_out(4)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 4) then
inclk_c_from_vco(i) <= vco_out(4);
end if;
end loop;
if (m_ph_val = 4) then
inclk_m_from_vco <= vco_out(4);
end if;
end if;
if (vco_out(5)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 5) then
inclk_c_from_vco(i) <= vco_out(5);
end if;
end loop;
if (m_ph_val = 5) then
inclk_m_from_vco <= vco_out(5);
end if;
end if;
if (vco_out(6)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 6) then
inclk_c_from_vco(i) <= vco_out(6);
end if;
end loop;
if (m_ph_val = 6) then
inclk_m_from_vco <= vco_out(6);
end if;
end if;
if (vco_out(7)'event) then
for i in 0 to 4 loop
if (c_ph_val(i) = 7) then
inclk_c_from_vco(i) <= vco_out(7);
end if;
end loop;
if (m_ph_val = 7) then
inclk_m_from_vco <= vco_out(7);
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_scandata_scanclk,
TimingData => TimingData_scandata_scanclk,
TestSignal => scandata_ipd,
TestSignalName => "scandata",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scandata_scanclk_noedge_negedge,
SetupLow => tsetup_scandata_scanclk_noedge_negedge,
HoldHigh => thold_scandata_scanclk_noedge_negedge,
HoldLow => thold_scandata_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_scanclkena_scanclk,
TimingData => TimingData_scanclkena_scanclk,
TestSignal => scanclkena_ipd,
TestSignalName => "scanclkena",
RefSignal => scanclk_ipd,
RefSignalName => "scanclk",
SetupHigh => tsetup_scanclkena_scanclk_noedge_negedge,
SetupLow => tsetup_scanclkena_scanclk_noedge_negedge,
HoldHigh => thold_scanclkena_scanclk_noedge_negedge,
HoldLow => thold_scanclkena_scanclk_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '\',
HeaderMsg => InstancePath & "/cycloneiii_pll",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (scanclk_ipd'event AND scanclk_ipd = '0' AND now > 0 ps) then
scanclkena_reg <= scanclkena_ipd;
if (scanclkena_reg = '1') then
scandata_in <= scandata_ipd;
scandata_out <= scandataout_tmp;
end if;
end if;
if (scanclk_ipd'event and scanclk_ipd = '1' and now > 0 ps) then
if (got_first_scanclk) then
scanclk_period <= now - scanclk_last_rising_edge;
else
got_first_scanclk := true;
end if;
if (scanclkena_reg = '1') then
for j in scan_chain_length - 1 downto 1 loop
scan_data(j) <= scan_data(j-1);
end loop;
scan_data(0) <= scandata_in;
end if;
scanclk_last_rising_edge := now;
end if;
end process;
-- PLL Phase Reconfiguration
PROCESS(scanclk_ipd, areset_ipd,phasestep_ipd)
VARIABLE i : INTEGER := 0;
VARIABLE c_ph : INTEGER := 0;
VARIABLE m_ph : INTEGER := 0;
VARIABLE select_counter : INTEGER := 0;
BEGIN
IF (NOW = 0 ps) THEN
m_ph_val_tmp <= m_ph_initial;
END IF;
-- Latch phase enable (same as phasestep) on neg edge of scan clock
IF (scanclk_ipd'EVENT AND scanclk_ipd = '0') THEN
phasestep_reg <= phasestep_ipd;
END IF;
IF (phasestep_ipd'EVENT and phasestep_ipd = '1') THEN
IF (update_phase = '0') THEN
phasestep_high_count <= 0; -- phase adjustments must be 1 cycle apart
-- if not, next phasestep cycle is skipped
END IF;
END IF;
-- revert counter phase tap values to POF programmed values
-- if PLL is reset
IF (areset_ipd'EVENT AND areset_ipd = '1') then
c_ph_val_tmp <= c_ph_val_orig;
m_ph_val_tmp <= m_ph_initial;
END IF;
IF (scanclk_ipd'EVENT AND scanclk_ipd = '1') THEN
IF (phasestep_reg = '1') THEN
IF (phasestep_high_count = 1) THEN
phasecounterselect_reg <= phasecounterselect_ipd;
phaseupdown_reg <= phaseupdown_ipd;
-- start reconfiguration
IF (phasecounterselect_ipd < "111") THEN -- no counters selected
IF (phasecounterselect_ipd = "000") THEN
i := 0;
WHILE (i < num_output_cntrs) LOOP
c_ph := c_ph_val(i);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(i) <= c_ph;
i := i + 1;
END LOOP;
ELSIF (phasecounterselect_ipd = "001") THEN
m_ph := m_ph_val;
IF (phaseupdown_ipd = '1') THEN
m_ph := (m_ph + 1) mod num_phase_taps;
ELSIF (m_ph = 0) THEN
m_ph := num_phase_taps - 1;
ELSE
m_ph := (m_ph - 1) mod num_phase_taps;
END IF;
m_ph_val_tmp <= m_ph;
ELSE
select_counter := alt_conv_integer(phasecounterselect_ipd) - 2;
c_ph := c_ph_val(select_counter);
IF (phaseupdown_ipd = '1') THEN
c_ph := (c_ph + 1) mod num_phase_taps;
ELSIF (c_ph = 0) THEN
c_ph := num_phase_taps - 1;
ELSE
c_ph := (c_ph - 1) mod num_phase_taps;
END IF;
c_ph_val_tmp(select_counter) <= c_ph;
END IF;
update_phase <= '1','0' AFTER (0.5 * scanclk_period);
END IF;
END IF;
phasestep_high_count <= phasestep_high_count + 1;
END IF;
END IF;
END PROCESS;
scandataout_tmp <= scan_data(SCAN_CHAIN - 2);
process (schedule_vco, areset_ipd, pfdena_ipd, refclk, fbclk)
variable sched_time : time := 0 ps;
TYPE time_array is ARRAY (0 to 7) of time;
variable init : boolean := true;
variable refclk_period : time;
variable m_times_vco_period : time;
variable new_m_times_vco_period : time;
variable phase_shift : time_array := (OTHERS => 0 ps);
variable last_phase_shift : time_array := (OTHERS => 0 ps);
variable l_index : integer := 1;
variable cycle_to_adjust : integer := 0;
variable stop_vco : boolean := false;
variable locked_tmp : std_logic := '0';
variable pll_is_locked : boolean := false;
variable cycles_pfd_low : integer := 0;
variable cycles_pfd_high : integer := 0;
variable cycles_to_lock : integer := 0;
variable cycles_to_unlock : integer := 0;
variable got_first_refclk : boolean := false;
variable got_second_refclk : boolean := false;
variable got_first_fbclk : boolean := false;
variable refclk_time : time := 0 ps;
variable fbclk_time : time := 0 ps;
variable first_fbclk_time : time := 0 ps;
variable fbclk_period : time := 0 ps;
variable first_schedule : boolean := true;
variable vco_val : std_logic := '0';
variable vco_period_was_phase_adjusted : boolean := false;
variable phase_adjust_was_scheduled : boolean := false;
variable loop_xplier : integer;
variable loop_initial : integer := 0;
variable loop_ph : integer := 0;
variable loop_time_delay : integer := 0;
variable initial_delay : time := 0 ps;
variable vco_per : time;
variable tmp_rem : integer;
variable my_rem : integer;
variable fbk_phase : integer := 0;
variable pull_back_M : integer := 0;
variable total_pull_back : integer := 0;
variable fbk_delay : integer := 0;
variable offset : time := 0 ps;
variable tmp_vco_per : integer := 0;
variable high_time : time;
variable low_time : time;
variable got_refclk_posedge : boolean := false;
variable got_fbclk_posedge : boolean := false;
variable inclk_out_of_range : boolean := false;
variable no_warn : boolean := false;
variable ext_fbk_cntr_modulus : integer := 1;
variable init_clks : boolean := true;
variable pll_is_in_reset : boolean := false;
variable buf : line;
begin
if (init) then
-- jump-start the VCO
-- add 1 ps delay to ensure all signals are updated to initial
-- values
schedule_vco <= transport not schedule_vco after 1 ps;
init := false;
end if;
if (schedule_vco'event) then
if (init_clks) then
refclk_period := inclk0_input_frequency * n_val * 1 ps;
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
init_clks := false;
end if;
sched_time := 0 ps;
for i in 0 to 7 loop
last_phase_shift(i) := phase_shift(i);
end loop;
cycle_to_adjust := 0;
l_index := 1;
m_times_vco_period := new_m_times_vco_period;
end if;
-- areset was asserted
if (areset_ipd'event and areset_ipd = '1') then
assert false report family_name & " PLL was reset" severity note;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
end if;
if (schedule_vco'event and (areset_ipd = '1' or stop_vco)) then
if (areset_ipd = '1') then
pll_is_in_reset := true;
got_first_refclk := false;
got_second_refclk := false;
end if;
-- drop VCO taps to 0
for i in 0 to 7 loop
vco_out(i) <= transport '0' after last_phase_shift(i);
phase_shift(i) := 0 ps;
last_phase_shift(i) := 0 ps;
end loop;
-- reset lock parameters
pll_is_locked := false;
cycles_to_lock := 0;
cycles_to_unlock := 0;
got_first_refclk := false;
got_second_refclk := false;
refclk_time := 0 ps;
got_first_fbclk := false;
fbclk_time := 0 ps;
first_fbclk_time := 0 ps;
fbclk_period := 0 ps;
first_schedule := true;
vco_val := '0';
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
elsif ((schedule_vco'event or areset_ipd'event) and areset_ipd = '0' and (not stop_vco) and now > 0 ps) then
-- note areset deassert time
-- note it as refclk_time to prevent false triggering
-- of stop_vco after areset
if (areset_ipd'event and areset_ipd = '0' and pll_is_in_reset) then
refclk_time := now;
pll_is_in_reset := false;
locked_tmp := '0';
end if;
-- calculate loop_xplier : this will be different from m_val
-- in external_feedback_mode
loop_xplier := m_val;
loop_initial := m_initial_val - 1;
loop_ph := m_ph_val;
-- convert initial value to delay
initial_delay := (loop_initial * m_times_vco_period)/loop_xplier;
-- convert loop ph_tap to delay
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
tmp_vco_per := (m_times_vco_period/1 ps) / loop_xplier;
if (my_rem /= 0) then
tmp_vco_per := tmp_vco_per + 1;
end if;
fbk_phase := (loop_ph * tmp_vco_per)/8;
pull_back_M := initial_delay/1 ps + fbk_phase;
total_pull_back := pull_back_M;
if (simulation_type = "timing") then
total_pull_back := total_pull_back + pll_compensation_delay;
end if;
while (total_pull_back > refclk_period/1 ps) loop
total_pull_back := total_pull_back - refclk_period/1 ps;
end loop;
if (total_pull_back > 0) then
offset := refclk_period - (total_pull_back * 1 ps);
end if;
fbk_delay := total_pull_back - fbk_phase;
if (fbk_delay < 0) then
offset := offset - (fbk_phase * 1 ps);
fbk_delay := total_pull_back;
end if;
-- assign m_delay
m_delay <= transport fbk_delay after 1 ps;
my_rem := (m_times_vco_period/1 ps) rem loop_xplier;
for i in 1 to loop_xplier loop
-- adjust cycles
tmp_vco_per := (m_times_vco_period/1 ps)/loop_xplier;
if (my_rem /= 0 and l_index <= my_rem) then
tmp_rem := (loop_xplier * l_index) rem my_rem;
cycle_to_adjust := (loop_xplier * l_index) / my_rem;
if (tmp_rem /= 0) then
cycle_to_adjust := cycle_to_adjust + 1;
end if;
end if;
if (cycle_to_adjust = i) then
tmp_vco_per := tmp_vco_per + 1;
l_index := l_index + 1;
end if;
-- calculate high and low periods
vco_per := tmp_vco_per * 1 ps;
high_time := (tmp_vco_per/2) * 1 ps;
if (tmp_vco_per rem 2 /= 0) then
high_time := high_time + 1 ps;
end if;
low_time := vco_per - high_time;
-- schedule the rising and falling edges
for j in 1 to 2 loop
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
if (first_schedule) then
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
else
vco_out(k) <= transport vco_val after (sched_time + last_phase_shift(k));
end if;
end loop;
end loop;
end loop;
-- schedule once more
if (first_schedule) then
vco_val := not vco_val;
if (vco_val = '0') then
sched_time := sched_time + high_time;
elsif (vco_val = '1') then
sched_time := sched_time + low_time;
end if;
-- schedule the phase taps
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
vco_out(k) <= transport vco_val after (sched_time + phase_shift(k));
end loop;
first_schedule := false;
end if;
schedule_vco <= transport not schedule_vco after sched_time;
if (vco_period_was_phase_adjusted) then
m_times_vco_period := refclk_period;
new_m_times_vco_period := refclk_period;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := true;
vco_per := m_times_vco_period/loop_xplier;
for k in 0 to 7 loop
phase_shift(k) := (k * vco_per)/8;
end loop;
end if;
end if;
-- Bypass lock detect
if (refclk'event and refclk = '1' and areset_ipd = '0') then
if (test_bypass_lock_detect = "on") then
if (pfdena_ipd = '1') then
cycles_pfd_low := 0;
if (pfd_locked = '0') then
if (cycles_pfd_high = lock_high) then
assert false report family_name & " PLL locked in test mode on PFD enable assertion." severity warning;
pfd_locked <= '1';
end if;
cycles_pfd_high := cycles_pfd_high + 1;
end if;
end if;
if (pfdena_ipd = '0') then
cycles_pfd_high := 0;
if (pfd_locked = '1') then
if (cycles_pfd_low = lock_low) then
assert false report family_name & " PLL lost lock in test mode on PFD enable de-assertion." severity warning;
pfd_locked <= '0';
end if;
cycles_pfd_low := cycles_pfd_low + 1;
end if;
end if;
end if;
if (refclk'event and refclk = '1' and areset_ipd = '0') then
got_refclk_posedge := true;
if (not got_first_refclk) then
got_first_refclk := true;
else
got_second_refclk := true;
refclk_period := now - refclk_time;
-- check if incoming freq. will cause VCO range to be
-- exceeded
if ( (i_vco_max /= 0 and i_vco_min /= 0 and pfdena_ipd = '1') and
(((refclk_period/1 ps)/loop_xplier > i_vco_max) or
((refclk_period/1 ps)/loop_xplier < i_vco_min)) ) then
if (pll_is_locked) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
if (inclk_out_of_range) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
end if;
elsif (not no_warn) then
if ((refclk_period/1 ps)/loop_xplier > i_vco_max) then
assert false report "Input clock freq. is over VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_over <= '1';
end if;
if ((refclk_period/1 ps)/loop_xplier < i_vco_min) then
assert false report "Input clock freq. is under VCO range. " & family_name & " PLL may lose lock" severity warning;
vco_under <= '1';
end if;
assert false report " Input clock freq. is not within VCO range : " & family_name & " PLL may not lock. Please use the correct frequency." severity warning;
no_warn := true;
end if;
inclk_out_of_range := true;
else
vco_over <= '0';
vco_under <= '0';
inclk_out_of_range := false;
no_warn := false;
end if;
end if;
end if;
if (stop_vco) then
stop_vco := false;
schedule_vco <= not schedule_vco;
end if;
refclk_time := now;
else
got_refclk_posedge := false;
end if;
-- Update M counter value on feedback clock edge
if (fbclk'event and fbclk = '1') then
got_fbclk_posedge := true;
if (not got_first_fbclk) then
got_first_fbclk := true;
else
fbclk_period := now - fbclk_time;
end if;
-- need refclk_period here, so initialized to proper value above
if ( ( (now - refclk_time > 1.5 * refclk_period) and pfdena_ipd = '1' and pll_is_locked) or
( (now - refclk_time > 5 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = false) or
( (now - refclk_time > 50 * refclk_period) and pfdena_ipd = '1' and pll_has_just_been_reconfigured = true) ) then
stop_vco := true;
-- reset
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
if (pll_is_locked) then
pll_is_locked := false;
locked_tmp := '0';
assert false report family_name & " PLL lost lock due to loss of input clock or the input clock is not detected within the allowed time frame." severity note;
if ((i_vco_max = 0) and (i_vco_min = 0)) then
assert false report "Please run timing simulation to check whether the input clock is operating within the supported VCO range or not." severity note;
end if;
end if;
cycles_to_lock := 0;
cycles_to_unlock := 0;
first_schedule := true;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
end if;
fbclk_time := now;
else
got_fbclk_posedge := false;
end if;
if ((got_refclk_posedge or got_fbclk_posedge) and got_second_refclk and pfdena_ipd = '1' and (not inclk_out_of_range)) then
-- now we know actual incoming period
if ( abs(fbclk_time - refclk_time) <= 5 ps or
(got_first_fbclk and abs(refclk_period - abs(fbclk_time - refclk_time)) <= 5 ps)) then
-- considered in phase
if (cycles_to_lock = real_lock_high) then
if (not pll_is_locked) then
assert false report family_name & " PLL locked to incoming clock" severity note;
end if;
pll_is_locked := true;
locked_tmp := '1';
cycles_to_unlock := 0;
end if;
-- increment lock counter only if second part of above
-- time check is NOT true
if (not(abs(refclk_period - abs(fbclk_time - refclk_time)) <= lock_window)) then
cycles_to_lock := cycles_to_lock + 1;
end if;
-- adjust m_times_vco_period
new_m_times_vco_period := refclk_period;
else
-- if locked, begin unlock
if (pll_is_locked) then
cycles_to_unlock := cycles_to_unlock + 1;
if (cycles_to_unlock = lock_low) then
pll_is_locked := false;
locked_tmp := '0';
cycles_to_lock := 0;
vco_period_was_phase_adjusted := false;
phase_adjust_was_scheduled := false;
assert false report family_name & " PLL lost lock." severity note;
got_first_refclk := false;
got_first_fbclk := false;
got_second_refclk := false;
end if;
end if;
if ( abs(refclk_period - fbclk_period) <= 2 ps ) then
-- frequency is still good
if (now = fbclk_time and (not phase_adjust_was_scheduled)) then
if ( abs(fbclk_time - refclk_time) > refclk_period/2) then
new_m_times_vco_period := m_times_vco_period + (refclk_period - abs(fbclk_time - refclk_time));
vco_period_was_phase_adjusted := true;
else
new_m_times_vco_period := m_times_vco_period - abs(fbclk_time - refclk_time);
vco_period_was_phase_adjusted := true;
end if;
end if;
else
phase_adjust_was_scheduled := false;
new_m_times_vco_period := refclk_period;
end if;
end if;
end if;
if (pfdena_ipd = '0') then
if (pll_is_locked) then
locked_tmp := 'X';
end if;
pll_is_locked := false;
cycles_to_lock := 0;
end if;
-- give message only at time of deassertion
if (pfdena_ipd'event and pfdena_ipd = '0') then
assert false report "PFDENA deasserted." severity note;
elsif (pfdena_ipd'event and pfdena_ipd = '1') then
got_first_refclk := false;
got_second_refclk := false;
refclk_time := now;
end if;
if (reconfig_err) then
lock <= '0';
else
lock <= locked_tmp;
end if;
-- signal to calculate quiet_time
sig_refclk_period <= refclk_period;
if (stop_vco = true) then
sig_stop_vco <= '1';
else
sig_stop_vco <= '0';
end if;
pll_locked <= pll_is_locked;
end process;
clk0_tmp <= c_clk(i_clk0_counter);
clk_pfd(0) <= clk0_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(0) <= clk_pfd(0) WHEN (test_bypass_lock_detect = "on") ELSE
clk0_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else
'X';
clk1_tmp <= c_clk(i_clk1_counter);
clk_pfd(1) <= clk1_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(1) <= clk_pfd(1) WHEN (test_bypass_lock_detect = "on") ELSE
clk1_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk2_tmp <= c_clk(i_clk2_counter);
clk_pfd(2) <= clk2_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(2) <= clk_pfd(2) WHEN (test_bypass_lock_detect = "on") ELSE
clk2_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk3_tmp <= c_clk(i_clk3_counter);
clk_pfd(3) <= clk3_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(3) <= clk_pfd(3) WHEN (test_bypass_lock_detect = "on") ELSE
clk3_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
clk4_tmp <= c_clk(i_clk4_counter);
clk_pfd(4) <= clk4_tmp WHEN (pfd_locked = '1') ELSE 'X';
clk(4) <= clk_pfd(4) WHEN (test_bypass_lock_detect = "on") ELSE
clk4_tmp when (areset_ipd = '1' or pll_in_test_mode) or (pll_locked and (not reconfig_err)) else 'X';
scandataout <= scandata_out;
scandone <= NOT scandone_tmp;
phasedone <= NOT update_phase;
vcooverrange <= 'Z' WHEN (vco_range_detector_high_bits = -1) ELSE vco_over;
vcounderrange <= 'Z' WHEN (vco_range_detector_low_bits = -1) ELSE vco_under;
fbout <= fbclk;
end vital_pll;
-- END ARCHITECTURE VITAL_PLL
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ff
--
-- Description : Cyclone III FF VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_and1;
entity cycloneiii_ff is
generic (
power_up : string := "low";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_ff";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
clrn : in std_logic := '1';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
asdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ff : entity is TRUE;
end cycloneiii_ff;
architecture vital_lcell_ff of cycloneiii_ff is
attribute VITAL_LEVEL0 of vital_lcell_ff : architecture is TRUE;
signal clk_ipd : std_logic;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal asdata_ipd : std_logic;
signal asdata_dly : std_logic;
signal asdata_dly1 : std_logic;
signal sclr_ipd : std_logic;
signal sload_ipd : std_logic;
signal clrn_ipd : std_logic;
signal aload_ipd : std_logic;
signal ena_ipd : std_logic;
component cycloneiii_and1
generic (XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
tpd_IN1_Y : VitalDelayType01 := DefPropDelay01;
tipd_IN1 : VitalDelayType01 := DefPropDelay01
);
port (Y : out STD_LOGIC;
IN1 : in STD_LOGIC
);
end component;
begin
ddelaybuffer: cycloneiii_and1
port map(IN1 => d_ipd,
Y => d_dly);
asdatadelaybuffer: cycloneiii_and1
port map(IN1 => asdata_ipd,
Y => asdata_dly);
asdatadelaybuffer1: cycloneiii_and1
port map(IN1 => asdata_dly,
Y => asdata_dly1);
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (asdata_ipd, asdata, tipd_asdata);
VitalWireDelay (sclr_ipd, sclr, tipd_sclr);
VitalWireDelay (sload_ipd, sload, tipd_sload);
VitalWireDelay (clrn_ipd, clrn, tipd_clrn);
VitalWireDelay (aload_ipd, aload, tipd_aload);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, d_dly, asdata_dly1,
sclr_ipd, sload_ipd, clrn_ipd, aload_ipd,
ena_ipd, devclrn, devpor)
variable Tviol_d_clk : std_ulogic := '0';
variable Tviol_asdata_clk : std_ulogic := '0';
variable Tviol_sclr_clk : std_ulogic := '0';
variable Tviol_sload_clk : std_ulogic := '0';
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_asdata_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sclr_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_sload_clk : VitalTimingDataType := VitalTimingDataInit;
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
if (now = 0 ns) then
if (power_up = "low") then
iq := '0';
elsif (power_up = "high") then
iq := '1';
end if;
end if;
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "DATAIN",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(sload_ipd) OR
(sclr_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_asdata_clk,
TimingData => TimingData_asdata_clk,
TestSignal => asdata_ipd,
TestSignalName => "ASDATA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_asdata_clk_noedge_posedge,
SetupLow => tsetup_asdata_clk_noedge_posedge,
HoldHigh => thold_asdata_clk_noedge_posedge,
HoldLow => thold_asdata_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT sload_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sclr_clk,
TimingData => TimingData_sclr_clk,
TestSignal => sclr_ipd,
TestSignalName => "SCLR",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sclr_clk_noedge_posedge,
SetupLow => tsetup_sclr_clk_noedge_posedge,
HoldHigh => thold_sclr_clk_noedge_posedge,
HoldLow => thold_sclr_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_sload_clk,
TimingData => TimingData_sload_clk,
TestSignal => sload_ipd,
TestSignalName => "SLOAD",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_sload_clk_noedge_posedge,
SetupLow => tsetup_sload_clk_noedge_posedge,
HoldHigh => thold_sload_clk_noedge_posedge,
HoldLow => thold_sload_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) OR
(NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((NOT clrn_ipd) OR
(NOT devpor) OR
(NOT devclrn) ) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/LCELL_FF",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
violation := Tviol_d_clk or Tviol_asdata_clk or
Tviol_sclr_clk or Tviol_sload_clk or Tviol_ena_clk;
if ((devpor = '0') or (devclrn = '0') or (clrn_ipd = '0')) then
iq := '0';
elsif (aload_ipd = '1') then
iq := asdata_dly1;
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' then
if (ena_ipd = '1') then
if (sclr_ipd = '1') then
iq := '0';
elsif (sload_ipd = '1') then
iq := asdata_dly1;
else
iq := d_dly;
end if;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clrn_ipd'last_event, tpd_clrn_q_posedge, TRUE),
1 => (aload_ipd'last_event, tpd_aload_q_posedge, TRUE),
2 => (asdata_ipd'last_event, tpd_asdata_q, TRUE),
3 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_lcell_ff;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_register
-- Description : Register module for RAM inputs/outputs
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_register IS
GENERIC (
width : INTEGER := 1;
preset : STD_LOGIC := '0';
tipd_d : VitalDelayArrayType01(143 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_stall : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpw_ena_posedge : VitalDelayType := DefPulseWdthCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_stall_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_aclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END cycloneiii_ram_register;
ARCHITECTURE reg_arch OF cycloneiii_ram_register IS
SIGNAL d_ipd : STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
SIGNAL clk_ipd : STD_LOGIC;
SIGNAL ena_ipd : STD_LOGIC;
SIGNAL aclr_ipd : STD_LOGIC;
SIGNAL stall_ipd : STD_LOGIC;
BEGIN
WireDelay : BLOCK
BEGIN
loopbits : FOR i in d'RANGE GENERATE
VitalWireDelay (d_ipd(i), d(i), tipd_d(i));
END GENERATE;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (stall_ipd, stall, tipd_stall);
END BLOCK;
-- REMCUDA PROCESS (d_ipd,ena_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
PROCESS (d_ipd,ena_ipd,stall_ipd,clk_ipd,aclr_ipd,devclrn,devpor)
VARIABLE Tviol_clk_ena : STD_ULOGIC := '0';
VARIABLE Tviol_clk_aclr : STD_ULOGIC := '0';
VARIABLE Tviol_data_clk : STD_ULOGIC := '0';
VARIABLE TimingData_clk_ena : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_stall : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_clk_aclr : VitalTimingDataType := VitalTimingDataInit;
VARIABLE TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
VARIABLE Tviol_ena : STD_ULOGIC := '0';
VARIABLE PeriodData_ena : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE q_VitalGlitchDataArray : VitalGlitchDataArrayType(143 downto 0);
VARIABLE CQDelay : TIME := 0 ns;
VARIABLE q_reg : STD_LOGIC_VECTOR(width - 1 DOWNTO 0) := (OTHERS => preset);
BEGIN
IF (aclr_ipd = '1' OR devclrn = '0' OR devpor = '0') THEN
q_reg := (OTHERS => preset);
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1' AND stall_ipd = '0') THEN
q_reg := d_ipd;
END IF;
-- Timing checks
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_ena,
TimingData => TimingData_clk_stall,
TestSignal => stall_ipd,
TestSignalName => "stall",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_stall_clk_noedge_posedge,
SetupLow => tsetup_stall_clk_noedge_posedge,
HoldHigh => thold_stall_clk_noedge_posedge,
HoldLow => thold_stall_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_clk_aclr,
TimingData => TimingData_clk_aclr,
TestSignal => aclr_ipd,
TestSignalName => "aclr",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_aclr_clk_noedge_posedge,
SetupLow => tsetup_aclr_clk_noedge_posedge,
HoldHigh => thold_aclr_clk_noedge_posedge,
HoldLow => thold_aclr_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => d_ipd,
TestSignalName => "data",
RefSignal => clk_ipd,
RefSignalName => "clk",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => ((aclr_ipd) OR (NOT ena_ipd)) /= '1',
RefTransition => '/',
HeaderMsg => "/RAM Register VitalSetupHoldCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
VitalPeriodPulseCheck (
Violation => Tviol_ena,
PeriodData => PeriodData_ena,
TestSignal => ena_ipd,
TestSignalName => "ena",
PulseWidthHigh => tpw_ena_posedge,
HeaderMsg => "/RAM Register VitalPeriodPulseCheck",
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks );
-- Path Delay Selection
CQDelay := SelectDelay (
Paths => (
(0 => (clk_ipd'LAST_EVENT,tpd_clk_q_posedge,TRUE),
1 => (aclr_ipd'LAST_EVENT,tpd_aclr_q_posedge,TRUE))
)
);
q <= TRANSPORT q_reg AFTER CQDelay;
END PROCESS;
aclrout <= aclr_ipd;
END reg_arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_ram_pulse_generator
-- Description : Generate pulse to initiate memory read/write operations
----------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ram_pulse_generator IS
GENERIC (
tipd_clk : VitalDelayType01 := (0.5 ns,0.5 ns);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tpd_clk_pulse_posedge : VitalDelayType01 := DefPropDelay01
);
PORT (
clk,ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse,cycle : OUT STD_LOGIC
);
ATTRIBUTE VITAL_Level0 OF cycloneiii_ram_pulse_generator:ENTITY IS TRUE;
END cycloneiii_ram_pulse_generator;
ARCHITECTURE pgen_arch OF cycloneiii_ram_pulse_generator IS
SIGNAL clk_ipd,ena_ipd : STD_LOGIC;
SIGNAL state : STD_LOGIC;
ATTRIBUTE VITAL_Level0 OF pgen_arch:ARCHITECTURE IS TRUE;
BEGIN
WireDelay : BLOCK
BEGIN
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
END BLOCK;
PROCESS (clk_ipd,state)
BEGIN
IF (state = '1' AND state'EVENT) THEN
state <= '0';
ELSIF (clk_ipd = '1' AND clk_ipd'EVENT AND ena_ipd = '1') THEN
IF (delaywrite = '1') THEN
state <= '1' AFTER 1 NS; -- delayed write
ELSE
state <= '1';
END IF;
END IF;
END PROCESS;
PathDelay : PROCESS
VARIABLE pulse_VitalGlitchData : VitalGlitchDataType;
BEGIN
WAIT UNTIL state'EVENT;
VitalPathDelay01 (
OutSignal => pulse,
OutSignalName => "pulse",
OutTemp => state,
Paths => (0 => (clk_ipd'LAST_EVENT,tpd_clk_pulse_posedge,TRUE)),
GlitchData => pulse_VitalGlitchData,
Mode => DefGlitchMode,
XOn => DefXOnChecks,
MsgOn => DefMsgOnChecks
);
END PROCESS;
cycle <= clk_ipd;
END pgen_arch;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.VITAL_Timing.all;
USE IEEE.VITAL_Primitives.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_ram_register;
USE work.cycloneiii_ram_pulse_generator;
ENTITY cycloneiii_ram_block IS
GENERIC (
-- -------- GLOBAL PARAMETERS ---------
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_address_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_read_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_address_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_write_enable_clock: STRING := "clock1";
port_b_read_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
port_a_read_during_write_mode : STRING := "new_data_no_nbe_read";
port_b_read_during_write_mode : STRING := "new_data_no_nbe_read";
power_up_uninitialized : STRING := "false";
port_b_byte_size : INTEGER := 0;
port_a_byte_size : INTEGER := 0;
safe_write : STRING := "err_on_2clk";
init_file_restructured : STRING := "unused";
lpm_type : string := "cycloneiii_ram_block";
lpm_hint : string := "true";
clk0_input_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_core_clock_enable : STRING := "none"; -- ena0,ena2,none
clk0_output_clock_enable : STRING := "none"; -- ena0,none
clk1_input_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_core_clock_enable : STRING := "none"; -- ena1,ena3,none
clk1_output_clock_enable : STRING := "none"; -- ena1,none
-- REMStratix IV -- REMArria II GX -- REMHardCopy III clock_duty_cycle_dependence : STRING := "Auto";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
mem_init2 : BIT_VECTOR := X"0";
mem_init3 : BIT_VECTOR := X"0";
mem_init4 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
-- -------- PORT DECLARATIONS ---------
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portare : IN STD_LOGIC := '1';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbwe : IN STD_LOGIC := '0';
portbre : IN STD_LOGIC := '1';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
ena2 : IN STD_LOGIC := '1';
ena3 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END cycloneiii_ram_block;
ARCHITECTURE block_arch OF cycloneiii_ram_block IS
COMPONENT cycloneiii_ram_pulse_generator
PORT (
clk : IN STD_LOGIC;
ena : IN STD_LOGIC;
delaywrite : IN STD_LOGIC := '0';
pulse : OUT STD_LOGIC;
cycle : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_ram_register
GENERIC (
preset : STD_LOGIC := '0';
width : integer := 1
);
PORT (
d : IN STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
clk : IN STD_LOGIC;
aclr : IN STD_LOGIC;
devclrn : IN STD_LOGIC;
devpor : IN STD_LOGIC;
ena : IN STD_LOGIC;
stall : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(width - 1 DOWNTO 0);
aclrout : OUT STD_LOGIC
);
END COMPONENT;
FUNCTION cond (condition : BOOLEAN;CONSTANT a,b : INTEGER) RETURN INTEGER IS
VARIABLE c: INTEGER;
BEGIN
IF (condition) THEN c := a; ELSE c := b; END IF;
RETURN c;
END;
SUBTYPE port_type IS BOOLEAN;
CONSTANT primary : port_type := TRUE;
CONSTANT secondary : port_type := FALSE;
CONSTANT primary_port_is_a : BOOLEAN := (port_b_data_width <= port_a_data_width);
CONSTANT primary_port_is_b : BOOLEAN := NOT primary_port_is_a;
CONSTANT mode_is_rom : BOOLEAN := (operation_mode = "rom");
CONSTANT mode_is_sp : BOOLEAN := (operation_mode = "single_port");
CONSTANT mode_is_dp : BOOLEAN := (operation_mode = "dual_port");
CONSTANT mode_is_bdp : BOOLEAN := (operation_mode = "bidir_dual_port");
CONSTANT wired_mode : BOOLEAN := (port_a_address_width = port_b_address_width) AND (port_a_address_width = 1)
AND (port_a_data_width /= port_b_data_width);
CONSTANT num_cols : INTEGER := cond(mode_is_rom OR mode_is_sp,1,
cond(wired_mode,2,2 ** (ABS(port_b_address_width - port_a_address_width))));
CONSTANT data_width : INTEGER := cond(primary_port_is_a,port_a_data_width,port_b_data_width);
CONSTANT data_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_data_width,port_b_data_width);
CONSTANT address_unit_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_a,port_a_address_width,port_b_address_width);
CONSTANT address_width : INTEGER := cond(mode_is_rom OR mode_is_sp OR primary_port_is_b,port_a_address_width,port_b_address_width);
CONSTANT byte_size_a : INTEGER := port_a_data_width / port_a_byte_enable_mask_width;
CONSTANT byte_size_b : INTEGER := port_b_data_width / port_b_byte_enable_mask_width;
CONSTANT out_a_is_reg : BOOLEAN := (port_a_data_out_clock /= "none" AND port_a_data_out_clock /= "UNUSED");
CONSTANT out_b_is_reg : BOOLEAN := (port_b_data_out_clock /= "none" AND port_b_data_out_clock /= "UNUSED");
CONSTANT bytes_a_disabled : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT bytes_b_disabled : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '0');
CONSTANT ram_type : BOOLEAN := FALSE;
TYPE bool_to_std_logic_map IS ARRAY(TRUE DOWNTO FALSE) OF STD_LOGIC;
CONSTANT bool_to_std_logic : bool_to_std_logic_map := ('1','0');
-- Hardware write modes
CONSTANT dual_clock : BOOLEAN := (operation_mode = "dual_port" OR
operation_mode = "bidir_dual_port") AND
(port_b_address_clock = "clock1");
CONSTANT both_new_data_same_port : BOOLEAN := (
((port_a_read_during_write_mode = "new_data_no_nbe_read") OR
(port_a_read_during_write_mode = "dont_care")) AND
((port_b_read_during_write_mode = "new_data_no_nbe_read") OR
(port_b_read_during_write_mode = "dont_care"))
);
SIGNAL hw_write_mode_a : STRING(3 DOWNTO 1);
SIGNAL hw_write_mode_b : STRING(3 DOWNTO 1);
SIGNAL delay_write_pulse_a : STD_LOGIC ;
SIGNAL delay_write_pulse_b : STD_LOGIC ;
CONSTANT be_mask_write_a : BOOLEAN := (port_a_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT be_mask_write_b : BOOLEAN := (port_b_read_during_write_mode = "new_data_with_nbe_read");
CONSTANT old_data_write_a : BOOLEAN := (port_a_read_during_write_mode = "old_data");
CONSTANT old_data_write_b : BOOLEAN := (port_b_read_during_write_mode = "old_data");
SIGNAL read_before_write_a : BOOLEAN;
SIGNAL read_before_write_b : BOOLEAN;
-- -------- internal signals ---------
-- clock / clock enable
SIGNAL clk_a_in,clk_b_in : STD_LOGIC;
SIGNAL clk_a_byteena,clk_b_byteena : STD_LOGIC;
SIGNAL clk_a_out,clk_b_out : STD_LOGIC;
SIGNAL clkena_a_out,clkena_b_out : STD_LOGIC;
SIGNAL clkena_out_c0, clkena_out_c1 : STD_LOGIC;
SIGNAL write_cycle_a,write_cycle_b : STD_LOGIC;
SIGNAL clk_a_rena, clk_a_wena : STD_LOGIC;
SIGNAL clk_a_core : STD_LOGIC;
SIGNAL clk_b_rena, clk_b_wena : STD_LOGIC;
SIGNAL clk_b_core : STD_LOGIC;
SUBTYPE one_bit_bus_type IS STD_LOGIC_VECTOR(0 DOWNTO 0);
-- asynch clear
TYPE clear_mode_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
TYPE clear_vec_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL datain_a_clr,datain_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr,dataout_b_clr : STD_LOGIC;
SIGNAL dataout_a_clr_reg, dataout_b_clr_reg : STD_LOGIC;
SIGNAL dataout_a_clr_reg_in, dataout_b_clr_reg_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_out, dataout_b_clr_reg_out : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch, dataout_b_clr_reg_latch : STD_LOGIC;
SIGNAL dataout_a_clr_reg_latch_in, dataout_b_clr_reg_latch_in : one_bit_bus_type;
SIGNAL dataout_a_clr_reg_latch_out, dataout_b_clr_reg_latch_out : one_bit_bus_type;
SIGNAL addr_a_clr,addr_b_clr : STD_LOGIC;
SIGNAL byteena_a_clr,byteena_b_clr : STD_LOGIC;
SIGNAL we_a_clr,re_a_clr,we_b_clr,re_b_clr : STD_LOGIC;
SIGNAL datain_a_clr_in,datain_b_clr_in : STD_LOGIC;
SIGNAL addr_a_clr_in,addr_b_clr_in : STD_LOGIC;
SIGNAL byteena_a_clr_in,byteena_b_clr_in : STD_LOGIC;
SIGNAL we_a_clr_in,re_a_clr_in,we_b_clr_in,re_b_clr_in : STD_LOGIC;
SIGNAL mem_invalidate,mem_invalidate_loc,read_latch_invalidate : clear_mode_type;
SIGNAL clear_asserted_during_write : clear_vec_type;
-- port A registers
SIGNAL we_a_reg : STD_LOGIC;
SIGNAL re_a_reg : STD_LOGIC;
SIGNAL we_a_reg_in,we_a_reg_out : one_bit_bus_type;
SIGNAL re_a_reg_in,re_a_reg_out : one_bit_bus_type;
SIGNAL addr_a_reg : STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0);
SIGNAL datain_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a_reg : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL dataout_a : STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
SIGNAL byteena_a_reg : STD_LOGIC_VECTOR(port_a_byte_enable_mask_width- 1 DOWNTO 0);
-- port B registers
SIGNAL we_b_reg, re_b_reg : STD_LOGIC;
SIGNAL re_b_reg_in,re_b_reg_out,we_b_reg_in,we_b_reg_out : one_bit_bus_type;
SIGNAL addr_b_reg : STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0);
SIGNAL datain_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b_reg : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL dataout_b : STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0);
SIGNAL byteena_b_reg : STD_LOGIC_VECTOR(port_b_byte_enable_mask_width- 1 DOWNTO 0);
-- pulses
TYPE pulse_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF STD_LOGIC;
SIGNAL write_pulse,read_pulse,read_pulse_feedthru : pulse_vec;
SIGNAL rw_pulse : pulse_vec;
SIGNAL wpgen_a_clk,wpgen_a_clkena,wpgen_b_clk,wpgen_b_clkena : STD_LOGIC;
SIGNAL rpgen_a_clkena,rpgen_b_clkena : STD_LOGIC;
SIGNAL ftpgen_a_clkena,ftpgen_b_clkena : STD_LOGIC;
SIGNAL rwpgen_a_clkena,rwpgen_b_clkena : STD_LOGIC;
-- registered address
SIGNAL addr_prime_reg,addr_sec_reg : INTEGER;
-- input/output
SIGNAL datain_prime_reg,dataout_prime : STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0);
SIGNAL datain_sec_reg,dataout_sec : STD_LOGIC_VECTOR(data_unit_width - 1 DOWNTO 0);
-- overlapping location write
SIGNAL dual_write : BOOLEAN;
-- byte enable mask write
TYPE be_mask_write_vec IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
SIGNAL be_mask_write : be_mask_write_vec;
-- memory core
SUBTYPE mem_word_type IS STD_LOGIC_VECTOR (data_width - 1 DOWNTO 0);
SUBTYPE mem_col_type IS STD_LOGIC_VECTOR (data_unit_width - 1 DOWNTO 0);
TYPE mem_row_type IS ARRAY (num_cols - 1 DOWNTO 0) OF mem_col_type;
TYPE mem_type IS ARRAY ((2 ** address_unit_width) - 1 DOWNTO 0) OF mem_row_type;
SIGNAL mem : mem_type;
SIGNAL init_mem : BOOLEAN := FALSE;
CONSTANT mem_x : mem_type := (OTHERS => (OTHERS => (OTHERS => 'X')));
CONSTANT row_x : mem_row_type := (OTHERS => (OTHERS => 'X'));
CONSTANT col_x : mem_col_type := (OTHERS => 'X');
SIGNAL mem_data : mem_row_type;
SIGNAL old_mem_data : mem_row_type;
SIGNAL mem_unit_data : mem_col_type;
-- latches
TYPE read_latch_rec IS RECORD
prime : mem_row_type;
sec : mem_col_type;
END RECORD;
SIGNAL read_latch : read_latch_rec;
-- (row,column) coordinates
SIGNAL row_sec,col_sec : INTEGER;
-- byte enable
TYPE mask_type IS (normal,inverse);
TYPE mask_prime_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_word_type;
TYPE mask_sec_type IS ARRAY(mask_type'HIGH DOWNTO mask_type'LOW) OF mem_col_type;
TYPE mask_rec IS RECORD
prime : mask_prime_type;
sec : mask_sec_type;
END RECORD;
SIGNAL mask_vector : mask_rec;
SIGNAL mask_vector_common : mem_col_type;
FUNCTION get_mask(
b_ena : IN STD_LOGIC_VECTOR;
mode : port_type;
CONSTANT b_ena_width ,byte_size: INTEGER
) RETURN mask_rec IS
VARIABLE l : INTEGER;
VARIABLE mask : mask_rec := (
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X')),
(normal => (OTHERS => '0'),inverse => (OTHERS => 'X'))
);
BEGIN
FOR l in 0 TO b_ena_width - 1 LOOP
IF (b_ena(l) = '0') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.prime(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
mask.sec(inverse)((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => '0');
END IF;
ELSIF (b_ena(l) = 'X' OR b_ena(l) = 'U') THEN
IF (mode = primary) THEN
mask.prime(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
ELSE
mask.sec(normal) ((l+1)*byte_size - 1 DOWNTO l*byte_size) := (OTHERS => 'X');
END IF;
END IF;
END LOOP;
RETURN mask;
END get_mask;
-- port active for read/write
SIGNAL active_a_core_in_vec,active_b_core_in_vec,active_a_core_out,active_b_core_out : one_bit_bus_type;
SIGNAL active_a_in,active_b_in : STD_LOGIC;
SIGNAL active_write_a : BOOLEAN;
SIGNAL active_write_b : BOOLEAN;
SIGNAL active_b_in_c0,active_b_core_in_c0,active_b_in_c1,active_b_core_in_c1 : STD_LOGIC;
SIGNAL active_a_core_in,active_b_core_in : STD_LOGIC;
SIGNAL active_a_core, active_b_core : BOOLEAN;
SIGNAL wire_vcc : STD_LOGIC := '1';
SIGNAL wire_gnd : STD_LOGIC := '0';
BEGIN
-- memory initialization
init_mem <= TRUE;
-- hardware write modes
hw_write_mode_a <= "R+W" WHEN ((port_a_read_during_write_mode = "old_data") OR
(port_a_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
hw_write_mode_b <= "R+W" WHEN ((port_b_read_during_write_mode = "old_data") OR
(port_b_read_during_write_mode = "new_data_with_nbe_read")) ELSE
" FW" WHEN (dual_clock OR (
mixed_port_feed_through_mode = "dont_care" AND
both_new_data_same_port
)) ELSE
" DW";
delay_write_pulse_a <= '1' WHEN (hw_write_mode_a /= " FW") ELSE '0';
delay_write_pulse_b <= '1' WHEN (hw_write_mode_b /= " FW") ELSE '0' ;
read_before_write_a <= (hw_write_mode_a = "R+W");
read_before_write_b <= (hw_write_mode_b = "R+W");
-- -------- core logic ---------------
clk_a_in <= clk0;
clk_a_wena <= '0' WHEN (port_a_write_enable_clock = "none") ELSE clk_a_in;
clk_a_rena <= '0' WHEN (port_a_read_enable_clock = "none") ELSE clk_a_in;
clk_a_byteena <= '0' WHEN (port_a_byte_enable_clock = "none" OR port_a_byte_enable_clock = "UNUSED") ELSE clk_a_in;
clk_a_out <= '0' WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_a_data_out_clock = "clock0") ELSE clk1;
clk_b_in <= clk0 WHEN (port_b_address_clock = "clock0") ELSE clk1;
clk_b_byteena <= '0' WHEN (port_b_byte_enable_clock = "none" OR port_b_byte_enable_clock = "UNUSED") ELSE
clk0 WHEN (port_b_byte_enable_clock = "clock0") ELSE clk1;
clk_b_wena <= '0' WHEN (port_b_write_enable_clock = "none") ELSE
clk0 WHEN (port_b_write_enable_clock = "clock0") ELSE
clk1;
clk_b_rena <= '0' WHEN (port_b_read_enable_clock = "none") ELSE
clk0 WHEN (port_b_read_enable_clock = "clock0") ELSE
clk1;
clk_b_out <= '0' WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
clk0 WHEN (port_b_data_out_clock = "clock0") ELSE clk1;
addr_a_clr_in <= '0' WHEN (port_a_address_clear = "none" OR port_a_address_clear = "UNUSED") ELSE clr0;
addr_b_clr_in <= '0' WHEN (port_b_address_clear = "none" OR port_b_address_clear = "UNUSED") ELSE
clr0 WHEN (port_b_address_clear = "clear0") ELSE clr1;
datain_a_clr_in <= '0';
datain_b_clr_in <= '0';
dataout_a_clr_reg <= '0' WHEN (port_a_data_out_clear = "none" OR port_a_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_a_data_out_clear = "clear0") ELSE clr1;
dataout_a_clr <= dataout_a_clr_reg WHEN (port_a_data_out_clock = "none" OR port_a_data_out_clock = "UNUSED") ELSE
'0';
dataout_b_clr_reg <= '0' WHEN (port_b_data_out_clear = "none" OR port_b_data_out_clear = "UNUSED") ELSE
clr0 WHEN (port_b_data_out_clear = "clear0") ELSE clr1;
dataout_b_clr <= dataout_b_clr_reg WHEN (port_b_data_out_clock = "none" OR port_b_data_out_clock = "UNUSED") ELSE
'0';
byteena_a_clr_in <= '0';
byteena_b_clr_in <= '0';
we_a_clr_in <= '0';
re_a_clr_in <= '0';
we_b_clr_in <= '0';
re_b_clr_in <= '0';
active_a_in <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_a_core_in <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
be_mask_write(primary_port_is_a) <= be_mask_write_a;
be_mask_write(primary_port_is_b) <= be_mask_write_b;
active_b_in_c0 <= '1' WHEN (clk0_input_clock_enable = "none") ELSE
ena0 WHEN (clk0_input_clock_enable = "ena0") ELSE
ena2;
active_b_in_c1 <= '1' WHEN (clk1_input_clock_enable = "none") ELSE
ena1 WHEN (clk1_input_clock_enable = "ena1") ELSE
ena3;
active_b_in <= active_b_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_in_c1;
active_b_core_in_c0 <= '1' WHEN (clk0_core_clock_enable = "none") ELSE
ena0 WHEN (clk0_core_clock_enable = "ena0") ELSE
ena2;
active_b_core_in_c1 <= '1' WHEN (clk1_core_clock_enable = "none") ELSE
ena1 WHEN (clk1_core_clock_enable = "ena1") ELSE
ena3;
active_b_core_in <= active_b_core_in_c0 WHEN (port_b_address_clock = "clock0") ELSE active_b_core_in_c1;
active_write_a <= (byteena_a_reg /= bytes_a_disabled);
active_write_b <= (byteena_b_reg /= bytes_b_disabled);
-- Store core clock enable value for delayed write
-- port A core active
active_a_core_in_vec(0) <= active_a_core_in;
active_core_port_a : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_a_core_in_vec,
clk => clk_a_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_a_core_out
);
active_a_core <= (active_a_core_out(0) = '1');
-- port B core active
active_b_core_in_vec(0) <= active_b_core_in;
active_core_port_b : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => active_b_core_in_vec,
clk => clk_b_in,
aclr => wire_gnd,
devclrn => wire_vcc,devpor => wire_vcc,
ena => wire_vcc,
stall => wire_gnd,
q => active_b_core_out
);
active_b_core <= (active_b_core_out(0) = '1');
-- ------ A input registers
-- write enable
we_a_reg_in(0) <= '0' WHEN mode_is_rom ELSE portawe;
we_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => we_a_reg_in,
clk => clk_a_wena,
aclr => we_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => we_a_reg_out,
aclrout => we_a_clr
);
we_a_reg <= we_a_reg_out(0);
-- read enable
re_a_reg_in(0) <= portare;
re_a_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => re_a_reg_in,
clk => clk_a_rena,
aclr => re_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => re_a_reg_out,
aclrout => re_a_clr
);
re_a_reg <= re_a_reg_out(0);
-- address
addr_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_address_width )
PORT MAP (
d => portaaddr,
clk => clk_a_in,
aclr => addr_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portaaddrstall,
ena => active_a_in,
q => addr_a_reg,
aclrout => addr_a_clr
);
-- data
datain_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => portadatain,
clk => clk_a_in,
aclr => datain_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => datain_a_reg,
aclrout => datain_a_clr
);
-- byte enable
byteena_a_register : cycloneiii_ram_register
GENERIC MAP (
width => port_a_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portabyteenamasks,
clk => clk_a_byteena,
aclr => byteena_a_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_a_in,
q => byteena_a_reg,
aclrout => byteena_a_clr
);
-- ------ B input registers
-- read enable
re_b_reg_in(0) <= portbre;
re_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => re_b_reg_in,
clk => clk_b_in,
aclr => re_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => re_b_reg_out,
aclrout => re_b_clr
);
re_b_reg <= re_b_reg_out(0);
-- write enable
we_b_reg_in(0) <= portbwe;
we_b_register : cycloneiii_ram_register
GENERIC MAP (
width => 1
)
PORT MAP (
d => we_b_reg_in,
clk => clk_b_in,
aclr => we_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => we_b_reg_out,
aclrout => we_b_clr
);
we_b_reg <= we_b_reg_out(0);
-- address
addr_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_address_width )
PORT MAP (
d => portbaddr,
clk => clk_b_in,
aclr => addr_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => portbaddrstall,
ena => active_b_in,
q => addr_b_reg,
aclrout => addr_b_clr
);
-- data
datain_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => portbdatain,
clk => clk_b_in,
aclr => datain_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => datain_b_reg,
aclrout => datain_b_clr
);
-- byte enable
byteena_b_register : cycloneiii_ram_register
GENERIC MAP (
width => port_b_byte_enable_mask_width,
preset => '1'
)
PORT MAP (
d => portbbyteenamasks,
clk => clk_b_byteena,
aclr => byteena_b_clr_in,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => active_b_in,
q => byteena_b_reg,
aclrout => byteena_b_clr
);
datain_prime_reg <= datain_a_reg WHEN primary_port_is_a ELSE datain_b_reg;
addr_prime_reg <= alt_conv_integer(addr_a_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_b_reg);
datain_sec_reg <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
datain_b_reg WHEN primary_port_is_a ELSE datain_a_reg;
addr_sec_reg <= alt_conv_integer(addr_b_reg) WHEN primary_port_is_a ELSE alt_conv_integer(addr_a_reg);
-- Write pulse generation
wpgen_a_clk <= clk_a_in;
wpgen_a_clkena <= '1' WHEN (active_a_core AND active_write_a AND (we_a_reg = '1')) ELSE '0';
wpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_a_clk,
ena => wpgen_a_clkena,
delaywrite => delay_write_pulse_a,
pulse => write_pulse(primary_port_is_a),
cycle => write_cycle_a
);
wpgen_b_clk <= clk_b_in;
wpgen_b_clkena <= '1' WHEN (active_b_core AND active_write_b AND mode_is_bdp AND (we_b_reg = '1')) ELSE '0';
wpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => wpgen_b_clk,
ena => wpgen_b_clkena,
delaywrite => delay_write_pulse_b,
pulse => write_pulse(primary_port_is_b),
cycle => write_cycle_b
);
-- Read pulse generation
rpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '0') AND (dataout_a_clr = '0')) ELSE '0';
rpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rpgen_a_clkena,
cycle => clk_a_core,
pulse => read_pulse(primary_port_is_a)
);
rpgen_b_clkena <= '1' WHEN ((mode_is_dp OR mode_is_bdp) AND active_b_core AND (re_b_reg = '1') AND (we_b_reg = '0') AND (dataout_b_clr = '0')) ELSE '0';
rpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rpgen_b_clkena,
cycle => clk_b_core,
pulse => read_pulse(primary_port_is_b)
);
-- Read-during-Write pulse generation
rwpgen_a_clkena <= '1' WHEN (active_a_core AND (re_a_reg = '1') AND (we_a_reg = '1') AND read_before_write_a AND (dataout_a_clr = '0')) ELSE '0';
rwpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => rwpgen_a_clkena,
pulse => rw_pulse(primary_port_is_a)
);
rwpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (re_b_reg = '1') AND (we_b_reg = '1') AND read_before_write_b AND (dataout_b_clr = '0')) ELSE '0';
rwpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => rwpgen_b_clkena,
pulse => rw_pulse(primary_port_is_b)
);
-- Create internal masks for byte enable processing
mask_create : PROCESS (byteena_a_reg,byteena_b_reg)
VARIABLE mask : mask_rec;
BEGIN
IF (byteena_a_reg'EVENT) THEN
mask := get_mask(byteena_a_reg,primary_port_is_a,port_a_byte_enable_mask_width,byte_size_a);
IF (primary_port_is_a) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
IF (byteena_b_reg'EVENT) THEN
mask := get_mask(byteena_b_reg,primary_port_is_b,port_b_byte_enable_mask_width,byte_size_b);
IF (primary_port_is_b) THEN
mask_vector.prime <= mask.prime;
ELSE
mask_vector.sec <= mask.sec;
END IF;
END IF;
END PROCESS mask_create;
-- (row,col) coordinates
row_sec <= addr_sec_reg / num_cols;
col_sec <= addr_sec_reg mod num_cols;
mem_rw : PROCESS (init_mem,
write_pulse,read_pulse,read_pulse_feedthru,
rw_pulse,
dataout_a_clr, dataout_b_clr,
mem_invalidate,mem_invalidate_loc,read_latch_invalidate)
-- mem init
TYPE rw_type IS ARRAY (port_type'HIGH DOWNTO port_type'LOW) OF BOOLEAN;
VARIABLE addr_range_init,row,col,index : INTEGER;
VARIABLE mem_init_std : STD_LOGIC_VECTOR((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
VARIABLE mem_init : bit_vector(mem_init4'length + mem_init3'length + mem_init2'length + mem_init1'length + mem_init0'length - 1 DOWNTO 0);
VARIABLE mem_val : mem_type;
-- read/write
VARIABLE mem_data_p : mem_row_type;
VARIABLE old_mem_data_p : mem_row_type;
VARIABLE row_prime,col_prime : INTEGER;
VARIABLE access_same_location : BOOLEAN;
VARIABLE read_during_write : rw_type;
BEGIN
-- Latch Clear
IF (dataout_a_clr'EVENT AND dataout_a_clr = '1') THEN
IF (primary_port_is_a) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
IF (dataout_b_clr'EVENT AND dataout_b_clr = '1') THEN
IF (primary_port_is_b) THEN
read_latch.prime <= (OTHERS => (OTHERS => '0'));
dataout_prime <= (OTHERS => '0');
ELSE
read_latch.sec <= (OTHERS => '0');
dataout_sec <= (OTHERS => '0');
END IF;
END IF;
read_during_write := (FALSE,FALSE);
-- Memory initialization
IF (init_mem'EVENT) THEN
-- Initialize output latches to 0
IF (primary_port_is_a) THEN
dataout_prime <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_sec <= (OTHERS => '0'); END IF;
ELSE
dataout_sec <= (OTHERS => '0');
IF (mode_is_dp OR mode_is_bdp) THEN dataout_prime <= (OTHERS => '0'); END IF;
END IF;
IF (power_up_uninitialized = "false" AND (NOT ram_type)) THEN
mem_val := (OTHERS => (OTHERS => (OTHERS => '0')));
END IF;
IF (primary_port_is_a) THEN
addr_range_init := port_a_last_address - port_a_first_address + 1;
ELSE
addr_range_init := port_b_last_address - port_b_first_address + 1;
END IF;
IF (init_file_layout = "port_a" OR init_file_layout = "port_b") THEN
mem_init := mem_init4 & mem_init3 & mem_init2 & mem_init1 & mem_init0;
mem_init_std := to_stdlogicvector(mem_init) ((port_a_last_address - port_a_first_address + 1)*port_a_data_width - 1 DOWNTO 0);
FOR row IN 0 TO addr_range_init - 1 LOOP
FOR col IN 0 to num_cols - 1 LOOP
index := row * data_width;
mem_val(row)(col) := mem_init_std(index + (col+1)*data_unit_width -1 DOWNTO
index + col*data_unit_width);
END LOOP;
END LOOP;
END IF;
mem <= mem_val;
END IF;
access_same_location := (mode_is_dp OR mode_is_bdp) AND (addr_prime_reg = row_sec);
-- Read before Write stage 1 : read data from memory
-- Read before Write stage 2 : send data to output
IF (rw_pulse(primary)'EVENT) THEN
IF (rw_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
ELSE
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = 'X') THEN
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END IF;
END LOOP;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
END IF;
IF (rw_pulse(secondary)'EVENT) THEN
IF (rw_pulse(secondary) = '1') THEN
read_latch.sec <= mem(row_sec)(col_sec);
ELSE
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = 'X') THEN
dataout_sec(i) <= read_latch.sec(i);
END IF;
END LOOP;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
END IF;
-- Write stage 1 : X to buffer
-- Write stage 2 : actual data to memory
IF (write_pulse(primary)'EVENT) THEN
IF (write_pulse(primary) = '1') THEN
old_mem_data_p := mem(addr_prime_reg);
mem_data_p := mem(addr_prime_reg);
FOR i IN 0 TO num_cols - 1 LOOP
mem_data_p(i) := mem_data_p(i) XOR
mask_vector.prime(inverse)((i + 1)*data_unit_width - 1 DOWNTO i*data_unit_width);
END LOOP;
read_during_write(secondary) := (access_same_location AND read_pulse(secondary)'EVENT AND read_pulse(secondary) = '1');
IF (read_during_write(secondary)) THEN
read_latch.sec <= old_mem_data_p(col_sec);
ELSE
mem_data <= mem_data_p;
END IF;
ELSIF (clear_asserted_during_write(primary) /= '1') THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= datain_prime_reg(i);
ELSIF (mask_vector.prime(inverse)(i) = 'X') THEN
mem(addr_prime_reg)(i / data_unit_width)(i mod data_unit_width) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
IF (write_pulse(secondary)'EVENT) THEN
IF (write_pulse(secondary) = '1') THEN
read_during_write(primary) := (access_same_location AND read_pulse(primary)'EVENT AND read_pulse(primary) = '1');
IF (read_during_write(primary)) THEN
read_latch.prime <= mem(addr_prime_reg);
read_latch.prime(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
ELSE
mem_unit_data <= mem(row_sec)(col_sec) XOR mask_vector.sec(inverse);
END IF;
IF (access_same_location AND write_pulse(primary)'EVENT AND write_pulse(primary) = '1') THEN
mask_vector_common <=
mask_vector.prime(inverse)(((col_sec + 1)* data_unit_width - 1) DOWNTO col_sec*data_unit_width) AND
mask_vector.sec(inverse);
dual_write <= TRUE;
END IF;
ELSIF (clear_asserted_during_write(secondary) /= '1') THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
mem(row_sec)(col_sec)(i) <= datain_sec_reg(i);
ELSIF (mask_vector.sec(inverse)(i) = 'X') THEN
mem(row_sec)(col_sec)(i) <= 'X';
END IF;
END LOOP;
END IF;
END IF;
-- Simultaneous write
IF (dual_write AND write_pulse = "00") THEN
mem(row_sec)(col_sec) <= mem(row_sec)(col_sec) XOR mask_vector_common;
dual_write <= FALSE;
END IF;
-- Read stage 1 : read data
-- Read stage 2 : send data to output
IF ((NOT read_during_write(primary)) AND read_pulse(primary)'EVENT) THEN
IF (read_pulse(primary) = '1') THEN
read_latch.prime <= mem(addr_prime_reg);
IF (access_same_location AND write_pulse(secondary) = '1') THEN
read_latch.prime(col_sec) <= mem_unit_data;
END IF;
ELSE
FOR i IN 0 TO data_width - 1 LOOP
row_prime := i / data_unit_width; col_prime := i mod data_unit_width;
dataout_prime(i) <= read_latch.prime(row_prime)(col_prime);
END LOOP;
END IF;
END IF;
IF ((NOT read_during_write(secondary)) AND read_pulse(secondary)'EVENT) THEN
IF (read_pulse(secondary) = '1') THEN
IF (access_same_location AND write_pulse(primary) = '1') THEN
read_latch.sec <= mem_data(col_sec);
ELSE
read_latch.sec <= mem(row_sec)(col_sec);
END IF;
ELSE
dataout_sec <= read_latch.sec;
END IF;
END IF;
-- Same port feed thru
IF (read_pulse_feedthru(primary)'EVENT AND read_pulse_feedthru(primary) = '0') THEN
IF (be_mask_write(primary)) THEN
FOR i IN 0 TO data_width - 1 LOOP
IF (mask_vector.prime(normal)(i) = '0') THEN
dataout_prime(i) <= datain_prime_reg(i);
END IF;
END LOOP;
ELSE
dataout_prime <= datain_prime_reg XOR mask_vector.prime(normal);
END IF;
END IF;
IF (read_pulse_feedthru(secondary)'EVENT AND read_pulse_feedthru(secondary) = '0') THEN
IF (be_mask_write(secondary)) THEN
FOR i IN 0 TO data_unit_width - 1 LOOP
IF (mask_vector.sec(normal)(i) = '0') THEN
dataout_sec(i) <= datain_sec_reg(i);
END IF;
END LOOP;
ELSE
dataout_sec <= datain_sec_reg XOR mask_vector.sec(normal);
END IF;
END IF;
-- Async clear
IF (mem_invalidate'EVENT) THEN
IF (mem_invalidate(primary) = TRUE OR mem_invalidate(secondary) = TRUE) THEN
mem <= mem_x;
END IF;
END IF;
IF (mem_invalidate_loc'EVENT) THEN
IF (mem_invalidate_loc(primary)) THEN mem(addr_prime_reg) <= row_x; END IF;
IF (mem_invalidate_loc(secondary)) THEN mem(row_sec)(col_sec) <= col_x; END IF;
END IF;
IF (read_latch_invalidate'EVENT) THEN
IF (read_latch_invalidate(primary)) THEN
read_latch.prime <= row_x;
END IF;
IF (read_latch_invalidate(secondary)) THEN
read_latch.sec <= col_x;
END IF;
END IF;
END PROCESS mem_rw;
-- Same port feed through
ftpgen_a_clkena <= '1' WHEN (active_a_core AND (NOT mode_is_dp) AND (NOT old_data_write_a) AND (we_a_reg = '1') AND (re_a_reg = '1') AND (dataout_a_clr = '0')) ELSE '0';
ftpgen_a : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_a_in,
ena => ftpgen_a_clkena,
pulse => read_pulse_feedthru(primary_port_is_a)
);
ftpgen_b_clkena <= '1' WHEN (active_b_core AND mode_is_bdp AND (NOT old_data_write_b) AND (we_b_reg = '1') AND (re_b_reg = '1') AND (dataout_b_clr = '0')) ELSE '0';
ftpgen_b : cycloneiii_ram_pulse_generator
PORT MAP (
clk => clk_b_in,
ena => ftpgen_b_clkena,
pulse => read_pulse_feedthru(primary_port_is_b)
);
-- Asynch clear events
clear_a : PROCESS(addr_a_clr,we_a_clr,datain_a_clr)
BEGIN
IF (addr_a_clr'EVENT AND addr_a_clr = '1') THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF (active_a_core AND re_a_reg = '1' AND dataout_a_clr = '0' AND dataout_a_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_a_clr'EVENT AND we_a_clr = '1') OR (datain_a_clr'EVENT AND datain_a_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_a) <= write_pulse(primary_port_is_a);
IF (active_write_a AND (write_cycle_a = '1') AND (we_a_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_a) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_a;
clear_b : PROCESS(addr_b_clr,we_b_clr,datain_b_clr)
BEGIN
IF (addr_b_clr'EVENT AND addr_b_clr = '1') THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
ELSIF ((mode_is_dp OR mode_is_bdp) AND active_b_core AND re_b_reg = '1' AND dataout_b_clr = '0' AND dataout_b_clr_reg_latch = '0') THEN
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
IF ((we_b_clr'EVENT AND we_b_clr = '1') OR (datain_b_clr'EVENT AND datain_b_clr = '1')) THEN
clear_asserted_during_write(primary_port_is_b) <= write_pulse(primary_port_is_b);
IF (mode_is_bdp AND active_write_b AND (write_cycle_b = '1') AND (we_b_reg = '1')) THEN
mem_invalidate_loc(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
read_latch_invalidate(primary_port_is_b) <= TRUE,FALSE AFTER 0.5 ns;
END IF;
END IF;
END PROCESS clear_b;
-- Clear mux registers (Latch Clear)
-- Port A output register clear
dataout_a_clr_reg_latch_in(0) <= dataout_a_clr;
aclr_a_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_a_clr_reg_latch_in,
clk => clk_a_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_a_clr_reg_latch_out
);
dataout_a_clr_reg_latch <= dataout_a_clr_reg_latch_out(0);
-- Port B output register clear
dataout_b_clr_reg_latch_in(0) <= dataout_b_clr;
aclr_b_mux_register : cycloneiii_ram_register
GENERIC MAP ( width => 1 )
PORT MAP (
d => dataout_b_clr_reg_latch_in,
clk => clk_b_core,
aclr => wire_gnd,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => wire_vcc,
q => dataout_b_clr_reg_latch_out
);
dataout_b_clr_reg_latch <= dataout_b_clr_reg_latch_out(0);
-- ------ Output registers
clkena_out_c0 <= '1' WHEN (clk0_output_clock_enable = "none") ELSE ena0;
clkena_out_c1 <= '1' WHEN (clk1_output_clock_enable = "none") ELSE ena1;
clkena_a_out <= clkena_out_c0 WHEN (port_a_data_out_clock = "clock0") ELSE clkena_out_c1;
clkena_b_out <= clkena_out_c0 WHEN (port_b_data_out_clock = "clock0") ELSE clkena_out_c1;
dataout_a <= dataout_prime WHEN primary_port_is_a ELSE dataout_sec;
dataout_b <= (OTHERS => 'U') WHEN (mode_is_rom OR mode_is_sp) ELSE
dataout_prime WHEN primary_port_is_b ELSE dataout_sec;
dataout_a_register : cycloneiii_ram_register
GENERIC MAP ( width => port_a_data_width )
PORT MAP (
d => dataout_a,
clk => clk_a_out,
aclr => dataout_a_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_a_out,
q => dataout_a_reg
);
dataout_b_register : cycloneiii_ram_register
GENERIC MAP ( width => port_b_data_width )
PORT MAP (
d => dataout_b,
clk => clk_b_out,
aclr => dataout_b_clr_reg,
devclrn => devclrn,
devpor => devpor,
stall => wire_gnd,
ena => clkena_b_out,
q => dataout_b_reg
);
portadataout <= dataout_a_reg WHEN out_a_is_reg ELSE dataout_a;
portbdataout <= dataout_b_reg WHEN out_b_is_reg ELSE dataout_b;
END block_arch;
-----------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_data_reg
--
-- Description : Simulation model for the data input register of
-- Cyclone II MAC_MULT
--
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_data_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END cycloneiii_mac_data_reg;
ARCHITECTURE vital_cuda_mac_data_reg OF cycloneiii_mac_data_reg IS
SIGNAL data_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL aclr_ipd : std_logic;
SIGNAL clk_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
SIGNAL dataout_tmp : std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in data'range generate
VitalWireDelay (data_ipd(i), data(i), tipd_data(i));
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
process (clk_ipd, aclr_ipd, data_ipd)
begin
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= data_ipd;
end if;
end process;
sh: block
begin
g0 : for i in data'range generate
process (data_ipd(i),clk_ipd,ena_ipd)
variable Tviol_data_clk : std_ulogic := '0';
variable TimingData_data_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_data_clk,
TimingData => TimingData_data_clk,
TestSignal => data_ipd(i),
TestSignalName => "DATA(i)",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_data_clk_noedge_posedge(i),
SetupLow => tsetup_data_clk_noedge_posedge(i),
HoldHigh => thold_data_clk_noedge_posedge(i),
HoldLow => thold_data_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena_ipd,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout_tmp'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn);
end process;
end generate;
end block;
END vital_cuda_mac_data_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_sign_reg
--
-- Description : Simulation model for the sign input register of
-- Cyclone II MAC_MULT
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_sign_reg IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END cycloneiii_mac_sign_reg;
ARCHITECTURE cycloneiii_mac_sign_reg OF cycloneiii_mac_sign_reg IS
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
signal aclr_ipd : std_logic;
signal ena_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process (clk_ipd, aclr_ipd)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01(aclr) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/SIGN_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (aclr_ipd = '1') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE),
1 => (aclr_ipd'last_event, tpd_aclr_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
END cycloneiii_mac_sign_reg;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult_internal
--
-- Description : Cyclone II MAC_MULT_INTERNAL VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_mult_internal IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END cycloneiii_mac_mult_internal;
ARCHITECTURE vital_cuda_mac_mult_internal OF cycloneiii_mac_mult_internal IS
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL signa_ipd : std_logic;
SIGNAL signb_ipd : std_logic;
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
end generate;
g2 : for i in datab'range generate
VitalWireDelay (datab_ipd(i), datab(i), tipd_datab(i));
end generate;
VitalWireDelay (signa_ipd, signa, tipd_signa);
VitalWireDelay (signb_ipd, signb, tipd_signb);
end block;
VITALtiming : process(dataa_ipd, datab_ipd, signa_ipd, signb_ipd)
begin
if((signa_ipd = '0') and (signb_ipd = '1')) then
dataout_tmp <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '0')) then
dataout_tmp <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
elsif((signa_ipd = '1') and (signb_ipd = '1')) then
dataout_tmp(dataout'range) <=
signed(dataa_ipd(dataa_width-1 downto 0)) *
signed(datab_ipd(datab_width-1 downto 0));
else --((signa_ipd = '0') and (signb_ipd = '0')) then
dataout_tmp(dataout'range) <=
unsigned(dataa_ipd(dataa_width-1 downto 0)) *
unsigned(datab_ipd(datab_width-1 downto 0));
end if;
end process;
----------------------
-- Path Delay Section
----------------------
PathDelay : block
begin
g1 : for i in dataout'range generate
VITALtiming : process (dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (OutSignal => dataout(i),
OutSignalName => "dataout",
OutTemp => dataout_tmp(i),
Paths => (0 => (dataa_ipd'last_event, tpd_dataa_dataout(i), TRUE),
1 => (datab_ipd'last_event, tpd_datab_dataout(i), TRUE),
2 => (signa'last_event, tpd_signa_dataout(i), TRUE),
3 => (signb'last_event, tpd_signb_dataout(i), TRUE)),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
MsgOn => FALSE,
XOn => TRUE );
end process;
end generate;
end block;
END vital_cuda_mac_mult_internal;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_mult
--
-- Description : Cyclone II MAC_MULT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.cycloneiii_atom_pack.all;
USE work.cycloneiii_mac_data_reg;
USE work.cycloneiii_mac_sign_reg;
USE work.cycloneiii_mac_mult_internal;
ENTITY cycloneiii_mac_mult IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_mult"
);
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '0';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_mult;
ARCHITECTURE vital_cuda_mac_mult OF cycloneiii_mac_mult IS
COMPONENT cycloneiii_mac_data_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_data : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tsetup_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_data_clk_noedge_posedge : VitalDelayArrayType(17 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_aclr_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
tpd_clk_dataout_posedge : VitalDelayArrayType01(17 downto 0) := (OTHERS => DefPropDelay01);
data_width : integer := 18
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
data : IN std_logic_vector(17 DOWNTO 0);
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
dataout : OUT std_logic_vector(17 DOWNTO 0)
);
END COMPONENT;
COMPONENT cycloneiii_mac_sign_reg
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
-- INPUT PORTS
clk : IN std_logic;
d : IN std_logic;
ena : IN std_logic;
aclr : IN std_logic;
-- OUTPUT PORTS
q : OUT std_logic
);
END COMPONENT;
COMPONENT cycloneiii_mac_mult_internal
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_datab : VitalDelayArrayType01(17 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_signa : VitalDelayType01 := DefPropDelay01;
tipd_signb : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_datab_dataout : VitalDelayArrayType01(18*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_signa_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_signb_dataout : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
dataa_width : integer := 18;
datab_width : integer := 18
);
PORT (
dataa : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
datab : IN std_logic_vector(17 DOWNTO 0) := (OTHERS => '0');
signa : IN std_logic := '1';
signb : IN std_logic := '1';
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0)
);
END COMPONENT;
-- Internal variables
SIGNAL dataa_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL datab_ipd : std_logic_vector(17 DOWNTO 0);
SIGNAL idataa_reg : std_logic_vector(17 DOWNTO 0); -- optional register for dataa input
SIGNAL idatab_reg : std_logic_vector(17 DOWNTO 0); -- optional register for datab input
SIGNAL isigna_reg : std_logic; -- optional register for signa input
SIGNAL isignb_reg : std_logic; -- optional register for signb input
SIGNAL idataa_int : std_logic_vector(17 DOWNTO 0); -- dataa as seen by the multiplier input
SIGNAL idatab_int : std_logic_vector(17 DOWNTO 0); -- datab as seen by the multiplier input
SIGNAL isigna_int : std_logic; -- signa as seen by the multiplier input
SIGNAL isignb_int : std_logic; -- signb as seen by the multiplier input
-- padding with 1's for input negation
SIGNAL reg_aclr : std_logic;
SIGNAL dataout_tmp : STD_LOGIC_VECTOR (dataa_width + datab_width downto 0) := (others => '0');
BEGIN
---------------------
-- INPUT PATH DELAYs
---------------------
reg_aclr <= (NOT devpor) OR (NOT devclrn) OR (aclr) ;
-- padding input data to full bus width
dataa_ipd(dataa_width-1 downto 0) <= dataa;
datab_ipd(datab_width-1 downto 0) <= datab;
-- Optional input registers for dataa,b and signa,b
dataa_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => dataa_width)
PORT MAP (
clk => clk,
data => dataa_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idataa_reg);
datab_reg : cycloneiii_mac_data_reg
GENERIC MAP (
data_width => datab_width)
PORT MAP (
clk => clk,
data => datab_ipd,
ena => ena,
aclr => reg_aclr,
dataout => idatab_reg);
signa_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signa,
ena => ena,
aclr => reg_aclr,
q => isigna_reg);
signb_reg : cycloneiii_mac_sign_reg
PORT MAP (
clk => clk,
d => signb,
ena => ena,
aclr => reg_aclr,
q => isignb_reg);
idataa_int <= dataa_ipd WHEN (dataa_clock = "none") ELSE idataa_reg;
idatab_int <= datab_ipd WHEN (datab_clock = "none") ELSE idatab_reg;
isigna_int <= signa WHEN (signa_clock = "none") ELSE isigna_reg;
isignb_int <= signb WHEN (signb_clock = "none") ELSE isignb_reg;
mac_multiply : cycloneiii_mac_mult_internal
GENERIC MAP (
dataa_width => dataa_width,
datab_width => datab_width
)
PORT MAP (
dataa => idataa_int,
datab => idatab_int,
signa => isigna_int,
signb => isignb_int,
dataout => dataout
);
END vital_cuda_mac_mult;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_mac_out
--
-- Description : Cyclone II MAC_OUT VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.VITAL_Primitives.all;
USE IEEE.VITAL_Timing.all;
USE IEEE.std_logic_1164.all;
USE work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_mac_out IS
GENERIC (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_dataa : VitalDelayArrayType01(35 downto 0)
:= (OTHERS => DefPropDelay01);
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tpd_dataa_dataout :VitalDelayArrayType01(36*36 -1 downto 0) :=(others => DefPropDelay01);
tpd_aclr_dataout_posedge : VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tpd_clk_dataout_posedge :VitalDelayArrayType01(35 downto 0) :=(others => DefPropDelay01);
tsetup_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_dataa_clk_noedge_posedge : VitalDelayArrayType(35 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
dataa_width : integer := 1;
output_clock : string := "none";
lpm_hint : string := "true";
lpm_type : string := "cycloneiii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (OTHERS => '0');
clk : IN std_logic := '0';
aclr : IN std_logic := '0';
ena : IN std_logic := '1';
dataout : OUT std_logic_vector(dataa_width-1 DOWNTO 0);
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_mac_out;
ARCHITECTURE vital_cuda_mac_out OF cycloneiii_mac_out IS
-- internal variables
SIGNAL dataa_ipd : std_logic_vector(dataa'range);
SIGNAL clk_ipd : std_logic;
SIGNAL aclr_ipd : std_logic;
SIGNAL ena_ipd : std_logic;
-- optional register
SIGNAL use_reg : std_logic;
SIGNAL dataout_tmp : std_logic_vector(dataout'range) := (OTHERS => '0');
BEGIN
---------------------
-- PATH DELAYs
---------------------
WireDelay : block
begin
g1 : for i in dataa'range generate
VitalWireDelay (dataa_ipd(i), dataa(i), tipd_dataa(i));
VITALtiming : process (clk_ipd, aclr_ipd, dataout_tmp(i))
variable dataout_VitalGlitchData : VitalGlitchDataType;
begin
VitalPathDelay01 (
OutSignal => dataout(i),
OutSignalName => "DATAOUT",
OutTemp => dataout_tmp(i),
Paths => (0 => (clk_ipd'last_event, tpd_clk_dataout_posedge(i), use_reg = '1'),
1 => (aclr_ipd'last_event, tpd_aclr_dataout_posedge(i), use_reg = '1'),
2 => (dataa_ipd(i)'last_event, tpd_dataa_dataout(i), use_reg = '0')),
GlitchData => dataout_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end generate;
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (aclr_ipd, aclr, tipd_aclr);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
use_reg <= '1' WHEN (output_clock /= "none") ELSE '0';
sh: block
begin
g0 : for i in dataa'range generate
VITALtiming : process (clk_ipd, ena_ipd, dataa_ipd(i))
variable Tviol_dataa_clk : std_ulogic := '0';
variable TimingData_dataa_clk : VitalTimingDataType := VitalTimingDataInit;
variable Tviol_ena_clk : std_ulogic := '0';
variable TimingData_ena_clk : VitalTimingDataType := VitalTimingDataInit;
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_dataa_clk,
TimingData => TimingData_dataa_clk,
TestSignal => dataa(i),
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_dataa_clk_noedge_posedge(i),
SetupLow => tsetup_dataa_clk_noedge_posedge(i),
HoldHigh => thold_dataa_clk_noedge_posedge(i),
HoldLow => thold_dataa_clk_noedge_posedge(i),
CheckEnabled => TO_X01((aclr) OR (NOT use_reg) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
VitalSetupHoldCheck (
Violation => Tviol_ena_clk,
TimingData => TimingData_ena_clk,
TestSignal => ena,
TestSignalName => "ENA",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_ena_clk_noedge_posedge,
SetupLow => tsetup_ena_clk_noedge_posedge,
HoldHigh => thold_ena_clk_noedge_posedge,
HoldLow => thold_ena_clk_noedge_posedge,
CheckEnabled => TO_X01((aclr) OR
(NOT use_reg)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/MAC_DATA_REG",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
END PROCESS;
end generate g0;
end block;
process (clk_ipd, aclr_ipd,ena_ipd, dataa_ipd)
begin
if (use_reg = '0') then
dataout_tmp <= dataa_ipd;
else
if (aclr_ipd = '1') then
dataout_tmp <= (OTHERS => '0');
elsif (clk_ipd'event and clk_ipd = '1' and (ena_ipd = '1')) then
dataout_tmp <= dataa_ipd;
end if;
end if;
end process;
END vital_cuda_mac_out;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_ibuf
--
-- Description : Cyclone III IO Ibuf VHDL simulation model
--
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_ibuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_ibar : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_ibar_o : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
differential_mode : string := "false";
bus_hold : string := "false";
simulate_z_as : string := "Z";
lpm_type : string := "cycloneiii_io_ibuf"
);
PORT (
i : IN std_logic := '0';
ibar : IN std_logic := '0';
o : OUT std_logic
);
END cycloneiii_io_ibuf;
ARCHITECTURE arch OF cycloneiii_io_ibuf IS
SIGNAL i_ipd : std_logic := '0';
SIGNAL ibar_ipd : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL out_tmp : std_logic;
SIGNAL prev_value : std_logic := '0';
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (ibar_ipd, ibar, tipd_ibar);
end block;
PROCESS(i_ipd, ibar_ipd)
BEGIN
IF (differential_mode = "false") THEN
IF (i_ipd = '1') THEN
o_tmp <= '1';
prev_value <= '1';
ELSIF (i_ipd = '0') THEN
o_tmp <= '0';
prev_value <= '0';
ELSE
o_tmp <= i_ipd;
END IF;
ELSE
IF (( i_ipd = '0' ) and (ibar_ipd = '1')) then
o_tmp <= '0';
ELSIF (( i_ipd = '1' ) and (ibar_ipd = '0')) then
o_tmp <= '1';
ELSIF((( i_ipd = '1' ) and (ibar_ipd = '1')) or (( i_ipd = '0' ) and (ibar_ipd = '0')))then
o_tmp <= 'X';
ELSE
o_tmp <= 'X';
END IF;
END IF;
END PROCESS;
out_tmp <= prev_value when (bus_hold = "true") else
'Z' when((o_tmp = 'Z') AND (simulate_z_as = "Z")) else
'X' when((o_tmp = 'Z') AND (simulate_z_as = "X")) else
'1' when((o_tmp = 'Z') AND (simulate_z_as = "vcc")) else
'0' when((o_tmp = 'Z') AND (simulate_z_as = "gnd")) else
o_tmp;
----------------------
-- Path Delay Section
----------------------
PROCESS( out_tmp)
variable output_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => out_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (ibar_ipd'last_event, tpd_ibar_o, TRUE)),
GlitchData => output_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_io_obuf
--
-- Description : Cyclone III IO Obuf VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_io_obuf IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tipd_oe : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_oe_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
tpd_oe_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
open_drain_output : string := "false";
bus_hold : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
PORT (
i : IN std_logic := '0';
oe : IN std_logic := '1';
seriesterminationcontrol : IN std_logic_vector(15 DOWNTO 0) := (others => '0');
devoe : IN std_logic := '1';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_io_obuf;
ARCHITECTURE arch OF cycloneiii_io_obuf IS
--INTERNAL Signals
SIGNAL i_ipd : std_logic := '0';
SIGNAL oe_ipd : std_logic := '0';
SIGNAL out_tmp : std_logic := 'Z';
SIGNAL out_tmp_bar : std_logic;
SIGNAL prev_value : std_logic := '0';
SIGNAL o_tmp : std_logic;
SIGNAL obar_tmp : std_logic;
SIGNAL o_tmp1 : std_logic;
SIGNAL obar_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
VitalWireDelay (oe_ipd, oe, tipd_oe);
end block;
PROCESS( i_ipd, oe_ipd)
BEGIN
IF (oe_ipd = '1') THEN
IF (open_drain_output = "true") THEN
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
END IF;
ELSE
IF (i_ipd = '0') THEN
out_tmp <= '0';
out_tmp_bar <= '1';
prev_value <= '0';
ELSE
IF (i_ipd = '1') THEN
out_tmp <= '1';
out_tmp_bar <= '0';
prev_value <= '1';
ELSE
out_tmp <= i_ipd;
out_tmp_bar <= i_ipd;
END IF;
END IF;
END IF;
ELSE
IF (oe_ipd = '0') THEN
out_tmp <= 'Z';
out_tmp_bar <= 'Z';
ELSE
out_tmp <= 'X';
out_tmp_bar <= 'X';
END IF;
END IF;
END PROCESS;
o_tmp1 <= prev_value WHEN (bus_hold = "true") ELSE out_tmp;
obar_tmp1 <= NOT prev_value WHEN (bus_hold = "true") ELSE out_tmp_bar;
o_tmp <= o_tmp1 WHEN (devoe = '1') ELSE 'Z';
obar_tmp <= obar_tmp1 WHEN (devoe = '1') ELSE 'Z';
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE),
1 => (oe_ipd'last_event, tpd_oe_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE),
1 => (oe_ipd'last_event, tpd_oe_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_oe
--
-- Description : Cyclone III DDIO_OE VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_oe IS
generic(
tipd_oe : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
PORT (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_oe;
ARCHITECTURE arch OF cycloneiii_ddio_oe IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL oe_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
signal nclk : std_logic;
signal dataout_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (oe_ipd, oe, tipd_oe);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
nclk <= NOT clk_ipd;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
ddioreg_hi : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => oe_ipd,
clk => clk_ipd,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dffhi_tmp,
devpor => devpor,
devclrn => devclrn
);
--DDIO Low Register
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => dffhi_tmp,
clk => nclk,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
--registered output
or_gate : cycloneiii_mux21
port map (
A => dffhi_tmp,
B => dfflo_tmp,
S => dfflo_tmp,
MO => dataout
);
dfflo <= dfflo_tmp ;
dffhi <= dffhi_tmp ;
END arch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_latch
--
-- Description : Cyclone III latch VHDL simulation model
--
--
---------------------------------------------------------------------
Library ieee;
use ieee.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_latch is
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_latch";
tsetup_d_ena_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_latch : entity is TRUE;
end cycloneiii_latch;
architecture vital_latch of cycloneiii_latch is
attribute VITAL_LEVEL0 of vital_latch : architecture is TRUE;
signal d_ipd : std_logic;
signal d_dly : std_logic;
signal clr_ipd : std_logic;
signal pre_ipd : std_logic;
signal ena_ipd : std_logic;
begin
d_dly <= d_ipd;
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clr_ipd, clr, tipd_clr);
VitalWireDelay (pre_ipd, pre, tipd_pre);
VitalWireDelay (ena_ipd, ena, tipd_ena);
end block;
VITALtiming : process ( d_dly, clr_ipd, pre_ipd,ena_ipd)
variable Tviol_d_ena : std_ulogic := '0';
variable TimingData_d_ena : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable iq : std_logic := '0';
variable idata: std_logic := '0';
-- variables for 'X' generation
variable violation : std_logic := '0';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_ena,
TimingData => TimingData_d_ena,
TestSignal => d_ipd,
TestSignalName => "DATAIN",
RefSignal => ena_ipd,
RefSignalName => "ENA",
SetupHigh => tsetup_d_ena_noedge_posedge,
SetupLow => tsetup_d_ena_noedge_posedge,
HoldHigh => thold_d_ena_noedge_negedge,
HoldLow => thold_d_ena_noedge_negedge,
CheckEnabled => TRUE,
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_latch",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
violation := Tviol_d_ena;
if ( (clr_ipd = '0')) then
iq := '0';
elsif (pre_ipd = '0') then
iq := '1';
elsif (violation = 'X' and x_on_violation = "on") then
iq := 'X';
elsif (ena_ipd = '1') then
iq := d_dly;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => iq,
Paths => (0 => (clr_ipd'last_event, tpd_clr_q_negedge, TRUE),
1 => (pre_ipd'last_event, tpd_pre_q_negedge, TRUE),
2 => (ena_ipd'last_event, tpd_ena_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end vital_latch;
---------------------------------------------------------------------
--
-- Entity Name : cycloneiii_ddio_out
--
-- Description : Cyclone III DDIO_OUT VHDL simulation model
--
--
---------------------------------------------------------------------
LIBRARY IEEE;
LIBRARY altera;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use altera.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ddio_out IS
generic(
tipd_datainlo : VitalDelayType01 := DefPropDelay01;
tipd_datainhi : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_clkhi : VitalDelayType01 := DefPropDelay01;
tipd_clklo : VitalDelayType01 := DefPropDelay01;
tipd_muxsel : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_sreset : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
use_new_clocking_model : string := "false";
lpm_type : string := "cycloneiii_ddio_out"
);
PORT (
datainlo : IN std_logic := '0';
datainhi : IN std_logic := '0';
clk : IN std_logic := '0';
clkhi : IN std_logic := '0';
clklo : IN std_logic := '0';
muxsel : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic;
dfflo : OUT std_logic;
dffhi : OUT std_logic ;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END cycloneiii_ddio_out;
ARCHITECTURE arch OF cycloneiii_ddio_out IS
component cycloneiii_mux21
generic(
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
InstancePath: STRING := "*";
tpd_A_MO : VitalDelayType01 := DefPropDelay01;
tpd_B_MO : VitalDelayType01 := DefPropDelay01;
tpd_S_MO : VitalDelayType01 := DefPropDelay01;
tipd_A : VitalDelayType01 := DefPropDelay01;
tipd_B : VitalDelayType01 := DefPropDelay01;
tipd_S : VitalDelayType01 := DefPropDelay01
);
port (
A : in std_logic := '0';
B : in std_logic := '0';
S : in std_logic := '0';
MO : out std_logic
);
end component;
component dffeas
generic (
power_up : string := "DONT_CARE";
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "DFFEAS";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_asdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clrn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_prn_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_asdata_q: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_asdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_clrn : VitalDelayType01 := DefPropDelay01;
tipd_prn : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
d : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
clrn : in std_logic := '1';
prn : in std_logic := '1';
aload : in std_logic := '0';
asdata : in std_logic := '1';
sclr : in std_logic := '0';
sload : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
q : out std_logic
);
end component;
component cycloneiii_latch
generic(
is_wysiwyg : string := "false";
x_on_violation : string := "on";
lpm_type : string := "cycloneiii_latch";
tsetup_d_ena_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_ena_noedge_negedge : VitalDelayType := DefSetupHoldCnst;
tpd_d_q : VitalDelayType01 := DefPropDelay01;
tpd_ena_q_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clr_q_negedge : VitalDelayType01 := DefPropDelay01;
tpd_pre_q_negedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clr : VitalDelayType01 := DefPropDelay01;
tipd_pre : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port(
d : in std_logic := '0';
ena : in std_logic := '1';
clr : in std_logic := '1';
pre : in std_logic := '1';
q : out std_logic
);
end component;
--Internal Signals
SIGNAL datainlo_ipd : std_logic := '0';
SIGNAL datainhi_ipd : std_logic := '0';
SIGNAL clk_ipd : std_logic := '0';
SIGNAL clkhi_ipd : std_logic := '0';
SIGNAL clklo_ipd : std_logic := '0';
SIGNAL muxsel_ipd : std_logic := '0';
SIGNAL ena_ipd : std_logic := '0';
SIGNAL areset_ipd : std_logic := '0';
SIGNAL sreset_ipd : std_logic := '0';
SIGNAL ddioreg_aclr : std_logic;
SIGNAL ddioreg_prn : std_logic;
SIGNAL ddioreg_adatasdata : std_logic;
SIGNAL ddioreg_sclr : std_logic;
SIGNAL ddioreg_sload : std_logic;
SIGNAL dfflo_tmp : std_logic;
SIGNAL dffhi_tmp : std_logic;
SIGNAL dataout_tmp : std_logic;
Signal mux_sel : std_logic;
Signal mux_hi : std_logic;
Signal sel_mux_hi_in : std_logic;
signal clk1 : std_logic;
signal clk_hi : std_logic;
signal clk_lo : std_logic;
signal muxsel1 : std_logic;
signal muxsel2: std_logic;
signal clk2 : std_logic;
signal muxsel_tmp: std_logic;
signal sel_mux_lo_in : std_logic;
signal datainlo_tmp : std_logic;
signal datainhi_tmp : std_logic;
signal dffhi_tmp1 : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (datainlo_ipd, datainlo, tipd_datainlo);
VitalWireDelay (datainhi_ipd, datainhi, tipd_datainhi);
VitalWireDelay (clk_ipd, clk, tipd_clk);
VitalWireDelay (clkhi_ipd, clkhi, tipd_clkhi);
VitalWireDelay (clklo_ipd, clklo, tipd_clklo);
VitalWireDelay (muxsel_ipd, muxsel, tipd_muxsel);
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (areset_ipd, areset, tipd_areset);
VitalWireDelay (sreset_ipd, sreset, tipd_sreset);
end block;
PROCESS
BEGIN
WAIT UNTIL areset_ipd'EVENT OR sreset_ipd'EVENT;
IF (async_mode = "clear") THEN
ddioreg_aclr <= NOT areset_ipd;
ddioreg_prn <= '1';
ELSIF (async_mode = "preset") THEN
ddioreg_aclr <= '1';
ddioreg_prn <= NOT areset_ipd;
ELSE
ddioreg_aclr <= '1';
ddioreg_prn <= '1';
END IF;
IF (sync_mode = "clear") THEN
ddioreg_adatasdata <= '0';
ddioreg_sclr <= sreset_ipd;
ddioreg_sload <= '0';
ELSIF (sync_mode = "preset") THEN
ddioreg_adatasdata <= '1';
ddioreg_sclr <= '0';
ddioreg_sload <= sreset_ipd;
ELSE
ddioreg_adatasdata <= '0';
ddioreg_sclr <= '0';
ddioreg_sload <= '0';
END IF;
END PROCESS;
process(clk_ipd)
begin
clk1 <= clk_ipd;
end process;
process(muxsel_ipd)
begin
muxsel1 <= muxsel_ipd;
end process;
process(dffhi_tmp)
begin
dffhi_tmp1 <= dffhi_tmp;
end process;
--DDIO HIGH Register
clk_hi <= ((NOT clkhi_ipd) and ena_ipd) when(use_new_clocking_model = "true") else ((NOT clk_ipd) and ena_ipd);
datainhi_tmp <= '1' when (ddioreg_sclr ='0'and ddioreg_sload = '1')else '0'when (ddioreg_sclr ='1'and ddioreg_sload = '0') else datainhi;
ddioreg_hi : cycloneiii_latch
PORT MAP (
d=> datainhi_tmp,
ena => clk_hi,
pre => ddioreg_prn,
clr => ddioreg_aclr,
q => dffhi_tmp
);
--DDIO Low Register
clk_lo <= clklo_ipd when(use_new_clocking_model = "true") else clk_ipd;
datainlo_tmp <= datainlo;
ddioreg_lo : dffeas
GENERIC MAP (
power_up => power_up
)
PORT MAP (
d => datainlo_tmp,
clk => clk_lo,
clrn => ddioreg_aclr,
prn => ddioreg_prn,
sclr => ddioreg_sclr,
sload => ddioreg_sload,
asdata => ddioreg_adatasdata,
ena => ena_ipd,
q => dfflo_tmp,
devpor => devpor,
devclrn => devclrn
);
muxsel2 <= muxsel1;
clk2 <= clk1;
mux_sel <= muxsel2 when(use_new_clocking_model = "true") else clk2;
muxsel_tmp <= NOT mux_sel;
sel_mux_lo_in <= dfflo_tmp;
sel_mux_hi_in <= dffhi_tmp1;
sel_mux : cycloneiii_mux21
port map (
A => sel_mux_hi_in,
B => sel_mux_lo_in,
S => muxsel_tmp,
MO => dataout
);
dfflo <= dfflo_tmp;
dffhi <= dffhi_tmp;
END arch;
----------------------------------------------------------------------------------
--Module Name: cycloneiii_pseudo_diff_out --
--Description: Simulation model for Cyclone III Pseudo Differential --
-- Output Buffer --
----------------------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_pseudo_diff_out IS
GENERIC (
tipd_i : VitalDelayType01 := DefPropDelay01;
tpd_i_o : VitalDelayType01 := DefPropDelay01;
tpd_i_obar : VitalDelayType01 := DefPropDelay01;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
lpm_type : string := "cycloneiii_pseudo_diff_out"
);
PORT (
i : IN std_logic := '0';
o : OUT std_logic;
obar : OUT std_logic
);
END cycloneiii_pseudo_diff_out;
ARCHITECTURE arch OF cycloneiii_pseudo_diff_out IS
SIGNAL i_ipd : std_logic ;
SIGNAL o_tmp : std_logic ;
SIGNAL obar_tmp : std_logic;
BEGIN
WireDelay : block
begin
VitalWireDelay (i_ipd, i, tipd_i);
end block;
PROCESS( i_ipd)
BEGIN
IF (i_ipd = '0') THEN
o_tmp <= '0';
obar_tmp <= '1';
ELSE
IF (i_ipd = '1') THEN
o_tmp <= '1';
obar_tmp <= '0';
ELSE
o_tmp <= i_ipd;
obar_tmp <= i_ipd;
END IF;
END IF;
END PROCESS;
---------------------
-- Path Delay Section
----------------------
PROCESS( o_tmp,obar_tmp)
variable o_VitalGlitchData : VitalGlitchDataType;
variable obar_VitalGlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01 (
OutSignal => o,
OutSignalName => "o",
OutTemp => o_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_o, TRUE)),
GlitchData => o_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
VitalPathDelay01 (
OutSignal => obar,
OutSignalName => "obar",
OutTemp => obar_tmp,
Paths => (0 => (i_ipd'last_event, tpd_i_obar, TRUE)),
GlitchData => obar_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn
);
END PROCESS;
END arch;
----------------------------------------------------------------------------
-- Module Name : cycloneiii_io_pad
-- Description : Simulation model for cycloneiii IO pad
----------------------------------------------------------------------------
LIBRARY IEEE;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
ENTITY cycloneiii_io_pad IS
GENERIC (
lpm_type : string := "cycloneiii_io_pad");
PORT (
--INPUT PORTS
padin : IN std_logic := '0'; -- Input Pad
--OUTPUT PORTS
padout : OUT std_logic); -- Output Pad
END cycloneiii_io_pad;
ARCHITECTURE arch OF cycloneiii_io_pad IS
BEGIN
padout <= padin;
END arch;
--/////////////////////////////////////////////////////////////////////////////
--
-- Entity Name : cycloneiii_ena_reg
--
-- Description : Simulation model for a simple DFF.
-- This is used for the gated clock generation
-- Powers upto 1.
--
--/////////////////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
ENTITY cycloneiii_ena_reg is
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_ena_reg : entity is TRUE;
end cycloneiii_ena_reg;
ARCHITECTURE behave of cycloneiii_ena_reg is
attribute VITAL_LEVEL0 of behave : architecture is TRUE;
signal d_ipd : std_logic;
signal clk_ipd : std_logic;
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (d_ipd, d, tipd_d);
VitalWireDelay (clk_ipd, clk, tipd_clk);
end block;
VITALtiming : process (clk_ipd, prn, clrn)
variable Tviol_d_clk : std_ulogic := '0';
variable TimingData_d_clk : VitalTimingDataType := VitalTimingDataInit;
variable q_VitalGlitchData : VitalGlitchDataType;
variable q_reg : std_logic := '1';
begin
------------------------
-- Timing Check Section
------------------------
if (TimingChecksOn) then
VitalSetupHoldCheck (
Violation => Tviol_d_clk,
TimingData => TimingData_d_clk,
TestSignal => d,
TestSignalName => "D",
RefSignal => clk_ipd,
RefSignalName => "CLK",
SetupHigh => tsetup_d_clk_noedge_posedge,
SetupLow => tsetup_d_clk_noedge_posedge,
HoldHigh => thold_d_clk_noedge_posedge,
HoldLow => thold_d_clk_noedge_posedge,
CheckEnabled => TO_X01((clrn) OR
(NOT ena)) /= '1',
RefTransition => '/',
HeaderMsg => InstancePath & "/cycloneiii_ena_reg",
XOn => XOnChecks,
MsgOn => MsgOnChecks );
end if;
if (prn = '0') then
q_reg := '1';
elsif (clrn = '0') then
q_reg := '0';
elsif (clk_ipd'event and clk_ipd = '1' and clk_ipd'last_value = '0' and (ena = '1')) then
q_reg := d_ipd;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => q,
OutSignalName => "Q",
OutTemp => q_reg,
Paths => (0 => (clk_ipd'last_event, tpd_clk_q_posedge, TRUE)),
GlitchData => q_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end behave;
--/////////////////////////////////////////////////////////////////////////////
--
-- VHDL Simulation Model for Cyclone III CLKCTRL Atom
--
--/////////////////////////////////////////////////////////////////////////////
--
--
-- CYCLONEII_CLKCTRL Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
use work.cycloneiii_ena_reg;
entity cycloneiii_clkctrl is
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "cycloneiii_clkctrl";
ena_register_mode : STRING := "Falling Edge";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
attribute VITAL_LEVEL0 of cycloneiii_clkctrl : entity is TRUE;
end cycloneiii_clkctrl;
architecture vital_clkctrl of cycloneiii_clkctrl is
attribute VITAL_LEVEL0 of vital_clkctrl : architecture is TRUE;
component cycloneiii_ena_reg
generic (
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tsetup_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_d_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_q_posedge : VitalDelayType01 := DefPropDelay01;
tipd_d : VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01
);
PORT (
clk : in std_logic;
ena : in std_logic := '1';
d : in std_logic;
clrn : in std_logic := '1';
prn : in std_logic := '1';
q : out std_logic
);
end component;
signal inclk_ipd : std_logic_vector(3 downto 0);
signal clkselect_ipd : std_logic_vector(1 downto 0);
signal ena_ipd : std_logic;
signal clkmux_out : std_logic;
signal clkmux_out_inv : std_logic;
signal cereg_clr : std_logic;
signal cereg1_out : std_logic;
signal cereg2_out : std_logic;
signal ena_out : std_logic;
signal vcc : std_logic := '1';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (ena_ipd, ena, tipd_ena);
VitalWireDelay (inclk_ipd(0), inclk(0), tipd_inclk(0));
VitalWireDelay (inclk_ipd(1), inclk(1), tipd_inclk(1));
VitalWireDelay (inclk_ipd(2), inclk(2), tipd_inclk(2));
VitalWireDelay (inclk_ipd(3), inclk(3), tipd_inclk(3));
VitalWireDelay (clkselect_ipd(0), clkselect(0), tipd_clkselect(0));
VitalWireDelay (clkselect_ipd(1), clkselect(1), tipd_clkselect(1));
end block;
process(inclk_ipd, clkselect_ipd)
variable tmp : std_logic;
begin
if (clkselect_ipd = "11") then
tmp := inclk_ipd(3);
elsif (clkselect_ipd = "10") then
tmp := inclk_ipd(2);
elsif (clkselect_ipd = "01") then
tmp := inclk_ipd(1);
else
tmp := inclk_ipd(0);
end if;
clkmux_out <= tmp;
clkmux_out_inv <= NOT tmp;
end process;
extena0_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => ena_ipd,
clrn => vcc,
prn => devpor,
q => cereg1_out
);
extena1_reg : cycloneiii_ena_reg
port map (
clk => clkmux_out_inv,
ena => vcc,
d => cereg1_out,
clrn => vcc,
prn => devpor,
q => cereg2_out
);
ena_out <= cereg1_out WHEN (ena_register_mode = "falling edge") ELSE
ena_ipd WHEN (ena_register_mode = "none") ELSE cereg2_out;
outclk <= ena_out AND clkmux_out;
end vital_clkctrl;
--
--
-- CYCLONEIII_RUBLOCK Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_rublock is
generic
(
sim_init_config : string := "factory";
sim_init_watchdog_value : integer := 0;
sim_init_status : integer := 0;
lpm_type : string := "cycloneiii_rublock"
);
port
(
clk : in std_logic;
shiftnld : in std_logic;
captnupdt : in std_logic;
regin : in std_logic;
rsttimer : in std_logic;
rconfig : in std_logic;
regout : out std_logic
);
end cycloneiii_rublock;
architecture architecture_rublock of cycloneiii_rublock is
begin
end architecture_rublock;
--
--
-- CYCLONEIII_APFCONTROLLER Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_apfcontroller is
generic
(
lpm_type: string := "cycloneiii_apfcontroller"
);
port
(
usermode : out std_logic; --REM_TARPON
nceout : out std_logic
);
end cycloneiii_apfcontroller;
architecture architecture_apfcontroller of cycloneiii_apfcontroller is
begin
end architecture_apfcontroller;
--------------------------------------------------------------------
--
-- Module Name : cycloneiii_termination
--
-- Description : Cyclone III Termination Atom VHDL simulation model
--
--------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY cycloneiii_termination IS
GENERIC (
pullup_control_to_core: string := "false";
power_down : string := "true";
test_mode : string := "false";
left_shift_termination_code : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
clock_divide_by : integer := 32; -- 1, 4, 32
runtime_control : string := "false";
shift_vref_rup : string := "true";
shift_vref_rdn : string := "true";
shifted_vref_control : string := "true";
lpm_type : string := "cycloneiii_termination");
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
devpor : IN std_logic := '1';
devclrn : IN std_logic := '1';
comparatorprobe : OUT std_logic;
terminationcontrolprobe : OUT std_logic;
calibrationdone : OUT std_logic;
terminationcontrol : OUT std_logic_vector(15 DOWNTO 0));
END cycloneiii_termination;
ARCHITECTURE cycloneiii_termination_arch OF cycloneiii_termination IS
SIGNAL rup_compout : std_logic := '0';
SIGNAL rdn_compout : std_logic := '1';
BEGIN
calibrationdone <= '1'; -- power-up calibration status
comparatorprobe <= rup_compout WHEN (pullup_control_to_core = "true") ELSE rdn_compout;
rup_compout <= rup;
rdn_compout <= not rdn;
END cycloneiii_termination_arch;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_jtag
--
-- Description : Cyclone III JTAG VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_jtag is
generic (
lpm_type : string := "cycloneiii_jtag"
);
port (
tms : in std_logic;
tck : in std_logic;
tdi : in std_logic;
tdoutap : in std_logic;
tdouser : in std_logic;
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
end cycloneiii_jtag;
architecture architecture_jtag of cycloneiii_jtag is
begin
end architecture_jtag;
-------------------------------------------------------------------
--
-- Entity Name : cycloneiii_crcblock
--
-- Description : Cyclone III CRCBLOCK VHDL Simulation model
--
-------------------------------------------------------------------
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_crcblock is
generic (
oscillator_divider : integer := 1;
lpm_type : string := "cycloneiii_crcblock"
);
port (
clk : in std_logic;
shiftnld : in std_logic;
ldsrc : in std_logic;
crcerror : out std_logic;
regout : out std_logic
);
end cycloneiii_crcblock;
architecture architecture_crcblock of cycloneiii_crcblock is
begin
end architecture_crcblock;
--
--
-- CYCLONEIII_OSCILLATOR Model
--
--
LIBRARY IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.VITAL_Timing.all;
use IEEE.VITAL_Primitives.all;
use work.cycloneiii_atom_pack.all;
entity cycloneiii_oscillator is
generic
(
lpm_type: string := "cycloneiii_oscillator";
TimingChecksOn: Boolean := True;
XOn: Boolean := DefGlitchXOn;
MsgOn: Boolean := DefGlitchMsgOn;
tpd_oscena_clkout_posedge : VitalDelayType01 := DefPropDelay01;
tipd_oscena : VitalDelayType01 := DefPropDelay01
);
port
(
oscena : in std_logic;
clkout : out std_logic
);
end cycloneiii_oscillator;
architecture architecture_oscillator of cycloneiii_oscillator is
signal oscena_ipd : std_logic;
signal int_osc : std_logic := '0';
begin
---------------------
-- INPUT PATH DELAYs
---------------------
WireDelay : block
begin
VitalWireDelay (oscena_ipd, oscena, tipd_oscena);
end block;
VITAL_osc : process(oscena_ipd, int_osc)
variable OSC_PW : time := 6250 ps; -- pulse width for 80MHz clock
variable osc_VitalGlitchData : VitalGlitchDataType;
begin
if (oscena_ipd = '1') then
if ((int_osc = '0') or (int_osc = '1')) then
int_osc <= not int_osc after OSC_PW;
else
int_osc <= '0' after OSC_PW;
end if;
end if;
----------------------
-- Path Delay Section
----------------------
VitalPathDelay01 (
OutSignal => clkout,
OutSignalName => "osc",
OutTemp => int_osc,
Paths => (0 => (InputChangeTime => oscena_ipd'last_event,
PathDelay => tpd_oscena_clkout_posedge,
PathCondition => (oscena_ipd = '1'))),
GlitchData => osc_VitalGlitchData,
Mode => DefGlitchMode,
XOn => XOn,
MsgOn => MsgOn );
end process;
end architecture_oscillator;
| gpl-2.0 | 8ebcdb11b0584d390639168bf1e002de | 0.453593 | 4.214105 | false | false | false | false |
khaledhassan/vhdl-examples | adders_1bit/half_adder_tb.vhd | 1 | 1,939 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Testbench for the half-adder.
library ieee;
use ieee.std_logic_1164.all;
entity half_adder_tb is
end half_adder_tb;
architecture TB of half_adder_tb is
signal a, b, sum, carry : std_logic;
begin
-- Instantiate the unit under test (UUT)
UUT : entity work.half_adder
port map (
a => a,
b => b,
sum => sum,
carry => carry
);
-- Stimulus process
process
begin
a <= '0';
b <= '0';
wait for 10 ns;
a <= '1';
b <= '0';
wait for 10 ns;
a <= '0';
b <= '1';
wait for 10 ns;
a <= '1';
b <= '1';
wait;
end process;
end TB;
| mit | 4b9ee312a4d3261f5827711dac32c28b | 0.646725 | 4.116773 | false | false | false | false |
hamsternz/Full_Stack_GPS_Receiver | misc/vhdl/top_level.vhd | 1 | 3,919 | --------------------------------------------
-- Author: Mike Field <[email protected]>
--------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top_level is
Port ( mclk : in STD_LOGIC;
gps_mag : in STD_LOGIC;
gps_sgn : in STD_LOGIC;
gps_clk : in STD_LOGIC;
led : OUT std_logic_vector(7 downto 0);
epp_astb : in STD_LOGIC;
epp_dstb : in STD_LOGIC;
epp_wait : out STD_LOGIC;
epp_wr : in STD_LOGIC;
epp_data : inout STD_LOGIC_VECTOR (7 downto 0));
end top_level;
architecture Behavioral of top_level is
signal clk_100 : std_logic;
component clocking is
port (
clk : in std_logic;
clk_100 : out std_logic);
end component;
component gps_capture is
port (
clk : in std_logic;
gps_mag : in std_logic;
gps_sgn : in std_logic;
gps_clk : in std_logic;
led : OUT std_logic_vector(7 downto 0);
fifo_data : out std_logic_vector(7 downto 0) := (others => '0');
fifo_we : out std_logic;
fifo_full : in std_logic;
fifo_empty : in std_logic;
overrun : out std_logic);
end component;
signal fifo_data_in : std_logic_vector(7 downto 0) := (others => '0');
signal fifo_we : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
component fifo_16k_x_8 is
port (
clk : in std_logic;
wr : in std_logic;
din : in std_logic_vector(7 downto 0) := (others => '0');
rd : in std_logic;
dout : out std_logic_vector(7 downto 0) := (others => '0');
full : out std_logic;
empty : out std_logic);
end component;
COMPONENT ip_fifo
PORT (
clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
signal fifo_data_out : std_logic_vector(7 downto 0) := (others => '0');
signal fifo_rd : std_logic;
component epp_interface is
port (
clk : in std_logic;
fifo_rd : out STD_LOGIC;
fifo_data : in STD_LOGIC_VECTOR(7 downto 0);
fifo_empty : in STD_LOGIC;
epp_astb : in STD_LOGIC;
epp_dstb : in STD_LOGIC;
epp_wait : out STD_LOGIC;
epp_wr : in STD_LOGIC;
epp_data : inout STD_LOGIC_VECTOR (7 downto 0));
end component;
signal gen_test_clk : std_logic_vector(3 downto 0) := "0011";
begin
i_clocking: clocking port map (
clk => mclk,
clk_100 => clk_100);
i_gps: gps_capture port map (
clk => clk_100,
gps_mag => gps_mag,
gps_sgn => gps_sgn,
gps_clk => gps_clk,
led => led,
fifo_data => fifo_data_in,
fifo_we => fifo_we,
fifo_full => fifo_full,
fifo_empty => fifo_empty,
overrun => open);
i_ip_fifo: ip_fifo port map (
clk => clk_100,
wr_en => fifo_we,
din => fifo_data_in,
rd_en => fifo_rd,
dout => fifo_data_out,
full => fifo_full,
empty => fifo_empty);
i_epp_interface: epp_interface port map (
clk => clk_100,
fifo_rd => fifo_rd,
fifo_data => fifo_data_out,
fifo_empty => fifo_empty,
epp_astb => epp_astb,
epp_dstb => epp_dstb,
epp_wait => epp_wait,
epp_wr => epp_wr,
epp_data => epp_data);
end Behavioral;
| mit | 9407bec4cbdc0e8a1e4b5e03cb784179 | 0.480225 | 3.434706 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-2/src/TestBench/var5/var5_TB.vhd | 1 | 2,089 | library ieee;
use ieee.std_logic_1164.all;
-- Add your library and packages declaration here ...
entity var5_tb is
end var5_tb;
architecture TB_ARCHITECTURE of var5_tb is
-- Component declaration of the tested unit
component var5
port(
W : in STD_LOGIC;
X : in STD_LOGIC;
Y : in STD_LOGIC;
Z : in STD_LOGIC;
F : out STD_LOGIC);
end component;
-- Stimulus signals - signals mapped to the input and inout ports of tested entity
signal W : STD_LOGIC;
signal X : STD_LOGIC;
signal Y : STD_LOGIC;
signal Z : STD_LOGIC;
-- Observed signals - signals mapped to the output ports of tested entity
signal F, F1 : STD_LOGIC;
signal error : std_logic;
-- Add your code here ...
begin
-- Unit Under Test port map
UUT : var5
port map (
W => W,
X => X,
Y => Y,
Z => Z,
F => F
);
UUT2 : var5
port map (
W => W,
X => X,
Y => Y,
Z => Z,
F => F1
);
--Below VHDL code is an inserted .\compile\task.vhs
--User can modify it ....
STIMULUS: process
begin -- of stimulus process
--wait for <time to next event>; -- <current time>
W <= '0';
Y <= '0';
Z <= '0';
X <= '0';
wait for 50 ns; --0 fs
X <= '1';
wait for 50 ns; --50 ns
Y <= '1';
X <= '0';
wait for 50 ns; --100 ns
X <= '1';
wait for 50 ns; --150 ns
Y <= '0';
Z <= '1';
X <= '0';
wait for 50 ns; --200 ns
X <= '1';
wait for 50 ns; --250 ns
Y <= '1';
X <= '0';
wait for 50 ns; --300 ns
X <= '1';
wait for 50 ns; --350 ns
W <= '1';
Y <= '0';
Z <= '0';
X <= '0';
wait for 50 ns; --400 ns
X <= '1';
wait for 50 ns; --450 ns
Y <= '1';
X <= '0';
wait for 50 ns; --500 ns
X <= '1';
wait for 50 ns; --550 ns
Y <= '0';
Z <= '1';
X <= '0';
wait for 50 ns; --600 ns
X <= '1';
wait for 50 ns; --650 ns
Y <= '1';
X <= '0';
wait for 50 ns; --700 ns
X <= '1';
wait for 50 ns; --750 ns
W <= '0';
Y <= '0';
Z <= '0';
X <= '0';
-- end of stimulus events 800 ns
wait;
end process; -- end of stimulus process
error <= F1 xor F;
-- Add your stimulus here ...
end TB_ARCHITECTURE;
| mit | e67b9b7a1d6c65bf2012c747cf12e085 | 0.531833 | 2.55379 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/proc3.vhd | 1 | 6,585 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: proc3
-- File: proc3.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: LEON3 processor core with pipeline, mul/div & cache control
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.arith.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity proc3 is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := 0;
memtech : integer range 0 to NTECH := 0;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 15 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 0;
svt : integer range 0 to 1 := 0;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
holdn : out std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
rfi : out iregfile_in_type;
rfo : in iregfile_out_type;
crami : out cram_in_type;
cramo : in cram_out_type;
tbi : out tracebuf_in_type;
tbo : in tracebuf_out_type;
fpi : out fpc_in_type;
fpo : in fpc_out_type;
cpi : out fpc_in_type;
cpo : in fpc_out_type;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of proc3 is
constant IRFWT : integer := 1; --regfile_3p_write_through(memtech);
signal ici : icache_in_type;
signal ico : icache_out_type;
signal dci : dcache_in_type;
signal dco : dcache_out_type;
signal holdnx, pholdn : std_logic;
signal muli : mul32_in_type;
signal mulo : mul32_out_type;
signal divi : div32_in_type;
signal divo : div32_out_type;
begin
holdnx <= ico.hold and dco.hold and fpo.holdn; holdn <= holdnx;
pholdn <= fpo.holdn;
-- integer unit
iu : iu3
generic map (nwindows, isets, dsets, fpu, v8, cp, mac, dsu, nwp, pclow,
notag, hindex, lddel, IRFWT, disas, tbuf, pwd, svt, rstaddr, smp, fabtech,
clk2x, bp)
port map (clk, rstn, holdnx, ici, ico, dci, dco, rfi, rfo, irqi, irqo,
dbgi, dbgo, muli, mulo, divi, divo, fpo, fpi, cpo, cpi, tbo, tbi, sclk);
-- multiply and divide units
mgen : if v8 /= 0 generate
mul0 : mul32 generic map (fabtech, v8/16, (v8 mod 4)/2, mac, (v8 mod 16)/4)
port map (rstn, clk, holdnx, muli, mulo);
div0 : div32 port map (rstn, clk, holdnx, divi, divo);
end generate;
nomgen : if v8 = 0 generate
divo <= ('0', '0', "0000", zero32);
mulo <= ('0', '0', "0000", zero32&zero32);
end generate;
-- cache controller
c0mmu : mmu_cache
generic map (
hindex, memtech, dsu, icen, irepl, isets, ilinesize, isetsize,
isetlock, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock,
dsnoop, ilram, ilramsize, ilramstart, dlram, dlramsize, dlramstart,
itlbnum, dtlbnum, tlb_type, tlb_rep, cached,
clk2x, scantest, mmupgsz, smp, mmuen)
port map (rstn, clk, ici, ico, dci, dco, ahbi, ahbo, ahbsi, ahbso,
crami, cramo, pholdn, hclk, sclk, hclken);
end;
| gpl-2.0 | d15a7c3a01f4e2cf81c007b4b5f28852 | 0.548823 | 3.598361 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Labs/POCP/POCP-4/src/TestBench/LFSR_out_t.vhd | 1 | 1,199 | library ieee;
use ieee.std_logic_1164.all;
entity LFSR_Out_T is
end LFSR_Out_T;
architecture Beh of LFSR_Out_T is
component LFSR_Out
port (
CLK: in std_logic;
RST: in std_logic;
LS: in std_logic;
Pin: in std_logic_vector(0 to 3);
Pout: out std_logic_vector(0 to 3)
);
end component;
signal CLK: std_logic := '0';
signal RST: std_logic := '0';
signal LS: std_logic := '0';
signal Pin: std_logic_vector(0 to 3) := (others => '0');
signal Pout: std_logic_vector(0 to 3);
constant CLK_Period: time := 10 ns;
begin
uut: LFSR_Out port map (
CLK => CLK,
RST => RST,
LS => LS,
PIn => Pin,
POut => POut
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
stim_proc: process
begin
wait for CLK_Period;
RST <= '0'; wait for CLK_Period;
RST <= '1'; wait for 2*CLK_Period;
RST <= '0'; wait for CLK_Period;
PIn <= "1011"; wait for CLK_Period;
LS <= '1'; wait for 8*CLK_period;
end process;
end Beh;
configuration TESTBENCH_FOR_lfsr_out of LFSR_OUT_T is
for Beh
for UUT : lfsr_out
use entity work.lfsr_out(behavior);
end for;
end for;
end TESTBENCH_FOR_lfsr_out; | mit | ca3d75b083769a371c0f7b39c91586a7 | 0.627189 | 2.629386 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-digilent-xc3s1600e/config.vhd | 1 | 6,038 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3e;
constant CFG_MEMTECH : integer := spartan3e;
constant CFG_PADTECH : integer := spartan3e;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3e;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000018#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (90);
constant CFG_DDRSP_COL : integer := (10);
constant CFG_DDRSP_SIZE : integer := (64);
constant CFG_DDRSP_RSKEW : integer := (40);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 7efb3a1a7d2c12c7bd28f977b377b80e | 0.643922 | 3.615569 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/leon4_net.vhd | 1 | 22,827 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use work.gencomp.all;
entity leon4_net is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk : in std_ulogic;
gclk : in std_ulogic;
hclken : in std_ulogic;
rstn : in std_ulogic;
ahbix : in ahb_mst_in_type;
ahbox : out ahb_mst_out_type;
ahbsix : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic);
end ;
architecture rtl of leon4_net is
signal disasen : std_ulogic;
component leon4_ut90nhbd
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer range 0 to NTECH := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 2 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 1 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 1 := 0;
tbuf : integer range 0 to 64 := 0;
pwd : integer range 0 to 2 := 2; -- power-down
svt : integer range 0 to 1 := 1; -- single vector trapping
rstaddr : integer := 0;
smp : integer range 0 to 31 := 0; -- support SMP systems
iuft : integer range 0 to 4 := 0;
fpft : integer range 0 to 4 := 0;
cmft : integer range 0 to 1 := 0;
cached : integer := 0;
scantest : integer := 0
);
port (
clk: in std_ulogic;
gclk: in std_ulogic;
hclken: in std_ulogic;
rstn: in std_ulogic;
ahbi_hgrant: in std_logic_vector(0 to NAHBMST-1); -- bus grant
ahbi_hready: in std_ulogic; -- transfer done
ahbi_hresp: in std_logic_vector(1 downto 0); -- response type
ahbi_hrdata: in std_logic_vector(127 downto 0); -- read data bus
ahbi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
ahbi_testen: in std_ulogic;
ahbi_testrst: in std_ulogic;
ahbi_scanen: in std_ulogic;
ahbi_testoen: in std_ulogic;
ahbo_hbusreq: out std_ulogic; -- bus request
ahbo_hlock: out std_ulogic; -- lock request
ahbo_htrans: out std_logic_vector(1 downto 0); -- transfer type
ahbo_haddr: out std_logic_vector(31 downto 0); -- address bus (byte)
ahbo_hwrite: out std_ulogic; -- read/write
ahbo_hsize: out std_logic_vector(2 downto 0); -- transfer size
ahbo_hburst: out std_logic_vector(2 downto 0); -- burst type
ahbo_hprot: out std_logic_vector(3 downto 0); -- protection control
ahbo_hwdata: out std_logic_vector(127 downto 0); -- write data bus
ahbo_hirq: out std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt bus
ahbsi_hsel: in std_logic_vector(0 to NAHBSLV-1); -- slave select
ahbsi_haddr: in std_logic_vector(31 downto 0); -- address bus (byte)
ahbsi_hwrite: in std_ulogic; -- read/write
ahbsi_htrans: in std_logic_vector(1 downto 0); -- transfer type
ahbsi_hsize: in std_logic_vector(2 downto 0); -- transfer size
ahbsi_hburst: in std_logic_vector(2 downto 0); -- burst type
ahbsi_hwdata: in std_logic_vector(127 downto 0); -- write data bus
ahbsi_hprot: in std_logic_vector(3 downto 0); -- protection control
ahbsi_hready: in std_ulogic; -- transfer done
ahbsi_hmaster: in std_logic_vector(3 downto 0); -- current master
ahbsi_hmastlock: in std_ulogic; -- locked access
ahbsi_hmbsel: in std_logic_vector(0 to NAHBAMR-1); -- memory bank select
ahbsi_hirq: in std_logic_vector(NAHBIRQ-1 downto 0); -- interrupt result bus
irqi_irl: in std_logic_vector(3 downto 0);
irqi_rst: in std_ulogic;
irqi_run: in std_ulogic;
irqi_rstvec: in std_logic_vector(31 downto 12);
irqi_iact: in std_ulogic;
irqi_index: in std_logic_vector(3 downto 0);
irqo_intack: out std_ulogic;
irqo_irl: out std_logic_vector(3 downto 0);
irqo_pwd: out std_ulogic;
irqo_fpen: out std_ulogic;
irqo_idle: out std_ulogic;
dbgi_dsuen: in std_ulogic; -- DSU enable
dbgi_denable: in std_ulogic; -- diagnostic register access enable
dbgi_dbreak: in std_ulogic; -- debug break-in
dbgi_step: in std_ulogic; -- single step
dbgi_halt: in std_ulogic; -- halt processor
dbgi_reset: in std_ulogic; -- reset processor
dbgi_dwrite: in std_ulogic; -- read/write
dbgi_daddr: in std_logic_vector(23 downto 2); -- diagnostic address
dbgi_ddata: in std_logic_vector(31 downto 0); -- diagnostic data
dbgi_btrapa: in std_ulogic; -- break on IU trap
dbgi_btrape: in std_ulogic; -- break on IU trap
dbgi_berror: in std_ulogic; -- break on IU error mode
dbgi_bwatch: in std_ulogic; -- break on IU watchpoint
dbgi_bsoft: in std_ulogic; -- break on software breakpoint (TA 1)
dbgi_tenable: in std_ulogic;
dbgi_timer: in std_logic_vector(30 downto 0);
dbgo_data: out std_logic_vector(31 downto 0);
dbgo_crdy: out std_ulogic;
dbgo_dsu: out std_ulogic;
dbgo_dsumode: out std_ulogic;
dbgo_error: out std_ulogic;
dbgo_halt: out std_ulogic;
dbgo_pwd: out std_ulogic;
dbgo_idle: out std_ulogic;
dbgo_ipend: out std_ulogic;
dbgo_icnt: out std_ulogic;
dbgo_fcnt : out std_ulogic;
dbgo_optype : out std_logic_vector(5 downto 0); -- instruction type
dbgo_bpmiss : out std_ulogic; -- branch predict miss
dbgo_istat_cmiss: out std_ulogic;
dbgo_istat_tmiss: out std_ulogic;
dbgo_istat_chold: out std_ulogic;
dbgo_istat_mhold: out std_ulogic;
dbgo_dstat_cmiss: out std_ulogic;
dbgo_dstat_tmiss: out std_ulogic;
dbgo_dstat_chold: out std_ulogic;
dbgo_dstat_mhold: out std_ulogic;
dbgo_wbhold : out std_ulogic; -- write buffer hold
dbgo_su : out std_ulogic;
disasen : in std_ulogic);
end component;
signal ahbi_hgrant: std_logic_vector(0 to NAHBMST-1);
signal ahbi_hready: std_ulogic;
signal ahbi_hresp: std_logic_vector(1 downto 0);
signal ahbi_hrdata: std_logic_vector(127 downto 0);
signal ahbi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbi_testen: std_ulogic;
signal ahbi_testrst: std_ulogic;
signal ahbi_scanen: std_ulogic;
signal ahbi_testoen: std_ulogic;
signal ahbo_hbusreq: std_ulogic;
signal ahbo_hlock: std_ulogic;
signal ahbo_htrans: std_logic_vector(1 downto 0);
signal ahbo_haddr: std_logic_vector(31 downto 0);
signal ahbo_hwrite: std_ulogic;
signal ahbo_hsize: std_logic_vector(2 downto 0);
signal ahbo_hburst: std_logic_vector(2 downto 0);
signal ahbo_hprot: std_logic_vector(3 downto 0);
signal ahbo_hwdata: std_logic_vector(127 downto 0);
signal ahbo_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
signal ahbsi_hsel: std_logic_vector(0 to NAHBSLV-1);
signal ahbsi_haddr: std_logic_vector(31 downto 0);
signal ahbsi_hwrite: std_ulogic;
signal ahbsi_htrans: std_logic_vector(1 downto 0);
signal ahbsi_hsize: std_logic_vector(2 downto 0);
signal ahbsi_hburst: std_logic_vector(2 downto 0);
signal ahbsi_hwdata: std_logic_vector(127 downto 0);
signal ahbsi_hprot: std_logic_vector(3 downto 0);
signal ahbsi_hready: std_ulogic;
signal ahbsi_hmaster: std_logic_vector(3 downto 0);
signal ahbsi_hmastlock: std_ulogic;
signal ahbsi_hmbsel: std_logic_vector(0 to NAHBAMR-1);
signal ahbsi_hirq: std_logic_vector(NAHBIRQ-1 downto 0);
constant hconfig: ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_LEON4, 0, 0, 0),
others => zero32);
begin
disasen <= '1' when disas /= 0 else '0';
-- Plug&Play information
ahbox.hconfig <= hconfig;
ahbox.hindex <= hindex;
ut09 : if fabtech = ut90 generate
wrp: leon4_ut90nhbd
generic map (fpu => fpu, v8 => v8, mmuen => mmuen, isets => isets, isetsize => isetsize, smp => smp)
port map(
clk => clk,
gclk => gclk,
hclken => hclken,
rstn => rstn,
ahbi_hgrant => ahbi_hgrant,
ahbi_hready => ahbi_hready,
ahbi_hresp => ahbi_hresp,
ahbi_hrdata => ahbi_hrdata,
ahbi_hirq => ahbi_hirq,
ahbi_testen => ahbi_testen,
ahbi_testrst => ahbi_testrst,
ahbi_scanen => ahbi_scanen,
ahbi_testoen => ahbi_testoen,
ahbo_hbusreq => ahbo_hbusreq,
ahbo_hlock => ahbo_hlock,
ahbo_htrans => ahbo_htrans,
ahbo_haddr => ahbo_haddr,
ahbo_hwrite => ahbo_hwrite,
ahbo_hsize => ahbo_hsize,
ahbo_hburst => ahbo_hburst,
ahbo_hprot => ahbo_hprot,
ahbo_hwdata => ahbo_hwdata,
ahbo_hirq => ahbo_hirq,
ahbsi_hsel => ahbsi_hsel,
ahbsi_haddr => ahbsi_haddr,
ahbsi_hwrite => ahbsi_hwrite,
ahbsi_htrans => ahbsi_htrans,
ahbsi_hsize => ahbsi_hsize,
ahbsi_hburst => ahbsi_hburst,
ahbsi_hwdata => ahbsi_hwdata,
ahbsi_hprot => ahbsi_hprot,
ahbsi_hready => ahbsi_hready,
ahbsi_hmaster => ahbsi_hmaster,
ahbsi_hmastlock => ahbsi_hmastlock,
ahbsi_hmbsel => ahbsi_hmbsel,
ahbsi_hirq => ahbsi_hirq,
irqi_irl => irqi_irl,
irqi_rst => irqi_rst,
irqi_run => irqi_run,
irqi_rstvec => irqi_rstvec,
irqi_iact => irqi_iact,
irqi_index => irqi_index,
irqo_intack => irqo_intack,
irqo_irl => irqo_irl,
irqo_pwd => irqo_pwd,
irqo_fpen => irqo_fpen,
irqo_idle => irqo_idle,
dbgi_dsuen => dbgi_dsuen,
dbgi_denable => dbgi_denable,
dbgi_dbreak => dbgi_dbreak,
dbgi_step => dbgi_step,
dbgi_halt => dbgi_halt,
dbgi_reset => dbgi_reset,
dbgi_dwrite => dbgi_dwrite,
dbgi_daddr => dbgi_daddr,
dbgi_ddata => dbgi_ddata,
dbgi_btrapa => dbgi_btrapa,
dbgi_btrape => dbgi_btrape,
dbgi_berror => dbgi_berror,
dbgi_bwatch => dbgi_bwatch,
dbgi_bsoft => dbgi_bsoft,
dbgi_tenable => dbgi_tenable,
dbgi_timer => dbgi_timer,
dbgo_data => dbgo_data,
dbgo_crdy => dbgo_crdy,
dbgo_dsu => dbgo_dsu,
dbgo_dsumode => dbgo_dsumode,
dbgo_error => dbgo_error,
dbgo_halt => dbgo_halt,
dbgo_pwd => dbgo_pwd,
dbgo_idle => dbgo_idle,
dbgo_ipend => dbgo_ipend,
dbgo_icnt => dbgo_icnt,
dbgo_fcnt => dbgo_fcnt,
dbgo_optype => dbgo_optype,
dbgo_bpmiss => dbgo_bpmiss,
dbgo_istat_cmiss => dbgo_istat_cmiss,
dbgo_istat_tmiss => dbgo_istat_tmiss,
dbgo_istat_chold => dbgo_istat_chold,
dbgo_istat_mhold => dbgo_istat_mhold,
dbgo_dstat_cmiss => dbgo_dstat_cmiss,
dbgo_dstat_tmiss => dbgo_dstat_tmiss,
dbgo_dstat_chold => dbgo_dstat_chold,
dbgo_dstat_mhold => dbgo_dstat_mhold,
dbgo_wbhold => dbgo_wbhold,
dbgo_su => dbgo_su,
disasen => disasen);
end generate;
ahbi_hgrant(0) <= ahbix.hgrant(hindex);
ahbi_hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi_hready <= ahbix.hready;
ahbi_hresp <= ahbix.hresp;
ahbi_hrdata(127 mod AHBDW downto 0) <= ahbix.hrdata(127 mod AHBDW downto 0);
ahbi_hirq <= ahbix.hirq;
ahbi_testen <= ahbix.testen;
ahbi_testrst <= ahbix.testrst;
ahbi_scanen <= ahbix.scanen;
ahbi_testoen <= ahbix.testoen;
ahbox.hbusreq <= ahbo_hbusreq;
ahbox.hlock <= ahbo_hlock;
ahbox.htrans <= ahbo_htrans;
ahbox.haddr <= ahbo_haddr;
ahbox.hwrite <= ahbo_hwrite;
ahbox.hsize <= ahbo_hsize(2 downto 0);
ahbox.hburst <= "00" & ahbo_hburst(0);
ahbox.hprot <= ahbo_hprot;
ahbox.hwdata(127 mod AHBDW downto 0) <= ahbo_hwdata(127 mod AHBDW downto 0);
ahbox.hirq <= (others => '0'); --ahbo_hirq;
ahbsi_hsel <= ahbsix.hsel;
ahbsi_haddr <= ahbsix.haddr;
ahbsi_hwrite <= ahbsix.hwrite;
ahbsi_htrans <= ahbsix.htrans;
ahbsi_hsize <= ahbsix.hsize;
ahbsi_hburst <= ahbsix.hburst;
ahbsi_hwdata(127 mod AHBDW downto 0) <= ahbsix.hwdata(127 mod AHBDW downto 0);
ahbsi_hprot <= ahbsix.hprot;
ahbsi_hready <= ahbsix.hready;
ahbsi_hmaster <= ahbsix.hmaster;
ahbsi_hmastlock <= ahbsix.hmastlock;
ahbsi_hmbsel <= ahbsix.hmbsel;
ahbsi_hirq <= ahbsix.hirq;
-- pragma translate_off
assert NAHBSLV=16
report "LEON3FT netlist: Only NAHBSLV=16 supported by wrapper"
severity Failure;
-- pragma translate_on
end architecture;
| gpl-2.0 | 490b1461c7c3cf599faa3d8f9ee3488b | 0.51093 | 3.878845 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/i2c/i2c2ahb_apb_gen.vhd | 1 | 5,329 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_apb_gen
-- File: i2c2ahb_apb_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Generic wrapper for I2C-slave, see i2c2ahb_apb.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb_apb_gen is
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
--ahbi : in ahb_mst_in_type;
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(AHBDW-1 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(AHBDW-1 downto 0);
-- APB slave interface
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_irq : out std_logic;
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2c2ahb_apb_gen;
architecture rtl of i2c2ahb_apb_gen is
-- AHB signals
signal ahbi : ahb_mst_in_type;
signal ahbo : ahb_mst_out_type;
-- APB signals
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
ahbi.hgrant(0) <= ahbi_hgrant;
ahbi.hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi.hready <= ahbi_hready;
ahbi.hresp <= ahbi_hresp;
ahbi.hrdata <= ahbi_hrdata;
ahbo_hbusreq <= ahbo.hbusreq;
ahbo_hlock <= ahbo.hlock;
ahbo_htrans <= ahbo.htrans;
ahbo_haddr <= ahbo.haddr;
ahbo_hwrite <= ahbo.hwrite;
ahbo_hsize <= ahbo.hsize;
ahbo_hburst <= ahbo.hburst;
ahbo_hprot <= ahbo.hprot;
ahbo_hwdata <= ahbo.hwdata;
apbi.psel(0) <= apbi_psel;
apbi.psel(1 to NAPBSLV-1) <= (others => '0');
apbi.penable <= apbi_penable;
apbi.paddr <= apbi_paddr;
apbi.pwrite <= apbi_pwrite;
apbi.pwdata <= apbi_pwdata;
apbi.pirq <= (others => '0');
apbi.testen <= '0';
apbi.testrst <= '0';
apbi.scanen <= '0';
apbi.testoen <= '0';
apbo_prdata <= apbo.prdata;
apbo_irq <= apbo.pirq(0);
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2c2ahb_apb
generic map (
hindex => 0,
ahbaddrh => ahbaddrh, ahbaddrl => ahbaddrl,
ahbmaskh => ahbmaskh, ahbmaskl => ahbmaskl,
resen => resen,
pindex => 0, paddr => 0, pmask => 0, pirq => 0,
i2cslvaddr => i2cslvaddr, i2ccfgaddr => i2ccfgaddr,
oepol => oepol, filter => filter)
port map (rstn, clk, ahbi, ahbo, apbi, apbo, i2ci, i2co);
end architecture rtl;
| gpl-2.0 | b8adf6f319666504883aee0db9438a41 | 0.589416 | 3.261322 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_1/sim/zqynq_lab_1_design_axi_gpio_1_1.vhd | 1 | 9,004 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_15;
USE axi_gpio_v2_0_15.axi_gpio;
ENTITY zqynq_lab_1_design_axi_gpio_1_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END zqynq_lab_1_design_axi_gpio_1_1;
ARCHITECTURE zqynq_lab_1_design_axi_gpio_1_1_arch OF zqynq_lab_1_design_axi_gpio_1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_gpio_1_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 5,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zqynq_lab_1_design_axi_gpio_1_1_arch;
| mit | 1465b9fed7e007bc369bf8160026499f | 0.681364 | 3.221467 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ipshared/a004/hdl/axi_timer_v2_0_vh_rfs.vhd | 1 | 102,160 |
-------------------------------------------------------------------------------
-- counter_f - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: counter_f.vhd
--
-- Description: Implements a parameterizable N-bit counter_f
-- Up/Down Counter
-- Count Enable
-- Parallel Load
-- Synchronous Reset
-- The structural implementation has incremental cost
-- of one LUT per bit.
-- Precedence of operations when simultaneous:
-- reset, load, count
--
-- A default inferred-RTL implementation is provided and
-- is used if the user explicitly specifies C_FAMILY=nofamily
-- or ommits C_FAMILY (allowing it to default to nofamily).
-- The default implementation is also used
-- if needed primitives are not available in FPGAs of the
-- type given by C_FAMILY.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- counter_f.vhd
-- family_support.vhd
--
-------------------------------------------------------------------------------
-- Author: FLO & Nitin 06/06/2006 First Version, functional equivalent
-- of counter.vhd.
-- History:
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.unsigned;
use IEEE.numeric_std."+";
use IEEE.numeric_std."-";
library unisim;
use unisim.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity counter_f is
generic(
C_NUM_BITS : integer := 9;
C_FAMILY : string := "nofamily"
);
port(
Clk : in std_logic;
Rst : in std_logic;
Load_In : in std_logic_vector(C_NUM_BITS - 1 downto 0);
Count_Enable : in std_logic;
Count_Load : in std_logic;
Count_Down : in std_logic;
Count_Out : out std_logic_vector(C_NUM_BITS - 1 downto 0);
Carry_Out : out std_logic
);
end entity counter_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of counter_f is
---------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------
begin
INFERRED_GEN : if (true) generate
signal icount_out : unsigned(C_NUM_BITS downto 0);
signal icount_out_x : unsigned(C_NUM_BITS downto 0);
signal load_in_x : unsigned(C_NUM_BITS downto 0);
begin
load_in_x <= unsigned('0' & Load_In);
-- Mask out carry position to retain legacy self-clear on next enable.
-- icount_out_x <= ('0' & icount_out(C_NUM_BITS-1 downto 0)); -- Echeck WA
icount_out_x <= unsigned('0' & std_logic_vector(icount_out(C_NUM_BITS-1 downto 0)));
-----------------------------------------------------------------
-- Process to generate counter with - synchronous reset, load,
-- counter enable, count down / up features.
-----------------------------------------------------------------
CNTR_PROC : process(Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
icount_out <= (others => '0');
elsif Count_Load = '1' then
icount_out <= load_in_x;
elsif Count_Down = '1' and Count_Enable = '1' then
icount_out <= icount_out_x - 1;
elsif Count_Enable = '1' then
icount_out <= icount_out_x + 1;
end if;
end if;
end process CNTR_PROC;
Carry_Out <= icount_out(C_NUM_BITS);
Count_Out <= std_logic_vector(icount_out(C_NUM_BITS-1 downto 0));
end generate INFERRED_GEN;
end architecture imp;
---------------------------------------------------------------
-- End of file counter_f.vhd
---------------------------------------------------------------
-- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
-- family_support
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Changed proc_common library version to v4_0
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
--library proc_common_v4_0_2;
--use proc_common_v4_0_2.family_support.all; -- 'supported' function, etc.
--
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
--constant NLS : natural := native_lut_size(fam_as_string => C_FAMILY,
constant NLS : natural := 6; --native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
-------------------------------------------------------------------------------
-- TC_TYPES - package
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_types.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Type definitions for Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- tc_types.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-------------------------------------------------------------------------------
--Package Declaration
-------------------------------------------------------------------------------
package TC_Types is
subtype QUADLET_TYPE is std_logic_vector(0 to 31);
subtype ELEVEN_BIT_TYPE is std_logic_vector(21 to 31);
subtype TWELVE_BIT_TYPE is std_logic_vector(20 to 31);
subtype QUADLET_PLUS1_TYPE is std_logic_vector(0 to 32);
subtype BYTE_TYPE is std_logic_vector(0 to 7);
subtype ALU_OP_TYPE is std_logic_vector(0 to 1);
subtype ADDR_WORD_TYPE is std_logic_vector(0 to 31);
subtype BYTE_ENABLE_TYPE is std_logic_vector(0 to 3);
subtype DATA_WORD_TYPE is QUADLET_TYPE;
subtype INSTRUCTION_WORD_TYPE is QUADLET_TYPE;
-- Bus interface data types
subtype PLB_DWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_AWIDTH_TYPE is QUADLET_TYPE;
subtype PLB_BEWIDTH_TYPE is std_logic_vector(0 to 3);
subtype BYTE_PLUS1_TYPE is std_logic_vector(0 to 8);
subtype NIBBLE_TYPE is std_logic_vector(0 to 3);
type TWO_QUADLET_TYPE is array (0 to 1) of QUADLET_TYPE;
constant CASC_POS : integer := 20;
constant ENALL_POS : integer := 21;
constant PWMA0_POS : integer := 22;
constant T0INT_POS : integer := 23;
constant ENT0_POS : integer := 24;
constant ENIT0_POS : integer := 25;
constant LOAD0_POS : integer := 26;
constant ARHT0_POS : integer := 27;
constant CAPT0_POS : integer := 28;
constant CMPT0_POS : integer := 29;
constant UDT0_POS : integer := 30;
constant MDT0_POS : integer := 31;
constant PWMB0_POS : integer := 22;
constant T1INT_POS : integer := 23;
constant ENT1_POS : integer := 24;
constant ENIT1_POS : integer := 25;
constant LOAD1_POS : integer := 26;
constant ARHT1_POS : integer := 27;
constant CAPT1_POS : integer := 28;
constant CMPT1_POS : integer := 29;
constant UDT1_POS : integer := 30;
constant MDT1_POS : integer := 31;
constant LS_ADDR : std_logic_vector(0 to 1) := "11";
constant NEXT_MSB_BIT : integer := -1;
constant NEXT_LSB_BIT : integer := 1;
-- The following four constants arer reversed from what's
-- in microblaze_isa_be_pkg.vhd
constant BYTE_ENABLE_BYTE_0 : natural := 0;
constant BYTE_ENABLE_BYTE_1 : natural := 1;
constant BYTE_ENABLE_BYTE_2 : natural := 2;
constant BYTE_ENABLE_BYTE_3 : natural := 3;
end package TC_TYPES;
-------------------------------------------------------------------------------
-- timer_control - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :timer_control.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Control logic for Peripheral Timer/Counter
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
-- timer_control.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- system clock
-- Reset -- system reset
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- Interrupt -- Interrupt
-- Counter_TC -- Carry out signal of counter
-- Bus2ip_data -- bus2ip data bus
-- BE -- te enab les
-- Load_Counter_Reg -- Load counter register control
-- Load_Load_Reg -- Load load register control
-- Write_Load_Reg -- write control of TLR reg
-- CaptGen_Mux_Sel -- mux select for capture and generate
-- Counter_En -- counter enable signal
-- Count_Down -- count down signal
-- Bus2ip_rdce -- read select
-- Bus2ip_wrce -- write select
-- Freeze -- freeze
-- TCSR0_Reg -- Control/Status register 0
-- TCSR1_Reg -- Control/Status register 1
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_lite_ipif_v3_0_4;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
use lib_pkg_v1_0_2.lib_pkg.RESET_ACTIVE;
library unisim;
use unisim.vcomponents.FDRSE;
library axi_timer_v2_0_15;
use axi_timer_v2_0_15.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0_15.TC_Types.TWELVE_BIT_TYPE;
use axi_timer_v2_0_15.TC_Types.ELEVEN_BIT_TYPE;
use axi_timer_v2_0_15.TC_Types.ARHT0_POS;
use axi_timer_v2_0_15.TC_Types.ARHT1_POS;
use axi_timer_v2_0_15.TC_Types.CAPT0_POS;
use axi_timer_v2_0_15.TC_Types.CAPT1_POS;
use axi_timer_v2_0_15.TC_Types.CMPT0_POS;
use axi_timer_v2_0_15.TC_Types.CMPT1_POS;
use axi_timer_v2_0_15.TC_Types.ENALL_POS;
use axi_timer_v2_0_15.TC_Types.ENIT0_POS;
use axi_timer_v2_0_15.TC_Types.ENIT1_POS;
use axi_timer_v2_0_15.TC_Types.ENT0_POS;
use axi_timer_v2_0_15.TC_Types.ENT1_POS;
use axi_timer_v2_0_15.TC_Types.LOAD0_POS;
use axi_timer_v2_0_15.TC_Types.LOAD1_POS;
use axi_timer_v2_0_15.TC_Types.MDT0_POS;
use axi_timer_v2_0_15.TC_Types.MDT1_POS;
use axi_timer_v2_0_15.TC_Types.PWMA0_POS;
use axi_timer_v2_0_15.TC_Types.PWMB0_POS;
use axi_timer_v2_0_15.TC_Types.T0INT_POS;
use axi_timer_v2_0_15.TC_Types.T1INT_POS;
use axi_timer_v2_0_15.TC_Types.UDT0_POS;
use axi_timer_v2_0_15.TC_Types.UDT1_POS;
use axi_timer_v2_0_15.TC_Types.CASC_POS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity timer_control is
generic (
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Reset : in std_logic;
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
Interrupt : out std_logic;
Counter_TC : in std_logic_vector(0 to 1);
Bus2ip_data : in std_logic_vector(0 to 31);
BE : in std_logic_vector(0 to 3);
Load_Counter_Reg : out std_logic_vector(0 to 1);
Load_Load_Reg : out std_logic_vector(0 to 1);
Write_Load_Reg : out std_logic_vector(0 to 1);
CaptGen_Mux_Sel : out std_logic_vector(0 to 1);
Counter_En : out std_logic_vector(0 to 1);
Count_Down : out std_logic_vector(0 to 1);
Bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Freeze : in std_logic;
TCSR0_Reg : out TWELVE_BIT_TYPE;
TCSR1_Reg : out ELEVEN_BIT_TYPE
);
end entity timer_control;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of timer_control is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal declaration
-------------------------------------------------------------------------------
signal TCSR0_In : TWELVE_BIT_TYPE;
signal TCSR0_Reset : TWELVE_BIT_TYPE;
signal TCSR0_Set : TWELVE_BIT_TYPE;
signal TCSR0_CE : TWELVE_BIT_TYPE;
signal TCSR0 : TWELVE_BIT_TYPE;
signal TCSR1_In : ELEVEN_BIT_TYPE;
signal TCSR1_Reset : ELEVEN_BIT_TYPE;
signal TCSR1_Set : ELEVEN_BIT_TYPE;
signal TCSR1_CE : ELEVEN_BIT_TYPE;
signal TCSR1 : ELEVEN_BIT_TYPE;
signal captureTrig0_d : std_logic;
signal captureTrig1_d : std_logic;
signal captureTrig0_d2 : std_logic;
signal captureTrig1_d2 : std_logic;
signal captureTrig0_Edge : std_logic;
signal captureTrig1_Edge : std_logic;
signal captureTrig0_pulse: std_logic;
signal captureTrig0_pulse_d1: std_logic;
signal captureTrig0_pulse_d2: std_logic;
signal captureTrig1_pulse: std_logic;
signal read_done0 : std_logic;
signal read_done1 : std_logic;
signal generateOutPre0 : std_logic;
signal generateOutPre1 : std_logic;
signal pair0_Select : std_logic;
signal counter_TC_Reg : std_logic_vector(0 to 1);
signal counter_TC_Reg2 : std_logic;
signal tccr0_select : std_logic;
signal tccr1_select : std_logic;
signal interrupt_reg : std_logic;
signal CaptureTrig0_int : std_logic := '0';
signal CaptureTrig1_int : std_logic := '0';
signal Freeze_int : std_logic := '0';
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 0 (TCSR0)
-------------------------------------------------------------------------------
alias CASC : std_logic is TCSR0(CASC_POS);
alias T0INT : std_logic is TCSR0(T0INT_POS);
alias ENT0 : std_logic is TCSR0(ENT0_POS);
alias ENIT0 : std_logic is TCSR0(ENIT0_POS);
alias LOAD0 : std_logic is TCSR0(LOAD0_POS);
alias ARHT0 : std_logic is TCSR0(ARHT0_POS);
alias CAPT0 : std_logic is TCSR0(CAPT0_POS);
alias CMPT0 : std_logic is TCSR0(CMPT0_POS);
alias UDT0 : std_logic is TCSR0(UDT0_POS);
alias MDT0 : std_logic is TCSR0(MDT0_POS);
alias PWMA0 : std_logic is TCSR0(PWMA0_POS);
-------------------------------------------------------------------------------
-- Bits in Timer Control Status Register 1 (TCSR1)
-------------------------------------------------------------------------------
alias T1INT : std_logic is TCSR1(T1INT_POS);
alias ENT1 : std_logic is TCSR1(ENT1_POS);
alias ENIT1 : std_logic is TCSR1(ENIT1_POS);
alias LOAD1 : std_logic is TCSR1(LOAD1_POS);
alias ARHT1 : std_logic is TCSR1(ARHT1_POS);
alias CAPT1 : std_logic is TCSR1(CAPT1_POS);
alias CMPT1 : std_logic is TCSR1(CMPT1_POS);
alias UDT1 : std_logic is TCSR1(UDT1_POS);
alias MDT1 : std_logic is TCSR1(MDT1_POS);
alias PWMB0 : std_logic is TCSR1(PWMB0_POS);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
pair0_Select <= (Bus2ip_wrce(0) or Bus2ip_wrce(4));
---------------------------------------------------
--Creating TCSR0 Register
---------------------------------------------------
TCSR0_GENERATE: for i in TWELVE_BIT_TYPE'range generate
TCSR0_FF_I: component FDRSE
port map (
Q => TCSR0(i), -- [out]
C => Clk, -- [in]
CE => TCSR0_CE(i), -- [in]
D => TCSR0_In(i), -- [in]
R => TCSR0_Reset(i), -- [in]
S => TCSR0_Set(i) -- [in]
);
end generate TCSR0_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR0 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR0_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"000100000000"
when Bus2ip_data(T0INT_POS)='1' and Bus2ip_wrce(0)='1' else
(others => '0') ;
----------------------------------------------------
--TCSR0 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR0 REGISTER
----------------------------------------------------
TCSR0_PROCESS: process (Bus2ip_wrce,Bus2ip_data,MDT0,
captureTrig0_Edge,generateOutPre0,TCSR0,
pair0_select,Reset,BE,ENT0,CASC,generateOutPre1) is
begin
TCSR0_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR0 register
---------------------------------------------
TCSR0_CE(31) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(30) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(29) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(28) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(27) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(26) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(25) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(24) <= Bus2ip_wrce(0) and BE(3);
TCSR0_CE(23) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(22) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(21) <= Bus2ip_wrce(0) and BE(2);
TCSR0_CE(20) <= Bus2ip_wrce(0) and BE(2);
TCSR0_In <= Bus2ip_data(20 to 31);
TCSR0_In(T0INT_POS) <= TCSR0(T0INT_POS);
----------------------------------------------------
---interrupt bit (23-bit) of TCSR1 register is set to 1
----------------------------------------------------
if (CASC = '0') then
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre0='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
else
if (((MDT0='1' and captureTrig0_Edge='1' and ENT0='1') or
(MDT0='0' and generateOutPre1='1'))) then
TCSR0_Set(T0INT_POS) <= '1';
else
TCSR0_Set(T0INT_POS) <= '0';
end if;
end if;
TCSR0_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR0_CE(ENT0_POS) <= pair0_Select;
TCSR0_In(ENT0_POS) <= (Bus2ip_data(ENT0_POS) and Bus2ip_wrce(0) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR0(ENT0_POS) and (not Bus2ip_wrce(0)));
end process TCSR0_PROCESS;
---------------------------------------------------
--Creating TCSR1 Register
---------------------------------------------------
TCSR1_GENERATE: for i in ELEVEN_BIT_TYPE'range generate
TCSR1_FF_I: component FDRSE
port map (
Q => TCSR1(i), -- [out]
C => Clk, -- [in]
CE => TCSR1_CE(i), -- [in]
D => TCSR1_In(i), -- [in]
R => TCSR1_Reset(i), -- [in]
S => TCSR1_Set(i) -- [in]
);
end generate TCSR1_GENERATE;
------------------------------------------------------------------------------------
---Interrupt bit (23-bit) of TCSR1 register is cleared by writing 1 to Interrupt bit
------------------------------------------------------------------------------------
TCSR1_Reset <= (others => '1') when Reset = RESET_ACTIVE else
"00100000000"
when Bus2ip_data(T1INT_POS)='1' and Bus2ip_wrce(4)='1' else
(others => '0') ;
------------------------------------------------------------------------
----------------------------------------------------
--TCSR1 PROCESS:
--TO GENERATE CLOCK ENABLES, AND RESET
--OF TCSR1 REGISTER
----------------------------------------------------
TCSR1_PROCESS: process (Bus2ip_data,Bus2ip_wrce,MDT1,
captureTrig1_Edge,generateOutPre1,TCSR1,
pair0_Select,Reset,BE,ENT1,CASC,
MDT0,captureTrig0_Edge,ENT0) is
begin
TCSR1_Set <= (others => '0');
---------------------------------------------
--Generating clock enables for TCSR1 register
---------------------------------------------
TCSR1_CE(31) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(30) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(29) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(28) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(27) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(26) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(25) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(24) <= Bus2ip_wrce(4) and BE(3);
TCSR1_CE(23) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(22) <= Bus2ip_wrce(4) and BE(2);
TCSR1_CE(21) <= Bus2ip_wrce(4) and BE(2);
TCSR1_In <= Bus2ip_data(21 to 31);
TCSR1_In(T1INT_POS) <= TCSR1(T1INT_POS);
----------------------------------------------------------------
---interrupt bit of TCSR1 register is set to 1
----------------------------------------------------------------
if (((MDT1='1' and captureTrig1_Edge='1' and ENT1='1') or
(MDT1='0' and generateOutPre1='1')) and CASC='0') then
TCSR1_Set(T1INT_POS) <= '1';
else
TCSR1_Set(T1INT_POS) <= '0';
end if;
TCSR1_CE(ENALL_POS) <= pair0_Select and BE(2);
TCSR1_CE(ENT1_POS) <= pair0_Select;
TCSR1_In(ENT1_POS) <= (Bus2ip_data(ENT1_POS) and Bus2ip_wrce(4) and BE(3)) or
(Bus2ip_data(ENALL_POS) and BE(2)) or
(TCSR1(ENT1_POS) and (not Bus2ip_wrce(4)));
end process TCSR1_PROCESS;
-------------------------------------------------------------------------------
-- Counter Controls
-------------------------------------------------------------------------------
READ_DONE0_I: component FDRSE
port map (
Q => read_done0, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done0, -- [in]
R => captureTrig0_Edge, -- [in]
S => tccr0_select -- [in]
);
READ_DONE1_I: component FDRSE
port map (
Q => read_done1, -- [out]
C => Clk, -- [in]
CE => '1', -- [in]
D => read_done1, -- [in]
R => captureTrig1_Edge, -- [in]
S => tccr1_select -- [in]
);
INPUT_DOUBLE_REGS3 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Freeze,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => Freeze_int,
scndry_vect_out => open
);
-------------------------------------------------------
---Generating count enable and count down for counter 0
-------------------------------------------------------
Counter_En(0) <= (not Freeze_int and ENT0 and (MDT0 or (not Counter_TC(0)
or (ARHT0 or PWMA0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(0) <= UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Generating count enable and count down for counter 1
-------------------------------------------------------
Counter_En(1) <= (not Freeze_int and ENT1 and (MDT1 or (not Counter_TC(1)
or (ARHT1 or PWMB0)))) when (CASC = '0') else
((not Freeze_int) and ENT0 and generateOutPre0 and (MDT0 or (not Counter_TC(1)) or ARHT0));
Count_Down(1) <= UDT1 when (CASC = '0') else
UDT0;
-------------------------------------------------------
-------------------------------------------------------
---Load counter0 and counter1 with TLR register value
-------------------------------------------------------
Load_Counter_Reg(0) <= ((Counter_TC(0) and (ARHT0 or PWMA0) and (not MDT0)) or LOAD0) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD0) ;
Load_Counter_Reg(1) <= ((Counter_TC(1) and ARHT1 and not PWMB0 and (not MDT1)) or
LOAD1 or (Counter_TC(0) and PWMB0)) when (CASC = '0') else
((Counter_TC(1) and ARHT0 and (not MDT0)) or LOAD1) ;
-------------------------------------------------------
Load_Load_Reg(0) <= (MDT0 and captureTrig0_Edge and ARHT0) or
(MDT0 and captureTrig0_Edge and not ARHT0 and read_done0);
Load_Load_Reg(1) <= ((MDT1 and captureTrig1_Edge and ARHT1) or
(MDT1 and captureTrig1_Edge and not ARHT1 and read_done1)) when (CASC = '0') else
((MDT0 and captureTrig1_Edge and ARHT0) or
(MDT0 and captureTrig1_Edge and not ARHT0 and read_done1));
-------------------------------------------------------
Write_Load_Reg(0) <= Bus2ip_wrce(1);
Write_Load_Reg(1) <= Bus2ip_wrce(5);
CaptGen_Mux_Sel(0)<= Bus2ip_wrce(1);
CaptGen_Mux_Sel(1)<= Bus2ip_wrce(5);
tccr0_select <= (Bus2ip_wrce(1) or Bus2ip_rdce(1));
tccr1_select <= (Bus2ip_wrce(5) or Bus2ip_rdce(5));
-------------------------------------------------------
---CAPTGEN_SYNC_PROCESS:
-- Process to register the signals
-------------------------------------------------------
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig0,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig0_int,
scndry_vect_out => open
);
INPUT_DOUBLE_REGS2 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => CaptureTrig1,
prmry_vect_in => (others => '0'),
scndry_aclk => Clk,
scndry_resetn => '0',
scndry_out => CaptureTrig1_int,
scndry_vect_out => open
);
CAPTGEN_SYNC_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_d <= not C_TRIG0_ASSERT;
captureTrig1_d <= not C_TRIG1_ASSERT;
captureTrig0_d2 <= '0';
captureTrig1_d2 <= '0';
counter_TC_Reg(0) <= '0';
counter_TC_Reg(1) <= '0';
counter_TC_Reg2 <= '0';
-- counter_TC_Reg2(1) <= '0';
generateOutPre0 <= '0';
generateOutPre1 <= '0';
GenerateOut0 <= not C_GEN0_ASSERT;
GenerateOut1 <= not C_GEN1_ASSERT;
Interrupt <= '0';
else
captureTrig0_d <= (CaptureTrig0_int xor not(C_TRIG0_ASSERT)) and CAPT0;
captureTrig1_d <= (CaptureTrig1_int xor not(C_TRIG1_ASSERT)) and CAPT1;
captureTrig0_d2 <= captureTrig0_d;
captureTrig1_d2 <= captureTrig1_d;
counter_TC_Reg(0) <= Counter_TC(0);
counter_TC_Reg(1) <= Counter_TC(1);
counter_TC_Reg2 <= counter_TC_Reg(0);
-- counter_TC_Reg2(1) <= counter_TC_Reg(1);
generateOutPre0 <= Counter_TC(0) and (not counter_TC_Reg(0));
generateOutPre1 <= Counter_TC(1) and (not counter_TC_Reg(1));
GenerateOut0 <= ((((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and (not CASC)) or
(((generateOutPre1 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
GenerateOut1 <= ((((generateOutPre1 and CMPT1) xor not(C_GEN1_ASSERT)) and (not CASC)) or
(((generateOutPre0 and CMPT0) xor not(C_GEN0_ASSERT)) and CASC));
Interrupt <= (ENIT0 and T0INT) or (ENIT1 and T1INT);
-- for edge-sensitive interrupt
--interrupt_reg<= (ENIT0 and T0INT) or (ENIT1 and T1INT);
--Interrupt <= ((ENIT0 and T0INT) or (ENIT1 and T1INT))
-- and (not interrupt_reg);
end if;
end if;
end process CAPTGEN_SYNC_PROCESS;
captureTrig0_pulse <= captureTrig0_d and not captureTrig0_d2;
captureTrig1_pulse <= captureTrig1_d and not captureTrig1_d2;
captureTrig0_Edge <= captureTrig0_pulse when (CASC = '0') else
(((not Counter_TC(0)) and (not counter_TC_Reg(0)) and captureTrig0_pulse) or
(captureTrig0_pulse_d2 and counter_TC_Reg2) or
(captureTrig0_pulse_d1 and counter_TC_Reg2));
captureTrig1_Edge <= captureTrig1_pulse when (CASC = '0') else
captureTrig0_Edge;
DELAY_CAPT_TRIG_PROCESS: process(Clk) is
begin
if Clk'event and Clk='1' then
if Reset='1' then
captureTrig0_pulse_d1 <= '0';
captureTrig0_pulse_d2 <= '0';
else
captureTrig0_pulse_d1 <= captureTrig0_pulse;
captureTrig0_pulse_d2 <= captureTrig0_pulse_d1;
end if;
end if;
end process DELAY_CAPT_TRIG_PROCESS;
TCSR0_Reg <= TCSR0;
TCSR1_Reg <= TCSR1;
end architecture imp;
-------------------------------------------------------------------------------
-- count_module - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: count_module.vhd
-- Version: v2.0
-- Description: Module with one counter and load register
--
-------------------------------------------------------------------------------
-- Structure:
--
-- count_module.vhd
-- -- counter_f.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_FAMILY -- Default family
-- C_COUNT_WIDTH -- Width of the counter
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- clock
-- Reset -- reset
-- Load_DBus -- Count Load bus
-- Load_Counter_Reg -- Counter load control
-- Load_Load_Reg -- Load register control
-- Write_Load_Reg -- Write Control of TLR reg
-- CaptGen_Mux_Sel -- Mux select for capture and generate data
-- Counter_En -- Counter enable
-- Count_Down -- Count down
-- BE -- Byte enable
-- LoadReg_DBus -- Load reg bus
-- CounterReg_DBus -- Counter reg bus
-- Counter_TC -- counter Carry out signal
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.FDRE;
library axi_timer_v2_0_15;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity count_module is
generic (
C_FAMILY : string := "virtex5";
C_COUNT_WIDTH : integer := 32
);
port (
Clk : in std_logic;
Reset : in std_logic;
Load_DBus : in std_logic_vector(0 to C_COUNT_WIDTH-1);
Load_Counter_Reg : in std_logic;
Load_Load_Reg : in std_logic;
Write_Load_Reg : in std_logic;
CaptGen_Mux_Sel : in std_logic;
Counter_En : in std_logic;
Count_Down : in std_logic;
BE : in std_Logic_vector(0 to 3);
LoadReg_DBus : out std_logic_vector(0 to C_COUNT_WIDTH-1);
CounterReg_DBus : out std_logic_vector(0 to C_COUNT_WIDTH-1);
Counter_TC : out std_logic
);
end entity count_module;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of count_module is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Signal Declaration
signal iCounterReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal loadRegIn : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal load_Reg : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal load_load_reg_be : std_logic_vector(0 to C_COUNT_WIDTH-1);
signal carry_out : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- Architecture imp
-------------------------------------------------------------------------------
--CAPTGEN_MUX_PROCESS : Process to implement mux the Load_DBus and
--iCounterReg_DBus
-------------------------------------------------------------------------------
CAPTGEN_MUX_PROCESS: process (CaptGen_Mux_Sel,Load_DBus,iCounterReg_DBus ) is
begin
if CaptGen_Mux_Sel='1' then
loadRegIn <= Load_DBus;
else
loadRegIn <= iCounterReg_DBus;
end if;
end process CAPTGEN_MUX_PROCESS;
-------------------------------------------------------------------------------
--LOAD_REG_GEN: To generate load register
-------------------------------------------------------------------------------
LOAD_REG_GEN: for i in 0 to C_COUNT_WIDTH-1 generate
load_load_reg_be(i) <= Load_Load_Reg or
(Write_Load_Reg and BE((i-C_COUNT_WIDTH+32)/8));
LOAD_REG_I: component FDRE
port map (
Q => load_Reg(i), -- [out]
C => Clk, -- [in]
CE => load_load_reg_be(i), -- [in]
D => loadRegIn(i), -- [in]
R => Reset -- [in]
);
end generate LOAD_REG_GEN;
-------------------------------------------------------------------------------
--counter_f module is instantiated
-------------------------------------------------------------------------------
COUNTER_I: entity axi_timer_v2_0_15.counter_f
generic map (
C_NUM_BITS => C_COUNT_WIDTH, -- [integer]
C_FAMILY => C_FAMILY -- [string]
)
port map(
Clk => Clk, -- [in std_logic]
Rst => Reset, -- [in std_logic]
Load_In => load_Reg, -- [in std_logic_vector]
Count_Enable => Counter_En, -- [in std_logic]
Count_Load => Load_Counter_Reg, -- [in std_logic]
Count_Down => Count_Down, -- [in std_logic]
Count_Out => iCounterReg_DBus, -- [out std_logic_vector]
Carry_Out => carry_out -- [out std_logic]
);
Counter_TC <= carry_out;
LoadReg_DBus <= load_Reg;
CounterReg_DBus <= iCounterReg_DBus;
end architecture imp;
-------------------------------------------------------------------------------
-- TC_Core - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :tc_core.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Dual Timer/Counter for PLB bus
-- Standard :VHDL-93
--
-------------------------------------------------------------------------------
-- Structure:
--
-- --tc_core.vhd
-- --mux_onehot_f.vhd
-- --family_support.vhd
-- --timer_control.vhd
-- --count_module.vhd
-- --counter_f.vhd
-- --family_support.vhd
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_FAMILY -- Default family
-- C_AWIDTH -- PLB address bus width
-- C_DWIDTH -- PLB data bus width
-- C_COUNT_WIDTH -- Width in the bits of the counter
-- C_ONE_TIMER_ONLY -- Number of the Timer
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-- C_ARD_NUM_CE_ARRAY -- Number of chip enable
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Clk -- PLB Clock
-- Rst -- PLB Reset
-- Bus2ip_addr -- bus to ip address bus
-- Bus2ip_be -- byte enables
-- Bus2ip_data -- bus to ip data bus
--
-- TC_DBus -- ip to bus data bus
-- bus2ip_rdce -- read select
-- bus2ip_wrce -- write select
-- ip2bus_rdack -- read acknowledge
-- ip2bus_wrack -- write acknowledge
-- TC_errAck -- error acknowledge
-------------------------------------------------------------------------------
-- Timer/Counter signals
-------------------------------------------------------------------------------
-- CaptureTrig0 -- Capture Trigger 0
-- CaptureTrig1 -- Capture Trigger 1
-- GenerateOut0 -- Generate Output 0
-- GenerateOut1 -- Generate Output 1
-- PWM0 -- Pulse Width Modulation Ouput 0
-- Interrupt -- Interrupt
-- Freeze -- Freeze count value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_timer_v2_0_15;
use axi_timer_v2_0_15.TC_Types.QUADLET_TYPE;
use axi_timer_v2_0_15.TC_Types.PWMA0_POS;
use axi_timer_v2_0_15.TC_Types.PWMB0_POS;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
library unisim;
use unisim.vcomponents.FDRS;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity tc_core is
generic (
C_FAMILY : string := "virtex5";
C_COUNT_WIDTH : integer := 32;
C_ONE_TIMER_ONLY : integer := 0;
C_DWIDTH : integer := 32;
C_AWIDTH : integer := 5;
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
);
port (
Clk : in std_logic;
Rst : in std_logic;
-- PLB signals
Bus2ip_addr : in std_logic_vector(0 to C_AWIDTH-1);
Bus2ip_be : in std_logic_vector(0 to 3);
Bus2ip_data : in std_logic_vector(0 to 31);
TC_DBus : out std_logic_vector(0 to 31);
bus2ip_rdce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
bus2ip_wrce : in std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
ip2bus_rdack : out std_logic;
ip2bus_wrack : out std_logic;
TC_errAck : out std_logic;
-- PTC signals
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic
);
end entity tc_core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of tc_core is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
--Attribute declaration
attribute syn_keep : boolean;
--Signal declaration
signal load_Counter_Reg : std_logic_vector(0 to 1);
signal load_Load_Reg : std_logic_vector(0 to 1);
signal write_Load_Reg : std_logic_vector(0 to 1);
signal captGen_Mux_Sel : std_logic_vector(0 to 1);
signal loadReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal counterReg_DBus : std_logic_vector(0 to C_COUNT_WIDTH*2-1);
signal tCSR0_Reg : QUADLET_TYPE;
signal tCSR1_Reg : QUADLET_TYPE;
signal counter_TC : std_logic_vector(0 to 1);
signal counter_En : std_logic_vector(0 to 1);
signal count_Down : std_logic_vector(0 to 1);
attribute syn_keep of count_Down : signal is true;
signal iPWM0 : std_logic;
signal iGenerateOut0 : std_logic;
signal iGenerateOut1 : std_logic;
signal pwm_Reset : std_logic;
signal Read_Reg_In : QUADLET_TYPE;
signal read_Mux_In : std_logic_vector(0 to 6*32-1);
signal read_Mux_S : std_logic_vector(0 to 5);
begin -- architecture imp
-----------------------------------------------------------------------------
-- Generating the acknowledgement/error signals
-----------------------------------------------------------------------------
ip2bus_rdack <= (Bus2ip_rdce(0) or Bus2ip_rdce(1) or Bus2ip_rdce(2) or
Bus2ip_rdce(4) or Bus2ip_rdce(5) or
Bus2ip_rdce(6) or Bus2ip_rdce(7));
ip2bus_wrack <= (Bus2ip_wrce(0) or Bus2ip_wrce(1) or Bus2ip_wrce(2) or
Bus2ip_wrce(4) or Bus2ip_wrce(5) or
Bus2ip_wrce(6) or Bus2ip_wrce(7));
--TCR0 AND TCR1 is read only register, hence writing to these register
--will not generate error ack.
--Modify TC_errAck <= (Bus2ip_wrce(2)or Bus2ip_wrce(6)) on 11/11/08 to;
TC_errAck <= '0';
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--Process :READ_MUX_INPUT
-----------------------------------------------------------------------------
READ_MUX_INPUT: process (TCSR0_Reg,TCSR1_Reg,LoadReg_DBus,CounterReg_DBus) is
begin
read_Mux_In(0 to 19) <= (others => '0');
read_Mux_In(20 to 31) <= TCSR0_Reg(20 to 31);
read_Mux_In(32 to 52) <= (others => '0');
read_Mux_In(53 to 63) <= TCSR1_Reg(21 to 31);
if C_COUNT_WIDTH < C_DWIDTH then
for i in 1 to C_DWIDTH-C_COUNT_WIDTH loop
read_Mux_In(63 +i) <= '0';
read_Mux_In(95 +i) <= '0';
read_Mux_In(127+i) <= '0';
read_Mux_In(159+i) <= '0';
end loop;
end if;
read_Mux_In(64 +C_DWIDTH-C_COUNT_WIDTH to 95) <=
LoadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(96 +C_DWIDTH-C_COUNT_WIDTH to 127) <=
LoadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
read_Mux_In(128+C_DWIDTH-C_COUNT_WIDTH to 159) <=
CounterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1);
read_Mux_In(160+C_DWIDTH-C_COUNT_WIDTH to 191) <=
CounterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1);
end process READ_MUX_INPUT;
---------------------------------------------------------
-- Create read mux select input
-- Bus2ip_rdce(0) -->TCSR0 REG READ ENABLE
-- Bus2ip_rdce(4) -->TCSR1 REG READ ENABLE
-- Bus2ip_rdce(1) -->TLR0 REG READ ENABLE
-- Bus2ip_rdce(5) -->TLR1 REG READ ENABLE
-- Bus2ip_rdce(2) -->TCR0 REG READ ENABLE
-- Bus2ip_rdce(6) -->TCR1 REG READ ENABLE
---------------------------------------------------------
read_Mux_S <= Bus2ip_rdce(0) & Bus2ip_rdce(4)& Bus2ip_rdce(1)
& Bus2ip_rdce(5) & Bus2ip_rdce(2) & Bus2ip_rdce(6);
-- mux_onehot_f
READ_MUX_I: entity axi_timer_v2_0_15.mux_onehot_f
generic map(
C_DW => 32,
C_NB => 6,
C_FAMILY => C_FAMILY)
port map(
D => read_Mux_In, --[in]
S => read_Mux_S, --[in]
Y => Read_Reg_In --[out]
);
--slave to bus data bus assignment
TC_DBus <= Read_Reg_In ;
------------------------------------------------------------------
------------------------------------------------------------------
-- COUNTER MODULE
------------------------------------------------------------------
COUNTER_0_I: entity axi_timer_v2_0_15.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(0), --[in]
Load_Load_Reg => load_Load_Reg(0), --[in]
Write_Load_Reg => write_Load_Reg(0), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(0), --[in]
Counter_En => counter_En(0), --[in]
Count_Down => count_Down(0), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*0 to C_COUNT_WIDTH*1-1), --[out]
Counter_TC => counter_TC(0) --[out]
);
----------------------------------------------------------------------
--GEN_SECOND_TIMER:SECOND COUNTER MODULE IS ADDED TO DESIGN
--WHEN C_ONE_TIMER_ONLY /= 1
----------------------------------------------------------------------
GEN_SECOND_TIMER: if C_ONE_TIMER_ONLY /= 1 generate
COUNTER_1_I: entity axi_timer_v2_0_15.count_module
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH)
port map (
Clk => Clk, --[in]
Reset => Rst, --[in]
Load_DBus => Bus2ip_data(C_DWIDTH-C_COUNT_WIDTH to C_DWIDTH-1), --[in]
Load_Counter_Reg => load_Counter_Reg(1), --[in]
Load_Load_Reg => load_Load_Reg(1), --[in]
Write_Load_Reg => write_Load_Reg(1), --[in]
CaptGen_Mux_Sel => captGen_Mux_Sel(1), --[in]
Counter_En => counter_En(1), --[in]
Count_Down => count_Down(1), --[in]
BE => Bus2ip_be, --[in]
LoadReg_DBus => loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
CounterReg_DBus => counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1), --[out]
Counter_TC => counter_TC(1) --[out]
);
end generate GEN_SECOND_TIMER;
----------------------------------------------------------------------
--GEN_NO_SECOND_TIMER: GENERATE WHEN C_ONE_TIMER_ONLY = 1
----------------------------------------------------------------------
GEN_NO_SECOND_TIMER: if C_ONE_TIMER_ONLY = 1 generate
loadReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counterReg_DBus(C_COUNT_WIDTH*1 to C_COUNT_WIDTH*2-1) <= (others => '0');
counter_TC(1) <= '0';
end generate GEN_NO_SECOND_TIMER;
----------------------------------------------------------------------
--TIMER_CONTROL_I: TIMER_CONTROL MODULE
----------------------------------------------------------------------
TIMER_CONTROL_I: entity axi_timer_v2_0_15.timer_control
generic map (
C_TRIG0_ASSERT => C_TRIG0_ASSERT,
C_TRIG1_ASSERT => C_TRIG1_ASSERT,
C_GEN0_ASSERT => C_GEN0_ASSERT,
C_GEN1_ASSERT => C_GEN1_ASSERT,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map (
Clk => Clk, -- [in]
Reset => Rst, -- [in]
CaptureTrig0 => CaptureTrig0, -- [in]
CaptureTrig1 => CaptureTrig1, -- [in]
GenerateOut0 => iGenerateOut0, -- [out]
GenerateOut1 => iGenerateOut1, -- [out]
Interrupt => Interrupt, -- [out]
Counter_TC => counter_TC, -- [in]
Bus2ip_data => Bus2ip_data, -- [in]
BE => Bus2ip_be, -- [in]
Load_Counter_Reg => load_Counter_Reg, -- [out]
Load_Load_Reg => load_Load_Reg, -- [out]
Write_Load_Reg => write_Load_Reg, -- [out]
CaptGen_Mux_Sel => captGen_Mux_Sel, -- [out]
Counter_En => counter_En, -- [out]
Count_Down => count_Down, -- [out]
Bus2ip_rdce => Bus2ip_rdce, -- [in]
Bus2ip_wrce => Bus2ip_wrce, -- [in]
Freeze => Freeze, -- [in]
TCSR0_Reg => tCSR0_Reg(20 to 31), -- [out]
TCSR1_Reg => tCSR1_Reg(21 to 31) -- [out]
);
tCSR0_Reg (0 to 19) <= (others => '0');
tCSR1_Reg (0 to 20) <= (others => '0');
pwm_Reset <= iGenerateOut1 or
(not tCSR0_Reg(PWMA0_POS) and not tCSR1_Reg(PWMB0_POS));
PWM_FF_I: component FDRS
port map (
Q => iPWM0, -- [out]
C => Clk, -- [in]
D => iPWM0, -- [in]
R => pwm_Reset, -- [in]
S => iGenerateOut0 -- [in]
);
PWM0 <= iPWM0;
GenerateOut0 <= iGenerateOut0;
GenerateOut1 <= iGenerateOut1;
end architecture IMP;
-------------------------------------------------------------------------------
-- xps_timer - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2001, 2002, 2003, 2004, 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename :axi_timer.vhd
-- Company :Xilinx
-- Version :v2.0
-- Description :Timer/Counter for AXI
-- Standard :VHDL-93
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_timer.
--
-- axi_timer.vhd
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-- --tc_types.vhd
-- --tc_core.vhd
-- --mux_onehot_f.vhd
-- --family_support.vhd
-- --timer_control.vhd
-- --count_module.vhd
-- --counter_f.vhd
-- --family_support.vhd
--
--
-------------------------------------------------------------------------------
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 03/18/2010 -- Ceated the version v1.00.a
-- ^^^^^^
-- Author: BSB
-- History:
-- BSB 09/18/2010 -- Ceated the version v1.01.a
-- -- axi lite ipif v1.01.a used
-- ^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- C_COUNT_WIDTH -- Width in the bits of the counter
-- C_ONE_TIMER_ONLY -- Number of the Timer
-- C_TRIG0_ASSERT -- Assertion Level of captureTrig0
-- C_TRIG1_ASSERT -- Assertion Level of captureTrig1
-- C_GEN0_ASSERT -- Assertion Level for GenerateOut0
-- C_GEN1_ASSERT -- Assertion Level for GenerateOut1
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-------------------------------------------------------------------------------
-- timer/counter signals
-------------------------------------------------------------------------------
-- capturetrig0 -- Capture Trigger 0
-- capturetrig1 -- Capture Trigger 1
-- generateout0 -- Generate Output 0
-- generateout1 -- Generate Output 1
-- pwm0 -- Pulse Width Modulation Ouput 0
-- interrupt -- Interrupt
-- freeze -- Freeze count value
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_timer_v2_0_15;
library axi_lite_ipif_v3_0_4;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.calc_num_ce;
use axi_lite_ipif_v3_0_4.ipif_pkg.SLV64_ARRAY_TYPE;
use axi_lite_ipif_v3_0_4.ipif_pkg.INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Entity declarations
-------------------------------------------------------------------------------
entity axi_timer is
generic (
C_FAMILY : string := "virtex7";
C_COUNT_WIDTH : integer := 32;
C_ONE_TIMER_ONLY : integer := 0;
C_TRIG0_ASSERT : std_logic := '1';
C_TRIG1_ASSERT : std_logic := '1';
C_GEN0_ASSERT : std_logic := '1';
C_GEN1_ASSERT : std_logic := '1';
-- axi lite ipif block generics
C_S_AXI_DATA_WIDTH: integer := 32;
C_S_AXI_ADDR_WIDTH: integer := 5 --5
);
port
(
--Timer/Counter signals
capturetrig0 : in std_logic;
capturetrig1 : in std_logic;
generateout0 : out std_logic;
generateout1 : out std_logic;
pwm0 : out std_logic;
interrupt : out std_logic;
freeze : in std_logic;
--system signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic := '1';
s_axi_awaddr : in std_logic_vector(4 downto 0);
--(c_s_axi_addr_width-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
-- (c_s_axi_data_width-1 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
-- ((c_s_axi_data_width/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(4 downto 0);
--(c_s_axi_addr_width-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
--(c_s_axi_data_width-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
-- Fan-out attributes for XST
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN: signal is "10000";
end entity axi_timer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of axi_timer is
-- Pragma Added to supress synth warnings
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- constant added for webtalk information
-------------------------------------------------------------------------------
--function chr(sl: std_logic) return character is
-- variable c: character;
-- begin
-- case sl is
-- when '0' => c:= '0';
-- when '1' => c:= '1';
-- when 'Z' => c:= 'Z';
-- when 'U' => c:= 'U';
-- when 'X' => c:= 'X';
-- when 'W' => c:= 'W';
-- when 'L' => c:= 'L';
-- when 'H' => c:= 'H';
-- when '-' => c:= '-';
-- end case;
-- return c;
-- end chr;
--
--function str(slv: std_logic_vector) return string is
-- variable result : string (1 to slv'length);
-- variable r : integer;
-- begin
-- r := 1;
-- for i in slv'range loop
-- result(r) := chr(slv(i));
-- r := r + 1;
-- end loop;
-- return result;
-- end str;
constant ZEROES : std_logic_vector(0 to 31) := X"00000000";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
-- Timer registers Base Address
ZEROES & X"00000000",
ZEROES & X"0000001F"
);
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 8
);
constant C_S_AXI_MIN_SIZE :std_logic_vector(31 downto 0):= X"0000001F";
constant C_USE_WSTRB :integer := 0;
constant C_DPHASE_TIMEOUT :integer range 0 to 256 := 32;
--Signal declaration --------------------------------
signal bus2ip_clk : std_logic;
signal bus2ip_resetn : std_logic;
signal bus2ip_reset : std_logic;
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1)
:=(others => '0');
signal ip2bus_error : std_logic := '0';
signal ip2bus_wrack : std_logic := '0';
signal ip2bus_rdack : std_logic := '0';
-----------------------------------------------------------------------
signal bus2ip_data : std_logic_vector
(0 to C_S_AXI_DATA_WIDTH-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1);
signal bus2ip_be : std_logic_vector
(0 to C_S_AXI_DATA_WIDTH/8-1 );
signal bus2ip_rdce : std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal bus2ip_wrce : std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture imp
TC_CORE_I: entity axi_timer_v2_0_15.tc_core
generic map (
C_FAMILY => C_FAMILY,
C_COUNT_WIDTH => C_COUNT_WIDTH,
C_ONE_TIMER_ONLY => C_ONE_TIMER_ONLY,
C_DWIDTH => C_S_AXI_DATA_WIDTH,
C_AWIDTH => C_S_AXI_ADDR_WIDTH,
C_TRIG0_ASSERT => C_TRIG0_ASSERT,
C_TRIG1_ASSERT => C_TRIG1_ASSERT,
C_GEN0_ASSERT => C_GEN0_ASSERT,
C_GEN1_ASSERT => C_GEN1_ASSERT,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map (
-- IPIF signals
Clk => bus2ip_clk, --[in]
Rst => bus2ip_reset, --[in]
Bus2ip_addr => bus2ip_addr, --[in]
Bus2ip_be => bus2ip_be, --[in]
Bus2ip_data => bus2ip_data, --[in]
TC_DBus => ip2bus_data, --[out]
bus2ip_rdce => bus2ip_rdce, --[in]
bus2ip_wrce => bus2ip_wrce, --[in]
ip2bus_rdack => ip2bus_rdack, --[out]
ip2bus_wrack => ip2bus_wrack, --[out]
TC_errAck => ip2bus_error, --[out]
-- Timer/Counter signals
CaptureTrig0 => capturetrig0, --[in]
CaptureTrig1 => capturetrig1, --[in]
GenerateOut0 => generateout0, --[out]
GenerateOut1 => generateout1, --[out]
PWM0 => pwm0, --[out]
Interrupt => interrupt, --[out]
Freeze => freeze --[in]
);
---------------------------------------------------------------------------
-- INSTANTIATE AXI Lite IPIF
---------------------------------------------------------------------------
AXI4_LITE_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IP Interconnect (IPIC) port signals -------------------------------
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Resetn => bus2ip_resetn,
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
Bus2IP_RNW => open,
Bus2IP_BE => bus2ip_be,
Bus2IP_CS => open,
Bus2IP_RdCE => bus2ip_rdce,
Bus2IP_WrCE => bus2ip_wrce
);
bus2ip_reset <= not bus2ip_resetn;
end architecture imp;
| mit | 96e0a4529fda38cae246dd6d2e95568a | 0.456588 | 4.295866 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_timer_0_0/zqynq_lab_1_design_axi_timer_0_0_sim_netlist.vhdl | 1 | 419,655 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:08:02 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_timer_0_0/zqynq_lab_1_design_axi_timer_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_timer_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_cdc_sync is
port (
captureTrig0_d0 : out STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 );
capturetrig0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_cdc_sync : entity is "cdc_sync";
end zqynq_lab_1_design_axi_timer_0_0_cdc_sync;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_cdc_sync is
signal CaptureTrig0_int : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => capturetrig0,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => CaptureTrig0_int,
R => '0'
);
captureTrig0_d_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => read_Mux_In(0),
I1 => CaptureTrig0_int,
O => captureTrig0_d0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_cdc_sync_1 is
port (
captureTrig1_d0 : out STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 0 to 0 );
capturetrig1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_cdc_sync_1 : entity is "cdc_sync";
end zqynq_lab_1_design_axi_timer_0_0_cdc_sync_1;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_cdc_sync_1 is
signal CaptureTrig1_int : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => capturetrig1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => CaptureTrig1_int,
R => '0'
);
captureTrig1_d_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => read_Mux_In(0),
I1 => CaptureTrig1_int,
O => captureTrig1_d0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_cdc_sync_2 is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC;
counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 );
read_Mux_In : in STD_LOGIC_VECTOR ( 7 downto 0 );
generateOutPre0 : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC;
Load_Counter_Reg030_out : in STD_LOGIC;
Load_Counter_Reg031_out : in STD_LOGIC;
\Load_Counter_Reg0__0\ : in STD_LOGIC;
Load_Counter_Reg028_out : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_cdc_sync_2 : entity is "cdc_sync";
end zqynq_lab_1_design_axi_timer_0_0_cdc_sync_2;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_cdc_sync_2 is
signal \Counter_En041_out__2\ : STD_LOGIC;
signal \Counter_En043_out__0\ : STD_LOGIC;
signal \Counter_En045_out__1\ : STD_LOGIC;
signal \Counter_En0__4\ : STD_LOGIC;
signal Freeze_int : STD_LOGIC;
signal counter_En : STD_LOGIC_VECTOR ( 0 to 1 );
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute BOX_TYPE of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
begin
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => freeze,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_d3,
Q => Freeze_int,
R => '0'
);
\INFERRED_GEN.icount_out[31]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCFFFCAA"
)
port map (
I0 => Load_Counter_Reg030_out,
I1 => Load_Counter_Reg031_out,
I2 => \Counter_En043_out__0\,
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => \Counter_En041_out__2\,
O => E(0)
);
\INFERRED_GEN.icount_out[31]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCFFFCAA"
)
port map (
I0 => \Load_Counter_Reg0__0\,
I1 => Load_Counter_Reg028_out,
I2 => \Counter_En045_out__1\,
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => \Counter_En0__4\,
O => \INFERRED_GEN.icount_out_reg[0]\(0)
);
\INFERRED_GEN.icount_out[31]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"00FB0000"
)
port map (
I0 => read_Mux_In(4),
I1 => counter_TC(1),
I2 => read_Mux_In(6),
I3 => Freeze_int,
I4 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
O => \Counter_En043_out__0\
);
\INFERRED_GEN.icount_out[31]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4040404040004040"
)
port map (
I0 => Freeze_int,
I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
I2 => generateOutPre0,
I3 => read_Mux_In(6),
I4 => counter_TC(1),
I5 => read_Mux_In(4),
O => \Counter_En045_out__1\
);
\INFERRED_GEN.icount_out[31]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444444444444404"
)
port map (
I0 => Freeze_int,
I1 => \TCSR0_GENERATE[24].TCSR0_FF_I\,
I2 => counter_TC(0),
I3 => read_Mux_In(7),
I4 => read_Mux_In(6),
I5 => read_Mux_In(4),
O => \Counter_En041_out__2\
);
\INFERRED_GEN.icount_out[31]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2222222222202222"
)
port map (
I0 => \TCSR1_GENERATE[24].TCSR1_FF_I\,
I1 => Freeze_int,
I2 => read_Mux_In(3),
I3 => read_Mux_In(2),
I4 => counter_TC(1),
I5 => read_Mux_In(0),
O => \Counter_En0__4\
);
icount_out0_carry_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \INFERRED_GEN.icount_out_reg[1]\(1),
I1 => counter_En(0),
I2 => read_Mux_In(5),
O => S(0)
);
\icount_out0_carry_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6A666AAA"
)
port map (
I0 => \INFERRED_GEN.icount_out_reg[1]\(0),
I1 => counter_En(1),
I2 => read_Mux_In(5),
I3 => \TCSR0_GENERATE[20].TCSR0_FF_I\,
I4 => read_Mux_In(1),
O => \INFERRED_GEN.icount_out_reg[4]\(0)
);
icount_out0_carry_i_6: unisim.vcomponents.MUXF7
port map (
I0 => \Counter_En041_out__2\,
I1 => \Counter_En043_out__0\,
O => counter_En(0),
S => \TCSR0_GENERATE[20].TCSR0_FF_I\
);
\icount_out0_carry_i_6__0\: unisim.vcomponents.MUXF7
port map (
I0 => \Counter_En0__4\,
I1 => \Counter_En045_out__1\,
O => counter_En(1),
S => \TCSR0_GENERATE[20].TCSR0_FF_I\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_counter_f is
port (
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
generateOutPre1_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
read_Mux_In : in STD_LOGIC_VECTOR ( 31 downto 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\counter_TC_Reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_counter_f : entity is "counter_f";
end zqynq_lab_1_design_axi_timer_0_0_counter_f;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_counter_f is
signal \INFERRED_GEN.icount_out[0]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[10]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[11]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[12]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[13]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[14]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[15]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[16]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[17]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[18]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[19]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[1]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[20]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[21]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[22]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[23]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[24]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[25]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[26]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[27]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[28]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[29]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[2]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[30]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[31]_i_2_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[3]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[4]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[5]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[6]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[7]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[8]_i_1_n_0\ : STD_LOGIC;
signal \INFERRED_GEN.icount_out[9]_i_1_n_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \icount_out0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_1\ : STD_LOGIC;
signal \icount_out0_carry__0_n_2\ : STD_LOGIC;
signal \icount_out0_carry__0_n_3\ : STD_LOGIC;
signal \icount_out0_carry__0_n_4\ : STD_LOGIC;
signal \icount_out0_carry__0_n_5\ : STD_LOGIC;
signal \icount_out0_carry__0_n_6\ : STD_LOGIC;
signal \icount_out0_carry__0_n_7\ : STD_LOGIC;
signal \icount_out0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_1\ : STD_LOGIC;
signal \icount_out0_carry__1_n_2\ : STD_LOGIC;
signal \icount_out0_carry__1_n_3\ : STD_LOGIC;
signal \icount_out0_carry__1_n_4\ : STD_LOGIC;
signal \icount_out0_carry__1_n_5\ : STD_LOGIC;
signal \icount_out0_carry__1_n_6\ : STD_LOGIC;
signal \icount_out0_carry__1_n_7\ : STD_LOGIC;
signal \icount_out0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_1\ : STD_LOGIC;
signal \icount_out0_carry__2_n_2\ : STD_LOGIC;
signal \icount_out0_carry__2_n_3\ : STD_LOGIC;
signal \icount_out0_carry__2_n_4\ : STD_LOGIC;
signal \icount_out0_carry__2_n_5\ : STD_LOGIC;
signal \icount_out0_carry__2_n_6\ : STD_LOGIC;
signal \icount_out0_carry__2_n_7\ : STD_LOGIC;
signal \icount_out0_carry__3_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_1\ : STD_LOGIC;
signal \icount_out0_carry__3_n_2\ : STD_LOGIC;
signal \icount_out0_carry__3_n_3\ : STD_LOGIC;
signal \icount_out0_carry__3_n_4\ : STD_LOGIC;
signal \icount_out0_carry__3_n_5\ : STD_LOGIC;
signal \icount_out0_carry__3_n_6\ : STD_LOGIC;
signal \icount_out0_carry__3_n_7\ : STD_LOGIC;
signal \icount_out0_carry__4_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_1\ : STD_LOGIC;
signal \icount_out0_carry__4_n_2\ : STD_LOGIC;
signal \icount_out0_carry__4_n_3\ : STD_LOGIC;
signal \icount_out0_carry__4_n_4\ : STD_LOGIC;
signal \icount_out0_carry__4_n_5\ : STD_LOGIC;
signal \icount_out0_carry__4_n_6\ : STD_LOGIC;
signal \icount_out0_carry__4_n_7\ : STD_LOGIC;
signal \icount_out0_carry__5_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_1\ : STD_LOGIC;
signal \icount_out0_carry__5_n_2\ : STD_LOGIC;
signal \icount_out0_carry__5_n_3\ : STD_LOGIC;
signal \icount_out0_carry__5_n_4\ : STD_LOGIC;
signal \icount_out0_carry__5_n_5\ : STD_LOGIC;
signal \icount_out0_carry__5_n_6\ : STD_LOGIC;
signal \icount_out0_carry__5_n_7\ : STD_LOGIC;
signal \icount_out0_carry__6_i_1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_n_1\ : STD_LOGIC;
signal \icount_out0_carry__6_n_2\ : STD_LOGIC;
signal \icount_out0_carry__6_n_3\ : STD_LOGIC;
signal \icount_out0_carry__6_n_4\ : STD_LOGIC;
signal \icount_out0_carry__6_n_5\ : STD_LOGIC;
signal \icount_out0_carry__6_n_6\ : STD_LOGIC;
signal \icount_out0_carry__6_n_7\ : STD_LOGIC;
signal icount_out0_carry_i_1_n_0 : STD_LOGIC;
signal icount_out0_carry_i_2_n_0 : STD_LOGIC;
signal icount_out0_carry_i_3_n_0 : STD_LOGIC;
signal icount_out0_carry_i_4_n_0 : STD_LOGIC;
signal icount_out0_carry_n_0 : STD_LOGIC;
signal icount_out0_carry_n_1 : STD_LOGIC;
signal icount_out0_carry_n_2 : STD_LOGIC;
signal icount_out0_carry_n_3 : STD_LOGIC;
signal icount_out0_carry_n_4 : STD_LOGIC;
signal icount_out0_carry_n_5 : STD_LOGIC;
signal icount_out0_carry_n_6 : STD_LOGIC;
signal icount_out0_carry_n_7 : STD_LOGIC;
signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1\ : label is "soft_lutpair45";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
Q(31 downto 0) <= \^q\(31 downto 0);
SR(0) <= \^sr\(0);
counter_TC(0) <= \^counter_tc\(0);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(31),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(31),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(31),
O => \s_axi_rdata_i_reg[31]\
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(21),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(21),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(21),
O => \s_axi_rdata_i_reg[21]\
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(20),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(20),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(20),
O => \s_axi_rdata_i_reg[20]\
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(19),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(19),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(19),
O => \s_axi_rdata_i_reg[19]\
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(18),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(18),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(18),
O => \s_axi_rdata_i_reg[18]\
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(17),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(17),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(17),
O => \s_axi_rdata_i_reg[17]\
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(16),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(16),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(16),
O => \s_axi_rdata_i_reg[16]\
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(15),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(15),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(15),
O => \s_axi_rdata_i_reg[15]\
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(14),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(14),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(14),
O => \s_axi_rdata_i_reg[14]\
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(13),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(13),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(13),
O => \s_axi_rdata_i_reg[13]\
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(12),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(12),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(12),
O => \s_axi_rdata_i_reg[12]\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(30),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(30),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(30),
O => \s_axi_rdata_i_reg[30]\
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(11),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(11),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(11),
O => \s_axi_rdata_i_reg[11]\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(10),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(10),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(10),
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(9),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(9),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(9),
O => \s_axi_rdata_i_reg[9]\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(8),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(8),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(8),
O => \s_axi_rdata_i_reg[8]\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(7),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(7),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(7),
O => \s_axi_rdata_i_reg[7]\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(6),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(6),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(6),
O => \s_axi_rdata_i_reg[6]\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(5),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(5),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(5),
O => \s_axi_rdata_i_reg[5]\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(4),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(4),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(4),
O => \s_axi_rdata_i_reg[4]\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(3),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(3),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(3),
O => \s_axi_rdata_i_reg[3]\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(2),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(2),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(2),
O => \s_axi_rdata_i_reg[2]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(29),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(29),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(29),
O => \s_axi_rdata_i_reg[29]\
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(1),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(1),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(1),
O => \s_axi_rdata_i_reg[1]\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(0),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(0),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(0),
O => \s_axi_rdata_i_reg[0]\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(28),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(28),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(28),
O => \s_axi_rdata_i_reg[28]\
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(27),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(27),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(27),
O => \s_axi_rdata_i_reg[27]\
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(26),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(26),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(26),
O => \s_axi_rdata_i_reg[26]\
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(25),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(25),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(25),
O => \s_axi_rdata_i_reg[25]\
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(24),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(24),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(24),
O => \s_axi_rdata_i_reg[24]\
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(23),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(23),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(23),
O => \s_axi_rdata_i_reg[23]\
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \^q\(22),
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
I3 => read_Mux_In(22),
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
I5 => \INFERRED_GEN.icount_out_reg[31]_0\(22),
O => \s_axi_rdata_i_reg[22]\
);
GenerateOut0_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\INFERRED_GEN.icount_out[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"A3"
)
port map (
I0 => read_Mux_In(0),
I1 => \^q\(0),
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[0]_i_1_n_0\
);
\INFERRED_GEN.icount_out[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(10),
I1 => \icount_out0_carry__1_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[10]_i_1_n_0\
);
\INFERRED_GEN.icount_out[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(11),
I1 => \icount_out0_carry__1_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[11]_i_1_n_0\
);
\INFERRED_GEN.icount_out[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(12),
I1 => \icount_out0_carry__1_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[12]_i_1_n_0\
);
\INFERRED_GEN.icount_out[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(13),
I1 => \icount_out0_carry__2_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[13]_i_1_n_0\
);
\INFERRED_GEN.icount_out[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(14),
I1 => \icount_out0_carry__2_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[14]_i_1_n_0\
);
\INFERRED_GEN.icount_out[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(15),
I1 => \icount_out0_carry__2_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[15]_i_1_n_0\
);
\INFERRED_GEN.icount_out[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(16),
I1 => \icount_out0_carry__2_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[16]_i_1_n_0\
);
\INFERRED_GEN.icount_out[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(17),
I1 => \icount_out0_carry__3_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[17]_i_1_n_0\
);
\INFERRED_GEN.icount_out[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(18),
I1 => \icount_out0_carry__3_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[18]_i_1_n_0\
);
\INFERRED_GEN.icount_out[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(19),
I1 => \icount_out0_carry__3_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[19]_i_1_n_0\
);
\INFERRED_GEN.icount_out[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(1),
I1 => icount_out0_carry_n_7,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[1]_i_1_n_0\
);
\INFERRED_GEN.icount_out[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(20),
I1 => \icount_out0_carry__3_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[20]_i_1_n_0\
);
\INFERRED_GEN.icount_out[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(21),
I1 => \icount_out0_carry__4_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[21]_i_1_n_0\
);
\INFERRED_GEN.icount_out[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(22),
I1 => \icount_out0_carry__4_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[22]_i_1_n_0\
);
\INFERRED_GEN.icount_out[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(23),
I1 => \icount_out0_carry__4_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[23]_i_1_n_0\
);
\INFERRED_GEN.icount_out[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(24),
I1 => \icount_out0_carry__4_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[24]_i_1_n_0\
);
\INFERRED_GEN.icount_out[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(25),
I1 => \icount_out0_carry__5_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[25]_i_1_n_0\
);
\INFERRED_GEN.icount_out[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(26),
I1 => \icount_out0_carry__5_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[26]_i_1_n_0\
);
\INFERRED_GEN.icount_out[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(27),
I1 => \icount_out0_carry__5_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[27]_i_1_n_0\
);
\INFERRED_GEN.icount_out[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(28),
I1 => \icount_out0_carry__5_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[28]_i_1_n_0\
);
\INFERRED_GEN.icount_out[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(29),
I1 => \icount_out0_carry__6_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[29]_i_1_n_0\
);
\INFERRED_GEN.icount_out[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(2),
I1 => icount_out0_carry_n_6,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[2]_i_1_n_0\
);
\INFERRED_GEN.icount_out[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(30),
I1 => \icount_out0_carry__6_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[30]_i_1_n_0\
);
\INFERRED_GEN.icount_out[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(31),
I1 => \icount_out0_carry__6_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[31]_i_2_n_0\
);
\INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E200"
)
port map (
I0 => \^counter_tc\(0),
I1 => E(0),
I2 => \icount_out0_carry__6_n_4\,
I3 => s_axi_aresetn,
I4 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[32]_i_1_n_0\
);
\INFERRED_GEN.icount_out[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(3),
I1 => icount_out0_carry_n_5,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[3]_i_1_n_0\
);
\INFERRED_GEN.icount_out[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(4),
I1 => icount_out0_carry_n_4,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[4]_i_1_n_0\
);
\INFERRED_GEN.icount_out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(5),
I1 => \icount_out0_carry__0_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[5]_i_1_n_0\
);
\INFERRED_GEN.icount_out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(6),
I1 => \icount_out0_carry__0_n_6\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[6]_i_1_n_0\
);
\INFERRED_GEN.icount_out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(7),
I1 => \icount_out0_carry__0_n_5\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[7]_i_1_n_0\
);
\INFERRED_GEN.icount_out[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(8),
I1 => \icount_out0_carry__0_n_4\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[8]_i_1_n_0\
);
\INFERRED_GEN.icount_out[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => read_Mux_In(9),
I1 => \icount_out0_carry__1_n_7\,
I2 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[9]_i_1_n_0\
);
\INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[0]_i_1_n_0\,
Q => \^q\(0),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[10]_i_1_n_0\,
Q => \^q\(10),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[11]_i_1_n_0\,
Q => \^q\(11),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[12]_i_1_n_0\,
Q => \^q\(12),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[13]_i_1_n_0\,
Q => \^q\(13),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[14]_i_1_n_0\,
Q => \^q\(14),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[15]_i_1_n_0\,
Q => \^q\(15),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[16]_i_1_n_0\,
Q => \^q\(16),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[17]_i_1_n_0\,
Q => \^q\(17),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[18]_i_1_n_0\,
Q => \^q\(18),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[19]_i_1_n_0\,
Q => \^q\(19),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[1]_i_1_n_0\,
Q => \^q\(1),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[20]_i_1_n_0\,
Q => \^q\(20),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[21]_i_1_n_0\,
Q => \^q\(21),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[22]_i_1_n_0\,
Q => \^q\(22),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[23]_i_1_n_0\,
Q => \^q\(23),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[24]_i_1_n_0\,
Q => \^q\(24),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[25]_i_1_n_0\,
Q => \^q\(25),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[26]_i_1_n_0\,
Q => \^q\(26),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[27]_i_1_n_0\,
Q => \^q\(27),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[28]_i_1_n_0\,
Q => \^q\(28),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[29]_i_1_n_0\,
Q => \^q\(29),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[2]_i_1_n_0\,
Q => \^q\(2),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[30]_i_1_n_0\,
Q => \^q\(30),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[31]_i_2_n_0\,
Q => \^q\(31),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out[32]_i_1_n_0\,
Q => \^counter_tc\(0),
R => '0'
);
\INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[3]_i_1_n_0\,
Q => \^q\(3),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[4]_i_1_n_0\,
Q => \^q\(4),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[5]_i_1_n_0\,
Q => \^q\(5),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[6]_i_1_n_0\,
Q => \^q\(6),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[7]_i_1_n_0\,
Q => \^q\(7),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[8]_i_1_n_0\,
Q => \^q\(8),
R => \^sr\(0)
);
\INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => \INFERRED_GEN.icount_out[9]_i_1_n_0\,
Q => \^q\(9),
R => \^sr\(0)
);
generateOutPre1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^counter_tc\(0),
I1 => \counter_TC_Reg_reg[1]\(0),
O => generateOutPre1_reg
);
icount_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => icount_out0_carry_n_0,
CO(2) => icount_out0_carry_n_1,
CO(1) => icount_out0_carry_n_2,
CO(0) => icount_out0_carry_n_3,
CYINIT => \^q\(0),
DI(3 downto 1) => \^q\(3 downto 1),
DI(0) => icount_out0_carry_i_1_n_0,
O(3) => icount_out0_carry_n_4,
O(2) => icount_out0_carry_n_5,
O(1) => icount_out0_carry_n_6,
O(0) => icount_out0_carry_n_7,
S(3) => icount_out0_carry_i_2_n_0,
S(2) => icount_out0_carry_i_3_n_0,
S(1) => icount_out0_carry_i_4_n_0,
S(0) => S(0)
);
\icount_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => icount_out0_carry_n_0,
CO(3) => \icount_out0_carry__0_n_0\,
CO(2) => \icount_out0_carry__0_n_1\,
CO(1) => \icount_out0_carry__0_n_2\,
CO(0) => \icount_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(7 downto 4),
O(3) => \icount_out0_carry__0_n_4\,
O(2) => \icount_out0_carry__0_n_5\,
O(1) => \icount_out0_carry__0_n_6\,
O(0) => \icount_out0_carry__0_n_7\,
S(3) => \icount_out0_carry__0_i_1_n_0\,
S(2) => \icount_out0_carry__0_i_2_n_0\,
S(1) => \icount_out0_carry__0_i_3_n_0\,
S(0) => \icount_out0_carry__0_i_4_n_0\
);
\icount_out0_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => \^q\(8),
O => \icount_out0_carry__0_i_1_n_0\
);
\icount_out0_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => \^q\(7),
O => \icount_out0_carry__0_i_2_n_0\
);
\icount_out0_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => \^q\(6),
O => \icount_out0_carry__0_i_3_n_0\
);
\icount_out0_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => \^q\(5),
O => \icount_out0_carry__0_i_4_n_0\
);
\icount_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__0_n_0\,
CO(3) => \icount_out0_carry__1_n_0\,
CO(2) => \icount_out0_carry__1_n_1\,
CO(1) => \icount_out0_carry__1_n_2\,
CO(0) => \icount_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(11 downto 8),
O(3) => \icount_out0_carry__1_n_4\,
O(2) => \icount_out0_carry__1_n_5\,
O(1) => \icount_out0_carry__1_n_6\,
O(0) => \icount_out0_carry__1_n_7\,
S(3) => \icount_out0_carry__1_i_1_n_0\,
S(2) => \icount_out0_carry__1_i_2_n_0\,
S(1) => \icount_out0_carry__1_i_3_n_0\,
S(0) => \icount_out0_carry__1_i_4_n_0\
);
\icount_out0_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(11),
I1 => \^q\(12),
O => \icount_out0_carry__1_i_1_n_0\
);
\icount_out0_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => \^q\(11),
O => \icount_out0_carry__1_i_2_n_0\
);
\icount_out0_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(9),
I1 => \^q\(10),
O => \icount_out0_carry__1_i_3_n_0\
);
\icount_out0_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => \^q\(9),
O => \icount_out0_carry__1_i_4_n_0\
);
\icount_out0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__1_n_0\,
CO(3) => \icount_out0_carry__2_n_0\,
CO(2) => \icount_out0_carry__2_n_1\,
CO(1) => \icount_out0_carry__2_n_2\,
CO(0) => \icount_out0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(15 downto 12),
O(3) => \icount_out0_carry__2_n_4\,
O(2) => \icount_out0_carry__2_n_5\,
O(1) => \icount_out0_carry__2_n_6\,
O(0) => \icount_out0_carry__2_n_7\,
S(3) => \icount_out0_carry__2_i_1_n_0\,
S(2) => \icount_out0_carry__2_i_2_n_0\,
S(1) => \icount_out0_carry__2_i_3_n_0\,
S(0) => \icount_out0_carry__2_i_4_n_0\
);
\icount_out0_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(15),
I1 => \^q\(16),
O => \icount_out0_carry__2_i_1_n_0\
);
\icount_out0_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(14),
I1 => \^q\(15),
O => \icount_out0_carry__2_i_2_n_0\
);
\icount_out0_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(13),
I1 => \^q\(14),
O => \icount_out0_carry__2_i_3_n_0\
);
\icount_out0_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(12),
I1 => \^q\(13),
O => \icount_out0_carry__2_i_4_n_0\
);
\icount_out0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__2_n_0\,
CO(3) => \icount_out0_carry__3_n_0\,
CO(2) => \icount_out0_carry__3_n_1\,
CO(1) => \icount_out0_carry__3_n_2\,
CO(0) => \icount_out0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(19 downto 16),
O(3) => \icount_out0_carry__3_n_4\,
O(2) => \icount_out0_carry__3_n_5\,
O(1) => \icount_out0_carry__3_n_6\,
O(0) => \icount_out0_carry__3_n_7\,
S(3) => \icount_out0_carry__3_i_1_n_0\,
S(2) => \icount_out0_carry__3_i_2_n_0\,
S(1) => \icount_out0_carry__3_i_3_n_0\,
S(0) => \icount_out0_carry__3_i_4_n_0\
);
\icount_out0_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(19),
I1 => \^q\(20),
O => \icount_out0_carry__3_i_1_n_0\
);
\icount_out0_carry__3_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(18),
I1 => \^q\(19),
O => \icount_out0_carry__3_i_2_n_0\
);
\icount_out0_carry__3_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(17),
I1 => \^q\(18),
O => \icount_out0_carry__3_i_3_n_0\
);
\icount_out0_carry__3_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(16),
I1 => \^q\(17),
O => \icount_out0_carry__3_i_4_n_0\
);
\icount_out0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__3_n_0\,
CO(3) => \icount_out0_carry__4_n_0\,
CO(2) => \icount_out0_carry__4_n_1\,
CO(1) => \icount_out0_carry__4_n_2\,
CO(0) => \icount_out0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(23 downto 20),
O(3) => \icount_out0_carry__4_n_4\,
O(2) => \icount_out0_carry__4_n_5\,
O(1) => \icount_out0_carry__4_n_6\,
O(0) => \icount_out0_carry__4_n_7\,
S(3) => \icount_out0_carry__4_i_1_n_0\,
S(2) => \icount_out0_carry__4_i_2_n_0\,
S(1) => \icount_out0_carry__4_i_3_n_0\,
S(0) => \icount_out0_carry__4_i_4_n_0\
);
\icount_out0_carry__4_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(23),
I1 => \^q\(24),
O => \icount_out0_carry__4_i_1_n_0\
);
\icount_out0_carry__4_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(22),
I1 => \^q\(23),
O => \icount_out0_carry__4_i_2_n_0\
);
\icount_out0_carry__4_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(21),
I1 => \^q\(22),
O => \icount_out0_carry__4_i_3_n_0\
);
\icount_out0_carry__4_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(20),
I1 => \^q\(21),
O => \icount_out0_carry__4_i_4_n_0\
);
\icount_out0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__4_n_0\,
CO(3) => \icount_out0_carry__5_n_0\,
CO(2) => \icount_out0_carry__5_n_1\,
CO(1) => \icount_out0_carry__5_n_2\,
CO(0) => \icount_out0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^q\(27 downto 24),
O(3) => \icount_out0_carry__5_n_4\,
O(2) => \icount_out0_carry__5_n_5\,
O(1) => \icount_out0_carry__5_n_6\,
O(0) => \icount_out0_carry__5_n_7\,
S(3) => \icount_out0_carry__5_i_1_n_0\,
S(2) => \icount_out0_carry__5_i_2_n_0\,
S(1) => \icount_out0_carry__5_i_3_n_0\,
S(0) => \icount_out0_carry__5_i_4_n_0\
);
\icount_out0_carry__5_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(27),
I1 => \^q\(28),
O => \icount_out0_carry__5_i_1_n_0\
);
\icount_out0_carry__5_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(26),
I1 => \^q\(27),
O => \icount_out0_carry__5_i_2_n_0\
);
\icount_out0_carry__5_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(25),
I1 => \^q\(26),
O => \icount_out0_carry__5_i_3_n_0\
);
\icount_out0_carry__5_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(24),
I1 => \^q\(25),
O => \icount_out0_carry__5_i_4_n_0\
);
\icount_out0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__5_n_0\,
CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \icount_out0_carry__6_n_1\,
CO(1) => \icount_out0_carry__6_n_2\,
CO(0) => \icount_out0_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \^q\(30 downto 28),
O(3) => \icount_out0_carry__6_n_4\,
O(2) => \icount_out0_carry__6_n_5\,
O(1) => \icount_out0_carry__6_n_6\,
O(0) => \icount_out0_carry__6_n_7\,
S(3) => \icount_out0_carry__6_i_1_n_0\,
S(2) => \icount_out0_carry__6_i_2_n_0\,
S(1) => \icount_out0_carry__6_i_3_n_0\,
S(0) => \icount_out0_carry__6_i_4_n_0\
);
\icount_out0_carry__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(31),
O => \icount_out0_carry__6_i_1_n_0\
);
\icount_out0_carry__6_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(30),
I1 => \^q\(31),
O => \icount_out0_carry__6_i_2_n_0\
);
\icount_out0_carry__6_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(29),
I1 => \^q\(30),
O => \icount_out0_carry__6_i_3_n_0\
);
\icount_out0_carry__6_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(28),
I1 => \^q\(29),
O => \icount_out0_carry__6_i_4_n_0\
);
icount_out0_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(1),
O => icount_out0_carry_i_1_n_0
);
icount_out0_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => \^q\(4),
O => icount_out0_carry_i_2_n_0
);
icount_out0_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => \^q\(3),
O => icount_out0_carry_i_3_n_0
);
icount_out0_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => \^q\(2),
O => icount_out0_carry_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_counter_f_3 is
port (
\LOAD_REG_GEN[0].LOAD_REG_I\ : out STD_LOGIC_VECTOR ( 31 downto 0 );
generateOutPre0_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
S : in STD_LOGIC_VECTOR ( 0 to 0 );
read_Mux_In : in STD_LOGIC_VECTOR ( 10 downto 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\LOAD_REG_GEN[0].LOAD_REG_I_0\ : in STD_LOGIC_VECTOR ( 20 downto 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn_0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_counter_f_3 : entity is "counter_f";
end zqynq_lab_1_design_axi_timer_0_0_counter_f_3;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_counter_f_3 is
signal \INFERRED_GEN.icount_out[32]_i_1_n_0\ : STD_LOGIC;
signal \^load_reg_gen[0].load_reg_i\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^counter_tc\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \icount_out0_carry__0_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__0_n_1\ : STD_LOGIC;
signal \icount_out0_carry__0_n_2\ : STD_LOGIC;
signal \icount_out0_carry__0_n_3\ : STD_LOGIC;
signal \icount_out0_carry__0_n_4\ : STD_LOGIC;
signal \icount_out0_carry__0_n_5\ : STD_LOGIC;
signal \icount_out0_carry__0_n_6\ : STD_LOGIC;
signal \icount_out0_carry__0_n_7\ : STD_LOGIC;
signal \icount_out0_carry__1_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_0\ : STD_LOGIC;
signal \icount_out0_carry__1_n_1\ : STD_LOGIC;
signal \icount_out0_carry__1_n_2\ : STD_LOGIC;
signal \icount_out0_carry__1_n_3\ : STD_LOGIC;
signal \icount_out0_carry__1_n_4\ : STD_LOGIC;
signal \icount_out0_carry__1_n_5\ : STD_LOGIC;
signal \icount_out0_carry__1_n_6\ : STD_LOGIC;
signal \icount_out0_carry__1_n_7\ : STD_LOGIC;
signal \icount_out0_carry__2_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_0\ : STD_LOGIC;
signal \icount_out0_carry__2_n_1\ : STD_LOGIC;
signal \icount_out0_carry__2_n_2\ : STD_LOGIC;
signal \icount_out0_carry__2_n_3\ : STD_LOGIC;
signal \icount_out0_carry__2_n_4\ : STD_LOGIC;
signal \icount_out0_carry__2_n_5\ : STD_LOGIC;
signal \icount_out0_carry__2_n_6\ : STD_LOGIC;
signal \icount_out0_carry__2_n_7\ : STD_LOGIC;
signal \icount_out0_carry__3_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_0\ : STD_LOGIC;
signal \icount_out0_carry__3_n_1\ : STD_LOGIC;
signal \icount_out0_carry__3_n_2\ : STD_LOGIC;
signal \icount_out0_carry__3_n_3\ : STD_LOGIC;
signal \icount_out0_carry__3_n_4\ : STD_LOGIC;
signal \icount_out0_carry__3_n_5\ : STD_LOGIC;
signal \icount_out0_carry__3_n_6\ : STD_LOGIC;
signal \icount_out0_carry__3_n_7\ : STD_LOGIC;
signal \icount_out0_carry__4_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_0\ : STD_LOGIC;
signal \icount_out0_carry__4_n_1\ : STD_LOGIC;
signal \icount_out0_carry__4_n_2\ : STD_LOGIC;
signal \icount_out0_carry__4_n_3\ : STD_LOGIC;
signal \icount_out0_carry__4_n_4\ : STD_LOGIC;
signal \icount_out0_carry__4_n_5\ : STD_LOGIC;
signal \icount_out0_carry__4_n_6\ : STD_LOGIC;
signal \icount_out0_carry__4_n_7\ : STD_LOGIC;
signal \icount_out0_carry__5_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_0\ : STD_LOGIC;
signal \icount_out0_carry__5_n_1\ : STD_LOGIC;
signal \icount_out0_carry__5_n_2\ : STD_LOGIC;
signal \icount_out0_carry__5_n_3\ : STD_LOGIC;
signal \icount_out0_carry__5_n_4\ : STD_LOGIC;
signal \icount_out0_carry__5_n_5\ : STD_LOGIC;
signal \icount_out0_carry__5_n_6\ : STD_LOGIC;
signal \icount_out0_carry__5_n_7\ : STD_LOGIC;
signal \icount_out0_carry__6_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_i_4__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry__6_n_1\ : STD_LOGIC;
signal \icount_out0_carry__6_n_2\ : STD_LOGIC;
signal \icount_out0_carry__6_n_3\ : STD_LOGIC;
signal \icount_out0_carry__6_n_4\ : STD_LOGIC;
signal \icount_out0_carry__6_n_5\ : STD_LOGIC;
signal \icount_out0_carry__6_n_6\ : STD_LOGIC;
signal \icount_out0_carry__6_n_7\ : STD_LOGIC;
signal \icount_out0_carry_i_1__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_2__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_3__0_n_0\ : STD_LOGIC;
signal \icount_out0_carry_i_4__0_n_0\ : STD_LOGIC;
signal icount_out0_carry_n_0 : STD_LOGIC;
signal icount_out0_carry_n_1 : STD_LOGIC;
signal icount_out0_carry_n_2 : STD_LOGIC;
signal icount_out0_carry_n_3 : STD_LOGIC;
signal icount_out0_carry_n_4 : STD_LOGIC;
signal icount_out0_carry_n_5 : STD_LOGIC;
signal icount_out0_carry_n_6 : STD_LOGIC;
signal icount_out0_carry_n_7 : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_icount_out0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[0]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[10]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[11]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[12]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[13]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[14]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[15]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[16]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[17]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[18]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[19]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[1]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[20]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[21]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[22]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[23]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[24]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[25]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[26]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[27]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[28]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[29]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[2]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[30]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_2__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[3]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[4]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[5]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[6]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[7]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[8]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[9]_i_1__0\ : label is "soft_lutpair29";
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of icount_out0_carry : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__0\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__1\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__2\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__3\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__4\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__5\ : label is "{SYNTH-8 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \icount_out0_carry__6\ : label is "{SYNTH-8 {cell *THIS*}}";
begin
\LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) <= \^load_reg_gen[0].load_reg_i\(31 downto 0);
counter_TC(0) <= \^counter_tc\(0);
\INFERRED_GEN.icount_out[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8B"
)
port map (
I0 => read_Mux_In(0),
I1 => load_Counter_Reg(0),
I2 => \^load_reg_gen[0].load_reg_i\(0),
O => p_1_in(0)
);
\INFERRED_GEN.icount_out[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(10),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_6\,
O => p_1_in(10)
);
\INFERRED_GEN.icount_out[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(0),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_5\,
O => p_1_in(11)
);
\INFERRED_GEN.icount_out[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(1),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_4\,
O => p_1_in(12)
);
\INFERRED_GEN.icount_out[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(2),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_7\,
O => p_1_in(13)
);
\INFERRED_GEN.icount_out[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(3),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_6\,
O => p_1_in(14)
);
\INFERRED_GEN.icount_out[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(4),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_5\,
O => p_1_in(15)
);
\INFERRED_GEN.icount_out[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(5),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__2_n_4\,
O => p_1_in(16)
);
\INFERRED_GEN.icount_out[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(6),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_7\,
O => p_1_in(17)
);
\INFERRED_GEN.icount_out[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(7),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_6\,
O => p_1_in(18)
);
\INFERRED_GEN.icount_out[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(8),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_5\,
O => p_1_in(19)
);
\INFERRED_GEN.icount_out[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(1),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_7,
O => p_1_in(1)
);
\INFERRED_GEN.icount_out[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(9),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__3_n_4\,
O => p_1_in(20)
);
\INFERRED_GEN.icount_out[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(10),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_7\,
O => p_1_in(21)
);
\INFERRED_GEN.icount_out[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(11),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_6\,
O => p_1_in(22)
);
\INFERRED_GEN.icount_out[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(12),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_5\,
O => p_1_in(23)
);
\INFERRED_GEN.icount_out[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(13),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__4_n_4\,
O => p_1_in(24)
);
\INFERRED_GEN.icount_out[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(14),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_7\,
O => p_1_in(25)
);
\INFERRED_GEN.icount_out[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(15),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_6\,
O => p_1_in(26)
);
\INFERRED_GEN.icount_out[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(16),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_5\,
O => p_1_in(27)
);
\INFERRED_GEN.icount_out[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(17),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__5_n_4\,
O => p_1_in(28)
);
\INFERRED_GEN.icount_out[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(18),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_7\,
O => p_1_in(29)
);
\INFERRED_GEN.icount_out[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(2),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_6,
O => p_1_in(2)
);
\INFERRED_GEN.icount_out[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(19),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_6\,
O => p_1_in(30)
);
\INFERRED_GEN.icount_out[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_0\(20),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__6_n_5\,
O => p_1_in(31)
);
\INFERRED_GEN.icount_out[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000E200"
)
port map (
I0 => \^counter_tc\(0),
I1 => E(0),
I2 => \icount_out0_carry__6_n_4\,
I3 => s_axi_aresetn,
I4 => load_Counter_Reg(0),
O => \INFERRED_GEN.icount_out[32]_i_1_n_0\
);
\INFERRED_GEN.icount_out[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(3),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_5,
O => p_1_in(3)
);
\INFERRED_GEN.icount_out[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(4),
I1 => load_Counter_Reg(0),
I2 => icount_out0_carry_n_4,
O => p_1_in(4)
);
\INFERRED_GEN.icount_out[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(5),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_7\,
O => p_1_in(5)
);
\INFERRED_GEN.icount_out[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(6),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_6\,
O => p_1_in(6)
);
\INFERRED_GEN.icount_out[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(7),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_5\,
O => p_1_in(7)
);
\INFERRED_GEN.icount_out[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(8),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__0_n_4\,
O => p_1_in(8)
);
\INFERRED_GEN.icount_out[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => read_Mux_In(9),
I1 => load_Counter_Reg(0),
I2 => \icount_out0_carry__1_n_7\,
O => p_1_in(9)
);
\INFERRED_GEN.icount_out_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(0),
Q => \^load_reg_gen[0].load_reg_i\(0),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(10),
Q => \^load_reg_gen[0].load_reg_i\(10),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(11),
Q => \^load_reg_gen[0].load_reg_i\(11),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(12),
Q => \^load_reg_gen[0].load_reg_i\(12),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(13),
Q => \^load_reg_gen[0].load_reg_i\(13),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(14),
Q => \^load_reg_gen[0].load_reg_i\(14),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(15),
Q => \^load_reg_gen[0].load_reg_i\(15),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(16),
Q => \^load_reg_gen[0].load_reg_i\(16),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(17),
Q => \^load_reg_gen[0].load_reg_i\(17),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(18),
Q => \^load_reg_gen[0].load_reg_i\(18),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(19),
Q => \^load_reg_gen[0].load_reg_i\(19),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(1),
Q => \^load_reg_gen[0].load_reg_i\(1),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(20),
Q => \^load_reg_gen[0].load_reg_i\(20),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(21),
Q => \^load_reg_gen[0].load_reg_i\(21),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(22),
Q => \^load_reg_gen[0].load_reg_i\(22),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(23),
Q => \^load_reg_gen[0].load_reg_i\(23),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(24),
Q => \^load_reg_gen[0].load_reg_i\(24),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(25),
Q => \^load_reg_gen[0].load_reg_i\(25),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(26),
Q => \^load_reg_gen[0].load_reg_i\(26),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(27),
Q => \^load_reg_gen[0].load_reg_i\(27),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(28),
Q => \^load_reg_gen[0].load_reg_i\(28),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(29),
Q => \^load_reg_gen[0].load_reg_i\(29),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(2),
Q => \^load_reg_gen[0].load_reg_i\(2),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(30),
Q => \^load_reg_gen[0].load_reg_i\(30),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(31),
Q => \^load_reg_gen[0].load_reg_i\(31),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[32]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out[32]_i_1_n_0\,
Q => \^counter_tc\(0),
R => '0'
);
\INFERRED_GEN.icount_out_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(3),
Q => \^load_reg_gen[0].load_reg_i\(3),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(4),
Q => \^load_reg_gen[0].load_reg_i\(4),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(5),
Q => \^load_reg_gen[0].load_reg_i\(5),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(6),
Q => \^load_reg_gen[0].load_reg_i\(6),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(7),
Q => \^load_reg_gen[0].load_reg_i\(7),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(8),
Q => \^load_reg_gen[0].load_reg_i\(8),
R => s_axi_aresetn_0
);
\INFERRED_GEN.icount_out_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => E(0),
D => p_1_in(9),
Q => \^load_reg_gen[0].load_reg_i\(9),
R => s_axi_aresetn_0
);
generateOutPre0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^counter_tc\(0),
I1 => Q(0),
O => generateOutPre0_reg
);
icount_out0_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => icount_out0_carry_n_0,
CO(2) => icount_out0_carry_n_1,
CO(1) => icount_out0_carry_n_2,
CO(0) => icount_out0_carry_n_3,
CYINIT => \^load_reg_gen[0].load_reg_i\(0),
DI(3 downto 1) => \^load_reg_gen[0].load_reg_i\(3 downto 1),
DI(0) => \icount_out0_carry_i_1__0_n_0\,
O(3) => icount_out0_carry_n_4,
O(2) => icount_out0_carry_n_5,
O(1) => icount_out0_carry_n_6,
O(0) => icount_out0_carry_n_7,
S(3) => \icount_out0_carry_i_2__0_n_0\,
S(2) => \icount_out0_carry_i_3__0_n_0\,
S(1) => \icount_out0_carry_i_4__0_n_0\,
S(0) => S(0)
);
\icount_out0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => icount_out0_carry_n_0,
CO(3) => \icount_out0_carry__0_n_0\,
CO(2) => \icount_out0_carry__0_n_1\,
CO(1) => \icount_out0_carry__0_n_2\,
CO(0) => \icount_out0_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(7 downto 4),
O(3) => \icount_out0_carry__0_n_4\,
O(2) => \icount_out0_carry__0_n_5\,
O(1) => \icount_out0_carry__0_n_6\,
O(0) => \icount_out0_carry__0_n_7\,
S(3) => \icount_out0_carry__0_i_1__0_n_0\,
S(2) => \icount_out0_carry__0_i_2__0_n_0\,
S(1) => \icount_out0_carry__0_i_3__0_n_0\,
S(0) => \icount_out0_carry__0_i_4__0_n_0\
);
\icount_out0_carry__0_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(7),
I1 => \^load_reg_gen[0].load_reg_i\(8),
O => \icount_out0_carry__0_i_1__0_n_0\
);
\icount_out0_carry__0_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(6),
I1 => \^load_reg_gen[0].load_reg_i\(7),
O => \icount_out0_carry__0_i_2__0_n_0\
);
\icount_out0_carry__0_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(5),
I1 => \^load_reg_gen[0].load_reg_i\(6),
O => \icount_out0_carry__0_i_3__0_n_0\
);
\icount_out0_carry__0_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(4),
I1 => \^load_reg_gen[0].load_reg_i\(5),
O => \icount_out0_carry__0_i_4__0_n_0\
);
\icount_out0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__0_n_0\,
CO(3) => \icount_out0_carry__1_n_0\,
CO(2) => \icount_out0_carry__1_n_1\,
CO(1) => \icount_out0_carry__1_n_2\,
CO(0) => \icount_out0_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(11 downto 8),
O(3) => \icount_out0_carry__1_n_4\,
O(2) => \icount_out0_carry__1_n_5\,
O(1) => \icount_out0_carry__1_n_6\,
O(0) => \icount_out0_carry__1_n_7\,
S(3) => \icount_out0_carry__1_i_1__0_n_0\,
S(2) => \icount_out0_carry__1_i_2__0_n_0\,
S(1) => \icount_out0_carry__1_i_3__0_n_0\,
S(0) => \icount_out0_carry__1_i_4__0_n_0\
);
\icount_out0_carry__1_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(11),
I1 => \^load_reg_gen[0].load_reg_i\(12),
O => \icount_out0_carry__1_i_1__0_n_0\
);
\icount_out0_carry__1_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(10),
I1 => \^load_reg_gen[0].load_reg_i\(11),
O => \icount_out0_carry__1_i_2__0_n_0\
);
\icount_out0_carry__1_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(9),
I1 => \^load_reg_gen[0].load_reg_i\(10),
O => \icount_out0_carry__1_i_3__0_n_0\
);
\icount_out0_carry__1_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(8),
I1 => \^load_reg_gen[0].load_reg_i\(9),
O => \icount_out0_carry__1_i_4__0_n_0\
);
\icount_out0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__1_n_0\,
CO(3) => \icount_out0_carry__2_n_0\,
CO(2) => \icount_out0_carry__2_n_1\,
CO(1) => \icount_out0_carry__2_n_2\,
CO(0) => \icount_out0_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(15 downto 12),
O(3) => \icount_out0_carry__2_n_4\,
O(2) => \icount_out0_carry__2_n_5\,
O(1) => \icount_out0_carry__2_n_6\,
O(0) => \icount_out0_carry__2_n_7\,
S(3) => \icount_out0_carry__2_i_1__0_n_0\,
S(2) => \icount_out0_carry__2_i_2__0_n_0\,
S(1) => \icount_out0_carry__2_i_3__0_n_0\,
S(0) => \icount_out0_carry__2_i_4__0_n_0\
);
\icount_out0_carry__2_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(15),
I1 => \^load_reg_gen[0].load_reg_i\(16),
O => \icount_out0_carry__2_i_1__0_n_0\
);
\icount_out0_carry__2_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(14),
I1 => \^load_reg_gen[0].load_reg_i\(15),
O => \icount_out0_carry__2_i_2__0_n_0\
);
\icount_out0_carry__2_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(13),
I1 => \^load_reg_gen[0].load_reg_i\(14),
O => \icount_out0_carry__2_i_3__0_n_0\
);
\icount_out0_carry__2_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(12),
I1 => \^load_reg_gen[0].load_reg_i\(13),
O => \icount_out0_carry__2_i_4__0_n_0\
);
\icount_out0_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__2_n_0\,
CO(3) => \icount_out0_carry__3_n_0\,
CO(2) => \icount_out0_carry__3_n_1\,
CO(1) => \icount_out0_carry__3_n_2\,
CO(0) => \icount_out0_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(19 downto 16),
O(3) => \icount_out0_carry__3_n_4\,
O(2) => \icount_out0_carry__3_n_5\,
O(1) => \icount_out0_carry__3_n_6\,
O(0) => \icount_out0_carry__3_n_7\,
S(3) => \icount_out0_carry__3_i_1__0_n_0\,
S(2) => \icount_out0_carry__3_i_2__0_n_0\,
S(1) => \icount_out0_carry__3_i_3__0_n_0\,
S(0) => \icount_out0_carry__3_i_4__0_n_0\
);
\icount_out0_carry__3_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(19),
I1 => \^load_reg_gen[0].load_reg_i\(20),
O => \icount_out0_carry__3_i_1__0_n_0\
);
\icount_out0_carry__3_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(18),
I1 => \^load_reg_gen[0].load_reg_i\(19),
O => \icount_out0_carry__3_i_2__0_n_0\
);
\icount_out0_carry__3_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(17),
I1 => \^load_reg_gen[0].load_reg_i\(18),
O => \icount_out0_carry__3_i_3__0_n_0\
);
\icount_out0_carry__3_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(16),
I1 => \^load_reg_gen[0].load_reg_i\(17),
O => \icount_out0_carry__3_i_4__0_n_0\
);
\icount_out0_carry__4\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__3_n_0\,
CO(3) => \icount_out0_carry__4_n_0\,
CO(2) => \icount_out0_carry__4_n_1\,
CO(1) => \icount_out0_carry__4_n_2\,
CO(0) => \icount_out0_carry__4_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(23 downto 20),
O(3) => \icount_out0_carry__4_n_4\,
O(2) => \icount_out0_carry__4_n_5\,
O(1) => \icount_out0_carry__4_n_6\,
O(0) => \icount_out0_carry__4_n_7\,
S(3) => \icount_out0_carry__4_i_1__0_n_0\,
S(2) => \icount_out0_carry__4_i_2__0_n_0\,
S(1) => \icount_out0_carry__4_i_3__0_n_0\,
S(0) => \icount_out0_carry__4_i_4__0_n_0\
);
\icount_out0_carry__4_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(23),
I1 => \^load_reg_gen[0].load_reg_i\(24),
O => \icount_out0_carry__4_i_1__0_n_0\
);
\icount_out0_carry__4_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(22),
I1 => \^load_reg_gen[0].load_reg_i\(23),
O => \icount_out0_carry__4_i_2__0_n_0\
);
\icount_out0_carry__4_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(21),
I1 => \^load_reg_gen[0].load_reg_i\(22),
O => \icount_out0_carry__4_i_3__0_n_0\
);
\icount_out0_carry__4_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(20),
I1 => \^load_reg_gen[0].load_reg_i\(21),
O => \icount_out0_carry__4_i_4__0_n_0\
);
\icount_out0_carry__5\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__4_n_0\,
CO(3) => \icount_out0_carry__5_n_0\,
CO(2) => \icount_out0_carry__5_n_1\,
CO(1) => \icount_out0_carry__5_n_2\,
CO(0) => \icount_out0_carry__5_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^load_reg_gen[0].load_reg_i\(27 downto 24),
O(3) => \icount_out0_carry__5_n_4\,
O(2) => \icount_out0_carry__5_n_5\,
O(1) => \icount_out0_carry__5_n_6\,
O(0) => \icount_out0_carry__5_n_7\,
S(3) => \icount_out0_carry__5_i_1__0_n_0\,
S(2) => \icount_out0_carry__5_i_2__0_n_0\,
S(1) => \icount_out0_carry__5_i_3__0_n_0\,
S(0) => \icount_out0_carry__5_i_4__0_n_0\
);
\icount_out0_carry__5_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(27),
I1 => \^load_reg_gen[0].load_reg_i\(28),
O => \icount_out0_carry__5_i_1__0_n_0\
);
\icount_out0_carry__5_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(26),
I1 => \^load_reg_gen[0].load_reg_i\(27),
O => \icount_out0_carry__5_i_2__0_n_0\
);
\icount_out0_carry__5_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(25),
I1 => \^load_reg_gen[0].load_reg_i\(26),
O => \icount_out0_carry__5_i_3__0_n_0\
);
\icount_out0_carry__5_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(24),
I1 => \^load_reg_gen[0].load_reg_i\(25),
O => \icount_out0_carry__5_i_4__0_n_0\
);
\icount_out0_carry__6\: unisim.vcomponents.CARRY4
port map (
CI => \icount_out0_carry__5_n_0\,
CO(3) => \NLW_icount_out0_carry__6_CO_UNCONNECTED\(3),
CO(2) => \icount_out0_carry__6_n_1\,
CO(1) => \icount_out0_carry__6_n_2\,
CO(0) => \icount_out0_carry__6_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \^load_reg_gen[0].load_reg_i\(30 downto 28),
O(3) => \icount_out0_carry__6_n_4\,
O(2) => \icount_out0_carry__6_n_5\,
O(1) => \icount_out0_carry__6_n_6\,
O(0) => \icount_out0_carry__6_n_7\,
S(3) => \icount_out0_carry__6_i_1__0_n_0\,
S(2) => \icount_out0_carry__6_i_2__0_n_0\,
S(1) => \icount_out0_carry__6_i_3__0_n_0\,
S(0) => \icount_out0_carry__6_i_4__0_n_0\
);
\icount_out0_carry__6_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(31),
O => \icount_out0_carry__6_i_1__0_n_0\
);
\icount_out0_carry__6_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(30),
I1 => \^load_reg_gen[0].load_reg_i\(31),
O => \icount_out0_carry__6_i_2__0_n_0\
);
\icount_out0_carry__6_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(29),
I1 => \^load_reg_gen[0].load_reg_i\(30),
O => \icount_out0_carry__6_i_3__0_n_0\
);
\icount_out0_carry__6_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(28),
I1 => \^load_reg_gen[0].load_reg_i\(29),
O => \icount_out0_carry__6_i_4__0_n_0\
);
\icount_out0_carry_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(1),
O => \icount_out0_carry_i_1__0_n_0\
);
\icount_out0_carry_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(3),
I1 => \^load_reg_gen[0].load_reg_i\(4),
O => \icount_out0_carry_i_2__0_n_0\
);
\icount_out0_carry_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(2),
I1 => \^load_reg_gen[0].load_reg_i\(3),
O => \icount_out0_carry_i_3__0_n_0\
);
\icount_out0_carry_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^load_reg_gen[0].load_reg_i\(1),
I1 => \^load_reg_gen[0].load_reg_i\(2),
O => \icount_out0_carry_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_mux_onehot_f is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
Bus_RNW_reg_reg : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]\ : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
Bus_RNW_reg_reg_7 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
Bus_RNW_reg_reg_8 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
Bus_RNW_reg_reg_9 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
Bus_RNW_reg_reg_10 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
Bus_RNW_reg_reg_11 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
Bus_RNW_reg_reg_12 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
Bus_RNW_reg_reg_13 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
Bus_RNW_reg_reg_14 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
Bus_RNW_reg_reg_15 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
Bus_RNW_reg_reg_16 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
Bus_RNW_reg_reg_17 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
Bus_RNW_reg_reg_18 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_mux_onehot_f : entity is "mux_onehot_f";
end zqynq_lab_1_design_axi_timer_0_0_mux_onehot_f;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_mux_onehot_f is
signal \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\ : STD_LOGIC;
signal cyout_1 : STD_LOGIC;
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute BOX_TYPE of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\ : label is "(MUXCY,XORCY)";
begin
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(31),
CO(0) => cyout_1,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[31]\,
S(0) => Bus_RNW_reg_reg
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(21),
CO(0) => \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[21]\,
S(0) => Bus_RNW_reg_reg_9
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(20),
CO(0) => \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[20]\,
S(0) => Bus_RNW_reg_reg_10
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(19),
CO(0) => \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[19]\,
S(0) => Bus_RNW_reg_reg_11
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(18),
CO(0) => \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[18]\,
S(0) => Bus_RNW_reg_reg_12
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(17),
CO(0) => \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[17]\,
S(0) => Bus_RNW_reg_reg_13
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(16),
CO(0) => \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[16]\,
S(0) => Bus_RNW_reg_reg_14
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(15),
CO(0) => \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[15]\,
S(0) => Bus_RNW_reg_reg_15
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(14),
CO(0) => \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[14]\,
S(0) => Bus_RNW_reg_reg_16
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(13),
CO(0) => \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[13]\,
S(0) => Bus_RNW_reg_reg_17
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(12),
CO(0) => \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[12]\,
S(0) => Bus_RNW_reg_reg_18
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(30),
CO(0) => \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[30]\,
S(0) => Bus_RNW_reg_reg_0
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(11),
CO(0) => \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[11]\,
S(0) => \LOAD_REG_GEN[20].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(10),
CO(0) => \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[10]\,
S(0) => \LOAD_REG_GEN[21].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(9),
CO(0) => \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[9]\,
S(0) => \LOAD_REG_GEN[22].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(8),
CO(0) => \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[8]\,
S(0) => \LOAD_REG_GEN[23].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(7),
CO(0) => \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[7]\,
S(0) => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(6),
CO(0) => \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[6]\,
S(0) => \LOAD_REG_GEN[25].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(5),
CO(0) => \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[5]\,
S(0) => \LOAD_REG_GEN[26].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(4),
CO(0) => \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[4]\,
S(0) => \LOAD_REG_GEN[27].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(3),
CO(0) => \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[3]\,
S(0) => \LOAD_REG_GEN[28].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(2),
CO(0) => \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[2]\,
S(0) => \LOAD_REG_GEN[29].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(29),
CO(0) => \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[29]\,
S(0) => Bus_RNW_reg_reg_1
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(1),
CO(0) => \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[1]\,
S(0) => \LOAD_REG_GEN[30].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(0),
CO(0) => \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[0]\,
S(0) => \LOAD_REG_GEN[31].LOAD_REG_I\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(28),
CO(0) => \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[28]\,
S(0) => Bus_RNW_reg_reg_2
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(27),
CO(0) => \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[27]\,
S(0) => Bus_RNW_reg_reg_3
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(26),
CO(0) => \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[26]\,
S(0) => Bus_RNW_reg_reg_4
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(25),
CO(0) => \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[25]\,
S(0) => Bus_RNW_reg_reg_5
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(24),
CO(0) => \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[24]\,
S(0) => Bus_RNW_reg_reg_6
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(23),
CO(0) => \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[23]\,
S(0) => Bus_RNW_reg_reg_7
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED\(3 downto 2),
CO(1) => D(22),
CO(0) => \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0\,
CYINIT => '0',
DI(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED\(3 downto 2),
DI(1 downto 0) => B"11",
O(3 downto 0) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => \NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED\(3 downto 2),
S(1) => \INFERRED_GEN.icount_out_reg[22]\,
S(0) => Bus_RNW_reg_reg_8
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_pselect_f is
port (
ce_expnd_i_7 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_pselect_f : entity is "pselect_f";
end zqynq_lab_1_design_axi_timer_0_0_pselect_f;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_pselect_f is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(1),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_7
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized1\ is
port (
ce_expnd_i_5 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized1\ : entity is "pselect_f";
end \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized1\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(1),
O => ce_expnd_i_5
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized3\ is
port (
ce_expnd_i_3 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized3\ : entity is "pselect_f";
end \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized3\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized3\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => \bus2ip_addr_i_reg[4]\(2),
I3 => Q,
O => ce_expnd_i_3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized4\ is
port (
ce_expnd_i_2 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized4\ : entity is "pselect_f";
end \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized4\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized4\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(2),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_2
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized5\ is
port (
ce_expnd_i_1 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized5\ : entity is "pselect_f";
end \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized5\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized5\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(0),
I1 => \bus2ip_addr_i_reg[4]\(2),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(1),
O => ce_expnd_i_1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized6\ is
port (
ce_expnd_i_0 : out STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized6\ : entity is "pselect_f";
end \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized6\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized6\ is
begin
CS: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(1),
I1 => \bus2ip_addr_i_reg[4]\(0),
I2 => \bus2ip_addr_i_reg[4]\(2),
I3 => Q,
O => ce_expnd_i_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_address_decoder is
port (
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg_1 : out STD_LOGIC;
s_axi_rvalid_i_reg_2 : out STD_LOGIC;
s_axi_bvalid_i_reg : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 );
s_axi_aresetn : in STD_LOGIC;
\state1__2\ : in STD_LOGIC;
s_axi_arvalid_0 : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arvalid : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_rvalid_i_reg_3 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_bvalid_i_reg_0 : in STD_LOGIC;
bus2ip_rnw_i : in STD_LOGIC;
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
\bus2ip_addr_i_reg[4]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_address_decoder : entity is "address_decoder";
end zqynq_lab_1_design_axi_timer_0_0_address_decoder;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_address_decoder is
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\ : STD_LOGIC;
signal \^load_reg_gen[31].load_reg_i\ : STD_LOGIC;
signal \^tcsr0_generate[23].tcsr0_ff_i\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal ce_expnd_i_5 : STD_LOGIC;
signal ce_expnd_i_6 : STD_LOGIC;
signal ce_expnd_i_7 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \eqOp__4\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_axi_arready_INST_0_i_4_n_0 : STD_LOGIC;
signal \^s_axi_rvalid_i_reg\ : STD_LOGIC;
signal \^s_axi_rvalid_i_reg_0\ : STD_LOGIC;
signal \^s_axi_rvalid_i_reg_1\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal s_axi_wready_INST_0_i_1_n_0 : STD_LOGIC;
signal s_axi_wready_INST_0_i_2_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of Bus_RNW_reg_i_1 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_7\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[2].LOAD_REG_I_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[3].LOAD_REG_I_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[9].LOAD_REG_I_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of READ_DONE0_I_i_2 : label is "soft_lutpair7";
attribute SOFT_HLUTNM of READ_DONE1_I_i_2 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[20].TCSR0_FF_I_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[21].TCSR0_FF_I_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[23].TCSR0_FF_I_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \TCSR0_GENERATE[24].TCSR0_FF_I_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[22].TCSR1_FF_I_i_1\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[23].TCSR1_FF_I_i_1\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \TCSR1_GENERATE[24].TCSR1_FF_I_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_2 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_3 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of s_axi_arready_INST_0_i_4 : label is "soft_lutpair2";
attribute SOFT_HLUTNM of s_axi_wready_INST_0_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of s_axi_wready_INST_0_i_2 : label is "soft_lutpair2";
begin
\LOAD_REG_GEN[31].LOAD_REG_I\ <= \^load_reg_gen[31].load_reg_i\;
\TCSR0_GENERATE[23].TCSR0_FF_I\ <= \^tcsr0_generate[23].tcsr0_ff_i\;
s_axi_arready <= \^s_axi_arready\;
s_axi_rvalid_i_reg <= \^s_axi_rvalid_i_reg\;
s_axi_rvalid_i_reg_0 <= \^s_axi_rvalid_i_reg_0\;
s_axi_rvalid_i_reg_1 <= \^s_axi_rvalid_i_reg_1\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i,
I1 => Q,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => \^tcsr0_generate[23].tcsr0_ff_i\,
R => '0'
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(84),
O => \s_axi_rdata_i_reg[31]\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[0]_0\
);
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[0]\
);
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(74),
O => \s_axi_rdata_i_reg[21]\
);
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(73),
O => \s_axi_rdata_i_reg[20]\
);
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(72),
O => \s_axi_rdata_i_reg[19]\
);
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(71),
O => \s_axi_rdata_i_reg[18]\
);
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(70),
O => \s_axi_rdata_i_reg[17]\
);
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(69),
O => \s_axi_rdata_i_reg[16]\
);
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(68),
O => \s_axi_rdata_i_reg[15]\
);
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(67),
O => \s_axi_rdata_i_reg[14]\
);
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(66),
O => \s_axi_rdata_i_reg[13]\
);
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(65),
O => \s_axi_rdata_i_reg[12]\
);
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(83),
O => \s_axi_rdata_i_reg[30]\
);
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0777FFFF"
)
port map (
I0 => read_Mux_In(64),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(87),
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[11]\
);
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(82),
O => \s_axi_rdata_i_reg[29]\
);
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(81),
O => \s_axi_rdata_i_reg[28]\
);
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(80),
O => \s_axi_rdata_i_reg[27]\
);
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(79),
O => \s_axi_rdata_i_reg[26]\
);
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(78),
O => \s_axi_rdata_i_reg[25]\
);
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(77),
O => \s_axi_rdata_i_reg[24]\
);
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(76),
O => \s_axi_rdata_i_reg[23]\
);
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"7F"
)
port map (
I0 => \^tcsr0_generate[23].tcsr0_ff_i\,
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => read_Mux_In(75),
O => \s_axi_rdata_i_reg[22]\
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_7,
Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => \bus2ip_addr_i_reg[4]\(2),
I1 => \bus2ip_addr_i_reg[4]\(1),
I2 => Q,
I3 => \bus2ip_addr_i_reg[4]\(0),
O => ce_expnd_i_6
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_6,
Q => \^load_reg_gen[31].load_reg_i\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_5,
Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_3,
Q => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_2,
Q => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_1,
Q => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_arready\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
R => cs_ce_clr
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(31),
I1 => read_Mux_In(31),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => D_0
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(31),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(63),
O => D_1
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \bus2ip_wrce__0\(0)
);
\LOAD_REG_GEN[10].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(21),
I1 => read_Mux_In(21),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[10].LOAD_REG_I\
);
\LOAD_REG_GEN[10].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(21),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(53),
O => \LOAD_REG_GEN[10].LOAD_REG_I_0\
);
\LOAD_REG_GEN[11].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(20),
I1 => read_Mux_In(20),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[11].LOAD_REG_I\
);
\LOAD_REG_GEN[11].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(20),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(52),
O => \LOAD_REG_GEN[11].LOAD_REG_I_0\
);
\LOAD_REG_GEN[12].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(19),
I1 => read_Mux_In(19),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[12].LOAD_REG_I\
);
\LOAD_REG_GEN[12].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(19),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(51),
O => \LOAD_REG_GEN[12].LOAD_REG_I_0\
);
\LOAD_REG_GEN[13].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(18),
I1 => read_Mux_In(18),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[13].LOAD_REG_I\
);
\LOAD_REG_GEN[13].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(18),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(50),
O => \LOAD_REG_GEN[13].LOAD_REG_I_0\
);
\LOAD_REG_GEN[14].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(17),
I1 => read_Mux_In(17),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[14].LOAD_REG_I\
);
\LOAD_REG_GEN[14].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(17),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(49),
O => \LOAD_REG_GEN[14].LOAD_REG_I_0\
);
\LOAD_REG_GEN[15].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(16),
I1 => read_Mux_In(16),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[15].LOAD_REG_I\
);
\LOAD_REG_GEN[15].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(16),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(48),
O => \LOAD_REG_GEN[15].LOAD_REG_I_0\
);
\LOAD_REG_GEN[16].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(15),
I1 => read_Mux_In(15),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[16].LOAD_REG_I\
);
\LOAD_REG_GEN[16].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(15),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(47),
O => \LOAD_REG_GEN[16].LOAD_REG_I_0\
);
\LOAD_REG_GEN[17].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(14),
I1 => read_Mux_In(14),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[17].LOAD_REG_I\
);
\LOAD_REG_GEN[17].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(14),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(46),
O => \LOAD_REG_GEN[17].LOAD_REG_I_0\
);
\LOAD_REG_GEN[18].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(13),
I1 => read_Mux_In(13),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[18].LOAD_REG_I\
);
\LOAD_REG_GEN[18].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(13),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(45),
O => \LOAD_REG_GEN[18].LOAD_REG_I_0\
);
\LOAD_REG_GEN[19].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(12),
I1 => read_Mux_In(12),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[19].LOAD_REG_I\
);
\LOAD_REG_GEN[19].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(12),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(44),
O => \LOAD_REG_GEN[19].LOAD_REG_I_0\
);
\LOAD_REG_GEN[1].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(30),
I1 => read_Mux_In(30),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[1].LOAD_REG_I\
);
\LOAD_REG_GEN[1].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(30),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(62),
O => \LOAD_REG_GEN[1].LOAD_REG_I_0\
);
\LOAD_REG_GEN[20].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(11),
I1 => read_Mux_In(11),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[20].LOAD_REG_I\
);
\LOAD_REG_GEN[20].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(11),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(43),
O => \LOAD_REG_GEN[20].LOAD_REG_I_0\
);
\LOAD_REG_GEN[21].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(10),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[21].LOAD_REG_I\
);
\LOAD_REG_GEN[21].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(10),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(42),
O => \LOAD_REG_GEN[21].LOAD_REG_I_0\
);
\LOAD_REG_GEN[22].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(9),
I1 => read_Mux_In(9),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[22].LOAD_REG_I\
);
\LOAD_REG_GEN[22].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(9),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(41),
O => \LOAD_REG_GEN[22].LOAD_REG_I_0\
);
\LOAD_REG_GEN[23].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(8),
I1 => read_Mux_In(8),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[23].LOAD_REG_I\
);
\LOAD_REG_GEN[23].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(8),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(40),
O => \LOAD_REG_GEN[23].LOAD_REG_I_0\
);
\LOAD_REG_GEN[24].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(7),
I1 => read_Mux_In(7),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\LOAD_REG_GEN[24].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(39),
O => \LOAD_REG_GEN[24].LOAD_REG_I_0\
);
\LOAD_REG_GEN[25].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(6),
I1 => read_Mux_In(6),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[25].LOAD_REG_I\
);
\LOAD_REG_GEN[25].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(38),
O => \LOAD_REG_GEN[25].LOAD_REG_I_0\
);
\LOAD_REG_GEN[26].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(5),
I1 => read_Mux_In(5),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[26].LOAD_REG_I\
);
\LOAD_REG_GEN[26].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(37),
O => \LOAD_REG_GEN[26].LOAD_REG_I_0\
);
\LOAD_REG_GEN[27].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(4),
I1 => read_Mux_In(4),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[27].LOAD_REG_I\
);
\LOAD_REG_GEN[27].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(36),
O => \LOAD_REG_GEN[27].LOAD_REG_I_0\
);
\LOAD_REG_GEN[28].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(3),
I1 => read_Mux_In(3),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[28].LOAD_REG_I\
);
\LOAD_REG_GEN[28].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(35),
O => \LOAD_REG_GEN[28].LOAD_REG_I_0\
);
\LOAD_REG_GEN[29].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(2),
I1 => read_Mux_In(2),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[29].LOAD_REG_I\
);
\LOAD_REG_GEN[29].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(34),
O => \LOAD_REG_GEN[29].LOAD_REG_I_0\
);
\LOAD_REG_GEN[2].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(29),
I1 => read_Mux_In(29),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[2].LOAD_REG_I\
);
\LOAD_REG_GEN[2].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(29),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(61),
O => \LOAD_REG_GEN[2].LOAD_REG_I_0\
);
\LOAD_REG_GEN[30].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(1),
I1 => read_Mux_In(1),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[30].LOAD_REG_I\
);
\LOAD_REG_GEN[30].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(33),
O => \LOAD_REG_GEN[30].LOAD_REG_I_0\
);
\LOAD_REG_GEN[31].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(0),
I1 => read_Mux_In(0),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[31].LOAD_REG_I_0\
);
\LOAD_REG_GEN[31].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(32),
O => \LOAD_REG_GEN[31].LOAD_REG_I_1\
);
\LOAD_REG_GEN[3].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(28),
I1 => read_Mux_In(28),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[3].LOAD_REG_I\
);
\LOAD_REG_GEN[3].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(28),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(60),
O => \LOAD_REG_GEN[3].LOAD_REG_I_0\
);
\LOAD_REG_GEN[4].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(27),
I1 => read_Mux_In(27),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[4].LOAD_REG_I\
);
\LOAD_REG_GEN[4].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(27),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(59),
O => \LOAD_REG_GEN[4].LOAD_REG_I_0\
);
\LOAD_REG_GEN[5].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(26),
I1 => read_Mux_In(26),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[5].LOAD_REG_I\
);
\LOAD_REG_GEN[5].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(26),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(58),
O => \LOAD_REG_GEN[5].LOAD_REG_I_0\
);
\LOAD_REG_GEN[6].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(25),
I1 => read_Mux_In(25),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[6].LOAD_REG_I\
);
\LOAD_REG_GEN[6].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(25),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(57),
O => \LOAD_REG_GEN[6].LOAD_REG_I_0\
);
\LOAD_REG_GEN[7].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(24),
I1 => read_Mux_In(24),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[7].LOAD_REG_I\
);
\LOAD_REG_GEN[7].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(24),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(56),
O => \LOAD_REG_GEN[7].LOAD_REG_I_0\
);
\LOAD_REG_GEN[8].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(23),
I1 => read_Mux_In(23),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[8].LOAD_REG_I\
);
\LOAD_REG_GEN[8].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(23),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(55),
O => \LOAD_REG_GEN[8].LOAD_REG_I_0\
);
\LOAD_REG_GEN[9].LOAD_REG_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCAC"
)
port map (
I0 => s_axi_wdata(22),
I1 => read_Mux_In(22),
I2 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \LOAD_REG_GEN[9].LOAD_REG_I\
);
\LOAD_REG_GEN[9].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(22),
I1 => \^load_reg_gen[31].load_reg_i\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => read_Mux_In(54),
O => \LOAD_REG_GEN[9].LOAD_REG_I_0\
);
\MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.zqynq_lab_1_design_axi_timer_0_0_pselect_f
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_7 => ce_expnd_i_7
);
\MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized1\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_5 => ce_expnd_i_5
);
\MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized3\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_3 => ce_expnd_i_3
);
\MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized4\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_2 => ce_expnd_i_2
);
\MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized5\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_1 => ce_expnd_i_1
);
\MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I\: entity work.\zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized6\
port map (
Q => Q,
\bus2ip_addr_i_reg[4]\(2 downto 0) => \bus2ip_addr_i_reg[4]\(2 downto 0),
ce_expnd_i_0 => ce_expnd_i_0
);
READ_DONE0_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => D_2,
O => READ_DONE0_I
);
READ_DONE1_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => read_done1,
O => READ_DONE1_I
);
\TCSR0_GENERATE[20].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => bus2ip_wrce(1)
);
\TCSR0_GENERATE[21].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"32"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
I2 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
O => pair0_Select
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
I2 => s_axi_wdata(8),
I3 => s_axi_aresetn,
O => \TCSR0_GENERATE[23].TCSR0_FF_I_0\
);
\TCSR0_GENERATE[24].TCSR0_FF_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFEEEAEE"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(86),
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I4 => s_axi_wdata(7),
O => \TCSR0_GENERATE[24].TCSR0_FF_I\
);
\TCSR1_GENERATE[22].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => bus2ip_wrce(0)
);
\TCSR1_GENERATE[23].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
I2 => s_axi_wdata(8),
I3 => s_axi_aresetn,
O => \TCSR1_GENERATE[23].TCSR1_FF_I\
);
\TCSR1_GENERATE[24].TCSR1_FF_I_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"EFEEEAEE"
)
port map (
I0 => s_axi_wdata(10),
I1 => read_Mux_In(85),
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I4 => s_axi_wdata(7),
O => \TCSR1_GENERATE[24].TCSR1_FF_I\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFEFFFEFFFEFF"
)
port map (
I0 => \^s_axi_rvalid_i_reg\,
I1 => \^s_axi_rvalid_i_reg_0\,
I2 => \^s_axi_rvalid_i_reg_1\,
I3 => s_axi_arready_INST_0_i_4_n_0,
I4 => is_read,
I5 => \eqOp__4\,
O => \^s_axi_arready\
);
s_axi_arready_INST_0_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \^s_axi_rvalid_i_reg\
);
s_axi_arready_INST_0_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \^s_axi_rvalid_i_reg_0\
);
s_axi_arready_INST_0_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
I1 => \^tcsr0_generate[23].tcsr0_ff_i\,
O => \^s_axi_rvalid_i_reg_1\
);
s_axi_arready_INST_0_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"00FF01FF"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => s_axi_arready_INST_0_i_4_n_0
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => \state_reg[1]\(1),
I2 => \state_reg[1]\(0),
I3 => s_axi_bready,
I4 => s_axi_bvalid_i_reg_0,
O => s_axi_bvalid_i_reg
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => s_axi_rready,
I4 => s_axi_rvalid_i_reg_3,
O => s_axi_rvalid_i_reg_2
);
s_axi_wready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"F777"
)
port map (
I0 => s_axi_wready_INST_0_i_1_n_0,
I1 => s_axi_wready_INST_0_i_2_n_0,
I2 => is_write_reg,
I3 => \eqOp__4\,
O => \^s_axi_wready\
);
s_axi_wready_INST_0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F0F1"
)
port map (
I0 => \^load_reg_gen[31].load_reg_i\,
I1 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg\,
I2 => \^tcsr0_generate[23].tcsr0_ff_i\,
I3 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => s_axi_wready_INST_0_i_1_n_0
);
s_axi_wready_INST_0_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FF00FF01"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg\,
I3 => \^tcsr0_generate[23].tcsr0_ff_i\,
I4 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
O => s_axi_wready_INST_0_i_2_n_0
);
s_axi_wready_INST_0_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(4),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(2),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(3),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(0),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(1),
O => \eqOp__4\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => \state_reg[1]\(0),
I2 => s_axi_arvalid,
I3 => \state_reg[1]\(1),
I4 => \^s_axi_wready\,
O => D(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => s_axi_arvalid_0,
I2 => \state_reg[1]\(1),
I3 => \state_reg[1]\(0),
I4 => \^s_axi_arready\,
O => D(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_count_module is
port (
\INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC_VECTOR ( 52 downto 0 );
read_Mux_In : out STD_LOGIC_VECTOR ( 10 downto 0 );
generateOutPre0_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn_0 : in STD_LOGIC;
\TCSR0_GENERATE[27].TCSR0_FF_I\ : in STD_LOGIC;
D_1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 0 to 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_count_module : entity is "count_module";
end zqynq_lab_1_design_axi_timer_0_0_count_module;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_count_module is
signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC_VECTOR ( 52 downto 0 );
signal \^read_mux_in\ : STD_LOGIC_VECTOR ( 10 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE";
begin
\INFERRED_GEN.icount_out_reg[31]\(52 downto 0) <= \^inferred_gen.icount_out_reg[31]\(52 downto 0);
read_Mux_In(10 downto 0) <= \^read_mux_in\(10 downto 0);
COUNTER_I: entity work.zqynq_lab_1_design_axi_timer_0_0_counter_f_3
port map (
E(0) => E(0),
\LOAD_REG_GEN[0].LOAD_REG_I\(31 downto 0) => \^inferred_gen.icount_out_reg[31]\(31 downto 0),
\LOAD_REG_GEN[0].LOAD_REG_I_0\(20 downto 0) => \^inferred_gen.icount_out_reg[31]\(52 downto 32),
Q(0) => Q(0),
S(0) => S(0),
counter_TC(0) => counter_TC(0),
generateOutPre0_reg => generateOutPre0_reg,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(10 downto 0) => \^read_mux_in\(10 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => s_axi_aresetn_0
);
\LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => D_1,
Q => \^inferred_gen.icount_out_reg[31]\(52),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\,
Q => \^inferred_gen.icount_out_reg[31]\(42),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\,
Q => \^inferred_gen.icount_out_reg[31]\(41),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\,
Q => \^inferred_gen.icount_out_reg[31]\(40),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\,
Q => \^inferred_gen.icount_out_reg[31]\(39),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\,
Q => \^inferred_gen.icount_out_reg[31]\(38),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\,
Q => \^inferred_gen.icount_out_reg[31]\(37),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\,
Q => \^inferred_gen.icount_out_reg[31]\(36),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\,
Q => \^inferred_gen.icount_out_reg[31]\(35),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\,
Q => \^inferred_gen.icount_out_reg[31]\(34),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\,
Q => \^inferred_gen.icount_out_reg[31]\(33),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q => \^inferred_gen.icount_out_reg[31]\(51),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\,
Q => \^inferred_gen.icount_out_reg[31]\(32),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\,
Q => \^read_mux_in\(10),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\,
Q => \^read_mux_in\(9),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\,
Q => \^read_mux_in\(8),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\,
Q => \^read_mux_in\(7),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\,
Q => \^read_mux_in\(6),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\,
Q => \^read_mux_in\(5),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\,
Q => \^read_mux_in\(4),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\,
Q => \^read_mux_in\(3),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\,
Q => \^read_mux_in\(2),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
Q => \^inferred_gen.icount_out_reg[31]\(50),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\,
Q => \^read_mux_in\(1),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\,
Q => \^read_mux_in\(0),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\,
Q => \^inferred_gen.icount_out_reg[31]\(49),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\,
Q => \^inferred_gen.icount_out_reg[31]\(48),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\,
Q => \^inferred_gen.icount_out_reg[31]\(47),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\,
Q => \^inferred_gen.icount_out_reg[31]\(46),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\,
Q => \^inferred_gen.icount_out_reg[31]\(45),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\,
Q => \^inferred_gen.icount_out_reg[31]\(44),
R => s_axi_aresetn_0
);
\LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[27].TCSR0_FF_I\,
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\,
Q => \^inferred_gen.icount_out_reg[31]\(43),
R => s_axi_aresetn_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_count_module_0 is
port (
\INFERRED_GEN.icount_out_reg[31]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 31 downto 0 );
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
generateOutPre1_reg : out STD_LOGIC;
counter_TC : out STD_LOGIC_VECTOR ( 0 to 0 );
\TCSR0_GENERATE[20].TCSR0_FF_I\ : in STD_LOGIC;
D_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]\ : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 0 to 0 );
load_Counter_Reg : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[31]_0\ : in STD_LOGIC_VECTOR ( 31 downto 0 );
\counter_TC_Reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_count_module_0 : entity is "count_module";
end zqynq_lab_1_design_axi_timer_0_0_count_module_0;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_count_module_0 is
signal \^inferred_gen.icount_out_reg[31]\ : STD_LOGIC;
signal read_Mux_In : STD_LOGIC_VECTOR ( 96 to 127 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \LOAD_REG_GEN[0].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[10].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[11].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[12].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[13].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[14].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[15].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[16].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[17].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[18].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[19].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[1].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[20].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[21].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[22].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[23].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[24].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[25].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[26].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[27].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[28].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[29].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[2].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[30].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[31].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[3].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[4].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[5].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[6].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[7].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[8].LOAD_REG_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \LOAD_REG_GEN[9].LOAD_REG_I\ : label is "PRIMITIVE";
begin
\INFERRED_GEN.icount_out_reg[31]\ <= \^inferred_gen.icount_out_reg[31]\;
COUNTER_I: entity work.zqynq_lab_1_design_axi_timer_0_0_counter_f
port map (
E(0) => E(0),
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
\INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0) => \INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0),
Q(31 downto 0) => Q(31 downto 0),
S(0) => S(0),
SR(0) => \^inferred_gen.icount_out_reg[31]\,
counter_TC(0) => counter_TC(0),
\counter_TC_Reg_reg[1]\(0) => \counter_TC_Reg_reg[1]\(0),
generateOutPre1_reg => generateOutPre1_reg,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(31) => read_Mux_In(96),
read_Mux_In(30) => read_Mux_In(97),
read_Mux_In(29) => read_Mux_In(98),
read_Mux_In(28) => read_Mux_In(99),
read_Mux_In(27) => read_Mux_In(100),
read_Mux_In(26) => read_Mux_In(101),
read_Mux_In(25) => read_Mux_In(102),
read_Mux_In(24) => read_Mux_In(103),
read_Mux_In(23) => read_Mux_In(104),
read_Mux_In(22) => read_Mux_In(105),
read_Mux_In(21) => read_Mux_In(106),
read_Mux_In(20) => read_Mux_In(107),
read_Mux_In(19) => read_Mux_In(108),
read_Mux_In(18) => read_Mux_In(109),
read_Mux_In(17) => read_Mux_In(110),
read_Mux_In(16) => read_Mux_In(111),
read_Mux_In(15) => read_Mux_In(112),
read_Mux_In(14) => read_Mux_In(113),
read_Mux_In(13) => read_Mux_In(114),
read_Mux_In(12) => read_Mux_In(115),
read_Mux_In(11) => read_Mux_In(116),
read_Mux_In(10) => read_Mux_In(117),
read_Mux_In(9) => read_Mux_In(118),
read_Mux_In(8) => read_Mux_In(119),
read_Mux_In(7) => read_Mux_In(120),
read_Mux_In(6) => read_Mux_In(121),
read_Mux_In(5) => read_Mux_In(122),
read_Mux_In(4) => read_Mux_In(123),
read_Mux_In(3) => read_Mux_In(124),
read_Mux_In(2) => read_Mux_In(125),
read_Mux_In(1) => read_Mux_In(126),
read_Mux_In(0) => read_Mux_In(127),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]\,
\s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]\,
\s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]\,
\s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]\,
\s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]\,
\s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]\,
\s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]\,
\s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]\,
\s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]\,
\s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]\,
\s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]\,
\s_axi_rdata_i_reg[1]\ => \s_axi_rdata_i_reg[1]\,
\s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]\,
\s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]\,
\s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]\,
\s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]\,
\s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]\,
\s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]\,
\s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]\,
\s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]\,
\s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]\,
\s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]\,
\s_axi_rdata_i_reg[2]\ => \s_axi_rdata_i_reg[2]\,
\s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]\,
\s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]\,
\s_axi_rdata_i_reg[3]\ => \s_axi_rdata_i_reg[3]\,
\s_axi_rdata_i_reg[4]\ => \s_axi_rdata_i_reg[4]\,
\s_axi_rdata_i_reg[5]\ => \s_axi_rdata_i_reg[5]\,
\s_axi_rdata_i_reg[6]\ => \s_axi_rdata_i_reg[6]\,
\s_axi_rdata_i_reg[7]\ => \s_axi_rdata_i_reg[7]\,
\s_axi_rdata_i_reg[8]\ => \s_axi_rdata_i_reg[8]\,
\s_axi_rdata_i_reg[9]\ => \s_axi_rdata_i_reg[9]\
);
\LOAD_REG_GEN[0].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => D_2,
Q => read_Mux_In(96),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[10].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[21]\,
Q => read_Mux_In(106),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[11].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[20]\,
Q => read_Mux_In(107),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[12].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[19]\,
Q => read_Mux_In(108),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[13].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[18]\,
Q => read_Mux_In(109),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[14].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[17]\,
Q => read_Mux_In(110),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[15].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[16]\,
Q => read_Mux_In(111),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[16].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[15]\,
Q => read_Mux_In(112),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[17].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[14]\,
Q => read_Mux_In(113),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[18].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[13]\,
Q => read_Mux_In(114),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[19].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[12]\,
Q => read_Mux_In(115),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[1].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[30]\,
Q => read_Mux_In(97),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[20].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[11]\,
Q => read_Mux_In(116),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[21].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[10]\,
Q => read_Mux_In(117),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[22].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[9]\,
Q => read_Mux_In(118),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[23].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[8]\,
Q => read_Mux_In(119),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[24].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[7]\,
Q => read_Mux_In(120),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[25].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[6]\,
Q => read_Mux_In(121),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[26].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[5]\,
Q => read_Mux_In(122),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[27].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[4]\,
Q => read_Mux_In(123),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[28].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[3]\,
Q => read_Mux_In(124),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[29].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[2]\,
Q => read_Mux_In(125),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[2].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[29]\,
Q => read_Mux_In(98),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[30].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[1]\,
Q => read_Mux_In(126),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[31].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[0]\,
Q => read_Mux_In(127),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[3].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[28]\,
Q => read_Mux_In(99),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[4].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[27]\,
Q => read_Mux_In(100),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[5].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[26]\,
Q => read_Mux_In(101),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[6].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[25]\,
Q => read_Mux_In(102),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[7].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[24]\,
Q => read_Mux_In(103),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[8].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[23]\,
Q => read_Mux_In(104),
R => \^inferred_gen.icount_out_reg[31]\
);
\LOAD_REG_GEN[9].LOAD_REG_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => \TCSR0_GENERATE[20].TCSR0_FF_I\,
D => \INFERRED_GEN.icount_out_reg[22]\,
Q => read_Mux_In(105),
R => \^inferred_gen.icount_out_reg[31]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_timer_control is
port (
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
interrupt : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I_0\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
read_done1 : out STD_LOGIC;
load_Counter_Reg : out STD_LOGIC_VECTOR ( 0 to 1 );
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[1]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[2]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[3]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[4]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[5]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[6]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[7]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[8]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[9]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
R : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
PWM_FF_I : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 0 to 0 );
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
\INFERRED_GEN.icount_out_reg[32]\ : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[32]_0\ : in STD_LOGIC;
bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
\LOAD_REG_GEN[21].LOAD_REG_I\ : in STD_LOGIC_VECTOR ( 10 downto 0 );
pair0_Select : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I_1\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
counter_TC : in STD_LOGIC_VECTOR ( 0 to 1 );
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC;
pwm0 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
freeze : in STD_LOGIC;
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_timer_control : entity is "timer_control";
end zqynq_lab_1_design_axi_timer_0_0_timer_control;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_timer_control is
signal \^d_0\ : STD_LOGIC;
signal GenerateOut00 : STD_LOGIC;
signal GenerateOut10 : STD_LOGIC;
signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC;
signal Interrupt0 : STD_LOGIC;
signal \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\ : STD_LOGIC;
signal \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\ : STD_LOGIC;
signal Load_Counter_Reg028_out : STD_LOGIC;
signal Load_Counter_Reg030_out : STD_LOGIC;
signal Load_Counter_Reg031_out : STD_LOGIC;
signal \Load_Counter_Reg0__0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal READ_DONE0_I_i_3_n_0 : STD_LOGIC;
signal READ_DONE1_I_i_1_n_0 : STD_LOGIC;
signal READ_DONE1_I_i_3_n_0 : STD_LOGIC;
signal R_0 : STD_LOGIC;
signal \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\ : STD_LOGIC;
signal \^tcsr0_generate[24].tcsr0_ff_i_0\ : STD_LOGIC;
signal \TCSR0_Set2__0\ : STD_LOGIC;
signal \^tcsr1_generate[23].tcsr1_ff_i_0\ : STD_LOGIC;
signal \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\ : STD_LOGIC;
signal captureTrig0_d : STD_LOGIC;
signal captureTrig0_d0 : STD_LOGIC;
signal captureTrig0_d2 : STD_LOGIC;
signal captureTrig0_pulse_d1 : STD_LOGIC;
signal captureTrig0_pulse_d1_i_1_n_0 : STD_LOGIC;
signal captureTrig0_pulse_d2 : STD_LOGIC;
signal captureTrig1_d : STD_LOGIC;
signal captureTrig1_d0 : STD_LOGIC;
signal captureTrig1_d2 : STD_LOGIC;
signal counter_TC_Reg2 : STD_LOGIC;
signal generateOutPre0 : STD_LOGIC;
signal generateOutPre1 : STD_LOGIC;
signal \^generateout0\ : STD_LOGIC;
signal \^generateout1\ : STD_LOGIC;
signal p_33_in : STD_LOGIC;
signal p_38_in : STD_LOGIC;
signal read_Mux_In : STD_LOGIC_VECTOR ( 21 to 63 );
signal \^read_done1\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of GenerateOut0_i_2 : label is "soft_lutpair50";
attribute SOFT_HLUTNM of GenerateOut1_i_1 : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \INFERRED_GEN.icount_out[31]_i_4__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_3\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \LOAD_REG_GEN[0].LOAD_REG_I_i_5\ : label is "soft_lutpair53";
attribute BOX_TYPE : string;
attribute BOX_TYPE of READ_DONE0_I : label is "PRIMITIVE";
attribute IS_CE_INVERTED : string;
attribute IS_CE_INVERTED of READ_DONE0_I : label is "1'b0";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of READ_DONE0_I : label is "1'b0";
attribute BOX_TYPE of READ_DONE1_I : label is "PRIMITIVE";
attribute IS_CE_INVERTED of READ_DONE1_I : label is "1'b0";
attribute IS_S_INVERTED of READ_DONE1_I : label is "1'b0";
attribute SOFT_HLUTNM of READ_DONE1_I_i_3 : label is "soft_lutpair52";
attribute BOX_TYPE of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[20].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[21].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[22].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[23].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[24].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[25].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[26].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[27].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[28].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[29].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[30].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR0_GENERATE[31].TCSR0_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[21].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[22].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[23].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[24].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[25].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[26].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[27].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[28].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[29].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[30].TCSR1_FF_I\ : label is "1'b0";
attribute BOX_TYPE of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "PRIMITIVE";
attribute IS_CE_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0";
attribute IS_S_INVERTED of \TCSR1_GENERATE[31].TCSR1_FF_I\ : label is "1'b0";
attribute SOFT_HLUTNM of captureTrig0_pulse_d1_i_1 : label is "soft_lutpair52";
begin
D_0 <= \^d_0\;
\INFERRED_GEN.icount_out_reg[0]\ <= \^inferred_gen.icount_out_reg[0]\;
Q(1 downto 0) <= \^q\(1 downto 0);
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ <= \^tcsr0_generate[24].tcsr0_ff_i_0\;
\TCSR1_GENERATE[23].TCSR1_FF_I_0\ <= \^tcsr1_generate[23].tcsr1_ff_i_0\;
generateout0 <= \^generateout0\;
generateout1 <= \^generateout1\;
read_done1 <= \^read_done1\;
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(10),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(21),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(53),
O => \s_axi_rdata_i_reg[10]\
);
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(9),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(22),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(54),
O => \s_axi_rdata_i_reg[9]\
);
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(8),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(23),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(55),
O => \s_axi_rdata_i_reg[8]\
);
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(7),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => \^tcsr0_generate[24].tcsr0_ff_i_0\,
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => \^tcsr1_generate[23].tcsr1_ff_i_0\,
O => \s_axi_rdata_i_reg[7]\
);
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(6),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(25),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(57),
O => \s_axi_rdata_i_reg[6]\
);
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(5),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(26),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(58),
O => \s_axi_rdata_i_reg[5]\
);
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(4),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(27),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(59),
O => \s_axi_rdata_i_reg[4]\
);
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(3),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(28),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(60),
O => \s_axi_rdata_i_reg[3]\
);
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(2),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(29),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(61),
O => \s_axi_rdata_i_reg[2]\
);
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(1),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(30),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(62),
O => \s_axi_rdata_i_reg[1]\
);
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000077707770777"
)
port map (
I0 => \LOAD_REG_GEN[21].LOAD_REG_I\(0),
I1 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
I3 => read_Mux_In(31),
I4 => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
I5 => read_Mux_In(63),
O => \s_axi_rdata_i_reg[0]\
);
GenerateOut0_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"B800"
)
port map (
I0 => generateOutPre1,
I1 => \^inferred_gen.icount_out_reg[0]\,
I2 => generateOutPre0,
I3 => read_Mux_In(29),
O => GenerateOut00
);
GenerateOut0_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GenerateOut00,
Q => \^generateout0\,
R => SR(0)
);
GenerateOut1_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8F808080"
)
port map (
I0 => generateOutPre0,
I1 => read_Mux_In(29),
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => read_Mux_In(61),
I4 => generateOutPre1,
O => GenerateOut10
);
GenerateOut1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GenerateOut10,
Q => \^generateout1\,
R => SR(0)
);
\INFERRED_GEN.icount_out[31]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAFEAAAA"
)
port map (
I0 => read_Mux_In(26),
I1 => read_Mux_In(22),
I2 => read_Mux_In(27),
I3 => read_Mux_In(31),
I4 => counter_TC(0),
O => Load_Counter_Reg030_out
);
\INFERRED_GEN.icount_out[31]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAEAAAAAAAEA"
)
port map (
I0 => read_Mux_In(58),
I1 => counter_TC(1),
I2 => read_Mux_In(59),
I3 => read_Mux_In(63),
I4 => read_Mux_In(54),
I5 => counter_TC(0),
O => \Load_Counter_Reg0__0\
);
\INFERRED_GEN.icount_out[31]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(58),
O => Load_Counter_Reg028_out
);
\INFERRED_GEN.icount_out[31]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FF40"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(26),
O => Load_Counter_Reg031_out
);
\INFERRED_GEN.icount_out[31]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40FFFFFF400000"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(58),
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => \Load_Counter_Reg0__0\,
O => load_Counter_Reg(1)
);
\INFERRED_GEN.icount_out[31]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40FFFFFF400000"
)
port map (
I0 => read_Mux_In(31),
I1 => counter_TC(1),
I2 => read_Mux_In(27),
I3 => read_Mux_In(26),
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => Load_Counter_Reg030_out,
O => load_Counter_Reg(0)
);
INPUT_DOUBLE_REGS: entity work.zqynq_lab_1_design_axi_timer_0_0_cdc_sync
port map (
captureTrig0_d0 => captureTrig0_d0,
capturetrig0 => capturetrig0,
read_Mux_In(0) => read_Mux_In(28),
s_axi_aclk => s_axi_aclk
);
INPUT_DOUBLE_REGS2: entity work.zqynq_lab_1_design_axi_timer_0_0_cdc_sync_1
port map (
captureTrig1_d0 => captureTrig1_d0,
capturetrig1 => capturetrig1,
read_Mux_In(0) => read_Mux_In(60),
s_axi_aclk => s_axi_aclk
);
INPUT_DOUBLE_REGS3: entity work.zqynq_lab_1_design_axi_timer_0_0_cdc_sync_2
port map (
E(0) => E(0),
\INFERRED_GEN.icount_out_reg[0]\(0) => \INFERRED_GEN.icount_out_reg[0]_0\(0),
\INFERRED_GEN.icount_out_reg[1]\(1 downto 0) => \INFERRED_GEN.icount_out_reg[1]\(1 downto 0),
\INFERRED_GEN.icount_out_reg[4]\(0) => \INFERRED_GEN.icount_out_reg[4]\(0),
Load_Counter_Reg028_out => Load_Counter_Reg028_out,
Load_Counter_Reg030_out => Load_Counter_Reg030_out,
Load_Counter_Reg031_out => Load_Counter_Reg031_out,
\Load_Counter_Reg0__0\ => \Load_Counter_Reg0__0\,
S(0) => S(0),
\TCSR0_GENERATE[20].TCSR0_FF_I\ => \^inferred_gen.icount_out_reg[0]\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \^tcsr0_generate[24].tcsr0_ff_i_0\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \^tcsr1_generate[23].tcsr1_ff_i_0\,
counter_TC(0 to 1) => counter_TC(0 to 1),
freeze => freeze,
generateOutPre0 => generateOutPre0,
read_Mux_In(7) => read_Mux_In(22),
read_Mux_In(6) => read_Mux_In(27),
read_Mux_In(5) => read_Mux_In(30),
read_Mux_In(4) => read_Mux_In(31),
read_Mux_In(3) => read_Mux_In(54),
read_Mux_In(2) => read_Mux_In(59),
read_Mux_In(1) => read_Mux_In(62),
read_Mux_In(0) => read_Mux_In(63),
s_axi_aclk => s_axi_aclk
);
Interrupt_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => read_Mux_In(25),
I1 => read_Mux_In(23),
I2 => read_Mux_In(57),
I3 => read_Mux_In(55),
O => Interrupt0
);
Interrupt_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Interrupt0,
Q => interrupt,
R => SR(0)
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E000FFFFE000E000"
)
port map (
I0 => read_Mux_In(27),
I1 => \^d_0\,
I2 => R_0,
I3 => read_Mux_In(31),
I4 => Bus_RNW_reg,
I5 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
O => \LOAD_REG_GEN[24].LOAD_REG_I\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF8080808"
)
port map (
I0 => \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\,
I1 => p_38_in,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\,
I4 => p_33_in,
I5 => \bus2ip_wrce__0\(0),
O => \LOAD_REG_GEN[24].LOAD_REG_I_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => read_Mux_In(59),
I1 => \^read_done1\,
O => \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F40400000000"
)
port map (
I0 => captureTrig1_d2,
I1 => captureTrig1_d,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => READ_DONE1_I_i_3_n_0,
I4 => READ_DONE0_I_i_3_n_0,
I5 => read_Mux_In(63),
O => p_38_in
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => read_Mux_In(27),
I1 => \^read_done1\,
O => \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0\
);
\LOAD_REG_GEN[0].LOAD_REG_I_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"F4F4F40400000000"
)
port map (
I0 => captureTrig1_d2,
I1 => captureTrig1_d,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => READ_DONE1_I_i_3_n_0,
I4 => READ_DONE0_I_i_3_n_0,
I5 => read_Mux_In(31),
O => p_33_in
);
PWM_FF_I_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"AB"
)
port map (
I0 => \^generateout1\,
I1 => read_Mux_In(22),
I2 => read_Mux_In(54),
O => R
);
PWM_FF_I_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^generateout0\,
I1 => pwm0,
O => PWM_FF_I
);
READ_DONE0_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
Q => \^d_0\,
R => R_0
);
READ_DONE0_I_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AA00AA00ABFFAA00"
)
port map (
I0 => READ_DONE0_I_i_3_n_0,
I1 => \^q\(1),
I2 => counter_TC(0),
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => captureTrig0_d,
I5 => captureTrig0_d2,
O => R_0
);
READ_DONE0_I_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"A8"
)
port map (
I0 => counter_TC_Reg2,
I1 => captureTrig0_pulse_d2,
I2 => captureTrig0_pulse_d1,
O => READ_DONE0_I_i_3_n_0
);
READ_DONE1_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
Q => \^read_done1\,
R => READ_DONE1_I_i_1_n_0
);
READ_DONE1_I_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"E0E0EFE0"
)
port map (
I0 => READ_DONE0_I_i_3_n_0,
I1 => READ_DONE1_I_i_3_n_0,
I2 => \^inferred_gen.icount_out_reg[0]\,
I3 => captureTrig1_d,
I4 => captureTrig1_d2,
O => READ_DONE1_I_i_1_n_0
);
READ_DONE1_I_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => captureTrig0_d2,
I1 => captureTrig0_d,
I2 => counter_TC(0),
I3 => \^q\(1),
O => READ_DONE1_I_i_3_n_0
);
\TCSR0_GENERATE[20].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(9),
Q => \^inferred_gen.icount_out_reg[0]\,
R => SR(0)
);
\TCSR0_GENERATE[21].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => s_axi_wdata(8),
Q => read_Mux_In(21),
R => SR(0)
);
\TCSR0_GENERATE[22].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(7),
Q => read_Mux_In(22),
R => SR(0)
);
\TCSR0_GENERATE[23].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\,
Q => read_Mux_In(23),
R => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF3F2F0F2"
)
port map (
I0 => generateOutPre0,
I1 => read_Mux_In(31),
I2 => \TCSR0_Set2__0\,
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => generateOutPre1,
I5 => read_Mux_In(23),
O => \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0\
);
\TCSR0_GENERATE[23].TCSR0_FF_I_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8AAA80000000000"
)
port map (
I0 => read_Mux_In(31),
I1 => READ_DONE0_I_i_3_n_0,
I2 => READ_DONE1_I_i_3_n_0,
I3 => \^inferred_gen.icount_out_reg[0]\,
I4 => captureTrig0_pulse_d1_i_1_n_0,
I5 => \^tcsr0_generate[24].tcsr0_ff_i_0\,
O => \TCSR0_Set2__0\
);
\TCSR0_GENERATE[24].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => \TCSR0_GENERATE[24].TCSR0_FF_I_1\,
Q => \^tcsr0_generate[24].tcsr0_ff_i_0\,
R => SR(0)
);
\TCSR0_GENERATE[25].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(6),
Q => read_Mux_In(25),
R => SR(0)
);
\TCSR0_GENERATE[26].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(5),
Q => read_Mux_In(26),
R => SR(0)
);
\TCSR0_GENERATE[27].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(4),
Q => read_Mux_In(27),
R => SR(0)
);
\TCSR0_GENERATE[28].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(3),
Q => read_Mux_In(28),
R => SR(0)
);
\TCSR0_GENERATE[29].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(2),
Q => read_Mux_In(29),
R => SR(0)
);
\TCSR0_GENERATE[30].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(1),
Q => read_Mux_In(30),
R => SR(0)
);
\TCSR0_GENERATE[31].TCSR0_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(1),
D => s_axi_wdata(0),
Q => read_Mux_In(31),
R => SR(0)
);
\TCSR1_GENERATE[21].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => s_axi_wdata(8),
Q => read_Mux_In(53),
R => SR(0)
);
\TCSR1_GENERATE[22].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(7),
Q => read_Mux_In(54),
R => SR(0)
);
\TCSR1_GENERATE[23].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\,
Q => read_Mux_In(55),
R => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\
);
\TCSR1_GENERATE[23].TCSR1_FF_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00008F80"
)
port map (
I0 => \^tcsr1_generate[23].tcsr1_ff_i_0\,
I1 => READ_DONE1_I_i_1_n_0,
I2 => read_Mux_In(63),
I3 => generateOutPre1,
I4 => \^inferred_gen.icount_out_reg[0]\,
I5 => read_Mux_In(55),
O => \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0\
);
\TCSR1_GENERATE[24].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => pair0_Select,
D => \TCSR1_GENERATE[24].TCSR1_FF_I_0\,
Q => \^tcsr1_generate[23].tcsr1_ff_i_0\,
R => SR(0)
);
\TCSR1_GENERATE[25].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(6),
Q => read_Mux_In(57),
R => SR(0)
);
\TCSR1_GENERATE[26].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(5),
Q => read_Mux_In(58),
R => SR(0)
);
\TCSR1_GENERATE[27].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(4),
Q => read_Mux_In(59),
R => SR(0)
);
\TCSR1_GENERATE[28].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(3),
Q => read_Mux_In(60),
R => SR(0)
);
\TCSR1_GENERATE[29].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(2),
Q => read_Mux_In(61),
R => SR(0)
);
\TCSR1_GENERATE[30].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(1),
Q => read_Mux_In(62),
R => SR(0)
);
\TCSR1_GENERATE[31].TCSR1_FF_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_wrce(0),
D => s_axi_wdata(0),
Q => read_Mux_In(63),
R => SR(0)
);
captureTrig0_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_d,
Q => captureTrig0_d2,
R => SR(0)
);
captureTrig0_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_d0,
Q => captureTrig0_d,
R => SR(0)
);
captureTrig0_pulse_d1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => captureTrig0_d,
I1 => captureTrig0_d2,
O => captureTrig0_pulse_d1_i_1_n_0
);
captureTrig0_pulse_d1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_pulse_d1_i_1_n_0,
Q => captureTrig0_pulse_d1,
R => SR(0)
);
captureTrig0_pulse_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig0_pulse_d1,
Q => captureTrig0_pulse_d2,
R => SR(0)
);
captureTrig1_d2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig1_d,
Q => captureTrig1_d2,
R => SR(0)
);
captureTrig1_d_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => captureTrig1_d0,
Q => captureTrig1_d,
R => SR(0)
);
counter_TC_Reg2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^q\(1),
Q => counter_TC_Reg2,
R => SR(0)
);
\counter_TC_Reg_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => counter_TC(0),
Q => \^q\(1),
R => SR(0)
);
\counter_TC_Reg_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => counter_TC(1),
Q => \^q\(0),
R => SR(0)
);
generateOutPre0_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out_reg[32]_0\,
Q => generateOutPre0,
R => SR(0)
);
generateOutPre1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \INFERRED_GEN.icount_out_reg[32]\,
Q => generateOutPre1,
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_slave_attachment is
port (
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\s_axi_rdata_i_reg[12]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]_0\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\s_axi_rdata_i_reg[11]_0\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LOAD_REG_GEN[31].LOAD_REG_I_1\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg_1 : out STD_LOGIC;
s_axi_rvalid_i_reg_2 : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_1\ : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_slave_attachment : entity is "slave_attachment";
end zqynq_lab_1_design_axi_timer_0_0_slave_attachment;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal I_DECODER_n_100 : STD_LOGIC;
signal I_DECODER_n_101 : STD_LOGIC;
signal I_DECODER_n_25 : STD_LOGIC;
signal I_DECODER_n_26 : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 2 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[4]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 5 downto 0 );
signal rst : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \bus2ip_addr_i[4]_i_2\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair16";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
O => plusOp(4)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
O => plusOp(5)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(4),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(4),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(5),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5),
R => clear
);
I_DECODER: entity work.zqynq_lab_1_design_axi_timer_0_0_address_decoder
port map (
D(1) => I_DECODER_n_25,
D(0) => I_DECODER_n_26,
D_0 => D_0,
D_1 => D_1,
D_2 => D_2,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]\(5 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(5 downto 0),
\LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\,
\LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\,
\LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\,
\LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\,
\LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\,
\LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\,
\LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\,
\LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\,
\LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\,
\LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\,
\LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\,
\LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\,
\LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\,
\LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\,
\LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\,
\LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\,
\LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\,
\LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\,
\LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\,
\LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\,
\LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I\ => \LOAD_REG_GEN[31].LOAD_REG_I\,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_1\,
\LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\,
\LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\,
\LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\,
\LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\,
\LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\,
\LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\,
\LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\,
Q => start2,
READ_DONE0_I => READ_DONE0_I,
READ_DONE1_I => READ_DONE1_I,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => \TCSR0_GENERATE[23].TCSR0_FF_I\,
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ => \TCSR0_GENERATE[23].TCSR0_FF_I_0\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
\bus2ip_addr_i_reg[4]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[4]\(1) => bus2ip_addr(1),
\bus2ip_addr_i_reg[4]\(0) => bus2ip_addr(2),
bus2ip_rnw_i => bus2ip_rnw_i,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
is_read => is_read,
is_write_reg => is_write_reg_n_0,
pair0_Select => pair0_Select,
read_Mux_In(87 downto 0) => read_Mux_In(87 downto 0),
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_arvalid_0 => \state[1]_i_3_n_0\,
s_axi_bready => s_axi_bready,
s_axi_bvalid_i_reg => I_DECODER_n_101,
s_axi_bvalid_i_reg_0 => \^s_axi_bvalid\,
\s_axi_rdata_i_reg[0]\ => \s_axi_rdata_i_reg[0]_0\,
\s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]_1\,
\s_axi_rdata_i_reg[10]\ => \s_axi_rdata_i_reg[10]_0\,
\s_axi_rdata_i_reg[11]\ => \s_axi_rdata_i_reg[11]_0\,
\s_axi_rdata_i_reg[12]\ => \s_axi_rdata_i_reg[12]_0\,
\s_axi_rdata_i_reg[13]\ => \s_axi_rdata_i_reg[13]_0\,
\s_axi_rdata_i_reg[14]\ => \s_axi_rdata_i_reg[14]_0\,
\s_axi_rdata_i_reg[15]\ => \s_axi_rdata_i_reg[15]_0\,
\s_axi_rdata_i_reg[16]\ => \s_axi_rdata_i_reg[16]_0\,
\s_axi_rdata_i_reg[17]\ => \s_axi_rdata_i_reg[17]_0\,
\s_axi_rdata_i_reg[18]\ => \s_axi_rdata_i_reg[18]_0\,
\s_axi_rdata_i_reg[19]\ => \s_axi_rdata_i_reg[19]_0\,
\s_axi_rdata_i_reg[20]\ => \s_axi_rdata_i_reg[20]_0\,
\s_axi_rdata_i_reg[21]\ => \s_axi_rdata_i_reg[21]_0\,
\s_axi_rdata_i_reg[22]\ => \s_axi_rdata_i_reg[22]_0\,
\s_axi_rdata_i_reg[23]\ => \s_axi_rdata_i_reg[23]_0\,
\s_axi_rdata_i_reg[24]\ => \s_axi_rdata_i_reg[24]_0\,
\s_axi_rdata_i_reg[25]\ => \s_axi_rdata_i_reg[25]_0\,
\s_axi_rdata_i_reg[26]\ => \s_axi_rdata_i_reg[26]_0\,
\s_axi_rdata_i_reg[27]\ => \s_axi_rdata_i_reg[27]_0\,
\s_axi_rdata_i_reg[28]\ => \s_axi_rdata_i_reg[28]_0\,
\s_axi_rdata_i_reg[29]\ => \s_axi_rdata_i_reg[29]_0\,
\s_axi_rdata_i_reg[30]\ => \s_axi_rdata_i_reg[30]_0\,
\s_axi_rdata_i_reg[31]\ => \s_axi_rdata_i_reg[31]_0\,
s_axi_rready => s_axi_rready,
s_axi_rvalid_i_reg => s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg_1,
s_axi_rvalid_i_reg_1 => s_axi_rvalid_i_reg_2,
s_axi_rvalid_i_reg_2 => I_DECODER_n_100,
s_axi_rvalid_i_reg_3 => \^s_axi_rvalid\,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
\state1__2\ => \state1__2\,
\state_reg[1]\(1 downto 0) => state(1 downto 0)
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(0),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(0),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(1),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(1),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[4]_i_1_n_0\
);
\bus2ip_addr_i[4]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFF0200"
)
port map (
I0 => s_axi_araddr(2),
I1 => state(0),
I2 => state(1),
I3 => s_axi_arvalid,
I4 => s_axi_awaddr(2),
O => \bus2ip_addr_i[4]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(2),
R => rst
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(1),
R => rst
);
\bus2ip_addr_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => \bus2ip_addr_i[4]_i_2_n_0\,
Q => bus2ip_addr(0),
R => rst
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[4]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => bus2ip_rnw_i,
R => rst
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => rst
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => rst
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => bus2ip_reset,
Q => rst,
R => '0'
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_101,
Q => \^s_axi_bvalid\,
R => rst
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[31]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(0),
Q => s_axi_rdata(0),
R => rst
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(10),
Q => s_axi_rdata(10),
R => rst
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(11),
Q => s_axi_rdata(11),
R => rst
);
\s_axi_rdata_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(12),
Q => s_axi_rdata(12),
R => rst
);
\s_axi_rdata_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(13),
Q => s_axi_rdata(13),
R => rst
);
\s_axi_rdata_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(14),
Q => s_axi_rdata(14),
R => rst
);
\s_axi_rdata_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(15),
Q => s_axi_rdata(15),
R => rst
);
\s_axi_rdata_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(16),
Q => s_axi_rdata(16),
R => rst
);
\s_axi_rdata_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(17),
Q => s_axi_rdata(17),
R => rst
);
\s_axi_rdata_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(18),
Q => s_axi_rdata(18),
R => rst
);
\s_axi_rdata_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(19),
Q => s_axi_rdata(19),
R => rst
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(1),
Q => s_axi_rdata(1),
R => rst
);
\s_axi_rdata_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(20),
Q => s_axi_rdata(20),
R => rst
);
\s_axi_rdata_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(21),
Q => s_axi_rdata(21),
R => rst
);
\s_axi_rdata_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(22),
Q => s_axi_rdata(22),
R => rst
);
\s_axi_rdata_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(23),
Q => s_axi_rdata(23),
R => rst
);
\s_axi_rdata_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(24),
Q => s_axi_rdata(24),
R => rst
);
\s_axi_rdata_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(25),
Q => s_axi_rdata(25),
R => rst
);
\s_axi_rdata_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(26),
Q => s_axi_rdata(26),
R => rst
);
\s_axi_rdata_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(27),
Q => s_axi_rdata(27),
R => rst
);
\s_axi_rdata_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(28),
Q => s_axi_rdata(28),
R => rst
);
\s_axi_rdata_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(29),
Q => s_axi_rdata(29),
R => rst
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(2),
Q => s_axi_rdata(2),
R => rst
);
\s_axi_rdata_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(30),
Q => s_axi_rdata(30),
R => rst
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(31),
Q => s_axi_rdata(31),
R => rst
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(3),
Q => s_axi_rdata(3),
R => rst
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(4),
Q => s_axi_rdata(4),
R => rst
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(5),
Q => s_axi_rdata(5),
R => rst
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(6),
Q => s_axi_rdata(6),
R => rst
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(7),
Q => s_axi_rdata(7),
R => rst
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(8),
Q => s_axi_rdata(8),
R => rst
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[31]_i_1_n_0\,
D => D(9),
Q => s_axi_rdata(9),
R => rst
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_100,
Q => \^s_axi_rvalid\,
R => rst
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => rst
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_26,
Q => state(0),
R => rst
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => I_DECODER_n_25,
Q => state(1),
R => rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_tc_core is
port (
D : out STD_LOGIC_VECTOR ( 31 downto 0 );
\INFERRED_GEN.icount_out_reg[0]\ : out STD_LOGIC_VECTOR ( 87 downto 0 );
bus2ip_reset : out STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
interrupt : out STD_LOGIC;
D_0 : out STD_LOGIC;
read_done1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
Bus_RNW_reg_reg : in STD_LOGIC;
Bus_RNW_reg_reg_0 : in STD_LOGIC;
Bus_RNW_reg_reg_1 : in STD_LOGIC;
Bus_RNW_reg_reg_2 : in STD_LOGIC;
Bus_RNW_reg_reg_3 : in STD_LOGIC;
Bus_RNW_reg_reg_4 : in STD_LOGIC;
Bus_RNW_reg_reg_5 : in STD_LOGIC;
Bus_RNW_reg_reg_6 : in STD_LOGIC;
Bus_RNW_reg_reg_7 : in STD_LOGIC;
Bus_RNW_reg_reg_8 : in STD_LOGIC;
Bus_RNW_reg_reg_9 : in STD_LOGIC;
Bus_RNW_reg_reg_10 : in STD_LOGIC;
Bus_RNW_reg_reg_11 : in STD_LOGIC;
Bus_RNW_reg_reg_12 : in STD_LOGIC;
Bus_RNW_reg_reg_13 : in STD_LOGIC;
Bus_RNW_reg_reg_14 : in STD_LOGIC;
Bus_RNW_reg_reg_15 : in STD_LOGIC;
Bus_RNW_reg_reg_16 : in STD_LOGIC;
Bus_RNW_reg_reg_17 : in STD_LOGIC;
Bus_RNW_reg_reg_18 : in STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : in STD_LOGIC;
D_1 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ : in STD_LOGIC;
D_2 : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[30]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[29]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[28]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[27]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[26]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[25]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[24]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[23]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[22]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[21]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[20]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[19]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[18]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[17]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[16]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[15]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[14]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[13]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[12]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[11]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[10]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[9]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[8]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[7]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[6]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[5]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[4]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[3]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[2]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[1]\ : in STD_LOGIC;
\INFERRED_GEN.icount_out_reg[0]_0\ : in STD_LOGIC;
bus2ip_wrce : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 9 downto 0 );
pair0_Select : in STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : in STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ : in STD_LOGIC;
Bus_RNW_reg : in STD_LOGIC;
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : in STD_LOGIC;
\bus2ip_wrce__0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
freeze : in STD_LOGIC;
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_tc_core : entity is "tc_core";
end zqynq_lab_1_design_axi_timer_0_0_tc_core;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_tc_core is
signal COUNTER_0_I_n_64 : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_33\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_34\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_35\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_36\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_37\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_38\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_39\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_40\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_41\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_42\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_43\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_44\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_45\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_46\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_47\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_48\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_49\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_50\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_51\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_52\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_53\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_54\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_55\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_56\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_57\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_58\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_59\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_60\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_61\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_62\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_63\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_64\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I_n_65\ : STD_LOGIC;
signal \^inferred_gen.icount_out_reg[0]\ : STD_LOGIC_VECTOR ( 87 downto 0 );
signal R : STD_LOGIC;
signal TIMER_CONTROL_I_n_12 : STD_LOGIC;
signal TIMER_CONTROL_I_n_13 : STD_LOGIC;
signal TIMER_CONTROL_I_n_14 : STD_LOGIC;
signal TIMER_CONTROL_I_n_15 : STD_LOGIC;
signal TIMER_CONTROL_I_n_16 : STD_LOGIC;
signal TIMER_CONTROL_I_n_17 : STD_LOGIC;
signal TIMER_CONTROL_I_n_18 : STD_LOGIC;
signal TIMER_CONTROL_I_n_19 : STD_LOGIC;
signal TIMER_CONTROL_I_n_20 : STD_LOGIC;
signal TIMER_CONTROL_I_n_21 : STD_LOGIC;
signal TIMER_CONTROL_I_n_22 : STD_LOGIC;
signal TIMER_CONTROL_I_n_24 : STD_LOGIC;
signal TIMER_CONTROL_I_n_25 : STD_LOGIC;
signal TIMER_CONTROL_I_n_26 : STD_LOGIC;
signal TIMER_CONTROL_I_n_27 : STD_LOGIC;
signal TIMER_CONTROL_I_n_28 : STD_LOGIC;
signal TIMER_CONTROL_I_n_29 : STD_LOGIC;
signal TIMER_CONTROL_I_n_3 : STD_LOGIC;
signal TIMER_CONTROL_I_n_30 : STD_LOGIC;
signal TIMER_CONTROL_I_n_4 : STD_LOGIC;
signal \^bus2ip_reset\ : STD_LOGIC;
signal counter_TC : STD_LOGIC_VECTOR ( 0 to 1 );
signal load_Counter_Reg : STD_LOGIC_VECTOR ( 0 to 1 );
signal \^pwm0\ : STD_LOGIC;
signal read_Mux_In : STD_LOGIC_VECTOR ( 85 to 95 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of PWM_FF_I : label is "PRIMITIVE";
attribute IS_S_INVERTED : string;
attribute IS_S_INVERTED of PWM_FF_I : label is "1'b0";
begin
\INFERRED_GEN.icount_out_reg[0]\(87 downto 0) <= \^inferred_gen.icount_out_reg[0]\(87 downto 0);
bus2ip_reset <= \^bus2ip_reset\;
pwm0 <= \^pwm0\;
COUNTER_0_I: entity work.zqynq_lab_1_design_axi_timer_0_0_count_module
port map (
D_1 => D_1,
E(0) => TIMER_CONTROL_I_n_24,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\,
\INFERRED_GEN.icount_out_reg[31]\(52 downto 0) => \^inferred_gen.icount_out_reg[0]\(84 downto 32),
Q(0) => TIMER_CONTROL_I_n_3,
S(0) => TIMER_CONTROL_I_n_27,
\TCSR0_GENERATE[27].TCSR0_FF_I\ => TIMER_CONTROL_I_n_28,
counter_TC(0) => counter_TC(0),
generateOutPre0_reg => COUNTER_0_I_n_64,
load_Counter_Reg(0) => load_Counter_Reg(0),
read_Mux_In(10) => read_Mux_In(85),
read_Mux_In(9) => read_Mux_In(86),
read_Mux_In(8) => read_Mux_In(87),
read_Mux_In(7) => read_Mux_In(88),
read_Mux_In(6) => read_Mux_In(89),
read_Mux_In(5) => read_Mux_In(90),
read_Mux_In(4) => read_Mux_In(91),
read_Mux_In(3) => read_Mux_In(92),
read_Mux_In(2) => read_Mux_In(93),
read_Mux_In(1) => read_Mux_In(94),
read_Mux_In(0) => read_Mux_In(95),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => \^bus2ip_reset\
);
\GEN_SECOND_TIMER.COUNTER_1_I\: entity work.zqynq_lab_1_design_axi_timer_0_0_count_module_0
port map (
D_2 => D_2,
E(0) => TIMER_CONTROL_I_n_25,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\,
\INFERRED_GEN.icount_out_reg[0]\ => \INFERRED_GEN.icount_out_reg[0]_0\,
\INFERRED_GEN.icount_out_reg[10]\ => \INFERRED_GEN.icount_out_reg[10]\,
\INFERRED_GEN.icount_out_reg[11]\ => \INFERRED_GEN.icount_out_reg[11]\,
\INFERRED_GEN.icount_out_reg[12]\ => \INFERRED_GEN.icount_out_reg[12]\,
\INFERRED_GEN.icount_out_reg[13]\ => \INFERRED_GEN.icount_out_reg[13]\,
\INFERRED_GEN.icount_out_reg[14]\ => \INFERRED_GEN.icount_out_reg[14]\,
\INFERRED_GEN.icount_out_reg[15]\ => \INFERRED_GEN.icount_out_reg[15]\,
\INFERRED_GEN.icount_out_reg[16]\ => \INFERRED_GEN.icount_out_reg[16]\,
\INFERRED_GEN.icount_out_reg[17]\ => \INFERRED_GEN.icount_out_reg[17]\,
\INFERRED_GEN.icount_out_reg[18]\ => \INFERRED_GEN.icount_out_reg[18]\,
\INFERRED_GEN.icount_out_reg[19]\ => \INFERRED_GEN.icount_out_reg[19]\,
\INFERRED_GEN.icount_out_reg[1]\ => \INFERRED_GEN.icount_out_reg[1]\,
\INFERRED_GEN.icount_out_reg[20]\ => \INFERRED_GEN.icount_out_reg[20]\,
\INFERRED_GEN.icount_out_reg[21]\ => \INFERRED_GEN.icount_out_reg[21]\,
\INFERRED_GEN.icount_out_reg[22]\ => \INFERRED_GEN.icount_out_reg[22]\,
\INFERRED_GEN.icount_out_reg[23]\ => \INFERRED_GEN.icount_out_reg[23]\,
\INFERRED_GEN.icount_out_reg[24]\ => \INFERRED_GEN.icount_out_reg[24]\,
\INFERRED_GEN.icount_out_reg[25]\ => \INFERRED_GEN.icount_out_reg[25]\,
\INFERRED_GEN.icount_out_reg[26]\ => \INFERRED_GEN.icount_out_reg[26]\,
\INFERRED_GEN.icount_out_reg[27]\ => \INFERRED_GEN.icount_out_reg[27]\,
\INFERRED_GEN.icount_out_reg[28]\ => \INFERRED_GEN.icount_out_reg[28]\,
\INFERRED_GEN.icount_out_reg[29]\ => \INFERRED_GEN.icount_out_reg[29]\,
\INFERRED_GEN.icount_out_reg[2]\ => \INFERRED_GEN.icount_out_reg[2]\,
\INFERRED_GEN.icount_out_reg[30]\ => \INFERRED_GEN.icount_out_reg[30]\,
\INFERRED_GEN.icount_out_reg[31]\ => \^bus2ip_reset\,
\INFERRED_GEN.icount_out_reg[31]_0\(31 downto 0) => \^inferred_gen.icount_out_reg[0]\(63 downto 32),
\INFERRED_GEN.icount_out_reg[3]\ => \INFERRED_GEN.icount_out_reg[3]\,
\INFERRED_GEN.icount_out_reg[4]\ => \INFERRED_GEN.icount_out_reg[4]\,
\INFERRED_GEN.icount_out_reg[5]\ => \INFERRED_GEN.icount_out_reg[5]\,
\INFERRED_GEN.icount_out_reg[6]\ => \INFERRED_GEN.icount_out_reg[6]\,
\INFERRED_GEN.icount_out_reg[7]\ => \INFERRED_GEN.icount_out_reg[7]\,
\INFERRED_GEN.icount_out_reg[8]\ => \INFERRED_GEN.icount_out_reg[8]\,
\INFERRED_GEN.icount_out_reg[9]\ => \INFERRED_GEN.icount_out_reg[9]\,
Q(31 downto 0) => \^inferred_gen.icount_out_reg[0]\(31 downto 0),
S(0) => TIMER_CONTROL_I_n_30,
\TCSR0_GENERATE[20].TCSR0_FF_I\ => TIMER_CONTROL_I_n_29,
counter_TC(0) => counter_TC(1),
\counter_TC_Reg_reg[1]\(0) => TIMER_CONTROL_I_n_4,
generateOutPre1_reg => \GEN_SECOND_TIMER.COUNTER_1_I_n_65\,
load_Counter_Reg(0) => load_Counter_Reg(1),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
\s_axi_rdata_i_reg[0]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_33\,
\s_axi_rdata_i_reg[10]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_43\,
\s_axi_rdata_i_reg[11]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_44\,
\s_axi_rdata_i_reg[12]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_45\,
\s_axi_rdata_i_reg[13]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_46\,
\s_axi_rdata_i_reg[14]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_47\,
\s_axi_rdata_i_reg[15]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_48\,
\s_axi_rdata_i_reg[16]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_49\,
\s_axi_rdata_i_reg[17]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_50\,
\s_axi_rdata_i_reg[18]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_51\,
\s_axi_rdata_i_reg[19]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_52\,
\s_axi_rdata_i_reg[1]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_34\,
\s_axi_rdata_i_reg[20]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_53\,
\s_axi_rdata_i_reg[21]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_54\,
\s_axi_rdata_i_reg[22]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_55\,
\s_axi_rdata_i_reg[23]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_56\,
\s_axi_rdata_i_reg[24]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_57\,
\s_axi_rdata_i_reg[25]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_58\,
\s_axi_rdata_i_reg[26]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_59\,
\s_axi_rdata_i_reg[27]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_60\,
\s_axi_rdata_i_reg[28]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_61\,
\s_axi_rdata_i_reg[29]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_62\,
\s_axi_rdata_i_reg[2]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_35\,
\s_axi_rdata_i_reg[30]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_63\,
\s_axi_rdata_i_reg[31]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_64\,
\s_axi_rdata_i_reg[3]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_36\,
\s_axi_rdata_i_reg[4]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_37\,
\s_axi_rdata_i_reg[5]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_38\,
\s_axi_rdata_i_reg[6]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_39\,
\s_axi_rdata_i_reg[7]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_40\,
\s_axi_rdata_i_reg[8]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_41\,
\s_axi_rdata_i_reg[9]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_42\
);
PWM_FF_I: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => TIMER_CONTROL_I_n_26,
Q => \^pwm0\,
R => R
);
READ_MUX_I: entity work.zqynq_lab_1_design_axi_timer_0_0_mux_onehot_f
port map (
Bus_RNW_reg_reg => Bus_RNW_reg_reg,
Bus_RNW_reg_reg_0 => Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1 => Bus_RNW_reg_reg_1,
Bus_RNW_reg_reg_10 => Bus_RNW_reg_reg_10,
Bus_RNW_reg_reg_11 => Bus_RNW_reg_reg_11,
Bus_RNW_reg_reg_12 => Bus_RNW_reg_reg_12,
Bus_RNW_reg_reg_13 => Bus_RNW_reg_reg_13,
Bus_RNW_reg_reg_14 => Bus_RNW_reg_reg_14,
Bus_RNW_reg_reg_15 => Bus_RNW_reg_reg_15,
Bus_RNW_reg_reg_16 => Bus_RNW_reg_reg_16,
Bus_RNW_reg_reg_17 => Bus_RNW_reg_reg_17,
Bus_RNW_reg_reg_18 => Bus_RNW_reg_reg_18,
Bus_RNW_reg_reg_2 => Bus_RNW_reg_reg_2,
Bus_RNW_reg_reg_3 => Bus_RNW_reg_reg_3,
Bus_RNW_reg_reg_4 => Bus_RNW_reg_reg_4,
Bus_RNW_reg_reg_5 => Bus_RNW_reg_reg_5,
Bus_RNW_reg_reg_6 => Bus_RNW_reg_reg_6,
Bus_RNW_reg_reg_7 => Bus_RNW_reg_reg_7,
Bus_RNW_reg_reg_8 => Bus_RNW_reg_reg_8,
Bus_RNW_reg_reg_9 => Bus_RNW_reg_reg_9,
D(31 downto 0) => D(31 downto 0),
\INFERRED_GEN.icount_out_reg[0]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_33\,
\INFERRED_GEN.icount_out_reg[10]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_43\,
\INFERRED_GEN.icount_out_reg[11]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_44\,
\INFERRED_GEN.icount_out_reg[12]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_45\,
\INFERRED_GEN.icount_out_reg[13]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_46\,
\INFERRED_GEN.icount_out_reg[14]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_47\,
\INFERRED_GEN.icount_out_reg[15]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_48\,
\INFERRED_GEN.icount_out_reg[16]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_49\,
\INFERRED_GEN.icount_out_reg[17]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_50\,
\INFERRED_GEN.icount_out_reg[18]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_51\,
\INFERRED_GEN.icount_out_reg[19]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_52\,
\INFERRED_GEN.icount_out_reg[1]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_34\,
\INFERRED_GEN.icount_out_reg[20]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_53\,
\INFERRED_GEN.icount_out_reg[21]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_54\,
\INFERRED_GEN.icount_out_reg[22]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_55\,
\INFERRED_GEN.icount_out_reg[23]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_56\,
\INFERRED_GEN.icount_out_reg[24]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_57\,
\INFERRED_GEN.icount_out_reg[25]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_58\,
\INFERRED_GEN.icount_out_reg[26]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_59\,
\INFERRED_GEN.icount_out_reg[27]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_60\,
\INFERRED_GEN.icount_out_reg[28]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_61\,
\INFERRED_GEN.icount_out_reg[29]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_62\,
\INFERRED_GEN.icount_out_reg[2]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_35\,
\INFERRED_GEN.icount_out_reg[30]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_63\,
\INFERRED_GEN.icount_out_reg[31]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_64\,
\INFERRED_GEN.icount_out_reg[3]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_36\,
\INFERRED_GEN.icount_out_reg[4]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_37\,
\INFERRED_GEN.icount_out_reg[5]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_38\,
\INFERRED_GEN.icount_out_reg[6]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_39\,
\INFERRED_GEN.icount_out_reg[7]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_40\,
\INFERRED_GEN.icount_out_reg[8]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_41\,
\INFERRED_GEN.icount_out_reg[9]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_42\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => TIMER_CONTROL_I_n_22,
\LOAD_REG_GEN[22].LOAD_REG_I\ => TIMER_CONTROL_I_n_21,
\LOAD_REG_GEN[23].LOAD_REG_I\ => TIMER_CONTROL_I_n_20,
\LOAD_REG_GEN[24].LOAD_REG_I\ => TIMER_CONTROL_I_n_19,
\LOAD_REG_GEN[25].LOAD_REG_I\ => TIMER_CONTROL_I_n_18,
\LOAD_REG_GEN[26].LOAD_REG_I\ => TIMER_CONTROL_I_n_17,
\LOAD_REG_GEN[27].LOAD_REG_I\ => TIMER_CONTROL_I_n_16,
\LOAD_REG_GEN[28].LOAD_REG_I\ => TIMER_CONTROL_I_n_15,
\LOAD_REG_GEN[29].LOAD_REG_I\ => TIMER_CONTROL_I_n_14,
\LOAD_REG_GEN[30].LOAD_REG_I\ => TIMER_CONTROL_I_n_13,
\LOAD_REG_GEN[31].LOAD_REG_I\ => TIMER_CONTROL_I_n_12
);
TIMER_CONTROL_I: entity work.zqynq_lab_1_design_axi_timer_0_0_timer_control
port map (
Bus_RNW_reg => Bus_RNW_reg,
D_0 => D_0,
E(0) => TIMER_CONTROL_I_n_24,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\,
\INFERRED_GEN.icount_out_reg[0]\ => \^inferred_gen.icount_out_reg[0]\(87),
\INFERRED_GEN.icount_out_reg[0]_0\(0) => TIMER_CONTROL_I_n_25,
\INFERRED_GEN.icount_out_reg[1]\(1) => \^inferred_gen.icount_out_reg[0]\(33),
\INFERRED_GEN.icount_out_reg[1]\(0) => \^inferred_gen.icount_out_reg[0]\(1),
\INFERRED_GEN.icount_out_reg[32]\ => \GEN_SECOND_TIMER.COUNTER_1_I_n_65\,
\INFERRED_GEN.icount_out_reg[32]_0\ => COUNTER_0_I_n_64,
\INFERRED_GEN.icount_out_reg[4]\(0) => TIMER_CONTROL_I_n_30,
\LOAD_REG_GEN[21].LOAD_REG_I\(10) => read_Mux_In(85),
\LOAD_REG_GEN[21].LOAD_REG_I\(9) => read_Mux_In(86),
\LOAD_REG_GEN[21].LOAD_REG_I\(8) => read_Mux_In(87),
\LOAD_REG_GEN[21].LOAD_REG_I\(7) => read_Mux_In(88),
\LOAD_REG_GEN[21].LOAD_REG_I\(6) => read_Mux_In(89),
\LOAD_REG_GEN[21].LOAD_REG_I\(5) => read_Mux_In(90),
\LOAD_REG_GEN[21].LOAD_REG_I\(4) => read_Mux_In(91),
\LOAD_REG_GEN[21].LOAD_REG_I\(3) => read_Mux_In(92),
\LOAD_REG_GEN[21].LOAD_REG_I\(2) => read_Mux_In(93),
\LOAD_REG_GEN[21].LOAD_REG_I\(1) => read_Mux_In(94),
\LOAD_REG_GEN[21].LOAD_REG_I\(0) => read_Mux_In(95),
\LOAD_REG_GEN[24].LOAD_REG_I\ => TIMER_CONTROL_I_n_28,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => TIMER_CONTROL_I_n_29,
PWM_FF_I => TIMER_CONTROL_I_n_26,
Q(1) => TIMER_CONTROL_I_n_3,
Q(0) => TIMER_CONTROL_I_n_4,
R => R,
S(0) => TIMER_CONTROL_I_n_27,
SR(0) => \^bus2ip_reset\,
\TCSR0_GENERATE[24].TCSR0_FF_I_0\ => \^inferred_gen.icount_out_reg[0]\(86),
\TCSR0_GENERATE[24].TCSR0_FF_I_1\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I_0\ => \^inferred_gen.icount_out_reg[0]\(85),
\TCSR1_GENERATE[24].TCSR1_FF_I_0\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
counter_TC(0 to 1) => counter_TC(0 to 1),
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
load_Counter_Reg(0 to 1) => load_Counter_Reg(0 to 1),
pair0_Select => pair0_Select,
pwm0 => \^pwm0\,
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
\s_axi_rdata_i_reg[0]\ => TIMER_CONTROL_I_n_12,
\s_axi_rdata_i_reg[10]\ => TIMER_CONTROL_I_n_22,
\s_axi_rdata_i_reg[1]\ => TIMER_CONTROL_I_n_13,
\s_axi_rdata_i_reg[2]\ => TIMER_CONTROL_I_n_14,
\s_axi_rdata_i_reg[3]\ => TIMER_CONTROL_I_n_15,
\s_axi_rdata_i_reg[4]\ => TIMER_CONTROL_I_n_16,
\s_axi_rdata_i_reg[5]\ => TIMER_CONTROL_I_n_17,
\s_axi_rdata_i_reg[6]\ => TIMER_CONTROL_I_n_18,
\s_axi_rdata_i_reg[7]\ => TIMER_CONTROL_I_n_19,
\s_axi_rdata_i_reg[8]\ => TIMER_CONTROL_I_n_20,
\s_axi_rdata_i_reg[9]\ => TIMER_CONTROL_I_n_21,
s_axi_wdata(9 downto 0) => s_axi_wdata(9 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_axi_lite_ipif is
port (
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : out STD_LOGIC;
Bus_RNW_reg : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\s_axi_rdata_i_reg[12]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[13]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[14]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[15]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[16]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[17]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[18]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[19]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[20]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[21]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[22]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[23]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[24]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[25]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[26]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[27]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[28]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[29]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[30]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[31]\ : out STD_LOGIC;
pair0_Select : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\s_axi_rdata_i_reg[11]\ : out STD_LOGIC;
\TCSR0_GENERATE[24].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[24].TCSR1_FF_I\ : out STD_LOGIC;
\LOAD_REG_GEN[31].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I\ : out STD_LOGIC;
D_0 : out STD_LOGIC;
\bus2ip_wrce__0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_wrce : out STD_LOGIC_VECTOR ( 1 downto 0 );
\LOAD_REG_GEN[31].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[30].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[29].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[28].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[27].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[26].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[25].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[24].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[23].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[22].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[21].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[20].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[19].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[18].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[17].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[16].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[15].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[14].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[13].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[12].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[11].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[10].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[9].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[8].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[7].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[6].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[5].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[4].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[3].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[2].LOAD_REG_I_0\ : out STD_LOGIC;
\LOAD_REG_GEN[1].LOAD_REG_I_0\ : out STD_LOGIC;
D_1 : out STD_LOGIC;
s_axi_rvalid_i_reg : out STD_LOGIC;
s_axi_rvalid_i_reg_0 : out STD_LOGIC;
s_axi_rvalid_i_reg_1 : out STD_LOGIC;
\TCSR0_GENERATE[23].TCSR0_FF_I\ : out STD_LOGIC;
\TCSR1_GENERATE[23].TCSR1_FF_I\ : out STD_LOGIC;
\s_axi_rdata_i_reg[10]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]\ : out STD_LOGIC;
\s_axi_rdata_i_reg[0]_0\ : out STD_LOGIC;
READ_DONE0_I : out STD_LOGIC;
READ_DONE1_I : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
bus2ip_reset : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
read_Mux_In : in STD_LOGIC_VECTOR ( 87 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D_2 : in STD_LOGIC;
read_done1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_axi_lite_ipif : entity is "axi_lite_ipif";
end zqynq_lab_1_design_axi_timer_0_0_axi_lite_ipif;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.zqynq_lab_1_design_axi_timer_0_0_slave_attachment
port map (
D(31 downto 0) => D(31 downto 0),
D_0 => D_0,
D_1 => D_1,
D_2 => D_2,
\LOAD_REG_GEN[10].LOAD_REG_I\ => \LOAD_REG_GEN[10].LOAD_REG_I\,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => \LOAD_REG_GEN[10].LOAD_REG_I_0\,
\LOAD_REG_GEN[11].LOAD_REG_I\ => \LOAD_REG_GEN[11].LOAD_REG_I\,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => \LOAD_REG_GEN[11].LOAD_REG_I_0\,
\LOAD_REG_GEN[12].LOAD_REG_I\ => \LOAD_REG_GEN[12].LOAD_REG_I\,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => \LOAD_REG_GEN[12].LOAD_REG_I_0\,
\LOAD_REG_GEN[13].LOAD_REG_I\ => \LOAD_REG_GEN[13].LOAD_REG_I\,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => \LOAD_REG_GEN[13].LOAD_REG_I_0\,
\LOAD_REG_GEN[14].LOAD_REG_I\ => \LOAD_REG_GEN[14].LOAD_REG_I\,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => \LOAD_REG_GEN[14].LOAD_REG_I_0\,
\LOAD_REG_GEN[15].LOAD_REG_I\ => \LOAD_REG_GEN[15].LOAD_REG_I\,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => \LOAD_REG_GEN[15].LOAD_REG_I_0\,
\LOAD_REG_GEN[16].LOAD_REG_I\ => \LOAD_REG_GEN[16].LOAD_REG_I\,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => \LOAD_REG_GEN[16].LOAD_REG_I_0\,
\LOAD_REG_GEN[17].LOAD_REG_I\ => \LOAD_REG_GEN[17].LOAD_REG_I\,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => \LOAD_REG_GEN[17].LOAD_REG_I_0\,
\LOAD_REG_GEN[18].LOAD_REG_I\ => \LOAD_REG_GEN[18].LOAD_REG_I\,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => \LOAD_REG_GEN[18].LOAD_REG_I_0\,
\LOAD_REG_GEN[19].LOAD_REG_I\ => \LOAD_REG_GEN[19].LOAD_REG_I\,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => \LOAD_REG_GEN[19].LOAD_REG_I_0\,
\LOAD_REG_GEN[1].LOAD_REG_I\ => \LOAD_REG_GEN[1].LOAD_REG_I\,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => \LOAD_REG_GEN[1].LOAD_REG_I_0\,
\LOAD_REG_GEN[20].LOAD_REG_I\ => \LOAD_REG_GEN[20].LOAD_REG_I\,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => \LOAD_REG_GEN[20].LOAD_REG_I_0\,
\LOAD_REG_GEN[21].LOAD_REG_I\ => \LOAD_REG_GEN[21].LOAD_REG_I\,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => \LOAD_REG_GEN[21].LOAD_REG_I_0\,
\LOAD_REG_GEN[22].LOAD_REG_I\ => \LOAD_REG_GEN[22].LOAD_REG_I\,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => \LOAD_REG_GEN[22].LOAD_REG_I_0\,
\LOAD_REG_GEN[23].LOAD_REG_I\ => \LOAD_REG_GEN[23].LOAD_REG_I\,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => \LOAD_REG_GEN[23].LOAD_REG_I_0\,
\LOAD_REG_GEN[24].LOAD_REG_I\ => \LOAD_REG_GEN[24].LOAD_REG_I\,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => \LOAD_REG_GEN[24].LOAD_REG_I_0\,
\LOAD_REG_GEN[25].LOAD_REG_I\ => \LOAD_REG_GEN[25].LOAD_REG_I\,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => \LOAD_REG_GEN[25].LOAD_REG_I_0\,
\LOAD_REG_GEN[26].LOAD_REG_I\ => \LOAD_REG_GEN[26].LOAD_REG_I\,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => \LOAD_REG_GEN[26].LOAD_REG_I_0\,
\LOAD_REG_GEN[27].LOAD_REG_I\ => \LOAD_REG_GEN[27].LOAD_REG_I\,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => \LOAD_REG_GEN[27].LOAD_REG_I_0\,
\LOAD_REG_GEN[28].LOAD_REG_I\ => \LOAD_REG_GEN[28].LOAD_REG_I\,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => \LOAD_REG_GEN[28].LOAD_REG_I_0\,
\LOAD_REG_GEN[29].LOAD_REG_I\ => \LOAD_REG_GEN[29].LOAD_REG_I\,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => \LOAD_REG_GEN[29].LOAD_REG_I_0\,
\LOAD_REG_GEN[2].LOAD_REG_I\ => \LOAD_REG_GEN[2].LOAD_REG_I\,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => \LOAD_REG_GEN[2].LOAD_REG_I_0\,
\LOAD_REG_GEN[30].LOAD_REG_I\ => \LOAD_REG_GEN[30].LOAD_REG_I\,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => \LOAD_REG_GEN[30].LOAD_REG_I_0\,
\LOAD_REG_GEN[31].LOAD_REG_I\ => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => \LOAD_REG_GEN[31].LOAD_REG_I\,
\LOAD_REG_GEN[31].LOAD_REG_I_1\ => \LOAD_REG_GEN[31].LOAD_REG_I_0\,
\LOAD_REG_GEN[3].LOAD_REG_I\ => \LOAD_REG_GEN[3].LOAD_REG_I\,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => \LOAD_REG_GEN[3].LOAD_REG_I_0\,
\LOAD_REG_GEN[4].LOAD_REG_I\ => \LOAD_REG_GEN[4].LOAD_REG_I\,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => \LOAD_REG_GEN[4].LOAD_REG_I_0\,
\LOAD_REG_GEN[5].LOAD_REG_I\ => \LOAD_REG_GEN[5].LOAD_REG_I\,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => \LOAD_REG_GEN[5].LOAD_REG_I_0\,
\LOAD_REG_GEN[6].LOAD_REG_I\ => \LOAD_REG_GEN[6].LOAD_REG_I\,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => \LOAD_REG_GEN[6].LOAD_REG_I_0\,
\LOAD_REG_GEN[7].LOAD_REG_I\ => \LOAD_REG_GEN[7].LOAD_REG_I\,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => \LOAD_REG_GEN[7].LOAD_REG_I_0\,
\LOAD_REG_GEN[8].LOAD_REG_I\ => \LOAD_REG_GEN[8].LOAD_REG_I\,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => \LOAD_REG_GEN[8].LOAD_REG_I_0\,
\LOAD_REG_GEN[9].LOAD_REG_I\ => \LOAD_REG_GEN[9].LOAD_REG_I\,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => \LOAD_REG_GEN[9].LOAD_REG_I_0\,
READ_DONE0_I => READ_DONE0_I,
READ_DONE1_I => READ_DONE1_I,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => Bus_RNW_reg,
\TCSR0_GENERATE[23].TCSR0_FF_I_0\ => \TCSR0_GENERATE[23].TCSR0_FF_I\,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => \TCSR0_GENERATE[24].TCSR0_FF_I\,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => \TCSR1_GENERATE[23].TCSR1_FF_I\,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => \TCSR1_GENERATE[24].TCSR1_FF_I\,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1 downto 0) => bus2ip_wrce(1 downto 0),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(0),
pair0_Select => pair0_Select,
read_Mux_In(87 downto 0) => read_Mux_In(87 downto 0),
read_done1 => read_done1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rdata_i_reg[0]_0\ => \s_axi_rdata_i_reg[0]\,
\s_axi_rdata_i_reg[0]_1\ => \s_axi_rdata_i_reg[0]_0\,
\s_axi_rdata_i_reg[10]_0\ => \s_axi_rdata_i_reg[10]\,
\s_axi_rdata_i_reg[11]_0\ => \s_axi_rdata_i_reg[11]\,
\s_axi_rdata_i_reg[12]_0\ => \s_axi_rdata_i_reg[12]\,
\s_axi_rdata_i_reg[13]_0\ => \s_axi_rdata_i_reg[13]\,
\s_axi_rdata_i_reg[14]_0\ => \s_axi_rdata_i_reg[14]\,
\s_axi_rdata_i_reg[15]_0\ => \s_axi_rdata_i_reg[15]\,
\s_axi_rdata_i_reg[16]_0\ => \s_axi_rdata_i_reg[16]\,
\s_axi_rdata_i_reg[17]_0\ => \s_axi_rdata_i_reg[17]\,
\s_axi_rdata_i_reg[18]_0\ => \s_axi_rdata_i_reg[18]\,
\s_axi_rdata_i_reg[19]_0\ => \s_axi_rdata_i_reg[19]\,
\s_axi_rdata_i_reg[20]_0\ => \s_axi_rdata_i_reg[20]\,
\s_axi_rdata_i_reg[21]_0\ => \s_axi_rdata_i_reg[21]\,
\s_axi_rdata_i_reg[22]_0\ => \s_axi_rdata_i_reg[22]\,
\s_axi_rdata_i_reg[23]_0\ => \s_axi_rdata_i_reg[23]\,
\s_axi_rdata_i_reg[24]_0\ => \s_axi_rdata_i_reg[24]\,
\s_axi_rdata_i_reg[25]_0\ => \s_axi_rdata_i_reg[25]\,
\s_axi_rdata_i_reg[26]_0\ => \s_axi_rdata_i_reg[26]\,
\s_axi_rdata_i_reg[27]_0\ => \s_axi_rdata_i_reg[27]\,
\s_axi_rdata_i_reg[28]_0\ => \s_axi_rdata_i_reg[28]\,
\s_axi_rdata_i_reg[29]_0\ => \s_axi_rdata_i_reg[29]\,
\s_axi_rdata_i_reg[30]_0\ => \s_axi_rdata_i_reg[30]\,
\s_axi_rdata_i_reg[31]_0\ => \s_axi_rdata_i_reg[31]\,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_rvalid_i_reg_0 => s_axi_rvalid_i_reg,
s_axi_rvalid_i_reg_1 => s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_2 => s_axi_rvalid_i_reg_1,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0_axi_timer is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
attribute C_COUNT_WIDTH : integer;
attribute C_COUNT_WIDTH of zqynq_lab_1_design_axi_timer_0_0_axi_timer : entity is 32;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_axi_timer_0_0_axi_timer : entity is "zynq";
attribute C_GEN0_ASSERT : string;
attribute C_GEN0_ASSERT of zqynq_lab_1_design_axi_timer_0_0_axi_timer : entity is "1'b1";
attribute C_GEN1_ASSERT : string;
attribute C_GEN1_ASSERT of zqynq_lab_1_design_axi_timer_0_0_axi_timer : entity is "1'b1";
attribute C_ONE_TIMER_ONLY : integer;
attribute C_ONE_TIMER_ONLY of zqynq_lab_1_design_axi_timer_0_0_axi_timer : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of zqynq_lab_1_design_axi_timer_0_0_axi_timer : entity is 5;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of zqynq_lab_1_design_axi_timer_0_0_axi_timer : entity is 32;
attribute C_TRIG0_ASSERT : string;
attribute C_TRIG0_ASSERT of zqynq_lab_1_design_axi_timer_0_0_axi_timer : entity is "1'b1";
attribute C_TRIG1_ASSERT : string;
attribute C_TRIG1_ASSERT of zqynq_lab_1_design_axi_timer_0_0_axi_timer : entity is "1'b1";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_axi_timer_0_0_axi_timer : entity is "axi_timer";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_timer_0_0_axi_timer : entity is "yes";
end zqynq_lab_1_design_axi_timer_0_0_axi_timer;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0_axi_timer is
signal \<const0>\ : STD_LOGIC;
signal AXI4_LITE_I_n_10 : STD_LOGIC;
signal AXI4_LITE_I_n_100 : STD_LOGIC;
signal AXI4_LITE_I_n_101 : STD_LOGIC;
signal AXI4_LITE_I_n_102 : STD_LOGIC;
signal AXI4_LITE_I_n_103 : STD_LOGIC;
signal AXI4_LITE_I_n_104 : STD_LOGIC;
signal AXI4_LITE_I_n_105 : STD_LOGIC;
signal AXI4_LITE_I_n_106 : STD_LOGIC;
signal AXI4_LITE_I_n_11 : STD_LOGIC;
signal AXI4_LITE_I_n_12 : STD_LOGIC;
signal AXI4_LITE_I_n_13 : STD_LOGIC;
signal AXI4_LITE_I_n_14 : STD_LOGIC;
signal AXI4_LITE_I_n_15 : STD_LOGIC;
signal AXI4_LITE_I_n_16 : STD_LOGIC;
signal AXI4_LITE_I_n_17 : STD_LOGIC;
signal AXI4_LITE_I_n_18 : STD_LOGIC;
signal AXI4_LITE_I_n_19 : STD_LOGIC;
signal AXI4_LITE_I_n_20 : STD_LOGIC;
signal AXI4_LITE_I_n_21 : STD_LOGIC;
signal AXI4_LITE_I_n_22 : STD_LOGIC;
signal AXI4_LITE_I_n_23 : STD_LOGIC;
signal AXI4_LITE_I_n_27 : STD_LOGIC;
signal AXI4_LITE_I_n_28 : STD_LOGIC;
signal AXI4_LITE_I_n_29 : STD_LOGIC;
signal AXI4_LITE_I_n_30 : STD_LOGIC;
signal AXI4_LITE_I_n_31 : STD_LOGIC;
signal AXI4_LITE_I_n_32 : STD_LOGIC;
signal AXI4_LITE_I_n_33 : STD_LOGIC;
signal AXI4_LITE_I_n_34 : STD_LOGIC;
signal AXI4_LITE_I_n_35 : STD_LOGIC;
signal AXI4_LITE_I_n_36 : STD_LOGIC;
signal AXI4_LITE_I_n_37 : STD_LOGIC;
signal AXI4_LITE_I_n_38 : STD_LOGIC;
signal AXI4_LITE_I_n_39 : STD_LOGIC;
signal AXI4_LITE_I_n_4 : STD_LOGIC;
signal AXI4_LITE_I_n_40 : STD_LOGIC;
signal AXI4_LITE_I_n_41 : STD_LOGIC;
signal AXI4_LITE_I_n_42 : STD_LOGIC;
signal AXI4_LITE_I_n_43 : STD_LOGIC;
signal AXI4_LITE_I_n_44 : STD_LOGIC;
signal AXI4_LITE_I_n_45 : STD_LOGIC;
signal AXI4_LITE_I_n_46 : STD_LOGIC;
signal AXI4_LITE_I_n_47 : STD_LOGIC;
signal AXI4_LITE_I_n_48 : STD_LOGIC;
signal AXI4_LITE_I_n_49 : STD_LOGIC;
signal AXI4_LITE_I_n_5 : STD_LOGIC;
signal AXI4_LITE_I_n_50 : STD_LOGIC;
signal AXI4_LITE_I_n_51 : STD_LOGIC;
signal AXI4_LITE_I_n_52 : STD_LOGIC;
signal AXI4_LITE_I_n_53 : STD_LOGIC;
signal AXI4_LITE_I_n_54 : STD_LOGIC;
signal AXI4_LITE_I_n_55 : STD_LOGIC;
signal AXI4_LITE_I_n_56 : STD_LOGIC;
signal AXI4_LITE_I_n_57 : STD_LOGIC;
signal AXI4_LITE_I_n_58 : STD_LOGIC;
signal AXI4_LITE_I_n_59 : STD_LOGIC;
signal AXI4_LITE_I_n_6 : STD_LOGIC;
signal AXI4_LITE_I_n_60 : STD_LOGIC;
signal AXI4_LITE_I_n_65 : STD_LOGIC;
signal AXI4_LITE_I_n_66 : STD_LOGIC;
signal AXI4_LITE_I_n_67 : STD_LOGIC;
signal AXI4_LITE_I_n_68 : STD_LOGIC;
signal AXI4_LITE_I_n_69 : STD_LOGIC;
signal AXI4_LITE_I_n_7 : STD_LOGIC;
signal AXI4_LITE_I_n_70 : STD_LOGIC;
signal AXI4_LITE_I_n_71 : STD_LOGIC;
signal AXI4_LITE_I_n_72 : STD_LOGIC;
signal AXI4_LITE_I_n_73 : STD_LOGIC;
signal AXI4_LITE_I_n_74 : STD_LOGIC;
signal AXI4_LITE_I_n_75 : STD_LOGIC;
signal AXI4_LITE_I_n_76 : STD_LOGIC;
signal AXI4_LITE_I_n_77 : STD_LOGIC;
signal AXI4_LITE_I_n_78 : STD_LOGIC;
signal AXI4_LITE_I_n_79 : STD_LOGIC;
signal AXI4_LITE_I_n_8 : STD_LOGIC;
signal AXI4_LITE_I_n_80 : STD_LOGIC;
signal AXI4_LITE_I_n_81 : STD_LOGIC;
signal AXI4_LITE_I_n_82 : STD_LOGIC;
signal AXI4_LITE_I_n_83 : STD_LOGIC;
signal AXI4_LITE_I_n_84 : STD_LOGIC;
signal AXI4_LITE_I_n_85 : STD_LOGIC;
signal AXI4_LITE_I_n_86 : STD_LOGIC;
signal AXI4_LITE_I_n_87 : STD_LOGIC;
signal AXI4_LITE_I_n_88 : STD_LOGIC;
signal AXI4_LITE_I_n_89 : STD_LOGIC;
signal AXI4_LITE_I_n_9 : STD_LOGIC;
signal AXI4_LITE_I_n_90 : STD_LOGIC;
signal AXI4_LITE_I_n_91 : STD_LOGIC;
signal AXI4_LITE_I_n_92 : STD_LOGIC;
signal AXI4_LITE_I_n_93 : STD_LOGIC;
signal AXI4_LITE_I_n_94 : STD_LOGIC;
signal AXI4_LITE_I_n_95 : STD_LOGIC;
signal AXI4_LITE_I_n_97 : STD_LOGIC;
signal AXI4_LITE_I_n_98 : STD_LOGIC;
signal AXI4_LITE_I_n_99 : STD_LOGIC;
signal \COUNTER_0_I/D\ : STD_LOGIC;
signal \GEN_SECOND_TIMER.COUNTER_1_I/D\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\ : STD_LOGIC;
signal \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \TIMER_CONTROL_I/D\ : STD_LOGIC;
signal \TIMER_CONTROL_I/pair0_Select\ : STD_LOGIC;
signal \TIMER_CONTROL_I/read_done1\ : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_wrce : STD_LOGIC_VECTOR ( 0 to 4 );
signal \bus2ip_wrce__0\ : STD_LOGIC_VECTOR ( 5 to 5 );
signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 );
signal read_Mux_In : STD_LOGIC_VECTOR ( 20 to 191 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI4_LITE_I: entity work.zqynq_lab_1_design_axi_timer_0_0_axi_lite_ipif
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
D(31) => ip2bus_data(0),
D(30) => ip2bus_data(1),
D(29) => ip2bus_data(2),
D(28) => ip2bus_data(3),
D(27) => ip2bus_data(4),
D(26) => ip2bus_data(5),
D(25) => ip2bus_data(6),
D(24) => ip2bus_data(7),
D(23) => ip2bus_data(8),
D(22) => ip2bus_data(9),
D(21) => ip2bus_data(10),
D(20) => ip2bus_data(11),
D(19) => ip2bus_data(12),
D(18) => ip2bus_data(13),
D(17) => ip2bus_data(14),
D(16) => ip2bus_data(15),
D(15) => ip2bus_data(16),
D(14) => ip2bus_data(17),
D(13) => ip2bus_data(18),
D(12) => ip2bus_data(19),
D(11) => ip2bus_data(20),
D(10) => ip2bus_data(21),
D(9) => ip2bus_data(22),
D(8) => ip2bus_data(23),
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
D_0 => \GEN_SECOND_TIMER.COUNTER_1_I/D\,
D_1 => \COUNTER_0_I/D\,
D_2 => \TIMER_CONTROL_I/D\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\LOAD_REG_GEN[10].LOAD_REG_I\ => AXI4_LITE_I_n_51,
\LOAD_REG_GEN[10].LOAD_REG_I_0\ => AXI4_LITE_I_n_86,
\LOAD_REG_GEN[11].LOAD_REG_I\ => AXI4_LITE_I_n_50,
\LOAD_REG_GEN[11].LOAD_REG_I_0\ => AXI4_LITE_I_n_85,
\LOAD_REG_GEN[12].LOAD_REG_I\ => AXI4_LITE_I_n_49,
\LOAD_REG_GEN[12].LOAD_REG_I_0\ => AXI4_LITE_I_n_84,
\LOAD_REG_GEN[13].LOAD_REG_I\ => AXI4_LITE_I_n_48,
\LOAD_REG_GEN[13].LOAD_REG_I_0\ => AXI4_LITE_I_n_83,
\LOAD_REG_GEN[14].LOAD_REG_I\ => AXI4_LITE_I_n_47,
\LOAD_REG_GEN[14].LOAD_REG_I_0\ => AXI4_LITE_I_n_82,
\LOAD_REG_GEN[15].LOAD_REG_I\ => AXI4_LITE_I_n_46,
\LOAD_REG_GEN[15].LOAD_REG_I_0\ => AXI4_LITE_I_n_81,
\LOAD_REG_GEN[16].LOAD_REG_I\ => AXI4_LITE_I_n_45,
\LOAD_REG_GEN[16].LOAD_REG_I_0\ => AXI4_LITE_I_n_80,
\LOAD_REG_GEN[17].LOAD_REG_I\ => AXI4_LITE_I_n_44,
\LOAD_REG_GEN[17].LOAD_REG_I_0\ => AXI4_LITE_I_n_79,
\LOAD_REG_GEN[18].LOAD_REG_I\ => AXI4_LITE_I_n_43,
\LOAD_REG_GEN[18].LOAD_REG_I_0\ => AXI4_LITE_I_n_78,
\LOAD_REG_GEN[19].LOAD_REG_I\ => AXI4_LITE_I_n_42,
\LOAD_REG_GEN[19].LOAD_REG_I_0\ => AXI4_LITE_I_n_77,
\LOAD_REG_GEN[1].LOAD_REG_I\ => AXI4_LITE_I_n_60,
\LOAD_REG_GEN[1].LOAD_REG_I_0\ => AXI4_LITE_I_n_95,
\LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_41,
\LOAD_REG_GEN[20].LOAD_REG_I_0\ => AXI4_LITE_I_n_76,
\LOAD_REG_GEN[21].LOAD_REG_I\ => AXI4_LITE_I_n_40,
\LOAD_REG_GEN[21].LOAD_REG_I_0\ => AXI4_LITE_I_n_75,
\LOAD_REG_GEN[22].LOAD_REG_I\ => AXI4_LITE_I_n_39,
\LOAD_REG_GEN[22].LOAD_REG_I_0\ => AXI4_LITE_I_n_74,
\LOAD_REG_GEN[23].LOAD_REG_I\ => AXI4_LITE_I_n_38,
\LOAD_REG_GEN[23].LOAD_REG_I_0\ => AXI4_LITE_I_n_73,
\LOAD_REG_GEN[24].LOAD_REG_I\ => AXI4_LITE_I_n_37,
\LOAD_REG_GEN[24].LOAD_REG_I_0\ => AXI4_LITE_I_n_72,
\LOAD_REG_GEN[25].LOAD_REG_I\ => AXI4_LITE_I_n_36,
\LOAD_REG_GEN[25].LOAD_REG_I_0\ => AXI4_LITE_I_n_71,
\LOAD_REG_GEN[26].LOAD_REG_I\ => AXI4_LITE_I_n_35,
\LOAD_REG_GEN[26].LOAD_REG_I_0\ => AXI4_LITE_I_n_70,
\LOAD_REG_GEN[27].LOAD_REG_I\ => AXI4_LITE_I_n_34,
\LOAD_REG_GEN[27].LOAD_REG_I_0\ => AXI4_LITE_I_n_69,
\LOAD_REG_GEN[28].LOAD_REG_I\ => AXI4_LITE_I_n_33,
\LOAD_REG_GEN[28].LOAD_REG_I_0\ => AXI4_LITE_I_n_68,
\LOAD_REG_GEN[29].LOAD_REG_I\ => AXI4_LITE_I_n_32,
\LOAD_REG_GEN[29].LOAD_REG_I_0\ => AXI4_LITE_I_n_67,
\LOAD_REG_GEN[2].LOAD_REG_I\ => AXI4_LITE_I_n_59,
\LOAD_REG_GEN[2].LOAD_REG_I_0\ => AXI4_LITE_I_n_94,
\LOAD_REG_GEN[30].LOAD_REG_I\ => AXI4_LITE_I_n_31,
\LOAD_REG_GEN[30].LOAD_REG_I_0\ => AXI4_LITE_I_n_66,
\LOAD_REG_GEN[31].LOAD_REG_I\ => AXI4_LITE_I_n_30,
\LOAD_REG_GEN[31].LOAD_REG_I_0\ => AXI4_LITE_I_n_65,
\LOAD_REG_GEN[3].LOAD_REG_I\ => AXI4_LITE_I_n_58,
\LOAD_REG_GEN[3].LOAD_REG_I_0\ => AXI4_LITE_I_n_93,
\LOAD_REG_GEN[4].LOAD_REG_I\ => AXI4_LITE_I_n_57,
\LOAD_REG_GEN[4].LOAD_REG_I_0\ => AXI4_LITE_I_n_92,
\LOAD_REG_GEN[5].LOAD_REG_I\ => AXI4_LITE_I_n_56,
\LOAD_REG_GEN[5].LOAD_REG_I_0\ => AXI4_LITE_I_n_91,
\LOAD_REG_GEN[6].LOAD_REG_I\ => AXI4_LITE_I_n_55,
\LOAD_REG_GEN[6].LOAD_REG_I_0\ => AXI4_LITE_I_n_90,
\LOAD_REG_GEN[7].LOAD_REG_I\ => AXI4_LITE_I_n_54,
\LOAD_REG_GEN[7].LOAD_REG_I_0\ => AXI4_LITE_I_n_89,
\LOAD_REG_GEN[8].LOAD_REG_I\ => AXI4_LITE_I_n_53,
\LOAD_REG_GEN[8].LOAD_REG_I_0\ => AXI4_LITE_I_n_88,
\LOAD_REG_GEN[9].LOAD_REG_I\ => AXI4_LITE_I_n_52,
\LOAD_REG_GEN[9].LOAD_REG_I_0\ => AXI4_LITE_I_n_87,
READ_DONE0_I => AXI4_LITE_I_n_105,
READ_DONE1_I => AXI4_LITE_I_n_106,
\TCSR0_GENERATE[23].TCSR0_FF_I\ => AXI4_LITE_I_n_100,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_28,
\TCSR1_GENERATE[23].TCSR1_FF_I\ => AXI4_LITE_I_n_101,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_29,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1) => bus2ip_wrce(0),
bus2ip_wrce(0) => bus2ip_wrce(4),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(5),
pair0_Select => \TIMER_CONTROL_I/pair0_Select\,
read_Mux_In(87) => read_Mux_In(20),
read_Mux_In(86) => read_Mux_In(24),
read_Mux_In(85) => read_Mux_In(56),
read_Mux_In(84) => read_Mux_In(64),
read_Mux_In(83) => read_Mux_In(65),
read_Mux_In(82) => read_Mux_In(66),
read_Mux_In(81) => read_Mux_In(67),
read_Mux_In(80) => read_Mux_In(68),
read_Mux_In(79) => read_Mux_In(69),
read_Mux_In(78) => read_Mux_In(70),
read_Mux_In(77) => read_Mux_In(71),
read_Mux_In(76) => read_Mux_In(72),
read_Mux_In(75) => read_Mux_In(73),
read_Mux_In(74) => read_Mux_In(74),
read_Mux_In(73) => read_Mux_In(75),
read_Mux_In(72) => read_Mux_In(76),
read_Mux_In(71) => read_Mux_In(77),
read_Mux_In(70) => read_Mux_In(78),
read_Mux_In(69) => read_Mux_In(79),
read_Mux_In(68) => read_Mux_In(80),
read_Mux_In(67) => read_Mux_In(81),
read_Mux_In(66) => read_Mux_In(82),
read_Mux_In(65) => read_Mux_In(83),
read_Mux_In(64) => read_Mux_In(84),
read_Mux_In(63) => read_Mux_In(128),
read_Mux_In(62) => read_Mux_In(129),
read_Mux_In(61) => read_Mux_In(130),
read_Mux_In(60) => read_Mux_In(131),
read_Mux_In(59) => read_Mux_In(132),
read_Mux_In(58) => read_Mux_In(133),
read_Mux_In(57) => read_Mux_In(134),
read_Mux_In(56) => read_Mux_In(135),
read_Mux_In(55) => read_Mux_In(136),
read_Mux_In(54) => read_Mux_In(137),
read_Mux_In(53) => read_Mux_In(138),
read_Mux_In(52) => read_Mux_In(139),
read_Mux_In(51) => read_Mux_In(140),
read_Mux_In(50) => read_Mux_In(141),
read_Mux_In(49) => read_Mux_In(142),
read_Mux_In(48) => read_Mux_In(143),
read_Mux_In(47) => read_Mux_In(144),
read_Mux_In(46) => read_Mux_In(145),
read_Mux_In(45) => read_Mux_In(146),
read_Mux_In(44) => read_Mux_In(147),
read_Mux_In(43) => read_Mux_In(148),
read_Mux_In(42) => read_Mux_In(149),
read_Mux_In(41) => read_Mux_In(150),
read_Mux_In(40) => read_Mux_In(151),
read_Mux_In(39) => read_Mux_In(152),
read_Mux_In(38) => read_Mux_In(153),
read_Mux_In(37) => read_Mux_In(154),
read_Mux_In(36) => read_Mux_In(155),
read_Mux_In(35) => read_Mux_In(156),
read_Mux_In(34) => read_Mux_In(157),
read_Mux_In(33) => read_Mux_In(158),
read_Mux_In(32) => read_Mux_In(159),
read_Mux_In(31) => read_Mux_In(160),
read_Mux_In(30) => read_Mux_In(161),
read_Mux_In(29) => read_Mux_In(162),
read_Mux_In(28) => read_Mux_In(163),
read_Mux_In(27) => read_Mux_In(164),
read_Mux_In(26) => read_Mux_In(165),
read_Mux_In(25) => read_Mux_In(166),
read_Mux_In(24) => read_Mux_In(167),
read_Mux_In(23) => read_Mux_In(168),
read_Mux_In(22) => read_Mux_In(169),
read_Mux_In(21) => read_Mux_In(170),
read_Mux_In(20) => read_Mux_In(171),
read_Mux_In(19) => read_Mux_In(172),
read_Mux_In(18) => read_Mux_In(173),
read_Mux_In(17) => read_Mux_In(174),
read_Mux_In(16) => read_Mux_In(175),
read_Mux_In(15) => read_Mux_In(176),
read_Mux_In(14) => read_Mux_In(177),
read_Mux_In(13) => read_Mux_In(178),
read_Mux_In(12) => read_Mux_In(179),
read_Mux_In(11) => read_Mux_In(180),
read_Mux_In(10) => read_Mux_In(181),
read_Mux_In(9) => read_Mux_In(182),
read_Mux_In(8) => read_Mux_In(183),
read_Mux_In(7) => read_Mux_In(184),
read_Mux_In(6) => read_Mux_In(185),
read_Mux_In(5) => read_Mux_In(186),
read_Mux_In(4) => read_Mux_In(187),
read_Mux_In(3) => read_Mux_In(188),
read_Mux_In(2) => read_Mux_In(189),
read_Mux_In(1) => read_Mux_In(190),
read_Mux_In(0) => read_Mux_In(191),
read_done1 => \TIMER_CONTROL_I/read_done1\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(4 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(4 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rdata_i_reg[0]\ => AXI4_LITE_I_n_103,
\s_axi_rdata_i_reg[0]_0\ => AXI4_LITE_I_n_104,
\s_axi_rdata_i_reg[10]\ => AXI4_LITE_I_n_102,
\s_axi_rdata_i_reg[11]\ => AXI4_LITE_I_n_27,
\s_axi_rdata_i_reg[12]\ => AXI4_LITE_I_n_4,
\s_axi_rdata_i_reg[13]\ => AXI4_LITE_I_n_5,
\s_axi_rdata_i_reg[14]\ => AXI4_LITE_I_n_6,
\s_axi_rdata_i_reg[15]\ => AXI4_LITE_I_n_7,
\s_axi_rdata_i_reg[16]\ => AXI4_LITE_I_n_8,
\s_axi_rdata_i_reg[17]\ => AXI4_LITE_I_n_9,
\s_axi_rdata_i_reg[18]\ => AXI4_LITE_I_n_10,
\s_axi_rdata_i_reg[19]\ => AXI4_LITE_I_n_11,
\s_axi_rdata_i_reg[20]\ => AXI4_LITE_I_n_12,
\s_axi_rdata_i_reg[21]\ => AXI4_LITE_I_n_13,
\s_axi_rdata_i_reg[22]\ => AXI4_LITE_I_n_14,
\s_axi_rdata_i_reg[23]\ => AXI4_LITE_I_n_15,
\s_axi_rdata_i_reg[24]\ => AXI4_LITE_I_n_16,
\s_axi_rdata_i_reg[25]\ => AXI4_LITE_I_n_17,
\s_axi_rdata_i_reg[26]\ => AXI4_LITE_I_n_18,
\s_axi_rdata_i_reg[27]\ => AXI4_LITE_I_n_19,
\s_axi_rdata_i_reg[28]\ => AXI4_LITE_I_n_20,
\s_axi_rdata_i_reg[29]\ => AXI4_LITE_I_n_21,
\s_axi_rdata_i_reg[30]\ => AXI4_LITE_I_n_22,
\s_axi_rdata_i_reg[31]\ => AXI4_LITE_I_n_23,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_rvalid_i_reg => AXI4_LITE_I_n_97,
s_axi_rvalid_i_reg_0 => AXI4_LITE_I_n_98,
s_axi_rvalid_i_reg_1 => AXI4_LITE_I_n_99,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
TC_CORE_I: entity work.zqynq_lab_1_design_axi_timer_0_0_tc_core
port map (
Bus_RNW_reg => \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg\,
Bus_RNW_reg_reg => AXI4_LITE_I_n_23,
Bus_RNW_reg_reg_0 => AXI4_LITE_I_n_22,
Bus_RNW_reg_reg_1 => AXI4_LITE_I_n_21,
Bus_RNW_reg_reg_10 => AXI4_LITE_I_n_12,
Bus_RNW_reg_reg_11 => AXI4_LITE_I_n_11,
Bus_RNW_reg_reg_12 => AXI4_LITE_I_n_10,
Bus_RNW_reg_reg_13 => AXI4_LITE_I_n_9,
Bus_RNW_reg_reg_14 => AXI4_LITE_I_n_8,
Bus_RNW_reg_reg_15 => AXI4_LITE_I_n_7,
Bus_RNW_reg_reg_16 => AXI4_LITE_I_n_6,
Bus_RNW_reg_reg_17 => AXI4_LITE_I_n_5,
Bus_RNW_reg_reg_18 => AXI4_LITE_I_n_4,
Bus_RNW_reg_reg_2 => AXI4_LITE_I_n_20,
Bus_RNW_reg_reg_3 => AXI4_LITE_I_n_19,
Bus_RNW_reg_reg_4 => AXI4_LITE_I_n_18,
Bus_RNW_reg_reg_5 => AXI4_LITE_I_n_17,
Bus_RNW_reg_reg_6 => AXI4_LITE_I_n_16,
Bus_RNW_reg_reg_7 => AXI4_LITE_I_n_15,
Bus_RNW_reg_reg_8 => AXI4_LITE_I_n_14,
Bus_RNW_reg_reg_9 => AXI4_LITE_I_n_13,
D(31) => ip2bus_data(0),
D(30) => ip2bus_data(1),
D(29) => ip2bus_data(2),
D(28) => ip2bus_data(3),
D(27) => ip2bus_data(4),
D(26) => ip2bus_data(5),
D(25) => ip2bus_data(6),
D(24) => ip2bus_data(7),
D(23) => ip2bus_data(8),
D(22) => ip2bus_data(9),
D(21) => ip2bus_data(10),
D(20) => ip2bus_data(11),
D(19) => ip2bus_data(12),
D(18) => ip2bus_data(13),
D(17) => ip2bus_data(14),
D(16) => ip2bus_data(15),
D(15) => ip2bus_data(16),
D(14) => ip2bus_data(17),
D(13) => ip2bus_data(18),
D(12) => ip2bus_data(19),
D(11) => ip2bus_data(20),
D(10) => ip2bus_data(21),
D(9) => ip2bus_data(22),
D(8) => ip2bus_data(23),
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
D_0 => \TIMER_CONTROL_I/D\,
D_1 => \COUNTER_0_I/D\,
D_2 => \GEN_SECOND_TIMER.COUNTER_1_I/D\,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\ => AXI4_LITE_I_n_100,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0\ => AXI4_LITE_I_n_102,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ => \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\ => AXI4_LITE_I_n_95,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0\ => AXI4_LITE_I_n_94,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1\ => AXI4_LITE_I_n_93,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10\ => AXI4_LITE_I_n_84,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11\ => AXI4_LITE_I_n_83,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12\ => AXI4_LITE_I_n_82,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13\ => AXI4_LITE_I_n_81,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14\ => AXI4_LITE_I_n_80,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15\ => AXI4_LITE_I_n_79,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16\ => AXI4_LITE_I_n_78,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17\ => AXI4_LITE_I_n_77,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18\ => AXI4_LITE_I_n_76,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19\ => AXI4_LITE_I_n_75,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2\ => AXI4_LITE_I_n_92,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20\ => AXI4_LITE_I_n_74,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21\ => AXI4_LITE_I_n_73,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22\ => AXI4_LITE_I_n_72,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23\ => AXI4_LITE_I_n_71,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24\ => AXI4_LITE_I_n_70,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25\ => AXI4_LITE_I_n_69,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26\ => AXI4_LITE_I_n_68,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27\ => AXI4_LITE_I_n_67,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28\ => AXI4_LITE_I_n_66,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29\ => AXI4_LITE_I_n_65,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3\ => AXI4_LITE_I_n_91,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30\ => AXI4_LITE_I_n_105,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31\ => AXI4_LITE_I_n_97,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4\ => AXI4_LITE_I_n_90,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5\ => AXI4_LITE_I_n_89,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6\ => AXI4_LITE_I_n_88,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7\ => AXI4_LITE_I_n_87,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8\ => AXI4_LITE_I_n_86,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9\ => AXI4_LITE_I_n_85,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\ => AXI4_LITE_I_n_99,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]\ => AXI4_LITE_I_n_101,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0\ => AXI4_LITE_I_n_98,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]\ => AXI4_LITE_I_n_106,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0\ => AXI4_LITE_I_n_103,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]\ => AXI4_LITE_I_n_104,
\INFERRED_GEN.icount_out_reg[0]\(87) => read_Mux_In(20),
\INFERRED_GEN.icount_out_reg[0]\(86) => read_Mux_In(24),
\INFERRED_GEN.icount_out_reg[0]\(85) => read_Mux_In(56),
\INFERRED_GEN.icount_out_reg[0]\(84) => read_Mux_In(64),
\INFERRED_GEN.icount_out_reg[0]\(83) => read_Mux_In(65),
\INFERRED_GEN.icount_out_reg[0]\(82) => read_Mux_In(66),
\INFERRED_GEN.icount_out_reg[0]\(81) => read_Mux_In(67),
\INFERRED_GEN.icount_out_reg[0]\(80) => read_Mux_In(68),
\INFERRED_GEN.icount_out_reg[0]\(79) => read_Mux_In(69),
\INFERRED_GEN.icount_out_reg[0]\(78) => read_Mux_In(70),
\INFERRED_GEN.icount_out_reg[0]\(77) => read_Mux_In(71),
\INFERRED_GEN.icount_out_reg[0]\(76) => read_Mux_In(72),
\INFERRED_GEN.icount_out_reg[0]\(75) => read_Mux_In(73),
\INFERRED_GEN.icount_out_reg[0]\(74) => read_Mux_In(74),
\INFERRED_GEN.icount_out_reg[0]\(73) => read_Mux_In(75),
\INFERRED_GEN.icount_out_reg[0]\(72) => read_Mux_In(76),
\INFERRED_GEN.icount_out_reg[0]\(71) => read_Mux_In(77),
\INFERRED_GEN.icount_out_reg[0]\(70) => read_Mux_In(78),
\INFERRED_GEN.icount_out_reg[0]\(69) => read_Mux_In(79),
\INFERRED_GEN.icount_out_reg[0]\(68) => read_Mux_In(80),
\INFERRED_GEN.icount_out_reg[0]\(67) => read_Mux_In(81),
\INFERRED_GEN.icount_out_reg[0]\(66) => read_Mux_In(82),
\INFERRED_GEN.icount_out_reg[0]\(65) => read_Mux_In(83),
\INFERRED_GEN.icount_out_reg[0]\(64) => read_Mux_In(84),
\INFERRED_GEN.icount_out_reg[0]\(63) => read_Mux_In(128),
\INFERRED_GEN.icount_out_reg[0]\(62) => read_Mux_In(129),
\INFERRED_GEN.icount_out_reg[0]\(61) => read_Mux_In(130),
\INFERRED_GEN.icount_out_reg[0]\(60) => read_Mux_In(131),
\INFERRED_GEN.icount_out_reg[0]\(59) => read_Mux_In(132),
\INFERRED_GEN.icount_out_reg[0]\(58) => read_Mux_In(133),
\INFERRED_GEN.icount_out_reg[0]\(57) => read_Mux_In(134),
\INFERRED_GEN.icount_out_reg[0]\(56) => read_Mux_In(135),
\INFERRED_GEN.icount_out_reg[0]\(55) => read_Mux_In(136),
\INFERRED_GEN.icount_out_reg[0]\(54) => read_Mux_In(137),
\INFERRED_GEN.icount_out_reg[0]\(53) => read_Mux_In(138),
\INFERRED_GEN.icount_out_reg[0]\(52) => read_Mux_In(139),
\INFERRED_GEN.icount_out_reg[0]\(51) => read_Mux_In(140),
\INFERRED_GEN.icount_out_reg[0]\(50) => read_Mux_In(141),
\INFERRED_GEN.icount_out_reg[0]\(49) => read_Mux_In(142),
\INFERRED_GEN.icount_out_reg[0]\(48) => read_Mux_In(143),
\INFERRED_GEN.icount_out_reg[0]\(47) => read_Mux_In(144),
\INFERRED_GEN.icount_out_reg[0]\(46) => read_Mux_In(145),
\INFERRED_GEN.icount_out_reg[0]\(45) => read_Mux_In(146),
\INFERRED_GEN.icount_out_reg[0]\(44) => read_Mux_In(147),
\INFERRED_GEN.icount_out_reg[0]\(43) => read_Mux_In(148),
\INFERRED_GEN.icount_out_reg[0]\(42) => read_Mux_In(149),
\INFERRED_GEN.icount_out_reg[0]\(41) => read_Mux_In(150),
\INFERRED_GEN.icount_out_reg[0]\(40) => read_Mux_In(151),
\INFERRED_GEN.icount_out_reg[0]\(39) => read_Mux_In(152),
\INFERRED_GEN.icount_out_reg[0]\(38) => read_Mux_In(153),
\INFERRED_GEN.icount_out_reg[0]\(37) => read_Mux_In(154),
\INFERRED_GEN.icount_out_reg[0]\(36) => read_Mux_In(155),
\INFERRED_GEN.icount_out_reg[0]\(35) => read_Mux_In(156),
\INFERRED_GEN.icount_out_reg[0]\(34) => read_Mux_In(157),
\INFERRED_GEN.icount_out_reg[0]\(33) => read_Mux_In(158),
\INFERRED_GEN.icount_out_reg[0]\(32) => read_Mux_In(159),
\INFERRED_GEN.icount_out_reg[0]\(31) => read_Mux_In(160),
\INFERRED_GEN.icount_out_reg[0]\(30) => read_Mux_In(161),
\INFERRED_GEN.icount_out_reg[0]\(29) => read_Mux_In(162),
\INFERRED_GEN.icount_out_reg[0]\(28) => read_Mux_In(163),
\INFERRED_GEN.icount_out_reg[0]\(27) => read_Mux_In(164),
\INFERRED_GEN.icount_out_reg[0]\(26) => read_Mux_In(165),
\INFERRED_GEN.icount_out_reg[0]\(25) => read_Mux_In(166),
\INFERRED_GEN.icount_out_reg[0]\(24) => read_Mux_In(167),
\INFERRED_GEN.icount_out_reg[0]\(23) => read_Mux_In(168),
\INFERRED_GEN.icount_out_reg[0]\(22) => read_Mux_In(169),
\INFERRED_GEN.icount_out_reg[0]\(21) => read_Mux_In(170),
\INFERRED_GEN.icount_out_reg[0]\(20) => read_Mux_In(171),
\INFERRED_GEN.icount_out_reg[0]\(19) => read_Mux_In(172),
\INFERRED_GEN.icount_out_reg[0]\(18) => read_Mux_In(173),
\INFERRED_GEN.icount_out_reg[0]\(17) => read_Mux_In(174),
\INFERRED_GEN.icount_out_reg[0]\(16) => read_Mux_In(175),
\INFERRED_GEN.icount_out_reg[0]\(15) => read_Mux_In(176),
\INFERRED_GEN.icount_out_reg[0]\(14) => read_Mux_In(177),
\INFERRED_GEN.icount_out_reg[0]\(13) => read_Mux_In(178),
\INFERRED_GEN.icount_out_reg[0]\(12) => read_Mux_In(179),
\INFERRED_GEN.icount_out_reg[0]\(11) => read_Mux_In(180),
\INFERRED_GEN.icount_out_reg[0]\(10) => read_Mux_In(181),
\INFERRED_GEN.icount_out_reg[0]\(9) => read_Mux_In(182),
\INFERRED_GEN.icount_out_reg[0]\(8) => read_Mux_In(183),
\INFERRED_GEN.icount_out_reg[0]\(7) => read_Mux_In(184),
\INFERRED_GEN.icount_out_reg[0]\(6) => read_Mux_In(185),
\INFERRED_GEN.icount_out_reg[0]\(5) => read_Mux_In(186),
\INFERRED_GEN.icount_out_reg[0]\(4) => read_Mux_In(187),
\INFERRED_GEN.icount_out_reg[0]\(3) => read_Mux_In(188),
\INFERRED_GEN.icount_out_reg[0]\(2) => read_Mux_In(189),
\INFERRED_GEN.icount_out_reg[0]\(1) => read_Mux_In(190),
\INFERRED_GEN.icount_out_reg[0]\(0) => read_Mux_In(191),
\INFERRED_GEN.icount_out_reg[0]_0\ => AXI4_LITE_I_n_30,
\INFERRED_GEN.icount_out_reg[10]\ => AXI4_LITE_I_n_40,
\INFERRED_GEN.icount_out_reg[11]\ => AXI4_LITE_I_n_41,
\INFERRED_GEN.icount_out_reg[12]\ => AXI4_LITE_I_n_42,
\INFERRED_GEN.icount_out_reg[13]\ => AXI4_LITE_I_n_43,
\INFERRED_GEN.icount_out_reg[14]\ => AXI4_LITE_I_n_44,
\INFERRED_GEN.icount_out_reg[15]\ => AXI4_LITE_I_n_45,
\INFERRED_GEN.icount_out_reg[16]\ => AXI4_LITE_I_n_46,
\INFERRED_GEN.icount_out_reg[17]\ => AXI4_LITE_I_n_47,
\INFERRED_GEN.icount_out_reg[18]\ => AXI4_LITE_I_n_48,
\INFERRED_GEN.icount_out_reg[19]\ => AXI4_LITE_I_n_49,
\INFERRED_GEN.icount_out_reg[1]\ => AXI4_LITE_I_n_31,
\INFERRED_GEN.icount_out_reg[20]\ => AXI4_LITE_I_n_50,
\INFERRED_GEN.icount_out_reg[21]\ => AXI4_LITE_I_n_51,
\INFERRED_GEN.icount_out_reg[22]\ => AXI4_LITE_I_n_52,
\INFERRED_GEN.icount_out_reg[23]\ => AXI4_LITE_I_n_53,
\INFERRED_GEN.icount_out_reg[24]\ => AXI4_LITE_I_n_54,
\INFERRED_GEN.icount_out_reg[25]\ => AXI4_LITE_I_n_55,
\INFERRED_GEN.icount_out_reg[26]\ => AXI4_LITE_I_n_56,
\INFERRED_GEN.icount_out_reg[27]\ => AXI4_LITE_I_n_57,
\INFERRED_GEN.icount_out_reg[28]\ => AXI4_LITE_I_n_58,
\INFERRED_GEN.icount_out_reg[29]\ => AXI4_LITE_I_n_59,
\INFERRED_GEN.icount_out_reg[2]\ => AXI4_LITE_I_n_32,
\INFERRED_GEN.icount_out_reg[30]\ => AXI4_LITE_I_n_60,
\INFERRED_GEN.icount_out_reg[3]\ => AXI4_LITE_I_n_33,
\INFERRED_GEN.icount_out_reg[4]\ => AXI4_LITE_I_n_34,
\INFERRED_GEN.icount_out_reg[5]\ => AXI4_LITE_I_n_35,
\INFERRED_GEN.icount_out_reg[6]\ => AXI4_LITE_I_n_36,
\INFERRED_GEN.icount_out_reg[7]\ => AXI4_LITE_I_n_37,
\INFERRED_GEN.icount_out_reg[8]\ => AXI4_LITE_I_n_38,
\INFERRED_GEN.icount_out_reg[9]\ => AXI4_LITE_I_n_39,
\LOAD_REG_GEN[20].LOAD_REG_I\ => AXI4_LITE_I_n_27,
\TCSR0_GENERATE[24].TCSR0_FF_I\ => AXI4_LITE_I_n_28,
\TCSR1_GENERATE[24].TCSR1_FF_I\ => AXI4_LITE_I_n_29,
bus2ip_reset => bus2ip_reset,
bus2ip_wrce(1) => bus2ip_wrce(0),
bus2ip_wrce(0) => bus2ip_wrce(4),
\bus2ip_wrce__0\(0) => \bus2ip_wrce__0\(5),
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
pair0_Select => \TIMER_CONTROL_I/pair0_Select\,
pwm0 => pwm0,
read_done1 => \TIMER_CONTROL_I/read_done1\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_wdata(9 downto 7) => s_axi_wdata(11 downto 9),
s_axi_wdata(6 downto 0) => s_axi_wdata(6 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_timer_0_0 is
port (
capturetrig0 : in STD_LOGIC;
capturetrig1 : in STD_LOGIC;
generateout0 : out STD_LOGIC;
generateout1 : out STD_LOGIC;
pwm0 : out STD_LOGIC;
interrupt : out STD_LOGIC;
freeze : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_axi_timer_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_axi_timer_0_0 : entity is "zqynq_lab_1_design_axi_timer_0_0,axi_timer,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_timer_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zqynq_lab_1_design_axi_timer_0_0 : entity is "axi_timer,Vivado 2017.2";
end zqynq_lab_1_design_axi_timer_0_0;
architecture STRUCTURE of zqynq_lab_1_design_axi_timer_0_0 is
attribute C_COUNT_WIDTH : integer;
attribute C_COUNT_WIDTH of U0 : label is 32;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GEN0_ASSERT : string;
attribute C_GEN0_ASSERT of U0 : label is "1'b1";
attribute C_GEN1_ASSERT : string;
attribute C_GEN1_ASSERT of U0 : label is "1'b1";
attribute C_ONE_TIMER_ONLY : integer;
attribute C_ONE_TIMER_ONLY of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 5;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRIG0_ASSERT : string;
attribute C_TRIG0_ASSERT of U0 : label is "1'b1";
attribute C_TRIG1_ASSERT : string;
attribute C_TRIG1_ASSERT of U0 : label is "1'b1";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.zqynq_lab_1_design_axi_timer_0_0_axi_timer
port map (
capturetrig0 => capturetrig0,
capturetrig1 => capturetrig1,
freeze => freeze,
generateout0 => generateout0,
generateout1 => generateout1,
interrupt => interrupt,
pwm0 => pwm0,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(4 downto 0) => s_axi_araddr(4 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(4 downto 0) => s_axi_awaddr(4 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 4f09a5d55d426ef03cce3fd2fefcd913 | 0.576385 | 2.531611 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/e7bb0a4eba6cd7b1/zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl | 1 | 291,100 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Sat Sep 23 13:25:26 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
port (
bvalid_cnt_inc : out STD_LOGIC;
bid_gets_fifo_load_d1_reg : out STD_LOGIC;
bid_gets_fifo_load : out STD_LOGIC;
axi_wdata_full_cmb114_out : out STD_LOGIC;
\axi_bid_int_reg[0]\ : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
\bvalid_cnt_reg[2]\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
bram_addr_ld_en : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
axi_bvalid_int_reg : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
\bvalid_cnt_reg[1]\ : in STD_LOGIC;
aw_active : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
axi_awid_pipe : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
axi_wr_burst : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[0]_i_2_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_5_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_6_n_0 : STD_LOGIC;
signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC;
signal bid_fifo_ld : STD_LOGIC;
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC;
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC;
signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC;
signal \^bvalid_cnt_inc\ : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair44";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair44";
begin
axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\;
bvalid_cnt_inc <= \^bvalid_cnt_inc\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => s_axi_aresetn
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => \axi_bid_int[0]_i_2_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => s_axi_aresetn
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => s_axi_aresetn
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => s_axi_aresetn
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[0]_i_2_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D,
Q => bid_fifo_not_empty,
R => s_axi_aresetn
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE0A"
)
port map (
I0 => bram_addr_ld_en,
I1 => Data_Exists_DFF_i_2_n_0,
I2 => Data_Exists_DFF_i_3_n_0,
I3 => bid_fifo_not_empty,
O => D
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFD"
)
port map (
I0 => \^bvalid_cnt_inc\,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
I3 => bvalid_cnt(1),
I4 => \^bid_gets_fifo_load_d1_reg\,
I5 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld,
Q => bid_fifo_rd
);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_awid_pipe,
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
O => bid_fifo_ld
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ACAFACA0"
)
port map (
I0 => bid_fifo_ld,
I1 => bid_fifo_rd,
I2 => \^bid_gets_fifo_load\,
I3 => \axi_bid_int[0]_i_2_n_0\,
I4 => s_axi_bid(0),
O => \axi_bid_int_reg[0]\
);
\axi_bid_int[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888AAAAA8888888"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => s_axi_bready,
I3 => axi_bvalid_int_reg,
I4 => bid_gets_fifo_load_d1_i_3_n_0,
I5 => \^bvalid_cnt_inc\,
O => \axi_bid_int[0]_i_2_n_0\
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000055FD00000000"
)
port map (
I0 => \out\(2),
I1 => \^axi_wdata_full_cmb114_out\,
I2 => axi_bvalid_int_i_4_n_0,
I3 => axi_wr_burst,
I4 => \out\(1),
I5 => axi_bvalid_int_i_5_n_0,
O => \^bvalid_cnt_inc\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FE000000"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => axi_bvalid_int_reg,
I4 => s_axi_bready,
O => \^bid_gets_fifo_load_d1_reg\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"1F11000000000000"
)
port map (
I0 => axi_bvalid_int_i_6_n_0,
I1 => \bvalid_cnt_reg[2]\,
I2 => wr_addr_sm_cs,
I3 => \bvalid_cnt_reg[2]_0\,
I4 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I5 => axi_awaddr_full,
O => axi_bvalid_int_i_4_n_0
);
axi_bvalid_int_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"74446444"
)
port map (
I0 => \out\(0),
I1 => \out\(2),
I2 => s_axi_wvalid,
I3 => s_axi_wlast,
I4 => \^axi_wdata_full_cmb114_out\,
O => axi_bvalid_int_i_5_n_0
);
axi_bvalid_int_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => curr_awlen_reg_1_or_2,
I1 => axi_awlen_pipe_1_or_2,
I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I3 => axi_awaddr_full,
I4 => last_data_ack_mod,
O => axi_bvalid_int_i_6_n_0
);
axi_wready_int_mod_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F007F007F00"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => aw_active,
I4 => s_axi_awready,
I5 => s_axi_awvalid,
O => \^axi_wdata_full_cmb114_out\
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800AA00AA00"
)
port map (
I0 => bram_addr_ld_en,
I1 => \^bid_gets_fifo_load_d1_reg\,
I2 => bid_fifo_not_empty,
I3 => \^bvalid_cnt_inc\,
I4 => \bvalid_cnt_reg[1]\,
I5 => bid_gets_fifo_load_d1_i_3_n_0,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => bid_gets_fifo_load_d1_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_addr_ld_en_mod : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC;
bram_addr_ld_en : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[2]_0\ : out STD_LOGIC;
curr_fixed_burst_reg_reg : out STD_LOGIC;
curr_wrap_burst_reg_reg : out STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
bram_addr_inc : in STD_LOGIC;
bram_addr_rst_cmb : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
aw_active : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
curr_fixed_burst : in STD_LOGIC;
curr_wrap_burst : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^bram_addr_ld_en_mod\ : STD_LOGIC;
signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 15 downto 3 );
signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_2\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_5_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[2]_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \curr_fixed_burst_reg_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3__0\ : label is "soft_lutpair47";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\;
SR(0) <= \^sr\(0);
bram_addr_ld_en <= \^bram_addr_ld_en\;
bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\;
\save_init_bram_addr_ld_reg[15]_2\ <= \^save_init_bram_addr_ld_reg[15]_2\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[2]_0\ <= \^wrap_burst_total_reg[2]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB8BBBBB88B88888"
)
port map (
I0 => bram_addr_ld(8),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(7),
I5 => bram_addr_a(8),
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(9),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(9),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\,
I4 => bram_addr_a(8),
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(12),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(13),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(14),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4500FFFF"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => bram_addr_inc,
I3 => bram_addr_rst_cmb,
I4 => s_axi_aresetn,
O => \^sr\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => \^bram_addr_ld_en_mod\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(15),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFFDF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => wrap_burst_total(1),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(0),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => bram_addr_a(2),
I1 => bram_addr_a(1),
I2 => wrap_burst_total(1),
I3 => bram_addr_a(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B800FFFF"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
I1 => axi_awaddr_full,
I2 => s_axi_awaddr(0),
I3 => \^bram_addr_ld_en\,
I4 => \^bram_addr_ld_en_mod\,
I5 => bram_addr_a(0),
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => bram_addr_ld(1),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(1),
I3 => bram_addr_a(0),
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BB8B8B8"
)
port map (
I0 => bram_addr_ld(2),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(2),
I3 => bram_addr_a(0),
I4 => bram_addr_a(1),
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BB8B8B8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(3),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(3),
I3 => bram_addr_a(2),
I4 => bram_addr_a(0),
I5 => bram_addr_a(1),
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => bram_addr_ld(4),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(5),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(5),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I4 => bram_addr_a(4),
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B88BB8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(6),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => bram_addr_a(4),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => bram_addr_a(5),
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => bram_addr_a(1),
I1 => bram_addr_a(0),
I2 => bram_addr_a(2),
I3 => bram_addr_a(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(7),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(6),
O => \^d\(7)
);
\curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_fixed_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_fixed_burst,
I3 => \^sr\(0),
O => curr_fixed_burst_reg_reg
);
\curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_wrap_burst,
I3 => \^sr\(0),
O => curr_wrap_burst_reg_reg
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(10),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(8),
O => bram_addr_ld(8)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(11),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(9),
O => bram_addr_ld(9)
);
\save_init_bram_addr_ld[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080808AA0808"
)
port map (
I0 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I1 => \^save_init_bram_addr_ld_reg[15]_0\,
I2 => wr_addr_sm_cs,
I3 => \^save_init_bram_addr_ld_reg[15]_1\,
I4 => last_data_ack_mod,
I5 => \^save_init_bram_addr_ld_reg[15]_2\,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"007F007F007F0000"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
I3 => aw_active,
I4 => axi_awaddr_full,
I5 => s_axi_awvalid,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[15]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => \^save_init_bram_addr_ld_reg[15]_1\
);
\save_init_bram_addr_ld[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I2 => axi_awlen_pipe_1_or_2,
I3 => curr_awlen_reg_1_or_2,
O => \^save_init_bram_addr_ld_reg[15]_2\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(1),
O => bram_addr_ld(1)
);
\save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => save_init_bram_addr_ld(3),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2__0_n_0\
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(2),
O => bram_addr_ld(2)
);
\save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => save_init_bram_addr_ld(4),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2__0_n_0\
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808F8F8F808080"
)
port map (
I0 => save_init_bram_addr_ld(5),
I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
I4 => axi_awaddr_full,
I5 => s_axi_awaddr(3),
O => bram_addr_ld(3)
);
\save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(0),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2__0_n_0\
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(4),
O => bram_addr_ld(4)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(5),
O => bram_addr_ld(5)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(8),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(6),
O => bram_addr_ld(6)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(7),
O => bram_addr_ld(7)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(8),
Q => save_init_bram_addr_ld(10),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(9),
Q => save_init_bram_addr_ld(11),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => save_init_bram_addr_ld(12),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => save_init_bram_addr_ld(13),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => save_init_bram_addr_ld(14),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => save_init_bram_addr_ld(15),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(1),
Q => save_init_bram_addr_ld(3),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(2),
Q => save_init_bram_addr_ld(4),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(3),
Q => save_init_bram_addr_ld(5),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(4),
Q => save_init_bram_addr_ld(6),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(5),
Q => save_init_bram_addr_ld(7),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(6),
Q => save_init_bram_addr_ld(8),
R => s_axi_aresetn_0
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(7),
Q => save_init_bram_addr_ld(9),
R => s_axi_aresetn_0
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F909090900000000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => \^wrap_burst_total_reg[0]_0\,
I2 => \wrap_burst_total[0]_i_4__0_n_0\,
I3 => Q(1),
I4 => Q(2),
I5 => \wrap_burst_total[0]_i_5_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(2),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(1),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_4__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_awaddr_full,
I1 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_4__0_n_0\
);
\wrap_burst_total[0]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awlen(0),
I1 => Q(0),
I2 => s_axi_awlen(3),
I3 => axi_awaddr_full,
I4 => Q(3),
O => \wrap_burst_total[0]_i_5_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"000008F3"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => axi_awsize_pipe(0),
I3 => \^wrap_burst_total_reg[2]_0\,
I4 => \wrap_burst_total[2]_i_2__0_n_0\,
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"5000000044004400"
)
port map (
I0 => \wrap_burst_total[2]_i_2__0_n_0\,
I1 => s_axi_awlen(2),
I2 => Q(2),
I3 => \^wrap_burst_total_reg[2]_0\,
I4 => axi_awsize_pipe(0),
I5 => axi_awaddr_full,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"335FFF5F"
)
port map (
I0 => s_axi_awlen(1),
I1 => Q(1),
I2 => s_axi_awlen(0),
I3 => axi_awaddr_full,
I4 => Q(0),
O => \wrap_burst_total[2]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(3),
O => \^wrap_burst_total_reg[2]_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => s_axi_aresetn_0
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => s_axi_aresetn_0
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => s_axi_aresetn_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
port (
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_1\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_3\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_addr_ld_en : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC;
\rd_data_sm_cs_reg[1]\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_rvalid_int_reg : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
end_brst_rd : in STD_LOGIC;
brst_zero : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_araddr_full : in STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
axi_rd_burst_two_reg : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
axi_aresetn_d2 : in STD_LOGIC;
last_bram_addr : in STD_LOGIC;
rd_addr_sm_cs : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
no_ar_ack : in STD_LOGIC;
pend_rd_op : in STD_LOGIC;
ar_active : in STD_LOGIC;
axi_b2b_brst : in STD_LOGIC;
axi_arsize_pipe_max : in STD_LOGIC;
disable_b2b_brst : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_arlen_pipe_1_or_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 : entity is "wrap_brst";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC;
signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[15]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[15]_i_3__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[13]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[14]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[15]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_5__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_4__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5__0\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair4";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\;
SR(0) <= \^sr\(0);
bram_addr_ld_en <= \^bram_addr_ld_en\;
\rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\;
\wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\;
\wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF20FFFFDF200000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I2 => curr_fixed_burst_reg,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0F0E0FFE0F0E0F0"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\,
I2 => \^rd_data_sm_cs_reg[1]\,
I3 => Q(1),
I4 => Q(3),
I5 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => Q(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0D00000000000000"
)
port map (
I0 => end_brst_rd,
I1 => axi_b2b_brst,
I2 => brst_zero,
I3 => axi_rvalid_int_reg,
I4 => s_axi_rready,
I5 => Q(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[12]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[13]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[14]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
O => E(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[15]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A80000"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\,
I2 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I4 => curr_wrap_burst_reg,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00A000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \wrap_burst_total_reg_n_0_[1]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I4 => \wrap_burst_total_reg_n_0_[0]\,
I5 => \wrap_burst_total_reg_n_0_[2]\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A808FD5D"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => s_axi_araddr(0),
I2 => axi_araddr_full,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAFFFFA6AA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
O => \^d\(7)
);
bram_en_int_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000004000"
)
port map (
I0 => Q(0),
I1 => Q(2),
I2 => axi_rvalid_int_reg,
I3 => s_axi_rready,
I4 => end_brst_rd,
I5 => brst_zero,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
bram_rst_b_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0302030203020300"
)
port map (
I0 => Q(0),
I1 => Q(3),
I2 => Q(2),
I3 => Q(1),
I4 => axi_rd_burst_two_reg,
I5 => axi_rd_burst,
O => \^rd_data_sm_cs_reg[1]\
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[10]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(8),
O => \save_init_bram_addr_ld[10]_i_1__0_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(9),
O => \save_init_bram_addr_ld[11]_i_1__0_n_0\
);
\save_init_bram_addr_ld[15]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888A88888888"
)
port map (
I0 => axi_aresetn_d2,
I1 => \save_init_bram_addr_ld[15]_i_2__0_n_0\,
I2 => \save_init_bram_addr_ld[15]_i_3__0_n_0\,
I3 => \^save_init_bram_addr_ld_reg[15]_0\,
I4 => \^save_init_bram_addr_ld_reg[15]_1\,
I5 => last_bram_addr,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000054"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => no_ar_ack,
I4 => pend_rd_op,
I5 => ar_active,
O => \save_init_bram_addr_ld[15]_i_2__0_n_0\
);
\save_init_bram_addr_ld[15]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => brst_zero,
I1 => s_axi_rready,
I2 => axi_rvalid_int_reg,
O => \save_init_bram_addr_ld[15]_i_3__0_n_0\
);
\save_init_bram_addr_ld[15]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0040"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[15]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => axi_arsize_pipe_max,
I1 => disable_b2b_brst,
I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\,
I3 => axi_arlen_pipe_1_or_2,
I4 => axi_araddr_full,
O => \^save_init_bram_addr_ld_reg[15]_1\
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(1),
O => \save_init_bram_addr_ld[3]_i_1__0_n_0\
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A282"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[3]\,
I1 => \wrap_burst_total_reg_n_0_[1]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[0]\,
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(2),
O => \save_init_bram_addr_ld[4]_i_1__0_n_0\
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[4]\,
I1 => \wrap_burst_total_reg_n_0_[0]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[5]\,
I1 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
I4 => axi_araddr_full,
I5 => s_axi_araddr(3),
O => \save_init_bram_addr_ld[5]_i_1__0_n_0\
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \wrap_burst_total_reg_n_0_[0]\,
I1 => \wrap_burst_total_reg_n_0_[2]\,
I2 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[6]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(4),
O => \save_init_bram_addr_ld[6]_i_1__0_n_0\
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[7]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(5),
O => \save_init_bram_addr_ld[7]_i_1__0_n_0\
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[8]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(6),
O => \save_init_bram_addr_ld[8]_i_1__0_n_0\
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[9]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(7),
O => \save_init_bram_addr_ld[9]_i_1__0_n_0\
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[10]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[11]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => \save_init_bram_addr_ld_reg_n_0_[12]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => \save_init_bram_addr_ld_reg_n_0_[13]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => \save_init_bram_addr_ld_reg_n_0_[14]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => \save_init_bram_addr_ld_reg_n_0_[15]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[3]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[4]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[5]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[6]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[7]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[8]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[9]\,
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A000C300"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I1 => \^wrap_burst_total_reg[0]_0\,
I2 => \^wrap_burst_total_reg[0]_1\,
I3 => \^wrap_burst_total_reg[0]_2\,
I4 => \wrap_burst_total[0]_i_5__0_n_0\,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I1 => axi_araddr_full,
I2 => s_axi_arlen(2),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
O => \^wrap_burst_total_reg[0]_1\
);
\wrap_burst_total[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0),
I1 => axi_araddr_full,
I2 => s_axi_arlen(0),
O => \^wrap_burst_total_reg[0]_2\
);
\wrap_burst_total[0]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
O => \wrap_burst_total[0]_i_5__0_n_0\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220A880A000A880A"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => axi_arsize_pipe(0),
I2 => s_axi_arlen(3),
I3 => axi_araddr_full,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3),
I5 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000888800000000"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => s_axi_arlen(2),
I2 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(2),
I3 => axi_arsize_pipe(0),
I4 => axi_araddr_full,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_arlen(1),
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(1),
I2 => s_axi_arlen(0),
I3 => axi_araddr_full,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(0),
O => \wrap_burst_total[2]_i_2_n_0\
);
\wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3),
I1 => axi_araddr_full,
I2 => s_axi_arlen(3),
O => \^wrap_burst_total_reg[0]_3\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[0]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[1]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[2]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
port (
bram_rst_a : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_en_b : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
axi_aresetn_d2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_aresetn_re_reg : in STD_LOGIC;
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_4_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[0]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_reg_n_0_[0]\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_26 : STD_LOGIC;
signal I_WRAP_BRST_n_27 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_5 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_i_1_n_0 : STD_LOGIC;
signal act_rd_burst_i_3_n_0 : STD_LOGIC;
signal act_rd_burst_i_4_n_0 : STD_LOGIC;
signal act_rd_burst_i_5_n_0 : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal act_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal ar_active : STD_LOGIC;
signal araddr_pipe_ld43_out : STD_LOGIC;
signal axi_araddr_full : STD_LOGIC;
signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_arid_pipe : STD_LOGIC;
signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_arlen_pipe_1_or_2 : STD_LOGIC;
signal axi_arready_int : STD_LOGIC;
signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_arsize_pipe_max : STD_LOGIC;
signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst : STD_LOGIC;
signal axi_b2b_brst_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst_i_2_n_0 : STD_LOGIC;
signal axi_early_arready_int : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_i_2_n_0 : STD_LOGIC;
signal axi_rd_burst_i_3_n_0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_two_reg_n_0 : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC;
signal axi_rid_temp2 : STD_LOGIC;
signal axi_rid_temp2_full : STD_LOGIC;
signal axi_rid_temp_full : STD_LOGIC;
signal axi_rid_temp_full_d1 : STD_LOGIC;
signal axi_rlast_int_i_1_n_0 : STD_LOGIC;
signal axi_rlast_set : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC;
signal axi_rvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal \^bram_en_b\ : STD_LOGIC;
signal bram_en_int_i_10_n_0 : STD_LOGIC;
signal bram_en_int_i_11_n_0 : STD_LOGIC;
signal bram_en_int_i_12_n_0 : STD_LOGIC;
signal bram_en_int_i_13_n_0 : STD_LOGIC;
signal bram_en_int_i_1_n_0 : STD_LOGIC;
signal bram_en_int_i_2_n_0 : STD_LOGIC;
signal bram_en_int_i_3_n_0 : STD_LOGIC;
signal bram_en_int_i_4_n_0 : STD_LOGIC;
signal bram_en_int_i_5_n_0 : STD_LOGIC;
signal bram_en_int_i_6_n_0 : STD_LOGIC;
signal bram_en_int_i_7_n_0 : STD_LOGIC;
signal bram_en_int_i_9_n_0 : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal brst_cnt_max : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_one_i_1_n_0 : STD_LOGIC;
signal brst_one_i_2_n_0 : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal brst_zero_i_1_n_0 : STD_LOGIC;
signal brst_zero_i_2_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal disable_b2b_brst_i_2_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_3_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_4_n_0 : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC;
signal end_brst_rd_i_1_n_0 : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal last_bram_addr_i_2_n_0 : STD_LOGIC;
signal last_bram_addr_i_3_n_0 : STD_LOGIC;
signal last_bram_addr_i_4_n_0 : STD_LOGIC;
signal last_bram_addr_i_5_n_0 : STD_LOGIC;
signal last_bram_addr_i_6_n_0 : STD_LOGIC;
signal last_bram_addr_i_7_n_0 : STD_LOGIC;
signal last_bram_addr_i_8_n_0 : STD_LOGIC;
signal last_bram_addr_i_9_n_0 : STD_LOGIC;
signal no_ar_ack : STD_LOGIC;
signal no_ar_ack_i_1_n_0 : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal pend_rd_op_i_1_n_0 : STD_LOGIC;
signal pend_rd_op_i_2_n_0 : STD_LOGIC;
signal pend_rd_op_i_3_n_0 : STD_LOGIC;
signal pend_rd_op_i_4_n_0 : STD_LOGIC;
signal pend_rd_op_i_5_n_0 : STD_LOGIC;
signal pend_rd_op_i_6_n_0 : STD_LOGIC;
signal pend_rd_op_i_7_n_0 : STD_LOGIC;
signal pend_rd_op_i_8_n_0 : STD_LOGIC;
signal rd_addr_sm_cs : STD_LOGIC;
signal rd_adv_buf67_out : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC;
signal rd_data_sm_ns : STD_LOGIC;
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rddata_mux_sel_cmb : STD_LOGIC;
signal rddata_mux_sel_i_1_n_0 : STD_LOGIC;
signal rddata_mux_sel_i_3_n_0 : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of rlast_sm_cs : signal is "yes";
signal \^s_axi_rid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_rlast_sm_cs[2]_i_2\ : label is "soft_lutpair14";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \GEN_AR_DUAL.ar_active_i_3\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_5\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_int[0]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp[0]_i_2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of act_rd_burst_i_5 : label is "soft_lutpair43";
attribute SOFT_HLUTNM of axi_rd_burst_two_i_2 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of bram_en_int_i_10 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of bram_en_int_i_11 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of bram_en_int_i_13 : label is "soft_lutpair22";
attribute SOFT_HLUTNM of bram_en_int_i_6 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of bram_en_int_i_9 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of brst_one_i_2 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair18";
attribute SOFT_HLUTNM of brst_zero_i_2 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair6";
attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair43";
attribute SOFT_HLUTNM of last_bram_addr_i_2 : label is "soft_lutpair31";
attribute SOFT_HLUTNM of last_bram_addr_i_7 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of last_bram_addr_i_9 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of pend_rd_op_i_5 : label is "soft_lutpair27";
attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair22";
attribute SOFT_HLUTNM of pend_rd_op_i_7 : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \rd_data_sm_cs[1]_i_2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_3\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_5\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_7\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of s_axi_arready_INST_0 : label is "soft_lutpair21";
begin
Q(13 downto 0) <= \^q\(13 downto 0);
bram_en_b <= \^bram_en_b\;
bram_rst_a <= \^bram_rst_a\;
s_axi_rid(0) <= \^s_axi_rid\(0);
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rvalid <= \^s_axi_rvalid\;
\/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0011001300130013"
)
port map (
I0 => axi_rd_burst,
I1 => rlast_sm_cs(1),
I2 => act_rd_burst_two,
I3 => axi_rd_burst_two_reg_n_0,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\
);
\/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F007F003F0055"
)
port map (
I0 => axi_rd_burst,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rlast_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_two,
O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\
);
\/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F111F000E000"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rlast_sm_cs(0),
I5 => last_bram_addr,
O => \/i__n_0\
);
\/i___0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080000F8080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(1),
I4 => rlast_sm_cs(2),
I5 => \^s_axi_rlast\,
O => axi_rlast_set
);
\FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(0),
O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(1),
O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A4FFFF00A40000"
)
port map (
I0 => rlast_sm_cs(1),
I1 => p_0_in13_in,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
I4 => \/i__n_0\,
I5 => rlast_sm_cs(2),
O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst,
O => p_0_in13_in
);
\FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\,
Q => rlast_sm_cs(0),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\,
Q => rlast_sm_cs(1),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\,
Q => rlast_sm_cs(2),
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEEE"
)
port map (
I0 => p_9_out,
I1 => axi_arready_int,
I2 => s_axi_arvalid,
I3 => axi_araddr_full,
I4 => araddr_pipe_ld43_out,
O => \GEN_ARREADY.axi_arready_int_i_1_n_0\
);
\GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BAAA"
)
port map (
I0 => axi_aresetn_re_reg,
I1 => axi_early_arready_int,
I2 => axi_araddr_full,
I3 => bram_addr_ld_en,
O => p_9_out
);
\GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_ARREADY.axi_arready_int_i_1_n_0\,
Q => axi_arready_int,
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\,
I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\,
I2 => rd_data_sm_cs(3),
I3 => brst_one,
I4 => axi_arready_int,
I5 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\,
O => p_48_out
);
\GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"03C4000400C40004"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_adv_buf67_out,
I5 => bram_en_int_i_9_n_0,
O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => axi_araddr_full,
I1 => s_axi_arvalid,
O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAEAAAEAFFFFAAEA"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => \rd_data_sm_cs[3]_i_6_n_0\,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => brst_zero,
I5 => rd_adv_buf67_out,
O => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\
);
\GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_48_out,
Q => axi_early_arready_int,
R => \^bram_rst_a\
);
\GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0FBFBFBF0F0F0F0"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\,
I1 => \rd_data_sm_cs[2]_i_3_n_0\,
I2 => bram_addr_ld_en,
I3 => \rd_data_sm_cs[2]_i_5_n_0\,
I4 => rd_adv_buf67_out,
I5 => ar_active,
O => \GEN_AR_DUAL.ar_active_i_1_n_0\
);
\GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B0FFBFFFB0FFBF0F"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_3_n_0\,
I1 => I_WRAP_BRST_n_27,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => axi_rd_burst,
O => \GEN_AR_DUAL.ar_active_i_2_n_0\
);
\GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"0DFFFFFF"
)
port map (
I0 => end_brst_rd,
I1 => axi_b2b_brst,
I2 => brst_zero,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => \GEN_AR_DUAL.ar_active_i_3_n_0\
);
\GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.ar_active_i_1_n_0\,
Q => ar_active,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10001000F0F01000"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I4 => last_bram_addr,
I5 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\,
O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\
);
\GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\,
Q => rd_addr_sm_cs,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(8),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(9),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(10),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(11),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(12),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(13),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(0),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(1),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(2),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(3),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(4),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(5),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(6),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(7),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C08888CCCC8888"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => s_axi_aresetn,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I4 => axi_araddr_full,
I5 => bram_addr_ld_en,
O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\,
Q => axi_araddr_full,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"03AA"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
I1 => s_axi_arburst(0),
I2 => s_axi_arburst(1),
I3 => araddr_pipe_ld43_out,
O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(0),
Q => axi_arburst_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(1),
Q => axi_arburst_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(0),
Q => axi_arid_pipe,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220022002A002200"
)
port map (
I0 => axi_aresetn_d2,
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I2 => rd_addr_sm_cs,
I3 => s_axi_arvalid,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I5 => axi_araddr_full,
O => araddr_pipe_ld43_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFF70FFFFFFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => brst_zero,
I3 => I_WRAP_BRST_n_26,
I4 => I_WRAP_BRST_n_27,
I5 => last_bram_addr,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => no_ar_ack,
I1 => pend_rd_op,
I2 => ar_active,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(1),
I1 => s_axi_arlen(7),
I2 => s_axi_arlen(4),
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\,
O => p_13_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_axi_arlen(6),
I1 => s_axi_arlen(2),
I2 => s_axi_arlen(5),
I3 => s_axi_arlen(3),
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => p_13_out,
Q => axi_arlen_pipe_1_or_2,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(0),
Q => axi_arlen_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(1),
Q => axi_arlen_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(2),
Q => axi_arlen_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(3),
Q => axi_arlen_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(4),
Q => axi_arlen_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(5),
Q => axi_arlen_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(6),
Q => axi_arlen_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(7),
Q => axi_arlen_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => '1',
Q => axi_arsize_pipe(1),
R => '0'
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => brst_cnt_max,
I1 => pend_rd_op,
I2 => ar_active,
I3 => brst_zero,
I4 => s_axi_aresetn,
I5 => bram_addr_ld_en,
O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\,
Q => brst_cnt_max,
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \^q\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => I_WRAP_BRST_n_24,
I3 => \^q\(5),
I4 => \^q\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_14,
Q => \^q\(8),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_13,
Q => \^q\(9),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_12,
Q => \^q\(10),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_11,
Q => \^q\(11),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_10,
Q => \^q\(12),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_9,
Q => \^q\(13),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_22,
Q => \^q\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_21,
Q => \^q\(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_20,
Q => \^q\(2),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_19,
Q => \^q\(3),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_18,
Q => \^q\(4),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_17,
Q => \^q\(5),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_16,
Q => \^q\(6),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_7,
D => I_WRAP_BRST_n_15,
Q => \^q\(7),
R => '0'
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_b(0),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_b(10),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_b(11),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_b(12),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_b(13),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_b(14),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_b(15),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_b(16),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_b(17),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_b(18),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_b(19),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_b(1),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\,
Q => s_axi_rdata(1),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_b(20),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_b(21),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_b(22),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_b(23),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_b(24),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_b(25),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_b(26),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_b(27),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_b(28),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_b(29),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_b(2),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_b(30),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
I2 => axi_b2b_brst,
I3 => s_axi_aresetn,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414545410000404"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\,
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_b(31),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
O => rd_adv_buf67_out
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
Q => s_axi_rdata(31),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_b(3),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_b(4),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_b(5),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_b(6),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_b(7),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_b(8),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_b(9),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAABAAAAAA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(3),
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(0),
O => rd_skid_buf_ld
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(0),
Q => rd_skid_buf(0),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(10),
Q => rd_skid_buf(10),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(11),
Q => rd_skid_buf(11),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(12),
Q => rd_skid_buf(12),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(13),
Q => rd_skid_buf(13),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(14),
Q => rd_skid_buf(14),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(15),
Q => rd_skid_buf(15),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(16),
Q => rd_skid_buf(16),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(17),
Q => rd_skid_buf(17),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(18),
Q => rd_skid_buf(18),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(19),
Q => rd_skid_buf(19),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(1),
Q => rd_skid_buf(1),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(20),
Q => rd_skid_buf(20),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(21),
Q => rd_skid_buf(21),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(22),
Q => rd_skid_buf(22),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(23),
Q => rd_skid_buf(23),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(24),
Q => rd_skid_buf(24),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(25),
Q => rd_skid_buf(25),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(26),
Q => rd_skid_buf(26),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(27),
Q => rd_skid_buf(27),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(28),
Q => rd_skid_buf(28),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(29),
Q => rd_skid_buf(29),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(2),
Q => rd_skid_buf(2),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(30),
Q => rd_skid_buf(30),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(31),
Q => rd_skid_buf(31),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(3),
Q => rd_skid_buf(3),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(4),
Q => rd_skid_buf(4),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(5),
Q => rd_skid_buf(5),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(6),
Q => rd_skid_buf(6),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(7),
Q => rd_skid_buf(7),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(8),
Q => rd_skid_buf(8),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(9),
Q => rd_skid_buf(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_int[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"E200E200F0000000"
)
port map (
I0 => \^s_axi_rid\(0),
I1 => axi_rvalid_set,
I2 => axi_rid_temp,
I3 => s_axi_aresetn,
I4 => axi_b2b_brst,
I5 => \GEN_RID.axi_rid_int[0]_i_2_n_0\,
O => \GEN_RID.axi_rid_int[0]_i_1_n_0\
);
\GEN_RID.axi_rid_int[0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
O => \GEN_RID.axi_rid_int[0]_i_2_n_0\
);
\GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_int[0]_i_1_n_0\,
Q => \^s_axi_rid\(0),
R => '0'
);
\GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFFFFFB8000000"
)
port map (
I0 => axi_arid_pipe,
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
I5 => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\,
O => \GEN_RID.axi_rid_temp2[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080000C8C800C0"
)
port map (
I0 => bram_addr_ld_en,
I1 => s_axi_aresetn,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full_d1,
I4 => axi_rid_temp_full,
I5 => p_4_out,
O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\,
Q => axi_rid_temp2_full,
R => '0'
);
\GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2[0]_i_1_n_0\,
Q => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFAACFCFC0AAC0C0"
)
port map (
I0 => axi_rid_temp2,
I1 => \GEN_RID.axi_rid_temp2_reg_n_0_[0]\,
I2 => \GEN_RID.axi_rid_temp[0]_i_3_n_0\,
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
I5 => axi_rid_temp,
O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe,
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
O => axi_rid_temp2
);
\GEN_RID.axi_rid_temp[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA08AAAAAA08AA08"
)
port map (
I0 => axi_rid_temp2_full,
I1 => axi_rid_temp_full_d1,
I2 => axi_rid_temp_full,
I3 => axi_rvalid_set,
I4 => \GEN_RID.axi_rid_int[0]_i_2_n_0\,
I5 => axi_b2b_brst,
O => \GEN_RID.axi_rid_temp[0]_i_3_n_0\
);
\GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rid_temp_full,
Q => axi_rid_temp_full_d1,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E000F0A0A0"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_rid_temp_full_d1,
I2 => s_axi_aresetn,
I3 => p_4_out,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2_full,
O => \GEN_RID.axi_rid_temp_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_rvalid_set,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => axi_b2b_brst,
O => p_4_out
);
\GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp_full_i_1_n_0\,
Q => axi_rid_temp_full,
R => '0'
);
\GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\,
Q => axi_rid_temp,
R => \^bram_rst_a\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0
port map (
D(13) => I_WRAP_BRST_n_9,
D(12) => I_WRAP_BRST_n_10,
D(11) => I_WRAP_BRST_n_11,
D(10) => I_WRAP_BRST_n_12,
D(9) => I_WRAP_BRST_n_13,
D(8) => I_WRAP_BRST_n_14,
D(7) => I_WRAP_BRST_n_15,
D(6) => I_WRAP_BRST_n_16,
D(5) => I_WRAP_BRST_n_17,
D(4) => I_WRAP_BRST_n_18,
D(3) => I_WRAP_BRST_n_19,
D(2) => I_WRAP_BRST_n_20,
D(1) => I_WRAP_BRST_n_21,
D(0) => I_WRAP_BRST_n_22,
E(1) => bram_addr_ld_en_mod,
E(0) => I_WRAP_BRST_n_7,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\(3 downto 0) => axi_arlen_pipe(3 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_0,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_8,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9 downto 0) => \^q\(9 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_24,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\,
Q(3 downto 0) => rd_data_sm_cs(3 downto 0),
SR(0) => \^bram_rst_a\,
ar_active => ar_active,
axi_araddr_full => axi_araddr_full,
axi_aresetn_d2 => axi_aresetn_d2,
axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2,
axi_arsize_pipe(0) => axi_arsize_pipe(1),
axi_arsize_pipe_max => axi_arsize_pipe_max,
axi_b2b_brst => axi_b2b_brst,
axi_rd_burst => axi_rd_burst,
axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0,
axi_rvalid_int_reg => \^s_axi_rvalid\,
bram_addr_ld_en => bram_addr_ld_en,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_wrap_burst_reg => curr_wrap_burst_reg,
disable_b2b_brst => disable_b2b_brst,
end_brst_rd => end_brst_rd,
last_bram_addr => last_bram_addr,
no_ar_ack => no_ar_ack,
pend_rd_op => pend_rd_op,
rd_addr_sm_cs => rd_addr_sm_cs,
\rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_25,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_26,
\save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_27,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_2,
\wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_3,
\wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_4,
\wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_5
);
act_rd_burst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002EEE22E2"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_set,
I2 => bram_addr_ld_en,
I3 => axi_rd_burst_two,
I4 => axi_rd_burst,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_i_1_n_0
);
act_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A888A888888888"
)
port map (
I0 => \rd_data_sm_cs[2]_i_3_n_0\,
I1 => act_rd_burst_i_4_n_0,
I2 => act_rd_burst_i_5_n_0,
I3 => axi_rd_burst_i_2_n_0,
I4 => I_WRAP_BRST_n_4,
I5 => bram_addr_ld_en,
O => act_rd_burst_set
);
act_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"20000040FFFFFFFF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => \rd_data_sm_cs[3]_i_7_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => s_axi_aresetn,
O => act_rd_burst_i_3_n_0
);
act_rd_burst_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"5500FC00"
)
port map (
I0 => bram_en_int_i_12_n_0,
I1 => axi_rd_burst_two_reg_n_0,
I2 => axi_rd_burst,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => act_rd_burst_i_4_n_0
);
act_rd_burst_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => act_rd_burst_i_5_n_0
);
act_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_i_1_n_0,
Q => act_rd_burst,
R => '0'
);
act_rd_burst_two_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst_set,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_two_i_1_n_0
);
act_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_two_i_1_n_0,
Q => act_rd_burst_two,
R => '0'
);
axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => axi_arsize_pipe_max,
O => axi_arsize_pipe_max_i_1_n_0
);
axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_arsize_pipe_max_i_1_n_0,
Q => axi_arsize_pipe_max,
R => \^bram_rst_a\
);
axi_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F074F0F0F074"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => axi_b2b_brst_i_2_n_0,
I2 => axi_b2b_brst,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => disable_b2b_brst_i_2_n_0,
O => axi_b2b_brst_i_1_n_0
);
axi_b2b_brst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AA080000"
)
port map (
I0 => \rd_data_sm_cs[0]_i_3_n_0\,
I1 => end_brst_rd,
I2 => axi_b2b_brst,
I3 => brst_zero,
I4 => rd_adv_buf67_out,
I5 => I_WRAP_BRST_n_27,
O => axi_b2b_brst_i_2_n_0
);
axi_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_b2b_brst_i_1_n_0,
Q => axi_b2b_brst,
R => \^bram_rst_a\
);
axi_rd_burst_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"303000A0"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_i_1_n_0
);
axi_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000001000111"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => I_WRAP_BRST_n_5,
I2 => axi_arlen_pipe(1),
I3 => axi_araddr_full,
I4 => s_axi_arlen(1),
I5 => axi_rd_burst_i_3_n_0,
O => axi_rd_burst_i_2_n_0
);
axi_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBBFCB8"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => axi_arlen_pipe(4),
I4 => s_axi_arlen(4),
I5 => last_bram_addr_i_9_n_0,
O => axi_rd_burst_i_3_n_0
);
axi_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_i_1_n_0,
Q => axi_rd_burst,
R => '0'
);
axi_rd_burst_two_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0C000A0"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst_two,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_two_i_1_n_0
);
axi_rd_burst_two_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => axi_rd_burst_two
);
axi_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_two_i_1_n_0,
Q => axi_rd_burst_two_reg_n_0,
R => '0'
);
axi_rlast_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88A8"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_rlast_set,
I2 => \^s_axi_rlast\,
I3 => s_axi_rready,
O => axi_rlast_int_i_1_n_0
);
axi_rlast_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rlast_int_i_1_n_0,
Q => \^s_axi_rlast\,
R => '0'
);
axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEEEA"
)
port map (
I0 => axi_rvalid_clr_ok,
I1 => last_bram_addr,
I2 => disable_b2b_brst,
I3 => disable_b2b_brst_cmb,
I4 => axi_rvalid_clr_ok_i_2_n_0,
I5 => axi_rvalid_clr_ok_i_3_n_0,
O => axi_rvalid_clr_ok_i_1_n_0
);
axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
O => axi_rvalid_clr_ok_i_2_n_0
);
axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_4_n_0\,
I1 => bram_addr_ld_en,
I2 => s_axi_aresetn,
O => axi_rvalid_clr_ok_i_3_n_0
);
axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_clr_ok_i_1_n_0,
Q => axi_rvalid_clr_ok,
R => '0'
);
axi_rvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00E0E0E0E0E0E0E0"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => axi_rvalid_set,
I2 => s_axi_aresetn,
I3 => axi_rvalid_clr_ok,
I4 => \^s_axi_rlast\,
I5 => s_axi_rready,
O => axi_rvalid_int_i_1_n_0
);
axi_rvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_int_i_1_n_0,
Q => \^s_axi_rvalid\,
R => '0'
);
axi_rvalid_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
O => axi_rvalid_set_cmb
);
axi_rvalid_set_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^bram_rst_a\
);
bram_en_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEEFFFA0022000A"
)
port map (
I0 => bram_en_int_i_2_n_0,
I1 => bram_en_int_i_3_n_0,
I2 => bram_en_int_i_4_n_0,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => \^bram_en_b\,
O => bram_en_int_i_1_n_0
);
bram_en_int_i_10: unisim.vcomponents.LUT5
generic map(
INIT => X"E0000000"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => bram_addr_ld_en,
O => bram_en_int_i_10_n_0
);
bram_en_int_i_11: unisim.vcomponents.LUT4
generic map(
INIT => X"0111"
)
port map (
I0 => end_brst_rd,
I1 => brst_zero,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => bram_en_int_i_11_n_0
);
bram_en_int_i_12: unisim.vcomponents.LUT6
generic map(
INIT => X"BFFFBFBFBFFFBFFF"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => brst_zero,
I4 => axi_b2b_brst,
I5 => end_brst_rd,
O => bram_en_int_i_12_n_0
);
bram_en_int_i_13: unisim.vcomponents.LUT3
generic map(
INIT => X"45"
)
port map (
I0 => brst_zero,
I1 => axi_b2b_brst,
I2 => end_brst_rd,
O => bram_en_int_i_13_n_0
);
bram_en_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFF4044"
)
port map (
I0 => bram_en_int_i_5_n_0,
I1 => rd_data_sm_cs(1),
I2 => bram_en_int_i_6_n_0,
I3 => rd_data_sm_cs(2),
I4 => bram_en_int_i_7_n_0,
I5 => I_WRAP_BRST_n_0,
O => bram_en_int_i_2_n_0
);
bram_en_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"707370707C7F7C7C"
)
port map (
I0 => bram_en_int_i_6_n_0,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => rd_adv_buf67_out,
I4 => bram_en_int_i_9_n_0,
I5 => bram_en_int_i_10_n_0,
O => bram_en_int_i_3_n_0
);
bram_en_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"A0001111AAAA1111"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => bram_addr_ld_en,
I2 => bram_en_int_i_11_n_0,
I3 => brst_one,
I4 => rd_data_sm_cs(1),
I5 => bram_en_int_i_12_n_0,
O => bram_en_int_i_4_n_0
);
bram_en_int_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0044054455440544"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => axi_rd_burst_two_reg_n_0,
I2 => bram_en_int_i_9_n_0,
I3 => rd_data_sm_cs(0),
I4 => rd_adv_buf67_out,
I5 => bram_en_int_i_13_n_0,
O => bram_en_int_i_5_n_0
);
bram_en_int_i_6: unisim.vcomponents.LUT4
generic map(
INIT => X"ECCC"
)
port map (
I0 => pend_rd_op,
I1 => bram_addr_ld_en,
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
O => bram_en_int_i_6_n_0
);
bram_en_int_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"5554005500540000"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => axi_rd_burst_two_reg_n_0,
I2 => axi_rd_burst,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => bram_addr_ld_en,
O => bram_en_int_i_7_n_0
);
bram_en_int_i_9: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => bram_en_int_i_9_n_0
);
bram_en_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_int_i_1_n_0,
Q => \^bram_en_b\,
R => \^bram_rst_a\
);
\brst_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1DDD111"
)
port map (
I0 => brst_cnt(0),
I1 => bram_addr_ld_en,
I2 => axi_arlen_pipe(0),
I3 => axi_araddr_full,
I4 => s_axi_arlen(0),
O => \brst_cnt[0]_i_1_n_0\
);
\brst_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
I3 => bram_addr_ld_en,
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[1]_i_1_n_0\
);
\brst_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => bram_addr_ld_en,
I2 => brst_cnt(2),
I3 => brst_cnt(1),
I4 => brst_cnt(0),
O => \brst_cnt[2]_i_1_n_0\
);
\brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_5,
I1 => bram_addr_ld_en,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[3]_i_1_n_0\
);
\brst_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arlen(4),
I3 => bram_addr_ld_en,
I4 => brst_cnt(4),
I5 => \brst_cnt[4]_i_2_n_0\,
O => \brst_cnt[4]_i_1_n_0\
);
\brst_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => brst_cnt(3),
I1 => brst_cnt(2),
I2 => brst_cnt(0),
I3 => brst_cnt(1),
O => \brst_cnt[4]_i_2_n_0\
);
\brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => bram_addr_ld_en,
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[5]_i_1_n_0\
);
\brst_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(6),
I3 => brst_cnt(5),
I4 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[6]_i_1_n_0\
);
\brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arlen(6),
O => \brst_cnt[6]_i_2_n_0\
);
\brst_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_8,
O => \brst_cnt[7]_i_1_n_0\
);
\brst_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB8B8B8B8"
)
port map (
I0 => \brst_cnt[7]_i_3_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(7),
I3 => brst_cnt(6),
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[7]_i_2_n_0\
);
\brst_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arlen(7),
O => \brst_cnt[7]_i_3_n_0\
);
\brst_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => brst_cnt(4),
I1 => brst_cnt(1),
I2 => brst_cnt(0),
I3 => brst_cnt(2),
I4 => brst_cnt(3),
O => \brst_cnt[7]_i_4_n_0\
);
brst_cnt_max_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_cnt_max,
Q => brst_cnt_max_d1,
R => \^bram_rst_a\
);
\brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[0]_i_1_n_0\,
Q => brst_cnt(0),
R => \^bram_rst_a\
);
\brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[1]_i_1_n_0\,
Q => brst_cnt(1),
R => \^bram_rst_a\
);
\brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[2]_i_1_n_0\,
Q => brst_cnt(2),
R => \^bram_rst_a\
);
\brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[3]_i_1_n_0\,
Q => brst_cnt(3),
R => \^bram_rst_a\
);
\brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[4]_i_1_n_0\,
Q => brst_cnt(4),
R => \^bram_rst_a\
);
\brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[5]_i_1_n_0\,
Q => brst_cnt(5),
R => \^bram_rst_a\
);
\brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[6]_i_1_n_0\,
Q => brst_cnt(6),
R => \^bram_rst_a\
);
\brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[7]_i_2_n_0\,
Q => brst_cnt(7),
R => \^bram_rst_a\
);
brst_one_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F0EE0000"
)
port map (
I0 => brst_one,
I1 => brst_one_i_2_n_0,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => s_axi_aresetn,
I5 => last_bram_addr_i_2_n_0,
O => brst_one_i_1_n_0
);
brst_one_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_5_n_0,
I1 => brst_cnt(1),
I2 => brst_cnt(0),
O => brst_one_i_2_n_0
);
brst_one_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_one_i_1_n_0,
Q => brst_one,
R => '0'
);
brst_zero_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => brst_zero,
I1 => last_bram_addr_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero_i_2_n_0,
O => brst_zero_i_1_n_0
);
brst_zero_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_arlen_pipe(0),
I2 => axi_araddr_full,
I3 => s_axi_arlen(0),
I4 => axi_rd_burst_i_2_n_0,
O => brst_zero_i_2_n_0
);
brst_zero_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_zero_i_1_n_0,
Q => brst_zero,
R => '0'
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arburst(0),
I1 => axi_arburst_pipe(0),
I2 => s_axi_arburst(1),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^bram_rst_a\
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_arburst(1),
I1 => axi_arburst_pipe(1),
I2 => s_axi_arburst(0),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^bram_rst_a\
);
disable_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000D0000"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst_i_2_n_0,
I5 => disable_b2b_brst_i_3_n_0,
O => disable_b2b_brst_cmb
);
disable_b2b_brst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
O => disable_b2b_brst_i_2_n_0
);
disable_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEE00EE0EEEE"
)
port map (
I0 => disable_b2b_brst_i_4_n_0,
I1 => disable_b2b_brst,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(3),
O => disable_b2b_brst_i_3_n_0
);
disable_b2b_brst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FE0000000000"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
I2 => brst_one,
I3 => rd_data_sm_cs(0),
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[2]_i_3_n_0\,
O => disable_b2b_brst_i_4_n_0
);
disable_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^bram_rst_a\
);
end_brst_rd_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFCD00002200"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => end_brst_rd_clr,
O => end_brst_rd_clr_i_1_n_0
);
end_brst_rd_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_clr_i_1_n_0,
Q => end_brst_rd_clr,
R => \^bram_rst_a\
);
end_brst_rd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0020F020"
)
port map (
I0 => brst_cnt_max,
I1 => brst_cnt_max_d1,
I2 => s_axi_aresetn,
I3 => end_brst_rd,
I4 => end_brst_rd_clr,
O => end_brst_rd_i_1_n_0
);
end_brst_rd_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_i_1_n_0,
Q => end_brst_rd,
R => '0'
);
last_bram_addr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FAAAAAAAAAAAAFAB"
)
port map (
I0 => last_bram_addr_i_2_n_0,
I1 => last_bram_addr_i_3_n_0,
I2 => rd_data_sm_cs(2),
I3 => last_bram_addr_i_4_n_0,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => last_bram_addr0
);
last_bram_addr_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_5_n_0,
I1 => brst_cnt(0),
I2 => brst_cnt(1),
O => last_bram_addr_i_2_n_0
);
last_bram_addr_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F707F7F7F7F7F"
)
port map (
I0 => p_0_in13_in,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(3),
I3 => bram_addr_ld_en,
I4 => I_WRAP_BRST_n_4,
I5 => axi_rd_burst_i_2_n_0,
O => last_bram_addr_i_3_n_0
);
last_bram_addr_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"A888200000000000"
)
port map (
I0 => rd_adv_buf67_out,
I1 => bram_addr_ld_en,
I2 => pend_rd_op,
I3 => p_0_in13_in,
I4 => last_bram_addr_i_6_n_0,
I5 => \rd_data_sm_cs[3]_i_6_n_0\,
O => last_bram_addr_i_4_n_0
);
last_bram_addr_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => I_WRAP_BRST_n_8,
I1 => brst_cnt(7),
I2 => brst_cnt(3),
I3 => brst_cnt(4),
I4 => brst_cnt(2),
I5 => last_bram_addr_i_7_n_0,
O => last_bram_addr_i_5_n_0
);
last_bram_addr_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => last_bram_addr_i_8_n_0,
I1 => last_bram_addr_i_9_n_0,
I2 => I_WRAP_BRST_n_3,
I3 => I_WRAP_BRST_n_5,
I4 => I_WRAP_BRST_n_2,
I5 => I_WRAP_BRST_n_4,
O => last_bram_addr_i_6_n_0
);
last_bram_addr_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_cnt(6),
I1 => brst_cnt(5),
O => last_bram_addr_i_7_n_0
);
last_bram_addr_i_8: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => s_axi_arlen(4),
I1 => axi_arlen_pipe(4),
I2 => s_axi_arlen(5),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(5),
O => last_bram_addr_i_8_n_0
);
last_bram_addr_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFACCFA"
)
port map (
I0 => s_axi_arlen(6),
I1 => axi_arlen_pipe(6),
I2 => s_axi_arlen(7),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(7),
O => last_bram_addr_i_9_n_0
);
last_bram_addr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^bram_rst_a\
);
no_ar_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"88C8AAAAAAAAAAAA"
)
port map (
I0 => no_ar_ack,
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[3]_i_6_n_0\,
I5 => rd_data_sm_cs(0),
O => no_ar_ack_i_1_n_0
);
no_ar_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => no_ar_ack_i_1_n_0,
Q => no_ar_ack,
R => \^bram_rst_a\
);
pend_rd_op_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFFFEAAAA0002"
)
port map (
I0 => pend_rd_op_i_2_n_0,
I1 => pend_rd_op_i_3_n_0,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
I4 => pend_rd_op_i_4_n_0,
I5 => pend_rd_op,
O => pend_rd_op_i_1_n_0
);
pend_rd_op_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFCC8C80CCCC8C8"
)
port map (
I0 => p_0_in13_in,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => pend_rd_op_i_5_n_0,
O => pend_rd_op_i_2_n_0
);
pend_rd_op_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0303070733F3FFFF"
)
port map (
I0 => p_0_in13_in,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => \^s_axi_rlast\,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => pend_rd_op_i_3_n_0
);
pend_rd_op_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080FFD5FF"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_adv_buf67_out,
I2 => pend_rd_op,
I3 => rd_data_sm_cs(1),
I4 => pend_rd_op_i_6_n_0,
I5 => pend_rd_op_i_7_n_0,
O => pend_rd_op_i_4_n_0
);
pend_rd_op_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ar_active,
I1 => end_brst_rd,
O => pend_rd_op_i_5_n_0
);
pend_rd_op_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => bram_addr_ld_en,
I1 => end_brst_rd,
I2 => ar_active,
O => pend_rd_op_i_6_n_0
);
pend_rd_op_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"F1FF"
)
port map (
I0 => pend_rd_op_i_8_n_0,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
O => pend_rd_op_i_7_n_0
);
pend_rd_op_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFF0008888"
)
port map (
I0 => pend_rd_op,
I1 => \^s_axi_rlast\,
I2 => ar_active,
I3 => end_brst_rd,
I4 => rd_data_sm_cs(0),
I5 => rd_data_sm_cs(1),
O => pend_rd_op_i_8_n_0
);
pend_rd_op_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => pend_rd_op_i_1_n_0,
Q => pend_rd_op,
R => \^bram_rst_a\
);
\rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF54005555"
)
port map (
I0 => \rd_data_sm_cs[0]_i_2_n_0\,
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[0]_i_3_n_0\,
I5 => \rd_data_sm_cs[0]_i_4_n_0\,
O => \rd_data_sm_cs[0]_i_1_n_0\
);
\rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"E000E0E0FFFFFFFF"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
I2 => disable_b2b_brst_i_2_n_0,
I3 => bram_addr_ld_en,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_6_n_0\,
O => \rd_data_sm_cs[0]_i_2_n_0\
);
\rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[0]_i_3_n_0\
);
\rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"001100F7001100D5"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => rd_adv_buf67_out,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => p_0_in13_in,
O => \rd_data_sm_cs[0]_i_4_n_0\
);
\rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAEAAAEFFFFAAAE"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => \rd_data_sm_cs[1]_i_2_n_0\,
I2 => end_brst_rd,
I3 => brst_zero,
I4 => I_WRAP_BRST_n_25,
I5 => \rd_data_sm_cs[2]_i_4_n_0\,
O => \rd_data_sm_cs[1]_i_1_n_0\
);
\rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[1]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFEEEAEAEA"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => \rd_data_sm_cs[2]_i_3_n_0\,
I2 => \rd_data_sm_cs[2]_i_4_n_0\,
I3 => p_0_in13_in,
I4 => disable_b2b_brst_i_2_n_0,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => \rd_data_sm_cs[2]_i_1_n_0\
);
\rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000007000F000000"
)
port map (
I0 => \rd_data_sm_cs[3]_i_7_n_0\,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[2]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => \rd_data_sm_cs[2]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"C8C8C8C808C8C8C8"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => I_WRAP_BRST_n_27,
O => \rd_data_sm_cs[2]_i_4_n_0\
);
\rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0004000400040000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => brst_zero,
I5 => end_brst_rd,
O => \rd_data_sm_cs[2]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7444777730007444"
)
port map (
I0 => \rd_data_sm_cs[3]_i_3_n_0\,
I1 => \rd_data_sm_cs[3]_i_4_n_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => \rd_data_sm_cs[3]_i_5_n_0\,
I5 => bram_addr_ld_en,
O => rd_data_sm_ns
);
\rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00800000AA800000"
)
port map (
I0 => \rd_data_sm_cs[3]_i_6_n_0\,
I1 => bram_addr_ld_en,
I2 => \rd_data_sm_cs[3]_i_7_n_0\,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[3]_i_2_n_0\
);
\rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000D0000000000"
)
port map (
I0 => end_brst_rd,
I1 => axi_b2b_brst,
I2 => brst_zero,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(3),
I5 => \rd_data_sm_cs[0]_i_3_n_0\,
O => \rd_data_sm_cs[3]_i_3_n_0\
);
\rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"BFAD"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_4_n_0\
);
\rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"0053"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
O => \rd_data_sm_cs[3]_i_6_n_0\
);
\rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => act_rd_burst_two,
I3 => act_rd_burst,
O => \rd_data_sm_cs[3]_i_7_n_0\
);
\rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[0]_i_1_n_0\,
Q => rd_data_sm_cs(0),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[3]_i_2_n_0\,
Q => rd_data_sm_cs(3),
R => \^bram_rst_a\
);
rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000111111110000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => rd_skid_buf_ld_cmb
);
rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^bram_rst_a\
);
rddata_mux_sel_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => rddata_mux_sel_cmb,
I1 => rd_data_sm_cs(3),
I2 => rddata_mux_sel_i_3_n_0,
I3 => rddata_mux_sel,
O => rddata_mux_sel_i_1_n_0
);
rddata_mux_sel_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"D208D208D208F208"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => rd_adv_buf67_out,
I3 => rd_data_sm_cs(2),
I4 => act_rd_burst,
I5 => act_rd_burst_two,
O => rddata_mux_sel_cmb
);
rddata_mux_sel_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"A007AF07AF07AF07"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => rddata_mux_sel_i_3_n_0
);
rddata_mux_sel_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rddata_mux_sel_i_1_n_0,
Q => rddata_mux_sel,
R => \^bram_rst_a\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_arready_int,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => axi_early_arready_int,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
port (
axi_aresetn_d2 : out STD_LOGIC;
axi_aresetn_re_reg : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aresetn_0 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
signal BID_FIFO_n_1 : STD_LOGIC;
signal BID_FIFO_n_4 : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC;
signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC;
signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal aw_active : STD_LOGIC;
signal \^axi_aresetn_d2\ : STD_LOGIC;
signal axi_aresetn_re : STD_LOGIC;
signal \^axi_aresetn_re_reg\ : STD_LOGIC;
signal axi_awaddr_full : STD_LOGIC;
signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_awid_pipe : STD_LOGIC;
signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_awlen_pipe_1_or_2 : STD_LOGIC;
signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_cmb114_out : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_cmb : STD_LOGIC;
signal axi_wr_burst_cmb0 : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_3_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal bram_addr_inc : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 13 downto 10 );
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal bram_addr_rst_cmb : STD_LOGIC;
signal bram_en_cmb : STD_LOGIC;
signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal bvalid_cnt_inc11_out : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal clr_bram_we_cmb : STD_LOGIC;
signal curr_awlen_reg_1_or_2 : STD_LOGIC;
signal curr_awlen_reg_1_or_20 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal delay_aw_active_clr : STD_LOGIC;
signal last_data_ack_mod : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_addr_sm_cs : STD_LOGIC;
signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of wr_data_sm_cs : signal is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair53";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair51";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair50";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair50";
begin
\GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\;
axi_aresetn_d2 <= \^axi_aresetn_d2\;
axi_aresetn_re_reg <= \^axi_aresetn_re_reg\;
bram_addr_a(13 downto 0) <= \^bram_addr_a\(13 downto 0);
s_axi_awready <= \^s_axi_awready\;
s_axi_bid(0) <= \^s_axi_bid\(0);
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
BID_FIFO: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awid_pipe => axi_awid_pipe,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
\axi_bid_int_reg[0]\ => BID_FIFO_n_4,
axi_bvalid_int_reg => \^s_axi_bvalid\,
axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => BID_FIFO_n_1,
bram_addr_ld_en => bram_addr_ld_en,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
bvalid_cnt_inc => bvalid_cnt_inc,
\bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0,
\bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_20,
\bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_19,
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn_0,
s_axi_awid(0) => s_axi_awid(0),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => \^s_axi_bid\(0),
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_addr_sm_cs => wr_addr_sm_cs
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(0),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05051F1A"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => axi_wr_burst_cmb0,
I2 => wr_data_sm_cs(0),
I3 => axi_wdata_full_cmb114_out,
I4 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => I_WRAP_BRST_n_21,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
O => axi_wr_burst_cmb0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(1),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000554000555540"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => s_axi_wlast,
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(2),
I5 => axi_wr_burst,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44010001"
)
port map (
I0 => wr_data_sm_cs(2),
I1 => wr_data_sm_cs(1),
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7774777774744444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(0),
I5 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\,
Q => wr_data_sm_cs(0),
R => s_axi_aresetn_0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\,
Q => wr_data_sm_cs(1),
R => s_axi_aresetn_0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\,
Q => wr_data_sm_cs(2),
R => s_axi_aresetn_0
);
\GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_aresetn,
Q => \I_RD_CHNL/axi_aresetn_d1\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \I_RD_CHNL/axi_aresetn_d1\,
Q => \^axi_aresetn_d2\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => \I_RD_CHNL/axi_aresetn_d1\,
O => axi_aresetn_re
);
\GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_aresetn_re,
Q => \^axi_aresetn_re_reg\,
R => '0'
);
\GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBFFFFFAA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => bram_addr_ld_en,
I4 => \^axi_aresetn_re_reg\,
I5 => \^s_axi_awready\,
O => \GEN_AWREADY.axi_awready_int_i_1_n_0\
);
\GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5444444400000000"
)
port map (
I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\,
I1 => aw_active,
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => s_axi_awvalid,
O => \GEN_AWREADY.axi_awready_int_i_2_n_0\
);
\GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABABABABABABA"
)
port map (
I0 => wr_addr_sm_cs,
I1 => I_WRAP_BRST_n_21,
I2 => last_data_ack_mod,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \GEN_AWREADY.axi_awready_int_i_3_n_0\
);
\GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AWREADY.axi_awready_int_i_1_n_0\,
Q => \^s_axi_awready\,
R => s_axi_aresetn_0
);
\GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi_aresetn_d2\,
O => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFF0000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => wr_data_sm_cs(2),
I3 => delay_aw_active_clr,
I4 => bram_addr_ld_en,
I5 => aw_active,
O => \GEN_AW_DUAL.aw_active_i_2_n_0\
);
\GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.aw_active_i_2_n_0\,
Q => aw_active,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => p_18_out
);
\GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_18_out,
Q => last_data_ack_mod,
R => s_axi_aresetn_0
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000100000"
)
port map (
I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\,
I1 => wr_addr_sm_cs,
I2 => s_axi_awvalid,
I3 => axi_awaddr_full,
I4 => I_WRAP_BRST_n_20,
I5 => aw_active,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => I_WRAP_BRST_n_20,
I1 => last_data_ack_mod,
I2 => axi_awaddr_full,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => axi_awlen_pipe_1_or_2,
I5 => curr_awlen_reg_1_or_2,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\,
Q => wr_addr_sm_cs,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(8),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(9),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(10),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(11),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(12),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(13),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(0),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(1),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(2),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(3),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(4),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(5),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(6),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(7),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000EA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => s_axi_aresetn,
I4 => bram_addr_ld_en,
O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\,
Q => axi_awaddr_full,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00FF40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(0),
Q => axi_awburst_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(1),
Q => axi_awburst_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(0),
Q => axi_awid_pipe,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(1),
O => p_9_out
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awlen(6),
I2 => s_axi_awlen(7),
I3 => s_axi_awlen(5),
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => p_9_out,
Q => axi_awlen_pipe_1_or_2,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(0),
Q => axi_awlen_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(1),
Q => axi_awlen_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(2),
Q => axi_awlen_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(3),
Q => axi_awlen_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(4),
Q => axi_awlen_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(5),
Q => axi_awlen_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(6),
Q => axi_awlen_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(7),
Q => axi_awlen_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => '1',
Q => axi_awsize_pipe(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WRAP_BRST_n_17,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => s_axi_wvalid,
O => bram_addr_inc
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => wr_data_sm_cs(1),
O => bram_addr_rst_cmb
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_8,
Q => \^bram_addr_a\(8),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_7,
Q => \^bram_addr_a\(9),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(10),
Q => \^bram_addr_a\(10),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(11),
Q => \^bram_addr_a\(11),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(12),
Q => \^bram_addr_a\(12),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(13),
Q => \^bram_addr_a\(13),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_16,
Q => \^bram_addr_a\(0),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_15,
Q => \^bram_addr_a\(1),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_14,
Q => \^bram_addr_a\(2),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_13,
Q => \^bram_addr_a\(3),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_12,
Q => \^bram_addr_a\(4),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_11,
Q => \^bram_addr_a\(5),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_10,
Q => \^bram_addr_a\(6),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_9,
Q => \^bram_addr_a\(7),
R => I_WRAP_BRST_n_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15FF1500"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => s_axi_aresetn_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4777477444444444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => s_axi_wvalid,
O => bram_en_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_cmb,
Q => bram_en_a,
R => s_axi_aresetn_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000101110"
)
port map (
I0 => wr_data_sm_cs(0),
I1 => wr_data_sm_cs(1),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I5 => axi_wr_burst,
O => clr_bram_we_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => clr_bram_we_cmb,
Q => clr_bram_we,
R => s_axi_aresetn_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAFEFF02AA0200"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\,
I1 => axi_wr_burst,
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\,
I5 => delay_aw_active_clr,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222E"
)
port map (
I0 => s_axi_wlast,
I1 => wr_data_sm_cs(2),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(1),
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B338B0088008800"
)
port map (
I0 => delay_aw_active_clr,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => bvalid_cnt_inc11_out,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_wlast,
O => bvalid_cnt_inc11_out
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\,
Q => delay_aw_active_clr,
R => s_axi_aresetn_0
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => clr_bram_we,
I3 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(0),
Q => bram_we_a(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(1),
Q => bram_we_a(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(2),
Q => bram_we_a(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(3),
Q => bram_we_a(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst
port map (
D(13 downto 10) => bram_addr_ld(13 downto 10),
D(9) => I_WRAP_BRST_n_7,
D(8) => I_WRAP_BRST_n_8,
D(7) => I_WRAP_BRST_n_9,
D(6) => I_WRAP_BRST_n_10,
D(5) => I_WRAP_BRST_n_11,
D(4) => I_WRAP_BRST_n_12,
D(3) => I_WRAP_BRST_n_13,
D(2) => I_WRAP_BRST_n_14,
D(1) => I_WRAP_BRST_n_15,
D(0) => I_WRAP_BRST_n_16,
E(0) => I_WRAP_BRST_n_2,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_17,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\,
Q(3 downto 0) => axi_awlen_pipe(3 downto 0),
SR(0) => I_WRAP_BRST_n_0,
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_awsize_pipe(0) => axi_awsize_pipe(1),
bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0),
bram_addr_inc => bram_addr_inc,
bram_addr_ld_en => bram_addr_ld_en,
bram_addr_ld_en_mod => bram_addr_ld_en_mod,
bram_addr_rst_cmb => bram_addr_rst_cmb,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
curr_fixed_burst => curr_fixed_burst,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_fixed_burst_reg_reg => I_WRAP_BRST_n_24,
curr_wrap_burst => curr_wrap_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
curr_wrap_burst_reg_reg => I_WRAP_BRST_n_25,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => s_axi_aresetn_0,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_19,
\save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_20,
\save_init_bram_addr_ld_reg[15]_2\ => I_WRAP_BRST_n_21,
wr_addr_sm_cs => wr_addr_sm_cs,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_22,
\wrap_burst_total_reg[2]_0\ => I_WRAP_BRST_n_23
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => BID_FIFO_n_4,
Q => \^s_axi_bid\(0),
R => s_axi_aresetn_0
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAA8A88"
)
port map (
I0 => s_axi_aresetn,
I1 => bvalid_cnt_inc,
I2 => BID_FIFO_n_1,
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => bvalid_cnt(1),
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^s_axi_bvalid\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_wr_burst_cmb,
I1 => axi_wr_burst_i_3_n_0,
I2 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"3088FCBB"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wlast,
O => axi_wr_burst_cmb
);
axi_wr_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA222"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(0),
I2 => axi_wr_burst_cmb0,
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(1),
I5 => wr_data_sm_cs(2),
O => axi_wr_burst_i_3_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => s_axi_aresetn_0
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EAFF00000000"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
I5 => s_axi_aresetn,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F8F9F0F0"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => axi_wdata_full_reg,
I3 => axi_wdata_full_cmb114_out,
I4 => s_axi_wvalid,
O => axi_wready_int_mod_i_3_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => s_axi_aresetn_0
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"95956A6A95956AAA"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5BFBF2A2A4000"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D52AFF00FF00BF00"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[0]_i_1_n_0\,
Q => bvalid_cnt(0),
R => s_axi_aresetn_0
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[1]_i_1_n_0\,
Q => bvalid_cnt(1),
R => s_axi_aresetn_0
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[2]_i_1_n_0\,
Q => bvalid_cnt(2),
R => s_axi_aresetn_0
);
curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000151"
)
port map (
I0 => I_WRAP_BRST_n_23,
I1 => s_axi_awlen(2),
I2 => axi_awaddr_full,
I3 => axi_awlen_pipe(2),
I4 => I_WRAP_BRST_n_22,
I5 => curr_awlen_reg_1_or_2_i_2_n_0,
O => curr_awlen_reg_1_or_20
);
curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F5F5F5F5F5F5F5C5"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => axi_awlen_pipe(5),
I2 => axi_awaddr_full,
I3 => axi_awlen_pipe(6),
I4 => axi_awlen_pipe(7),
I5 => axi_awlen_pipe(4),
O => curr_awlen_reg_1_or_2_i_2_n_0
);
curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_awlen_reg_1_or_20,
Q => curr_awlen_reg_1_or_2,
R => s_axi_aresetn_0
);
curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_24,
Q => curr_fixed_burst_reg,
R => '0'
);
curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_25,
Q => curr_wrap_burst_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
signal I_WR_CHNL_n_36 : STD_LOGIC;
signal axi_aresetn_d2 : STD_LOGIC;
signal axi_aresetn_re_reg : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
begin
bram_rst_a <= \^bram_rst_a\;
I_RD_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36,
Q(13 downto 0) => bram_addr_b(13 downto 0),
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
I_WR_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl
port map (
\GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36,
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_en_a => bram_en_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0 => \^bram_rst_a\,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi
port map (
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_addr_b(13 downto 0) => bram_addr_b(13 downto 0),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 1;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_rst_a\ : STD_LOGIC;
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(15 downto 2) <= \^bram_addr_a\(15 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(15 downto 2) <= \^bram_addr_b\(15 downto 2);
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \^s_axi_aclk\;
bram_rst_a <= \^bram_rst_a\;
bram_rst_b <= \^bram_rst_a\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top
port map (
bram_addr_a(13 downto 0) => \^bram_addr_a\(15 downto 2),
bram_addr_b(13 downto 0) => \^bram_addr_b\(15 downto 2),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(13 downto 0) => s_axi_araddr(15 downto 2),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => s_axi_arid(0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(15 downto 2),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(0) => s_axi_awid(0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => s_axi_bid(0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => s_axi_rid(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_bram_ctrl,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 1;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl
port map (
bram_addr_a(15 downto 0) => bram_addr_a(15 downto 0),
bram_addr_b(15 downto 0) => bram_addr_b(15 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => bram_clk_b,
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_rst_b => bram_rst_b,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => bram_we_b(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(15 downto 0) => s_axi_araddr(15 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(0) => '0',
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(15 downto 0) => s_axi_awaddr(15 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(0) => '0',
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 7d569fa05c004ace5ab593c0d8a9961a | 0.550666 | 2.566114 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-digilent-xc3s1000/config.vhd | 1 | 5,267 |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 8;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 1;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#00F0#;
constant CFG_GRGPIO_WIDTH : integer := (18);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
| gpl-2.0 | 5a139e809ffbe0eb2eae53d0696e7e36 | 0.64325 | 3.662726 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-de2-ep2c35/testbench.vhd | 1 | 8,561 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romdepth : integer := 22 -- rom address depth (flash 4 MB)
-- sramwidth : integer := 32; -- ram data width (8/16/32)
-- sramdepth : integer := 20; -- ram address depth
-- srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(21 downto 0);
signal data : std_logic_vector(31 downto 24);
signal romsn : std_logic;
signal oen : std_logic;
signal writen : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_logic;
signal dsurst : std_logic;
signal error : std_logic;
signal gpio_0 : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal gpio_1 : std_logic_vector(CFG_GRGPIO2_WIDTH-1 downto 0);
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal dram_ldqm : std_logic;
signal dram_udqm : std_logic;
signal sdclk : std_logic;
signal sw : std_logic_vector(0 to 2);
signal ps2_clk : std_logic;
signal ps2_dat : std_logic;
signal vga_clk : std_ulogic;
signal vga_blank : std_ulogic;
signal vga_sync : std_ulogic;
signal vga_hs : std_ulogic;
signal vga_vs : std_ulogic;
signal vga_r : std_logic_vector(9 downto 0);
signal vga_g : std_logic_vector(9 downto 0);
signal vga_b : std_logic_vector(9 downto 0);
constant lresp : boolean := false;
signal sa : std_logic_vector(13 downto 0);
signal sd : std_logic_vector(15 downto 0);
begin
clk <= not clk after ct * 1 ns; --50 MHz clk
rst <= dsurst; --reset
dsuen <= '1';
dsubre <= '1'; -- inverted on the board
sw(0) <= '1';
gpio_0(CFG_GRGPIO_WIDTH-1 downto 0) <= (others => 'H');
gpio_1(CFG_GRGPIO2_WIDTH-1 downto 0) <= (others => 'H');
d3 : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
port map (rst, clk, error, address(21 downto 0), data,
sa(11 downto 0), sa(12), sa(13), sd, sdclk, sdcke, sdcsn, sdwen,
sdrasn, sdcasn, dram_ldqm, dram_udqm, dsutx, dsurx, dsubre, dsuact,
oen, writen, open, romsn, open, open, open, open, open, open, gpio_0, gpio_1,
ps2_clk, ps2_dat, vga_clk, vga_blank, vga_sync, vga_hs, vga_vs, vga_r,
vga_g, vga_b, sw);
sd1 : if (CFG_SDCTRL = 1) generate
u1: entity work.mt48lc16m16a2 generic map (addr_bits => 12, col_bits => 8, index => 1024, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(11 downto 0),
Ba => sa(13 downto 12), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm(0) => dram_ldqm, Dqm(1) => dram_udqm );
end generate;
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data) after 5 ns;
sd <= buskeep(sd) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0'; --reset low
wait for 500 ns;
dsurst <= '1'; --reset high
wait; --evig w8
wait for 5000 ns;
txc(dsutx, 16#55#, txp);
-- txc(dsutx, 16#c0#, txp); --control byte
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp); --adress
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp); --write data
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 168181cd381d5e5382ee10b4da830a43 | 0.579372 | 3.078389 | false | false | false | false |
khaledhassan/vhdl-examples | adder_tree/adder_tree.vhd | 1 | 7,515 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Adder tree (generic)
-- Recursively generate a tree of adders in order to add a large amount of numbers
-- together. The height of the tree is 1+ceil(log2(TOPWIDTH)).
-- Imagine it looking like an "inverted triangle" to get an idea of the nodes
-- that this code generates.
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity adder_tree is
generic (
WIDTH : positive := 8;
TOPWIDTH : positive := 4
);
port (
rst : in std_logic;
clk : in std_logic;
input : in std_logic_vector(TOPWIDTH*WIDTH-1 downto 0);
output : out std_logic_vector(WIDTH-1 downto 0);
valid_in : in std_logic;
valid_out : out std_logic
);
end adder_tree;
architecture STR of adder_tree is
signal valid : std_logic;
begin
-- Delay the valid bit by one cycle for each level in the pipeline
U_VALID : entity work.reg
port map (
rst => rst,
clk => clk,
d(0) => valid_in,
q(0) => valid
);
-- Base case
BASE_CASE : if TOPWIDTH = 2 generate
signal register_input : std_logic_vector(WIDTH-1 downto 0);
begin
-- Valid bit
valid_out <= valid;
-- Adder
U_ADDER : entity work.adder
generic map (
WIDTH => WIDTH
)
port map (
input1 => input(TOPWIDTH*WIDTH-1 downto WIDTH),
input2 => input(WIDTH-1 downto 0),
c_in => '0',
output => register_input,
c_out => open
);
-- Vector of Registers
U_FFV : entity work.reg
generic map (
WIDTH => WIDTH
)
port map (
rst => rst,
clk => clk,
d => register_input,
q => output
);
end generate BASE_CASE;
-- Recursive case for even inputs
RECURSIVE_CASE_EVEN : if (TOPWIDTH > 2 and (TOPWIDTH mod 2) = 0) generate
signal register_input, register_output : std_logic_vector((TOPWIDTH/2)*WIDTH-1 downto 0);
begin
-- Slice off a line of values from the top of the tree and sum them up
U_ADDERS : for i in TOPWIDTH/2-1 downto 0 generate
U_ADDER : entity work.adder
generic map (
WIDTH => WIDTH
)
port map (
input1 => input(((i*2)*WIDTH)+(WIDTH-1) downto (i*2)*WIDTH),
input2 => input(((i*2+1)*WIDTH)+(WIDTH-1) downto (i*2+1)*WIDTH),
c_in => '0',
output => register_input((i*WIDTH)+(WIDTH-1) downto i*WIDTH),
c_out => open
);
U_FFV : entity work.reg
generic map (
WIDTH => WIDTH
)
port map (
rst => rst,
clk => clk,
d => register_input((i*WIDTH)+(WIDTH-1) downto i*WIDTH),
q => register_output((i*WIDTH)+(WIDTH-1) downto i*WIDTH)
);
end generate U_ADDERS;
-- The remaining triangle becomes its own adder tree
U_SUBTREE : entity work.adder_tree
generic map (
WIDTH => WIDTH,
TOPWIDTH => TOPWIDTH/2
)
port map (
rst => rst,
clk => clk,
input => register_output,
output => output,
valid_in => valid,
valid_out => valid_out
);
end generate RECURSIVE_CASE_EVEN;
-- Recursive case for odd inputs
RECURSIVE_CASE_ODD : if (TOPWIDTH > 2 and (TOPWIDTH mod 2) = 1) generate
constant TREEHEIGHT : integer := integer(ceil(log2(real(TOPWIDTH))));
signal base_case : std_logic_vector(WIDTH*2-1 downto 0);
signal delay_chain : std_logic_vector((TREEHEIGHT+1)*WIDTH-1 downto 0);
signal valid2 : std_logic;
begin
-- Take the odd value out and push it down to the bottom of the tree
-- The number of delays is equal to the height of the tree (minus 1)
-- The height of the tree is 1+ceil(log2(N)) where N is the number
-- of registers wide the top row is.
U_FFV_DELAYCHAIN : for i in TREEHEIGHT downto 1 generate
U_FFV : entity work.reg
generic map (
WIDTH => WIDTH
)
port map (
rst => rst,
clk => clk,
d => delay_chain((i+1)*WIDTH-1 downto ((i+1)*WIDTH-1)-(WIDTH-1)),
q => delay_chain(i*WIDTH-1 downto (i*WIDTH-1)-(WIDTH-1))
);
end generate U_FFV_DELAYCHAIN;
-- Provide a source for the first register in the delay chain
delay_chain((TREEHEIGHT+1)*WIDTH-1 downto ((TREEHEIGHT+1)*WIDTH-1)-(WIDTH-1)) <= input(WIDTH-1 downto 0);
-- Rename the output of the last register in the delay chain
base_case(WIDTH-1 downto 0) <= delay_chain(WIDTH-1 downto 0);
-- The rest of the values are an even case
U_SUBTREE : entity work.adder_tree
generic map (
WIDTH => WIDTH,
TOPWIDTH => TOPWIDTH-1
)
port map (
rst => rst,
clk => clk,
input => input(TOPWIDTH*WIDTH-1 downto WIDTH),
output => base_case(WIDTH*2-1 downto WIDTH),
valid_in => valid,
valid_out => valid2
);
-- Extra base case to add in the odd value
U_EXTRABASE : entity work.adder_tree
generic map (
WIDTH => WIDTH,
TOPWIDTH => 2
)
port map (
rst => rst,
clk => clk,
input => base_case,
output => output,
valid_in => valid2,
valid_out => valid_out
);
end generate RECURSIVE_CASE_ODD;
end STR;
| mit | ad356090b4ed360f43141b58a9395c8a | 0.527611 | 4.286937 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/cpu_disas_net.vhd | 1 | 4,505 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: cpu_disas_net
-- File: cpu_disas_net.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: SPARC disassembler according to SPARC V8 manual
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity cpu_disas_net is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
inst : in std_logic_vector(31 downto 0);
pc : in std_logic_vector(31 downto 2);
result: in std_logic_vector(31 downto 0);
index : in std_logic_vector(3 downto 0);
wreg : in std_ulogic;
annul : in std_ulogic;
holdn : in std_ulogic;
pv : in std_ulogic;
trap : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of cpu_disas_net is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
op := inst(31 downto 30); op3 := inst(24 downto 19);
fpins := (op = FMT3) and ((op3 = FPOP1) or (op3 = FPOP2));
fpld := (op = LDST) and ((op3 = LDF) or (op3 = LDDF) or (op3 = LDFSR));
valid := (((not annul) and pv) = '1') and (not ((fpins or fpld) and (trap = '0')));
valid := valid and (holdn = '1');
if rising_edge(clk) and (rstn = '1') and (disas = '1') then
print_insn (iindex, pc(31 downto 2) & "00", inst,
result, valid, trap = '1', wreg = '1', false);
end if;
end process;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library grlib;
use grlib.stdlib.all;
use grlib.sparc.all;
use grlib.sparc_disas.all;
-- pragma translate_on
entity fpu_disas_net is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
dummy : out std_ulogic;
wr2inst : in std_logic_vector(31 downto 0);
wr2pc : in std_logic_vector(31 downto 2);
divinst : in std_logic_vector(31 downto 0);
divpc : in std_logic_vector(31 downto 2);
dbg_wrdata: in std_logic_vector(63 downto 0);
index : in std_logic_vector(3 downto 0);
dbg_wren : in std_logic_vector(1 downto 0);
resv : in std_ulogic;
ld : in std_ulogic;
rdwr : in std_ulogic;
ccwr : in std_ulogic;
rdd : in std_ulogic;
div_valid : in std_ulogic;
holdn : in std_ulogic;
disas : in std_ulogic);
end;
architecture behav of fpu_disas_net is
begin
dummy <= '1';
-- pragma translate_off
trc : process(clk)
variable valid : boolean;
variable op : std_logic_vector(1 downto 0);
variable op3 : std_logic_vector(5 downto 0);
variable fpins, fpld : boolean;
variable iindex : integer;
begin
iindex := conv_integer(index);
if rising_edge(clk) and (rstn = '1') and (disas /= '0') then
valid := ((((rdwr and not ld) or ccwr or (ld and resv)) and holdn) = '1');
print_fpinsn(0, wr2pc(31 downto 2) & "00", wr2inst, dbg_wrdata,
(rdd = '1'), valid, false, (dbg_wren /= "00"));
print_fpinsn(0, divpc(31 downto 2) & "00", divinst, dbg_wrdata,
(rdd = '1'), (div_valid and holdn) = '1', false, (dbg_wren /= "00"));
end if;
end process;
-- pragma translate_on
end;
| gpl-2.0 | 81fda35f0f80220a9c3572e3831b2d51 | 0.607991 | 3.433689 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-sp601/leon3mp.vhd | 1 | 24,173 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
reset_o1 : out std_ulogic;
reset_o2 : out std_ulogic;
clk27 : in std_ulogic;
clk200_p : in std_ulogic;
clk200_n : in std_ulogic;
errorn : out std_ulogic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(7 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(23 downto 0);
-- pragma translate_on
-- DDR2 memory
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_cke : out std_logic;
ddr_we : out std_ulogic; -- write enable
ddr_ras : out std_ulogic; -- ras
ddr_cas : out std_ulogic; -- cas
ddr_dm : out std_logic_vector(1 downto 0); -- dm
ddr_dqs : inout std_logic_vector(1 downto 0); -- dqs
ddr_dqsn : inout std_logic_vector(1 downto 0); -- dqsn
ddr_ad : out std_logic_vector(12 downto 0); -- address
ddr_ba : out std_logic_vector(2 downto 0); -- bank address
ddr_dq : inout std_logic_vector(15 downto 0); -- data
ddr_odt : out std_logic;
ddr_rzq : inout std_logic;
ddr_zio : inout std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
-- SPI flash
-- spi_sel_n : inout std_ulogic;
-- spi_clk : out std_ulogic;
-- spi_mosi : out std_ulogic;
-- Output signals to LEDs
led : out std_logic_vector(2 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal ddr_clk_fb_out : std_logic;
signal ddr_clk_fb : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal lclk, lclk200 : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 27000; -- CLK input frequency in KHz
constant DDR2_FREQ : integer := 200000; -- DDR2 input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
-- Glitch free reset that can be used for the Eth Phy and flash memory
reset_o1 <= rstn;
reset_o2 <= rstn;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk27_pad : clkpad generic map (tech => padtech) port map (clk27, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH,
nahbs => 8, devid => XILINX_SP601)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "00";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 24)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : iopadv generic map (tech => padtech, width => 24)
port map (testdata(23 downto 0), memo.data(23 downto 0),
memo.bdrive(1), memi.data(23 downto 0));
-- pragma translate_on
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2sp0 : if (CFG_DDR2SP /= 0) generate
clk200_pad : inpad_ds generic map (tech => padtech, voltage => x25v)
port map (clk200_p, clk200_n, lclk200);
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR2_FREQ/1000, clkmul => 5, clkdiv => 8,
TRFC => CFG_DDR2SP_TRFC,
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
ddrbits => 16, eightbanks => 1, odten => 0)
port map ( cgo.clklock, rstn, lclk200, clkm, vcc, lock, clkml, clkml, ahbsi, ahbso(4),
core_ddr_clk, core_ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, core_ddr_cke,
core_ddr_csb, ddr_we, ddr_ras, ddr_cas, ddr_dm, ddr_dqs, ddr_dqsn,
core_ddr_ad, ddr_ba, ddr_dq, core_ddr_odt);
ddr_clk <= core_ddr_clk(0);
ddr_clkb <= core_ddr_clkb(0);
ddr_cke <= core_ddr_cke(0);
ddr_ad <= core_ddr_ad(12 downto 0);
ddr_odt <= core_ddr_odt(0);
end generate;
mig_gen : if (CFG_MIG_DDR2 = 1) generate
ddrc : entity work.ahb2mig_sp601 generic map(
hindex => 4, haddr => 16#400#, hmask => 16#F80#,
pindex => 5, paddr => 5)
port map(
mcb3_dram_dq => ddr_dq,
mcb3_dram_a => ddr_ad,
mcb3_dram_ba => ddr_ba,
mcb3_dram_ras_n => ddr_ras,
mcb3_dram_cas_n => ddr_cas,
mcb3_dram_we_n => ddr_we,
mcb3_dram_odt => ddr_odt,
mcb3_dram_cke => ddr_cke,
mcb3_dram_dm => ddr_dm(0),
mcb3_dram_udqs => ddr_dqs(1),
mcb3_dram_udqs_n => ddr_dqsn(1),
mcb3_rzq => ddr_rzq,
mcb3_zio => ddr_zio,
mcb3_dram_udm => ddr_dm(1),
mcb3_dram_dqs => ddr_dqs(0),
mcb3_dram_dqs_n => ddr_dqsn(0),
mcb3_dram_ck => ddr_clk,
mcb3_dram_ck_n => ddr_clkb,
ahbsi => ahbsi,
ahbso => ahbso(4),
apbi => apbi,
apbo => apbo(5),
calib_done => lock,
rst_n_syn => rstn,
rst_n_async => rstraw,
clk_amba => clkm,
clk_mem_n => clk200_n,
clk_mem_p => clk200_p,
test_error => open
);
end generate;
noddr : if (CFG_DDR2SP+CFG_MIG_DDR2) = 0 generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
-- spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
-- spimctrl0 : spimctrl -- SPI Memory Controller
-- generic map (hindex => 7, hirq => 11, faddr => 16#e00#, fmask => 16#ff8#,
-- ioaddr => 16#002#, iomask => 16#fff#,
-- spliten => CFG_SPLIT, oepol => 0,
-- sdcard => CFG_SPIMCTRL_SDCARD,
-- readcmd => CFG_SPIMCTRL_READCMD,
-- dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
-- dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
-- scaler => CFG_SPIMCTRL_SCALER,
-- altscaler => CFG_SPIMCTRL_ASCALER,
-- pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
-- port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
--
-- -- MISO is shared with Flash data 0
-- spmi.miso <= memi.data(24);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, spmo.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spmo.sck);
-- slvsel0_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, spmo.csn);
-- end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
-- spi1 : spictrl
-- generic map (pindex => 7, paddr => 7, pmask => 16#fff#, pirq => 11,
-- fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
-- slvselsz => CFG_SPICTRL_SLVS, odmode => 0)
-- port map (rstn, clkm, apbi, apbo(7), spii, spio, slvsel);
-- spii.spisel <= '1'; -- Master only
-- -- MISO is shared with Flash data 0
-- spii.miso <= memi.data(24);
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, spio.mosi);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, spio.sck);
-- slvsel_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, slvsel(0));
-- end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
-- mosi_pad : outpad generic map (tech => padtech)
-- port map (spi_mosi, gnd);
-- sck_pad : outpad generic map (tech => padtech)
-- port map (spi_clk, gnd);
-- slvsel_pad : odpad generic map (tech => padtech)
-- port map (spi_sel_n, vcc);
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (erxd, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (etxd, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Spartan6 SP601 board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
| gpl-2.0 | e845924b86d6e94f14f1d31bd3d9996b | 0.531088 | 3.675943 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_2/syn/vhdl/convolve_kernel_fbkb.vhd | 1 | 3,167 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fbkb is
generic (
ID : integer := 7;
NUM_STAGE : integer := 9;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fbkb is
--------------------- Component ---------------------
component convolve_kernel_ap_fadd_7_full_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fadd_7_full_dsp_32_u : component convolve_kernel_ap_fadd_7_full_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | 60c3dbe884d29d1102f5dbad690a7002 | 0.467635 | 3.743499 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/spi/spictrlx.vhd | 1 | 73,502 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spictrlx
-- File: spictrlx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Auto mode: J. Andersson, J. Ekergarn - Aeroflex Gaisler AB
-- Contact: [email protected]
--
-- Description: SPI controller with an interface compatible with MPC83xx SPI.
-- Relies on APB's wait state between back-to-back transfers.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.spi.all;
entity spictrlx is
generic (
rev : integer := 0; -- Core revision
fdepth : integer range 1 to 7 := 1; -- FIFO depth is 2^fdepth
slvselen : integer range 0 to 1 := 0; -- Slave select register enable
slvselsz : integer range 1 to 32 := 1; -- Number of slave select signals
oepol : integer range 0 to 1 := 0; -- Output enable polarity
odmode : integer range 0 to 1 := 0; -- Support open drain mode, only
-- set if pads are i/o or od pads.
automode : integer range 0 to 1 := 0; -- Enable automated transfer mode
acntbits : integer range 1 to 32 := 32; -- # Bits in am period counter
aslvsel : integer range 0 to 1 := 0; -- Automatic slave select
twen : integer range 0 to 1 := 1; -- Enable three wire mode
maxwlen : integer range 0 to 15 := 0; -- Maximum word length;
syncram : integer range 0 to 1 := 1; -- Use SYNCRAM for buffers
memtech : integer range 0 to NTECH := 0; -- Memory technology
ft : integer range 0 to 2 := 0; -- Fault-Tolerance
scantest : integer range 0 to 1 := 0; -- Scan test support
syncrst : integer range 0 to 1 := 0; -- Use only sync reset
automask0 : integer := 0; -- Mask 0 for automated transfers
automask1 : integer := 0; -- Mask 1 for automated transfers
automask2 : integer := 0; -- Mask 2 for automated transfers
automask3 : integer := 0; -- Mask 3 for automated transfers
ignore : integer range 0 to 1 := 0 -- Ignore samples
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spii_ignore : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0)
);
attribute sync_set_reset of rstn : signal is "true";
end entity spictrlx;
architecture rtl of spictrlx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant OUTPUT : std_ulogic := OEPOL_LEVEL; -- Enable outputs
constant INPUT : std_ulogic := not OEPOL_LEVEL; -- Tri-state outputs
constant FIFO_DEPTH : integer := 2**fdepth;
constant SLVSEL_EN : integer := slvselen;
constant SLVSEL_SZ : integer := slvselsz;
constant ASEL_EN : integer := aslvsel * slvselen;
constant AM_EN : integer := automode;
constant AM_CNT_BITS : integer := acntbits;
constant OD_EN : integer := odmode;
constant TW_EN : integer := twen;
constant MAX_WLEN : integer := maxwlen;
constant AM_MSK1_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 32;
constant AM_MSK2_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 64;
constant AM_MSK3_EN : boolean := AM_EN = 1 and FIFO_DEPTH > 96;
constant FIFO_BITS : integer := fdepth;
constant APBBITS : integer := 6+3*AM_EN;
constant APBH : integer := 2+APBBITS-1;
constant CAP_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(0, APBBITS);
constant MODE_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(8, APBBITS);
constant EVENT_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(9, APBBITS);
constant MASK_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(10, APBBITS);
constant COM_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(11, APBBITS);
constant TD_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(12, APBBITS);
constant RD_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(13, APBBITS);
constant SLVSEL_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(14, APBBITS);
constant ASEL_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(15, APBBITS);
constant AMCFG_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(16, APBBITS);
constant AMPER_ADDR : std_logic_vector(APBH downto 2) := conv_std_logic_vector(17, APBBITS);
constant AMMSK0_ADDR : std_logic_vector(10 downto 2) := "000010100"; -- 0x050
constant AMMSK1_ADDR : std_logic_vector(10 downto 2) := "000010101"; -- 0x054
constant AMMSK2_ADDR : std_logic_vector(10 downto 2) := "000010110"; -- 0x058
constant AMMSK3_ADDR : std_logic_vector(10 downto 2) := "000010111"; -- 0x05C
constant AMTX_ADDR : std_logic_vector(10 downto 2) := "010000000"; -- 0x200
constant AMRX_ADDR : std_logic_vector(10 downto 2) := "100000000"; -- 0x40
constant SPICTRLCAPREG : std_logic_vector(31 downto 0) :=
conv_std_logic_vector(SLVSEL_SZ, 8) & conv_std_logic_vector(MAX_WLEN, 4) &
conv_std_logic_vector(TW_EN, 1) & conv_std_logic_vector(AM_EN, 1) &
conv_std_logic_vector(ASEL_EN, 1) & conv_std_logic_vector(SLVSEL_EN, 1) &
conv_std_logic_vector(FIFO_DEPTH, 8) & conv_std_logic(syncram = 1) &
conv_std_logic_vector(ft, 2) & conv_std_logic_vector(rev, 5);
-- Returns an integer containing the maximum characted length - 1 as
-- restricted by the maxwlen VHDL generic.
function wlen return integer is
begin -- maxwlen
if MAX_WLEN = 0 then return 31; end if;
return MAX_WLEN;
end wlen;
constant PROG_AM_MASK : boolean :=
AM_EN = 1 and automask0 = 0 and (automask1 = 0 or FIFO_DEPTH <= 32) and
(automask2 = 0 or FIFO_DEPTH <= 64) and (automask3 = 0 or FIFO_DEPTH <= 96);
constant AM_MASK : std_logic_vector(127 downto 0) :=
conv_std_logic_vector_signed(automask3,32) &
conv_std_logic_vector_signed(automask2,32) &
conv_std_logic_vector_signed(automask1,32) &
conv_std_logic_vector_signed(automask0,32);
function check_discont_am_mask return boolean is
variable foundzero : boolean;
begin
if AM_EN = 0 then
return false;
elsif PROG_AM_MASK then
return true;
else
foundzero := false;
for i in 0 to FIFO_DEPTH-1 loop
if AM_MASK(i) = '0' then
foundzero := true;
else
if foundzero then
return true;
end if;
end if;
end loop;
return false;
end if;
end function;
constant DISCONT_AM_MASK : boolean := check_discont_am_mask;
function check_am_mask_end return integer is
variable ret : integer;
begin
ret := 0;
for i in 0 to FIFO_DEPTH-1 loop
if AM_MASK(i) = '1' then
ret := i;
end if;
end loop;
return ret;
end function;
constant AM_MASK_END : integer := check_am_mask_end;
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type spi_mode_rec is record -- SPI Mode register
amen : std_ulogic;
loopb : std_ulogic; -- loopback mode
cpol : std_ulogic; -- clock polarity
cpha : std_ulogic; -- clock phase
div16 : std_ulogic; -- Divide by 16
rev : std_ulogic; -- Reverse data mode
ms : std_ulogic; -- Master/slave
en : std_ulogic; -- Enable SPI
len : std_logic_vector(3 downto 0); -- Bits per character
pm : std_logic_vector(3 downto 0); -- Prescale modulus
tw : std_ulogic; -- 3-wire mode
asel : std_ulogic; -- Automatic slave select
fact : std_ulogic; -- PM multiplication factor
od : std_ulogic; -- Open drain mode
cg : std_logic_vector(4 downto 0); -- Clock gap
aseldel : std_logic_vector(1 downto 0); -- Asel delay
tac : std_ulogic;
tto : std_ulogic; -- Three-wire mode word order
igsel : std_ulogic; -- Ignore spisel input
cite : std_ulogic; -- Require SCK = CPOL for TIP end
end record;
type spi_em_rec is record -- SPI Event and Mask registers
tip : std_ulogic; -- Transfer in progress/Clock generated
lt : std_ulogic; -- last character transmitted
ov : std_ulogic; -- slave/master overrun
un : std_ulogic; -- slave/master underrun
mme : std_ulogic; -- Multiple-master error
ne : std_ulogic; -- Not empty
nf : std_ulogic; -- Not full
at : std_ulogic; -- Automated transfer
end record;
type spi_fifo is array (0 to (1-syncram)*(FIFO_DEPTH-1)) of std_logic_vector(wlen downto 0);
type spi_amcfg_rec is record -- AM config register
seq : std_ulogic; -- Data must always be read out of receive queue
strict : std_ulogic; -- Strict period
ovtb : std_ulogic; -- Perform transfer on OV
ovdb : std_ulogic; -- Skip data on OV
act : std_ulogic; -- Start immediately
eact : std_ulogic; -- Activate on external event
erpt : std_ulogic; -- Repeat on external event, not on period done
lock : std_ulogic; -- Lock receive registers when reading data
ecgc : std_ulogic; -- External clock gap control
end record;
type spi_am_rec is record -- Automode state
-- Register interface
cfg : spi_amcfg_rec; -- AM config register
per : std_logic_vector((AM_CNT_BITS-1)*AM_EN downto 0); -- AM period
--
active : std_ulogic; -- Auto mode active
lock : std_ulogic;
cnt : unsigned((AM_CNT_BITS-1)*AM_EN downto 0);
--
skipdata : std_ulogic;
rxfull : std_ulogic; -- AM RX FIFO is filled
rxfifo : spi_fifo; -- Receive data FIFO
txfifo : spi_fifo; -- Transmit data FIFO
rfreecnt : integer range 0 to FIFO_DEPTH; -- free rx fifo slots
mask : std_logic_vector(FIFO_DEPTH-1 downto 0);
mask_shdw : std_logic_vector(FIFO_DEPTH-1 downto 0);
unread : std_logic_vector(FIFO_DEPTH-1 downto 0);
at : std_ulogic;
--
rxread : std_ulogic;
txwrite : std_ulogic;
txread : std_ulogic;
apbaddr : std_logic_vector(FIFO_BITS-1 downto 0);
rxsel : std_ulogic;
end record;
-- Two stage synchronizers on each input coming from off-chip
type spi_in_local_type is record
miso : std_ulogic;
mosi : std_ulogic;
sck : std_ulogic;
spisel : std_ulogic;
end record;
type spi_in_array is array (1 downto 0) of spi_in_local_type;
-- Local spi out type without ssn
type spi_out_local_type is record
miso : std_ulogic;
misooen : std_ulogic;
mosi : std_ulogic;
mosioen : std_ulogic;
sck : std_ulogic;
sckoen : std_ulogic;
enable : std_ulogic;
astart : std_ulogic;
aready : std_ulogic;
end record;
-- Yet another subset of out type to make it easier for certain tools to
-- place registers near pads.
type spi_out_local_lb_type is record
mosi : std_ulogic;
sck : std_ulogic;
end record;
type spi_reg_type is record
-- SPI registers
mode : spi_mode_rec; -- Mode register
event : spi_em_rec; -- Event register
mask : spi_em_rec; -- Mask register
lst : std_ulogic; -- Only field on command register
td : std_logic_vector(31 downto 0); -- Transmit register
rd : std_logic_vector(31 downto 0); -- Receive register
slvsel : std_logic_vector((SLVSEL_SZ-1) downto 0); -- Slave select register
aslvsel : std_logic_vector((SLVSEL_SZ-1) downto 0); -- Automatic slave select
--
uf : std_ulogic; -- Slave in underflow condition
ov : std_ulogic; -- Receive overflow condition
td_occ : std_ulogic; -- Transmit register occupied
rd_free : std_ulogic; -- Receive register free (empty)
txfifo : spi_fifo; -- Transmit data FIFO
rxfifo : spi_fifo; -- Receive data FIFO
rxd : std_logic_vector(wlen downto 0); -- Receive shift register
txd : std_logic_vector(wlen downto 0); -- Transmit shift register
txdupd : std_ulogic; -- Update txd
txdbyp : std_ulogic; -- txd update bypass
toggle : std_ulogic; -- SCK has toggled
samp : std_ulogic; -- Sample
chng : std_ulogic; -- Change
psck : std_ulogic; -- Previous value of SC
twdir : std_ulogic; -- Direction in 3-wire mode
syncsamp : std_logic_vector(1 downto 0); -- Sample synchronized input
incrdli : std_ulogic;
rxdone : std_ulogic;
rxdone2 : std_ulogic;
running : std_ulogic;
ov2 : std_ulogic;
-- counters
tfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
rfreecnt : integer range 0 to FIFO_DEPTH; -- free td fifo slots
tdfi : std_logic_vector(fdepth-1 downto 0); -- First tx queue element
rdfi : std_logic_vector(fdepth-1 downto 0); -- First rx queue element
tdli : std_logic_vector(fdepth-1 downto 0); -- Last tx queue element
rdli : std_logic_vector(fdepth-1 downto 0); -- Last rx queue element
rbitcnt : std_logic_vector(log2(wlen+1)-1 downto 0); -- Current receive bit
tbitcnt : std_logic_vector(log2(wlen+1)-1 downto 0); -- Current transmit bit
divcnt : unsigned(9 downto 0); -- Clock scaler
cgcnt : unsigned(5 downto 0); -- Clock gap counter
cgcntblock: std_ulogic;
aselcnt : unsigned(1 downto 0); -- ASEL delay
cgasel : std_ulogic; -- ASEL when entering CG
--
irq : std_ulogic;
--
-- Automode
am : spi_am_rec;
-- Sync registers for inputs
spii : spi_in_array;
-- Output
spio : spi_out_local_type;
spiolb : spi_out_local_lb_type;
--
astart : std_ulogic;
cstart : std_ulogic;
txdupd2 : std_ulogic;
twdir2 : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Sub programs
-----------------------------------------------------------------------------
-- Returns a vector containing the character length - 1 in bits as selected
-- by the Mode field LEN.
function spilen (
len : std_logic_vector(3 downto 0))
return std_logic_vector is
begin -- spilen
if len = zero32(3 downto 0) then
return "11111";
else
return "0" & len;
end if;
end spilen;
-- Write clear
procedure wc (
reg_o : out std_ulogic;
reg_i : in std_ulogic;
b : in std_ulogic) is
begin
reg_o := reg_i and not b;
end procedure wc;
-- Reverses string. After this function has been called the first bit
-- to send is always at position 0.
function reverse(
data : std_logic_vector)
return std_logic_vector is
variable rdata: std_logic_vector(data'reverse_range);
begin
for i in data'range loop
rdata(i) := data(i);
end loop;
return rdata;
end function reverse;
-- Performs a HWORD swap if len /= 0
function condhwordswap (
data : std_logic_vector(31 downto 0);
len : std_logic_vector(4 downto 0))
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0);
begin -- condhwordswap
if len = one32(4 downto 0) then
rdata := data;
else
rdata := data(15 downto 0) & data(31 downto 16);
end if;
return rdata;
end condhwordswap;
-- Zeroes out unused part of receive vector.
function select_data (
data : std_logic_vector(wlen downto 0);
len : std_logic_vector(4 downto 0))
return std_logic_vector is
variable rdata : std_logic_vector(31 downto 0) := (others => '0');
variable length : integer range 0 to 31 := conv_integer(len);
variable sdata : std_logic_vector(31 downto 0) := (others => '0');
begin -- select_data
-- Quartus can not handle variable ranges
-- rdata(conv_integer(len) downto 0) := data(conv_integer(len) downto 0);
sdata := (others => '0'); sdata(wlen downto 0) := data;
case length is
when 15 => rdata(15 downto 0) := sdata(15 downto 0);
when 14 => rdata(14 downto 0) := sdata(14 downto 0);
when 13 => rdata(13 downto 0) := sdata(13 downto 0);
when 12 => rdata(12 downto 0) := sdata(12 downto 0);
when 11 => rdata(11 downto 0) := sdata(11 downto 0);
when 10 => rdata(10 downto 0) := sdata(10 downto 0);
when 9 => rdata(9 downto 0) := sdata(9 downto 0);
when 8 => rdata(8 downto 0) := sdata(8 downto 0);
when 7 => rdata(7 downto 0) := sdata(7 downto 0);
when 6 => rdata(6 downto 0) := sdata(6 downto 0);
when 5 => rdata(5 downto 0) := sdata(5 downto 0);
when 4 => rdata(4 downto 0) := sdata(4 downto 0);
when 3 => rdata(3 downto 0) := sdata(3 downto 0);
when others => rdata := sdata;
end case;
return rdata;
end select_data;
-- purpose: Returns true when a slave is selected and the clock starts
function slv_start (
spisel : std_ulogic;
cpol : std_ulogic;
sck : std_ulogic;
fsck_chg : std_ulogic)
return boolean is
begin -- slv_start
if spisel = '0' then -- Slave is selected
if fsck_chg = '1' then -- The clock has changed
return (cpol xor sck) = '1'; -- The clock is not idle
end if;
end if;
return false;
end slv_start;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
function spictrl_resval return spi_reg_type is
variable v : spi_reg_type;
begin
v.mode := ('0','0','0','0','0','0','0','0',"0000","0000",
'0','0','0','0',"00000","00", '0', '0', '0', '0');
v.event := ('0', '0', '0', '0', '0', '0', '0', '0');
v.mask := ('0', '0', '0', '0', '0', '0', '0', '0');
v.lst := '0';
v.td := (others => '0');
v.rd := (others => '0');
v.slvsel := (others => '1');
v.aslvsel := (others => '0');
v.uf := '0';
v.ov := '0';
v.td_occ := '0';
v.rd_free := '1';
for i in 0 to (1-syncram)*(FIFO_DEPTH-1) loop
v.txfifo(i) := (others => '0');
v.rxfifo(i) := (others => '0');
end loop;
v.rxd := (others => '0');
v.txd := (others => '0'); v.txd(0) := '1';
v.txdupd := '0';
v.txdbyp := '0';
v.toggle := '0';
v.samp := '1';
v.chng := '0';
v.psck := '0';
v.twdir := INPUT;
v.syncsamp := (others => '0');
v.incrdli := '0';
v.rxdone := '0';
v.rxdone2 := '0';
v.running := '0';
v.ov2 := '0';
v.tfreecnt := FIFO_DEPTH;
v.rfreecnt := FIFO_DEPTH;
v.tdfi := (others => '0');
v.rdfi := (others => '0');
v.tdli := (others => '0');
v.rdli := (others => '0');
v.rbitcnt := (others => '0');
v.tbitcnt := (others => '0');
v.divcnt := (others => '0');
v.cgcnt := (others => '0');
v.cgcntblock := '0';
v.aselcnt := (others => '0');
v.cgasel := '0';
v.irq := '0';
v.am.cfg := ('0', '0', '0', '0', '0', '0', '0', '0', '0');
v.am.per := (others => '0');
v.am.active := '0';
v.am.lock := '0';
v.am.cnt := (others => '0');
v.am.skipdata := '0';
v.am.rxfull := '0';
for i in 0 to (1-syncram)*(FIFO_DEPTH-1) loop
v.am.rxfifo := (others => (others => '0'));
v.am.txfifo := (others => (others => '0'));
end loop;
v.am.rfreecnt := 0;
v.am.mask := (others => '0');
v.am.mask_shdw := (others => '1');
v.am.unread := (others => '0');
v.am.at := '0';
v.am.rxread := '0';
v.am.txwrite := '0';
v.am.txread := '0';
v.am.apbaddr := (others => '0');
v.am.rxsel := '0';
for i in 1 downto 0 loop
v.spii(i).miso := '1';
v.spii(i).mosi := '1';
v.spii(i).sck := '0';
v.spii(i).spisel := '1';
end loop;
v.spio.miso := '1';
v.spio.misooen := INPUT;
v.spio.mosi := '1';
v.spio.mosioen := INPUT;
v.spio.sck := '0';
v.spio.sckoen := INPUT;
v.spio.enable := '0';
v.spio.astart := '0';
v.spio.aready := '0';
v.spiolb.mosi := '1';
v.spiolb.sck := '1';
v.astart := '0';
v.cstart := '0';
v.txdupd2 := '0';
v.twdir2 := '0';
return v;
end spictrl_resval;
constant RES : spi_reg_type := spictrl_resval;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : spi_reg_type;
type fifo_data_vector_array is array (automode downto 0) of std_logic_vector(wlen downto 0);
type fifo_addr_vector_array is array (automode downto 0) of std_logic_vector(fdepth-1 downto 0);
signal rx_di, rx_do, tx_di, tx_do : fifo_data_vector_array;
signal rx_ra, rx_wa, tx_ra, tx_wa : fifo_addr_vector_array;
signal rx_read, tx_read, rx_write, tx_write : std_logic_vector(automode downto 0);
signal arstn : std_ulogic;
begin
arstn <= apbi_testrst when (scantest = 1) and (apbi_testen = '1') else rstn;
-- SPI controller, register interface and related logic
comb: process (r, rstn, apbi_psel, apbi_penable, apbi_paddr, apbi_pwrite,
apbi_pwdata, apbi_testen, apbi_testrst, apbi_scanen,
apbi_testoen, spii_miso, spii_mosi, spii_sck, spii_spisel,
spii_astart, rx_do, tx_do, spii_cstart, spii_ignore)
variable v : spi_reg_type;
variable apbaddr : std_logic_vector(APBH downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable len : std_logic_vector(4 downto 0);
variable indata : std_ulogic;
variable change : std_ulogic;
variable update : std_ulogic;
variable sample : std_ulogic;
variable reload : std_ulogic;
variable cgasel : std_ulogic;
variable txshift : std_ulogic;
-- automode
variable rstop1 : std_ulogic;
variable rstop2 : std_ulogic;
variable rstop3 : std_ulogic;
variable tstop1 : std_ulogic;
variable tstop2 : std_ulogic;
variable tstop3 : std_ulogic;
variable astart : std_ulogic;
-- fifos
variable rx_rd : std_ulogic;
variable tx_rd : std_ulogic;
variable rx_wr : std_ulogic;
variable tx_wr : std_ulogic;
--
variable fsck : std_ulogic;
variable fsck_chg : std_ulogic;
--
variable spisel : std_ulogic;
--
variable rntxd : std_logic_vector(0 to 31);
variable ntxd : std_logic_vector(wlen downto 0);
variable amask : std_logic_vector(FIFO_DEPTH-1 downto 0);
variable aloop : integer;
begin -- process comb
v := r; v.irq := '0';
apbaddr := apbi_paddr(APBH downto 2); apbout := (others => '0');
len := spilen(r.mode.len); v.toggle := '0'; v.txdupd := '0';
v.syncsamp := r.syncsamp(0) & '0'; update := '0'; v.rxdone := '0';
indata := '0'; sample := '0'; change := '0'; reload := '0';
v.spio.astart := '0'; cgasel := '0'; v.ov2 := r.ov; txshift := '0';
fsck := '0'; fsck_chg := '0'; v.txdbyp := '0';
spisel := r.spii(1).spisel or r.mode.igsel;
ntxd := r.td(wlen downto 0); rntxd := reverse(r.td);
if r.mode.rev = '1' then ntxd := rntxd(31-wlen to 31); end if;
v.spio.aready := '0';
if AM_EN = 1 then
v.txdupd2 := '0';
v.cstart := '0';
if TW_EN = 1 then
v.twdir2 := r.twdir;
end if;
end if;
if PROG_AM_MASK then
amask := r.am.mask;
aloop := FIFO_DEPTH-1;
else
amask := AM_MASK(FIFO_DEPTH-1 downto 0);
aloop := AM_MASK_END;
end if;
rx_rd := '0'; tx_rd := '0'; rx_wr := '0'; tx_wr := '0';
rstop1 := '0'; rstop2 := '0'; rstop3 := '0';
tstop1 := '0'; tstop2 := '0'; tstop3 := '0';
astart := '0'; v.am.txwrite := '0'; v.am.txwrite := '0'; v.am.rxread := '0';
if AM_EN = 1 then
v.am.at := r.event.at;
v.astart := spii_astart;
if r.event.at = '0' then
astart := spii_astart and (not r.astart);
if PROG_AM_MASK then
v.am.mask := r.am.mask_shdw;
end if;
end if;
if spii_cstart = '1' then v.cstart := '1'; end if;
end if;
if (apbi_psel and apbi_penable and (not apbi_pwrite)) = '1' then
if apbaddr = CAP_ADDR then
apbout := SPICTRLCAPREG;
elsif apbaddr = MODE_ADDR then
apbout := r.mode.amen & r.mode.loopb & r.mode.cpol & r.mode.cpha &
r.mode.div16 & r.mode.rev & r.mode.ms & r.mode.en &
r.mode.len & r.mode.pm & r.mode.tw & r.mode.asel &
r.mode.fact & r.mode.od & r.mode.cg & r.mode.aseldel &
r.mode.tac & r.mode.tto & r.mode.igsel & r.mode.cite &
zero32(0);
elsif apbaddr = EVENT_ADDR then
apbout := r.event.tip & zero32(30 downto 16) & r.event.at &
r.event.lt & zero32(13) & r.event.ov & r.event.un &
r.event.mme & r.event.ne & r.event.nf & zero32(7 downto 0);
elsif apbaddr = MASK_ADDR then
apbout := r.mask.tip & zero32(30 downto 16) & r.mask.at &
r.mask.lt & zero32(13) & r.mask.ov & r.mask.un &
r.mask.mme & r.mask.ne & r.mask.nf & zero32(7 downto 0);
elsif apbaddr = RD_ADDR then
apbout := condhwordswap(r.rd, len);
if AM_EN = 0 or r.mode.amen = '0' then
v.rd_free := '1';
end if;
elsif apbaddr = SLVSEL_ADDR then
if SLVSEL_EN /= 0 then apbout((SLVSEL_SZ-1) downto 0) := r.slvsel;
else null; end if;
elsif apbaddr = ASEL_ADDR then
if ASEL_EN /= 0 then
apbout((SLVSEL_SZ-1) downto 0) := r.aslvsel;
else null; end if;
end if;
end if;
-- write registers
if (apbi_psel and apbi_penable and apbi_pwrite) = '1' then
if apbaddr = MODE_ADDR then
if AM_EN = 1 then v.mode.amen := apbi_pwdata(31); end if;
v.mode.loopb := apbi_pwdata(30);
v.mode.cpol := apbi_pwdata(29);
v.mode.cpha := apbi_pwdata(28);
v.mode.div16 := apbi_pwdata(27);
v.mode.rev := apbi_pwdata(26);
v.mode.ms := apbi_pwdata(25);
v.mode.en := apbi_pwdata(24);
v.mode.len := apbi_pwdata(23 downto 20);
v.mode.pm := apbi_pwdata(19 downto 16);
if TW_EN = 1 then v.mode.tw := apbi_pwdata(15); end if;
if ASEL_EN = 1 then v.mode.asel := apbi_pwdata(14); end if;
v.mode.fact := apbi_pwdata(13);
if OD_EN = 1 then v.mode.od := apbi_pwdata(12); end if;
v.mode.cg := apbi_pwdata(11 downto 7);
if ASEL_EN = 1 then
v.mode.aseldel := apbi_pwdata(6 downto 5);
v.mode.tac := apbi_pwdata(4);
end if;
if TW_EN = 1 then v.mode.tto := apbi_pwdata(3); end if;
v.mode.igsel := apbi_pwdata(2);
v.mode.cite := apbi_pwdata(1);
elsif apbaddr = EVENT_ADDR then
wc(v.event.lt, r.event.lt, apbi_pwdata(14));
wc(v.event.ov, r.event.ov, apbi_pwdata(12));
wc(v.event.un, r.event.un, apbi_pwdata(11));
wc(v.event.mme, r.event.mme, apbi_pwdata(10));
elsif apbaddr = MASK_ADDR then
v.mask.tip := apbi_pwdata(31);
if AM_EN = 1 then
v.mask.at := apbi_pwdata(15);
end if;
v.mask.lt := apbi_pwdata(14);
v.mask.ov := apbi_pwdata(12);
v.mask.un := apbi_pwdata(11);
v.mask.mme := apbi_pwdata(10);
v.mask.ne := apbi_pwdata(9);
v.mask.nf := apbi_pwdata(8);
elsif apbaddr = COM_ADDR then
v.lst := apbi_pwdata(22);
elsif apbaddr = TD_ADDR then
-- The write is lost if the transmit register is written when
-- the not full bit is zero.
if r.event.nf = '1' then
v.td := apbi_pwdata;
if AM_EN = 0 or r.mode.amen = '0' then
v.td_occ := '1';
end if;
end if;
elsif apbaddr = SLVSEL_ADDR then
if SLVSEL_EN /= 0 then v.slvsel := apbi_pwdata((SLVSEL_SZ-1) downto 0);
else null; end if;
elsif apbaddr = ASEL_ADDR then
if ASEL_EN /= 0 then
v.aslvsel := apbi_pwdata((SLVSEL_SZ-1) downto 0);
else null; end if;
end if;
end if;
-- Automode register interface
if AM_EN /= 0 then
if apbi_psel = '1' then
v.am.apbaddr := apbaddr(FIFO_BITS+1 downto 2);
if syncram /= 0 then
-- Check if tx queue will be read
if apbaddr(10 downto 9) = AMTX_ADDR(10 downto 9) then
v.am.txread := apbi_pwrite and not r.am.txread;
end if;
if apbaddr(10 downto 9) = AMRX_ADDR(10 downto 9) then
v.am.rxread := not r.am.rxread;
end if;
end if;
end if;
if (apbi_psel and apbi_penable) = '1' then
if apbaddr = AMCFG_ADDR then
apbout := zero32(31 downto 9) & r.am.cfg.ecgc & r.am.cfg.lock &
r.am.cfg.erpt & r.am.cfg.seq & r.am.cfg.strict &
r.am.cfg.ovtb & r.am.cfg.ovdb & r.am.active &
r.am.cfg.eact;
if apbi_pwrite = '1' then
v.am.cfg.ecgc := apbi_pwdata(8);
v.am.cfg.lock := apbi_pwdata(7);
v.am.cfg.erpt := apbi_pwdata(6);
v.am.cfg.seq := apbi_pwdata(5);
v.am.cfg.strict := apbi_pwdata(4);
v.am.cfg.ovtb := apbi_pwdata(3);
v.am.cfg.ovdb := apbi_pwdata(2);
v.am.cfg.act := apbi_pwdata(1);
v.spio.astart := apbi_pwdata(1);
v.am.cfg.eact := apbi_pwdata(0);
end if;
elsif apbaddr = AMPER_ADDR then
apbout((AM_CNT_BITS-1)*AM_EN downto 0) := r.am.per;
if apbi_pwrite = '1' then
v.am.per := apbi_pwdata((AM_CNT_BITS-1)*AM_EN downto 0);
end if;
elsif apbaddr = AMMSK0_ADDR then
if FIFO_DEPTH > 32 then
apbout := amask(31 downto 0);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(31 downto 0) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-1 downto 0) := amask(FIFO_DEPTH-1 downto 0);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 0) := apbi_pwdata(FIFO_DEPTH-1 downto 0);
end if;
end if;
end if;
elsif apbaddr = AMMSK1_ADDR then
if AM_MSK1_EN then
if FIFO_DEPTH > 64 then
apbout := amask(63 downto 32);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(63 downto 32) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-33 downto 0) := amask(FIFO_DEPTH-1 downto 32);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 32) := apbi_pwdata(FIFO_DEPTH-33 downto 0);
end if;
end if;
end if;
else
null;
end if;
elsif apbaddr = AMMSK2_ADDR then
if AM_MSK2_EN then
if FIFO_DEPTH > 96 then
apbout := amask(95 downto 64);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(95 downto 64) := apbi_pwdata;
end if;
end if;
else
apbout(FIFO_DEPTH-65 downto 0) := amask(FIFO_DEPTH-1 downto 64);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 64) := apbi_pwdata(FIFO_DEPTH-65 downto 0);
end if;
end if;
end if;
else
null;
end if;
elsif apbaddr = AMMSK3_ADDR then
if AM_MSK3_EN then
apbout(FIFO_DEPTH-97 downto 0) := amask(FIFO_DEPTH-1 downto 96);
if PROG_AM_MASK then
if apbi_pwrite = '1' then
v.am.mask_shdw(FIFO_DEPTH-1 downto 96) := apbi_pwdata(FIFO_DEPTH-97 downto 0);
end if;
end if;
else
null;
end if;
elsif apbaddr(10 downto 9) = AMTX_ADDR(10 downto 9) then
if conv_integer(apbaddr(8 downto 2)) < FIFO_DEPTH then
if syncram = 0 then
apbout(wlen downto 0) :=
r.am.txfifo(conv_integer(apbaddr(FIFO_BITS+1 downto 2)));
else
apbout(wlen downto 0) := tx_do(automode);
end if;
if apbi_pwrite = '1' then
v.am.txwrite := '1';
v.td := apbi_pwdata;
end if;
end if;
elsif apbaddr(10 downto 9) = AMRX_ADDR(10 downto 9) then
if conv_integer(apbaddr(8 downto 2)) < FIFO_DEPTH then
if syncram = 0 then
if r.mode.rev = '0' then
apbout := condhwordswap(reverse(select_data(r.rxfifo(conv_integer(r.am.apbaddr)), len)), len);
else
apbout := condhwordswap(select_data(r.rxfifo(conv_integer(r.am.apbaddr)), len), len);
end if;
else
if r.mode.rev = '0' then
apbout := condhwordswap(reverse(select_data(rx_do(conv_integer(not r.am.rxsel)), len)), len);
else
apbout := condhwordswap(select_data(rx_do(conv_integer(not r.am.rxsel)), len), len);
end if;
end if;
if r.am.unread(conv_integer(r.am.apbaddr)) = '1' then
v.rd_free := '1';
v.am.unread(conv_integer(r.am.apbaddr)) := '0';
v.am.lock := r.am.cfg.lock;
end if;
end if;
end if;
end if;
end if;
-- Handle transmit FIFO
if r.td_occ = '1' and r.tfreecnt /= 0 then
if syncram = 0 then
v.txfifo(conv_integer(r.tdli)) := ntxd;
else
tx_wr := '1';
end if;
v.tdli := r.tdli + 1;
v.tfreecnt := r.tfreecnt - 1;
v.td_occ := '0';
if r.tfreecnt = FIFO_DEPTH then
v.txdbyp := r.running and r.mode.ms and r.txdupd;
v.txdupd := not r.uf;
tx_rd := '1';
end if;
end if;
-- AM transmit FIFO handling when core is not implemented with SYNCRAM
if syncram = 0 and AM_EN /= 0 and r.am.txwrite = '1' then
if r.mode.rev = '0' then
v.am.txfifo(conv_integer(r.am.apbaddr)) := r.td(wlen downto 0);
else
v.am.txfifo(conv_integer(r.am.apbaddr)) := reverse(r.td)(31-wlen to 31);
end if;
end if;
-- Update receive register and FIFO
if r.rd_free = '1' and r.rfreecnt /= FIFO_DEPTH then
if syncram = 0 then
if r.mode.rev = '0' then
v.rd := reverse(select_data(r.rxfifo(conv_integer(r.rdfi)), len));
else
v.rd := select_data(r.rxfifo(conv_integer(r.rdfi)), len);
end if;
else
if r.mode.rev = '0' then
v.rd := reverse(select_data(rx_do(0), len));
else
v.rd := select_data(rx_do(0), len);
end if;
end if;
if not ((ignore > 0) and (spii_ignore = '1')) then
v.rdfi := r.rdfi + 1;
v.rfreecnt := r.rfreecnt + 1;
v.rd_free := '0';
end if;
end if;
if v.rd_free = '1' and r.rfreecnt /= FIFO_DEPTH then rx_rd := '1'; end if;
if r.mode.en = '1' then -- Core is enabled
-- Not full detection
if r.tfreecnt /= 0 or r.td_occ /= '1' then
v.event.nf := '1';
if (r.mask.nf and not r.event.nf) = '1' then
v.irq := '1';
end if;
else
v.event.nf := '0';
end if;
-- Not empty detection
if ((AM_EN = 0 or r.mode.amen = '0') and (r.rfreecnt /= FIFO_DEPTH or r.rd_free /= '1')) or
(AM_EN = 1 and r.mode.amen = '1' and r.am.unread /= zero128(FIFO_DEPTH-1 downto 0)) then
v.event.ne := '1';
if (r.mask.ne and not r.event.ne) = '1' then
v.irq := '1';
end if;
else
v.event.ne := '0';
if AM_EN = 1 then v.am.lock := '0'; end if;
end if;
end if;
---------------------------------------------------------------------------
-- Automated periodic transfer control
---------------------------------------------------------------------------
if AM_EN = 1 and r.mode.amen = '1' then
if r.am.active = '0' then
-- Activation either from register write or external event.
v.am.active := r.spio.astart or (astart and r.am.cfg.eact);
v.am.cfg.act := v.am.active;
v.am.rfreecnt := 0;
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.rfreecnt := v.am.rfreecnt+1;
end if;
end loop;
v.am.skipdata := '0'; v.am.rxfull := '0';
v.am.cnt := unsigned(r.am.per);
v.event.at := v.am.active;
v.tdfi := (others => '0');
-- Check mask to see which word in the FIFO to start with.
for i in 0 to aloop loop
if amask(i) = '1' then
if tstop1 = '0' then
v.tdfi := conv_std_logic_vector(i, r.tdfi'length);
end if;
tstop1 := '1';
end if;
end loop;
if v.am.active = '1' then
v.txdupd2 := '1'; tx_rd := '1';
v.tfreecnt := FIFO_DEPTH;
for i in 0 to aloop loop
if amask(i) = '1' then
v.tfreecnt := v.tfreecnt-1;
end if;
end loop;
end if;
v.rdli := (others => '0');
for i in 0 to aloop loop
if rstop1 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop1 := '1';
end if;
end if;
end loop;
v.cstart := v.am.active;
else
-- Receive fifo handling
if r.am.rxfull = '1' then -- AM RX fifo is filled
-- Move to receive queue if the queue is empty or if there is no
-- requirement on sequential transfers and the queue is not locked.
if (r.event.ne and (v.am.lock or r.am.cfg.seq)) = '0' then
-- Queue is empty
if syncram = 0 then
v.rxfifo := r.am.rxfifo;
else
v.am.rxsel := not r.am.rxsel;
end if;
v.rdfi := (others => '0');
v.rfreecnt := r.am.rfreecnt;
v.rd_free := '0';
v.am.rxfull := '0';
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.unread(i) := '1';
end if;
end loop;
end if;
if r.event.tip = '0' and r.am.at = '1' then
v.event.at := '0';
end if;
if (r.mask.at and r.event.at) = '1' then
v.irq := '1';
end if;
end if;
if r.am.cfg.act = '0' then v.am.active := r.running; end if;
v.am.cfg.eact := '0';
if (r.am.cnt = 0 and r.am.cfg.erpt = '0') or (astart = '1' and r.am.cfg.erpt = '1') then
-- Only allowed to start new transfer if previous transfer(s) is finished
if r.event.tip = '0' then
if (not v.am.rxfull or r.am.cfg.strict) = '1' then
v.am.cnt := unsigned(r.am.per);
end if;
if (not v.am.rxfull or (r.am.cfg.strict and not r.am.cfg.ovtb)) = '1' then
-- Start transfer. Initialize indexes and fifo counter
v.txdupd2 := '1'; tx_rd := '1';
v.am.cnt := unsigned(r.am.per);
v.rdli := (others => '0');
for i in 0 to aloop loop
if rstop2 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop2 := '1';
end if;
end if;
end loop;
v.tfreecnt := FIFO_DEPTH;
v.am.rfreecnt := 0;
for i in 0 to aloop loop
if amask(i) = '1' then
v.am.rfreecnt := v.am.rfreecnt+1;
v.tfreecnt := v.tfreecnt-1;
end if;
end loop;
v.tdfi := (others => '0');
-- Check mask to see which word in the FIFO to start with.
for i in 0 to aloop loop
if amask(i) = '1' then
if tstop2 = '0' then
v.tdfi := conv_std_logic_vector(i, r.tdfi'length);
end if;
tstop2 := '1';
end if;
end loop;
-- Skip incoming data if receive FIFO is full and OVDB is '1'.
v.am.skipdata := v.am.rxfull and r.am.cfg.ovdb;
if v.am.skipdata = '0' then
-- Clear AM receive fifo if we will overwrite it.
v.am.rfreecnt := FIFO_DEPTH;
for i in 0 to aloop loop
if amask(i) = '0' then
v.am.rfreecnt := v.am.rfreecnt-1;
end if;
end loop;
v.am.rxfull := '0';
end if;
v.event.at := '1';
v.cstart := astart and r.am.cfg.erpt;
end if;
end if;
else
v.am.cnt := r.am.cnt - 1;
end if;
end if;
end if;
---------------------------------------------------------------------------
-- SCK filtering, only used in slave mode
---------------------------------------------------------------------------
fsck := r.psck;
if (r.mode.en and not r.mode.ms) = '1' then
if (r.spii(1).sck xor r.psck) = '0' then
reload := '1';
else
-- Detected SCK change
if r.divcnt = 0 then
v.psck := r.spii(1).sck;
fsck := r.spii(1).sck;
fsck_chg := '1';
reload := '1';
else
v.divcnt := r.divcnt - 1;
end if;
end if;
elsif r.mode.en = '1' then
v.psck := r.spii(1).sck;
end if;
---------------------------------------------------------------------------
-- SPI bus control
---------------------------------------------------------------------------
if (r.mode.en and not r.running) = '1' and (r.mode.ms = '0' or r.divcnt = 0) then
if r.mode.ms = '1' then
if r.divcnt = 0 then
v.spio.sck := r.mode.cpol;
end if;
v.spio.misooen := INPUT;
if TW_EN = 0 or r.mode.tw = '0' then
if OD_EN = 0 or r.mode.od = '0' then
v.spio.mosioen := OUTPUT;
end if;
else
v.spio.mosioen := INPUT;
end if;
v.spio.sckoen := OUTPUT;
if TW_EN = 1 then v.twdir := OUTPUT xor r.mode.tto; end if;
else
if (spisel or r.mode.tw) = '0' then
v.spio.misooen := OUTPUT;
else
v.spio.misooen := INPUT;
end if;
if (not spisel and r.mode.tw and r.mode.tto) = '0' then
v.spio.mosioen := INPUT;
else
v.spio.mosioen := OUTPUT;
end if;
v.spio.sckoen := INPUT;
if TW_EN = 1 then v.twdir := INPUT xor r.mode.tto; end if;
end if;
if ((((AM_EN = 0 or r.mode.amen = '0') or
(AM_EN = 1 and r.mode.amen = '1' and r.am.active = '1')) and
r.mode.ms = '1' and r.tfreecnt /= FIFO_DEPTH and r.txdupd = '0' and (AM_EN = 0 or r.txdupd2 = '0')) or
slv_start(spisel, r.mode.cpol, fsck, fsck_chg)) then
-- Slave underrun detection
if r.tfreecnt = FIFO_DEPTH then
v.uf := '1';
if (r.mask.un and not v.event.un) = '1' then
v.irq := '1';
end if;
v.event.un := '1';
end if;
v.running := '1';
if r.mode.ms = '1' then
if TW_EN = 0 or r.mode.tw = '0' then
v.spio.mosioen := OUTPUT;
else
v.spio.mosioen := OUTPUT xor r.mode.tto;
end if;
change := not r.mode.cpha;
-- Insert cycles when cpha = '0' to ensure proper setup
-- time for first MOSI value in master mode.
reload := not r.mode.cpha;
end if;
end if;
v.cgcnt := (others => '0');
v.rbitcnt := (others => '0'); v.tbitcnt := (others => '0');
if r.mode.ms = '0' then
update := not (r.mode.cpha or (fsck xor r.mode.cpol));
if r.mode.cpha = '0' then
-- Prepare first bit
v.tbitcnt := (others => '0'); v.tbitcnt(0) := '1';
if v.running = '1' and (TW_EN = 0 or r.mode.tw = '0' or r.twdir = OUTPUT) then
txshift := '1';
end if;
end if;
end if;
-- samp and chng should not be changed on b2b
if spisel /= '0' then
v.samp := not r.mode.cpha;
v.chng := r.mode.cpha;
v.psck := r.mode.cpol;
end if;
end if;
if AM_EN = 0 or r.mode.amen = '0' or r.am.cfg.ecgc = '0' then
v.cgcntblock := '0';
else
if r.cstart = '1' then
v.cgcntblock := '0';
end if;
end if;
---------------------------------------------------------------------------
-- Clock generation, only in master mode
---------------------------------------------------------------------------
if r.mode.ms = '1' and (r.running = '1' or r.divcnt /= 0) then
-- The frequency of the SPI clock relative to the system clock is
-- determined by the fact, div16 and pm register fields.
--
-- With fact = 0 the fields have the same meaning as in the MPC83xx
-- register interface. The clock is divided by 4*([PM]+1) and if div16
-- is set the clock is divided by 16*(4*([PM]+1)).
--
-- With fact = 1 the core's register i/f is no longer compatible with
-- the MPC83xx register interface. The clock is divided by 2*([PM]+1) and
-- if div16 is set the clock is divided by 16*(2*([PM]+1)).
--
-- The generated clock's duty cycle is always 50%.
if r.divcnt = 0 then
if ASEL_EN = 0 or r.aselcnt = 0 then
-- Toggle SCK unless we are in a clock gap
if (r.cgcnt = 0 and (AM_EN = 0 or r.cgcntblock = '0')) or
r.spiolb.sck /= r.mode.cpol then
v.spio.sck := not r.spiolb.sck;
v.toggle := r.running;
end if;
if r.cgcnt /= 0 and (AM_EN = 0 or r.cgcntblock = '0') then
v.cgcnt := r.cgcnt - 1;
if ASEL_EN /= 0 and r.cgcnt = 1 then
cgasel := r.mode.tac;
end if;
end if;
elsif ASEL_EN = 1 then
v.aselcnt := r.aselcnt - 1;
end if;
reload := '1';
else
v.divcnt := r.divcnt - 1;
end if;
elsif r.mode.ms = '1' then
v.divcnt := (others => '0');
end if;
if reload = '1' then
-- Reload clock scale counter
v.divcnt(4 downto 0) := unsigned('0' & r.mode.pm) + 1;
if (not r.mode.fact and r.mode.ms) = '1' then
if r.mode.div16 = '1' then
v.divcnt := shift_left(v.divcnt, 5) - 1;
else
v.divcnt := shift_left(v.divcnt, 1) - 1;
end if;
else
if (r.mode.div16 and r.mode.ms) = '1' then
v.divcnt := shift_left(v.divcnt, 4) - 1;
else
v.divcnt(9 downto 4) := (others => '0');
v.divcnt(3 downto 0) := unsigned(r.mode.pm);
end if;
end if;
end if;
---------------------------------------------------------------------------
-- Handle master operation.
---------------------------------------------------------------------------
if r.mode.ms = '1' then
-- Sample data
if r.toggle = '1' then
v.samp := not r.samp;
sample := r.samp;
end if;
-- Change data on the clock flank...
if v.toggle = '1' then
v.chng := not r.chng;
change := r.chng;
end if;
-- Detect multiple-master errors (mode-fault)
if spisel = '0' then
v.mode.en := '0';
v.mode.ms := '0';
v.event.mme := '1';
if (r.mask.mme and not r.event.mme) = '1' then
v.irq := '1';
end if;
v.running := '0';
v.event.tip := '0';
if AM_EN = 1 then
v.event.at := '0';
end if;
end if;
-- Select input data
if r.mode.loopb = '1' then
indata := r.spiolb.mosi;
elsif TW_EN = 1 and r.mode.tw = '1' then
indata := r.spii(1).mosi;
else
indata := r.spii(1).miso;
end if;
end if;
---------------------------------------------------------------------------
-- Handle slave operation
---------------------------------------------------------------------------
if (r.mode.en and not r.mode.ms) = '1' then
if spisel = '0' then
if fsck_chg = '1' then
sample := r.samp; v.samp := not r.samp;
change := r.chng; v.chng := not r.chng;
end if;
indata := r.spii(1).mosi;
end if;
end if;
---------------------------------------------------------------------------
-- Used in both master and slave operation
---------------------------------------------------------------------------
if sample = '1' then
-- Detect receive overflow
if ((AM_EN = 0 or r.mode.amen = '0' ) and (r.rfreecnt = 0 and r.rd_free = '0')) or
(AM_EN = 1 and r.mode.amen = '1' and r.am.rfreecnt = 0) or
r.ov = '1' then
if TW_EN = 0 or r.mode.tw = '0' or r.twdir = INPUT then
-- Overflow event and IRQ
v.ov := '1';
if r.ov = '0' then
if (r.mask.ov and not r.event.ov) = '1' then
v.irq := '1';
end if;
v.event.ov := '1';
end if;
end if;
sample := '0'; -- Prevent sample below
else
sample := not r.mode.ms or r.mode.loopb;
v.syncsamp(0) := not sample;
end if;
if r.rbitcnt = len(log2(wlen+1)-1 downto 0) then
v.rbitcnt := (others => '0');
if TW_EN = 1 then
v.twdir := r.twdir xor not r.mode.loopb;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(r.mode.tw = '1' and r.twdir = INPUT)) then
v.incrdli := not r.ov;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(TW_EN = 1 and r.mode.tw = '1' and
(((r.mode.ms xor r.mode.tto) = '1' and r.twdir = INPUT) or
((r.mode.ms xor r.mode.tto) = '0' and r.twdir = OUTPUT)))) then
if r.mode.cpha = '0' then
v.cgcnt := unsigned(r.mode.cg & '0');
if ASEL_EN /= 0 then v.cgasel := r.mode.tac; end if;
if AM_EN = 1 and r.mode.amen = '1' and r.am.cfg.ecgc = '1' then
v.cgcntblock := '1';
end if;
end if;
v.ov := '0';
if r.tfreecnt = FIFO_DEPTH then
v.running := '0';
-- When running with with SCK freq. at half the system freq. we are
-- past the last edge here and SCK has transitioned from CPOL.
-- Force controller into idle state, only applies to master mode.
if (r.toggle and v.toggle) = '1' then
v.toggle := '0';
v.spio.sck := r.mode.cpol;
v.chng := r.chng;
end if;
end if;
v.uf := '0';
end if;
else
v.rbitcnt := r.rbitcnt + 1;
end if;
end if;
-- Sample data line and put into shift register.
if (r.syncsamp(1) or sample) = '1' then
v.rxd := r.rxd(wlen-1 downto 0) & indata;
if ((r.syncsamp(1) and r.incrdli) or (sample and v.incrdli)) = '1' then
v.rxdone := '1'; v.rxdone2 := '1'; v.incrdli := '0';
end if;
end if;
-- Put data into receive queue
if ((AM_EN = 0 or (r.mode.amen and r.am.skipdata) = '0') and
r.rxdone = '1') then
if AM_EN = 1 and r.am.active = '1'then
if not ((ignore > 0) and (spii_ignore = '1')) then
-- Check mask, maybe we need to skip next word in fifo
v.rdli := r.rdli + 1;
v.am.rfreecnt := v.am.rfreecnt - 1;
if DISCONT_AM_MASK then
for i in 0 to aloop loop
if i > conv_integer(r.rdli) and rstop3 = '0' then
if amask(i) = '0' then
v.rdli := v.rdli + 1;
else
rstop3 := '1';
end if;
end if;
end loop;
end if;
end if;
else
v.rdli := r.rdli + 1;
v.rfreecnt := v.rfreecnt - 1;
rx_rd := v.rd_free;
end if;
if syncram = 0 then
if AM_EN = 1 and r.am.active = '1' then
v.am.rxfifo(conv_integer(r.rdli)) := r.rxd;
else
v.rxfifo(conv_integer(r.rdli)) := r.rxd;
end if;
else
rx_wr := '1';
end if;
if r.running = '0' then
if AM_EN = 1 then v.am.rxfull := r.am.active; end if;
end if;
end if;
if AM_EN = 1 and r.mode.amen = '1' then
if TW_EN = 0 or r.mode.tw = '0' or r.mode.tto = '0' then
if r.rxdone = '1' then
v.spio.aready := '1';
end if;
else
if r.twdir = '1' and r.twdir2 = '0' then
v.spio.aready := '1';
end if;
end if;
end if;
-- Special case to put data in receive queue for automatic
-- transfer while in three wire mode with tto = 1
if AM_EN = 1 and TW_EN = 1 and r.mode.amen = '1' and
r.mode.tw = '1' and r.running = '0' and r.rxdone2 = '1' and
r.mode.tto = '1' and r.twdir = INPUT and r.mode.ms = '1' then
v.am.rxfull := r.am.active;
end if;
-- Advance transmit queue
if change = '1' then
if TW_EN = 1 and r.mode.tw = '1' then
v.spio.mosioen := r.twdir;
end if;
if r.tbitcnt = len(log2(wlen+1)-1 downto 0) then
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or
(TW_EN = 1 and r.mode.tw = '1' and
(((r.mode.ms xor r.mode.tto) = '1' and r.twdir = INPUT) or
((r.mode.ms xor r.mode.tto) = '0' and r.twdir = OUTPUT)))) then
if r.mode.cpha = '1' then
v.cgcnt := unsigned(r.mode.cg & '0');
if ASEL_EN /= 0 then v.cgasel := r.mode.tac; end if;
if AM_EN = 1 and r.mode.amen = '1' and r.am.cfg.ecgc = '1' then
v.cgcntblock := '1';
end if;
end if;
end if;
if (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or r.twdir = OUTPUT) then
if r.uf = '0' then
if not ((ignore > 0) and (spii_ignore = '1')) then
v.tfreecnt := v.tfreecnt + 1;
end if;
end if;
v.txdupd := '1'; tx_rd := '1';
end if;
v.tbitcnt := (others => '0');
else
v.tbitcnt := r.tbitcnt + 1;
end if;
if v.uf = '0' and (TW_EN = 0 or r.mode.tw = '0' or r.mode.loopb = '1' or r.twdir = OUTPUT) then
txshift := v.running;
end if;
end if;
if txshift = '1' then
v.txd := '1' & r.txd(wlen downto 1);
end if;
if AM_EN = 1 then
if r.txdupd2 = '1' then
tx_rd := '1';
v.txdupd := '1';
end if;
end if;
if r.txdupd = '1' then
tx_rd := '1';
if r.txdbyp = '0' then
if syncram = 0 then
if AM_EN = 1 and r.mode.amen = '1' then
v.txd := r.am.txfifo(conv_integer(r.tdfi));
else
v.txd := r.txfifo(conv_integer(r.tdfi));
end if;
else
-- The first FIFO is always used when using syncrams, even in AM mode
v.txd := tx_do(0);
end if;
end if;
-- Data written to TD, bypass
if v.txdbyp = '1' then
v.txd := ntxd;
end if;
if r.tfreecnt /= FIFO_DEPTH then
if AM_EN = 0 or r.mode.amen = '0' then
v.tdfi := v.tdfi + 1;
else
-- Check mask, might need to skip next word
if not (((ignore > 0) and (spii_ignore = '1'))) then
if DISCONT_AM_MASK then
for i in 0 to aloop loop
if tstop3 = '0' and i > conv_integer(v.tdfi) then
if amask(i) = '0' then
v.tdfi := v.tdfi + 1;
else
tstop3 := '1';
end if;
end if;
end loop;
end if;
v.tdfi := v.tdfi + 1;
end if;
end if;
elsif v.txdbyp = '0' then
-- Bus idle value
v.txd(0) := '1';
end if;
end if;
-- Transmit bit
if (change or update) = '1' then
if v.uf = '0' then
v.spio.miso := r.txd(0);
v.spio.mosi := r.txd(0);
if OD_EN = 1 and r.mode.od = '1' then
if (r.mode.ms or r.mode.tw) = '1' then
v.spio.mosioen := r.txd(0) xor OUTPUT;
else
v.spio.misooen := r.txd(0) xor OUTPUT;
end if;
end if;
else
v.spio.miso := '1';
v.spio.mosi := '1';
if OD_EN = 1 and r.mode.od = '1' then
v.spio.misooen := INPUT;
v.spio.mosioen := INPUT;
end if;
end if;
end if;
-- Transfer in progress interrupt generation
if (not r.running and (r.ov2 or (r.rxdone2 or (not r.mode.ms and r.mode.tw)))) = '1' then
if r.mode.ms = '0' or r.mode.cite = '0' or r.divcnt = 0 then
v.event.tip := '0'; v.rxdone2 := '0';
end if;
end if;
if v.running = '1' then v.event.tip := '1'; end if;
if (v.running and not r.event.tip and r.mask.tip and r.mode.en) = '1' then
v.irq := '1';
end if;
-- LST detection and interrupt generation
if v.running = '0' and v.tfreecnt = FIFO_DEPTH and r.lst = '1' then
v.event.lt := '1'; v.lst := '0';
if (r.mask.lt and not r.event.lt) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- Automatic slave select, only in master mode
---------------------------------------------------------------------------
if ASEL_EN /= 0 then
if (r.mode.ms and r.mode.asel) = '1' then
if ((not r.running and v.running) or -- Transfer start or
(r.event.tip and not v.event.tip) or -- transfer end or
(v.running and (cgasel or -- End or start of CG
(r.cgasel and not (r.spiolb.sck xor r.mode.cpol))))) = '1'
then
v.slvsel := r.aslvsel;
v.aslvsel := r.slvsel;
v.cgasel := '0';
end if;
-- May need to delay start of transfer
if ((not r.running and v.running) or cgasel) = '1' then -- Transfer start
v.aselcnt := unsigned(r.mode.aseldel);
end if;
else
v.cgasel := '0';
v.aselcnt := (others => '0');
end if;
end if;
-- Do not toggle outputs in loopback mode
if (r.mode.loopb = '1' or
(r.mode.tw = '1' and TW_EN = 1 and r.twdir = INPUT)) then
v.spio.mosioen := INPUT; v.spio.misooen := INPUT;
end if;
if r.mode.loopb = '1' then v.spio.sckoen := INPUT; end if;
-- When driving in OD mode, always drive low.
if OD_EN = 1 and (r.mode.od and not r.mode.loopb) = '1' then
v.spio.miso := v.spio.miso and not r.mode.od;
v.spio.mosi := v.spio.mosi and not r.mode.od;
end if;
-- Core is disabled
if ((not RESET_ALL) and rstn = '0') or (r.mode.en = '0') then
v.tfreecnt := FIFO_DEPTH;
v.rfreecnt := FIFO_DEPTH;
v.tdfi := RES.tdfi; v.rdfi := RES.rdfi;
v.tdli := RES.tdli; v.rdli := RES.rdli;
v.rd_free := RES.rd_free;
v.td_occ := RES.td_occ;
v.lst := RES.lst;
v.uf := RES.uf;
v.ov := RES.ov;
v.running := RES.running;
v.event.tip := RES.event.tip;
v.incrdli := RES.incrdli;
if TW_EN = 1 then
v.twdir := RES.twdir;
end if;
v.spio.miso := RES.spio.miso;
v.spio.mosi := RES.spio.mosi;
if syncrst = 1 or (r.mode.en = '0') then
v.spio.misooen := RES.spio.misooen;
v.spio.mosioen := RES.spio.mosioen;
v.spio.sckoen := RES.spio.sckoen;
end if;
if AM_EN = 1 then
v.event.at := RES.event.at;
end if;
-- Need to assign samp, chng and psck here if spisel is low when the
-- core is enabled
v.samp := not r.mode.cpha;
v.chng := r.mode.cpha;
v.psck := r.mode.cpol;
if AM_EN = 1 then
v.am.active := RES.am.active;
v.am.cfg.act := RES.am.cfg.act;
v.am.cfg.eact := RES.am.cfg.eact;
v.am.unread := RES.am.unread;
v.am.rxsel := RES.am.rxsel;
end if;
v.rxdone2 := '0';
v.divcnt := (others => '0');
end if;
-- Chip reset
if (not RESET_ALL) and (rstn = '0') then
v.mode := RES.mode;
v.event.tip := RES.event.tip;
v.event.lt := RES.event.lt;
v.event.ov := RES.event.ov;
v.event.un := RES.event.un;
v.event.mme := RES.event.mme;
v.event.ne := RES.event.ne;
v.event.nf := RES.event.nf;
v.mask := RES.mask;
if AM_EN = 1 then
v.event.at := RES.event.at;
if PROG_AM_MASK then
v.am.mask_shdw := RES.am.mask_shdw;
end if;
v.am.per := RES.am.per;
v.am.cfg := RES.am.cfg;
v.am.rxread := RES.am.rxread;
v.am.txwrite := RES.am.txwrite;
v.am.txread := RES.am.txread;
v.am.apbaddr := RES.am.apbaddr;
v.am.rxsel := RES.am.rxsel;
v.cgcntblock := RES.cgcntblock;
end if;
v.lst := RES.lst;
if syncrst = 1 then
v.slvsel := RES.slvsel;
end if;
v.cgcnt := RES.cgcnt;
v.rbitcnt := RES.rbitcnt; v.tbitcnt := RES.tbitcnt;
v.txd := RES.txd;
end if;
-- Drive unused bit if open drain mode is not supported
if OD_EN = 0 then v.mode.od := '0'; end if;
-- Drive unused bits if automode is not supported
if AM_EN = 0 then
v.mode.amen := '0';
--
v.am.cfg.seq := '0';
v.am.cfg.strict := '0';
v.am.cfg.ovtb := '0';
v.am.cfg.ovdb := '0';
v.am.cfg.act := '0';
v.am.cfg.eact := '0';
v.am.per := (others => '0');
v.am.active := '0';
v.am.lock := '0';
v.am.skipdata := '0';
v.am.rxfull := '0';
v.am.rfreecnt := 0;
v.event.at := '0';
v.am.unread := (others=>'0');
v.am.cfg.erpt := '0';
v.am.cfg.lock := '0';
v.am.cfg.ecgc := '0';
v.am.cnt := (others=>'0');
v.am.rxread := '0';
v.am.txwrite := '0';
v.am.txread := '0';
v.am.apbaddr := (others => '0');
v.am.rxsel := '0';
v.mask.at := '0';
v.cstart := '0';
end if;
if AM_EN = 0 or not PROG_AM_MASK then
v.am.mask := (others=>'0');
v.am.mask_shdw := (others=>'0');
end if;
-- Drive unused bits if automatic slave select is not enabled
if ASEL_EN = 0 then
v.mode.asel := '0';
v.aslvsel := (others => '0');
v.mode.aseldel := (others => '0');
v.mode.tac := '0';
v.aselcnt := (others => '0');
v.cgasel := '0';
end if;
-- Drive unused bits if three-wire mode is not enabled
if TW_EN = 0 then
v.mode.tw := '0';
v.mode.tto := '0';
v.twdir := INPUT;
end if;
if TW_EN = 0 or AM_EN = 0 then
v.twdir2 := INPUT;
end if;
if SLVSEL_EN = 0 then
v.slvsel := (others => '1');
end if;
-- Propagate core enable bit
v.spio.enable := r.mode.en;
-- Synchronize inputs coming from off-chip
v.spii(0) := (spii_miso, spii_mosi, spii_sck, spii_spisel);
v.spii(1) := r.spii(0);
-- Outputs to RAMs
if syncram = 0 then
rx_di <= (others => (others => '0'));
tx_di <= (others => (others => '0'));
rx_ra <= (others => (others => '0'));
rx_wa <= (others => (others => '0'));
tx_ra <= (others => (others => '0'));
tx_wa <= (others => (others => '0'));
rx_read <= (others => '0'); rx_write <= (others => '0');
tx_read <= (others => '0'); tx_write <= (others => '0');
else
-- TX RAM(s) write
-- TX RAM(s) are either written from TX register or AM TX area
for i in 0 to automode loop
tx_di(i) <= ntxd;
end loop;
for i in 0 to automode loop
tx_wa(i) <= r.tdli;
end loop;
tx_write(0) <= tx_wr;
if AM_EN /= 0 then
-- Auto mode present
-- Write from AM register interface writes both RAMs
-- Write from TXD register writes RAM 0
tx_write(automode) <= r.am.txwrite;
tx_write(0) <= tx_wr or r.am.txwrite;
if r.am.txwrite = '1' then
for i in 0 to automode loop
tx_wa(i) <= r.am.apbaddr;
end loop;
end if;
end if;
-- TX RAM(s) read
-- First RAM is read by bit shift logic
tx_read(0) <= tx_rd;
tx_ra(0) <= r.tdfi;
if AM_EN /= 0 then
-- Second RAM is read from register interface
tx_read(automode) <= v.am.txread or r.am.txread;
tx_ra(automode) <= v.am.apbaddr;
end if;
-- RX RAM(s) write
-- RX RAM(s) is always written from receive shift register
for i in 0 to automode loop
rx_di(i) <= r.rxd;
rx_wa(i) <= r.rdli;
end loop;
rx_write(0) <= rx_wr;
if AM_EN /= 0 then
rx_write(automode) <= '0';
end if;
if AM_EN /= 0 and r.mode.amen = '1' then
-- AM active
-- Handle writes from bit shift logic
if r.am.rxsel = '0' then
rx_write(0) <= rx_wr;
rx_write(automode) <= '0';
else
rx_write(0) <= '0';
rx_write(automode) <= rx_wr;
end if;
end if;
-- RX RAM(s) are read via register interface
for i in 0 to automode loop
rx_ra(i) <= r.rdfi;
rx_read(i) <= rx_rd;
end loop;
if AM_EN /= 0 and r.mode.amen = '1' then
if r.am.rxsel = '0' then
rx_read(0) <= '0';
rx_read(automode) <= v.am.rxread;
if v.am.rxread = '1' then
rx_ra(automode) <= v.am.apbaddr;
end if;
else
rx_read(0) <= v.am.rxread;
rx_read(automode) <= '0';
if v.am.rxread = '1' then
rx_ra(0) <= v.am.apbaddr;
end if;
end if;
end if;
if scantest = 1 and (apbi_scanen and apbi_testen) = '1' then
rx_read <= (others => '0'); rx_write <= (others => '0');
tx_read <= (others => '0'); tx_write <= (others => '0');
end if;
end if;
v.spiolb.mosi := v.spio.mosi;
v.spiolb.sck := v.spio.sck;
-- Update registers
rin <= v;
-- Update outputs
apbo_prdata <= apbout;
apbo_pirq <= r.irq;
slvsel <= r.slvsel;
spio_miso <= r.spio.miso;
spio_misooen <= r.spio.misooen;
spio_mosi <= r.spio.mosi;
spio_mosioen <= r.spio.mosioen;
spio_sck <= r.spio.sck;
spio_sckoen <= r.spio.sckoen;
spio_enable <= r.spio.enable;
spio_astart <= r.spio.astart;
spio_aready <= r.spio.aready;
if scantest = 1 and apbi_testen = '1' then
spio_misooen <= apbi_testoen;
spio_mosioen <= apbi_testoen;
spio_sckoen <= apbi_testoen;
end if;
end process comb;
-- FIFOs
fiforams : if syncram /= 0 generate
fifoloop : for i in 0 to automode generate
noft : if ft = 0 generate
rxfifo : syncram_2p
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1)
port map (
rclk => clk,
renable => rx_read(i),
raddress => rx_ra(i),
dataout => rx_do(i),
wclk => clk,
write => rx_write(i),
waddress => rx_wa(i),
datain => rx_di(i));
-- testin => testin);
txfifo : syncram_2p
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1)
port map (
rclk => clk,
renable => tx_read(i),
raddress => tx_ra(i),
dataout => tx_do(i),
wclk => clk,
write => tx_write(i),
waddress => tx_wa(i),
datain => tx_di(i));
-- testin => testin);
end generate noft;
ftfifos : if ft /= 0 generate
ftrxfifo : syncram_2pft
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1,
ft => ft)
port map (
rclk => clk,
renable => rx_read(i),
raddress => rx_ra(i),
dataout => rx_do(i),
wclk => clk,
write => rx_write(i),
waddress => rx_wa(i),
datain => rx_di(i),
error => open);
-- testin => testin);
fttxfifo : syncram_2pft
generic map (
tech => memtech,
abits => fdepth,
dbits => wlen+1,
sepclk => 0,
wrfst => 1,
ft => ft)
port map (
rclk => clk,
renable => tx_read(i),
raddress => tx_ra(i),
dataout => tx_do(i),
wclk => clk,
write => tx_write(i),
waddress => tx_wa(i),
datain => tx_di(i),
error => open);
-- testin => testin);
end generate ftfifos;
end generate fifoloop;
end generate fiforams;
nofiforams : if syncram = 0 generate
rx_do <= (others => (others => '0'));
tx_do <= (others => (others => '0'));
end generate;
-- Registers
reg: process (clk, arstn)
begin -- process reg
if rising_edge(clk) then
r <= rin;
if rstn = '0' then
r.spio.sck <= RES.spio.sck;
r.rbitcnt <= RES.rbitcnt; r.tbitcnt <= RES.tbitcnt;
if RESET_ALL then
r <= RES;
-- Do not use synchronous reset for sync. registers
r.spii <= rin.spii;
end if;
end if;
end if;
if syncrst = 0 and arstn = '0' then
r.spio.misooen <= RES.spio.misooen;
r.spio.mosioen <= RES.spio.mosioen;
r.spio.sckoen <= RES.spio.sckoen;
if SLVSEL_EN /= 0 then
r.slvsel <= RES.slvsel;
end if;
end if;
end process reg;
end architecture rtl;
| gpl-2.0 | cd60262762bf7511fa13e399be968808 | 0.501809 | 3.416155 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_1/zynq_design_1_axi_gpio_0_1_sim_netlist.vhdl | 1 | 51,912 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:29:41 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_gpio_0_1/zynq_design_1_axi_gpio_0_1_sim_netlist.vhdl
-- Design : zynq_design_1_axi_gpio_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_1_GPIO_Core is
port (
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
rst_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_1_GPIO_Core : entity is "GPIO_Core";
end zynq_design_1_axi_gpio_0_1_GPIO_Core;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_1_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair4";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_io_o(7 downto 0) <= \^gpio_io_o\(7 downto 0);
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(7),
Q => D(7),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[1].GPIO_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(6),
Q => D(6),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[2].GPIO_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(5),
Q => D(5),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[3].GPIO_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(4),
Q => D(4),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[4].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(3),
Q => D(3),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[5].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(2),
Q => D(2),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[6].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(1),
Q => D(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_io_o\(0),
Q => D(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7),
Q => \^gpio_io_o\(7),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6),
Q => \^gpio_io_o\(6),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5),
Q => \^gpio_io_o\(5),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => \^gpio_io_o\(4),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => \^gpio_io_o\(3),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => \^gpio_io_o\(2),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => \^gpio_io_o\(1),
R => SS(0)
);
\Not_Dual.gpio_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => \^gpio_io_o\(0),
R => SS(0)
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7),
Q => gpio_io_t(7),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6),
Q => gpio_io_t(6),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5),
Q => gpio_io_t(5),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4),
Q => gpio_io_t(4),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3),
Q => gpio_io_t(3),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2),
Q => gpio_io_t(2),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1),
Q => gpio_io_t(1),
S => SS(0)
);
\Not_Dual.gpio_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => rst_reg(0),
D => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0),
Q => gpio_io_t(0),
S => SS(0)
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_1_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
rst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
start2_reg : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_1_address_decoder : entity is "address_decoder";
end zynq_design_1_axi_gpio_0_1_address_decoder;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_1_address_decoder is
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => start2_reg,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\Not_Dual.ALLOUT_ND.READ_REG_GEN[7].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => gpio_xferAck_Reg,
I3 => GPIO_xferAck_i,
O => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAABAAAA"
)
port map (
I0 => rst_reg,
I1 => Q(1),
I2 => bus2ip_rnw_i_reg,
I3 => Q(0),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => Q(2),
O => E(0)
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(7),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(15),
O => D(7)
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(6),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(14),
O => D(6)
);
\Not_Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(5),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(13),
O => D(5)
);
\Not_Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(4),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(12),
O => D(4)
);
\Not_Dual.gpio_Data_Out[4]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(3),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(11),
O => D(3)
);
\Not_Dual.gpio_Data_Out[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(2),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(10),
O => D(2)
);
\Not_Dual.gpio_Data_Out[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(1),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(9),
O => D(1)
);
\Not_Dual.gpio_Data_Out[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s_axi_wdata(0),
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => Q(1),
I3 => s_axi_wdata(8),
O => D(0)
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => rst_reg,
I1 => Q(0),
I2 => Q(1),
I3 => bus2ip_rnw_i_reg,
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => Q(2),
O => \Not_Dual.gpio_OE_reg[0]\(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_1_slave_attachment is
port (
SR : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_1_slave_attachment : entity is "slave_attachment";
end zynq_design_1_axi_gpio_0_1_slave_attachment;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_1_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.gpio_data_out_reg[0]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \s_axi_rdata_i[7]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair1";
begin
\Not_Dual.gpio_Data_Out_reg[0]\ <= \^not_dual.gpio_data_out_reg[0]\;
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.zynq_design_1_axi_gpio_0_1_address_decoder
port map (
D(7 downto 0) => D(7 downto 0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(2) => bus2ip_addr(0),
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^not_dual.gpio_data_out_reg[0]\,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
rst_reg => \^sr\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
s_axi_wready => \^s_axi_wready\,
start2_reg => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCCACCCC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => state(0),
I3 => state(1),
I4 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(5),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"10"
)
port map (
I0 => state(0),
I1 => state(1),
I2 => s_axi_arvalid,
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => bus2ip_rnw_i06_out,
Q => \^not_dual.gpio_data_out_reg[0]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_in,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => \s_axi_rdata_i[7]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(0),
Q => s_axi_rdata(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(1),
Q => s_axi_rdata(1),
R => \^sr\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(2),
Q => s_axi_rdata(2),
R => \^sr\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(3),
Q => s_axi_rdata(3),
R => \^sr\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(4),
Q => s_axi_rdata(4),
R => \^sr\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(5),
Q => s_axi_rdata(5),
R => \^sr\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(6),
Q => s_axi_rdata(6),
R => \^sr\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \s_axi_rdata_i[7]_i_1_n_0\,
D => Q(7),
Q => s_axi_rdata(7),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => p_0_out(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_1_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 7 downto 0 );
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_1_axi_lite_ipif : entity is "axi_lite_ipif";
end zynq_design_1_axi_gpio_0_1_axi_lite_ipif;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_1_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.zynq_design_1_axi_gpio_0_1_slave_attachment
port map (
D(7 downto 0) => D(7 downto 0),
E(0) => E(0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => \Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => bus2ip_rnw,
\Not_Dual.gpio_OE_reg[0]\(0) => \Not_Dual.gpio_OE_reg[0]\(0),
Q(7 downto 0) => Q(7 downto 0),
SR => bus2ip_reset,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => s_axi_rdata(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(15 downto 0) => s_axi_wdata(15 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_1_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 7 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is 1;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of zynq_design_1_axi_gpio_0_1_axi_gpio : entity is "LOGICORE";
end zynq_design_1_axi_gpio_0_1_axi_gpio;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_1_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_6 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC;
signal DBus_Reg : STD_LOGIC_VECTOR ( 0 to 7 );
signal GPIO_xferAck_i : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_core_1_n_19 : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 24 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 24 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7 downto 0) <= \^s_axi_rdata\(7 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.zynq_design_1_axi_gpio_0_1_axi_lite_ipif
port map (
D(7) => DBus_Reg(0),
D(6) => DBus_Reg(1),
D(5) => DBus_Reg(2),
D(4) => DBus_Reg(3),
D(3) => DBus_Reg(4),
D(2) => DBus_Reg(5),
D(1) => DBus_Reg(6),
D(0) => DBus_Reg(7),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.ALLOUT_ND.READ_REG_GEN[0].GPIO_DBus_i_reg[24]\ => AXI_LITE_IPIF_I_n_17,
\Not_Dual.gpio_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_7,
Q(7) => ip2bus_data_i_D1(24),
Q(6) => ip2bus_data_i_D1(25),
Q(5) => ip2bus_data_i_D1(26),
Q(4) => ip2bus_data_i_D1(27),
Q(3) => ip2bus_data_i_D1(28),
Q(2) => ip2bus_data_i_D1(29),
Q(1) => ip2bus_data_i_D1(30),
Q(0) => ip2bus_data_i_D1(31),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(7 downto 0) => \^s_axi_rdata\(7 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(15 downto 8) => s_axi_wdata(31 downto 24),
s_axi_wdata(7 downto 0) => s_axi_wdata(7 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
gpio_core_1: entity work.zynq_design_1_axi_gpio_0_1_GPIO_Core
port map (
D(7) => ip2bus_data(24),
D(6) => ip2bus_data(25),
D(5) => ip2bus_data(26),
D(4) => ip2bus_data(27),
D(3) => ip2bus_data(28),
D(2) => ip2bus_data(29),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
E(0) => AXI_LITE_IPIF_I_n_6,
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(7) => DBus_Reg(0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(6) => DBus_Reg(1),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(5) => DBus_Reg(2),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(4) => DBus_Reg(3),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(3) => DBus_Reg(4),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(2) => DBus_Reg(5),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(1) => DBus_Reg(6),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\(0) => DBus_Reg(7),
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_17,
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => gpio_io_t(7 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_19,
rst_reg(0) => AXI_LITE_IPIF_I_n_7,
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(24),
Q => ip2bus_data_i_D1(24),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(25),
Q => ip2bus_data_i_D1(25),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(26),
Q => ip2bus_data_i_D1(26),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(27),
Q => ip2bus_data_i_D1(27),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(28),
Q => ip2bus_data_i_D1(28),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(29),
Q => ip2bus_data_i_D1(29),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_19,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_gpio_0_1 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_axi_gpio_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_axi_gpio_0_1 : entity is "zynq_design_1_axi_gpio_0_1,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_gpio_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zynq_design_1_axi_gpio_0_1 : entity is "axi_gpio,Vivado 2017.2";
end zynq_design_1_axi_gpio_0_1;
architecture STRUCTURE of zynq_design_1_axi_gpio_0_1 is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 1;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 8;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.zynq_design_1_axi_gpio_0_1_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(7 downto 0) => B"00000000",
gpio_io_o(7 downto 0) => gpio_io_o(7 downto 0),
gpio_io_t(7 downto 0) => NLW_U0_gpio_io_t_UNCONNECTED(7 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | 3c22c75d3dcb80206e7ac76b6bfc6496 | 0.551375 | 2.650194 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/tbufmem.vhd | 1 | 2,221 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: tbufmem
-- File: tbufmem.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: 128-bit trace buffer memory (CPU/AHB)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity tbufmem is
generic (
tech : integer := 0;
tbuf : integer := 0; -- trace buf size in kB (0 - no trace buffer)
testen : integer := 0
);
port (
clk : in std_ulogic;
di : in tracebuf_in_type;
do : out tracebuf_out_type);
end;
architecture rtl of tbufmem is
constant ADDRBITS : integer := 10 + log2(tbuf) - 4;
signal enable : std_logic_vector(1 downto 0);
begin
enable <= di.enable & di.enable;
mem0 : for i in 0 to 1 generate
ram0 : syncram64 generic map (tech => tech, abits => addrbits, testen => testen)
port map ( clk, di.addr(addrbits-1 downto 0), di.data(((i*64)+63) downto (i*64)),
do.data(((i*64)+63) downto (i*64)), enable ,di.write(i*2+1 downto i*2),
di.diag);
end generate;
end;
| gpl-2.0 | e1e2445f483320d8a9357f00e4dd12e9 | 0.60018 | 3.973166 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2.1/22465fc93bb76d40/zqynq_lab_1_design_xbar_0_sim_netlist.vhdl | 1 | 857,760 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 17:41:03 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter is
port (
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : out STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast_i0 : out STD_LOGIC;
\m_axi_arqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
ADDRESS_HIT_0 : out STD_LOGIC;
match : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : out STD_LOGIC;
p_39_in : out STD_LOGIC;
p_57_in : out STD_LOGIC;
p_75_in : out STD_LOGIC;
\gen_master_slots[4].r_issuing_cnt_reg[32]\ : out STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_arready_4 : in STD_LOGIC;
p_23_in : in STD_LOGIC;
\read_cs__0\ : in STD_LOGIC;
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
\r_cmd_pop_0__1\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
\r_cmd_pop_1__1\ : in STD_LOGIC;
\r_cmd_pop_3__1\ : in STD_LOGIC;
\r_cmd_pop_2__1\ : in STD_LOGIC;
m_valid_i : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
\s_axi_araddr[24]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter is
signal \^address_hit_0\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^aa_mi_arvalid\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_3_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \^m_axi_arqos[15]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^match\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
signal st_aa_artarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_rid_i[11]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[10]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[18]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[19]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[19]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[26]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair2";
begin
ADDRESS_HIT_0 <= \^address_hit_0\;
D(2 downto 0) <= \^d\(2 downto 0);
Q(0) <= \^q\(0);
aa_mi_arvalid <= \^aa_mi_arvalid\;
\m_axi_arqos[15]\(68 downto 0) <= \^m_axi_arqos[15]\(68 downto 0);
match <= \^match\;
\gen_axi.s_axi_rid_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
I2 => mi_arready_4,
I3 => p_23_in,
O => \gen_axi.s_axi_rid_i_reg[11]\(0)
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55035500"
)
port map (
I0 => \read_cs__0\,
I1 => \^m_axi_arqos[15]\(45),
I2 => \^m_axi_arqos[15]\(44),
I3 => p_23_in,
I4 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
O => s_axi_rlast_i0
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \^m_axi_arqos[15]\(46),
I1 => \^m_axi_arqos[15]\(47),
I2 => \^m_axi_arqos[15]\(48),
I3 => \^m_axi_arqos[15]\(49),
I4 => \^m_axi_arqos[15]\(51),
I5 => \^m_axi_arqos[15]\(50),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \r_cmd_pop_0__1\,
I2 => m_axi_arready(0),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(0),
I5 => r_issuing_cnt(1),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I1 => r_issuing_cnt(1),
I2 => r_issuing_cnt(2),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(1),
I1 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I2 => r_issuing_cnt(3),
I3 => r_issuing_cnt(2),
O => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(0),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(0),
O => p_93_in
);
\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \r_cmd_pop_0__1\,
I2 => m_axi_arready(0),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(0),
I5 => r_issuing_cnt(1),
O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I1 => r_issuing_cnt(5),
I2 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(5),
I1 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I2 => r_issuing_cnt(7),
I3 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(1),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(1),
O => p_75_in
);
\gen_master_slots[1].r_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \r_cmd_pop_1__1\,
I2 => m_axi_arready(1),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(1),
I5 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \r_cmd_pop_1__1\,
I2 => m_axi_arready(1),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(1),
I5 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0)
);
\gen_master_slots[2].r_issuing_cnt[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(8),
I1 => \r_cmd_pop_2__1\,
I2 => m_axi_arready(2),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(2),
I5 => r_issuing_cnt(9),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0)
);
\gen_master_slots[2].r_issuing_cnt[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\,
I1 => r_issuing_cnt(9),
I2 => r_issuing_cnt(10),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(9),
I1 => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\,
I2 => r_issuing_cnt(11),
I3 => r_issuing_cnt(10),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(2),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(2),
O => p_57_in
);
\gen_master_slots[2].r_issuing_cnt[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(8),
I1 => \r_cmd_pop_2__1\,
I2 => m_axi_arready(2),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(2),
I5 => r_issuing_cnt(9),
O => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\
);
\gen_master_slots[3].r_issuing_cnt[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(12),
I1 => \r_cmd_pop_3__1\,
I2 => m_axi_arready(3),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(3),
I5 => r_issuing_cnt(13),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0)
);
\gen_master_slots[3].r_issuing_cnt[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\,
I1 => r_issuing_cnt(13),
I2 => r_issuing_cnt(14),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(13),
I1 => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\,
I2 => r_issuing_cnt(15),
I3 => r_issuing_cnt(14),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(3),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(3),
O => p_39_in
);
\gen_master_slots[3].r_issuing_cnt[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(12),
I1 => \r_cmd_pop_3__1\,
I2 => m_axi_arready(3),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(3),
I5 => r_issuing_cnt(13),
O => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\
);
\gen_master_slots[4].r_issuing_cnt[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"807F0080"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
I2 => mi_arready_4,
I3 => \r_cmd_pop_4__1\,
I4 => r_issuing_cnt(16),
O => \gen_master_slots[4].r_issuing_cnt_reg[32]\
);
\gen_no_arbiter.m_mesg_i[11]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_mi_arvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(0),
Q => \^m_axi_arqos[15]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(10),
Q => \^m_axi_arqos[15]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(11),
Q => \^m_axi_arqos[15]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(12),
Q => \^m_axi_arqos[15]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(13),
Q => \^m_axi_arqos[15]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(14),
Q => \^m_axi_arqos[15]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(15),
Q => \^m_axi_arqos[15]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(16),
Q => \^m_axi_arqos[15]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(17),
Q => \^m_axi_arqos[15]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(18),
Q => \^m_axi_arqos[15]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(19),
Q => \^m_axi_arqos[15]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(1),
Q => \^m_axi_arqos[15]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(20),
Q => \^m_axi_arqos[15]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(21),
Q => \^m_axi_arqos[15]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(22),
Q => \^m_axi_arqos[15]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(23),
Q => \^m_axi_arqos[15]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(24),
Q => \^m_axi_arqos[15]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(25),
Q => \^m_axi_arqos[15]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(26),
Q => \^m_axi_arqos[15]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(27),
Q => \^m_axi_arqos[15]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(28),
Q => \^m_axi_arqos[15]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(29),
Q => \^m_axi_arqos[15]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(2),
Q => \^m_axi_arqos[15]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(30),
Q => \^m_axi_arqos[15]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(31),
Q => \^m_axi_arqos[15]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(32),
Q => \^m_axi_arqos[15]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(33),
Q => \^m_axi_arqos[15]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(34),
Q => \^m_axi_arqos[15]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(35),
Q => \^m_axi_arqos[15]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(36),
Q => \^m_axi_arqos[15]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(37),
Q => \^m_axi_arqos[15]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(38),
Q => \^m_axi_arqos[15]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(39),
Q => \^m_axi_arqos[15]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(3),
Q => \^m_axi_arqos[15]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(40),
Q => \^m_axi_arqos[15]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(41),
Q => \^m_axi_arqos[15]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(42),
Q => \^m_axi_arqos[15]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(43),
Q => \^m_axi_arqos[15]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(44),
Q => \^m_axi_arqos[15]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(45),
Q => \^m_axi_arqos[15]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(46),
Q => \^m_axi_arqos[15]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(47),
Q => \^m_axi_arqos[15]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(48),
Q => \^m_axi_arqos[15]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(49),
Q => \^m_axi_arqos[15]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(4),
Q => \^m_axi_arqos[15]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(50),
Q => \^m_axi_arqos[15]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(51),
Q => \^m_axi_arqos[15]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(52),
Q => \^m_axi_arqos[15]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(53),
Q => \^m_axi_arqos[15]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(54),
Q => \^m_axi_arqos[15]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(55),
Q => \^m_axi_arqos[15]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(56),
Q => \^m_axi_arqos[15]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(57),
Q => \^m_axi_arqos[15]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(58),
Q => \^m_axi_arqos[15]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(5),
Q => \^m_axi_arqos[15]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(59),
Q => \^m_axi_arqos[15]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(60),
Q => \^m_axi_arqos[15]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(61),
Q => \^m_axi_arqos[15]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(62),
Q => \^m_axi_arqos[15]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(63),
Q => \^m_axi_arqos[15]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(64),
Q => \^m_axi_arqos[15]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(6),
Q => \^m_axi_arqos[15]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(65),
Q => \^m_axi_arqos[15]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(66),
Q => \^m_axi_arqos[15]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(67),
Q => \^m_axi_arqos[15]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(68),
Q => \^m_axi_arqos[15]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(7),
Q => \^m_axi_arqos[15]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(8),
Q => \^m_axi_arqos[15]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(9),
Q => \^m_axi_arqos[15]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^address_hit_0\,
I1 => \^match\,
O => st_aa_artarget_hot(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
I4 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^address_hit_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I1 => \s_axi_arqos[3]\(29),
I2 => \s_axi_arqos[3]\(28),
I3 => \s_axi_arqos[3]\(31),
I4 => \s_axi_arqos[3]\(30),
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \s_axi_arqos[3]\(34),
I1 => \s_axi_arqos[3]\(35),
I2 => \s_axi_arqos[3]\(33),
I3 => \s_axi_arqos[3]\(32),
I4 => \s_axi_arqos[3]\(37),
I5 => \s_axi_arqos[3]\(36),
O => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
\gen_no_arbiter.m_target_hot_i[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
I4 => \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(1)
);
\gen_no_arbiter.m_target_hot_i[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => \s_axi_arqos[3]\(35),
I1 => \s_axi_arqos[3]\(34),
I2 => \s_axi_arqos[3]\(32),
I3 => \s_axi_arqos[3]\(33),
I4 => \s_axi_arqos[3]\(36),
I5 => \s_axi_arqos[3]\(37),
O => \gen_no_arbiter.m_target_hot_i[2]_i_2__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\,
I1 => \s_axi_arqos[3]\(25),
I2 => \s_axi_arqos[3]\(26),
I3 => \s_axi_arqos[3]\(27),
I4 => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\,
I5 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(2)
);
\gen_no_arbiter.m_target_hot_i[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \s_axi_arqos[3]\(32),
I1 => \s_axi_arqos[3]\(33),
I2 => \s_axi_arqos[3]\(34),
I3 => \s_axi_arqos[3]\(35),
I4 => \s_axi_arqos[3]\(37),
I5 => \s_axi_arqos[3]\(36),
O => \gen_no_arbiter.m_target_hot_i[3]_i_2__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \s_axi_arqos[3]\(31),
I1 => \s_axi_arqos[3]\(30),
I2 => \s_axi_arqos[3]\(29),
I3 => \s_axi_arqos[3]\(28),
O => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_arqos[3]\(40),
I1 => \s_axi_arqos[3]\(41),
I2 => \s_axi_arqos[3]\(38),
I3 => \s_axi_arqos[3]\(39),
I4 => \s_axi_arqos[3]\(43),
I5 => \s_axi_arqos[3]\(42),
O => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
\gen_no_arbiter.m_target_hot_i[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^d\(1),
I1 => \^d\(2),
I2 => \^d\(0),
I3 => \^address_hit_0\,
O => \^match\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_artarget_hot(0),
Q => aa_mi_artarget_hot(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(0),
Q => aa_mi_artarget_hot(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(1),
Q => aa_mi_artarget_hot(2),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(2),
Q => aa_mi_artarget_hot(3),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \s_axi_araddr[24]\(0),
Q => \^q\(0),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"DC"
)
port map (
I0 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
I1 => m_valid_i,
I2 => \^aa_mi_arvalid\,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF88800000000"
)
port map (
I0 => m_axi_arready(2),
I1 => aa_mi_artarget_hot(2),
I2 => m_axi_arready(1),
I3 => aa_mi_artarget_hot(1),
I4 => \gen_no_arbiter.m_valid_i_i_3_n_0\,
I5 => \^aa_mi_arvalid\,
O => \gen_no_arbiter.m_valid_i_i_2_n_0\
);
\gen_no_arbiter.m_valid_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => m_axi_arready(0),
I2 => \^q\(0),
I3 => mi_arready_4,
I4 => m_axi_arready(3),
I5 => aa_mi_artarget_hot(3),
O => \gen_no_arbiter.m_valid_i_i_3_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^aa_mi_arvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => E(0),
Q => S_AXI_ARREADY(0),
R => '0'
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(1),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(2),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(2)
);
\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(3),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 is
port (
ss_aa_awready : out STD_LOGIC;
aa_sa_awvalid : out STD_LOGIC;
\mi_awready_mux__3\ : out STD_LOGIC;
\s_ready_i0__1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_84_in : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
p_66_in : out STD_LOGIC;
p_48_in : out STD_LOGIC;
p_101_in : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
write_cs01_out : out STD_LOGIC;
ADDRESS_HIT_0 : out STD_LOGIC;
match : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
\sa_wm_awready_mux__3\ : out STD_LOGIC;
\gen_master_slots[4].w_issuing_cnt_reg[32]\ : out STD_LOGIC;
\m_axi_awqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
mi_awready_4 : in STD_LOGIC;
\s_axi_awqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[24]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 is
signal \^address_hit_0\ : STD_LOGIC;
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^aa_sa_awvalid\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC;
signal \^match\ : STD_LOGIC;
signal \^mi_awready_mux__3\ : STD_LOGIC;
signal \^s_ready_i0__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal s_ready_i2 : STD_LOGIC;
signal \^ss_aa_awready\ : STD_LOGIC;
signal st_aa_awtarget_hot : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^write_cs01_out\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_2\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_4\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_4\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[0]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[4]_i_2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair14";
begin
ADDRESS_HIT_0 <= \^address_hit_0\;
D(2 downto 0) <= \^d\(2 downto 0);
Q(4 downto 0) <= \^q\(4 downto 0);
aa_sa_awvalid <= \^aa_sa_awvalid\;
match <= \^match\;
\mi_awready_mux__3\ <= \^mi_awready_mux__3\;
\s_ready_i0__1\(0) <= \^s_ready_i0__1\(0);
ss_aa_awready <= \^ss_aa_awready\;
write_cs01_out <= \^write_cs01_out\;
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => mi_awready_4,
I1 => \^q\(4),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => \^write_cs01_out\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(0),
I1 => \^q\(0),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_101_in
);
\gen_master_slots[1].w_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(1),
I1 => \^q\(1),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_84_in
);
\gen_master_slots[2].w_issuing_cnt[19]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(2),
I1 => \^q\(2),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_66_in
);
\gen_master_slots[3].w_issuing_cnt[27]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(3),
I1 => \^q\(3),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_48_in
);
\gen_master_slots[4].w_issuing_cnt[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"95552AAA"
)
port map (
I0 => \^write_cs01_out\,
I1 => s_axi_bready(0),
I2 => p_46_out,
I3 => \chosen_reg[4]\(0),
I4 => w_issuing_cnt(0),
O => \gen_master_slots[4].w_issuing_cnt_reg[32]\
);
\gen_no_arbiter.m_mesg_i[11]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_sa_awvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(0),
Q => \m_axi_awqos[15]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(10),
Q => \m_axi_awqos[15]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(11),
Q => \m_axi_awqos[15]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(12),
Q => \m_axi_awqos[15]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(13),
Q => \m_axi_awqos[15]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(14),
Q => \m_axi_awqos[15]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(15),
Q => \m_axi_awqos[15]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(16),
Q => \m_axi_awqos[15]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(17),
Q => \m_axi_awqos[15]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(18),
Q => \m_axi_awqos[15]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(19),
Q => \m_axi_awqos[15]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(1),
Q => \m_axi_awqos[15]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(20),
Q => \m_axi_awqos[15]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(21),
Q => \m_axi_awqos[15]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(22),
Q => \m_axi_awqos[15]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(23),
Q => \m_axi_awqos[15]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(24),
Q => \m_axi_awqos[15]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(25),
Q => \m_axi_awqos[15]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(26),
Q => \m_axi_awqos[15]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(27),
Q => \m_axi_awqos[15]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(28),
Q => \m_axi_awqos[15]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(29),
Q => \m_axi_awqos[15]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(2),
Q => \m_axi_awqos[15]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(30),
Q => \m_axi_awqos[15]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(31),
Q => \m_axi_awqos[15]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(32),
Q => \m_axi_awqos[15]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(33),
Q => \m_axi_awqos[15]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(34),
Q => \m_axi_awqos[15]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(35),
Q => \m_axi_awqos[15]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(36),
Q => \m_axi_awqos[15]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(37),
Q => \m_axi_awqos[15]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(38),
Q => \m_axi_awqos[15]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(39),
Q => \m_axi_awqos[15]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(3),
Q => \m_axi_awqos[15]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(40),
Q => \m_axi_awqos[15]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(41),
Q => \m_axi_awqos[15]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(42),
Q => \m_axi_awqos[15]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(43),
Q => \m_axi_awqos[15]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(44),
Q => \m_axi_awqos[15]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(45),
Q => \m_axi_awqos[15]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(46),
Q => \m_axi_awqos[15]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(47),
Q => \m_axi_awqos[15]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(48),
Q => \m_axi_awqos[15]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(49),
Q => \m_axi_awqos[15]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(4),
Q => \m_axi_awqos[15]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(50),
Q => \m_axi_awqos[15]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(51),
Q => \m_axi_awqos[15]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(52),
Q => \m_axi_awqos[15]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(53),
Q => \m_axi_awqos[15]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(54),
Q => \m_axi_awqos[15]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(55),
Q => \m_axi_awqos[15]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(56),
Q => \m_axi_awqos[15]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(57),
Q => \m_axi_awqos[15]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(58),
Q => \m_axi_awqos[15]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(5),
Q => \m_axi_awqos[15]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(59),
Q => \m_axi_awqos[15]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(60),
Q => \m_axi_awqos[15]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(61),
Q => \m_axi_awqos[15]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(62),
Q => \m_axi_awqos[15]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(63),
Q => \m_axi_awqos[15]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(64),
Q => \m_axi_awqos[15]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(6),
Q => \m_axi_awqos[15]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(65),
Q => \m_axi_awqos[15]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(66),
Q => \m_axi_awqos[15]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(67),
Q => \m_axi_awqos[15]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(68),
Q => \m_axi_awqos[15]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(7),
Q => \m_axi_awqos[15]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(8),
Q => \m_axi_awqos[15]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_awqos[3]\(9),
Q => \m_axi_awqos[15]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^address_hit_0\,
I1 => \^match\,
O => st_aa_awtarget_hot(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_awqos[3]\(29),
I1 => \s_axi_awqos[3]\(28),
I2 => \s_axi_awqos[3]\(31),
I3 => \s_axi_awqos[3]\(30),
I4 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^address_hit_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I1 => \s_axi_awqos[3]\(29),
I2 => \s_axi_awqos[3]\(28),
I3 => \s_axi_awqos[3]\(31),
I4 => \s_axi_awqos[3]\(30),
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(0)
);
\gen_no_arbiter.m_target_hot_i[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \s_axi_awqos[3]\(34),
I1 => \s_axi_awqos[3]\(35),
I2 => \s_axi_awqos[3]\(33),
I3 => \s_axi_awqos[3]\(32),
I4 => \s_axi_awqos[3]\(37),
I5 => \s_axi_awqos[3]\(36),
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
\gen_no_arbiter.m_target_hot_i[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_awqos[3]\(29),
I1 => \s_axi_awqos[3]\(28),
I2 => \s_axi_awqos[3]\(31),
I3 => \s_axi_awqos[3]\(30),
I4 => \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(1)
);
\gen_no_arbiter.m_target_hot_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => \s_axi_awqos[3]\(35),
I1 => \s_axi_awqos[3]\(34),
I2 => \s_axi_awqos[3]\(32),
I3 => \s_axi_awqos[3]\(33),
I4 => \s_axi_awqos[3]\(36),
I5 => \s_axi_awqos[3]\(37),
O => \gen_no_arbiter.m_target_hot_i[2]_i_2_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0002000000000000"
)
port map (
I0 => \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\,
I1 => \s_axi_awqos[3]\(25),
I2 => \s_axi_awqos[3]\(26),
I3 => \s_axi_awqos[3]\(27),
I4 => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\,
I5 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\,
O => \^d\(2)
);
\gen_no_arbiter.m_target_hot_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \s_axi_awqos[3]\(32),
I1 => \s_axi_awqos[3]\(33),
I2 => \s_axi_awqos[3]\(34),
I3 => \s_axi_awqos[3]\(35),
I4 => \s_axi_awqos[3]\(37),
I5 => \s_axi_awqos[3]\(36),
O => \gen_no_arbiter.m_target_hot_i[3]_i_2_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \s_axi_awqos[3]\(31),
I1 => \s_axi_awqos[3]\(30),
I2 => \s_axi_awqos[3]\(29),
I3 => \s_axi_awqos[3]\(28),
O => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_awqos[3]\(40),
I1 => \s_axi_awqos[3]\(41),
I2 => \s_axi_awqos[3]\(38),
I3 => \s_axi_awqos[3]\(39),
I4 => \s_axi_awqos[3]\(43),
I5 => \s_axi_awqos[3]\(42),
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
\gen_no_arbiter.m_target_hot_i[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^d\(1),
I1 => \^d\(2),
I2 => \^d\(0),
I3 => \^address_hit_0\,
O => \^match\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_awtarget_hot(0),
Q => \^q\(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(0),
Q => \^q\(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(1),
Q => \^q\(2),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \^d\(2),
Q => \^q\(3),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \s_axi_awaddr[24]\(0),
Q => \^q\(4),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1F00"
)
port map (
I0 => m_ready_d(1),
I1 => \^mi_awready_mux__3\,
I2 => \^s_ready_i0__1\(0),
I3 => \^aa_sa_awvalid\,
I4 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1__0_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1__0_n_0\,
Q => \^aa_sa_awvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_34\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^ss_aa_awready\,
I1 => s_axi_awvalid(0),
I2 => m_ready_d_0(0),
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => E(0),
Q => \^ss_aa_awready\,
R => '0'
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(0),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(2),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(2)
);
\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(3),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(3)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(4),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(2),
I4 => \^q\(3),
O => \sa_wm_awready_mux__3\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \m_ready_d[1]_i_4_n_0\,
I1 => \^q\(1),
I2 => m_axi_awready(1),
I3 => \^q\(2),
I4 => m_axi_awready(2),
O => \^mi_awready_mux__3\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => m_ready_d(0),
I1 => \^q\(3),
I2 => \^q\(2),
I3 => \^q\(1),
I4 => \^q\(0),
I5 => \^q\(4),
O => \^s_ready_i0__1\(0)
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^q\(0),
I1 => m_axi_awready(0),
I2 => \^q\(4),
I3 => mi_awready_4,
I4 => m_axi_awready(3),
I5 => \^q\(3),
O => \m_ready_d[1]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].w_issuing_cnt_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
\s_axi_bvalid[0]\ : out STD_LOGIC;
resp_select : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
f_mux4_return : out STD_LOGIC_VECTOR ( 13 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
p_84_in : in STD_LOGIC;
p_66_in : in STD_LOGIC;
p_48_in : in STD_LOGIC;
p_101_in : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
match : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
p_0_out : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
st_mr_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
st_mr_bmesg : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_68_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_24_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_25_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_26_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_36_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_37_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_38_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_39_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6_n_0\ : STD_LOGIC;
signal last_rr_hot : STD_LOGIC;
signal \last_rr_hot[0]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_4__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_5__0_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_5_in6_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in9_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal \^resp_select\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \resp_select__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_bvalid[0]\ : STD_LOGIC;
signal \^s_ready_i_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \w_cmd_pop_0__0\ : STD_LOGIC;
signal \w_cmd_pop_1__0\ : STD_LOGIC;
signal \w_cmd_pop_2__0\ : STD_LOGIC;
signal \w_cmd_pop_3__0\ : STD_LOGIC;
signal \w_cmd_pop_4__0\ : STD_LOGIC;
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[3]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_3\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_3\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_3\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_2__0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_3__0\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \last_rr_hot[1]_i_2__0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_3__0\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_2__0\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_3__0\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_1\ : label is "soft_lutpair156";
begin
SR(0) <= \^sr\(0);
m_valid_i <= \^m_valid_i\;
resp_select(0) <= \^resp_select\(0);
\s_axi_bvalid[0]\ <= \^s_axi_bvalid[0]\;
s_ready_i_reg(4 downto 0) <= \^s_ready_i_reg\(4 downto 0);
\chosen[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBB8"
)
port map (
I0 => s_axi_bready(0),
I1 => \^s_axi_bvalid[0]\,
I2 => p_46_out,
I3 => p_128_out,
I4 => p_108_out,
I5 => m_valid_i_reg,
O => need_arbitration
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(0),
Q => \^s_ready_i_reg\(0),
R => \^sr\(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(1),
Q => \^s_ready_i_reg\(1),
R => \^sr\(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(2),
Q => \^s_ready_i_reg\(2),
R => \^sr\(0)
);
\chosen_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(3),
Q => \^s_ready_i_reg\(3),
R => \^sr\(0)
);
\chosen_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(4),
Q => \^s_ready_i_reg\(4),
R => \^sr\(0)
);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(36),
I1 => st_mr_bid(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(24),
I5 => st_mr_bid(12),
O => f_mux4_return(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(46),
I1 => st_mr_bid(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(34),
I5 => st_mr_bid(22),
O => f_mux4_return(10)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_ready_i_reg\(4),
I1 => p_46_out,
O => \^resp_select\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(47),
I1 => st_mr_bid(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(35),
I5 => st_mr_bid(23),
O => f_mux4_return(11)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_68_out,
I1 => \^s_ready_i_reg\(3),
I2 => p_108_out,
I3 => \^s_ready_i_reg\(1),
O => \resp_select__0\(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bmesg(6),
I1 => st_mr_bmesg(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bmesg(4),
I5 => st_mr_bmesg(2),
O => f_mux4_return(12)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bmesg(7),
I1 => st_mr_bmesg(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bmesg(5),
I5 => st_mr_bmesg(3),
O => f_mux4_return(13)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(37),
I1 => st_mr_bid(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(25),
I5 => st_mr_bid(13),
O => f_mux4_return(1)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(38),
I1 => st_mr_bid(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(26),
I5 => st_mr_bid(14),
O => f_mux4_return(2)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(39),
I1 => st_mr_bid(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(27),
I5 => st_mr_bid(15),
O => f_mux4_return(3)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(40),
I1 => st_mr_bid(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(28),
I5 => st_mr_bid(16),
O => f_mux4_return(4)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(41),
I1 => st_mr_bid(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(29),
I5 => st_mr_bid(17),
O => f_mux4_return(5)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(42),
I1 => st_mr_bid(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(30),
I5 => st_mr_bid(18),
O => f_mux4_return(6)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(43),
I1 => st_mr_bid(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(31),
I5 => st_mr_bid(19),
O => f_mux4_return(7)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(44),
I1 => st_mr_bid(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(32),
I5 => st_mr_bid(20),
O => f_mux4_return(8)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(45),
I1 => st_mr_bid(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(33),
I5 => st_mr_bid(21),
O => f_mux4_return(9)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(1),
I1 => w_issuing_cnt(2),
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(3),
I4 => \w_cmd_pop_0__0\,
I5 => p_101_in,
O => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(0),
I1 => p_128_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_0__0\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(5),
I1 => w_issuing_cnt(6),
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(7),
I4 => \w_cmd_pop_1__0\,
I5 => p_84_in,
O => E(0)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(1),
I1 => p_108_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_1__0\
);
\gen_master_slots[2].w_issuing_cnt[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(9),
I1 => w_issuing_cnt(10),
I2 => w_issuing_cnt(8),
I3 => w_issuing_cnt(11),
I4 => \w_cmd_pop_2__0\,
I5 => p_66_in,
O => \gen_master_slots[2].w_issuing_cnt_reg[16]\(0)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(2),
I1 => p_88_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_2__0\
);
\gen_master_slots[3].w_issuing_cnt[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(13),
I1 => w_issuing_cnt(14),
I2 => w_issuing_cnt(12),
I3 => w_issuing_cnt(15),
I4 => \w_cmd_pop_3__0\,
I5 => p_48_in,
O => \gen_master_slots[3].w_issuing_cnt_reg[24]\(0)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(3),
I1 => p_68_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_3__0\
);
\gen_no_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\,
I5 => aa_sa_awvalid,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_24\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8888888AAAAAAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
I1 => \gen_multi_thread.accept_cnt_reg[0]\,
I2 => \^s_axi_bvalid[0]\,
I3 => p_0_out,
I4 => s_axi_bready(0),
I5 => Q(0),
O => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_25\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_36_n_0\,
I1 => \s_axi_awaddr[30]\(0),
I2 => ADDRESS_HIT_0,
I3 => \gen_no_arbiter.s_ready_i[0]_i_37_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_26\: unisim.vcomponents.LUT4
generic map(
INIT => X"ECA0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_38_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_39_n_0\,
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_26_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(4),
I1 => p_46_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_36\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_1__0\,
I1 => w_issuing_cnt(4),
I2 => w_issuing_cnt(7),
I3 => w_issuing_cnt(5),
I4 => w_issuing_cnt(6),
O => \gen_no_arbiter.s_ready_i[0]_i_36_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_37\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_0__0\,
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(3),
I3 => w_issuing_cnt(1),
I4 => w_issuing_cnt(2),
O => \gen_no_arbiter.s_ready_i[0]_i_37_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_38\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_2__0\,
I1 => w_issuing_cnt(8),
I2 => w_issuing_cnt(11),
I3 => w_issuing_cnt(9),
I4 => w_issuing_cnt(10),
O => \gen_no_arbiter.s_ready_i[0]_i_38_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_39\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_3__0\,
I1 => w_issuing_cnt(12),
I2 => w_issuing_cnt(15),
I3 => w_issuing_cnt(13),
I4 => w_issuing_cnt(14),
O => \gen_no_arbiter.s_ready_i[0]_i_39_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8AAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_26_n_0\,
I3 => \w_cmd_pop_4__0\,
I4 => match,
I5 => w_issuing_cnt(16),
O => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\
);
\last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_128_out,
I1 => p_68_out,
I2 => p_46_out,
I3 => \last_rr_hot[0]_i_2__0_n_0\,
I4 => \last_rr_hot[0]_i_3__0_n_0\,
I5 => p_6_in,
O => next_rr_hot(0)
);
\last_rr_hot[0]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_5_in6_in,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_108_out,
I3 => p_88_out,
O => \last_rr_hot[0]_i_2__0_n_0\
);
\last_rr_hot[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_46_out,
I1 => p_7_in9_in,
I2 => p_8_in,
O => \last_rr_hot[0]_i_3__0_n_0\
);
\last_rr_hot[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_108_out,
I1 => p_128_out,
I2 => p_46_out,
I3 => \last_rr_hot[1]_i_2__0_n_0\,
I4 => \last_rr_hot[4]_i_4__0_n_0\,
I5 => p_7_in9_in,
O => next_rr_hot(1)
);
\last_rr_hot[1]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_6_in,
I1 => p_5_in6_in,
I2 => p_88_out,
I3 => p_68_out,
O => \last_rr_hot[1]_i_2__0_n_0\
);
\last_rr_hot[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_88_out,
I1 => m_valid_i_reg_0,
I2 => \last_rr_hot[4]_i_5__0_n_0\,
I3 => p_46_out,
I4 => \last_rr_hot[2]_i_3__0_n_0\,
I5 => p_8_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_108_out,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_5_in6_in,
O => \last_rr_hot[2]_i_3__0_n_0\
);
\last_rr_hot[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_68_out,
I1 => p_108_out,
I2 => p_88_out,
I3 => \last_rr_hot[3]_i_2__0_n_0\,
I4 => \last_rr_hot[3]_i_3__0_n_0\,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(3)
);
\last_rr_hot[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_8_in,
I1 => p_7_in9_in,
I2 => p_46_out,
I3 => p_128_out,
O => \last_rr_hot[3]_i_2__0_n_0\
);
\last_rr_hot[3]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_88_out,
I1 => p_5_in6_in,
I2 => p_6_in,
O => \last_rr_hot[3]_i_3__0_n_0\
);
\last_rr_hot[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(3),
I2 => next_rr_hot(2),
I3 => next_rr_hot(1),
I4 => next_rr_hot(0),
I5 => next_rr_hot(4),
O => last_rr_hot
);
\last_rr_hot[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_46_out,
I1 => m_valid_i_reg,
I2 => \last_rr_hot[4]_i_4__0_n_0\,
I3 => p_108_out,
I4 => \last_rr_hot[4]_i_5__0_n_0\,
I5 => p_5_in6_in,
O => next_rr_hot(4)
);
\last_rr_hot[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_128_out,
I1 => p_8_in,
I2 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[4]_i_4__0_n_0\
);
\last_rr_hot[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_68_out,
I1 => p_6_in,
I2 => p_7_in9_in,
O => \last_rr_hot[4]_i_5__0_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(0),
Q => \last_rr_hot_reg_n_0_[0]\,
R => \^sr\(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(1),
Q => p_5_in6_in,
R => \^sr\(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(2),
Q => p_6_in,
R => \^sr\(0)
);
\last_rr_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(3),
Q => p_7_in9_in,
R => \^sr\(0)
);
\last_rr_hot_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(4),
Q => p_8_in,
S => \^sr\(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \^resp_select\(0),
I1 => p_128_out,
I2 => \^s_ready_i_reg\(0),
I3 => p_108_out,
I4 => \^s_ready_i_reg\(1),
I5 => \resp_select__0\(1),
O => \^s_axi_bvalid[0]\
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_68_out,
I1 => \^s_ready_i_reg\(3),
I2 => p_88_out,
I3 => \^s_ready_i_reg\(2),
O => \resp_select__0\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8 is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
f_mux4_return : out STD_LOGIC_VECTOR ( 46 downto 0 );
\s_axi_rvalid[0]\ : out STD_LOGIC;
resp_select : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
match : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : in STD_LOGIC;
st_mr_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
st_mr_rmesg : in STD_LOGIC_VECTOR ( 135 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_62_out : in STD_LOGIC;
p_102_out : in STD_LOGIC;
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[34]_4\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_40_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8 : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8 is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\ : STD_LOGIC;
signal last_rr_hot : STD_LOGIC;
signal \last_rr_hot[0]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_4_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_5_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_in1_in : STD_LOGIC_VECTOR ( 3 downto 1 );
signal p_5_in6_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in9_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal \^resp_select\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \resp_select__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rvalid[0]\ : STD_LOGIC;
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[3]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_2\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \last_rr_hot[1]_i_2\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_3\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_2\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_3\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_4\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_5\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__3\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_1\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_3\ : label is "soft_lutpair123";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
m_valid_i <= \^m_valid_i\;
resp_select(0) <= \^resp_select\(0);
\s_axi_rvalid[0]\ <= \^s_axi_rvalid[0]\;
\chosen[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBB8"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rvalid[0]\,
I2 => p_40_out,
I3 => p_122_out,
I4 => p_102_out,
I5 => m_valid_i_reg,
O => need_arbitration
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(0),
Q => \^q\(0),
R => SR(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(1),
Q => \^q\(1),
R => SR(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(2),
Q => \^q\(2),
R => SR(0)
);
\chosen_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(3),
Q => \^q\(3),
R => SR(0)
);
\chosen_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(4),
Q => \^q\(4),
R => SR(0)
);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(36),
I1 => st_mr_rid(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(24),
I5 => st_mr_rid(12),
O => f_mux4_return(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(46),
I1 => st_mr_rid(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(34),
I5 => st_mr_rid(22),
O => f_mux4_return(10)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(4),
I1 => p_40_out,
O => \^resp_select\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(47),
I1 => st_mr_rid(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(35),
I5 => st_mr_rid(23),
O => f_mux4_return(11)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_62_out,
I1 => \^q\(3),
I2 => p_102_out,
I3 => \^q\(1),
O => \resp_select__0\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_62_out,
I1 => \^q\(3),
I2 => p_82_out,
I3 => \^q\(2),
O => \resp_select__0\(1)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(102),
I1 => st_mr_rmesg(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(68),
I5 => st_mr_rmesg(34),
O => f_mux4_return(12)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(103),
I1 => st_mr_rmesg(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(69),
I5 => st_mr_rmesg(35),
O => f_mux4_return(13)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(104),
I1 => st_mr_rmesg(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(70),
I5 => st_mr_rmesg(36),
O => f_mux4_return(14)
);
\gen_fpga.gen_mux_5_8[16].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(105),
I1 => st_mr_rmesg(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(71),
I5 => st_mr_rmesg(37),
O => f_mux4_return(15)
);
\gen_fpga.gen_mux_5_8[17].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(106),
I1 => st_mr_rmesg(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(72),
I5 => st_mr_rmesg(38),
O => f_mux4_return(16)
);
\gen_fpga.gen_mux_5_8[18].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(107),
I1 => st_mr_rmesg(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(73),
I5 => st_mr_rmesg(39),
O => f_mux4_return(17)
);
\gen_fpga.gen_mux_5_8[19].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(108),
I1 => st_mr_rmesg(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(74),
I5 => st_mr_rmesg(40),
O => f_mux4_return(18)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(37),
I1 => st_mr_rid(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(25),
I5 => st_mr_rid(13),
O => f_mux4_return(1)
);
\gen_fpga.gen_mux_5_8[20].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(109),
I1 => st_mr_rmesg(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(75),
I5 => st_mr_rmesg(41),
O => f_mux4_return(19)
);
\gen_fpga.gen_mux_5_8[21].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(110),
I1 => st_mr_rmesg(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(76),
I5 => st_mr_rmesg(42),
O => f_mux4_return(20)
);
\gen_fpga.gen_mux_5_8[22].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(111),
I1 => st_mr_rmesg(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(77),
I5 => st_mr_rmesg(43),
O => f_mux4_return(21)
);
\gen_fpga.gen_mux_5_8[23].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(112),
I1 => st_mr_rmesg(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(78),
I5 => st_mr_rmesg(44),
O => f_mux4_return(22)
);
\gen_fpga.gen_mux_5_8[24].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(113),
I1 => st_mr_rmesg(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(79),
I5 => st_mr_rmesg(45),
O => f_mux4_return(23)
);
\gen_fpga.gen_mux_5_8[25].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(114),
I1 => st_mr_rmesg(12),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(80),
I5 => st_mr_rmesg(46),
O => f_mux4_return(24)
);
\gen_fpga.gen_mux_5_8[26].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(115),
I1 => st_mr_rmesg(13),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(81),
I5 => st_mr_rmesg(47),
O => f_mux4_return(25)
);
\gen_fpga.gen_mux_5_8[27].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(116),
I1 => st_mr_rmesg(14),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(82),
I5 => st_mr_rmesg(48),
O => f_mux4_return(26)
);
\gen_fpga.gen_mux_5_8[28].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(117),
I1 => st_mr_rmesg(15),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(83),
I5 => st_mr_rmesg(49),
O => f_mux4_return(27)
);
\gen_fpga.gen_mux_5_8[29].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(118),
I1 => st_mr_rmesg(16),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(84),
I5 => st_mr_rmesg(50),
O => f_mux4_return(28)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(38),
I1 => st_mr_rid(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(26),
I5 => st_mr_rid(14),
O => f_mux4_return(2)
);
\gen_fpga.gen_mux_5_8[30].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(119),
I1 => st_mr_rmesg(17),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(85),
I5 => st_mr_rmesg(51),
O => f_mux4_return(29)
);
\gen_fpga.gen_mux_5_8[31].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(120),
I1 => st_mr_rmesg(18),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(86),
I5 => st_mr_rmesg(52),
O => f_mux4_return(30)
);
\gen_fpga.gen_mux_5_8[32].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(121),
I1 => st_mr_rmesg(19),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(87),
I5 => st_mr_rmesg(53),
O => f_mux4_return(31)
);
\gen_fpga.gen_mux_5_8[33].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(122),
I1 => st_mr_rmesg(20),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(88),
I5 => st_mr_rmesg(54),
O => f_mux4_return(32)
);
\gen_fpga.gen_mux_5_8[34].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(123),
I1 => st_mr_rmesg(21),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(89),
I5 => st_mr_rmesg(55),
O => f_mux4_return(33)
);
\gen_fpga.gen_mux_5_8[35].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(124),
I1 => st_mr_rmesg(22),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(90),
I5 => st_mr_rmesg(56),
O => f_mux4_return(34)
);
\gen_fpga.gen_mux_5_8[36].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(125),
I1 => st_mr_rmesg(23),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(91),
I5 => st_mr_rmesg(57),
O => f_mux4_return(35)
);
\gen_fpga.gen_mux_5_8[37].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(126),
I1 => st_mr_rmesg(24),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(92),
I5 => st_mr_rmesg(58),
O => f_mux4_return(36)
);
\gen_fpga.gen_mux_5_8[38].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(127),
I1 => st_mr_rmesg(25),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(93),
I5 => st_mr_rmesg(59),
O => f_mux4_return(37)
);
\gen_fpga.gen_mux_5_8[39].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(128),
I1 => st_mr_rmesg(26),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(94),
I5 => st_mr_rmesg(60),
O => f_mux4_return(38)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(39),
I1 => st_mr_rid(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(27),
I5 => st_mr_rid(15),
O => f_mux4_return(3)
);
\gen_fpga.gen_mux_5_8[40].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(129),
I1 => st_mr_rmesg(27),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(95),
I5 => st_mr_rmesg(61),
O => f_mux4_return(39)
);
\gen_fpga.gen_mux_5_8[41].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(130),
I1 => st_mr_rmesg(28),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(96),
I5 => st_mr_rmesg(62),
O => f_mux4_return(40)
);
\gen_fpga.gen_mux_5_8[42].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(131),
I1 => st_mr_rmesg(29),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(97),
I5 => st_mr_rmesg(63),
O => f_mux4_return(41)
);
\gen_fpga.gen_mux_5_8[43].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(132),
I1 => st_mr_rmesg(30),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(98),
I5 => st_mr_rmesg(64),
O => f_mux4_return(42)
);
\gen_fpga.gen_mux_5_8[44].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(133),
I1 => st_mr_rmesg(31),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(99),
I5 => st_mr_rmesg(65),
O => f_mux4_return(43)
);
\gen_fpga.gen_mux_5_8[45].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(134),
I1 => st_mr_rmesg(32),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(100),
I5 => st_mr_rmesg(66),
O => f_mux4_return(44)
);
\gen_fpga.gen_mux_5_8[46].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(135),
I1 => st_mr_rmesg(33),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(101),
I5 => st_mr_rmesg(67),
O => f_mux4_return(45)
);
\gen_fpga.gen_mux_5_8[47].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => \m_payload_i_reg[34]_0\(0),
I1 => \m_payload_i_reg[34]_1\(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => \m_payload_i_reg[34]_2\(0),
I5 => \m_payload_i_reg[34]_3\(0),
O => f_mux4_return(46)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(40),
I1 => st_mr_rid(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(28),
I5 => st_mr_rid(16),
O => f_mux4_return(4)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(41),
I1 => st_mr_rid(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(29),
I5 => st_mr_rid(17),
O => f_mux4_return(5)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(42),
I1 => st_mr_rid(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(30),
I5 => st_mr_rid(18),
O => f_mux4_return(6)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(43),
I1 => st_mr_rid(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(31),
I5 => st_mr_rid(19),
O => f_mux4_return(7)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(44),
I1 => st_mr_rid(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(32),
I5 => st_mr_rid(20),
O => f_mux4_return(8)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(45),
I1 => st_mr_rid(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(33),
I5 => st_mr_rid(21),
O => f_mux4_return(9)
);
\gen_no_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => E(0)
);
\gen_no_arbiter.s_ready_i[0]_i_24__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4440404044444444"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => s_axi_arvalid(0),
I2 => \gen_multi_thread.accept_cnt_reg[0]\,
I3 => \^s_axi_rvalid[0]\,
I4 => \m_payload_i_reg[34]_4\,
I5 => \gen_multi_thread.accept_cnt_reg[3]\(0),
O => \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\,
I5 => aa_mi_arvalid,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8AAAA"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\,
I1 => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
I2 => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
I3 => \r_cmd_pop_4__1\,
I4 => match,
I5 => r_issuing_cnt(0),
O => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\
);
\last_rr_hot[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_122_out,
I1 => p_62_out,
I2 => p_40_out,
I3 => \last_rr_hot[0]_i_2_n_0\,
I4 => \last_rr_hot[0]_i_3_n_0\,
I5 => p_6_in,
O => next_rr_hot(0)
);
\last_rr_hot[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_5_in6_in,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_102_out,
I3 => p_82_out,
O => \last_rr_hot[0]_i_2_n_0\
);
\last_rr_hot[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_40_out,
I1 => p_7_in9_in,
I2 => p_8_in,
O => \last_rr_hot[0]_i_3_n_0\
);
\last_rr_hot[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_102_out,
I1 => p_40_out,
I2 => p_122_out,
I3 => \last_rr_hot[1]_i_2_n_0\,
I4 => \last_rr_hot[4]_i_4_n_0\,
I5 => p_7_in9_in,
O => next_rr_hot(1)
);
\last_rr_hot[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_6_in,
I1 => p_5_in6_in,
I2 => p_82_out,
I3 => p_62_out,
O => \last_rr_hot[1]_i_2_n_0\
);
\last_rr_hot[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_82_out,
I1 => m_valid_i_reg_0,
I2 => \last_rr_hot[4]_i_5_n_0\,
I3 => p_40_out,
I4 => \last_rr_hot[2]_i_3_n_0\,
I5 => p_8_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_102_out,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_5_in6_in,
O => \last_rr_hot[2]_i_3_n_0\
);
\last_rr_hot[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_62_out,
I1 => p_102_out,
I2 => p_82_out,
I3 => \last_rr_hot[3]_i_2_n_0\,
I4 => \last_rr_hot[3]_i_3_n_0\,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(3)
);
\last_rr_hot[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_8_in,
I1 => p_7_in9_in,
I2 => p_40_out,
I3 => p_122_out,
O => \last_rr_hot[3]_i_2_n_0\
);
\last_rr_hot[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_82_out,
I1 => p_5_in6_in,
I2 => p_6_in,
O => \last_rr_hot[3]_i_3_n_0\
);
\last_rr_hot[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(3),
I2 => next_rr_hot(2),
I3 => next_rr_hot(1),
I4 => next_rr_hot(0),
I5 => next_rr_hot(4),
O => last_rr_hot
);
\last_rr_hot[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_40_out,
I1 => m_valid_i_reg,
I2 => \last_rr_hot[4]_i_4_n_0\,
I3 => p_102_out,
I4 => \last_rr_hot[4]_i_5_n_0\,
I5 => p_5_in6_in,
O => next_rr_hot(4)
);
\last_rr_hot[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_122_out,
I1 => p_8_in,
I2 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[4]_i_4_n_0\
);
\last_rr_hot[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_62_out,
I1 => p_6_in,
I2 => p_7_in9_in,
O => \last_rr_hot[4]_i_5_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(0),
Q => \last_rr_hot_reg_n_0_[0]\,
R => SR(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(1),
Q => p_5_in6_in,
R => SR(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(2),
Q => p_6_in,
R => SR(0)
);
\last_rr_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(3),
Q => p_7_in9_in,
R => SR(0)
);
\last_rr_hot_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(4),
Q => p_8_in,
S => SR(0)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(0),
I1 => s_axi_rready(0),
I2 => p_122_out,
O => \m_payload_i_reg[0]\(0)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(1),
I1 => s_axi_rready(0),
I2 => p_102_out,
O => \m_payload_i_reg[0]_0\(0)
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(4),
I1 => s_axi_rready(0),
I2 => p_40_out,
O => \m_payload_i_reg[34]\(0)
);
\m_payload_i[46]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(3),
I1 => s_axi_rready(0),
I2 => p_62_out,
O => \m_payload_i_reg[0]_1\(0)
);
\m_payload_i[46]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(2),
I1 => s_axi_rready(0),
I2 => p_82_out,
O => \m_payload_i_reg[0]_2\(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF8"
)
port map (
I0 => \^q\(0),
I1 => p_122_out,
I2 => p_0_in1_in(2),
I3 => p_0_in1_in(1),
I4 => p_0_in1_in(3),
I5 => \^resp_select\(0),
O => \^s_axi_rvalid[0]\
);
\s_axi_rvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(2),
I1 => p_82_out,
O => p_0_in1_in(2)
);
\s_axi_rvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(1),
I1 => p_102_out,
O => p_0_in1_in(1)
);
\s_axi_rvalid[0]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(3),
I1 => p_62_out,
O => p_0_in1_in(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_awready_4 : out STD_LOGIC;
p_22_in : out STD_LOGIC;
p_29_in : out STD_LOGIC;
p_23_in : out STD_LOGIC;
p_25_in : out STD_LOGIC;
\read_cs__0\ : out STD_LOGIC;
mi_arready_4 : out STD_LOGIC;
\m_payload_i_reg[13]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_rready_4 : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
mi_bready_4 : in STD_LOGIC;
\write_cs0__0\ : in STD_LOGIC;
write_cs01_out : in STD_LOGIC;
s_axi_rlast_i0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aresetn_d : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bid_i[11]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^mi_arready_4\ : STD_LOGIC;
signal \^mi_awready_4\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_22_in\ : STD_LOGIC;
signal \^p_23_in\ : STD_LOGIC;
signal \^p_25_in\ : STD_LOGIC;
signal \^p_29_in\ : STD_LOGIC;
signal \^read_cs__0\ : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[2]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_2\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_3\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair16";
begin
mi_arready_4 <= \^mi_arready_4\;
mi_awready_4 <= \^mi_awready_4\;
p_22_in <= \^p_22_in\;
p_23_in <= \^p_23_in\;
p_25_in <= \^p_25_in\;
p_29_in <= \^p_29_in\;
\read_cs__0\ <= \^read_cs__0\;
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(0),
I1 => \^p_23_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(12),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E22E"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(13),
I1 => \^p_23_in\,
I2 => \gen_axi.read_cnt_reg__0\(0),
I3 => \gen_axi.read_cnt_reg\(1),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(14),
I1 => \gen_axi.read_cnt_reg\(1),
I2 => \gen_axi.read_cnt_reg__0\(0),
I3 => \^p_23_in\,
I4 => \gen_axi.read_cnt_reg\(2),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCAAAA0003AAAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(15),
I1 => \gen_axi.read_cnt_reg__0\(0),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg\(2),
I4 => \^p_23_in\,
I5 => \gen_axi.read_cnt_reg\(3),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCAAAA0003AAAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(16),
I1 => \gen_axi.read_cnt_reg\(2),
I2 => \gen_axi.read_cnt[4]_i_2_n_0\,
I3 => \gen_axi.read_cnt_reg\(3),
I4 => \^p_23_in\,
I5 => \gen_axi.read_cnt_reg\(4),
O => p_0_in(4)
);
\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \gen_axi.read_cnt_reg\(1),
I1 => \gen_axi.read_cnt_reg__0\(0),
O => \gen_axi.read_cnt[4]_i_2_n_0\
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CA3A"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(17),
I1 => \gen_axi.read_cnt[5]_i_2_n_0\,
I2 => \^p_23_in\,
I3 => \gen_axi.read_cnt_reg\(5),
O => p_0_in(5)
);
\gen_axi.read_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg\(3),
I1 => \gen_axi.read_cnt_reg__0\(0),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg\(2),
I4 => \gen_axi.read_cnt_reg\(4),
O => \gen_axi.read_cnt[5]_i_2_n_0\
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CA3A"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(18),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \^p_23_in\,
I3 => \gen_axi.read_cnt_reg\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F40404040404040"
)
port map (
I0 => \^read_cs__0\,
I1 => mi_rready_4,
I2 => \^p_23_in\,
I3 => \^mi_arready_4\,
I4 => aa_mi_arvalid,
I5 => \gen_no_arbiter.m_target_hot_i_reg[4]\(0),
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(19),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg\(6),
I3 => \^p_23_in\,
I4 => \gen_axi.read_cnt_reg\(7),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(2),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg__0\(0),
I4 => \gen_axi.read_cnt_reg\(3),
I5 => \gen_axi.read_cnt_reg\(5),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg__0\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F70707070707070"
)
port map (
I0 => \^read_cs__0\,
I1 => mi_rready_4,
I2 => \^p_23_in\,
I3 => \^mi_arready_4\,
I4 => aa_mi_arvalid,
I5 => \gen_no_arbiter.m_target_hot_i_reg[4]\(0),
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^p_23_in\,
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FBBB0000"
)
port map (
I0 => \^mi_arready_4\,
I1 => \^p_23_in\,
I2 => \^read_cs__0\,
I3 => mi_rready_4,
I4 => aresetn_d,
I5 => E(0),
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_axi.read_cnt[4]_i_2_n_0\,
I1 => \gen_axi.read_cnt_reg\(6),
I2 => \gen_axi.read_cnt_reg\(7),
I3 => \gen_axi.s_axi_arready_i_i_3_n_0\,
I4 => \gen_axi.read_cnt_reg\(2),
I5 => \gen_axi.read_cnt_reg\(3),
O => \^read_cs__0\
);
\gen_axi.s_axi_arready_i_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(5),
O => \gen_axi.s_axi_arready_i_i_3_n_0\
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready_4\,
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFBB0000F0FF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => Q(0),
I2 => mi_bready_4,
I3 => write_cs(1),
I4 => write_cs(0),
I5 => \^mi_awready_4\,
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready_4\,
R => SR(0)
);
\gen_axi.s_axi_bid_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => write_cs(1),
I1 => write_cs(0),
I2 => m_ready_d(0),
I3 => aa_sa_awvalid,
I4 => Q(0),
I5 => \^mi_awready_4\,
O => \gen_axi.s_axi_bid_i[11]_i_1_n_0\
);
\gen_axi.s_axi_bid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(0),
Q => \m_payload_i_reg[13]\(0),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(10),
Q => \m_payload_i_reg[13]\(10),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(11),
Q => \m_payload_i_reg[13]\(11),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(1),
Q => \m_payload_i_reg[13]\(1),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(2),
Q => \m_payload_i_reg[13]\(2),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(3),
Q => \m_payload_i_reg[13]\(3),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(4),
Q => \m_payload_i_reg[13]\(4),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(5),
Q => \m_payload_i_reg[13]\(5),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(6),
Q => \m_payload_i_reg[13]\(6),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(7),
Q => \m_payload_i_reg[13]\(7),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(8),
Q => \m_payload_i_reg[13]\(8),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(9),
Q => \m_payload_i_reg[13]\(9),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFF00C0"
)
port map (
I0 => mi_bready_4,
I1 => write_cs(0),
I2 => \write_cs0__0\,
I3 => write_cs(1),
I4 => \^p_29_in\,
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => \^p_29_in\,
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(0),
Q => \skid_buffer_reg[46]\(0),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(10),
Q => \skid_buffer_reg[46]\(10),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(11),
Q => \skid_buffer_reg[46]\(11),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(1),
Q => \skid_buffer_reg[46]\(1),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(2),
Q => \skid_buffer_reg[46]\(2),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(3),
Q => \skid_buffer_reg[46]\(3),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(4),
Q => \skid_buffer_reg[46]\(4),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(5),
Q => \skid_buffer_reg[46]\(5),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(6),
Q => \skid_buffer_reg[46]\(6),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(7),
Q => \skid_buffer_reg[46]\(7),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(8),
Q => \skid_buffer_reg[46]\(8),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(9),
Q => \skid_buffer_reg[46]\(9),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFBFFAAAA0800"
)
port map (
I0 => s_axi_rlast_i0,
I1 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I4 => E(0),
I5 => \^p_25_in\,
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_axi.read_cnt_reg\(2),
I1 => \gen_axi.read_cnt_reg\(3),
O => \gen_axi.s_axi_rlast_i_i_3_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(5),
I2 => \gen_axi.read_cnt_reg\(6),
I3 => \gen_axi.read_cnt_reg\(7),
I4 => mi_rready_4,
I5 => \^p_23_in\,
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => \^p_25_in\,
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF5F000C"
)
port map (
I0 => \write_cs0__0\,
I1 => write_cs01_out,
I2 => write_cs(0),
I3 => write_cs(1),
I4 => \^p_22_in\,
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => \^p_22_in\,
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4522"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => write_cs(1),
I2 => \write_cs0__0\,
I3 => write_cs(0),
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE00FE44"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => write_cs(1),
I2 => \write_cs0__0\,
I3 => write_cs(0),
I4 => mi_bready_4,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => write_cs(1),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter is
port (
\s_axi_awready[0]\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
ss_wr_awvalid : out STD_LOGIC;
ss_wr_awready : in STD_LOGIC;
ss_aa_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_valid_i_i_2__0\ : label is "soft_lutpair190";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair190";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready,
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000C8C0"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready,
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_valid_i_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
O => ss_wr_awvalid
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => \^m_ready_d\(1),
I1 => ss_wr_awready,
I2 => \^m_ready_d\(0),
I3 => ss_aa_awready,
O => \s_axi_awready[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5 is
port (
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_axi.s_axi_awready_i_reg\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[19]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[3].w_issuing_cnt_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 15 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_108_out : in STD_LOGIC;
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_88_out : in STD_LOGIC;
p_68_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\mi_awready_mux__3\ : in STD_LOGIC;
\s_ready_i0__1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\sa_wm_awready_mux__3\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5 : entity is "axi_crossbar_v2_1_14_splitter";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5 is
signal \^gen_axi.s_axi_awready_i_reg\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\ : STD_LOGIC;
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_awready_i_i_2\ : label is "soft_lutpair194";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair197";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[10]_i_1\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_2\ : label is "soft_lutpair193";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[18]_i_1\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_2\ : label is "soft_lutpair195";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[26]_i_1\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_2\ : label is "soft_lutpair196";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_1\ : label is "soft_lutpair194";
begin
\gen_axi.s_axi_awready_i_reg\ <= \^gen_axi.s_axi_awready_i_reg\;
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\gen_axi.s_axi_awready_i_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_ready_d\(1),
I1 => aa_sa_awvalid,
O => \^gen_axi.s_axi_awready_i_reg\
);
\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(1),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(1),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(3),
I4 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(0),
I2 => m_axi_awready(0),
I3 => s_axi_bready(0),
I4 => p_128_out,
I5 => \chosen_reg[3]\(0),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I1 => w_issuing_cnt(4),
I2 => w_issuing_cnt(5),
I3 => w_issuing_cnt(6),
O => D(1)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(5),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(7),
I4 => w_issuing_cnt(6),
O => D(2)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(1),
I2 => m_axi_awready(1),
I3 => s_axi_bready(0),
I4 => p_108_out,
I5 => \chosen_reg[3]\(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(5),
O => D(0)
);
\gen_master_slots[2].w_issuing_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(8),
I1 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I2 => w_issuing_cnt(9),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(0)
);
\gen_master_slots[2].w_issuing_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I1 => w_issuing_cnt(8),
I2 => w_issuing_cnt(9),
I3 => w_issuing_cnt(10),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(1)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(9),
I1 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I2 => w_issuing_cnt(8),
I3 => w_issuing_cnt(11),
I4 => w_issuing_cnt(10),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(2)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(2),
I2 => m_axi_awready(2),
I3 => s_axi_bready(0),
I4 => p_88_out,
I5 => \chosen_reg[3]\(2),
O => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\
);
\gen_master_slots[3].w_issuing_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(12),
I1 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I2 => w_issuing_cnt(13),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(0)
);
\gen_master_slots[3].w_issuing_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I1 => w_issuing_cnt(12),
I2 => w_issuing_cnt(13),
I3 => w_issuing_cnt(14),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(1)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(13),
I1 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I2 => w_issuing_cnt(12),
I3 => w_issuing_cnt(15),
I4 => w_issuing_cnt(14),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(2)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(3),
I2 => m_axi_awready(3),
I3 => s_axi_bready(0),
I4 => p_68_out,
I5 => \chosen_reg[3]\(3),
O => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => aa_sa_awvalid,
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => \mi_awready_mux__3\,
I4 => \^m_ready_d\(0),
I5 => \sa_wm_awready_mux__3\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000C8C0"
)
port map (
I0 => aa_sa_awvalid,
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => \mi_awready_mux__3\,
I4 => \s_ready_i0__1\(0),
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
push : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
out0 : in STD_LOGIC_VECTOR ( 0 to 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
signal \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => D(0),
Q => \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0EEFFFFF0EE0000"
)
port map (
I0 => \s_axi_awaddr[30]\(1),
I1 => \s_axi_awaddr[30]\(0),
I2 => \gen_primitive_shifter.gen_srls[0].srl_inst_n_0\,
I3 => out0(0),
I4 => load_s1,
I5 => m_select_enc(0),
O => \storage_data1_reg[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ is
port (
\storage_data1_reg[1]\ : out STD_LOGIC;
push : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
out0 : in STD_LOGIC_VECTOR ( 0 to 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ is
signal p_2_out : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => D(0),
Q => p_2_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0EEFFFFF0EE0000"
)
port map (
I0 => \s_axi_awaddr[30]\(1),
I1 => \s_axi_awaddr[30]\(0),
I2 => p_2_out,
I3 => out0(0),
I4 => load_s1,
I5 => m_select_enc(0),
O => \storage_data1_reg[1]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ is
port (
push : out STD_LOGIC;
\storage_data1_reg[2]\ : out STD_LOGIC;
\m_aready__1\ : out STD_LOGIC;
\m_aready0__3\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
match : in STD_LOGIC;
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
ss_wr_awready : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ is
signal \^m_aready0__3\ : STD_LOGIC;
signal \^m_aready__1\ : STD_LOGIC;
signal p_3_out : STD_LOGIC;
signal \^push\ : STD_LOGIC;
signal \s_axi_wready[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\m_aready0__3\ <= \^m_aready0__3\;
\m_aready__1\ <= \^m_aready__1\;
push <= \^push\;
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => \^push\,
CLK => aclk,
D => D(0),
Q => p_3_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0088000000F80000"
)
port map (
I0 => ss_wr_awready,
I1 => out0(0),
I2 => out0(1),
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => \^m_aready__1\,
O => \^push\
);
\m_valid_i_i_1__8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => s_axi_wlast(0),
I1 => m_avalid,
I2 => s_axi_wvalid(0),
I3 => \^m_aready0__3\,
O => \^m_aready__1\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAFEAAAAAAAEA"
)
port map (
I0 => \s_axi_wready[0]_INST_0_i_2_n_0\,
I1 => m_axi_wready(1),
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
I5 => m_axi_wready(2),
O => \^m_aready0__3\
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0000CA000000CA"
)
port map (
I0 => m_axi_wready(0),
I1 => p_22_in,
I2 => m_select_enc(2),
I3 => m_select_enc(1),
I4 => m_select_enc(0),
I5 => m_axi_wready(3),
O => \s_axi_wready[0]_INST_0_i_2_n_0\
);
\storage_data1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"C5FFC500"
)
port map (
I0 => match,
I1 => p_3_out,
I2 => out0(0),
I3 => load_s1,
I4 => m_select_enc(2),
O => \storage_data1_reg[2]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
\m_payload_i_reg[2]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
mi_bready_4 : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_29_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^mi_bready_4\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
begin
\m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
mi_bready_4 <= \^mi_bready_4\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => '0'
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => p_29_in,
I1 => \^mi_bready_4\,
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[2]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__0_n_0\
);
\m_valid_i_i_1__9\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg_0\,
O => \^m_valid_i_reg_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^m_payload_i_reg[2]_0\,
R => \^m_valid_i_reg_0\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
I1 => p_29_in,
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^mi_bready_4\,
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
\m_axi_bid[35]\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal \s_ready_i_i_1__3_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => \m_axi_bid[35]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__3_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__3_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
\m_axi_bid[23]\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__1_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => \m_axi_bid[23]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__1_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__1_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
p_108_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__0_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\last_rr_hot[2]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_108_out,
O => \chosen_reg[2]\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_2_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__0_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__0_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
\chosen_reg[4]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
p_88_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^p_1_in\ : STD_LOGIC;
signal s_ready_i_i_2_n_0 : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
p_1_in <= \^p_1_in\;
\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(1),
I1 => aresetn,
O => \aresetn_d_reg[1]\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => p_0_in(1),
R => '0'
);
\last_rr_hot[4]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_88_out,
O => \chosen_reg[4]\
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]_0\
);
s_ready_i_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => \^p_1_in\
);
s_ready_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_1\,
O => s_ready_i_i_2_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i_i_2_n_0,
Q => \^m_axi_bready\(0),
R => \^p_1_in\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\skid_buffer_reg[34]_0\ : out STD_LOGIC;
\r_cmd_pop_4__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_23_in : in STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_25_in : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \s_ready_i_i_1__6_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 34 );
signal \^skid_buffer_reg[34]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__3\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__3\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__3\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__3\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__3\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__3\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__3\ : label is "soft_lutpair114";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0);
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\skid_buffer_reg[34]_0\ <= \^skid_buffer_reg[34]_0\;
\gen_master_slots[4].r_issuing_cnt[32]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I1 => \chosen_reg[4]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \r_cmd_pop_4__1\
);
\m_payload_i[34]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_25_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(0),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(1),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(2),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(3),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(4),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[40]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(5),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(6),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(7),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(8),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(9),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(10),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(11),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_valid_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^skid_buffer_reg[34]_0\,
I1 => p_23_in,
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[4]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[4]\(0),
I3 => \^skid_buffer_reg[34]_0\,
I4 => p_23_in,
O => \s_ready_i_i_1__6_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__6_n_0\,
Q => \^skid_buffer_reg[34]_0\,
R => p_1_in
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => p_25_in,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[3]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_3__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[4]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_39_in : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_3__1\ : STD_LOGIC;
signal \s_ready_i_i_1__7_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_3\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_3\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__7\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__2\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__2\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__2\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__2\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__2\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__2\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__2\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__2\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair110";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[3]\ <= \^m_axi_rready[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_3__1\ <= \^r_cmd_pop_3__1\;
\gen_master_slots[3].r_issuing_cnt[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1),
I1 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2),
I2 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0),
I3 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3),
I4 => \^r_cmd_pop_3__1\,
I5 => p_39_in,
O => E(0)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[3]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_3__1\
);
\gen_no_arbiter.s_ready_i[0]_i_38__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_3__1\,
I1 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0),
I2 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3),
I3 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1),
I4 => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\last_rr_hot[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => p_82_out,
O => \chosen_reg[4]\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[3]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[3]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[3]\(0),
I3 => \^m_axi_rready[3]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__7_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__7_n_0\,
Q => \^m_axi_rready[3]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_2__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_57_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[24]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\chosen_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\ : STD_LOGIC;
signal \^m_axi_rready[2]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_2__1\ : STD_LOGIC;
signal \s_ready_i_i_1__8_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__6\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair85";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[2]\ <= \^m_axi_rready[2]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_2__1\ <= \^r_cmd_pop_2__1\;
\gen_master_slots[2].r_issuing_cnt[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1),
I1 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2),
I2 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0),
I3 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3),
I4 => \^r_cmd_pop_2__1\,
I5 => p_57_in,
O => E(0)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[2]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_2__1\
);
\gen_no_arbiter.s_ready_i[0]_i_26__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ECA0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\,
I1 => \gen_master_slots[3].r_issuing_cnt_reg[24]\,
I2 => D(0),
I3 => D(1),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_37__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_2__1\,
I1 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0),
I2 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3),
I3 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1),
I4 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_37__0_n_0\
);
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[2]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[2]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__8\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[2]\(0),
I3 => \^m_axi_rready[2]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__8_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__8_n_0\,
Q => \^m_axi_rready[2]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_1__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_75_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\chosen_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\ : STD_LOGIC;
signal \^m_axi_rready[1]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_1__1\ : STD_LOGIC;
signal \s_ready_i_i_1__5_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__5\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__0\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__0\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair62";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[1]\ <= \^m_axi_rready[1]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_1__1\ <= \^r_cmd_pop_1__1\;
\gen_master_slots[1].r_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1),
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3),
I4 => \^r_cmd_pop_1__1\,
I5 => p_75_in,
O => E(0)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_1__1\
);
\gen_no_arbiter.s_ready_i[0]_i_25__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\,
I1 => D(0),
I2 => ADDRESS_HIT_0,
I3 => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_35__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_1__1\,
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1),
I4 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_35__0_n_0\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[1]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[1]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[1]\(0),
I3 => \^m_axi_rready[1]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__5_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__5_n_0\,
Q => \^m_axi_rready[1]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_0__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : in STD_LOGIC;
p_102_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[0]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_0__1\ : STD_LOGIC;
signal \s_ready_i_i_1__4_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_2\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__4\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair40";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[0]\ <= \^m_axi_rready[0]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_0__1\ <= \^r_cmd_pop_0__1\;
\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I4 => \^r_cmd_pop_0__1\,
I5 => p_93_in,
O => E(0)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[0]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_0__1\
);
\gen_no_arbiter.s_ready_i[0]_i_36__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_0__1\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I4 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\last_rr_hot[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => p_102_out,
O => \chosen_reg[2]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[0]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[0]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[0]\(0),
I3 => \^m_axi_rready[0]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__4_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__4_n_0\,
Q => \^m_axi_rready[0]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc is
port (
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
resp_select : in STD_LOGIC_VECTOR ( 0 to 0 );
f_mux4_return : in STD_LOGIC_VECTOR ( 46 downto 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_0 : in STD_LOGIC;
\thread_valid_0__2\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\thread_valid_3__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_4 : in STD_LOGIC;
\thread_valid_4__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_7 : in STD_LOGIC;
\thread_valid_7__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_6 : in STD_LOGIC;
\thread_valid_6__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_5 : in STD_LOGIC;
\thread_valid_5__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_2 : in STD_LOGIC;
\thread_valid_2__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_1 : in STD_LOGIC;
\thread_valid_1__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc is
signal \any_pop__1\ : STD_LOGIC;
signal \^s_axi_rid[0]\ : STD_LOGIC;
signal \^s_axi_rid[10]\ : STD_LOGIC;
signal \^s_axi_rid[11]\ : STD_LOGIC;
signal \^s_axi_rid[1]\ : STD_LOGIC;
signal \^s_axi_rid[2]\ : STD_LOGIC;
signal \^s_axi_rid[3]\ : STD_LOGIC;
signal \^s_axi_rid[4]\ : STD_LOGIC;
signal \^s_axi_rid[5]\ : STD_LOGIC;
signal \^s_axi_rid[6]\ : STD_LOGIC;
signal \^s_axi_rid[7]\ : STD_LOGIC;
signal \^s_axi_rid[8]\ : STD_LOGIC;
signal \^s_axi_rid[9]\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[0].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[10].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[11].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[12].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[13].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[15].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[16].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[17].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[18].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[19].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[1].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[20].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[21].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[22].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[23].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[24].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[25].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[26].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[27].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[28].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[29].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[2].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[30].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[31].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[32].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[33].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[34].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[35].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[36].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[37].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[38].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[39].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[3].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[40].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[41].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[42].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[43].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[44].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[45].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[46].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[47].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[4].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[5].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[6].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[7].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[8].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[9].mux_s2_inst\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1__0\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_34__0\ : label is "soft_lutpair128";
begin
\s_axi_rid[0]\ <= \^s_axi_rid[0]\;
\s_axi_rid[10]\ <= \^s_axi_rid[10]\;
\s_axi_rid[11]\ <= \^s_axi_rid[11]\;
\s_axi_rid[1]\ <= \^s_axi_rid[1]\;
\s_axi_rid[2]\ <= \^s_axi_rid[2]\;
\s_axi_rid[3]\ <= \^s_axi_rid[3]\;
\s_axi_rid[4]\ <= \^s_axi_rid[4]\;
\s_axi_rid[5]\ <= \^s_axi_rid[5]\;
\s_axi_rid[6]\ <= \^s_axi_rid[6]\;
\s_axi_rid[7]\ <= \^s_axi_rid[7]\;
\s_axi_rid[8]\ <= \^s_axi_rid[8]\;
\s_axi_rid[9]\ <= \^s_axi_rid[9]\;
s_axi_rlast(0) <= \^s_axi_rlast\(0);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(0),
I1 => st_mr_rid(0),
O => \^s_axi_rid[0]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(10),
I1 => st_mr_rid(10),
O => \^s_axi_rid[10]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(11),
I1 => st_mr_rid(11),
O => \^s_axi_rid[11]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(12),
I1 => '1',
O => s_axi_rresp(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(13),
I1 => '1',
O => s_axi_rresp(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(14),
I1 => '0',
O => s_axi_rdata(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[16].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(15),
I1 => '0',
O => s_axi_rdata(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[17].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(16),
I1 => '0',
O => s_axi_rdata(2),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[18].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(17),
I1 => '0',
O => s_axi_rdata(3),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[19].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(18),
I1 => '0',
O => s_axi_rdata(4),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(1),
I1 => st_mr_rid(1),
O => \^s_axi_rid[1]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[20].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(19),
I1 => '0',
O => s_axi_rdata(5),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[21].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(20),
I1 => '0',
O => s_axi_rdata(6),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[22].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(21),
I1 => '0',
O => s_axi_rdata(7),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[23].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(22),
I1 => '0',
O => s_axi_rdata(8),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[24].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(23),
I1 => '0',
O => s_axi_rdata(9),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[25].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(24),
I1 => '0',
O => s_axi_rdata(10),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[26].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(25),
I1 => '0',
O => s_axi_rdata(11),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[27].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(26),
I1 => '0',
O => s_axi_rdata(12),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[28].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(27),
I1 => '0',
O => s_axi_rdata(13),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[29].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(28),
I1 => '0',
O => s_axi_rdata(14),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(2),
I1 => st_mr_rid(2),
O => \^s_axi_rid[2]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[30].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(29),
I1 => '0',
O => s_axi_rdata(15),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[31].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(30),
I1 => '0',
O => s_axi_rdata(16),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[32].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(31),
I1 => '0',
O => s_axi_rdata(17),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[33].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(32),
I1 => '0',
O => s_axi_rdata(18),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[34].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(33),
I1 => '0',
O => s_axi_rdata(19),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[35].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(34),
I1 => '0',
O => s_axi_rdata(20),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[36].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(35),
I1 => '0',
O => s_axi_rdata(21),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[37].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(36),
I1 => '0',
O => s_axi_rdata(22),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[38].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(37),
I1 => '0',
O => s_axi_rdata(23),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[39].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(38),
I1 => '0',
O => s_axi_rdata(24),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(3),
I1 => st_mr_rid(3),
O => \^s_axi_rid[3]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[40].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(39),
I1 => '0',
O => s_axi_rdata(25),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[41].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(40),
I1 => '0',
O => s_axi_rdata(26),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[42].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(41),
I1 => '0',
O => s_axi_rdata(27),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[43].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(42),
I1 => '0',
O => s_axi_rdata(28),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[44].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(43),
I1 => '0',
O => s_axi_rdata(29),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[45].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(44),
I1 => '0',
O => s_axi_rdata(30),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[46].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(45),
I1 => '0',
O => s_axi_rdata(31),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[47].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(46),
I1 => \m_payload_i_reg[34]\(0),
O => \^s_axi_rlast\(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(4),
I1 => st_mr_rid(4),
O => \^s_axi_rid[4]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(5),
I1 => st_mr_rid(5),
O => \^s_axi_rid[5]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(6),
I1 => st_mr_rid(6),
O => \^s_axi_rid[6]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(7),
I1 => st_mr_rid(7),
O => \^s_axi_rid[7]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(8),
I1 => st_mr_rid(8),
O => \^s_axi_rid[8]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(9),
I1 => st_mr_rid(9),
O => \^s_axi_rid[9]\,
S => resp_select(0)
);
\gen_multi_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A65"
)
port map (
I0 => Q(0),
I1 => \any_pop__1\,
I2 => S_AXI_ARREADY(0),
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFF2200D"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => \any_pop__1\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => \any_pop__1\,
I5 => S_AXI_ARREADY(0),
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800FFAE0051"
)
port map (
I0 => Q(1),
I1 => S_AXI_ARREADY(0),
I2 => \any_pop__1\,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_0,
I1 => \any_pop__1\,
I2 => \thread_valid_0__2\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_1,
I1 => \any_pop__1\,
I2 => \thread_valid_1__2\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_2,
I1 => \any_pop__1\,
I2 => \thread_valid_2__2\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_3,
I1 => \any_pop__1\,
I2 => \thread_valid_3__2\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_4,
I1 => \any_pop__1\,
I2 => \thread_valid_4__2\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_5,
I1 => \any_pop__1\,
I2 => \thread_valid_5__2\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_6,
I1 => \any_pop__1\,
I2 => \thread_valid_6__2\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_7,
I1 => \any_pop__1\,
I2 => \thread_valid_7__2\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rlast\(0),
I2 => \chosen_reg[0]\,
O => \any_pop__1\
);
\gen_no_arbiter.s_ready_i[0]_i_34__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_axi_rlast\(0),
I1 => s_axi_rready(0),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\i__carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \^s_axi_rid[11]\,
O => S(3)
);
\i__carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \^s_axi_rid[8]\,
O => S(2)
);
\i__carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \^s_axi_rid[5]\,
O => S(1)
);
\i__carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \^s_axi_rid[2]\,
O => S(0)
);
p_10_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
p_10_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
p_10_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
p_10_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
p_12_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
p_12_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
p_12_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
p_12_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
p_14_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3)
);
p_14_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2)
);
p_14_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1)
);
p_14_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
p_2_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
p_2_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
p_2_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
p_2_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
p_4_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
p_4_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
p_4_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
p_4_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
p_6_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
p_6_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
p_6_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
p_6_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
p_8_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3)
);
p_8_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2)
);
p_8_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1)
);
p_8_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ is
port (
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
p_0_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
resp_select : in STD_LOGIC_VECTOR ( 0 to 0 );
f_mux4_return : in STD_LOGIC_VECTOR ( 13 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
cmd_push_0 : in STD_LOGIC;
\thread_valid_0__2\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\thread_valid_3__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_4 : in STD_LOGIC;
\thread_valid_4__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_7 : in STD_LOGIC;
\thread_valid_7__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_6 : in STD_LOGIC;
\thread_valid_6__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_5 : in STD_LOGIC;
\thread_valid_5__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_2 : in STD_LOGIC;
\thread_valid_2__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_1 : in STD_LOGIC;
\thread_valid_1__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ : entity is "generic_baseblocks_v2_1_0_mux_enc";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ is
signal \any_pop__1\ : STD_LOGIC;
signal \^p_0_out\ : STD_LOGIC;
signal \^s_axi_bid[0]\ : STD_LOGIC;
signal \^s_axi_bid[10]\ : STD_LOGIC;
signal \^s_axi_bid[11]\ : STD_LOGIC;
signal \^s_axi_bid[1]\ : STD_LOGIC;
signal \^s_axi_bid[2]\ : STD_LOGIC;
signal \^s_axi_bid[3]\ : STD_LOGIC;
signal \^s_axi_bid[4]\ : STD_LOGIC;
signal \^s_axi_bid[5]\ : STD_LOGIC;
signal \^s_axi_bid[6]\ : STD_LOGIC;
signal \^s_axi_bid[7]\ : STD_LOGIC;
signal \^s_axi_bid[8]\ : STD_LOGIC;
signal \^s_axi_bid[9]\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[0].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[10].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[11].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[12].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[13].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[15].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[1].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[2].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[3].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[4].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[5].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[6].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[7].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[8].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[9].mux_s2_inst\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1\ : label is "soft_lutpair162";
begin
p_0_out <= \^p_0_out\;
\s_axi_bid[0]\ <= \^s_axi_bid[0]\;
\s_axi_bid[10]\ <= \^s_axi_bid[10]\;
\s_axi_bid[11]\ <= \^s_axi_bid[11]\;
\s_axi_bid[1]\ <= \^s_axi_bid[1]\;
\s_axi_bid[2]\ <= \^s_axi_bid[2]\;
\s_axi_bid[3]\ <= \^s_axi_bid[3]\;
\s_axi_bid[4]\ <= \^s_axi_bid[4]\;
\s_axi_bid[5]\ <= \^s_axi_bid[5]\;
\s_axi_bid[6]\ <= \^s_axi_bid[6]\;
\s_axi_bid[7]\ <= \^s_axi_bid[7]\;
\s_axi_bid[8]\ <= \^s_axi_bid[8]\;
\s_axi_bid[9]\ <= \^s_axi_bid[9]\;
\gen_fpga.gen_mux_5_8[0].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(0),
I1 => st_mr_bid(0),
O => \^s_axi_bid[0]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(10),
I1 => st_mr_bid(10),
O => \^s_axi_bid[10]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(11),
I1 => st_mr_bid(11),
O => \^s_axi_bid[11]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(12),
I1 => '1',
O => s_axi_bresp(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(13),
I1 => '1',
O => s_axi_bresp(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => '1',
I1 => '1',
O => \^p_0_out\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(1),
I1 => st_mr_bid(1),
O => \^s_axi_bid[1]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(2),
I1 => st_mr_bid(2),
O => \^s_axi_bid[2]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(3),
I1 => st_mr_bid(3),
O => \^s_axi_bid[3]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(4),
I1 => st_mr_bid(4),
O => \^s_axi_bid[4]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(5),
I1 => st_mr_bid(5),
O => \^s_axi_bid[5]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(6),
I1 => st_mr_bid(6),
O => \^s_axi_bid[6]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(7),
I1 => st_mr_bid(7),
O => \^s_axi_bid[7]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(8),
I1 => st_mr_bid(8),
O => \^s_axi_bid[8]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(9),
I1 => st_mr_bid(9),
O => \^s_axi_bid[9]\,
S => resp_select(0)
);
\gen_multi_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A65"
)
port map (
I0 => Q(0),
I1 => \any_pop__1\,
I2 => \m_ready_d_reg[1]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFF2200D"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \any_pop__1\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => \any_pop__1\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800FFAE0051"
)
port map (
I0 => Q(1),
I1 => \m_ready_d_reg[1]\,
I2 => \any_pop__1\,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_0,
I1 => \any_pop__1\,
I2 => \thread_valid_0__2\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_1,
I1 => \any_pop__1\,
I2 => \thread_valid_1__2\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_2,
I1 => \any_pop__1\,
I2 => \thread_valid_2__2\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_3,
I1 => \any_pop__1\,
I2 => \thread_valid_3__2\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_4,
I1 => \any_pop__1\,
I2 => \thread_valid_4__2\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_5,
I1 => \any_pop__1\,
I2 => \thread_valid_5__2\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_6,
I1 => \any_pop__1\,
I2 => \thread_valid_6__2\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_7,
I1 => \any_pop__1\,
I2 => \thread_valid_7__2\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_bready(0),
I1 => \^p_0_out\,
I2 => m_valid_i_reg,
O => \any_pop__1\
);
\i__carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \^s_axi_bid[11]\,
O => S(3)
);
\i__carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \^s_axi_bid[8]\,
O => S(2)
);
\i__carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \^s_axi_bid[5]\,
O => S(1)
);
\i__carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \^s_axi_bid[2]\,
O => S(0)
);
\p_10_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
\p_10_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
\p_10_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
\p_10_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
\p_12_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
\p_12_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
\p_12_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
\p_12_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
\p_14_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3)
);
\p_14_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2)
);
\p_14_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1)
);
\p_14_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\p_2_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
\p_2_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
\p_2_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
\p_2_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
\p_4_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
\p_4_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
\p_4_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
\p_4_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
\p_6_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
\p_6_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
\p_6_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
\p_6_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
\p_8_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3)
);
\p_8_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2)
);
\p_8_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1)
);
\p_8_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor is
port (
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
\s_axi_rvalid[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 59 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
match : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\s_axi_araddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : in STD_LOGIC;
st_mr_rmesg : in STD_LOGIC_VECTOR ( 135 downto 0 );
\m_payload_i_reg[34]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_62_out : in STD_LOGIC;
p_102_out : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
p_40_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_arid[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \accum_push_5__0\ : STD_LOGIC;
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 58 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal aid_match_00_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal \aid_match_0__0\ : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal aid_match_10_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal \aid_match_1__0\ : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal aid_match_20_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal \aid_match_2__0\ : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal aid_match_30_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal \aid_match_3__0\ : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal aid_match_40_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal \aid_match_4__0\ : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal aid_match_50_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal \aid_match_5__0\ : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal aid_match_60_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal \aid_match_6__0\ : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal aid_match_70_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal \aid_match_7__0\ : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal f_mux4_return : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \gen_multi_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_47\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_48\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_49\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_50\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_51\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_52\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_53\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_54\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_55\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_56\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_57\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_58\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_59\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_60\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_61\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_62\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_63\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_64\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_65\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_66\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_67\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_68\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_69\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_70\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_71\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_72\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_73\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_74\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_75\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_76\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_77\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_78\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_79\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_80\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_81\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_82\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_83\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_84\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_85\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_86\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_87\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_88\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_89\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_90\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_91\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_31_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal resp_select : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^s_axi_rvalid[0]\ : STD_LOGIC;
signal \thread_valid_0__2\ : STD_LOGIC;
signal \thread_valid_1__2\ : STD_LOGIC;
signal \thread_valid_2__2\ : STD_LOGIC;
signal \thread_valid_3__2\ : STD_LOGIC;
signal \thread_valid_4__2\ : STD_LOGIC;
signal \thread_valid_5__2\ : STD_LOGIC;
signal \thread_valid_6__2\ : STD_LOGIC;
signal \thread_valid_7__2\ : STD_LOGIC;
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_10__0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13__0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_16__0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_19__0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_20__0\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_27__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_29__0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_32__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_33__0\ : label is "soft_lutpair155";
begin
D(0) <= \^d\(0);
\s_axi_rvalid[0]\ <= \^s_axi_rvalid[0]\;
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_00_carry_i_1_n_0,
S(2) => aid_match_00_carry_i_2_n_0,
S(1) => aid_match_00_carry_i_3_n_0,
S(0) => aid_match_00_carry_i_4_n_0
);
aid_match_00_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
O => aid_match_00_carry_i_1_n_0
);
aid_match_00_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
O => aid_match_00_carry_i_2_n_0
);
aid_match_00_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
O => aid_match_00_carry_i_3_n_0
);
aid_match_00_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
O => aid_match_00_carry_i_4_n_0
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_10_carry_i_1_n_0,
S(2) => aid_match_10_carry_i_2_n_0,
S(1) => aid_match_10_carry_i_3_n_0,
S(0) => aid_match_10_carry_i_4_n_0
);
aid_match_10_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
I5 => \s_axi_arid[11]\(11),
O => aid_match_10_carry_i_1_n_0
);
aid_match_10_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
I5 => \s_axi_arid[11]\(8),
O => aid_match_10_carry_i_2_n_0
);
aid_match_10_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
I5 => \s_axi_arid[11]\(5),
O => aid_match_10_carry_i_3_n_0
);
aid_match_10_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
I5 => \s_axi_arid[11]\(2),
O => aid_match_10_carry_i_4_n_0
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_20_carry_i_1_n_0,
S(2) => aid_match_20_carry_i_2_n_0,
S(1) => aid_match_20_carry_i_3_n_0,
S(0) => aid_match_20_carry_i_4_n_0
);
aid_match_20_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
O => aid_match_20_carry_i_1_n_0
);
aid_match_20_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
O => aid_match_20_carry_i_2_n_0
);
aid_match_20_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
O => aid_match_20_carry_i_3_n_0
);
aid_match_20_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
O => aid_match_20_carry_i_4_n_0
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_30_carry_i_1_n_0,
S(2) => aid_match_30_carry_i_2_n_0,
S(1) => aid_match_30_carry_i_3_n_0,
S(0) => aid_match_30_carry_i_4_n_0
);
aid_match_30_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
O => aid_match_30_carry_i_1_n_0
);
aid_match_30_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
O => aid_match_30_carry_i_2_n_0
);
aid_match_30_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
O => aid_match_30_carry_i_3_n_0
);
aid_match_30_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
O => aid_match_30_carry_i_4_n_0
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_40_carry_i_1_n_0,
S(2) => aid_match_40_carry_i_2_n_0,
S(1) => aid_match_40_carry_i_3_n_0,
S(0) => aid_match_40_carry_i_4_n_0
);
aid_match_40_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
O => aid_match_40_carry_i_1_n_0
);
aid_match_40_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
O => aid_match_40_carry_i_2_n_0
);
aid_match_40_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
O => aid_match_40_carry_i_3_n_0
);
aid_match_40_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
O => aid_match_40_carry_i_4_n_0
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_50_carry_i_1_n_0,
S(2) => aid_match_50_carry_i_2_n_0,
S(1) => aid_match_50_carry_i_3_n_0,
S(0) => aid_match_50_carry_i_4_n_0
);
aid_match_50_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
O => aid_match_50_carry_i_1_n_0
);
aid_match_50_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
O => aid_match_50_carry_i_2_n_0
);
aid_match_50_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
O => aid_match_50_carry_i_3_n_0
);
aid_match_50_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
O => aid_match_50_carry_i_4_n_0
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_60_carry_i_1_n_0,
S(2) => aid_match_60_carry_i_2_n_0,
S(1) => aid_match_60_carry_i_3_n_0,
S(0) => aid_match_60_carry_i_4_n_0
);
aid_match_60_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
O => aid_match_60_carry_i_1_n_0
);
aid_match_60_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
O => aid_match_60_carry_i_2_n_0
);
aid_match_60_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
O => aid_match_60_carry_i_3_n_0
);
aid_match_60_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
O => aid_match_60_carry_i_4_n_0
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_70_carry_i_1_n_0,
S(2) => aid_match_70_carry_i_2_n_0,
S(1) => aid_match_70_carry_i_3_n_0,
S(0) => aid_match_70_carry_i_4_n_0
);
aid_match_70_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
O => aid_match_70_carry_i_1_n_0
);
aid_match_70_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
O => aid_match_70_carry_i_2_n_0
);
aid_match_70_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
O => aid_match_70_carry_i_3_n_0
);
aid_match_70_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
O => aid_match_70_carry_i_4_n_0
);
\gen_multi_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.accept_cnt[0]_i_1_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_58\,
Q => \gen_multi_thread.accept_cnt_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_57\,
Q => \gen_multi_thread.accept_cnt_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.mux_resp_multi_thread_n_56\,
Q => \gen_multi_thread.accept_cnt_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8
port map (
E(0) => E(0),
Q(4 downto 0) => Q(4 downto 0),
SR(0) => SR(0),
S_AXI_ARREADY(0) => S_AXI_ARREADY(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
f_mux4_return(46 downto 14) => f_mux4_return(47 downto 15),
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.accept_cnt_reg__0\(3),
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ => \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\,
\m_payload_i_reg[0]\(0) => \m_payload_i_reg[0]\(0),
\m_payload_i_reg[0]_0\(0) => \m_payload_i_reg[0]_0\(0),
\m_payload_i_reg[0]_1\(0) => \m_payload_i_reg[0]_1\(0),
\m_payload_i_reg[0]_2\(0) => \m_payload_i_reg[0]_2\(0),
\m_payload_i_reg[34]\(0) => \m_payload_i_reg[34]\(0),
\m_payload_i_reg[34]_0\(0) => \m_payload_i_reg[34]_1\(0),
\m_payload_i_reg[34]_1\(0) => \m_payload_i_reg[34]_2\(0),
\m_payload_i_reg[34]_2\(0) => \m_payload_i_reg[34]_3\(0),
\m_payload_i_reg[34]_3\(0) => \m_payload_i_reg[34]_4\(0),
\m_payload_i_reg[34]_4\ => \gen_multi_thread.mux_resp_multi_thread_n_59\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
match => match,
p_102_out => p_102_out,
p_122_out => p_122_out,
p_40_out => p_40_out,
p_62_out => p_62_out,
p_82_out => p_82_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(0) => r_issuing_cnt(0),
resp_select(0) => resp_select(2),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rready(0) => s_axi_rready(0),
\s_axi_rvalid[0]\ => \^s_axi_rvalid[0]\,
st_mr_rid(47 downto 0) => st_mr_rid(47 downto 0),
st_mr_rmesg(135 downto 0) => st_mr_rmesg(135 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(0),
I1 => cmd_push_0,
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(2),
I3 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(1),
I1 => cmd_push_0,
I2 => active_cnt(0),
I3 => active_cnt(3),
I4 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\,
Q => active_cnt(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\,
Q => active_cnt(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\,
Q => active_cnt(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_47\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\,
Q => active_cnt(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E222"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => aid_match_00,
I3 => S_AXI_ARREADY(0),
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_1,
I1 => active_cnt(8),
I2 => active_cnt(10),
I3 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(9),
I1 => cmd_push_1,
I2 => active_cnt(8),
I3 => active_cnt(11),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(8),
I1 => cmd_push_1,
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\,
Q => active_cnt(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\,
Q => active_cnt(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\,
Q => active_cnt(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\,
Q => active_cnt(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => aid_match_10,
I4 => S_AXI_ARREADY(0),
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(16),
I1 => cmd_push_2,
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_2,
I1 => active_cnt(16),
I2 => active_cnt(18),
I3 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(17),
I1 => cmd_push_2,
I2 => active_cnt(16),
I3 => active_cnt(19),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\,
Q => active_cnt(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\,
Q => active_cnt(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\,
Q => active_cnt(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\,
Q => active_cnt(19),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80008000800080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => \thread_valid_2__2\,
I4 => aid_match_20,
I5 => S_AXI_ARREADY(0),
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
O => \thread_valid_0__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
O => \thread_valid_1__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
O => \thread_valid_2__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(24),
I1 => cmd_push_3,
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(26),
I3 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(25),
I1 => cmd_push_3,
I2 => active_cnt(24),
I3 => active_cnt(27),
I4 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\,
Q => active_cnt(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\,
Q => active_cnt(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\,
Q => active_cnt(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_48\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\,
Q => active_cnt(27),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I2 => \thread_valid_3__2\,
I3 => aid_match_30,
I4 => S_AXI_ARREADY(0),
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(32),
I1 => cmd_push_4,
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_4,
I1 => active_cnt(32),
I2 => active_cnt(34),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(33),
I1 => cmd_push_4,
I2 => active_cnt(32),
I3 => active_cnt(35),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\,
Q => active_cnt(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\,
Q => active_cnt(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\,
Q => active_cnt(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\,
Q => active_cnt(35),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
I1 => \thread_valid_3__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \thread_valid_4__2\,
I4 => aid_match_40,
I5 => S_AXI_ARREADY(0),
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555557FFFFFFFF"
)
port map (
I0 => \thread_valid_0__2\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
I5 => \thread_valid_2__2\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
O => \thread_valid_3__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
O => \thread_valid_4__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(40),
I1 => cmd_push_5,
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_5,
I1 => active_cnt(40),
I2 => active_cnt(42),
I3 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(41),
I1 => cmd_push_5,
I2 => active_cnt(40),
I3 => active_cnt(43),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\,
Q => active_cnt(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\,
Q => active_cnt(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\,
Q => active_cnt(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\,
Q => active_cnt(43),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I2 => \thread_valid_5__2\,
I3 => aid_match_50,
I4 => S_AXI_ARREADY(0),
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(48),
I1 => cmd_push_6,
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_6,
I1 => active_cnt(48),
I2 => active_cnt(50),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(49),
I1 => cmd_push_6,
I2 => active_cnt(48),
I3 => active_cnt(51),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\,
Q => active_cnt(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\,
Q => active_cnt(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\,
Q => active_cnt(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\,
Q => active_cnt(51),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \thread_valid_5__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \thread_valid_6__2\,
I4 => aid_match_60,
I5 => S_AXI_ARREADY(0),
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
O => \thread_valid_5__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(51),
I2 => active_cnt(49),
I3 => active_cnt(48),
O => \thread_valid_6__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(56),
I1 => cmd_push_7,
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_7,
I1 => active_cnt(56),
I2 => active_cnt(58),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(57),
I1 => cmd_push_7,
I2 => active_cnt(56),
I3 => active_cnt(59),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
O => \thread_valid_7__2\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\,
Q => active_cnt(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\,
Q => active_cnt(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\,
Q => active_cnt(58),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\,
Q => active_cnt(59),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_araddr[30]\(2),
I1 => \s_axi_araddr[30]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_araddr[30]\(2),
I1 => \s_axi_araddr[30]\(1),
O => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \aid_match_7__0\,
I4 => S_AXI_ARREADY(0),
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55555557"
)
port map (
I0 => \thread_valid_3__2\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
O => \accum_push_5__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => \thread_valid_6__2\,
I5 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\,
I4 => \aid_match_6__0\,
I5 => \aid_match_7__0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
O => \aid_match_7__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_00,
I1 => \thread_valid_0__2\,
I2 => aid_match_10,
I3 => \thread_valid_1__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_20,
I1 => \thread_valid_2__2\,
I2 => aid_match_30,
I3 => \thread_valid_3__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_40,
I1 => \thread_valid_4__2\,
I2 => aid_match_50,
I3 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(48),
I1 => active_cnt(49),
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => aid_match_60,
O => \aid_match_6__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0_n_0\,
Q => active_target(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0_n_0\,
Q => active_target(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(58),
R => SR(0)
);
\gen_multi_thread.mux_resp_multi_thread\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc
port map (
CO(0) => p_14_out,
D(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
D(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
D(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\,
E(0) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg__0\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_60\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_61\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_62\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_63\,
S_AXI_ARREADY(0) => S_AXI_ARREADY(0),
\chosen_reg[0]\ => \^s_axi_rvalid[0]\,
cmd_push_0 => cmd_push_0,
cmd_push_1 => cmd_push_1,
cmd_push_2 => cmd_push_2,
cmd_push_3 => cmd_push_3,
cmd_push_4 => cmd_push_4,
cmd_push_5 => cmd_push_5,
cmd_push_6 => cmd_push_6,
cmd_push_7 => cmd_push_7,
f_mux4_return(46 downto 14) => f_mux4_return(47 downto 15),
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3) => \gen_multi_thread.mux_resp_multi_thread_n_88\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2) => \gen_multi_thread.mux_resp_multi_thread_n_89\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1) => \gen_multi_thread.mux_resp_multi_thread_n_90\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_91\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_84\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_85\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_86\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_87\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_80\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_81\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_82\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_83\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_76\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_77\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_78\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_79\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_72\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_73\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_74\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_75\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_68\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_69\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_70\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_71\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_64\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_65\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_66\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_67\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_multi_thread.mux_resp_multi_thread_n_59\,
\m_payload_i_reg[34]\(0) => \m_payload_i_reg[34]_0\(0),
resp_select(0) => resp_select(2),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => \s_axi_rid[0]\,
\s_axi_rid[10]\ => \s_axi_rid[10]\,
\s_axi_rid[11]\ => \s_axi_rid[11]\,
\s_axi_rid[1]\ => \s_axi_rid[1]\,
\s_axi_rid[2]\ => \s_axi_rid[2]\,
\s_axi_rid[3]\ => \s_axi_rid[3]\,
\s_axi_rid[4]\ => \s_axi_rid[4]\,
\s_axi_rid[5]\ => \s_axi_rid[5]\,
\s_axi_rid[6]\ => \s_axi_rid[6]\,
\s_axi_rid[7]\ => \s_axi_rid[7]\,
\s_axi_rid[8]\ => \s_axi_rid[8]\,
\s_axi_rid[9]\ => \s_axi_rid[9]\,
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
st_mr_rid(11 downto 0) => st_mr_rid(59 downto 48),
\thread_valid_0__2\ => \thread_valid_0__2\,
\thread_valid_1__2\ => \thread_valid_1__2\,
\thread_valid_2__2\ => \thread_valid_2__2\,
\thread_valid_3__2\ => \thread_valid_3__2\,
\thread_valid_4__2\ => \thread_valid_4__2\,
\thread_valid_5__2\ => \thread_valid_5__2\,
\thread_valid_6__2\ => \thread_valid_6__2\,
\thread_valid_7__2\ => \thread_valid_7__2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => match,
O => \^d\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
I4 => aid_match_30,
O => \aid_match_3__0\
);
\gen_no_arbiter.s_ready_i[0]_i_11__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(17),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(18),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
I4 => aid_match_20,
O => \aid_match_2__0\
);
\gen_no_arbiter.s_ready_i[0]_i_14__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(9),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(10),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
I4 => aid_match_10,
O => \aid_match_1__0\
);
\gen_no_arbiter.s_ready_i[0]_i_17__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(1),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(2),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
I4 => aid_match_00,
O => \aid_match_0__0\
);
\gen_no_arbiter.s_ready_i[0]_i_20__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(49),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(50),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(57),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(58),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_27__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(41),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(42),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_29__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
I4 => aid_match_50,
O => \aid_match_5__0\
);
\gen_no_arbiter.s_ready_i[0]_i_30__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(33),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_31\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(34),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_31_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_32__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
O => \aid_match_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_33__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
I1 => \gen_multi_thread.accept_cnt_reg__0\(2),
I2 => \gen_multi_thread.accept_cnt_reg__0\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_33__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\,
I2 => \aid_match_3__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\,
I5 => \aid_match_2__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0\,
I2 => \aid_match_1__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\,
I5 => \aid_match_0__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0\,
I2 => \aid_match_6__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_23__0_n_0\,
I5 => \aid_match_7__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_27__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_28_n_0\,
I2 => \aid_match_5__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_30__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_31_n_0\,
I5 => \aid_match_4__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(25),
I1 => \s_axi_araddr[30]\(2),
I2 => \s_axi_araddr[30]\(1),
I3 => \s_axi_araddr[30]\(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(26),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_araddr[30]\(0),
I3 => \s_axi_araddr[30]\(2),
I4 => \s_axi_araddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_60\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_61\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_62\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_63\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_80\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_81\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_82\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_83\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_84\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_85\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_86\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_87\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_88\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_89\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_90\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_91\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_64\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_65\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_66\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_67\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_68\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_69\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_70\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_71\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_72\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_73\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_74\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_75\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_76\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_77\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_78\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_79\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
port (
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].w_issuing_cnt_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\s_axi_bvalid[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 59 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
p_84_in : in STD_LOGIC;
p_66_in : in STD_LOGIC;
p_48_in : in STD_LOGIC;
p_101_in : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
match : in STD_LOGIC;
ADDRESS_HIT_0 : in STD_LOGIC;
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
st_mr_bmesg : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_68_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_awid[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_14_si_transactor";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
signal \^d\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \accum_push_5__0\ : STD_LOGIC;
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 58 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal \aid_match_00_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal \aid_match_0__0\ : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal \aid_match_10_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal \aid_match_1__0\ : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal \aid_match_20_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal \aid_match_2__0\ : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal \aid_match_30_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal \aid_match_3__0\ : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal \aid_match_40_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal \aid_match_4__0\ : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal \aid_match_50_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal \aid_match_5__0\ : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal \aid_match_60_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal \aid_match_6__0\ : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal \aid_match_70_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal \aid_match_7__0\ : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal f_mux4_return : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_15\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_16\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_17\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_18\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_19\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_20\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_21\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_22\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_23\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_24\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_25\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_26\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_27\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_28\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_29\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_30\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_31\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_32\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_33\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_34\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_35\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_36\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_37\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_38\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_39\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_40\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_41\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_42\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_43\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_44\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_45\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_46\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_47\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_48\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_49\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_50\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_51\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_52\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_53\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_54\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_55\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_56\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_57\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_58\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_15_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_21_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_23_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_29_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_32_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_35_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal p_0_out_0 : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal resp_select : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^s_axi_bvalid[0]\ : STD_LOGIC;
signal \thread_valid_0__2\ : STD_LOGIC;
signal \thread_valid_1__2\ : STD_LOGIC;
signal \thread_valid_2__2\ : STD_LOGIC;
signal \thread_valid_3__2\ : STD_LOGIC;
signal \thread_valid_4__2\ : STD_LOGIC;
signal \thread_valid_5__2\ : STD_LOGIC;
signal \thread_valid_6__2\ : STD_LOGIC;
signal \thread_valid_7__2\ : STD_LOGIC;
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair189";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\ : label is "soft_lutpair188";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\ : label is "soft_lutpair187";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\ : label is "soft_lutpair186";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_10\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_13\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_16\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_19\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_20\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_28__0\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_30\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_33\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_35\ : label is "soft_lutpair189";
begin
D(2 downto 0) <= \^d\(2 downto 0);
SR(0) <= \^sr\(0);
\s_axi_bvalid[0]\ <= \^s_axi_bvalid[0]\;
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_00_carry_i_1__0_n_0\,
S(2) => \aid_match_00_carry_i_2__0_n_0\,
S(1) => \aid_match_00_carry_i_3__0_n_0\,
S(0) => \aid_match_00_carry_i_4__0_n_0\
);
\aid_match_00_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
O => \aid_match_00_carry_i_1__0_n_0\
);
\aid_match_00_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8),
O => \aid_match_00_carry_i_2__0_n_0\
);
\aid_match_00_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
O => \aid_match_00_carry_i_3__0_n_0\
);
\aid_match_00_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
O => \aid_match_00_carry_i_4__0_n_0\
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_10_carry_i_1__0_n_0\,
S(2) => \aid_match_10_carry_i_2__0_n_0\,
S(1) => \aid_match_10_carry_i_3__0_n_0\,
S(0) => \aid_match_10_carry_i_4__0_n_0\
);
\aid_match_10_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \s_axi_awid[11]\(11),
O => \aid_match_10_carry_i_1__0_n_0\
);
\aid_match_10_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8),
I5 => \s_axi_awid[11]\(8),
O => \aid_match_10_carry_i_2__0_n_0\
);
\aid_match_10_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \s_axi_awid[11]\(5),
O => \aid_match_10_carry_i_3__0_n_0\
);
\aid_match_10_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I5 => \s_axi_awid[11]\(2),
O => \aid_match_10_carry_i_4__0_n_0\
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_20_carry_i_1__0_n_0\,
S(2) => \aid_match_20_carry_i_2__0_n_0\,
S(1) => \aid_match_20_carry_i_3__0_n_0\,
S(0) => \aid_match_20_carry_i_4__0_n_0\
);
\aid_match_20_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
O => \aid_match_20_carry_i_1__0_n_0\
);
\aid_match_20_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8),
O => \aid_match_20_carry_i_2__0_n_0\
);
\aid_match_20_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
O => \aid_match_20_carry_i_3__0_n_0\
);
\aid_match_20_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
O => \aid_match_20_carry_i_4__0_n_0\
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_30_carry_i_1__0_n_0\,
S(2) => \aid_match_30_carry_i_2__0_n_0\,
S(1) => \aid_match_30_carry_i_3__0_n_0\,
S(0) => \aid_match_30_carry_i_4__0_n_0\
);
\aid_match_30_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
O => \aid_match_30_carry_i_1__0_n_0\
);
\aid_match_30_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8),
O => \aid_match_30_carry_i_2__0_n_0\
);
\aid_match_30_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
O => \aid_match_30_carry_i_3__0_n_0\
);
\aid_match_30_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
O => \aid_match_30_carry_i_4__0_n_0\
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_40_carry_i_1__0_n_0\,
S(2) => \aid_match_40_carry_i_2__0_n_0\,
S(1) => \aid_match_40_carry_i_3__0_n_0\,
S(0) => \aid_match_40_carry_i_4__0_n_0\
);
\aid_match_40_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
O => \aid_match_40_carry_i_1__0_n_0\
);
\aid_match_40_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8),
O => \aid_match_40_carry_i_2__0_n_0\
);
\aid_match_40_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
O => \aid_match_40_carry_i_3__0_n_0\
);
\aid_match_40_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
O => \aid_match_40_carry_i_4__0_n_0\
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_50_carry_i_1__0_n_0\,
S(2) => \aid_match_50_carry_i_2__0_n_0\,
S(1) => \aid_match_50_carry_i_3__0_n_0\,
S(0) => \aid_match_50_carry_i_4__0_n_0\
);
\aid_match_50_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
O => \aid_match_50_carry_i_1__0_n_0\
);
\aid_match_50_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8),
O => \aid_match_50_carry_i_2__0_n_0\
);
\aid_match_50_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
O => \aid_match_50_carry_i_3__0_n_0\
);
\aid_match_50_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
O => \aid_match_50_carry_i_4__0_n_0\
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_60_carry_i_1__0_n_0\,
S(2) => \aid_match_60_carry_i_2__0_n_0\,
S(1) => \aid_match_60_carry_i_3__0_n_0\,
S(0) => \aid_match_60_carry_i_4__0_n_0\
);
\aid_match_60_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
O => \aid_match_60_carry_i_1__0_n_0\
);
\aid_match_60_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8),
O => \aid_match_60_carry_i_2__0_n_0\
);
\aid_match_60_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
O => \aid_match_60_carry_i_3__0_n_0\
);
\aid_match_60_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
O => \aid_match_60_carry_i_4__0_n_0\
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_70_carry_i_1__0_n_0\,
S(2) => \aid_match_70_carry_i_2__0_n_0\,
S(1) => \aid_match_70_carry_i_3__0_n_0\,
S(0) => \aid_match_70_carry_i_4__0_n_0\
);
\aid_match_70_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
O => \aid_match_70_carry_i_1__0_n_0\
);
\aid_match_70_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8),
O => \aid_match_70_carry_i_2__0_n_0\
);
\aid_match_70_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
O => \aid_match_70_carry_i_3__0_n_0\
);
\aid_match_70_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
O => \aid_match_70_carry_i_4__0_n_0\
);
\gen_multi_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\,
Q => \gen_multi_thread.accept_cnt_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_26\,
Q => \gen_multi_thread.accept_cnt_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_25\,
Q => \gen_multi_thread.accept_cnt_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_24\,
Q => \gen_multi_thread.accept_cnt_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp
port map (
ADDRESS_HIT_0 => ADDRESS_HIT_0,
E(0) => E(0),
Q(0) => \gen_multi_thread.accept_cnt_reg\(3),
SR(0) => \^sr\(0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0),
\gen_master_slots[2].w_issuing_cnt_reg[16]\(0) => \gen_master_slots[2].w_issuing_cnt_reg[16]\(0),
\gen_master_slots[3].w_issuing_cnt_reg[24]\(0) => \gen_master_slots[3].w_issuing_cnt_reg[24]\(0),
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_35_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\ => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\ => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\ => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\ => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]\(0) => \gen_no_arbiter.s_ready_i_reg[0]\(0),
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_no_arbiter.s_ready_i_reg[0]_0\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
match => match,
p_0_out => p_0_out_0,
p_101_in => p_101_in,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_68_out => p_68_out,
p_84_in => p_84_in,
p_88_out => p_88_out,
resp_select(0) => resp_select(2),
\s_axi_awaddr[30]\(2 downto 0) => \s_axi_awaddr[30]\(2 downto 0),
s_axi_bready(0) => s_axi_bready(0),
\s_axi_bvalid[0]\ => \^s_axi_bvalid[0]\,
s_ready_i_reg(4 downto 0) => Q(4 downto 0),
st_mr_bid(47 downto 0) => st_mr_bid(47 downto 0),
st_mr_bmesg(7 downto 0) => st_mr_bmesg(7 downto 0),
w_issuing_cnt(16 downto 0) => w_issuing_cnt(16 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(0),
I1 => cmd_push_0,
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(2),
I3 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(1),
I1 => cmd_push_0,
I2 => active_cnt(0),
I3 => active_cnt(3),
I4 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\,
Q => active_cnt(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\,
Q => active_cnt(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\,
Q => active_cnt(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_15\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\,
Q => active_cnt(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E222"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => aid_match_00,
I3 => \m_ready_d_reg[1]\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(1),
Q => active_target(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(2),
Q => active_target(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_1,
I1 => active_cnt(8),
I2 => active_cnt(10),
I3 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(9),
I1 => cmd_push_1,
I2 => active_cnt(8),
I3 => active_cnt(11),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(8),
I1 => cmd_push_1,
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\,
Q => active_cnt(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\,
Q => active_cnt(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\,
Q => active_cnt(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\,
Q => active_cnt(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => aid_match_10,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(2),
Q => active_target(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(1),
Q => active_target(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(16),
I1 => cmd_push_2,
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_2,
I1 => active_cnt(16),
I2 => active_cnt(18),
I3 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(17),
I1 => cmd_push_2,
I2 => active_cnt(16),
I3 => active_cnt(19),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\,
Q => active_cnt(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\,
Q => active_cnt(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\,
Q => active_cnt(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\,
Q => active_cnt(19),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80008000800080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => \thread_valid_2__2\,
I4 => aid_match_20,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
O => \thread_valid_0__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
O => \thread_valid_1__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
O => \thread_valid_2__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(1),
Q => active_target(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(2),
Q => active_target(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(24),
I1 => cmd_push_3,
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(26),
I3 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(25),
I1 => cmd_push_3,
I2 => active_cnt(24),
I3 => active_cnt(27),
I4 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\,
Q => active_cnt(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\,
Q => active_cnt(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\,
Q => active_cnt(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\,
Q => active_cnt(27),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I2 => \thread_valid_3__2\,
I3 => aid_match_30,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(1),
Q => active_target(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(2),
Q => active_target(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(32),
I1 => cmd_push_4,
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_4,
I1 => active_cnt(32),
I2 => active_cnt(34),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(33),
I1 => cmd_push_4,
I2 => active_cnt(32),
I3 => active_cnt(35),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\,
Q => active_cnt(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\,
Q => active_cnt(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\,
Q => active_cnt(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\,
Q => active_cnt(35),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
I1 => \thread_valid_3__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \thread_valid_4__2\,
I4 => aid_match_40,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555557FFFFFFFF"
)
port map (
I0 => \thread_valid_0__2\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
I5 => \thread_valid_2__2\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
O => \thread_valid_3__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
O => \thread_valid_4__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(1),
Q => active_target(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(2),
Q => active_target(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(40),
I1 => cmd_push_5,
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_5,
I1 => active_cnt(40),
I2 => active_cnt(42),
I3 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(41),
I1 => cmd_push_5,
I2 => active_cnt(40),
I3 => active_cnt(43),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\,
Q => active_cnt(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\,
Q => active_cnt(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\,
Q => active_cnt(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\,
Q => active_cnt(43),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I2 => \thread_valid_5__2\,
I3 => aid_match_50,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(1),
Q => active_target(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(2),
Q => active_target(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(48),
I1 => cmd_push_6,
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_6,
I1 => active_cnt(48),
I2 => active_cnt(50),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(49),
I1 => cmd_push_6,
I2 => active_cnt(48),
I3 => active_cnt(51),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\,
Q => active_cnt(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\,
Q => active_cnt(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\,
Q => active_cnt(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\,
Q => active_cnt(51),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \thread_valid_5__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \thread_valid_6__2\,
I4 => aid_match_60,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
O => \thread_valid_5__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(51),
I2 => active_cnt(49),
I3 => active_cnt(48),
O => \thread_valid_6__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(1),
Q => active_target(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(2),
Q => active_target(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(56),
I1 => cmd_push_7,
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_7,
I1 => active_cnt(56),
I2 => active_cnt(58),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(57),
I1 => cmd_push_7,
I2 => active_cnt(56),
I3 => active_cnt(59),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
O => \thread_valid_7__2\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\,
Q => active_cnt(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\,
Q => active_cnt(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\,
Q => active_cnt(58),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\,
Q => active_cnt(59),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_awaddr[30]\(2),
I1 => \s_axi_awaddr[30]\(0),
O => \^d\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \s_axi_awaddr[30]\(2),
I1 => \s_axi_awaddr[30]\(1),
O => \^d\(1)
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \aid_match_7__0\,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55555557"
)
port map (
I0 => \thread_valid_3__2\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
O => \accum_push_5__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => \thread_valid_6__2\,
I5 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\,
I4 => \aid_match_6__0\,
I5 => \aid_match_7__0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
O => \aid_match_7__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_00,
I1 => \thread_valid_0__2\,
I2 => aid_match_10,
I3 => \thread_valid_1__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_20,
I1 => \thread_valid_2__2\,
I2 => aid_match_30,
I3 => \thread_valid_3__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_40,
I1 => \thread_valid_4__2\,
I2 => aid_match_50,
I3 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(48),
I1 => active_cnt(49),
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => aid_match_60,
O => \aid_match_6__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(1),
Q => active_target(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(2),
Q => active_target(58),
R => \^sr\(0)
);
\gen_multi_thread.mux_resp_multi_thread\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\
port map (
CO(0) => p_14_out,
D(2) => \gen_multi_thread.mux_resp_multi_thread_n_24\,
D(1) => \gen_multi_thread.mux_resp_multi_thread_n_25\,
D(0) => \gen_multi_thread.mux_resp_multi_thread_n_26\,
E(0) => \gen_multi_thread.mux_resp_multi_thread_n_15\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_27\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_28\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_29\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_30\,
cmd_push_0 => cmd_push_0,
cmd_push_1 => cmd_push_1,
cmd_push_2 => cmd_push_2,
cmd_push_3 => cmd_push_3,
cmd_push_4 => cmd_push_4,
cmd_push_5 => cmd_push_5,
cmd_push_6 => cmd_push_6,
cmd_push_7 => cmd_push_7,
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_23\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_22\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_21\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_16\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_43\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_44\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_45\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_46\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_17\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_39\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_40\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_41\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_42\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_20\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_35\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_36\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_37\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_38\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_19\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_31\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_32\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_33\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_34\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_18\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11 downto 0),
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
m_valid_i_reg => \^s_axi_bvalid[0]\,
p_0_out => p_0_out_0,
resp_select(0) => resp_select(2),
\s_axi_bid[0]\ => \s_axi_bid[0]\,
\s_axi_bid[10]\ => \s_axi_bid[10]\,
\s_axi_bid[11]\ => \s_axi_bid[11]\,
\s_axi_bid[1]\ => \s_axi_bid[1]\,
\s_axi_bid[2]\ => \s_axi_bid[2]\,
\s_axi_bid[3]\ => \s_axi_bid[3]\,
\s_axi_bid[4]\ => \s_axi_bid[4]\,
\s_axi_bid[5]\ => \s_axi_bid[5]\,
\s_axi_bid[6]\ => \s_axi_bid[6]\,
\s_axi_bid[7]\ => \s_axi_bid[7]\,
\s_axi_bid[8]\ => \s_axi_bid[8]\,
\s_axi_bid[9]\ => \s_axi_bid[9]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
st_mr_bid(11 downto 0) => st_mr_bid(59 downto 48),
\thread_valid_0__2\ => \thread_valid_0__2\,
\thread_valid_1__2\ => \thread_valid_1__2\,
\thread_valid_2__2\ => \thread_valid_2__2\,
\thread_valid_3__2\ => \thread_valid_3__2\,
\thread_valid_4__2\ => \thread_valid_4__2\,
\thread_valid_5__2\ => \thread_valid_5__2\,
\thread_valid_6__2\ => \thread_valid_6__2\,
\thread_valid_7__2\ => \thread_valid_7__2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => match,
O => \^d\(2)
);
\gen_no_arbiter.s_ready_i[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(24),
I1 => active_cnt(25),
I2 => active_cnt(27),
I3 => active_cnt(26),
I4 => aid_match_30,
O => \aid_match_3__0\
);
\gen_no_arbiter.s_ready_i[0]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(17),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(16),
O => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(18),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(16),
I1 => active_cnt(17),
I2 => active_cnt(19),
I3 => active_cnt(18),
I4 => aid_match_20,
O => \aid_match_2__0\
);
\gen_no_arbiter.s_ready_i[0]_i_14\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(9),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(8),
O => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_15\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(10),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(8),
I1 => active_cnt(9),
I2 => active_cnt(11),
I3 => active_cnt(10),
I4 => aid_match_10,
O => \aid_match_1__0\
);
\gen_no_arbiter.s_ready_i[0]_i_17\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(1),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(0),
O => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(2),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(0),
I1 => active_cnt(1),
I2 => active_cnt(3),
I3 => active_cnt(2),
I4 => aid_match_00,
O => \aid_match_0__0\
);
\gen_no_arbiter.s_ready_i[0]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(49),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(48),
O => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_21\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(50),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(57),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(56),
O => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_23\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(58),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_28__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(41),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(40),
O => \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_29\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(42),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_29_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\,
I2 => \aid_match_3__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\,
I5 => \aid_match_2__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_30\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(40),
I1 => active_cnt(41),
I2 => active_cnt(43),
I3 => active_cnt(42),
I4 => aid_match_50,
O => \aid_match_5__0\
);
\gen_no_arbiter.s_ready_i[0]_i_31__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(33),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(32),
O => \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_32\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(34),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_32_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_33\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(32),
I1 => active_cnt(33),
I2 => active_cnt(35),
I3 => active_cnt(34),
I4 => aid_match_40,
O => \aid_match_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_35\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
I1 => \gen_multi_thread.accept_cnt_reg\(2),
I2 => \gen_multi_thread.accept_cnt_reg\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_35_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_15_n_0\,
I2 => \aid_match_1__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\,
I5 => \aid_match_0__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_21_n_0\,
I2 => \aid_match_6__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_23_n_0\,
I5 => \aid_match_7__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFE0E0E0E0E0"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_28__0_n_0\,
I1 => \gen_no_arbiter.s_ready_i[0]_i_29_n_0\,
I2 => \aid_match_5__0\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_31__0_n_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_32_n_0\,
I5 => \aid_match_4__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"5677FFDE"
)
port map (
I0 => active_target(25),
I1 => \s_axi_awaddr[30]\(2),
I2 => \s_axi_awaddr[30]\(1),
I3 => \s_axi_awaddr[30]\(0),
I4 => active_target(24),
O => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAA9"
)
port map (
I0 => active_target(26),
I1 => ADDRESS_HIT_0,
I2 => \s_axi_awaddr[30]\(0),
I3 => \s_axi_awaddr[30]\(2),
I4 => \s_axi_awaddr[30]\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_27\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_28\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_29\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_30\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_31\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_32\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_33\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_34\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_35\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_36\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_37\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_38\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_39\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_40\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_41\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_42\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_43\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_44\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_45\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_46\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\write_cs0__0\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
match : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
signal \/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal areset_d1 : STD_LOGIC;
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[1].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[2].srl_nx1_n_1\ : STD_LOGIC;
signal load_s1 : STD_LOGIC;
signal \m_aready0__3\ : STD_LOGIC;
signal \m_aready__1\ : STD_LOGIC;
signal m_avalid : STD_LOGIC;
signal m_select_enc : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_valid_i__0\ : STD_LOGIC;
signal m_valid_i_n_0 : STD_LOGIC;
signal p_0_in5_out : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal \s_ready_i1__4\ : STD_LOGIC;
signal \s_ready_i_i_1__9_n_0\ : STD_LOGIC;
signal \^ss_wr_awready\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair191";
attribute SOFT_HLUTNM of \m_axi_wvalid[2]_INST_0\ : label is "soft_lutpair192";
attribute SOFT_HLUTNM of \m_axi_wvalid[3]_INST_0\ : label is "soft_lutpair192";
begin
ss_wr_awready <= \^ss_wr_awready\;
\/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20202F20"
)
port map (
I0 => s_axi_awvalid(0),
I1 => m_ready_d(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[1]_i_1_n_0\
);
\/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0B0B0BF"
)
port map (
I0 => m_ready_d(0),
I1 => s_axi_awvalid(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"008A0000"
)
port map (
I0 => \m_aready__1\,
I1 => m_ready_d(0),
I2 => s_axi_awvalid(0),
I3 => p_9_in,
I4 => p_0_in8_in,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF488F488F488"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => \m_valid_i__0\
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00007500"
)
port map (
I0 => \m_aready__1\,
I1 => m_ready_d(0),
I2 => s_axi_awvalid(0),
I3 => p_0_in8_in,
I4 => p_9_in,
O => \FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => areset_d1
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \/FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => areset_d1
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \/FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => areset_d1
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => areset_d1
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => SR(0),
Q => areset_d1,
R => '0'
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000800000"
)
port map (
I0 => s_axi_wlast(0),
I1 => m_avalid,
I2 => s_axi_wvalid(0),
I3 => m_select_enc(0),
I4 => m_select_enc(2),
I5 => m_select_enc(1),
O => \write_cs0__0\
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => push,
I3 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FF77008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(0),
I3 => push,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8FFFFFF770000008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(0),
I3 => fifoaddr(1),
I4 => push,
I5 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\
port map (
D(0) => D(0),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
m_select_enc(0) => m_select_enc(0),
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
\s_axi_awaddr[30]\(1) => \s_axi_awaddr[30]\(2),
\s_axi_awaddr[30]\(0) => \s_axi_awaddr[30]\(0),
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[1].srl_nx1\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\
port map (
D(0) => D(1),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
m_select_enc(0) => m_select_enc(1),
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
push => push,
\s_axi_awaddr[30]\(1 downto 0) => \s_axi_awaddr[30]\(2 downto 1),
\storage_data1_reg[1]\ => \gen_srls[0].gen_rep[1].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[2].srl_nx1\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\
port map (
D(0) => D(2),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
\m_aready0__3\ => \m_aready0__3\,
\m_aready__1\ => \m_aready__1\,
m_avalid => m_avalid,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_ready_d(0) => m_ready_d(0),
m_select_enc(2 downto 0) => m_select_enc(2 downto 0),
match => match,
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
p_22_in => p_22_in,
push => push,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => \^ss_wr_awready\,
\storage_data1_reg[2]\ => \gen_srls[0].gen_rep[2].srl_nx1_n_1\
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(2)
);
\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(3)
);
m_valid_i: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF400F400F400"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i_n_0
);
m_valid_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(1),
I3 => fifoaddr(0),
I4 => fifoaddr(2),
I5 => push,
O => p_0_in5_out
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => m_valid_i_n_0,
Q => m_avalid,
R => areset_d1
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => m_avalid,
I1 => \m_aready0__3\,
O => s_axi_wready(0)
);
\s_ready_i_i_1__9\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0FFF0F8"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => areset_d1,
I3 => \s_ready_i1__4\,
I4 => \^ss_wr_awready\,
O => \s_ready_i_i_1__9_n_0\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000700000000000"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(2),
I3 => fifoaddr(1),
I4 => fifoaddr(0),
I5 => push,
O => \s_ready_i1__4\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__9_n_0\,
Q => \^ss_wr_awready\,
R => SR(0)
);
\storage_data1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0FCA0A0A0ECA0A0"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => p_9_in,
I2 => \m_aready__1\,
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => p_0_in8_in,
O => load_s1
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
Q => m_select_enc(0),
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[1].srl_nx1_n_0\,
Q => m_select_enc(1),
R => '0'
);
\storage_data1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[2].srl_nx1_n_1\,
Q => m_select_enc(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
port (
p_128_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_0__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\chosen_reg[2]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : in STD_LOGIC;
p_102_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
begin
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\chosen_reg[2]\ => \chosen_reg[2]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_128_out,
p_108_out => p_108_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[0]\(0) => \chosen_reg[0]\(0),
\chosen_reg[0]_0\(0) => \chosen_reg[0]_0\(0),
\chosen_reg[2]\ => \chosen_reg[2]\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_122_out,
p_102_out => p_102_out,
p_1_in => p_1_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 is
port (
p_108_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_102_out : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_1__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_75_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
\m_axi_bid[23]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 is
begin
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\
port map (
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
\m_axi_bid[23]\(13 downto 0) => \m_axi_bid[23]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_108_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\
port map (
ADDRESS_HIT_0 => ADDRESS_HIT_0,
D(0) => D(0),
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[1]\(0) => \chosen_reg[1]\(0),
\chosen_reg[1]_0\(0) => \chosen_reg[1]_0\(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0) => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[1]\ => \m_axi_rready[1]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_102_out,
p_1_in => p_1_in,
p_75_in => p_75_in,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 is
port (
p_88_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_82_out : out STD_LOGIC;
\m_axi_rready[2]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_2__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_57_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[24]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_axi_bid[35]\ : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 is
begin
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\
port map (
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
\m_axi_bid[35]\(13 downto 0) => \m_axi_bid[35]\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_88_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\
port map (
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[2]\(0) => \chosen_reg[2]\(0),
\chosen_reg[2]_0\(0) => \chosen_reg[2]_0\(0),
\gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0) => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0),
\gen_master_slots[3].r_issuing_cnt_reg[24]\ => \gen_master_slots[3].r_issuing_cnt_reg[24]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[2]\ => \m_axi_rready[2]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_82_out,
p_1_in => p_1_in,
p_57_in => p_57_in,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3 is
port (
p_68_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
p_62_out : out STD_LOGIC;
\m_axi_rready[3]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_3__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[4]\ : out STD_LOGIC;
\chosen_reg[4]_0\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_39_in : in STD_LOGIC;
p_82_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3 is
signal \^p_1_in\ : STD_LOGIC;
begin
p_1_in <= \^p_1_in\;
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\aresetn_d_reg[1]_1\ => \aresetn_d_reg[1]_1\,
\chosen_reg[4]\ => \chosen_reg[4]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_68_out,
p_1_in => \^p_1_in\,
p_88_out => p_88_out,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]_0\,
\chosen_reg[3]\(0) => \chosen_reg[3]\(0),
\chosen_reg[3]_0\(0) => \chosen_reg[3]_0\(0),
\chosen_reg[4]\ => \chosen_reg[4]\,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0) => \gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[3]\ => \m_axi_rready[3]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_62_out,
p_1_in => \^p_1_in\,
p_39_in => p_39_in,
p_82_out => p_82_out,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4 is
port (
p_46_out : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
mi_bready_4 : out STD_LOGIC;
p_40_out : out STD_LOGIC;
mi_rready_4 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
\r_cmd_pop_4__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_29_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_23_in : in STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_25_in : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4 is
signal \^m_valid_i_reg\ : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
D(11 downto 0) => D(11 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(11 downto 0),
\m_payload_i_reg[2]_0\ => p_46_out,
m_valid_i_reg_0 => \^m_valid_i_reg\,
mi_bready_4 => mi_bready_4,
p_1_in => p_1_in,
p_29_in => p_29_in,
s_axi_bready(0) => s_axi_bready(0),
s_ready_i_reg_0 => s_ready_i_reg
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \^m_valid_i_reg\,
\chosen_reg[4]\(0) => \chosen_reg[4]\(0),
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0),
m_valid_i_reg_0 => p_40_out,
p_1_in => p_1_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
s_axi_rready(0) => s_axi_rready(0),
\skid_buffer_reg[34]_0\ => mi_rready_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\write_cs0__0\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
match : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[30]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router is
begin
wrouter_aw_fifo: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
port map (
D(2 downto 0) => D(2 downto 0),
SR(0) => SR(0),
aclk => aclk,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(0) => m_ready_d(0),
match => match,
p_22_in => p_22_in,
\s_axi_awaddr[30]\(2 downto 0) => \s_axi_awaddr[30]\(2 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
\write_cs0__0\ => \write_cs0__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar is
port (
M_AXI_RREADY : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
\m_axi_arqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_axi_awready[0]\ : out STD_LOGIC;
\s_axi_bvalid[0]\ : out STD_LOGIC;
\s_axi_rvalid[0]\ : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 68 downto 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
aresetn : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar is
signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 4 to 4 );
signal aa_mi_arvalid : STD_LOGIC;
signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal aa_sa_awvalid : STD_LOGIC;
signal addr_arbiter_ar_n_79 : STD_LOGIC;
signal addr_arbiter_ar_n_80 : STD_LOGIC;
signal addr_arbiter_ar_n_81 : STD_LOGIC;
signal addr_arbiter_ar_n_82 : STD_LOGIC;
signal addr_arbiter_ar_n_83 : STD_LOGIC;
signal addr_arbiter_ar_n_84 : STD_LOGIC;
signal addr_arbiter_ar_n_85 : STD_LOGIC;
signal addr_arbiter_ar_n_86 : STD_LOGIC;
signal addr_arbiter_ar_n_87 : STD_LOGIC;
signal addr_arbiter_ar_n_88 : STD_LOGIC;
signal addr_arbiter_ar_n_89 : STD_LOGIC;
signal addr_arbiter_ar_n_90 : STD_LOGIC;
signal addr_arbiter_ar_n_99 : STD_LOGIC;
signal addr_arbiter_aw_n_23 : STD_LOGIC;
signal addr_arbiter_aw_n_25 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_54\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_55\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_53\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_53\ : STD_LOGIC;
signal \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_55\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_56\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_57\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_7\ : STD_LOGIC;
signal \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[4].reg_slice_mi_n_1\ : STD_LOGIC;
signal \gen_master_slots[4].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst/chosen\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst/chosen_9\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\ : STD_LOGIC;
signal \^m_axi_arqos[15]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_12 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_valid_i : STD_LOGIC;
signal m_valid_i_10 : STD_LOGIC;
signal match : STD_LOGIC;
signal match_3 : STD_LOGIC;
signal mi_arready_4 : STD_LOGIC;
signal mi_awready_4 : STD_LOGIC;
signal \mi_awready_mux__3\ : STD_LOGIC;
signal mi_bready_4 : STD_LOGIC;
signal mi_rready_4 : STD_LOGIC;
signal p_101_in : STD_LOGIC;
signal p_102_out : STD_LOGIC;
signal p_104_out : STD_LOGIC;
signal p_108_out : STD_LOGIC;
signal p_122_out : STD_LOGIC;
signal p_124_out : STD_LOGIC;
signal p_128_out : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_22_in : STD_LOGIC;
signal p_23_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_28_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_29_in : STD_LOGIC;
signal p_32_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_39_in : STD_LOGIC;
signal p_40_out : STD_LOGIC;
signal p_42_out : STD_LOGIC;
signal p_46_out : STD_LOGIC;
signal p_48_in : STD_LOGIC;
signal p_57_in : STD_LOGIC;
signal p_62_out : STD_LOGIC;
signal p_64_out : STD_LOGIC;
signal p_66_in : STD_LOGIC;
signal p_68_out : STD_LOGIC;
signal p_75_in : STD_LOGIC;
signal p_82_out : STD_LOGIC;
signal p_84_in : STD_LOGIC;
signal p_84_out : STD_LOGIC;
signal p_88_out : STD_LOGIC;
signal p_93_in : STD_LOGIC;
signal \r_cmd_pop_0__1\ : STD_LOGIC;
signal \r_cmd_pop_1__1\ : STD_LOGIC;
signal \r_cmd_pop_2__1\ : STD_LOGIC;
signal \r_cmd_pop_3__1\ : STD_LOGIC;
signal \r_cmd_pop_4__1\ : STD_LOGIC;
signal r_issuing_cnt : STD_LOGIC_VECTOR ( 32 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal \r_pipe/p_1_in_5\ : STD_LOGIC;
signal \r_pipe/p_1_in_6\ : STD_LOGIC;
signal \r_pipe/p_1_in_7\ : STD_LOGIC;
signal \r_pipe/p_1_in_8\ : STD_LOGIC;
signal \read_cs__0\ : STD_LOGIC;
signal reset : STD_LOGIC;
signal \^s_axi_awready[0]\ : STD_LOGIC;
signal s_axi_rlast_i0 : STD_LOGIC;
signal s_axi_rvalid_i : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal s_ready_i0_11 : STD_LOGIC;
signal \s_ready_i0__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \sa_wm_awready_mux__3\ : STD_LOGIC;
signal splitter_aw_mi_n_0 : STD_LOGIC;
signal splitter_aw_mi_n_1 : STD_LOGIC;
signal splitter_aw_mi_n_10 : STD_LOGIC;
signal splitter_aw_mi_n_11 : STD_LOGIC;
signal splitter_aw_mi_n_12 : STD_LOGIC;
signal splitter_aw_mi_n_2 : STD_LOGIC;
signal splitter_aw_mi_n_3 : STD_LOGIC;
signal splitter_aw_mi_n_4 : STD_LOGIC;
signal splitter_aw_mi_n_5 : STD_LOGIC;
signal splitter_aw_mi_n_6 : STD_LOGIC;
signal splitter_aw_mi_n_7 : STD_LOGIC;
signal splitter_aw_mi_n_8 : STD_LOGIC;
signal splitter_aw_mi_n_9 : STD_LOGIC;
signal ss_aa_awready : STD_LOGIC;
signal ss_wr_awready : STD_LOGIC;
signal ss_wr_awvalid : STD_LOGIC;
signal st_aa_awtarget_enc : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_bid : STD_LOGIC_VECTOR ( 59 downto 0 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 10 downto 0 );
signal st_mr_rid : STD_LOGIC_VECTOR ( 59 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 139 downto 0 );
signal w_issuing_cnt : STD_LOGIC_VECTOR ( 32 downto 0 );
signal write_cs01_out : STD_LOGIC;
signal \write_cs0__0\ : STD_LOGIC;
begin
Q(68 downto 0) <= \^q\(68 downto 0);
S_AXI_ARREADY(0) <= \^s_axi_arready\(0);
\m_axi_arqos[15]\(68 downto 0) <= \^m_axi_arqos[15]\(68 downto 0);
\s_axi_awready[0]\ <= \^s_axi_awready[0]\;
addr_arbiter_ar: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
E(0) => s_ready_i0,
Q(0) => aa_mi_artarget_hot(4),
SR(0) => reset,
S_AXI_ARREADY(0) => \^s_axi_arready\(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
\gen_axi.s_axi_rid_i_reg[11]\(0) => s_axi_rvalid_i,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(2) => addr_arbiter_ar_n_79,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(1) => addr_arbiter_ar_n_80,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(0) => addr_arbiter_ar_n_81,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(2) => addr_arbiter_ar_n_82,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(1) => addr_arbiter_ar_n_83,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(0) => addr_arbiter_ar_n_84,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(2) => addr_arbiter_ar_n_88,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(1) => addr_arbiter_ar_n_89,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(0) => addr_arbiter_ar_n_90,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(2) => addr_arbiter_ar_n_85,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(1) => addr_arbiter_ar_n_86,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(0) => addr_arbiter_ar_n_87,
\gen_master_slots[4].r_issuing_cnt_reg[32]\ => addr_arbiter_ar_n_99,
\m_axi_arqos[15]\(68 downto 0) => \^m_axi_arqos[15]\(68 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_valid_i => m_valid_i,
match => match,
mi_arready_4 => mi_arready_4,
p_23_in => p_23_in,
p_39_in => p_39_in,
p_57_in => p_57_in,
p_75_in => p_75_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(16) => r_issuing_cnt(32),
r_issuing_cnt(15 downto 12) => r_issuing_cnt(27 downto 24),
r_issuing_cnt(11 downto 8) => r_issuing_cnt(19 downto 16),
r_issuing_cnt(7 downto 4) => r_issuing_cnt(11 downto 8),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0),
\read_cs__0\ => \read_cs__0\,
\s_axi_araddr[24]\(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\,
\s_axi_arqos[3]\(68 downto 0) => \s_axi_arqos[3]\(68 downto 0),
s_axi_rlast_i0 => s_axi_rlast_i0
);
addr_arbiter_aw: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\,
D(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
E(0) => s_ready_i0_11,
Q(4 downto 0) => aa_mi_awtarget_hot(4 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
\chosen_reg[4]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4),
\gen_master_slots[4].w_issuing_cnt_reg[32]\ => addr_arbiter_aw_n_25,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_23,
\m_axi_awqos[15]\(68 downto 0) => \^q\(68 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d_12(1 downto 0),
m_ready_d_0(0) => m_ready_d(0),
m_valid_i => m_valid_i_10,
match => match_3,
mi_awready_4 => mi_awready_4,
\mi_awready_mux__3\ => \mi_awready_mux__3\,
p_101_in => p_101_in,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_84_in => p_84_in,
\s_axi_awaddr[24]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
\s_axi_awqos[3]\(68 downto 0) => D(68 downto 0),
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
\s_ready_i0__1\(0) => \s_ready_i0__1\(0),
\sa_wm_awready_mux__3\ => \sa_wm_awready_mux__3\,
ss_aa_awready => ss_aa_awready,
w_issuing_cnt(0) => w_issuing_cnt(32),
write_cs01_out => write_cs01_out
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr_slave.decerr_slave_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave
port map (
E(0) => s_axi_rvalid_i,
Q(0) => aa_mi_awtarget_hot(4),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_no_arbiter.m_mesg_i_reg[11]\(11 downto 0) => \^q\(11 downto 0),
\gen_no_arbiter.m_mesg_i_reg[51]\(19 downto 12) => \^m_axi_arqos[15]\(51 downto 44),
\gen_no_arbiter.m_mesg_i_reg[51]\(11 downto 0) => \^m_axi_arqos[15]\(11 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[4]\(0) => aa_mi_artarget_hot(4),
\m_payload_i_reg[13]\(11 downto 0) => p_32_in(11 downto 0),
m_ready_d(0) => m_ready_d_12(1),
\m_ready_d_reg[1]\ => splitter_aw_mi_n_3,
mi_arready_4 => mi_arready_4,
mi_awready_4 => mi_awready_4,
mi_bready_4 => mi_bready_4,
mi_rready_4 => mi_rready_4,
p_22_in => p_22_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
p_29_in => p_29_in,
\read_cs__0\ => \read_cs__0\,
s_axi_rlast_i0 => s_axi_rlast_i0,
\skid_buffer_reg[46]\(11 downto 0) => p_28_in(11 downto 0),
write_cs01_out => write_cs01_out,
\write_cs0__0\ => \write_cs0__0\
);
\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(0),
O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\,
Q => r_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_81,
Q => r_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_80,
Q => r_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_79,
Q => r_issuing_cnt(3),
R => reset
);
\gen_master_slots[0].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
port map (
D(13 downto 2) => m_axi_bid(11 downto 0),
D(1 downto 0) => m_axi_bresp(1 downto 0),
E(0) => \gen_master_slots[0].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[0]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(0),
\chosen_reg[0]_0\(0) => \r_pipe/p_1_in_8\,
\chosen_reg[2]\ => \gen_master_slots[0].reg_slice_mi_n_54\,
\chosen_reg[2]_0\ => \gen_master_slots[0].reg_slice_mi_n_55\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => r_issuing_cnt(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_124_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(34 downto 3),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(1 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_6\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => M_AXI_RREADY(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
p_102_out => p_102_out,
p_108_out => p_108_out,
p_122_out => p_122_out,
p_128_out => p_128_out,
p_1_in => p_1_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(0),
O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\,
Q => w_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_12,
Q => w_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_11,
Q => w_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_10,
Q => w_issuing_cnt(3),
R => reset
);
\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(8),
O => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].r_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_83,
Q => r_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_82,
Q => r_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\,
Q => r_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_84,
Q => r_issuing_cnt(9),
R => reset
);
\gen_master_slots[1].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
E(0) => \gen_master_slots[1].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(1),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[1]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(1),
\chosen_reg[1]_0\(0) => \r_pipe/p_1_in_7\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_6\,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0) => r_issuing_cnt(11 downto 8),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_104_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(36 downto 35),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(69 downto 38),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(4 downto 3),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_53\,
\m_axi_bid[23]\(13 downto 2) => m_axi_bid(23 downto 12),
\m_axi_bid[23]\(1 downto 0) => m_axi_bresp(3 downto 2),
m_axi_bready(0) => m_axi_bready(1),
m_axi_bvalid(0) => m_axi_bvalid(1),
m_axi_rdata(31 downto 0) => m_axi_rdata(63 downto 32),
m_axi_rid(11 downto 0) => m_axi_rid(23 downto 12),
m_axi_rlast(0) => m_axi_rlast(1),
\m_axi_rready[1]\ => M_AXI_RREADY(1),
m_axi_rresp(1 downto 0) => m_axi_rresp(3 downto 2),
m_axi_rvalid(0) => m_axi_rvalid(1),
p_102_out => p_102_out,
p_108_out => p_108_out,
p_1_in => p_1_in,
p_75_in => p_75_in,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(8),
O => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].w_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_1,
Q => w_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_0,
Q => w_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\,
Q => w_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_2,
Q => w_issuing_cnt(9),
R => reset
);
\gen_master_slots[2].r_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(16),
O => \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\
);
\gen_master_slots[2].r_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\,
Q => r_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_90,
Q => r_issuing_cnt(17),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_89,
Q => r_issuing_cnt(18),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_88,
Q => r_issuing_cnt(19),
R => reset
);
\gen_master_slots[2].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2
port map (
D(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
D(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
E(0) => \gen_master_slots[2].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(2),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2),
\chosen_reg[2]_0\(0) => \r_pipe/p_1_in\,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0) => r_issuing_cnt(19 downto 16),
\gen_master_slots[3].r_issuing_cnt_reg[24]\ => \gen_master_slots[3].reg_slice_mi_n_7\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_84_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(71 downto 70),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(104 downto 73),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(7 downto 6),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[2].reg_slice_mi_n_53\,
\m_axi_bid[35]\(13 downto 2) => m_axi_bid(35 downto 24),
\m_axi_bid[35]\(1 downto 0) => m_axi_bresp(5 downto 4),
m_axi_bready(0) => m_axi_bready(2),
m_axi_bvalid(0) => m_axi_bvalid(2),
m_axi_rdata(31 downto 0) => m_axi_rdata(95 downto 64),
m_axi_rid(11 downto 0) => m_axi_rid(35 downto 24),
m_axi_rlast(0) => m_axi_rlast(2),
\m_axi_rready[2]\ => M_AXI_RREADY(2),
m_axi_rresp(1 downto 0) => m_axi_rresp(5 downto 4),
m_axi_rvalid(0) => m_axi_rvalid(2),
p_1_in => p_1_in,
p_57_in => p_57_in,
p_82_out => p_82_out,
p_88_out => p_88_out,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[2].w_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(16),
O => \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\
);
\gen_master_slots[2].w_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\,
Q => w_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_6,
Q => w_issuing_cnt(17),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_5,
Q => w_issuing_cnt(18),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_4,
Q => w_issuing_cnt(19),
R => reset
);
\gen_master_slots[3].r_issuing_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(24),
O => \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\
);
\gen_master_slots[3].r_issuing_cnt_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\,
Q => r_issuing_cnt(24),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_87,
Q => r_issuing_cnt(25),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_86,
Q => r_issuing_cnt(26),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_85,
Q => r_issuing_cnt(27),
R => reset
);
\gen_master_slots[3].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3
port map (
D(13 downto 2) => m_axi_bid(47 downto 36),
D(1 downto 0) => m_axi_bresp(7 downto 6),
E(0) => \gen_master_slots[3].reg_slice_mi_n_5\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(3),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \gen_master_slots[3].reg_slice_mi_n_57\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_1\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(3),
\chosen_reg[3]_0\(0) => \r_pipe/p_1_in_5\,
\chosen_reg[4]\ => \gen_master_slots[3].reg_slice_mi_n_55\,
\chosen_reg[4]_0\ => \gen_master_slots[3].reg_slice_mi_n_56\,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(3 downto 0) => r_issuing_cnt(27 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(47 downto 36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_64_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(106 downto 105),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(139 downto 108),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(47 downto 36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(10 downto 9),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[3].reg_slice_mi_n_7\,
m_axi_bready(0) => m_axi_bready(3),
m_axi_bvalid(0) => m_axi_bvalid(3),
m_axi_rdata(31 downto 0) => m_axi_rdata(127 downto 96),
m_axi_rid(11 downto 0) => m_axi_rid(47 downto 36),
m_axi_rlast(0) => m_axi_rlast(3),
\m_axi_rready[3]\ => M_AXI_RREADY(3),
m_axi_rresp(1 downto 0) => m_axi_rresp(7 downto 6),
m_axi_rvalid(0) => m_axi_rvalid(3),
p_1_in => p_1_in,
p_39_in => p_39_in,
p_62_out => p_62_out,
p_68_out => p_68_out,
p_82_out => p_82_out,
p_88_out => p_88_out,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[3].w_issuing_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(24),
O => \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\
);
\gen_master_slots[3].w_issuing_cnt_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\,
Q => w_issuing_cnt(24),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_9,
Q => w_issuing_cnt(25),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_8,
Q => w_issuing_cnt(26),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_7,
Q => w_issuing_cnt(27),
R => reset
);
\gen_master_slots[4].r_issuing_cnt_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_ar_n_99,
Q => r_issuing_cnt(32),
R => reset
);
\gen_master_slots[4].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4
port map (
D(11 downto 0) => p_32_in(11 downto 0),
E(0) => \r_pipe/p_1_in_6\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4),
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_master_slots[3].reg_slice_mi_n_57\,
\chosen_reg[4]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(4),
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => p_28_in(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 1) => st_mr_rid(59 downto 48),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => p_42_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(11 downto 0) => st_mr_bid(59 downto 48),
m_valid_i_reg => \gen_master_slots[4].reg_slice_mi_n_1\,
mi_bready_4 => mi_bready_4,
mi_rready_4 => mi_rready_4,
p_1_in => p_1_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
p_29_in => p_29_in,
p_40_out => p_40_out,
p_46_out => p_46_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0),
s_ready_i_reg => \gen_master_slots[4].reg_slice_mi_n_5\
);
\gen_master_slots[4].w_issuing_cnt_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_aw_n_25,
Q => w_issuing_cnt(32),
R => reset
);
\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
D(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\,
E(0) => s_ready_i0,
Q(4 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(4 downto 0),
SR(0) => reset,
S_AXI_ARREADY(0) => \^s_axi_arready\(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_53\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_53\,
\m_payload_i_reg[0]\(0) => \r_pipe/p_1_in_8\,
\m_payload_i_reg[0]_0\(0) => \r_pipe/p_1_in_7\,
\m_payload_i_reg[0]_1\(0) => \r_pipe/p_1_in_5\,
\m_payload_i_reg[0]_2\(0) => \r_pipe/p_1_in\,
\m_payload_i_reg[34]\(0) => \r_pipe/p_1_in_6\,
\m_payload_i_reg[34]_0\(0) => p_42_out,
\m_payload_i_reg[34]_1\(0) => p_64_out,
\m_payload_i_reg[34]_2\(0) => p_124_out,
\m_payload_i_reg[34]_3\(0) => p_84_out,
\m_payload_i_reg[34]_4\(0) => p_104_out,
m_valid_i => m_valid_i,
m_valid_i_reg => \gen_master_slots[3].reg_slice_mi_n_55\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_54\,
match => match,
p_102_out => p_102_out,
p_122_out => p_122_out,
p_40_out => p_40_out,
p_62_out => p_62_out,
p_82_out => p_82_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(0) => r_issuing_cnt(32),
\s_axi_araddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
\s_axi_araddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2\,
\s_axi_araddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
\s_axi_arid[11]\(11 downto 0) => \s_axi_arqos[3]\(11 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => \s_axi_rid[0]\,
\s_axi_rid[10]\ => \s_axi_rid[10]\,
\s_axi_rid[11]\ => \s_axi_rid[11]\,
\s_axi_rid[1]\ => \s_axi_rid[1]\,
\s_axi_rid[2]\ => \s_axi_rid[2]\,
\s_axi_rid[3]\ => \s_axi_rid[3]\,
\s_axi_rid[4]\ => \s_axi_rid[4]\,
\s_axi_rid[5]\ => \s_axi_rid[5]\,
\s_axi_rid[6]\ => \s_axi_rid[6]\,
\s_axi_rid[7]\ => \s_axi_rid[7]\,
\s_axi_rid[8]\ => \s_axi_rid[8]\,
\s_axi_rid[9]\ => \s_axi_rid[9]\,
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
\s_axi_rvalid[0]\ => \s_axi_rvalid[0]\,
st_mr_rid(59 downto 0) => st_mr_rid(59 downto 0),
st_mr_rmesg(135 downto 104) => st_mr_rmesg(139 downto 108),
st_mr_rmesg(103 downto 70) => st_mr_rmesg(106 downto 73),
st_mr_rmesg(69 downto 36) => st_mr_rmesg(71 downto 38),
st_mr_rmesg(35 downto 2) => st_mr_rmesg(36 downto 3),
st_mr_rmesg(1 downto 0) => st_mr_rmesg(1 downto 0)
);
\gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_4\,
D(2) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
D(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
E(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
Q(4 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(4 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
\gen_master_slots[3].w_issuing_cnt_reg[24]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
\gen_no_arbiter.s_ready_i_reg[0]\(0) => s_ready_i0_11,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_23,
\m_ready_d_reg[1]\ => \^s_axi_awready[0]\,
m_valid_i => m_valid_i_10,
m_valid_i_reg => \gen_master_slots[3].reg_slice_mi_n_56\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_55\,
match => match_3,
p_101_in => p_101_in,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_68_out => p_68_out,
p_84_in => p_84_in,
p_88_out => p_88_out,
\s_axi_awaddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
\s_axi_awaddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
\s_axi_awaddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
\s_axi_awid[11]\(11 downto 0) => D(11 downto 0),
\s_axi_bid[0]\ => \s_axi_bid[0]\,
\s_axi_bid[10]\ => \s_axi_bid[10]\,
\s_axi_bid[11]\ => \s_axi_bid[11]\,
\s_axi_bid[1]\ => \s_axi_bid[1]\,
\s_axi_bid[2]\ => \s_axi_bid[2]\,
\s_axi_bid[3]\ => \s_axi_bid[3]\,
\s_axi_bid[4]\ => \s_axi_bid[4]\,
\s_axi_bid[5]\ => \s_axi_bid[5]\,
\s_axi_bid[6]\ => \s_axi_bid[6]\,
\s_axi_bid[7]\ => \s_axi_bid[7]\,
\s_axi_bid[8]\ => \s_axi_bid[8]\,
\s_axi_bid[9]\ => \s_axi_bid[9]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
\s_axi_bvalid[0]\ => \s_axi_bvalid[0]\,
st_mr_bid(59 downto 0) => st_mr_bid(59 downto 0),
st_mr_bmesg(7 downto 6) => st_mr_bmesg(10 downto 9),
st_mr_bmesg(5 downto 4) => st_mr_bmesg(7 downto 6),
st_mr_bmesg(3 downto 2) => st_mr_bmesg(4 downto 3),
st_mr_bmesg(1 downto 0) => st_mr_bmesg(1 downto 0),
w_issuing_cnt(16) => w_issuing_cnt(32),
w_issuing_cnt(15 downto 12) => w_issuing_cnt(27 downto 24),
w_issuing_cnt(11 downto 8) => w_issuing_cnt(19 downto 16),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
\gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
\s_axi_awready[0]\ => \^s_axi_awready[0]\,
s_axi_awvalid(0) => s_axi_awvalid(0),
ss_aa_awready => ss_aa_awready,
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid
);
\gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router
port map (
D(2) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
D(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
SR(0) => reset,
aclk => aclk,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(0) => m_ready_d(1),
match => match_3,
p_22_in => p_22_in,
\s_axi_awaddr[30]\(2) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_2\,
\s_axi_awaddr[30]\(1) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_2_1\,
\s_axi_awaddr[30]\(0) => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
\write_cs0__0\ => \write_cs0__0\
);
splitter_aw_mi: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5
port map (
D(2) => splitter_aw_mi_n_0,
D(1) => splitter_aw_mi_n_1,
D(0) => splitter_aw_mi_n_2,
Q(3 downto 0) => aa_mi_awtarget_hot(3 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\chosen_reg[3]\(3 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_9\(3 downto 0),
\gen_axi.s_axi_awready_i_reg\ => splitter_aw_mi_n_3,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(2) => splitter_aw_mi_n_10,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(1) => splitter_aw_mi_n_11,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(0) => splitter_aw_mi_n_12,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(2) => splitter_aw_mi_n_4,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(1) => splitter_aw_mi_n_5,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(0) => splitter_aw_mi_n_6,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(2) => splitter_aw_mi_n_7,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(1) => splitter_aw_mi_n_8,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(0) => splitter_aw_mi_n_9,
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d_12(1 downto 0),
\mi_awready_mux__3\ => \mi_awready_mux__3\,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_68_out => p_68_out,
p_88_out => p_88_out,
s_axi_bready(0) => s_axi_bready(0),
\s_ready_i0__1\(0) => \s_ready_i0__1\(0),
\sa_wm_awready_mux__3\ => \sa_wm_awready_mux__3\,
w_issuing_cnt(15 downto 12) => w_issuing_cnt(27 downto 24),
w_issuing_cnt(11 downto 8) => w_issuing_cnt(19 downto 16),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001101000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 127 downto 96 );
signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 127 downto 96 );
signal \^m_axi_awburst\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \^m_axi_awcache\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 31 downto 24 );
signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^m_axi_awprot\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_awqos\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\(0) <= s_axi_wlast(0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(127 downto 96) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(95 downto 64) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(63 downto 32) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(127 downto 96);
m_axi_arburst(7 downto 6) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(5 downto 4) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(7 downto 6);
m_axi_arcache(15 downto 12) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(11 downto 8) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(15 downto 12);
m_axi_arid(47 downto 36) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(35 downto 24) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_arlen(31 downto 24) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(23 downto 16) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(15 downto 8) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlock(3) <= \^m_axi_arlock\(3);
m_axi_arlock(2) <= \^m_axi_arlock\(3);
m_axi_arlock(1) <= \^m_axi_arlock\(3);
m_axi_arlock(0) <= \^m_axi_arlock\(3);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(11 downto 9);
m_axi_arqos(15 downto 12) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(11 downto 8) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(15 downto 12);
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
m_axi_arregion(12) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(11 downto 9) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(8 downto 6) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(11 downto 9);
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(127 downto 96) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(95 downto 64) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(63 downto 32) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awburst(7 downto 6) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(5 downto 4) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(3 downto 2) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(1 downto 0) <= \^m_axi_awburst\(7 downto 6);
m_axi_awcache(15 downto 12) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(11 downto 8) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(7 downto 4) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(3 downto 0) <= \^m_axi_awcache\(15 downto 12);
m_axi_awid(47 downto 36) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(35 downto 24) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(23 downto 12) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(11 downto 0) <= \^m_axi_awid\(11 downto 0);
m_axi_awlen(31 downto 24) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(23 downto 16) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlock(3) <= \^m_axi_awlock\(3);
m_axi_awlock(2) <= \^m_axi_awlock\(3);
m_axi_awlock(1) <= \^m_axi_awlock\(3);
m_axi_awlock(0) <= \^m_axi_awlock\(3);
m_axi_awprot(11 downto 9) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(8 downto 6) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(5 downto 3) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(2 downto 0) <= \^m_axi_awprot\(11 downto 9);
m_axi_awqos(15 downto 12) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(11 downto 8) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(7 downto 4) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(3 downto 0) <= \^m_axi_awqos\(15 downto 12);
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
m_axi_awregion(12) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(11 downto 9) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(8 downto 6) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(5 downto 3) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(2 downto 0) <= \^m_axi_awsize\(11 downto 9);
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(47) <= \<const0>\;
m_axi_wid(46) <= \<const0>\;
m_axi_wid(45) <= \<const0>\;
m_axi_wid(44) <= \<const0>\;
m_axi_wid(43) <= \<const0>\;
m_axi_wid(42) <= \<const0>\;
m_axi_wid(41) <= \<const0>\;
m_axi_wid(40) <= \<const0>\;
m_axi_wid(39) <= \<const0>\;
m_axi_wid(38) <= \<const0>\;
m_axi_wid(37) <= \<const0>\;
m_axi_wid(36) <= \<const0>\;
m_axi_wid(35) <= \<const0>\;
m_axi_wid(34) <= \<const0>\;
m_axi_wid(33) <= \<const0>\;
m_axi_wid(32) <= \<const0>\;
m_axi_wid(31) <= \<const0>\;
m_axi_wid(30) <= \<const0>\;
m_axi_wid(29) <= \<const0>\;
m_axi_wid(28) <= \<const0>\;
m_axi_wid(27) <= \<const0>\;
m_axi_wid(26) <= \<const0>\;
m_axi_wid(25) <= \<const0>\;
m_axi_wid(24) <= \<const0>\;
m_axi_wid(23) <= \<const0>\;
m_axi_wid(22) <= \<const0>\;
m_axi_wid(21) <= \<const0>\;
m_axi_wid(20) <= \<const0>\;
m_axi_wid(19) <= \<const0>\;
m_axi_wid(18) <= \<const0>\;
m_axi_wid(17) <= \<const0>\;
m_axi_wid(16) <= \<const0>\;
m_axi_wid(15) <= \<const0>\;
m_axi_wid(14) <= \<const0>\;
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(3) <= \^s_axi_wlast\(0);
m_axi_wlast(2) <= \^s_axi_wlast\(0);
m_axi_wlast(1) <= \^s_axi_wlast\(0);
m_axi_wlast(0) <= \^s_axi_wlast\(0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_samd.crossbar_samd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar
port map (
D(68 downto 65) => s_axi_awqos(3 downto 0),
D(64 downto 61) => s_axi_awcache(3 downto 0),
D(60 downto 59) => s_axi_awburst(1 downto 0),
D(58 downto 56) => s_axi_awprot(2 downto 0),
D(55) => s_axi_awlock(0),
D(54 downto 52) => s_axi_awsize(2 downto 0),
D(51 downto 44) => s_axi_awlen(7 downto 0),
D(43 downto 12) => s_axi_awaddr(31 downto 0),
D(11 downto 0) => s_axi_awid(11 downto 0),
M_AXI_RREADY(3 downto 0) => m_axi_rready(3 downto 0),
Q(68 downto 65) => \^m_axi_awqos\(15 downto 12),
Q(64 downto 61) => \^m_axi_awcache\(15 downto 12),
Q(60 downto 59) => \^m_axi_awburst\(7 downto 6),
Q(58 downto 56) => \^m_axi_awprot\(11 downto 9),
Q(55) => \^m_axi_awlock\(3),
Q(54 downto 52) => \^m_axi_awsize\(11 downto 9),
Q(51 downto 44) => \^m_axi_awlen\(31 downto 24),
Q(43 downto 12) => \^m_axi_awaddr\(127 downto 96),
Q(11 downto 0) => \^m_axi_awid\(11 downto 0),
S_AXI_ARREADY(0) => s_axi_arready(0),
aclk => aclk,
aresetn => aresetn,
\m_axi_arqos[15]\(68 downto 65) => \^m_axi_arqos\(15 downto 12),
\m_axi_arqos[15]\(64 downto 61) => \^m_axi_arcache\(15 downto 12),
\m_axi_arqos[15]\(60 downto 59) => \^m_axi_arburst\(7 downto 6),
\m_axi_arqos[15]\(58 downto 56) => \^m_axi_arprot\(11 downto 9),
\m_axi_arqos[15]\(55) => \^m_axi_arlock\(3),
\m_axi_arqos[15]\(54 downto 52) => \^m_axi_arsize\(11 downto 9),
\m_axi_arqos[15]\(51 downto 44) => \^m_axi_arlen\(7 downto 0),
\m_axi_arqos[15]\(43 downto 12) => \^m_axi_araddr\(127 downto 96),
\m_axi_arqos[15]\(11 downto 0) => \^m_axi_arid\(11 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => m_axi_bid(47 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => m_axi_rid(47 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
\s_axi_arqos[3]\(68 downto 65) => s_axi_arqos(3 downto 0),
\s_axi_arqos[3]\(64 downto 61) => s_axi_arcache(3 downto 0),
\s_axi_arqos[3]\(60 downto 59) => s_axi_arburst(1 downto 0),
\s_axi_arqos[3]\(58 downto 56) => s_axi_arprot(2 downto 0),
\s_axi_arqos[3]\(55) => s_axi_arlock(0),
\s_axi_arqos[3]\(54 downto 52) => s_axi_arsize(2 downto 0),
\s_axi_arqos[3]\(51 downto 44) => s_axi_arlen(7 downto 0),
\s_axi_arqos[3]\(43 downto 12) => s_axi_araddr(31 downto 0),
\s_axi_arqos[3]\(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
\s_axi_awready[0]\ => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
\s_axi_bid[0]\ => s_axi_bid(0),
\s_axi_bid[10]\ => s_axi_bid(10),
\s_axi_bid[11]\ => s_axi_bid(11),
\s_axi_bid[1]\ => s_axi_bid(1),
\s_axi_bid[2]\ => s_axi_bid(2),
\s_axi_bid[3]\ => s_axi_bid(3),
\s_axi_bid[4]\ => s_axi_bid(4),
\s_axi_bid[5]\ => s_axi_bid(5),
\s_axi_bid[6]\ => s_axi_bid(6),
\s_axi_bid[7]\ => s_axi_bid(7),
\s_axi_bid[8]\ => s_axi_bid(8),
\s_axi_bid[9]\ => s_axi_bid(9),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
\s_axi_bvalid[0]\ => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => s_axi_rid(0),
\s_axi_rid[10]\ => s_axi_rid(10),
\s_axi_rid[11]\ => s_axi_rid(11),
\s_axi_rid[1]\ => s_axi_rid(1),
\s_axi_rid[2]\ => s_axi_rid(2),
\s_axi_rid[3]\ => s_axi_rid(3),
\s_axi_rid[4]\ => s_axi_rid(4),
\s_axi_rid[5]\ => s_axi_rid(5),
\s_axi_rid[6]\ => s_axi_rid(6),
\s_axi_rid[7]\ => s_axi_rid(7),
\s_axi_rid[8]\ => s_axi_rid(8),
\s_axi_rid[9]\ => s_axi_rid(9),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
\s_axi_rvalid[0]\ => s_axi_rvalid(0),
s_axi_wlast(0) => \^s_axi_wlast\(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "128'b00000000000000000000000000001101000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 8;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(127 downto 0) => m_axi_araddr(127 downto 0),
m_axi_arburst(7 downto 0) => m_axi_arburst(7 downto 0),
m_axi_arcache(15 downto 0) => m_axi_arcache(15 downto 0),
m_axi_arid(47 downto 0) => m_axi_arid(47 downto 0),
m_axi_arlen(31 downto 0) => m_axi_arlen(31 downto 0),
m_axi_arlock(3 downto 0) => m_axi_arlock(3 downto 0),
m_axi_arprot(11 downto 0) => m_axi_arprot(11 downto 0),
m_axi_arqos(15 downto 0) => m_axi_arqos(15 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arregion(15 downto 0) => m_axi_arregion(15 downto 0),
m_axi_arsize(11 downto 0) => m_axi_arsize(11 downto 0),
m_axi_aruser(3 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awaddr(127 downto 0) => m_axi_awaddr(127 downto 0),
m_axi_awburst(7 downto 0) => m_axi_awburst(7 downto 0),
m_axi_awcache(15 downto 0) => m_axi_awcache(15 downto 0),
m_axi_awid(47 downto 0) => m_axi_awid(47 downto 0),
m_axi_awlen(31 downto 0) => m_axi_awlen(31 downto 0),
m_axi_awlock(3 downto 0) => m_axi_awlock(3 downto 0),
m_axi_awprot(11 downto 0) => m_axi_awprot(11 downto 0),
m_axi_awqos(15 downto 0) => m_axi_awqos(15 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awregion(15 downto 0) => m_axi_awregion(15 downto 0),
m_axi_awsize(11 downto 0) => m_axi_awsize(11 downto 0),
m_axi_awuser(3 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => m_axi_bid(47 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_buser(3 downto 0) => B"0000",
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => m_axi_rid(47 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rready(3 downto 0) => m_axi_rready(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_ruser(3 downto 0) => B"0000",
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(47 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(47 downto 0),
m_axi_wlast(3 downto 0) => m_axi_wlast(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(3 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
| mit | 8ee5c2597649e0584c7d057fa0de9583 | 0.554332 | 2.62716 | false | false | false | false |
JimLewis/OSVVM | RandomPkg.vhd | 1 | 67,648 | --
-- File Name : RandomPkg.vhd
-- Design Unit Name : RandomPkg
-- Revision : STANDARD VERSION
--
-- Maintainer : Jim Lewis email : [email protected]
-- Contributor(s) :
-- Jim Lewis email: [email protected]
-- Lars Asplund email: [email protected] - RandBool, RandSl, RandBit, DistBool, DistSl, DistBit
-- *
--
-- * In writing procedures normal, poisson, the following sources were referenced :
-- Wikipedia
-- package rnd2 written by John Breen and Ken Christensen
-- package RNG written by Gnanasekaran Swaminathan
--
--
-- Description :
-- RandomPType, a protected type, defined to hold randomization RandomSeeds and
-- function methods to facilitate randomization with uniform and weighted
-- distributions
--
-- Developed for :
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http ://www.SynthWorks.com
--
-- Revision History :
-- Date Version Description
-- 12/2006 : 0.1 Initial revision
-- Numerous revisions for SynthWorks' Advanced VHDL Testbenches and Verification
-- 02/2009 : 1.0 First Public Released Version
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference to
-- ieee_proposed.standard_additions.all ;
-- 06/2010 1.2 Added Normal and Poisson distributions
-- 03/2011 2.0 Major clean-up. Moved RandomParmType and control to here
-- 07/2011 2.1 Bug fix to convenience functions for slv, unsigned, and signed.
-- 06/2012 2.2 Removed '_' in the name of subprograms FavorBig and FavorSmall
-- 04/2013 2013.04 Changed DistInt. Return array indices now match input
-- Better Min, Max error handling in Uniform, FavorBig, FavorSmall, Normal, Poisson
-- 5/2013 - Removed extra variable declaration in functions RandInt and RandReal
-- 5/2013 2013.05 Big vector randomization added overloading RandUnsigned, RandSlv, and RandSigned
-- Added NULL_RANGE_TYPE to minimize null range warnings
-- 1/2014 2014.01 Added RandTime, RandReal(set), RandIntV, RandRealV, RandTimeV
-- Made sort, revsort from SortListPkg_int visible via aliases
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 5/2015 2015.06 Revised Alerts to Alert(OSVVM_ALERTLOG_ID, ...) ;
-- 11/2016 2016.11 No changes. Updated release numbers to make documentation and
-- package have consistent release identifiers.
-- 01/2020 2020.01 Updated Licenses to Apache
-- 08/2020 2020.08 RandBool, RandSl, RandBit, DistBool, DistSl, DistBit (from Lars)
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2020 by SynthWorks Design Inc.
-- Copyright (C) 2020 by OSVVM Authors
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use work.RandomBasePkg.all ;
use work.SortListPkg_int.all ;
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.numeric_std_unsigned.all ;
use ieee.math_real.all ;
-- comment out following 3 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
-- use ieee_proposed.standard_textio_additions.all ; -- remove with VHDL-2008
package RandomPkg is
-- Uncomment the following with VHDL-2008 package generics.
-- For now they are defined in the package RandomBasePkg.vhd
-- package RandomGenericPkg is
-- generic (
-- type RandomSeedType ; -- base type for randomization
-- procedure Uniform (Result : out real ; Seed : inout RandomSeedType) ;
-- function GenRandSeed(IV : integer_vector) return RandomSeedType ;
-- function GenRandSeed(I : integer) return RandomSeedType ;
-- function GenRandSeed(S : string) return RandomSeedType ;
-- ) ;
-- make things from SortListPkg_int visible
alias sort is work.SortListPkg_int.sort[integer_vector return integer_vector] ;
alias revsort is work.SortListPkg_int.revsort[integer_vector return integer_vector] ;
-- note NULL_RANGE_TYPE should probably be in std.standard
subtype NULL_RANGE_TYPE is integer range 0 downto 1 ;
constant NULL_INTV : integer_vector (NULL_RANGE_TYPE) := (others => 0) ;
-- Supports DistValInt functionality
type DistRecType is record
Value : integer ;
Weight : integer ;
end record ;
type DistType is array (natural range <>) of DistRecType ;
-- Weight vectors not indexed by integers
type NaturalVBoolType is array (boolean range <>) of natural;
type NaturalVSlType is array (std_logic range <>) of natural;
type NaturalVBitType is array (bit range <>) of natural;
-- Parameters for randomization
-- RandomDistType specifies the distribution to use for randomize
type RandomDistType is (NONE, UNIFORM, FAVOR_SMALL, FAVOR_BIG, NORMAL, POISSON) ;
type RandomParmType is record
Distribution : RandomDistType ;
Mean : Real ; -- also used as probability of success
StdDeviation : Real ; -- also used as number of trials for binomial
end record ;
-- RandomParm IO
function to_string(A : RandomDistType) return string ;
procedure write(variable L : inout line ; A : RandomDistType ) ;
procedure read(variable L : inout line ; A : out RandomDistType ; good : out boolean ) ;
procedure read(variable L : inout line ; A : out RandomDistType ) ;
function to_string(A : RandomParmType) return string ;
procedure write(variable L : inout line ; A : RandomParmType ) ;
procedure read(variable L : inout line ; A : out RandomParmType ; good : out boolean ) ;
procedure read(variable L : inout line ; A : out RandomParmType ) ;
type RandomPType is protected
-- Seed Manipulation
-- Known ambiguity between InitSeed with string and integer_vector
-- Recommendation, use : RV.InitSeed(RV'instance_path) ;
-- For integer_vector use either : RV.InitSeed(IV => (1,5)) ;
-- or : RV.InitSeed(integer_vector'(1,5)) ;
procedure InitSeed (S : string ) ;
procedure InitSeed (I : integer ) ;
procedure InitSeed (IV : integer_vector ) ;
-- SetSeed & GetSeed : Used to save and restore seed values
procedure SetSeed (RandomSeedIn : RandomSeedType ) ;
impure function GetSeed return RandomSeedType ;
-- SeedRandom = SetSeed & GetSeed for SV compatibility
-- replace with aliases when they work in popular simulators
procedure SeedRandom (RandomSeedIn : RandomSeedType ) ;
impure function SeedRandom return RandomSeedType ;
-- alias SeedRandom is SetSeed [RandomSeedType] ;
-- alias SeedRandom is GetSeed [return RandomSeedType] ;
-- Setting Randomization Parameters
-- Allows RandInt to have distributions other than uniform
procedure SetRandomParm (RandomParmIn : RandomParmType) ;
procedure SetRandomParm (
Distribution : RandomDistType ;
Mean : Real := 0.0 ;
Deviation : Real := 0.0
) ;
impure function GetRandomParm return RandomParmType ;
impure function GetRandomParm return RandomDistType ;
-- For compatibility with previous version - replace with alias
procedure SetRandomMode (RandomDistIn : RandomDistType) ;
-- alias SetRandomMode is SetRandomParm [RandomDistType, Real, Real] ;
-- Base Randomization Distributions
-- Uniform : Generate a random number with a Uniform distribution
impure function Uniform (Min, Max : in real) return real ;
impure function Uniform (Min, Max : integer) return integer ;
impure function Uniform (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- FavorSmall
-- Generate random numbers with a greater number of small
-- values than large values
impure function FavorSmall (Min, Max : real) return real ;
impure function FavorSmall (Min, Max : integer) return integer ;
impure function FavorSmall (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- FavorBig
-- Generate random numbers with a greater number of large
-- values than small values
impure function FavorBig (Min, Max : real) return real ;
impure function FavorBig (Min, Max : integer) return integer ;
impure function FavorBig (Min, Max : integer ; Exclude : integer_vector) return integer ;
-- Normal : Generate a random number with a normal distribution
impure function Normal (Mean, StdDeviation : real) return real ;
-- Normal + RandomVal >= Min and RandomVal < Max
impure function Normal (Mean, StdDeviation, Min, Max : real) return real ;
impure function Normal (
Mean : real ;
StdDeviation : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer ;
-- Poisson : Generate a random number with a poisson distribution
-- Discrete distribution = only generates integral values
impure function Poisson (Mean : real) return real ;
-- Poisson + RandomVal >= Min and RandomVal < Max
impure function Poisson (Mean, Min, Max : real) return real ;
impure function Poisson (
Mean : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer ;
-- randomization with a range
impure function RandInt (Min, Max : integer) return integer ;
impure function RandReal(Min, Max : Real) return real ;
impure function RandTime (Min, Max : time ; Unit : time := ns) return time ;
impure function RandSlv (Min, Max, Size : natural) return std_logic_vector ;
impure function RandUnsigned (Min, Max, Size : natural) return Unsigned ;
impure function RandSigned (Min, Max : integer ; Size : natural ) return Signed ;
impure function RandIntV (Min, Max : integer ; Size : natural) return integer_vector ;
impure function RandIntV (Min, Max : integer ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (Min, Max : real ; Size : natural) return real_vector ;
impure function RandTimeV (Min, Max : time ; Size : natural ; Unit : time := ns) return time_vector ;
impure function RandTimeV (Min, Max : time ; Unique : natural ; Size : natural ; Unit : time := ns) return time_vector ;
-- randomization with a range and exclude vector
impure function RandInt (Min, Max : integer ; Exclude : integer_vector ) return integer ;
impure function RandTime (Min, Max : time ; Exclude : time_vector ; Unit : time := ns) return time ;
impure function RandSlv (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return std_logic_vector ;
impure function RandUnsigned (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return Unsigned ;
impure function RandSigned (Min, Max : integer ; Exclude : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Size : natural ; Unit : in time := ns) return time_vector ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Unique : natural ; Size : natural ; Unit : in time := ns) return time_vector ;
-- Randomly select a value within a set of values
impure function RandInt ( A : integer_vector ) return integer ;
impure function RandReal ( A : real_vector ) return real ;
impure function RandTime (A : time_vector) return time ;
impure function RandSlv (A : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (A : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (A : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (A : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (A : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (A : real_vector ; Size : natural) return real_vector ;
impure function RandRealV (A : real_vector ; Unique : natural ; Size : natural) return real_vector ;
impure function RandTimeV (A : time_vector ; Size : natural) return time_vector ;
impure function RandTimeV (A : time_vector ; Unique : natural ; Size : natural) return time_vector ;
-- Randomly select a value within a set of values with exclude values (so can skip last or last n)
impure function RandInt ( A, Exclude : integer_vector ) return integer ;
impure function RandReal ( A, Exclude : real_vector ) return real ;
impure function RandTime (A, Exclude : time_vector) return time ;
impure function RandSlv (A, Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (A, Exclude : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (A, Exclude : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (A, Exclude : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (A, Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (A, Exclude : real_vector ; Size : natural) return real_vector ;
impure function RandRealV (A, Exclude : real_vector ; Unique : natural ; Size : natural) return real_vector ;
impure function RandTimeV (A, Exclude : time_vector ; Size : natural) return time_vector ;
impure function RandTimeV (A, Exclude : time_vector ; Unique : natural ; Size : natural) return time_vector ;
-- Randomly select between 0 and N-1 based on the specified weight.
-- where N = number values in weight array
impure function DistInt ( Weight : integer_vector ) return integer ;
impure function DistSlv ( Weight : integer_vector ; Size : natural ) return std_logic_vector ;
impure function DistUnsigned ( Weight : integer_vector ; Size : natural ) return unsigned ;
impure function DistSigned ( Weight : integer_vector ; Size : natural ) return signed ;
impure function DistBool ( Weight : NaturalVBoolType ) return boolean ;
impure function DistSl ( Weight : NaturalVSlType ) return std_logic ;
impure function DistBit ( Weight : NaturalVBitType ) return bit ;
-- Distribution with just weights and with exclude values
impure function DistInt ( Weight : integer_vector ; Exclude : integer_vector ) return integer ;
impure function DistSlv ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return std_logic_vector ;
impure function DistUnsigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return unsigned ;
impure function DistSigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return signed ;
-- Distribution with weight and value
impure function DistValInt ( A : DistType ) return integer ;
impure function DistValSlv ( A : DistType ; Size : natural) return std_logic_vector ;
impure function DistValUnsigned ( A : DistType ; Size : natural) return unsigned ;
impure function DistValSigned ( A : DistType ; Size : natural) return signed ;
-- Distribution with weight and value and with exclude values
impure function DistValInt ( A : DistType ; Exclude : integer_vector ) return integer ;
impure function DistValSlv ( A : DistType ; Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function DistValUnsigned ( A : DistType ; Exclude : integer_vector ; Size : natural) return unsigned ;
impure function DistValSigned ( A : DistType ; Exclude : integer_vector ; Size : natural) return signed ;
-- Large vector handling.
impure function RandUnsigned (Size : natural) return unsigned ;
impure function RandSlv (Size : natural) return std_logic_vector ;
impure function RandSigned (Size : natural) return signed ;
impure function RandUnsigned (Max : Unsigned) return unsigned ;
impure function RandSlv (Max : std_logic_vector) return std_logic_vector ;
impure function RandSigned (Max : signed) return signed ;
impure function RandUnsigned (Min, Max : unsigned) return unsigned ;
impure function RandSlv (Min, Max : std_logic_vector) return std_logic_vector ;
impure function RandSigned (Min, Max : signed) return signed ;
-- Convenience Functions
impure function RandReal return real ; -- 0.0 to 1.0
impure function RandReal(Max : Real) return real ; -- 0.0 to Max
impure function RandInt (Max : integer) return integer ;
impure function RandSlv (Max, Size : natural) return std_logic_vector ;
impure function RandUnsigned (Max, Size : natural) return Unsigned ;
impure function RandSigned (Max : integer ; Size : natural ) return Signed ;
impure function RandBool return boolean;
impure function RandSl return std_logic;
impure function RandBit return bit;
end protected RandomPType ;
end RandomPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body RandomPkg is
-----------------------------------------------------------------
-- Local Randomization Support
-----------------------------------------------------------------
constant NULL_SLV : std_logic_vector (NULL_RANGE_TYPE) := (others => '0') ;
constant NULL_UV : unsigned (NULL_RANGE_TYPE) := (others => '0') ;
constant NULL_SV : signed (NULL_RANGE_TYPE) := (others => '0') ;
-----------------------------------------------------------------
-- Scale -- Scale a value to be within a given range
--
function Scale (A, Min, Max : real) return real is
variable ValRange : Real ;
begin
if Max >= Min then
ValRange := Max - Min ;
return A * ValRange + Min ;
else
return real'left ;
end if ;
end function Scale ;
function Scale (A : real ; Min, Max : integer) return integer is
variable ValRange : real ;
variable rMin, rMax : real ;
begin
if Max >= Min then
rMin := real(Min) - 0.5 ;
rMax := real(Max) + 0.5 ;
ValRange := rMax - rMin ;
return integer(round(A * ValRange + rMin)) ;
else
return integer'left ;
end if ;
end function Scale ;
-- create more smaller values
function FavorSmall (A : real) return real is
begin
return 1.0 - sqrt(A) ;
end FavorSmall ;
-- create more larger values
-- alias FavorBig is sqrt[real return real] ;
function FavorBig (A : real) return real is
begin
return sqrt(A) ;
end FavorBig ;
-- local.
function to_time_vector (A : integer_vector ; Unit : time) return time_vector is
variable result : time_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) * Unit ;
end loop ;
return result ;
end function to_time_vector ;
-- local
function to_integer_vector (A : time_vector ; Unit : time) return integer_vector is
variable result : integer_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) / Unit ;
end loop ;
return result ;
end function to_integer_vector ;
-- Local. Remove the exclude list from the list - integer_vector
procedure RemoveExclude(A, Exclude : integer_vector ; variable NewA : out integer_vector ; variable NewALength : inout natural ) is
alias norm_NewA : integer_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-- Local. Inside - real_vector
function inside(A : real ; Exclude : real_vector) return boolean is
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-- Local. Remove the exclude list from the list - real_vector
procedure RemoveExclude(A, Exclude : real_vector ; variable NewA : out real_vector ; variable NewALength : inout natural ) is
alias norm_NewA : real_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-- Local. Inside - time_vector
function inside(A : time ; Exclude : time_vector) return boolean is
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-- Local. Remove the exclude list from the list - time_vector
procedure RemoveExclude(A, Exclude : time_vector ; variable NewA : out time_vector ; variable NewALength : inout natural ) is
alias norm_NewA : time_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-----------------------------------------------------------------
-- RandomParmType IO
-----------------------------------------------------------------
-----------------------------------------------------------------
function to_string(A : RandomDistType) return string is
begin
return RandomDistType'image(A) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomDistType ) is
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ; good : out boolean ) is
variable strval : string(1 to 40) ;
variable len : natural ;
begin
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A := RandomDistType'value(strval(1 to len)) ;
good := len > 0 ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ) is
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomDistType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
function to_string(A : RandomParmType) return string is
begin
return RandomDistType'image(A.Distribution) & " " &
to_string(A.Mean, 2) & " " & to_string(A.StdDeviation, 2) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomParmType ) is
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ; good : out boolean ) is
variable strval : string(1 to 40) ;
variable len : natural ;
variable igood : boolean ;
begin
loop
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A.Distribution := RandomDistType'value(strval(1 to len)) ;
igood := len > 0 ;
exit when not igood ;
read(L, A.Mean, igood) ;
exit when not igood ;
read(L, A.StdDeviation, igood) ;
exit ;
end loop ;
good := igood ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ) is
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomParmType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
-----------------------------------------------------------------
type RandomPType is protected body
--
-- RandomSeed manipulation
--
variable RandomSeed : RandomSeedType := GenRandSeed(integer_vector'(1,7)) ;
procedure InitSeed (S : string ) is
begin
RandomSeed := GenRandSeed(S) ;
end procedure InitSeed ;
procedure InitSeed (I : integer ) is
begin
RandomSeed := GenRandSeed(I) ;
end procedure InitSeed ;
procedure InitSeed (IV : integer_vector ) is
begin
RandomSeed := GenRandSeed(IV) ;
end procedure InitSeed ;
procedure SetSeed (RandomSeedIn : RandomSeedType ) is
begin
RandomSeed := RandomSeedIn ;
end procedure SetSeed ;
procedure SeedRandom (RandomSeedIn : RandomSeedType ) is
begin
RandomSeed := RandomSeedIn ;
end procedure SeedRandom ;
impure function GetSeed return RandomSeedType is
begin
return RandomSeed ;
end function GetSeed ;
impure function SeedRandom return RandomSeedType is
begin
return RandomSeed ;
end function SeedRandom ;
--
-- randomization mode
--
variable RandomParm : RandomParmType ; -- left most values ok for init
procedure SetRandomParm (RandomParmIn : RandomParmType) is
begin
RandomParm := RandomParmIn ;
end procedure SetRandomParm ;
procedure SetRandomParm (
Distribution : RandomDistType ;
Mean : Real := 0.0 ;
Deviation : Real := 0.0
) is
begin
RandomParm := RandomParmType'(Distribution, Mean, Deviation) ;
end procedure SetRandomParm ;
impure function GetRandomParm return RandomParmType is
begin
return RandomParm ;
end function GetRandomParm ;
impure function GetRandomParm return RandomDistType is
begin
return RandomParm.Distribution ;
end function GetRandomParm ;
-- For compatibility with previous version
procedure SetRandomMode (RandomDistIn : RandomDistType) is
begin
SetRandomParm(RandomDistIn) ;
end procedure SetRandomMode ;
--
-- Base Randomization Distributions
--
--
-- Uniform : Generate a random number with a Uniform distribution
--
impure function Uniform (Min, Max : in real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.Uniform: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(rRandomVal, Min, Max) ;
end function Uniform ;
impure function Uniform (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.Uniform: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(rRandomVal, Min, Max) ;
end function Uniform ;
impure function Uniform (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := Uniform(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function Uniform ;
--
-- FavorSmall
-- Generate random numbers with a greater number of small
-- values than large values
--
impure function FavorSmall (Min, Max : real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorSmall: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorSmall(rRandomVal), Min, Max) ; -- real
end function FavorSmall ;
impure function FavorSmall (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorSmall: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorSmall(rRandomVal), Min, Max) ; -- integer
end function FavorSmall ;
impure function FavorSmall (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := FavorSmall(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function FavorSmall ;
--
-- FavorBig
-- Generate random numbers with a greater number of large
-- values than small values
--
impure function FavorBig (Min, Max : real) return real is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorBig: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorBig(rRandomVal), Min, Max) ; -- real
end function FavorBig ;
impure function FavorBig (Min, Max : integer) return integer is
variable rRandomVal : real ;
begin
AlertIf (OSVVM_ALERTLOG_ID, Max < Min, "RandomPkg.FavorBig: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
return scale(FavorBig(rRandomVal), Min, Max) ; -- integer
end function FavorBig ;
impure function FavorBig (Min, Max : integer ; Exclude : integer_vector) return integer is
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := FavorBig(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function FavorBig ;
-----------------------------------------------------------------
-- Normal
-- Generate a random number with a normal distribution
--
-- Use Box Muller, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Box%E2%80%93Muller_transform
--
-- Use polar method, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Marsaglia_polar_method
--
impure function Normal (Mean, StdDeviation : real) return real is
variable x01, y01 : real ;
variable StdNormalDist : real ; -- mean 0, variance 1
begin
-- add this check to set parameters?
if StdDeviation < 0.0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Standard deviation must be >= 0.0", FAILURE) ;
return -1.0 ;
end if ;
-- Box Muller
Uniform (x01, RandomSeed) ;
Uniform (y01, RandomSeed) ;
StdNormalDist := sqrt(-2.0 * log(x01)) * cos(math_2_pi*y01) ;
-- Polar form rejected due to mean 50.0, std deviation = 5 resulted
-- in a median of 49
-- -- find two Uniform distributed values with range -1 to 1
-- -- that satisify S = X **2 + Y**2 < 1.0
-- loop
-- Uniform (x01, RandomSeed) ;
-- Uniform (y01, RandomSeed) ;
-- x := 2.0 * x01 - 1.0 ; -- scale to -1 to 1
-- y := 2.0 * y01 - 1.0 ;
-- s := x*x + y*y ;
-- exit when s < 1.0 and s > 0.0 ;
-- end loop ;
-- -- Calculate Standard Normal Distribution
-- StdNormalDist := x * sqrt((-2.0 * log(s)) / s) ;
-- Convert to have Mean and StdDeviation
return StdDeviation * StdNormalDist + Mean ;
end function Normal ;
-- Normal + RandomVal >= Min and RandomVal <= Max
impure function Normal (Mean, StdDeviation, Min, Max : real) return real is
variable rRandomVal : real ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Max < Min", FAILURE) ;
return Mean ;
else
loop
rRandomVal := Normal (Mean, StdDeviation) ;
exit when rRandomVal >= Min and rRandomVal <= Max ;
end loop ;
end if ;
return rRandomVal ;
end function Normal ;
-- Normal + RandomVal >= Min and RandomVal <= Max
impure function Normal (
Mean : real ;
StdDeviation : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer is
variable iRandomVal : integer ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Normal: Max < Min", FAILURE) ;
return integer(round(Mean)) ;
else
loop
iRandomVal := integer(round( Normal(Mean, StdDeviation) )) ;
exit when iRandomVal >= Min and iRandomVal <= Max and
not inside(iRandomVal, Exclude) ;
end loop ;
end if ;
return iRandomVal ;
end function Normal ;
-----------------------------------------------------------------
-- Poisson
-- Generate a random number with a poisson distribution
-- Discrete distribution = only generates integral values
--
-- Use knuth method, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Poisson_distribution
--
impure function Poisson (Mean : real) return real is
variable Product : Real := 1.0 ;
variable Bound : Real := 0.0 ;
variable UniformRand : Real := 0.0 ;
variable PoissonRand : Real := 0.0 ;
begin
Bound := exp(-1.0 * Mean) ;
Product := 1.0 ;
-- add this check to set parameters?
if Mean <= 0.0 or Bound <= 0.0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Mean < 0 or too large. Mean = " & real'image(Mean), FAILURE) ;
return Mean ;
end if ;
while (Product >= Bound) loop
PoissonRand := PoissonRand + 1.0 ;
Uniform(UniformRand, RandomSeed) ;
Product := Product * UniformRand ;
end loop ;
return PoissonRand ;
end function Poisson ; -- no range
-- Poisson + RandomVal >= Min and RandomVal < Max
impure function Poisson (Mean, Min, Max : real) return real is
variable rRandomVal : real ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Max < Min", FAILURE) ;
return Mean ;
else
loop
rRandomVal := Poisson (Mean) ;
exit when rRandomVal >= Min and rRandomVal <= Max ;
end loop ;
end if ;
return rRandomVal ;
end function Poisson ;
impure function Poisson (
Mean : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer is
variable iRandomVal : integer ;
begin
if Max < Min then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.Poisson: Max < Min", FAILURE) ;
return integer(round(Mean)) ;
else
loop
iRandomVal := integer(round( Poisson (Mean) )) ;
exit when iRandomVal >= Min and iRandomVal <= Max and
not inside(iRandomVal, Exclude) ;
end loop ;
end if ;
return iRandomVal ;
end function Poisson ;
--
-- integer randomization with a range
-- Distribution determined by RandomParm
--
impure function RandInt (Min, Max : integer) return integer is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max) ;
when FAVOR_SMALL => return FavorSmall(Min, Max) ;
when FAVOR_BIG => return FavorBig (Min, Max) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandInt: RandomParm.Distribution not implemented", FAILURE) ;
return integer'low ;
end case ;
end function RandInt ;
--
-- real randomization with a range
-- Distribution determined by RandomParm
--
impure function RandReal(Min, Max : Real) return real is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max) ;
when FAVOR_SMALL => return FavorSmall(Min, Max) ;
when FAVOR_BIG => return FavorBig (Min, Max) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandReal: Specified RandomParm.Distribution not implemented", FAILURE) ;
return real(integer'low) ;
end case ;
end function RandReal ;
impure function RandTime (Min, Max : time ; Unit :time := ns) return time is
variable IntVal : integer ;
begin
-- if Max - Min > 2**31 result will be out of range
IntVal := RandInt(0, (Max - Min)/Unit) ;
Return Min + Unit*IntVal ;
end function RandTime ;
impure function RandSlv (Min, Max, Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(Min, Max), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Min, Max, Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(Min, Max), Size) ;
end function RandUnsigned ;
impure function RandSigned (Min, Max : integer ; Size : natural ) return Signed is
begin
return to_signed(RandInt(Min, Max), Size) ;
end function RandSigned ;
impure function RandIntV (Min, Max : integer ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(Min, Max) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (Min, Max : integer ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
iUnique := Unique ;
if Max-Min+1 < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.(RandIntV | RandRealV | RandTimeV): Unique > number of values available", FAILURE) ;
iUnique := Max-Min+1 ;
end if ;
for i in result'range loop
result(i) := RandInt(Min, Max, result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (Min, Max : real ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandReal(Min, Max) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (Min, Max : time ; Size : natural ; Unit : time := ns) return time_vector is
variable result : time_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandTime(Min, Max, Unit) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (Min, Max : time ; Unique : natural ; Size : natural ; Unit : time := ns) return time_vector is
begin
-- if Unique = 0, it is more efficient to call RandTimeV(Min, Max, Size)
return to_time_vector(RandIntV(Min/Unit, Max/Unit, Unique, Size), Unit) ;
end function RandTimeV ;
--
-- integer randomization with a range and exclude vector
-- Distribution determined by RandomParm
--
impure function RandInt (Min, Max : integer ; Exclude : integer_vector ) return integer is
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return Uniform(Min, Max, Exclude) ;
when FAVOR_SMALL => return FavorSmall(Min, Max, Exclude) ;
when FAVOR_BIG => return FavorBig (Min, Max, Exclude) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max, Exclude) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max, Exclude) ;
when others =>
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandInt: Specified RandomParm.Distribution not implemented", FAILURE) ;
return integer'low ;
end case ;
end function RandInt ;
impure function RandTime (Min, Max : time ; Exclude : time_vector ; Unit : time := ns) return time is
variable IntVal : integer ;
begin
-- if Min or Max > 2**31 value will be out of range
return RandInt(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit)) * Unit ;
end function RandTime ;
impure function RandSlv (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(Min, Max, Exclude), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return Unsigned is
begin
return to_unsigned(RandInt(Min, Max, Exclude), Size) ;
end function RandUnsigned ;
impure function RandSigned (Min, Max : integer ; Exclude : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(Min, Max, Exclude), Size) ;
end function RandSigned ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(Min, Max, Exclude) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable ResultPlus : integer_vector(1 to Size + Exclude'length) ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
ResultPlus(Size+1 to ResultPlus'right) := Exclude ;
for i in 1 to Size loop
ResultPlus(i) := RandInt(Min, Max, ResultPlus(maximum(1, 1 + i - Unique) to ResultPlus'right)) ;
end loop ;
return ResultPlus(1 to Size) ;
end function RandIntV ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Size : natural ; Unit : in time := ns) return time_vector is
begin
return to_time_vector( RandIntV(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit), Size), Unit ) ;
end function RandTimeV ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Unique : natural ; Size : natural ; Unit : in time := ns) return time_vector is
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
return to_time_vector( RandIntV(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit), Unique, Size), Unit ) ;
end function RandTimeV ;
--
-- Randomly select a value within a set of values
-- Distribution determined by RandomParm
--
impure function RandInt ( A : integer_vector ) return integer is
alias A_norm : integer_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandInt ;
impure function RandReal ( A : real_vector ) return real is
alias A_norm : real_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandReal ;
impure function RandTime ( A : time_vector ) return time is
alias A_norm : time_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandTime ;
impure function RandSlv (A : integer_vector ; Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(A), Size)) ;
end function RandSlv ;
impure function RandUnsigned (A : integer_vector ; Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(A), Size) ;
end function RandUnsigned ;
impure function RandSigned (A : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(A), Size) ;
end function RandSigned ;
impure function RandIntV (A : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(A) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (A : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(A, Size)
-- require A'length >= Unique
iUnique := Unique ;
if A'length < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandIntV: Unique > length of set of values", FAILURE) ;
iUnique := A'length ;
end if ;
for i in result'range loop
result(i) := RandInt(A, result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (A : real_vector ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandReal(A) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandRealV (A : real_vector ; Unique : natural ; Size : natural) return real_vector is
alias A_norm : real_vector(1 to A'length) is A ;
variable result : real_vector(1 to Size) ;
variable IntResult : integer_vector(result'range) ;
begin
-- randomly generate indices
IntResult := RandIntV(1, A'length, Unique, Size) ;
-- translate indicies into result values
for i in result'range loop
result(i) := A_norm(IntResult(i)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (A : time_vector ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandTime(A) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (A : time_vector ; Unique : natural ; Size : natural) return time_vector is
alias A_norm : time_vector(1 to A'length) is A ;
variable result : time_vector(1 to Size) ;
variable IntResult : integer_vector(result'range) ;
begin
-- randomly generate indices
IntResult := RandIntV(1, A'length, Unique, Size) ;
-- translate indicies into result values
for i in result'range loop
result(i) := A_norm(IntResult(i)) ;
end loop ;
return result ;
end function RandTimeV ;
--
-- Randomly select a value within a set of values with exclude values (so can skip last or last n)
-- Distribution determined by RandomParm
--
impure function RandInt ( A, Exclude : integer_vector ) return integer is
variable NewA : integer_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandInt ;
impure function RandReal ( A, Exclude : real_vector ) return real is
variable NewA : real_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandReal ;
impure function RandTime ( A, Exclude : time_vector ) return time is
variable NewA : time_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandTime ;
impure function RandSlv (A, Exclude : integer_vector ; Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(A, Exclude), Size)) ;
end function RandSlv ;
impure function RandUnsigned (A, Exclude : integer_vector ; Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(A, Exclude), Size) ;
end function RandUnsigned ;
impure function RandSigned (A, Exclude : integer_vector ; Size : natural ) return Signed is
begin
return to_signed(RandInt(A, Exclude), Size) ;
end function RandSigned ;
impure function RandIntV (A, Exclude : integer_vector ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable NewA : integer_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandIntV (A, Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
variable result : integer_vector(1 to Size) ;
variable NewA : integer_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandIntV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandInt(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
impure function RandRealV (A, Exclude : real_vector ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
variable NewA : real_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandRealV (A, Exclude : real_vector ; Unique : natural ; Size : natural) return real_vector is
variable result : real_vector(1 to Size) ;
variable NewA : real_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandRealV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandRealV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandReal(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandRealV ;
impure function RandTimeV (A, Exclude : time_vector ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
variable NewA : time_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandTimeV ;
impure function RandTimeV (A, Exclude : time_vector ; Unique : natural ; Size : natural) return time_vector is
variable result : time_vector(1 to Size) ;
variable NewA : time_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandRealV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandTimeV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandTime(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandTimeV ;
--
-- Basic Discrete Distributions
-- Always uses Uniform
--
impure function DistInt ( Weight : integer_vector ) return integer is
variable DistArray : integer_vector(weight'range) ;
variable sum : integer ;
variable iRandomVal : integer ;
begin
DistArray := Weight ;
sum := 0 ;
for i in DistArray'range loop
DistArray(i) := DistArray(i) + sum ;
if DistArray(i) < sum then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: negative weight or sum > 31 bits", FAILURE) ;
return DistArray'low ; -- allows debugging vs integer'left, out of range
end if ;
sum := DistArray(i) ;
end loop ;
if sum >= 1 then
iRandomVal := Uniform(1, sum) ;
for i in DistArray'range loop
if iRandomVal <= DistArray(i) then
return i ;
end if ;
end loop ;
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: randomization failed", FAILURE) ;
else
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.DistInt: No randomization weights", FAILURE) ;
end if ;
return DistArray'low ; -- allows debugging vs integer'left, out of range
end function DistInt ;
impure function DistSlv ( Weight : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistInt(Weight), Size)) ;
end function DistSlv ;
impure function DistUnsigned ( Weight : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistInt(Weight), Size) ;
end function DistUnsigned ;
impure function DistSigned ( Weight : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistInt(Weight), Size) ;
end function DistSigned ;
impure function DistBool ( Weight : NaturalVBoolType ) return boolean is
-- variable FullWeight : NaturalVBoolType(false to true) := (0, 0);
variable FullWeight : integer_vector(0 to 1) := (0, 0);
begin
for i in Weight'range loop
FullWeight(boolean'pos(i)) := Weight(i) ;
end loop ;
return boolean'val(DistInt(FullWeight)) ;
-- FullWeight(Weight'range) := Weight;
-- return DistInt(integer_vector(FullWeight)) = 1 ;
end function DistBool ;
impure function DistSl ( Weight : NaturalVSlType ) return std_logic is
-- variable FullWeight : NaturalVSlType('U' to '-') := (others => 0);
variable FullWeight : integer_vector(0 to 8) := (others => 0);
begin
for i in Weight'range loop
FullWeight(std_logic'pos(i)) := Weight(i) ;
end loop ;
return std_logic'val(DistInt(FullWeight)) ;
-- FullWeight(Weight'range) := Weight;
-- return std_logic'val(DistInt(integer_vector(FullWeight))) ;
end function DistSl ;
impure function DistBit ( Weight : NaturalVBitType ) return bit is
-- variable FullWeight : NaturalVBitType('0' to '1') := (0, 0);
variable FullWeight : integer_vector(0 to 1) := (others => 0);
begin
for i in Weight'range loop
FullWeight(bit'pos(i)) := Weight(i) ;
end loop ;
return bit'val(DistInt(FullWeight)) ;
-- FullWeight(Weight'range) := Weight;
-- return bit'val(DistInt(integer_vector(FullWeight))) ;
end function DistBit ;
--
-- Basic Distributions with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
impure function DistInt ( Weight : integer_vector ; Exclude : integer_vector ) return integer is
variable DistArray : integer_vector(weight'range) ;
variable ExcludeTemp : integer ;
begin
DistArray := Weight ;
for i in Exclude'range loop
ExcludeTemp := Exclude(i) ;
if ExcludeTemp >= DistArray'low and ExcludeTemp <= DistArray'high then
DistArray(ExcludeTemp) := 0 ;
end if ;
end loop ;
return DistInt(DistArray) ;
end function DistInt ;
impure function DistSlv ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistInt(Weight, Exclude), Size)) ;
end function DistSlv ;
impure function DistUnsigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistInt(Weight, Exclude), Size) ;
end function DistUnsigned ;
impure function DistSigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistInt(Weight, Exclude), Size) ;
end function DistSigned ;
--
-- Distribution for sparse values
-- Always uses Uniform via DistInt
--
impure function DistValInt ( A : DistType ) return integer is
variable DistArray : integer_vector(0 to A'length -1) ;
alias DistRecArray : DistType(DistArray'range) is A ;
begin
for i in DistArray'range loop
DistArray(i) := DistRecArray(i).Weight ;
end loop ;
return DistRecArray(DistInt(DistArray)).Value ;
end function DistValInt ;
impure function DistValSlv ( A : DistType ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistValInt(A), Size)) ;
end function DistValSlv ;
impure function DistValUnsigned ( A : DistType ; Size : natural ) return unsigned is
begin
return to_unsigned(DistValInt(A), Size) ;
end function DistValUnsigned ;
impure function DistValSigned ( A : DistType ; Size : natural ) return signed is
begin
return to_signed(DistValInt(A), Size) ;
end function DistValSigned ;
--
-- Distribution for sparse values with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
impure function DistValInt ( A : DistType ; Exclude : integer_vector ) return integer is
variable DistArray : integer_vector(0 to A'length -1) ;
alias DistRecArray : DistType(DistArray'range) is A ;
begin
for i in DistRecArray'range loop
if inside(DistRecArray(i).Value, exclude) then
DistArray(i) := 0 ; -- exclude
else
DistArray(i) := DistRecArray(i).Weight ;
end if ;
end loop ;
return DistRecArray(DistInt(DistArray)).Value ;
end function DistValInt ;
impure function DistValSlv ( A : DistType ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(DistValInt(A, Exclude), Size)) ;
end function DistValSlv ;
impure function DistValUnsigned ( A : DistType ; Exclude : integer_vector ; Size : natural ) return unsigned is
begin
return to_unsigned(DistValInt(A, Exclude), Size) ;
end function DistValUnsigned ;
impure function DistValSigned ( A : DistType ; Exclude : integer_vector ; Size : natural ) return signed is
begin
return to_signed(DistValInt(A, Exclude), Size) ;
end function DistValSigned ;
--
-- Large vector handling.
--
impure function RandUnsigned (Size : natural) return unsigned is
constant NumLoops : integer := integer(ceil(real(Size)/30.0)) ;
constant Remain : integer := (Size - 1) mod 30 + 1 ; -- range 1 to 30
variable RandVal : unsigned(1 to Size) ;
begin
if size = 0 then
return NULL_UV ; -- Null array
end if ;
for i in 0 to NumLoops-2 loop
RandVal(1 + 30*i to 30 + 30*i) := to_unsigned(RandInt(0, 2**30-1), 30) ;
end loop ;
RandVal(1+30*(NumLoops-1) to Remain + 30*(NumLoops-1)) := to_unsigned(RandInt(0, 2**Remain-1), Remain) ;
return RandVal ;
end function RandUnsigned ;
impure function RandSlv (Size : natural) return std_logic_vector is
begin
return std_logic_vector(RandUnsigned(Size)) ;
end function RandSlv ;
impure function RandSigned (Size : natural) return signed is
begin
return signed(RandUnsigned(Size)) ;
end function RandSigned ;
impure function RandUnsigned (Max : unsigned) return unsigned is
alias normMax : unsigned (Max'length downto 1) is Max ;
variable Result : unsigned(Max'range) := (others => '0') ;
alias normResult : unsigned(normMax'range) is Result ;
variable Size : integer ;
begin
-- Size = -1 if not found or Max'length = 0
Size := find_leftmost(normMax, '1') ;
if Size > 0 then
loop
normResult(Size downto 1) := RandUnsigned(Size) ;
exit when normResult <= Max ;
end loop ;
return Result ; -- = normResult with range same as Max
else
return resize("0", Max'length) ;
end if ;
end function RandUnsigned ;
-- Working version that scales the value
-- impure function RandUnsigned (Max : unsigned) return unsigned is
-- constant MaxVal : unsigned(Max'length+3 downto 1) := (others => '1') ;
-- begin
-- if max'length > 0 then
-- -- "Max'length+3" creates 3 guard bits
-- return resize( RandUnsigned(Max'length+3) * ('0'&Max+1) / ('0'&MaxVal+1), Max'length) ;
-- else
-- return NULL_UV ; -- Null Array
-- end if ;
-- end function RandUnsigned ;
impure function RandSlv (Max : std_logic_vector) return std_logic_vector is
begin
return std_logic_vector(RandUnsigned( unsigned(Max))) ;
end function RandSlv ;
impure function RandSigned (Max : signed) return signed is
begin
if max'length > 0 then
AlertIf (OSVVM_ALERTLOG_ID, Max < 0, "RandomPkg.RandSigned: Max < 0", FAILURE) ;
return signed(RandUnsigned( unsigned(Max))) ;
else
return NULL_SV ; -- Null Array
end if ;
end function RandSigned ;
impure function RandUnsigned (Min, Max : unsigned) return unsigned is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return RandUnsigned(Max-Min) + Min ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandUnsigned: Max < Min", FAILURE) ;
end if ;
return NULL_UV ;
end if ;
end function RandUnsigned ;
impure function RandSlv (Min, Max : std_logic_vector) return std_logic_vector is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return RandSlv(Max-Min) + Min ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandSlv: Max < Min", FAILURE) ;
end if ;
return NULL_SlV ;
end if ;
end function RandSlv ;
impure function RandSigned (Min, Max : signed) return signed is
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return resize(RandSigned(resize(Max,LEN+1) - resize(Min,LEN+1)) + Min, LEN) ;
else
if Len > 0 then
Alert(OSVVM_ALERTLOG_ID, "RandomPkg.RandSigned: Max < Min", FAILURE) ;
end if ;
return NULL_SV ;
end if ;
end function RandSigned ;
--
-- Convenience Functions. Resolve into calls into the other functions
--
impure function RandReal return real is
begin
return RandReal(0.0, 1.0) ;
end function RandReal ;
impure function RandReal(Max : Real) return real is -- 0.0 to Max
begin
return RandReal(0.0, Max) ;
end function RandReal ;
impure function RandInt (Max : integer) return integer is
begin
return RandInt(0, Max) ;
end function RandInt ;
impure function RandSlv (Max, Size : natural) return std_logic_vector is
begin
return std_logic_vector(to_unsigned(RandInt(0, Max), Size)) ;
end function RandSlv ;
impure function RandUnsigned (Max, Size : natural) return Unsigned is
begin
return to_unsigned(RandInt(0, Max), Size) ;
end function RandUnsigned ;
impure function RandSigned (Max : integer ; Size : natural ) return Signed is
begin
-- chose 0 to Max rather than -Max to +Max to be same as RandUnsigned, either seems logical
return to_signed(RandInt(0, Max), Size) ;
end function RandSigned ;
impure function RandBool return boolean is
begin
return RandInt(1) = 1;
end function RandBool ;
impure function RandSl return std_logic is
begin
return std_logic'val(RandInt(8));
end function RandSl ;
impure function RandBit return bit is
begin
return bit'val(RandInt(1));
end function RandBit ;
end protected body RandomPType ;
end RandomPkg ;
| artistic-2.0 | 5ed54fbed24608549591a6dd5e063d08 | 0.634165 | 4.00284 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_0/zynq_design_1_rst_ps7_0_100M_0_sim_netlist.vhdl | 1 | 32,867 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:38:22 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_rst_ps7_0_100M_0/zynq_design_1_rst_ps7_0_100M_0_sim_netlist.vhdl
-- Design : zynq_design_1_rst_ps7_0_100M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_rst_ps7_0_100M_0_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
aux_reset_in : in STD_LOGIC;
lpf_asr : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_rst_ps7_0_100M_0_cdc_sync : entity is "cdc_sync";
end zynq_design_1_rst_ps7_0_100M_0_cdc_sync;
architecture STRUCTURE of zynq_design_1_rst_ps7_0_100M_0_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => asr_lpf(0),
I2 => \^scndry_out\,
I3 => p_1_in,
I4 => p_2_in,
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_rst_ps7_0_100M_0_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_rst_ps7_0_100M_0_cdc_sync_0 : entity is "cdc_sync";
end zynq_design_1_rst_ps7_0_100M_0_cdc_sync_0;
architecture STRUCTURE of zynq_design_1_rst_ps7_0_100M_0_cdc_sync_0 is
signal \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\ : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0\
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(0),
I2 => \^scndry_out\,
I3 => p_3_out(1),
I4 => p_3_out(2),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_rst_ps7_0_100M_0_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_rst_ps7_0_100M_0_upcnt_n : entity is "upcnt_n";
end zynq_design_1_rst_ps7_0_100M_0_upcnt_n;
architecture STRUCTURE of zynq_design_1_rst_ps7_0_100M_0_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_rst_ps7_0_100M_0_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_rst_ps7_0_100M_0_lpf : entity is "lpf";
end zynq_design_1_rst_ps7_0_100M_0_lpf;
architecture STRUCTURE of zynq_design_1_rst_ps7_0_100M_0_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.zynq_design_1_rst_ps7_0_100M_0_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.zynq_design_1_rst_ps7_0_100M_0_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFEF"
)
port map (
I0 => Q,
I1 => lpf_asr,
I2 => dcm_locked,
I3 => lpf_exr,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_rst_ps7_0_100M_0_sequence_psr is
port (
Core : out STD_LOGIC;
bsr : out STD_LOGIC;
pr : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_rst_ps7_0_100M_0_sequence_psr : entity is "sequence_psr";
end zynq_design_1_rst_ps7_0_100M_0_sequence_psr;
architecture STRUCTURE of zynq_design_1_rst_ps7_0_100M_0_sequence_psr is
signal \^core\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^bsr\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^pr\ : STD_LOGIC;
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Core <= \^core\;
bsr <= \^bsr\;
pr <= \^pr\;
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^core\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^core\,
S => lpf_int
);
SEQ_COUNTER: entity work.zynq_design_1_rst_ps7_0_100M_0_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0804"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8040"
)
port map (
I0 => seq_cnt(4),
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt_en,
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^core\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0210"
)
port map (
I0 => seq_cnt(0),
I1 => seq_cnt(1),
I2 => seq_cnt(2),
I3 => seq_cnt_en,
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"1080"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(5),
I2 => seq_cnt(3),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset : entity is 1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset : entity is "proc_sys_reset";
end zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset;
architecture STRUCTURE of zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset is
signal Core : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal bsr : STD_LOGIC;
signal lpf_int : STD_LOGIC;
signal pr : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ : label is "no";
attribute equivalent_register_removal of \BSR_OUT_DFF[0].bus_struct_reset_reg[0]\ : label is "no";
attribute equivalent_register_removal of \PR_OUT_DFF[0].peripheral_reset_reg[0]\ : label is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].bus_struct_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.zynq_design_1_rst_ps7_0_100M_0_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
\PR_OUT_DFF[0].peripheral_reset_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.zynq_design_1_rst_ps7_0_100M_0_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].interconnect_aresetn_reg[0]\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].peripheral_aresetn_reg[0]\ => SEQ_n_4,
Core => Core,
bsr => bsr,
lpf_int => lpf_int,
pr => pr,
slowest_sync_clk => slowest_sync_clk
);
mb_reset_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core,
Q => mb_reset,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_rst_ps7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_rst_ps7_0_100M_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_rst_ps7_0_100M_0 : entity is "zynq_design_1_rst_ps7_0_100M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_rst_ps7_0_100M_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zynq_design_1_rst_ps7_0_100M_0 : entity is "proc_sys_reset,Vivado 2017.2";
end zynq_design_1_rst_ps7_0_100M_0;
architecture STRUCTURE of zynq_design_1_rst_ps7_0_100M_0 is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
begin
U0: entity work.zynq_design_1_rst_ps7_0_100M_0_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
| mit | 57339cb1d44a3318d33b4448ea27540f | 0.574771 | 2.81227 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ac701/testbench.vhd | 1 | 18,454 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
use work.config.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := true;
USE_MIG_INTERFACE_MODEL : boolean := false
);
end;
architecture behav of testbench is
-- DDR3 Simulation parameters
constant SIM_BYPASS_INIT_CAL : string := "FAST";
-- # = "OFF" - Complete memory init &
-- calibration sequence
-- # = "SKIP" - Not supported
-- # = "FAST" - Complete memory init & use
-- abbreviated calib sequence
constant SIMULATION : string := "TRUE";
-- Should be TRUE during design simulations and
-- FALSE during implementations
constant promfile : string := "prom.srec"; -- rom contents
constant ramfile : string := "ram.srec"; -- ram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0';
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal txd1 , rxd1 , dsurx : std_logic;
signal txd2 , rxd2 , dsutx : std_logic;
signal ctsn1 , rtsn1 , dsuctsn : std_ulogic;
signal ctsn2 , rtsn2 , dsurtsn : std_ulogic;
signal phy_gtxclk : std_logic := '0';
signal phy_txer : std_ulogic;
signal phy_txd : std_logic_vector(7 downto 0);
signal phy_txctl_txen : std_ulogic;
signal phy_txclk : std_ulogic;
signal phy_rxer : std_ulogic;
signal phy_rxd : std_logic_vector(7 downto 0);
signal phy_rxctl_rxdv : std_ulogic;
signal phy_rxclk : std_ulogic;
signal phy_reset : std_ulogic;
signal phy_mdio : std_logic;
signal phy_mdc : std_ulogic;
signal phy_crs : std_ulogic;
signal phy_col : std_ulogic;
signal phy_int : std_ulogic;
signal phy_rxdl : std_logic_vector(7 downto 0);
signal phy_txdl : std_logic_vector(7 downto 0);
signal clk27 : std_ulogic := '0';
signal clk200p : std_ulogic := '0';
signal clk200n : std_ulogic := '1';
signal clk33 : std_ulogic := '0';
signal clkethp : std_ulogic := '0';
signal clkethn : std_ulogic := '1';
signal txp1 : std_logic;
signal txn : std_logic;
signal rxp : std_logic := '1';
signal rxn : std_logic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR3 memory
signal ddr3_dq : std_logic_vector(63 downto 0);
signal ddr3_dqs_p : std_logic_vector(7 downto 0);
signal ddr3_dqs_n : std_logic_vector(7 downto 0);
signal ddr3_addr : std_logic_vector(13 downto 0);
signal ddr3_ba : std_logic_vector(2 downto 0);
signal ddr3_ras_n : std_logic;
signal ddr3_cas_n : std_logic;
signal ddr3_we_n : std_logic;
signal ddr3_reset_n : std_logic;
signal ddr3_ck_p : std_logic_vector(0 downto 0);
signal ddr3_ck_n : std_logic_vector(0 downto 0);
signal ddr3_cke : std_logic_vector(0 downto 0);
signal ddr3_cs_n : std_logic_vector(0 downto 0);
signal ddr3_dm : std_logic_vector(7 downto 0);
signal ddr3_odt : std_logic_vector(0 downto 0);
-- SPI flash
signal spi_sel_n : std_logic;
signal spi_clk : std_ulogic;
signal spi_miso : std_ulogic := '0';
signal spi_simo : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(3 downto 0); -- I/O port
signal button : std_logic_vector(3 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
constant lresp : boolean := false;
signal tdqs_n : std_logic;
signal gmii_tx_clk : std_logic;
signal gmii_rx_clk : std_logic;
signal gmii_txd : std_logic_vector(7 downto 0);
signal gmii_tx_en : std_logic;
signal gmii_tx_er : std_logic;
signal gmii_rxd : std_logic_vector(7 downto 0);
signal gmii_rx_dv : std_logic;
signal gmii_rx_er : std_logic;
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false;
SIM_BYPASS_INIT_CAL : string := "OFF";
SIMULATION : string := "FALSE";
USE_MIG_INTERFACE_MODEL : boolean := false
);
port (
reset : in std_ulogic;
clk200p : in std_ulogic; -- 200 MHz clock
clk200n : in std_ulogic; -- 200 MHz clock
-- spi_sel_n : inout std_ulogic;
-- spi_clk : out std_ulogic;
-- spi_miso : in std_ulogic;
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_ras_n : out std_logic;
ddr3_cas_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0);
dsurx : in std_ulogic;
dsutx : out std_ulogic;
dsuctsn : in std_ulogic;
dsurtsn : out std_ulogic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(3 downto 0);
led : out std_logic_vector(3 downto 0);
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
phy_txclk : out std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txctl_txen : out std_ulogic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxctl_rxdv : in std_ulogic;
phy_rxclk : in std_ulogic;
phy_reset : out std_ulogic;
phy_mdio : inout std_logic;
phy_mdc : out std_ulogic;
sfp_clock_mux : out std_logic_vector(1 downto 0)
);
end component;
begin
-- clock and reset
clk200p <= not clk200p after 2.5 ns;
clk200n <= not clk200n after 2.5 ns;
clkethp <= not clkethp after 4 ns;
clkethn <= not clkethp after 4 ns;
rst <= not dsurst;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
button <= "0000";
switch(2 downto 0) <= "000";
cpu : leon3mp
generic map (
fabtech => fabtech,
memtech => memtech,
padtech => padtech,
clktech => clktech,
disas => disas,
dbguart => dbguart,
pclow => pclow,
testahb => testahb,
SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
SIMULATION => SIMULATION,
USE_MIG_INTERFACE_MODEL => USE_MIG_INTERFACE_MODEL
)
port map (
reset => rst,
clk200p => clk200p,
clk200n => clk200n,
-- spi_sel_n => spi_sel_n,
-- spi_clk => spi_clk,
-- spi_miso => spi_miso,
ddr3_dq => ddr3_dq,
ddr3_dqs_p => ddr3_dqs_p,
ddr3_dqs_n => ddr3_dqs_n,
ddr3_addr => ddr3_addr,
ddr3_ba => ddr3_ba,
ddr3_ras_n => ddr3_ras_n,
ddr3_cas_n => ddr3_cas_n,
ddr3_we_n => ddr3_we_n,
ddr3_reset_n => ddr3_reset_n,
ddr3_ck_p => ddr3_ck_p,
ddr3_ck_n => ddr3_ck_n,
ddr3_cke => ddr3_cke,
ddr3_cs_n => ddr3_cs_n,
ddr3_dm => ddr3_dm,
ddr3_odt => ddr3_odt,
dsurx => dsurx,
dsutx => dsutx,
dsuctsn => dsuctsn,
dsurtsn => dsurtsn,
button => button,
switch => switch,
led => led,
iic_scl => iic_scl,
iic_sda => iic_sda,
gtrefclk_p => clkethp,
gtrefclk_n => clkethn,
phy_txclk => phy_gtxclk,
phy_txd => phy_txd(3 downto 0),
phy_txctl_txen => phy_txctl_txen,
phy_rxd => phy_rxd(3 downto 0),
phy_rxctl_rxdv => phy_rxctl_rxdv,
phy_rxclk => phy_rxclk'delayed(1 ns),
phy_reset => phy_reset,
phy_mdio => phy_mdio,
phy_mdc => phy_mdc,
sfp_clock_mux => OPEN
);
-- spi_gen_model : if (CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1) generate
-- spi0 : spi_flash
-- generic map (
-- ftype => 3,
-- debug => 0,
-- readcmd => 16#0B#,
-- dummybyte => 0,
-- dualoutput => 0)
-- port map (
-- sck => spi_clk,
-- di => spi_simo,
-- do => spi_miso,
-- csn => spi_sel_n,
-- sd_cmd_timeout => '0',
-- sd_data_timeout => '0');
-- end generate;
-- Memory Models instantiations
gen_mem_model : if (USE_MIG_INTERFACE_MODEL /= true) generate
ddr3mem : if (CFG_MIG_SERIES7 = 1) generate
u1 : ddr3ram
generic map (
width => 64,
abits => 14,
colbits => 10,
rowbits => 10,
implbanks => 1,
fname => ramfile,
lddelay => (0 ns),
ldguard => 1,
speedbin => 9, --DDR3-1600K
density => 3,
pagesize => 1,
changeendian => 8)
port map (
ck => ddr3_ck_p(0),
ckn => ddr3_ck_n(0),
cke => ddr3_cke(0),
csn => ddr3_cs_n(0),
odt => ddr3_odt(0),
rasn => ddr3_ras_n,
casn => ddr3_cas_n,
wen => ddr3_we_n,
dm => ddr3_dm,
ba => ddr3_ba,
a => ddr3_addr,
resetn => ddr3_reset_n,
dq => ddr3_dq,
dqs => ddr3_dqs_p,
dqsn => ddr3_dqs_n,
doload => led(3)
);
end generate ddr3mem;
end generate gen_mem_model;
mig_mem_model : if (USE_MIG_INTERFACE_MODEL = true) generate
ddr3_dq <= (others => 'Z');
ddr3_dqs_p <= (others => 'Z');
ddr3_dqs_n <= (others => 'Z');
end generate mig_mem_model;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
phy_mdio <= 'H';
phy_int <= '0';
p0: phy
generic map (
address => 7,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(phy_reset, phy_mdio, phy_txclk, phy_rxclk, phy_rxd,
phy_rxctl_rxdv, phy_rxer, phy_col, phy_crs, phy_txd,
phy_txctl_txen, phy_txer, phy_mdc, phy_gtxclk);
end generate;
iuerr : process
begin
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
wait on led(3); -- DDR3 Memory Init ready
wait for 5000 ns;
wait for 100 us;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ; -- this should be a failure
end process;
--data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
switch(3) <= '0';
wait for 2500 ns;
wait for 210 us; -- This is for proper DDR3 behaviour durign init phase not needed durin simulation
dsurst <= '1';
switch(3) <= '1';
if (USE_MIG_INTERFACE_MODEL /= true) then
wait on led(3); -- Wait for DDR3 Memory Init ready
end if;
report "Start DSU transfer";
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- Reads from memory and DSU register to mimic GRMON during simulation
l1 : loop
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU read memory " & tost(w32);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
rxi(dsurx, w32, txp, lresp);
--report "DSU Break and Single Step register" & tost(w32);
end loop l1;
wait;
-- ** This is only kept for reference --
-- do test read and writes to DDR3 to check status
-- Write
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#01#, 16#23#, 16#45#, 16#67#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
txa(dsutx, 16#89#, 16#AB#, 16#CD#, 16#EF#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
txa(dsutx, 16#08#, 16#19#, 16#2A#, 16#3B#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
txa(dsutx, 16#4C#, 16#5D#, 16#6E#, 16#7F#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#04#, txp);
rxi(dsurx, w32, txp, lresp);
report "* Read " & tost(w32);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#08#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#0C#, txp);
rxi(dsurx, w32, txp, lresp);
wait;
-- Register 0x90000000 (DSU Control Register)
-- Data 0x0000202e (b0010 0000 0010 1110)
-- [0] - Trace Enable
-- [1] - Break On Error
-- [2] - Break on IU watchpoint
-- [3] - Break on s/w break points
--
-- [4] - (Break on trap)
-- [5] - Break on error traps
-- [6] - Debug mode (Read mode only)
-- [7] - DSUEN (read mode)
--
-- [8] - DSUBRE (read mode)
-- [9] - Processor mode error (clears error)
-- [10] - processor halt (returns 1 if processor halted)
-- [11] - power down mode (return 1 if processor in power down mode)
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#80#, 16#02#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
end;
begin
dsuctsn <= '0';
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 09b73fb8001174e4cbc7abdce5cd89fe | 0.525685 | 3.297713 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/d5e322d2745b1271/zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl | 1 | 330,339 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:09:46 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_bram_ctrl_0_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
bid_gets_fifo_load : out STD_LOGIC;
bvalid_cnt_inc : out STD_LOGIC;
bid_gets_fifo_load_d1_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
axi_wdata_full_cmb114_out : out STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
\bvalid_cnt_reg[2]\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
\bvalid_cnt_reg[2]_0\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
bram_addr_ld_en : in STD_LOGIC;
bid_gets_fifo_load_d1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
axi_bvalid_int_reg : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\bvalid_cnt_reg[1]\ : in STD_LOGIC;
aw_active : in STD_LOGIC;
s_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
axi_wr_burst : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO is
signal \Addr_Counters[0].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[1].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[2].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].FDRE_I_n_0\ : STD_LOGIC;
signal \Addr_Counters[3].XORCY_I_i_1_n_0\ : STD_LOGIC;
signal CI : STD_LOGIC;
signal D_0 : STD_LOGIC;
signal Data_Exists_DFF_i_2_n_0 : STD_LOGIC;
signal Data_Exists_DFF_i_3_n_0 : STD_LOGIC;
signal S : STD_LOGIC;
signal S0_out : STD_LOGIC;
signal S1_out : STD_LOGIC;
signal addr_cy_1 : STD_LOGIC;
signal addr_cy_2 : STD_LOGIC;
signal addr_cy_3 : STD_LOGIC;
signal \axi_bid_int[11]_i_3_n_0\ : STD_LOGIC;
signal axi_bvalid_int_i_4_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_5_n_0 : STD_LOGIC;
signal axi_bvalid_int_i_6_n_0 : STD_LOGIC;
signal \^axi_wdata_full_cmb114_out\ : STD_LOGIC;
signal bid_fifo_ld : STD_LOGIC_VECTOR ( 11 downto 0 );
signal bid_fifo_not_empty : STD_LOGIC;
signal bid_fifo_rd : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^bid_gets_fifo_load\ : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_3_n_0 : STD_LOGIC;
signal \^bid_gets_fifo_load_d1_reg\ : STD_LOGIC;
signal \^bvalid_cnt_inc\ : STD_LOGIC;
signal sum_A_0 : STD_LOGIC;
signal sum_A_1 : STD_LOGIC;
signal sum_A_2 : STD_LOGIC;
signal sum_A_3 : STD_LOGIC;
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \Addr_Counters[0].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "(MUXCY,XORCY)";
attribute XILINX_TRANSFORM_PINMAP : string;
attribute XILINX_TRANSFORM_PINMAP of \Addr_Counters[0].MUXCY_L_I_CARRY4\ : label is "LO:O";
attribute BOX_TYPE of \Addr_Counters[1].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[2].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of \Addr_Counters[3].FDRE_I\ : label is "PRIMITIVE";
attribute BOX_TYPE of Data_Exists_DFF : label is "PRIMITIVE";
attribute XILINX_LEGACY_PRIM of Data_Exists_DFF : label is "FDR";
attribute BOX_TYPE of \FIFO_RAM[0].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name : string;
attribute srl_name of \FIFO_RAM[0].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[0].SRL16E_I ";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FIFO_RAM[0].SRL16E_I_i_1\ : label is "soft_lutpair44";
attribute BOX_TYPE of \FIFO_RAM[10].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[10].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[10].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[10].SRL16E_I_i_1\ : label is "soft_lutpair54";
attribute BOX_TYPE of \FIFO_RAM[11].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[11].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[11].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[11].SRL16E_I_i_1\ : label is "soft_lutpair55";
attribute BOX_TYPE of \FIFO_RAM[1].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[1].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[1].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[1].SRL16E_I_i_1\ : label is "soft_lutpair45";
attribute BOX_TYPE of \FIFO_RAM[2].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[2].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[2].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[2].SRL16E_I_i_1\ : label is "soft_lutpair46";
attribute BOX_TYPE of \FIFO_RAM[3].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[3].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[3].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[3].SRL16E_I_i_1\ : label is "soft_lutpair47";
attribute BOX_TYPE of \FIFO_RAM[4].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[4].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[4].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[4].SRL16E_I_i_1\ : label is "soft_lutpair48";
attribute BOX_TYPE of \FIFO_RAM[5].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[5].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[5].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[5].SRL16E_I_i_1\ : label is "soft_lutpair49";
attribute BOX_TYPE of \FIFO_RAM[6].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[6].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[6].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[6].SRL16E_I_i_1\ : label is "soft_lutpair50";
attribute BOX_TYPE of \FIFO_RAM[7].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[7].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[7].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[7].SRL16E_I_i_1\ : label is "soft_lutpair51";
attribute BOX_TYPE of \FIFO_RAM[8].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[8].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[8].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[8].SRL16E_I_i_1\ : label is "soft_lutpair52";
attribute BOX_TYPE of \FIFO_RAM[9].SRL16E_I\ : label is "PRIMITIVE";
attribute srl_bus_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM ";
attribute srl_name of \FIFO_RAM[9].SRL16E_I\ : label is "U0/\gext_inst.abcv4_0_ext_inst/GEN_AXI4.I_FULL_AXI/I_WR_CHNL/BID_FIFO/FIFO_RAM[9].SRL16E_I ";
attribute SOFT_HLUTNM of \FIFO_RAM[9].SRL16E_I_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[0]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \axi_bid_int[10]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \axi_bid_int[11]_i_2\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \axi_bid_int[1]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \axi_bid_int[2]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \axi_bid_int[3]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \axi_bid_int[4]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \axi_bid_int[5]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \axi_bid_int[6]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \axi_bid_int[7]_i_1\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axi_bid_int[8]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \axi_bid_int[9]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of axi_bvalid_int_i_3 : label is "soft_lutpair56";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_3 : label is "soft_lutpair56";
begin
axi_wdata_full_cmb114_out <= \^axi_wdata_full_cmb114_out\;
bid_gets_fifo_load <= \^bid_gets_fifo_load\;
bid_gets_fifo_load_d1_reg <= \^bid_gets_fifo_load_d1_reg\;
bvalid_cnt_inc <= \^bvalid_cnt_inc\;
\Addr_Counters[0].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_3,
Q => \Addr_Counters[0].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[0].MUXCY_L_I_CARRY4\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_CO_UNCONNECTED\(3),
CO(2) => addr_cy_1,
CO(1) => addr_cy_2,
CO(0) => addr_cy_3,
CYINIT => CI,
DI(3) => \NLW_Addr_Counters[0].MUXCY_L_I_CARRY4_DI_UNCONNECTED\(3),
DI(2) => \Addr_Counters[2].FDRE_I_n_0\,
DI(1) => \Addr_Counters[1].FDRE_I_n_0\,
DI(0) => \Addr_Counters[0].FDRE_I_n_0\,
O(3) => sum_A_0,
O(2) => sum_A_1,
O(1) => sum_A_2,
O(0) => sum_A_3,
S(3) => \Addr_Counters[3].XORCY_I_i_1_n_0\,
S(2) => S0_out,
S(1) => S1_out,
S(0) => S
);
\Addr_Counters[0].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[1].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[0].FDRE_I_n_0\,
O => S
);
\Addr_Counters[0].MUXCY_L_I_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"8AAAAAAAAAAAAAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => \axi_bid_int[11]_i_3_n_0\,
I2 => \Addr_Counters[0].FDRE_I_n_0\,
I3 => \Addr_Counters[1].FDRE_I_n_0\,
I4 => \Addr_Counters[3].FDRE_I_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => CI
);
\Addr_Counters[1].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_2,
Q => \Addr_Counters[1].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[1].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[3].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[1].FDRE_I_n_0\,
O => S1_out
);
\Addr_Counters[2].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_1,
Q => \Addr_Counters[2].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[2].MUXCY_L_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[2].FDRE_I_n_0\,
O => S0_out
);
\Addr_Counters[3].FDRE_I\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => s_axi_aclk,
CE => bid_fifo_not_empty,
D => sum_A_0,
Q => \Addr_Counters[3].FDRE_I_n_0\,
R => SR(0)
);
\Addr_Counters[3].XORCY_I_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[2].FDRE_I_n_0\,
I3 => bram_addr_ld_en,
I4 => \axi_bid_int[11]_i_3_n_0\,
I5 => \Addr_Counters[3].FDRE_I_n_0\,
O => \Addr_Counters[3].XORCY_I_i_1_n_0\
);
Data_Exists_DFF: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => D_0,
Q => bid_fifo_not_empty,
R => SR(0)
);
Data_Exists_DFF_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE0A"
)
port map (
I0 => bram_addr_ld_en,
I1 => Data_Exists_DFF_i_2_n_0,
I2 => Data_Exists_DFF_i_3_n_0,
I3 => bid_fifo_not_empty,
O => D_0
);
Data_Exists_DFF_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000FFFD"
)
port map (
I0 => \^bvalid_cnt_inc\,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
I3 => bvalid_cnt(1),
I4 => \^bid_gets_fifo_load_d1_reg\,
I5 => bid_gets_fifo_load_d1,
O => Data_Exists_DFF_i_2_n_0
);
Data_Exists_DFF_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \Addr_Counters[0].FDRE_I_n_0\,
I1 => \Addr_Counters[1].FDRE_I_n_0\,
I2 => \Addr_Counters[3].FDRE_I_n_0\,
I3 => \Addr_Counters[2].FDRE_I_n_0\,
O => Data_Exists_DFF_i_3_n_0
);
\FIFO_RAM[0].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(11),
Q => bid_fifo_rd(11)
);
\FIFO_RAM[0].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
O => bid_fifo_ld(11)
);
\FIFO_RAM[10].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(1),
Q => bid_fifo_rd(1)
);
\FIFO_RAM[10].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
O => bid_fifo_ld(1)
);
\FIFO_RAM[11].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(0),
Q => bid_fifo_rd(0)
);
\FIFO_RAM[11].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
O => bid_fifo_ld(0)
);
\FIFO_RAM[1].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(10),
Q => bid_fifo_rd(10)
);
\FIFO_RAM[1].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
O => bid_fifo_ld(10)
);
\FIFO_RAM[2].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(9),
Q => bid_fifo_rd(9)
);
\FIFO_RAM[2].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
O => bid_fifo_ld(9)
);
\FIFO_RAM[3].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(8),
Q => bid_fifo_rd(8)
);
\FIFO_RAM[3].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
O => bid_fifo_ld(8)
);
\FIFO_RAM[4].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(7),
Q => bid_fifo_rd(7)
);
\FIFO_RAM[4].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
O => bid_fifo_ld(7)
);
\FIFO_RAM[5].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(6),
Q => bid_fifo_rd(6)
);
\FIFO_RAM[5].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
O => bid_fifo_ld(6)
);
\FIFO_RAM[6].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(5),
Q => bid_fifo_rd(5)
);
\FIFO_RAM[6].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
O => bid_fifo_ld(5)
);
\FIFO_RAM[7].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(4),
Q => bid_fifo_rd(4)
);
\FIFO_RAM[7].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
O => bid_fifo_ld(4)
);
\FIFO_RAM[8].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(3),
Q => bid_fifo_rd(3)
);
\FIFO_RAM[8].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
O => bid_fifo_ld(3)
);
\FIFO_RAM[9].SRL16E_I\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000",
IS_CLK_INVERTED => '0'
)
port map (
A0 => \Addr_Counters[0].FDRE_I_n_0\,
A1 => \Addr_Counters[1].FDRE_I_n_0\,
A2 => \Addr_Counters[2].FDRE_I_n_0\,
A3 => \Addr_Counters[3].FDRE_I_n_0\,
CE => CI,
CLK => s_axi_aclk,
D => bid_fifo_ld(2),
Q => bid_fifo_rd(2)
);
\FIFO_RAM[9].SRL16E_I_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
O => bid_fifo_ld(2)
);
\axi_bid_int[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awid(0),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(0),
O => D(0)
);
\axi_bid_int[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(10),
I1 => axi_awaddr_full,
I2 => s_axi_awid(10),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(10),
O => D(10)
);
\axi_bid_int[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^bid_gets_fifo_load\,
I1 => \axi_bid_int[11]_i_3_n_0\,
O => E(0)
);
\axi_bid_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(11),
I1 => axi_awaddr_full,
I2 => s_axi_awid(11),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(11),
O => D(11)
);
\axi_bid_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"A888AAAAA8888888"
)
port map (
I0 => bid_fifo_not_empty,
I1 => bid_gets_fifo_load_d1,
I2 => s_axi_bready,
I3 => axi_bvalid_int_reg,
I4 => bid_gets_fifo_load_d1_i_3_n_0,
I5 => \^bvalid_cnt_inc\,
O => \axi_bid_int[11]_i_3_n_0\
);
\axi_bid_int[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awid(1),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(1),
O => D(1)
);
\axi_bid_int[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(2),
I1 => axi_awaddr_full,
I2 => s_axi_awid(2),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(2),
O => D(2)
);
\axi_bid_int[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awid(3),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(3),
O => D(3)
);
\axi_bid_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(4),
I1 => axi_awaddr_full,
I2 => s_axi_awid(4),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(4),
O => D(4)
);
\axi_bid_int[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(5),
I1 => axi_awaddr_full,
I2 => s_axi_awid(5),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(5),
O => D(5)
);
\axi_bid_int[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(6),
I1 => axi_awaddr_full,
I2 => s_axi_awid(6),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(6),
O => D(6)
);
\axi_bid_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(7),
I1 => axi_awaddr_full,
I2 => s_axi_awid(7),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(7),
O => D(7)
);
\axi_bid_int[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(8),
I1 => axi_awaddr_full,
I2 => s_axi_awid(8),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(8),
O => D(8)
);
\axi_bid_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => Q(9),
I1 => axi_awaddr_full,
I2 => s_axi_awid(9),
I3 => \^bid_gets_fifo_load\,
I4 => bid_fifo_rd(9),
O => D(9)
);
axi_bvalid_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"000055FD00000000"
)
port map (
I0 => \out\(2),
I1 => \^axi_wdata_full_cmb114_out\,
I2 => axi_bvalid_int_i_4_n_0,
I3 => axi_wr_burst,
I4 => \out\(1),
I5 => axi_bvalid_int_i_5_n_0,
O => \^bvalid_cnt_inc\
);
axi_bvalid_int_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"FE000000"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => axi_bvalid_int_reg,
I4 => s_axi_bready,
O => \^bid_gets_fifo_load_d1_reg\
);
axi_bvalid_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"1F11000000000000"
)
port map (
I0 => axi_bvalid_int_i_6_n_0,
I1 => \bvalid_cnt_reg[2]\,
I2 => wr_addr_sm_cs,
I3 => \bvalid_cnt_reg[2]_0\,
I4 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I5 => axi_awaddr_full,
O => axi_bvalid_int_i_4_n_0
);
axi_bvalid_int_i_5: unisim.vcomponents.LUT5
generic map(
INIT => X"74446444"
)
port map (
I0 => \out\(0),
I1 => \out\(2),
I2 => s_axi_wvalid,
I3 => s_axi_wlast,
I4 => \^axi_wdata_full_cmb114_out\,
O => axi_bvalid_int_i_5_n_0
);
axi_bvalid_int_i_6: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFFFFFF"
)
port map (
I0 => curr_awlen_reg_1_or_2,
I1 => axi_awlen_pipe_1_or_2,
I2 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I3 => axi_awaddr_full,
I4 => last_data_ack_mod,
O => axi_bvalid_int_i_6_n_0
);
axi_wready_int_mod_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"7F7F7F007F007F00"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(2),
I3 => aw_active,
I4 => s_axi_awready,
I5 => s_axi_awvalid,
O => \^axi_wdata_full_cmb114_out\
);
bid_gets_fifo_load_d1_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000800AA00AA00"
)
port map (
I0 => bram_addr_ld_en,
I1 => \^bid_gets_fifo_load_d1_reg\,
I2 => bid_fifo_not_empty,
I3 => \^bvalid_cnt_inc\,
I4 => \bvalid_cnt_reg[1]\,
I5 => bid_gets_fifo_load_d1_i_3_n_0,
O => \^bid_gets_fifo_load\
);
bid_gets_fifo_load_d1_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => bid_gets_fifo_load_d1_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bram_addr_ld_en_mod : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : out STD_LOGIC;
bram_addr_ld_en : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_1\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_2\ : out STD_LOGIC;
curr_fixed_burst_reg_reg : out STD_LOGIC;
curr_wrap_burst_reg_reg : out STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
bram_addr_inc : in STD_LOGIC;
bram_addr_rst_cmb : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wvalid : in STD_LOGIC;
bram_addr_a : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : in STD_LOGIC;
axi_awaddr_full : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
wr_addr_sm_cs : in STD_LOGIC;
last_data_ack_mod : in STD_LOGIC;
bvalid_cnt : in STD_LOGIC_VECTOR ( 2 downto 0 );
aw_active : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_awlen_pipe_1_or_2 : in STD_LOGIC;
curr_awlen_reg_1_or_2 : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_awsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
curr_fixed_burst : in STD_LOGIC;
curr_wrap_burst : in STD_LOGIC;
s_axi_aresetn_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[8]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal bram_addr_ld : STD_LOGIC_VECTOR ( 9 downto 1 );
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^bram_addr_ld_en_mod\ : STD_LOGIC;
signal save_init_bram_addr_ld : STD_LOGIC_VECTOR ( 15 downto 3 );
signal \save_init_bram_addr_ld[3]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_1\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_2\ : STD_LOGIC;
signal wrap_burst_total : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \wrap_burst_total[0]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_2_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_3_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_3__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \curr_wrap_burst_reg_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[15]_i_4\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[3]_i_2__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_2\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \wrap_burst_total[1]_i_3\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3__0\ : label is "soft_lutpair57";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[8]\;
SR(0) <= \^sr\(0);
bram_addr_ld_en <= \^bram_addr_ld_en\;
bram_addr_ld_en_mod <= \^bram_addr_ld_en_mod\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\save_init_bram_addr_ld_reg[15]_1\ <= \^save_init_bram_addr_ld_reg[15]_1\;
\save_init_bram_addr_ld_reg[15]_2\ <= \^save_init_bram_addr_ld_reg[15]_2\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BB8BBBBB88B88888"
)
port map (
I0 => bram_addr_ld(8),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(7),
I5 => bram_addr_a(8),
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(9),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(9),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\,
I4 => bram_addr_a(8),
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(12),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(13),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(14),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"4500FFFF"
)
port map (
I0 => \^bram_addr_ld_en_mod\,
I1 => curr_fixed_burst_reg,
I2 => bram_addr_inc,
I3 => bram_addr_rst_cmb,
I4 => s_axi_aresetn,
O => \^sr\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAAAAAAAAAAA"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
I2 => \out\(1),
I3 => \out\(2),
I4 => \out\(0),
I5 => s_axi_wvalid,
O => \^bram_addr_ld_en_mod\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(15),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555555FFFFFFDF"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => wrap_burst_total(1),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(0),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_6_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00C000"
)
port map (
I0 => bram_addr_a(2),
I1 => bram_addr_a(1),
I2 => wrap_burst_total(1),
I3 => bram_addr_a(0),
I4 => wrap_burst_total(0),
I5 => wrap_burst_total(2),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_8_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B800B800FFFF"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
I1 => axi_awaddr_full,
I2 => s_axi_awaddr(0),
I3 => \^bram_addr_ld_en\,
I4 => \^bram_addr_ld_en_mod\,
I5 => bram_addr_a(0),
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8BB8"
)
port map (
I0 => bram_addr_ld(1),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(1),
I3 => bram_addr_a(0),
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BB8B8B8"
)
port map (
I0 => bram_addr_ld(2),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(2),
I3 => bram_addr_a(0),
I4 => bram_addr_a(1),
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8BB8B8B8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(3),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(3),
I3 => bram_addr_a(2),
I4 => bram_addr_a(0),
I5 => bram_addr_a(1),
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B88B"
)
port map (
I0 => bram_addr_ld(4),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(4),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(5),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(5),
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I4 => bram_addr_a(4),
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B88BB8B8B8B8B8"
)
port map (
I0 => bram_addr_ld(6),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(6),
I3 => bram_addr_a(4),
I4 => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\,
I5 => bram_addr_a(5),
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => bram_addr_a(1),
I1 => bram_addr_a(0),
I2 => bram_addr_a(2),
I3 => bram_addr_a(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[8]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => bram_addr_ld(7),
I1 => \^bram_addr_ld_en_mod\,
I2 => bram_addr_a(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\,
I4 => bram_addr_a(6),
O => \^d\(7)
);
\curr_fixed_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_fixed_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_fixed_burst,
I3 => \^sr\(0),
O => curr_fixed_burst_reg_reg
);
\curr_wrap_burst_reg_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00E2"
)
port map (
I0 => curr_wrap_burst_reg,
I1 => \^bram_addr_ld_en\,
I2 => curr_wrap_burst,
I3 => \^sr\(0),
O => curr_wrap_burst_reg_reg
);
\save_init_bram_addr_ld[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(10),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(8),
O => bram_addr_ld(8)
);
\save_init_bram_addr_ld[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(11),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(9),
O => bram_addr_ld(9)
);
\save_init_bram_addr_ld[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0808080808AA0808"
)
port map (
I0 => \GEN_AWREADY.axi_aresetn_d2_reg\,
I1 => \^save_init_bram_addr_ld_reg[15]_0\,
I2 => wr_addr_sm_cs,
I3 => \^save_init_bram_addr_ld_reg[15]_1\,
I4 => last_data_ack_mod,
I5 => \^save_init_bram_addr_ld_reg[15]_2\,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"007F007F007F0000"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
I3 => aw_active,
I4 => axi_awaddr_full,
I5 => s_axi_awvalid,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[15]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => bvalid_cnt(2),
I1 => bvalid_cnt(0),
I2 => bvalid_cnt(1),
O => \^save_init_bram_addr_ld_reg[15]_1\
);
\save_init_bram_addr_ld[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\,
I2 => axi_awlen_pipe_1_or_2,
I3 => curr_awlen_reg_1_or_2,
O => \^save_init_bram_addr_ld_reg[15]_2\
);
\save_init_bram_addr_ld[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(1),
O => bram_addr_ld(1)
);
\save_init_bram_addr_ld[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"C80C"
)
port map (
I0 => wrap_burst_total(0),
I1 => save_init_bram_addr_ld(3),
I2 => wrap_burst_total(1),
I3 => wrap_burst_total(2),
O => \save_init_bram_addr_ld[3]_i_2__0_n_0\
);
\save_init_bram_addr_ld[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2__0_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(2),
O => bram_addr_ld(2)
);
\save_init_bram_addr_ld[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => save_init_bram_addr_ld(4),
I1 => wrap_burst_total(0),
I2 => wrap_burst_total(2),
I3 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[4]_i_2__0_n_0\
);
\save_init_bram_addr_ld[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F808F8F8F808080"
)
port map (
I0 => save_init_bram_addr_ld(5),
I1 => \save_init_bram_addr_ld[5]_i_2__0_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I3 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
I4 => axi_awaddr_full,
I5 => s_axi_awaddr(3),
O => bram_addr_ld(3)
);
\save_init_bram_addr_ld[5]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FB"
)
port map (
I0 => wrap_burst_total(0),
I1 => wrap_burst_total(2),
I2 => wrap_burst_total(1),
O => \save_init_bram_addr_ld[5]_i_2__0_n_0\
);
\save_init_bram_addr_ld[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(4),
O => bram_addr_ld(4)
);
\save_init_bram_addr_ld[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(5),
O => bram_addr_ld(5)
);
\save_init_bram_addr_ld[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(8),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(6),
O => bram_addr_ld(6)
);
\save_init_bram_addr_ld[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => save_init_bram_addr_ld(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_7_n_0\,
I2 => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
I3 => axi_awaddr_full,
I4 => s_axi_awaddr(7),
O => bram_addr_ld(7)
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(8),
Q => save_init_bram_addr_ld(10),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(9),
Q => save_init_bram_addr_ld(11),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => save_init_bram_addr_ld(12),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => save_init_bram_addr_ld(13),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => save_init_bram_addr_ld(14),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => save_init_bram_addr_ld(15),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(1),
Q => save_init_bram_addr_ld(3),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(2),
Q => save_init_bram_addr_ld(4),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(3),
Q => save_init_bram_addr_ld(5),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(4),
Q => save_init_bram_addr_ld(6),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(5),
Q => save_init_bram_addr_ld(7),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(6),
Q => save_init_bram_addr_ld(8),
R => s_axi_aresetn_0(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => bram_addr_ld(7),
Q => save_init_bram_addr_ld(9),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000A22200000000"
)
port map (
I0 => \wrap_burst_total[0]_i_2__0_n_0\,
I1 => \wrap_burst_total[0]_i_3_n_0\,
I2 => Q(1),
I3 => Q(2),
I4 => \wrap_burst_total[2]_i_2__0_n_0\,
I5 => \wrap_burst_total[1]_i_2_n_0\,
O => \wrap_burst_total[0]_i_1__0_n_0\
);
\wrap_burst_total[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"CCA533A5FFA5FFA5"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
I5 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_2__0_n_0\
);
\wrap_burst_total[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_awaddr_full,
I1 => axi_awsize_pipe(0),
O => \wrap_burst_total[0]_i_3_n_0\
);
\wrap_burst_total[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"08000800F3000000"
)
port map (
I0 => \wrap_burst_total[2]_i_3__0_n_0\,
I1 => axi_awaddr_full,
I2 => axi_awsize_pipe(0),
I3 => \wrap_burst_total[1]_i_2_n_0\,
I4 => \wrap_burst_total[1]_i_3_n_0\,
I5 => \wrap_burst_total[2]_i_2__0_n_0\,
O => \wrap_burst_total[1]_i_1__0_n_0\
);
\wrap_burst_total[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(0),
O => \wrap_burst_total[1]_i_2_n_0\
);
\wrap_burst_total[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(1),
O => \wrap_burst_total[1]_i_3_n_0\
);
\wrap_burst_total[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A000000088008800"
)
port map (
I0 => \wrap_burst_total[2]_i_2__0_n_0\,
I1 => s_axi_awlen(0),
I2 => Q(0),
I3 => \wrap_burst_total[2]_i_3__0_n_0\,
I4 => axi_awsize_pipe(0),
I5 => axi_awaddr_full,
O => \wrap_burst_total[2]_i_1__0_n_0\
);
\wrap_burst_total[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_awaddr_full,
I2 => s_axi_awlen(3),
O => \wrap_burst_total[2]_i_2__0_n_0\
);
\wrap_burst_total[2]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_awlen(2),
I1 => Q(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => Q(1),
O => \wrap_burst_total[2]_i_3__0_n_0\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1__0_n_0\,
Q => wrap_burst_total(0),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1__0_n_0\,
Q => wrap_burst_total(1),
R => s_axi_aresetn_0(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1__0_n_0\,
Q => wrap_burst_total(2),
R => s_axi_aresetn_0(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
port (
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_burst_total_reg[0]_0\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_1\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_2\ : out STD_LOGIC;
\wrap_burst_total_reg[0]_3\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 1 downto 0 );
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 13 downto 0 );
bram_addr_ld_en : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ : out STD_LOGIC;
\rd_data_sm_cs_reg[1]\ : out STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ : out STD_LOGIC;
\save_init_bram_addr_ld_reg[15]_0\ : out STD_LOGIC;
axi_b2b_brst_reg : out STD_LOGIC;
\rd_data_sm_cs_reg[3]\ : out STD_LOGIC;
rd_adv_buf67_out : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_arsize_pipe : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_araddr_full : in STD_LOGIC;
curr_fixed_burst_reg : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : in STD_LOGIC;
curr_wrap_burst_reg : in STD_LOGIC;
\rd_data_sm_cs_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_rd_burst_two_reg : in STD_LOGIC;
axi_rd_burst : in STD_LOGIC;
axi_aresetn_d2 : in STD_LOGIC;
rd_addr_sm_cs : in STD_LOGIC;
last_bram_addr : in STD_LOGIC;
ar_active : in STD_LOGIC;
pend_rd_op : in STD_LOGIC;
no_ar_ack : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
brst_zero : in STD_LOGIC;
axi_rvalid_int_reg : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
end_brst_rd : in STD_LOGIC;
axi_b2b_brst : in STD_LOGIC;
axi_arsize_pipe_max : in STD_LOGIC;
disable_b2b_brst : in STD_LOGIC;
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ : in STD_LOGIC;
axi_arlen_pipe_1_or_2 : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 : entity is "wrap_brst";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0 is
signal \^d\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\ : STD_LOGIC;
signal \^gen_dual_addr_cnt.bram_addr_int_reg[6]\ : STD_LOGIC;
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axi_b2b_brst_reg\ : STD_LOGIC;
signal \^bram_addr_ld_en\ : STD_LOGIC;
signal \^rd_adv_buf67_out\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[1]\ : STD_LOGIC;
signal \^rd_data_sm_cs_reg[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld[10]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[11]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[15]_i_2__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[3]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[4]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[5]_i_2_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[6]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[7]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[8]_i_1__0_n_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld[9]_i_1__0_n_0\ : STD_LOGIC;
signal \^save_init_bram_addr_ld_reg[15]_0\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[10]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[11]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[12]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[13]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[14]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[15]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[3]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[4]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[5]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[6]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[7]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[8]\ : STD_LOGIC;
signal \save_init_bram_addr_ld_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_burst_total[1]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_1_n_0\ : STD_LOGIC;
signal \wrap_burst_total[2]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_0\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_1\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_2\ : STD_LOGIC;
signal \^wrap_burst_total_reg[0]_3\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_burst_total_reg_n_0_[2]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[4]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \save_init_bram_addr_ld[5]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_2\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_3__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[0]_i_5\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wrap_burst_total[2]_i_3\ : label is "soft_lutpair3";
begin
D(13 downto 0) <= \^d\(13 downto 0);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\;
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ <= \^gen_dual_addr_cnt.bram_addr_int_reg[6]\;
SR(0) <= \^sr\(0);
axi_b2b_brst_reg <= \^axi_b2b_brst_reg\;
bram_addr_ld_en <= \^bram_addr_ld_en\;
rd_adv_buf67_out <= \^rd_adv_buf67_out\;
\rd_data_sm_cs_reg[1]\ <= \^rd_data_sm_cs_reg[1]\;
\rd_data_sm_cs_reg[3]\ <= \^rd_data_sm_cs_reg[3]\;
\save_init_bram_addr_ld_reg[15]_0\ <= \^save_init_bram_addr_ld_reg[15]_0\;
\wrap_burst_total_reg[0]_0\ <= \^wrap_burst_total_reg[0]_0\;
\wrap_burst_total_reg[0]_1\ <= \^wrap_burst_total_reg[0]_1\;
\wrap_burst_total_reg[0]_2\ <= \^wrap_burst_total_reg[0]_2\;
\wrap_burst_total_reg[0]_3\ <= \^wrap_burst_total_reg[0]_3\;
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"DF20FFFFDF200000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
O => \^d\(8)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"5D"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I2 => curr_fixed_burst_reg,
O => E(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(8),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
O => \^d\(9)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"E0E0F0F0E0E0FFF0"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\,
I2 => \^rd_data_sm_cs_reg[1]\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\,
I4 => \rd_data_sm_cs_reg[3]_0\(1),
I5 => \rd_data_sm_cs_reg[3]_0\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => \rd_data_sm_cs_reg[3]_0\(0),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_5_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000080800080"
)
port map (
I0 => \rd_data_sm_cs_reg[3]_0\(0),
I1 => axi_rvalid_int_reg,
I2 => s_axi_rready,
I3 => end_brst_rd,
I4 => axi_b2b_brst,
I5 => brst_zero,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_6_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[12]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[12]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(10),
O => \^d\(10)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[13]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[13]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(11),
O => \^d\(11)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[14]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[14]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(12),
O => \^d\(12)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
O => E(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[15]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(13),
O => \^d\(13)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"88A80000"
)
port map (
I0 => \^gen_dual_addr_cnt.bram_addr_int_reg[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\,
I2 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I3 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I4 => curr_wrap_burst_reg,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000008F00A000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \wrap_burst_total_reg_n_0_[1]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I4 => \wrap_burst_total_reg_n_0_[0]\,
I5 => \wrap_burst_total_reg_n_0_[2]\,
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000A808FD5D"
)
port map (
I0 => \^bram_addr_ld_en\,
I1 => s_axi_araddr(0),
I2 => axi_araddr_full,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I5 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
O => \^d\(0)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6F60"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
O => \^d\(1)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AFF6A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
O => \^d\(2)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAFFFF6AAA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
O => \^d\(3)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9F90"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I3 => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
O => \^d\(4)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I1 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
O => \^d\(5)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A6AAFFFFA6AA0000"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(4),
I2 => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\,
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(5),
I4 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I5 => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
O => \^d\(6)
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[8]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7FFF"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(1),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(0),
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(2),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(3),
O => \^gen_dual_addr_cnt.bram_addr_int_reg[6]\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"9AFF9A00"
)
port map (
I0 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(7),
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(6),
I3 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_3__0_n_0\,
I4 => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
O => \^d\(7)
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rvalid_int_reg,
I1 => s_axi_rready,
O => \^rd_adv_buf67_out\
);
axi_b2b_brst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFDFFFF"
)
port map (
I0 => axi_arsize_pipe_max,
I1 => disable_b2b_brst,
I2 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\,
I3 => axi_arlen_pipe_1_or_2,
I4 => axi_araddr_full,
O => \^axi_b2b_brst_reg\
);
bram_en_int_i_5: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \rd_data_sm_cs_reg[3]_0\(3),
I1 => \rd_data_sm_cs_reg[3]_0\(2),
O => \^rd_data_sm_cs_reg[3]\
);
bram_en_int_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => end_brst_rd,
I1 => brst_zero,
I2 => \rd_data_sm_cs_reg[3]_0\(2),
I3 => \rd_data_sm_cs_reg[3]_0\(0),
I4 => axi_rvalid_int_reg,
I5 => s_axi_rready,
O => \^gen_dual_addr_cnt.bram_addr_int_reg[11]_0\
);
bram_rst_b_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => \^sr\(0)
);
\rd_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F000E000F0000"
)
port map (
I0 => axi_rd_burst_two_reg,
I1 => axi_rd_burst,
I2 => \rd_data_sm_cs_reg[3]_0\(3),
I3 => \rd_data_sm_cs_reg[3]_0\(2),
I4 => \rd_data_sm_cs_reg[3]_0\(1),
I5 => \rd_data_sm_cs_reg[3]_0\(0),
O => \^rd_data_sm_cs_reg[1]\
);
\save_init_bram_addr_ld[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[10]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(8),
O => \save_init_bram_addr_ld[10]_i_1__0_n_0\
);
\save_init_bram_addr_ld[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[11]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(9),
O => \save_init_bram_addr_ld[11]_i_1__0_n_0\
);
\save_init_bram_addr_ld[15]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"02AA0202"
)
port map (
I0 => axi_aresetn_d2,
I1 => rd_addr_sm_cs,
I2 => \save_init_bram_addr_ld[15]_i_2__0_n_0\,
I3 => \^save_init_bram_addr_ld_reg[15]_0\,
I4 => last_bram_addr,
O => \^bram_addr_ld_en\
);
\save_init_bram_addr_ld[15]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEFEFEFF"
)
port map (
I0 => ar_active,
I1 => pend_rd_op,
I2 => no_ar_ack,
I3 => s_axi_arvalid,
I4 => axi_araddr_full,
O => \save_init_bram_addr_ld[15]_i_2__0_n_0\
);
\save_init_bram_addr_ld[15]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \^axi_b2b_brst_reg\,
I1 => \rd_data_sm_cs_reg[3]_0\(0),
I2 => \rd_data_sm_cs_reg[3]_0\(1),
I3 => \^rd_data_sm_cs_reg[3]\,
I4 => brst_zero,
I5 => \^rd_adv_buf67_out\,
O => \^save_init_bram_addr_ld_reg[15]_0\
);
\save_init_bram_addr_ld[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[3]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(1),
O => \save_init_bram_addr_ld[3]_i_1__0_n_0\
);
\save_init_bram_addr_ld[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A282"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[3]\,
I1 => \wrap_burst_total_reg_n_0_[1]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[0]\,
O => \save_init_bram_addr_ld[3]_i_2_n_0\
);
\save_init_bram_addr_ld[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld[4]_i_2_n_0\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(2),
O => \save_init_bram_addr_ld[4]_i_1__0_n_0\
);
\save_init_bram_addr_ld[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A28A"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[4]\,
I1 => \wrap_burst_total_reg_n_0_[0]\,
I2 => \wrap_burst_total_reg_n_0_[2]\,
I3 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[4]_i_2_n_0\
);
\save_init_bram_addr_ld[5]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"2F202F2F2F202020"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[5]\,
I1 => \save_init_bram_addr_ld[5]_i_2_n_0\,
I2 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I3 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
I4 => axi_araddr_full,
I5 => s_axi_araddr(3),
O => \save_init_bram_addr_ld[5]_i_1__0_n_0\
);
\save_init_bram_addr_ld[5]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \wrap_burst_total_reg_n_0_[0]\,
I1 => \wrap_burst_total_reg_n_0_[2]\,
I2 => \wrap_burst_total_reg_n_0_[1]\,
O => \save_init_bram_addr_ld[5]_i_2_n_0\
);
\save_init_bram_addr_ld[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[6]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(4),
O => \save_init_bram_addr_ld[6]_i_1__0_n_0\
);
\save_init_bram_addr_ld[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[7]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(5),
O => \save_init_bram_addr_ld[7]_i_1__0_n_0\
);
\save_init_bram_addr_ld[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[8]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(6),
O => \save_init_bram_addr_ld[8]_i_1__0_n_0\
);
\save_init_bram_addr_ld[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8BBB888"
)
port map (
I0 => \save_init_bram_addr_ld_reg_n_0_[9]\,
I1 => \GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4__0_n_0\,
I2 => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
I3 => axi_araddr_full,
I4 => s_axi_araddr(7),
O => \save_init_bram_addr_ld[9]_i_1__0_n_0\
);
\save_init_bram_addr_ld_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[10]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[10]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[11]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[11]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(10),
Q => \save_init_bram_addr_ld_reg_n_0_[12]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(11),
Q => \save_init_bram_addr_ld_reg_n_0_[13]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(12),
Q => \save_init_bram_addr_ld_reg_n_0_[14]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \^d\(13),
Q => \save_init_bram_addr_ld_reg_n_0_[15]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[3]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[3]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[4]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[4]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[5]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[5]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[6]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[6]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[7]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[7]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[8]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[8]\,
R => \^sr\(0)
);
\save_init_bram_addr_ld_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \save_init_bram_addr_ld[9]_i_1__0_n_0\,
Q => \save_init_bram_addr_ld_reg_n_0_[9]\,
R => \^sr\(0)
);
\wrap_burst_total[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"3202010100000000"
)
port map (
I0 => \^wrap_burst_total_reg[0]_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => \wrap_burst_total[0]_i_3__0_n_0\,
I3 => Q(2),
I4 => \^wrap_burst_total_reg[0]_2\,
I5 => \^wrap_burst_total_reg[0]_3\,
O => \wrap_burst_total[0]_i_1_n_0\
);
\wrap_burst_total[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(2),
I1 => axi_araddr_full,
I2 => s_axi_arlen(2),
O => \^wrap_burst_total_reg[0]_0\
);
\wrap_burst_total[0]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_araddr_full,
I1 => axi_arsize_pipe(0),
O => \wrap_burst_total[0]_i_3__0_n_0\
);
\wrap_burst_total[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
O => \^wrap_burst_total_reg[0]_2\
);
\wrap_burst_total[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(0),
I1 => axi_araddr_full,
I2 => s_axi_arlen(0),
O => \^wrap_burst_total_reg[0]_3\
);
\wrap_burst_total[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220A880A000A880A"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => axi_arsize_pipe(0),
I2 => s_axi_arlen(3),
I3 => axi_araddr_full,
I4 => Q(3),
I5 => Q(2),
O => \wrap_burst_total[1]_i_1_n_0\
);
\wrap_burst_total[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8088008880000000"
)
port map (
I0 => \wrap_burst_total[2]_i_2_n_0\,
I1 => \^wrap_burst_total_reg[0]_1\,
I2 => axi_arsize_pipe(0),
I3 => axi_araddr_full,
I4 => Q(2),
I5 => s_axi_arlen(2),
O => \wrap_burst_total[2]_i_1_n_0\
);
\wrap_burst_total[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CCA000A0"
)
port map (
I0 => s_axi_arlen(1),
I1 => Q(1),
I2 => s_axi_arlen(0),
I3 => axi_araddr_full,
I4 => Q(0),
O => \wrap_burst_total[2]_i_2_n_0\
);
\wrap_burst_total[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => Q(3),
I1 => axi_araddr_full,
I2 => s_axi_arlen(3),
O => \^wrap_burst_total_reg[0]_1\
);
\wrap_burst_total_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[0]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[0]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[1]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[1]\,
R => \^sr\(0)
);
\wrap_burst_total_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \^bram_addr_ld_en\,
D => \wrap_burst_total[2]_i_1_n_0\,
Q => \wrap_burst_total_reg_n_0_[2]\,
R => \^sr\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
port (
bram_rst_a : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aclk : in STD_LOGIC;
\GEN_AWREADY.axi_aresetn_d2_reg\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
axi_aresetn_d2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
axi_aresetn_re_reg : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl is
signal \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \/i__n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_arready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_ARREADY.axi_early_arready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.ar_active_i_4_n_0\ : STD_LOGIC;
signal \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_int[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp2_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[0]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[10]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[11]_i_2_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[1]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[2]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[4]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[5]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[6]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[8]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp[9]_i_1_n_0\ : STD_LOGIC;
signal \GEN_RID.axi_rid_temp_full_i_1_n_0\ : STD_LOGIC;
signal I_WRAP_BRST_n_1 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_18 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_24 : STD_LOGIC;
signal I_WRAP_BRST_n_25 : STD_LOGIC;
signal I_WRAP_BRST_n_26 : STD_LOGIC;
signal I_WRAP_BRST_n_27 : STD_LOGIC;
signal I_WRAP_BRST_n_28 : STD_LOGIC;
signal I_WRAP_BRST_n_3 : STD_LOGIC;
signal I_WRAP_BRST_n_4 : STD_LOGIC;
signal I_WRAP_BRST_n_6 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal act_rd_burst : STD_LOGIC;
signal act_rd_burst_i_1_n_0 : STD_LOGIC;
signal act_rd_burst_i_3_n_0 : STD_LOGIC;
signal act_rd_burst_i_4_n_0 : STD_LOGIC;
signal act_rd_burst_set : STD_LOGIC;
signal act_rd_burst_two : STD_LOGIC;
signal act_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal ar_active : STD_LOGIC;
signal araddr_pipe_ld43_out : STD_LOGIC;
signal axi_araddr_full : STD_LOGIC;
signal axi_arburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_arid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_arlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_arlen_pipe_1_or_2 : STD_LOGIC;
signal axi_arready_int : STD_LOGIC;
signal axi_arsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_arsize_pipe_max : STD_LOGIC;
signal axi_arsize_pipe_max_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst : STD_LOGIC;
signal axi_b2b_brst_i_1_n_0 : STD_LOGIC;
signal axi_b2b_brst_i_3_n_0 : STD_LOGIC;
signal axi_early_arready_int : STD_LOGIC;
signal axi_rd_burst : STD_LOGIC;
signal axi_rd_burst_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_i_2_n_0 : STD_LOGIC;
signal axi_rd_burst_i_3_n_0 : STD_LOGIC;
signal axi_rd_burst_two : STD_LOGIC;
signal axi_rd_burst_two_i_1_n_0 : STD_LOGIC;
signal axi_rd_burst_two_reg_n_0 : STD_LOGIC;
signal axi_rid_temp : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp20_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_rid_temp2_full : STD_LOGIC;
signal axi_rid_temp_full : STD_LOGIC;
signal axi_rid_temp_full_d1 : STD_LOGIC;
signal axi_rlast_int_i_1_n_0 : STD_LOGIC;
signal axi_rlast_set : STD_LOGIC;
signal axi_rvalid_clr_ok : STD_LOGIC;
signal axi_rvalid_clr_ok_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_2_n_0 : STD_LOGIC;
signal axi_rvalid_clr_ok_i_3_n_0 : STD_LOGIC;
signal axi_rvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_set : STD_LOGIC;
signal axi_rvalid_set_cmb : STD_LOGIC;
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal \^bram_en_b\ : STD_LOGIC;
signal bram_en_int_i_10_n_0 : STD_LOGIC;
signal bram_en_int_i_11_n_0 : STD_LOGIC;
signal bram_en_int_i_1_n_0 : STD_LOGIC;
signal bram_en_int_i_2_n_0 : STD_LOGIC;
signal bram_en_int_i_3_n_0 : STD_LOGIC;
signal bram_en_int_i_4_n_0 : STD_LOGIC;
signal bram_en_int_i_6_n_0 : STD_LOGIC;
signal bram_en_int_i_7_n_0 : STD_LOGIC;
signal bram_en_int_i_9_n_0 : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
signal brst_cnt : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \brst_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[5]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[6]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_2_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \brst_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal brst_cnt_max : STD_LOGIC;
signal brst_cnt_max_d1 : STD_LOGIC;
signal brst_one : STD_LOGIC;
signal brst_one0 : STD_LOGIC;
signal brst_one_i_1_n_0 : STD_LOGIC;
signal brst_zero : STD_LOGIC;
signal brst_zero_i_1_n_0 : STD_LOGIC;
signal brst_zero_i_2_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal disable_b2b_brst : STD_LOGIC;
signal disable_b2b_brst_cmb : STD_LOGIC;
signal disable_b2b_brst_i_2_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_3_n_0 : STD_LOGIC;
signal disable_b2b_brst_i_4_n_0 : STD_LOGIC;
signal end_brst_rd : STD_LOGIC;
signal end_brst_rd_clr : STD_LOGIC;
signal end_brst_rd_clr_i_1_n_0 : STD_LOGIC;
signal end_brst_rd_i_1_n_0 : STD_LOGIC;
signal last_bram_addr : STD_LOGIC;
signal last_bram_addr0 : STD_LOGIC;
signal last_bram_addr_i_2_n_0 : STD_LOGIC;
signal last_bram_addr_i_3_n_0 : STD_LOGIC;
signal last_bram_addr_i_4_n_0 : STD_LOGIC;
signal last_bram_addr_i_5_n_0 : STD_LOGIC;
signal last_bram_addr_i_6_n_0 : STD_LOGIC;
signal last_bram_addr_i_7_n_0 : STD_LOGIC;
signal last_bram_addr_i_8_n_0 : STD_LOGIC;
signal last_bram_addr_i_9_n_0 : STD_LOGIC;
signal no_ar_ack : STD_LOGIC;
signal no_ar_ack_i_1_n_0 : STD_LOGIC;
signal p_0_in13_in : STD_LOGIC;
signal p_13_out : STD_LOGIC;
signal p_26_out : STD_LOGIC;
signal p_48_out : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal pend_rd_op : STD_LOGIC;
signal pend_rd_op_i_1_n_0 : STD_LOGIC;
signal pend_rd_op_i_2_n_0 : STD_LOGIC;
signal pend_rd_op_i_3_n_0 : STD_LOGIC;
signal pend_rd_op_i_4_n_0 : STD_LOGIC;
signal pend_rd_op_i_5_n_0 : STD_LOGIC;
signal pend_rd_op_i_6_n_0 : STD_LOGIC;
signal pend_rd_op_i_7_n_0 : STD_LOGIC;
signal pend_rd_op_i_8_n_0 : STD_LOGIC;
signal pend_rd_op_i_9_n_0 : STD_LOGIC;
signal rd_addr_sm_cs : STD_LOGIC;
signal rd_adv_buf67_out : STD_LOGIC;
signal rd_data_sm_cs : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \rd_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[0]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[1]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[2]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_2_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_3_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_4_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_5_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_6_n_0\ : STD_LOGIC;
signal \rd_data_sm_cs[3]_i_7_n_0\ : STD_LOGIC;
signal rd_data_sm_ns : STD_LOGIC;
signal rd_skid_buf : STD_LOGIC_VECTOR ( 31 downto 0 );
signal rd_skid_buf_ld : STD_LOGIC;
signal rd_skid_buf_ld_cmb : STD_LOGIC;
signal rd_skid_buf_ld_reg : STD_LOGIC;
signal rddata_mux_sel : STD_LOGIC;
signal rddata_mux_sel_cmb : STD_LOGIC;
signal rddata_mux_sel_i_1_n_0 : STD_LOGIC;
signal rddata_mux_sel_i_3_n_0 : STD_LOGIC;
signal rlast_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of rlast_sm_cs : signal is "yes";
signal \^s_axi_rlast\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_rlast_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_arready_int_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_ARREADY.axi_early_arready_int_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[0]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[10]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[11]_i_2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[1]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[2]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[3]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[4]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[5]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[6]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[7]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[8]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \GEN_RID.axi_rid_temp2[9]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of act_rd_burst_i_4 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_2 : label is "soft_lutpair11";
attribute SOFT_HLUTNM of axi_rvalid_clr_ok_i_3 : label is "soft_lutpair19";
attribute SOFT_HLUTNM of axi_rvalid_set_i_1 : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \brst_cnt[4]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \brst_cnt[6]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_3\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \brst_cnt[7]_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of brst_zero_i_1 : label is "soft_lutpair15";
attribute SOFT_HLUTNM of brst_zero_i_2 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of disable_b2b_brst_i_2 : label is "soft_lutpair17";
attribute SOFT_HLUTNM of last_bram_addr_i_4 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of last_bram_addr_i_5 : label is "soft_lutpair23";
attribute SOFT_HLUTNM of last_bram_addr_i_7 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of last_bram_addr_i_9 : label is "soft_lutpair10";
attribute SOFT_HLUTNM of pend_rd_op_i_4 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of pend_rd_op_i_6 : label is "soft_lutpair13";
attribute SOFT_HLUTNM of pend_rd_op_i_7 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of pend_rd_op_i_8 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of pend_rd_op_i_9 : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[0]_i_3\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_4\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \rd_data_sm_cs[2]_i_5\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_3\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \rd_data_sm_cs[3]_i_6\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of rddata_mux_sel_i_1 : label is "soft_lutpair13";
begin
Q(13 downto 0) <= \^q\(13 downto 0);
bram_en_b <= \^bram_en_b\;
bram_rst_a <= \^bram_rst_a\;
s_axi_rlast <= \^s_axi_rlast\;
s_axi_rvalid <= \^s_axi_rvalid\;
\/FSM_sequential_rlast_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0011001300130013"
)
port map (
I0 => axi_rd_burst,
I1 => rlast_sm_cs(1),
I2 => act_rd_burst_two,
I3 => axi_rd_burst_two_reg_n_0,
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\
);
\/FSM_sequential_rlast_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"003F007F003F0055"
)
port map (
I0 => axi_rd_burst,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rlast_sm_cs(1),
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_two,
O => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\
);
\/i_\: unisim.vcomponents.LUT6
generic map(
INIT => X"F000F111F000E000"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => rlast_sm_cs(0),
I5 => last_bram_addr,
O => \/i__n_0\
);
\/i___0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008080000F8080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(1),
I4 => rlast_sm_cs(2),
I5 => \^s_axi_rlast\,
O => axi_rlast_set
);
\FSM_sequential_rlast_sm_cs[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[0]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(0),
O => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"01FF0100"
)
port map (
I0 => rlast_sm_cs(2),
I1 => rlast_sm_cs(0),
I2 => \/FSM_sequential_rlast_sm_cs[1]_i_2_n_0\,
I3 => \/i__n_0\,
I4 => rlast_sm_cs(1),
O => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00A4FFFF00A40000"
)
port map (
I0 => rlast_sm_cs(1),
I1 => p_0_in13_in,
I2 => rlast_sm_cs(0),
I3 => rlast_sm_cs(2),
I4 => \/i__n_0\,
I5 => rlast_sm_cs(2),
O => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_rlast_sm_cs[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst,
O => p_0_in13_in
);
\FSM_sequential_rlast_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[0]_i_1_n_0\,
Q => rlast_sm_cs(0),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[1]_i_1_n_0\,
Q => rlast_sm_cs(1),
R => \^bram_rst_a\
);
\FSM_sequential_rlast_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_rlast_sm_cs[2]_i_1_n_0\,
Q => rlast_sm_cs(2),
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_arready_int_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAEEE"
)
port map (
I0 => p_9_out,
I1 => axi_arready_int,
I2 => s_axi_arvalid,
I3 => axi_araddr_full,
I4 => araddr_pipe_ld43_out,
O => \GEN_ARREADY.axi_arready_int_i_1_n_0\
);
\GEN_ARREADY.axi_arready_int_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BAAA"
)
port map (
I0 => axi_aresetn_re_reg,
I1 => axi_early_arready_int,
I2 => axi_araddr_full,
I3 => bram_addr_ld_en,
O => p_9_out
);
\GEN_ARREADY.axi_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_ARREADY.axi_arready_int_i_1_n_0\,
Q => axi_arready_int,
R => \^bram_rst_a\
);
\GEN_ARREADY.axi_early_arready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000200"
)
port map (
I0 => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\,
I1 => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\,
I2 => rd_data_sm_cs(3),
I3 => brst_one,
I4 => axi_arready_int,
I5 => I_WRAP_BRST_n_26,
O => p_48_out
);
\GEN_ARREADY.axi_early_arready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00CC304400000044"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_ARREADY.axi_early_arready_int_i_2_n_0\
);
\GEN_ARREADY.axi_early_arready_int_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => axi_araddr_full,
I1 => s_axi_arvalid,
O => \GEN_ARREADY.axi_early_arready_int_i_3_n_0\
);
\GEN_ARREADY.axi_early_arready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_48_out,
Q => axi_early_arready_int,
R => \^bram_rst_a\
);
\GEN_AR_DUAL.ar_active_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"CDCDCDDDCCCCCCCC"
)
port map (
I0 => \GEN_AR_DUAL.ar_active_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => \GEN_AR_DUAL.ar_active_i_3_n_0\,
I3 => end_brst_rd,
I4 => brst_zero,
I5 => ar_active,
O => \GEN_AR_DUAL.ar_active_i_1_n_0\
);
\GEN_AR_DUAL.ar_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"808880808088A280"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_data_sm_cs(1),
I2 => \GEN_AR_DUAL.ar_active_i_4_n_0\,
I3 => rd_data_sm_cs(0),
I4 => axi_rd_burst_two_reg_n_0,
I5 => axi_rd_burst,
O => \GEN_AR_DUAL.ar_active_i_2_n_0\
);
\GEN_AR_DUAL.ar_active_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010000000000000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => \^s_axi_rvalid\,
I5 => s_axi_rready,
O => \GEN_AR_DUAL.ar_active_i_3_n_0\
);
\GEN_AR_DUAL.ar_active_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"8A88000000000000"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => brst_zero,
I2 => axi_b2b_brst,
I3 => end_brst_rd,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => \GEN_AR_DUAL.ar_active_i_4_n_0\
);
\GEN_AR_DUAL.ar_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.ar_active_i_1_n_0\,
Q => ar_active,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_DUAL.rd_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"10001000F0F01000"
)
port map (
I0 => rd_addr_sm_cs,
I1 => axi_araddr_full,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I4 => last_bram_addr,
I5 => I_WRAP_BRST_n_26,
O => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\
);
\GEN_AR_DUAL.rd_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_DUAL.rd_addr_sm_cs_i_1_n_0\,
Q => rd_addr_sm_cs,
R => \GEN_AWREADY.axi_aresetn_d2_reg\
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(8),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(9),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(10),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(11),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(12),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(13),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(0),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(1),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(2),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(3),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(4),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(5),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(6),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_araddr(7),
Q => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C08888CCCC8888"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => s_axi_aresetn,
I2 => s_axi_arvalid,
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I4 => axi_araddr_full,
I5 => bram_addr_ld_en,
O => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_araddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_araddr_full_i_1_n_0\,
Q => axi_araddr_full,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"03AA"
)
port map (
I0 => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
I1 => s_axi_arburst(0),
I2 => s_axi_arburst(1),
I3 => araddr_pipe_ld43_out,
O => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(0),
Q => axi_arburst_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arburst(1),
Q => axi_arburst_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(0),
Q => axi_arid_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(10),
Q => axi_arid_pipe(10),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(11),
Q => axi_arid_pipe(11),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(1),
Q => axi_arid_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(2),
Q => axi_arid_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(3),
Q => axi_arid_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(4),
Q => axi_arid_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(5),
Q => axi_arid_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(6),
Q => axi_arid_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(7),
Q => axi_arid_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(8),
Q => axi_arid_pipe(8),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arid(9),
Q => axi_arid_pipe(9),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"220022002A002200"
)
port map (
I0 => axi_aresetn_d2,
I1 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\,
I2 => rd_addr_sm_cs,
I3 => s_axi_arvalid,
I4 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\,
I5 => axi_araddr_full,
O => araddr_pipe_ld43_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => I_WRAP_BRST_n_26,
I1 => last_bram_addr,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => no_ar_ack,
I1 => pend_rd_op,
I2 => ar_active,
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe[7]_i_3_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_arlen(7),
I1 => s_axi_arlen(1),
I2 => s_axi_arlen(3),
I3 => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\,
O => p_13_out
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => s_axi_arlen(5),
I1 => s_axi_arlen(4),
I2 => s_axi_arlen(2),
I3 => s_axi_arlen(6),
O => \GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => p_13_out,
Q => axi_arlen_pipe_1_or_2,
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(0),
Q => axi_arlen_pipe(0),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(1),
Q => axi_arlen_pipe(1),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(2),
Q => axi_arlen_pipe(2),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(3),
Q => axi_arlen_pipe(3),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(4),
Q => axi_arlen_pipe(4),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(5),
Q => axi_arlen_pipe(5),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(6),
Q => axi_arlen_pipe(6),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => s_axi_arlen(7),
Q => axi_arlen_pipe(7),
R => '0'
);
\GEN_AR_PIPE_DUAL.axi_arsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => araddr_pipe_ld43_out,
D => '1',
Q => axi_arsize_pipe(1),
R => '0'
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000BAAA0000"
)
port map (
I0 => brst_cnt_max,
I1 => pend_rd_op,
I2 => ar_active,
I3 => brst_zero,
I4 => s_axi_aresetn,
I5 => bram_addr_ld_en,
O => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\
);
\GEN_BRST_MAX_WO_NARROW.brst_cnt_max_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_BRST_MAX_WO_NARROW.brst_cnt_max_i_1_n_0\,
Q => brst_cnt_max,
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^q\(4),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(3),
I5 => \^q\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => I_WRAP_BRST_n_23,
I3 => \^q\(5),
I4 => \^q\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_13,
Q => \^q\(8),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_12,
Q => \^q\(9),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_11,
Q => \^q\(10),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_10,
Q => \^q\(11),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_9,
Q => \^q\(12),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => I_WRAP_BRST_n_8,
Q => \^q\(13),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_21,
Q => \^q\(0),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_20,
Q => \^q\(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_19,
Q => \^q\(2),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_18,
Q => \^q\(3),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_17,
Q => \^q\(4),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_16,
Q => \^q\(5),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_15,
Q => \^q\(6),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_6,
D => I_WRAP_BRST_n_14,
Q => \^q\(7),
R => '0'
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(0),
I1 => bram_rddata_b(0),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[0].axi_rdata_int[0]_i_1_n_0\,
Q => s_axi_rdata(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(10),
I1 => bram_rddata_b(10),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[10].axi_rdata_int[10]_i_1_n_0\,
Q => s_axi_rdata(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(11),
I1 => bram_rddata_b(11),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[11].axi_rdata_int[11]_i_1_n_0\,
Q => s_axi_rdata(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(12),
I1 => bram_rddata_b(12),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[12].axi_rdata_int[12]_i_1_n_0\,
Q => s_axi_rdata(12),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(13),
I1 => bram_rddata_b(13),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[13].axi_rdata_int[13]_i_1_n_0\,
Q => s_axi_rdata(13),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(14),
I1 => bram_rddata_b(14),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[14].axi_rdata_int[14]_i_1_n_0\,
Q => s_axi_rdata(14),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(15),
I1 => bram_rddata_b(15),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[15].axi_rdata_int[15]_i_1_n_0\,
Q => s_axi_rdata(15),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(16),
I1 => bram_rddata_b(16),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[16].axi_rdata_int[16]_i_1_n_0\,
Q => s_axi_rdata(16),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(17),
I1 => bram_rddata_b(17),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[17].axi_rdata_int[17]_i_1_n_0\,
Q => s_axi_rdata(17),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(18),
I1 => bram_rddata_b(18),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[18].axi_rdata_int[18]_i_1_n_0\,
Q => s_axi_rdata(18),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(19),
I1 => bram_rddata_b(19),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[19].axi_rdata_int[19]_i_1_n_0\,
Q => s_axi_rdata(19),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(1),
I1 => bram_rddata_b(1),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[1].axi_rdata_int[1]_i_1_n_0\,
Q => s_axi_rdata(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(20),
I1 => bram_rddata_b(20),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[20].axi_rdata_int[20]_i_1_n_0\,
Q => s_axi_rdata(20),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(21),
I1 => bram_rddata_b(21),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[21].axi_rdata_int[21]_i_1_n_0\,
Q => s_axi_rdata(21),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(22),
I1 => bram_rddata_b(22),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[22].axi_rdata_int[22]_i_1_n_0\,
Q => s_axi_rdata(22),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(23),
I1 => bram_rddata_b(23),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[23].axi_rdata_int[23]_i_1_n_0\,
Q => s_axi_rdata(23),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(24),
I1 => bram_rddata_b(24),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[24].axi_rdata_int[24]_i_1_n_0\,
Q => s_axi_rdata(24),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(25),
I1 => bram_rddata_b(25),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[25].axi_rdata_int[25]_i_1_n_0\,
Q => s_axi_rdata(25),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(26),
I1 => bram_rddata_b(26),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[26].axi_rdata_int[26]_i_1_n_0\,
Q => s_axi_rdata(26),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(27),
I1 => bram_rddata_b(27),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[27].axi_rdata_int[27]_i_1_n_0\,
Q => s_axi_rdata(27),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(28),
I1 => bram_rddata_b(28),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[28].axi_rdata_int[28]_i_1_n_0\,
Q => s_axi_rdata(28),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(29),
I1 => bram_rddata_b(29),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[29].axi_rdata_int[29]_i_1_n_0\,
Q => s_axi_rdata(29),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(2),
I1 => bram_rddata_b(2),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[2].axi_rdata_int[2]_i_1_n_0\,
Q => s_axi_rdata(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(30),
I1 => bram_rddata_b(30),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[30].axi_rdata_int[30]_i_1_n_0\,
Q => s_axi_rdata(30),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"1414545410000404"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\,
I4 => rd_data_sm_cs(0),
I5 => rd_adv_buf67_out,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(31),
I1 => bram_rddata_b(31),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_3_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_2_n_0\,
Q => s_axi_rdata(31),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(3),
I1 => bram_rddata_b(3),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[3].axi_rdata_int[3]_i_1_n_0\,
Q => s_axi_rdata(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(4),
I1 => bram_rddata_b(4),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[4].axi_rdata_int[4]_i_1_n_0\,
Q => s_axi_rdata(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(5),
I1 => bram_rddata_b(5),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[5].axi_rdata_int[5]_i_1_n_0\,
Q => s_axi_rdata(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(6),
I1 => bram_rddata_b(6),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[6].axi_rdata_int[6]_i_1_n_0\,
Q => s_axi_rdata(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(7),
I1 => bram_rddata_b(7),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[7].axi_rdata_int[7]_i_1_n_0\,
Q => s_axi_rdata(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(8),
I1 => bram_rddata_b(8),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[8].axi_rdata_int[8]_i_1_n_0\,
Q => s_axi_rdata(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => rd_skid_buf(9),
I1 => bram_rddata_b(9),
I2 => rddata_mux_sel,
O => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RDATA_NO_ECC.GEN_RDATA[31].axi_rdata_int[31]_i_1_n_0\,
D => \GEN_RDATA_NO_ECC.GEN_RDATA[9].axi_rdata_int[9]_i_1_n_0\,
Q => s_axi_rdata(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RDATA_NO_ECC.rd_skid_buf[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAEAA"
)
port map (
I0 => rd_skid_buf_ld_reg,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(3),
O => rd_skid_buf_ld
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(0),
Q => rd_skid_buf(0),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(10),
Q => rd_skid_buf(10),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(11),
Q => rd_skid_buf(11),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(12),
Q => rd_skid_buf(12),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(13),
Q => rd_skid_buf(13),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(14),
Q => rd_skid_buf(14),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(15),
Q => rd_skid_buf(15),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(16),
Q => rd_skid_buf(16),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(17),
Q => rd_skid_buf(17),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(18),
Q => rd_skid_buf(18),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(19),
Q => rd_skid_buf(19),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(1),
Q => rd_skid_buf(1),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(20),
Q => rd_skid_buf(20),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(21),
Q => rd_skid_buf(21),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(22),
Q => rd_skid_buf(22),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(23),
Q => rd_skid_buf(23),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(24),
Q => rd_skid_buf(24),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(25),
Q => rd_skid_buf(25),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(26),
Q => rd_skid_buf(26),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(27),
Q => rd_skid_buf(27),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(28),
Q => rd_skid_buf(28),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(29),
Q => rd_skid_buf(29),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(2),
Q => rd_skid_buf(2),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(30),
Q => rd_skid_buf(30),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(31),
Q => rd_skid_buf(31),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(3),
Q => rd_skid_buf(3),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(4),
Q => rd_skid_buf(4),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(5),
Q => rd_skid_buf(5),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(6),
Q => rd_skid_buf(6),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(7),
Q => rd_skid_buf(7),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(8),
Q => rd_skid_buf(8),
R => \^bram_rst_a\
);
\GEN_RDATA_NO_ECC.rd_skid_buf_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => rd_skid_buf_ld,
D => bram_rddata_b(9),
Q => rd_skid_buf(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_int[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"08FF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rlast\,
I2 => axi_b2b_brst,
I3 => s_axi_aresetn,
O => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_rvalid_set,
I1 => s_axi_rready,
I2 => \^s_axi_rlast\,
I3 => axi_b2b_brst,
O => p_4_out
);
\GEN_RID.axi_rid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(0),
Q => s_axi_rid(0),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(10),
Q => s_axi_rid(10),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(11),
Q => s_axi_rid(11),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(1),
Q => s_axi_rid(1),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(2),
Q => s_axi_rid(2),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(3),
Q => s_axi_rid(3),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(4),
Q => s_axi_rid(4),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(5),
Q => s_axi_rid(5),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(6),
Q => s_axi_rid(6),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(7),
Q => s_axi_rid(7),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(8),
Q => s_axi_rid(8),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_4_out,
D => axi_rid_temp(9),
Q => s_axi_rid(9),
R => \GEN_RID.axi_rid_int[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp2[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
O => axi_rid_temp20_in(0)
);
\GEN_RID.axi_rid_temp2[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
O => axi_rid_temp20_in(10)
);
\GEN_RID.axi_rid_temp2[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => axi_rid_temp_full,
I1 => bram_addr_ld_en,
O => p_26_out
);
\GEN_RID.axi_rid_temp2[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
O => axi_rid_temp20_in(11)
);
\GEN_RID.axi_rid_temp2[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
O => axi_rid_temp20_in(1)
);
\GEN_RID.axi_rid_temp2[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
O => axi_rid_temp20_in(2)
);
\GEN_RID.axi_rid_temp2[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
O => axi_rid_temp20_in(3)
);
\GEN_RID.axi_rid_temp2[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
O => axi_rid_temp20_in(4)
);
\GEN_RID.axi_rid_temp2[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
O => axi_rid_temp20_in(5)
);
\GEN_RID.axi_rid_temp2[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
O => axi_rid_temp20_in(6)
);
\GEN_RID.axi_rid_temp2[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
O => axi_rid_temp20_in(7)
);
\GEN_RID.axi_rid_temp2[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
O => axi_rid_temp20_in(8)
);
\GEN_RID.axi_rid_temp2[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
O => axi_rid_temp20_in(9)
);
\GEN_RID.axi_rid_temp2_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"08080000C8C800C0"
)
port map (
I0 => bram_addr_ld_en,
I1 => s_axi_aresetn,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full_d1,
I4 => axi_rid_temp_full,
I5 => p_4_out,
O => \GEN_RID.axi_rid_temp2_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp2_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp2_full_i_1_n_0\,
Q => axi_rid_temp2_full,
R => '0'
);
\GEN_RID.axi_rid_temp2_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(0),
Q => axi_rid_temp2(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(10),
Q => axi_rid_temp2(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(11),
Q => axi_rid_temp2(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(1),
Q => axi_rid_temp2(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(2),
Q => axi_rid_temp2(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(3),
Q => axi_rid_temp2(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(4),
Q => axi_rid_temp2(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(5),
Q => axi_rid_temp2(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(6),
Q => axi_rid_temp2(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(7),
Q => axi_rid_temp2(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(8),
Q => axi_rid_temp2(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp2_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => p_26_out,
D => axi_rid_temp20_in(9),
Q => axi_rid_temp2(9),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(0),
I1 => axi_araddr_full,
I2 => s_axi_arid(0),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(0),
O => \GEN_RID.axi_rid_temp[0]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(10),
I1 => axi_araddr_full,
I2 => s_axi_arid(10),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(10),
O => \GEN_RID.axi_rid_temp[10]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A0FFA0E0"
)
port map (
I0 => p_4_out,
I1 => axi_rid_temp_full_d1,
I2 => axi_rid_temp2_full,
I3 => axi_rid_temp_full,
I4 => bram_addr_ld_en,
O => \GEN_RID.axi_rid_temp[11]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[11]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(11),
I1 => axi_araddr_full,
I2 => s_axi_arid(11),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(11),
O => \GEN_RID.axi_rid_temp[11]_i_2_n_0\
);
\GEN_RID.axi_rid_temp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arid(1),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(1),
O => \GEN_RID.axi_rid_temp[1]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(2),
I1 => axi_araddr_full,
I2 => s_axi_arid(2),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(2),
O => \GEN_RID.axi_rid_temp[2]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(3),
I1 => axi_araddr_full,
I2 => s_axi_arid(3),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(3),
O => \GEN_RID.axi_rid_temp[3]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arid(4),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(4),
O => \GEN_RID.axi_rid_temp[4]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arid(5),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(5),
O => \GEN_RID.axi_rid_temp[5]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arid(6),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(6),
O => \GEN_RID.axi_rid_temp[6]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arid(7),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(7),
O => \GEN_RID.axi_rid_temp[7]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(8),
I1 => axi_araddr_full,
I2 => s_axi_arid(8),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(8),
O => \GEN_RID.axi_rid_temp[8]_i_1_n_0\
);
\GEN_RID.axi_rid_temp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFB8FF0000B800"
)
port map (
I0 => axi_arid_pipe(9),
I1 => axi_araddr_full,
I2 => s_axi_arid(9),
I3 => bram_addr_ld_en,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2(9),
O => \GEN_RID.axi_rid_temp[9]_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rid_temp_full,
Q => axi_rid_temp_full_d1,
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_full_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0E000F0A0A0"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_rid_temp_full_d1,
I2 => s_axi_aresetn,
I3 => p_4_out,
I4 => axi_rid_temp_full,
I5 => axi_rid_temp2_full,
O => \GEN_RID.axi_rid_temp_full_i_1_n_0\
);
\GEN_RID.axi_rid_temp_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_RID.axi_rid_temp_full_i_1_n_0\,
Q => axi_rid_temp_full,
R => '0'
);
\GEN_RID.axi_rid_temp_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[0]_i_1_n_0\,
Q => axi_rid_temp(0),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[10]_i_1_n_0\,
Q => axi_rid_temp(10),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[11]_i_2_n_0\,
Q => axi_rid_temp(11),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[1]_i_1_n_0\,
Q => axi_rid_temp(1),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[2]_i_1_n_0\,
Q => axi_rid_temp(2),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[3]_i_1_n_0\,
Q => axi_rid_temp(3),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[4]_i_1_n_0\,
Q => axi_rid_temp(4),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[5]_i_1_n_0\,
Q => axi_rid_temp(5),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[6]_i_1_n_0\,
Q => axi_rid_temp(6),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[7]_i_1_n_0\,
Q => axi_rid_temp(7),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[8]_i_1_n_0\,
Q => axi_rid_temp(8),
R => \^bram_rst_a\
);
\GEN_RID.axi_rid_temp_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_RID.axi_rid_temp[11]_i_1_n_0\,
D => \GEN_RID.axi_rid_temp[9]_i_1_n_0\,
Q => axi_rid_temp(9),
R => \^bram_rst_a\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst_0
port map (
D(13) => I_WRAP_BRST_n_8,
D(12) => I_WRAP_BRST_n_9,
D(11) => I_WRAP_BRST_n_10,
D(10) => I_WRAP_BRST_n_11,
D(9) => I_WRAP_BRST_n_12,
D(8) => I_WRAP_BRST_n_13,
D(7) => I_WRAP_BRST_n_14,
D(6) => I_WRAP_BRST_n_15,
D(5) => I_WRAP_BRST_n_16,
D(4) => I_WRAP_BRST_n_17,
D(3) => I_WRAP_BRST_n_18,
D(2) => I_WRAP_BRST_n_19,
D(1) => I_WRAP_BRST_n_20,
D(0) => I_WRAP_BRST_n_21,
E(1) => bram_addr_ld_en_mod,
E(0) => I_WRAP_BRST_n_6,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[10].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[11].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[12].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[13].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[14].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[15].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[2].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[3].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[4].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[5].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[6].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[7].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[8].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\ => \GEN_AR_PIPE_DUAL.GEN_ARADDR[9].axi_araddr_pipe_reg\,
\GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg\ => \GEN_AR_PIPE_DUAL.axi_arburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\ => I_WRAP_BRST_n_7,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_0\ => I_WRAP_BRST_n_25,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]_1\(9 downto 0) => \^q\(9 downto 0),
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => I_WRAP_BRST_n_23,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_4_n_0\,
Q(3 downto 0) => axi_arlen_pipe(3 downto 0),
SR(0) => \^bram_rst_a\,
ar_active => ar_active,
axi_araddr_full => axi_araddr_full,
axi_aresetn_d2 => axi_aresetn_d2,
axi_arlen_pipe_1_or_2 => axi_arlen_pipe_1_or_2,
axi_arsize_pipe(0) => axi_arsize_pipe(1),
axi_arsize_pipe_max => axi_arsize_pipe_max,
axi_b2b_brst => axi_b2b_brst,
axi_b2b_brst_reg => I_WRAP_BRST_n_27,
axi_rd_burst => axi_rd_burst,
axi_rd_burst_two_reg => axi_rd_burst_two_reg_n_0,
axi_rvalid_int_reg => \^s_axi_rvalid\,
bram_addr_ld_en => bram_addr_ld_en,
brst_zero => brst_zero,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_wrap_burst_reg => curr_wrap_burst_reg,
disable_b2b_brst => disable_b2b_brst,
end_brst_rd => end_brst_rd,
last_bram_addr => last_bram_addr,
no_ar_ack => no_ar_ack,
pend_rd_op => pend_rd_op,
rd_addr_sm_cs => rd_addr_sm_cs,
rd_adv_buf67_out => rd_adv_buf67_out,
\rd_data_sm_cs_reg[1]\ => I_WRAP_BRST_n_24,
\rd_data_sm_cs_reg[3]\ => I_WRAP_BRST_n_28,
\rd_data_sm_cs_reg[3]_0\(3 downto 0) => rd_data_sm_cs(3 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_rready => s_axi_rready,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_26,
\wrap_burst_total_reg[0]_0\ => I_WRAP_BRST_n_1,
\wrap_burst_total_reg[0]_1\ => I_WRAP_BRST_n_2,
\wrap_burst_total_reg[0]_2\ => I_WRAP_BRST_n_3,
\wrap_burst_total_reg[0]_3\ => I_WRAP_BRST_n_4
);
act_rd_burst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"000000002EEE22E2"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_set,
I2 => bram_addr_ld_en,
I3 => axi_rd_burst_two,
I4 => axi_rd_burst,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_i_1_n_0
);
act_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"A8A8AAA8A8A8A8A8"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => act_rd_burst_i_4_n_0,
I2 => axi_b2b_brst_i_3_n_0,
I3 => \rd_data_sm_cs[2]_i_4_n_0\,
I4 => last_bram_addr_i_7_n_0,
I5 => bram_addr_ld_en,
O => act_rd_burst_set
);
act_rd_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"04000010FFFFFFFF"
)
port map (
I0 => \rd_data_sm_cs[3]_i_6_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => s_axi_aresetn,
O => act_rd_burst_i_3_n_0
);
act_rd_burst_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"4440"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
O => act_rd_burst_i_4_n_0
);
act_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_i_1_n_0,
Q => act_rd_burst,
R => '0'
);
act_rd_burst_two_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E2EEE222"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst_set,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => axi_rd_burst_two_reg_n_0,
I5 => act_rd_burst_i_3_n_0,
O => act_rd_burst_two_i_1_n_0
);
act_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => act_rd_burst_two_i_1_n_0,
Q => act_rd_burst_two,
R => '0'
);
axi_arsize_pipe_max_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => araddr_pipe_ld43_out,
I1 => axi_arsize_pipe_max,
O => axi_arsize_pipe_max_i_1_n_0
);
axi_arsize_pipe_max_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_arsize_pipe_max_i_1_n_0,
Q => axi_arsize_pipe_max,
R => \^bram_rst_a\
);
axi_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CC0CCC55CC0CCCCC"
)
port map (
I0 => I_WRAP_BRST_n_27,
I1 => axi_b2b_brst,
I2 => disable_b2b_brst_i_2_n_0,
I3 => rd_data_sm_cs(3),
I4 => rd_data_sm_cs(2),
I5 => axi_b2b_brst_i_3_n_0,
O => axi_b2b_brst_i_1_n_0
);
axi_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000088880080"
)
port map (
I0 => \rd_data_sm_cs[0]_i_3_n_0\,
I1 => rd_adv_buf67_out,
I2 => end_brst_rd,
I3 => axi_b2b_brst,
I4 => brst_zero,
I5 => I_WRAP_BRST_n_27,
O => axi_b2b_brst_i_3_n_0
);
axi_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_b2b_brst_i_1_n_0,
Q => axi_b2b_brst,
R => \^bram_rst_a\
);
axi_rd_burst_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"303000A0"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_i_2_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_i_1_n_0
);
axi_rd_burst_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000004"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => axi_rd_burst_i_3_n_0,
I2 => I_WRAP_BRST_n_3,
I3 => \brst_cnt[7]_i_3_n_0\,
I4 => I_WRAP_BRST_n_2,
I5 => I_WRAP_BRST_n_1,
O => axi_rd_burst_i_2_n_0
);
axi_rd_burst_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arlen(5),
I1 => axi_arlen_pipe(5),
I2 => s_axi_arlen(4),
I3 => axi_araddr_full,
I4 => axi_arlen_pipe(4),
O => axi_rd_burst_i_3_n_0
);
axi_rd_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_i_1_n_0,
Q => axi_rd_burst,
R => '0'
);
axi_rd_burst_two_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"C0C000A0"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => axi_rd_burst_two,
I2 => s_axi_aresetn,
I3 => brst_zero,
I4 => bram_addr_ld_en,
O => axi_rd_burst_two_i_1_n_0
);
axi_rd_burst_two_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"A808"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => axi_rd_burst_two
);
axi_rd_burst_two_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rd_burst_two_i_1_n_0,
Q => axi_rd_burst_two_reg_n_0,
R => '0'
);
axi_rlast_int_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"88A8"
)
port map (
I0 => s_axi_aresetn,
I1 => axi_rlast_set,
I2 => \^s_axi_rlast\,
I3 => s_axi_rready,
O => axi_rlast_int_i_1_n_0
);
axi_rlast_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rlast_int_i_1_n_0,
Q => \^s_axi_rlast\,
R => '0'
);
axi_rvalid_clr_ok_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FFFFEEEA"
)
port map (
I0 => axi_rvalid_clr_ok,
I1 => last_bram_addr,
I2 => disable_b2b_brst,
I3 => disable_b2b_brst_cmb,
I4 => axi_rvalid_clr_ok_i_2_n_0,
I5 => axi_rvalid_clr_ok_i_3_n_0,
O => axi_rvalid_clr_ok_i_1_n_0
);
axi_rvalid_clr_ok_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAABAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => axi_rvalid_clr_ok_i_2_n_0
);
axi_rvalid_clr_ok_i_3: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => I_WRAP_BRST_n_26,
I1 => bram_addr_ld_en,
I2 => s_axi_aresetn,
O => axi_rvalid_clr_ok_i_3_n_0
);
axi_rvalid_clr_ok_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_clr_ok_i_1_n_0,
Q => axi_rvalid_clr_ok,
R => '0'
);
axi_rvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00E0E0E0E0E0E0E0"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => axi_rvalid_set,
I2 => s_axi_aresetn,
I3 => axi_rvalid_clr_ok,
I4 => \^s_axi_rlast\,
I5 => s_axi_rready,
O => axi_rvalid_int_i_1_n_0
);
axi_rvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_int_i_1_n_0,
Q => \^s_axi_rvalid\,
R => '0'
);
axi_rvalid_set_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"0100"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
O => axi_rvalid_set_cmb
);
axi_rvalid_set_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_rvalid_set_cmb,
Q => axi_rvalid_set,
R => \^bram_rst_a\
);
bram_en_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEFFFEEEEE000E"
)
port map (
I0 => bram_en_int_i_2_n_0,
I1 => bram_en_int_i_3_n_0,
I2 => bram_en_int_i_4_n_0,
I3 => I_WRAP_BRST_n_28,
I4 => bram_en_int_i_6_n_0,
I5 => \^bram_en_b\,
O => bram_en_int_i_1_n_0
);
bram_en_int_i_10: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF777FFFFFFFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => act_rd_burst,
I3 => act_rd_burst_two,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_10_n_0
);
bram_en_int_i_11: unisim.vcomponents.LUT6
generic map(
INIT => X"D0D000F0D0D0F0F0"
)
port map (
I0 => \rd_data_sm_cs[3]_i_7_n_0\,
I1 => I_WRAP_BRST_n_27,
I2 => rd_data_sm_cs(1),
I3 => brst_one,
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => bram_en_int_i_11_n_0
);
bram_en_int_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FDF50000"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(1),
I5 => bram_en_int_i_7_n_0,
O => bram_en_int_i_2_n_0
);
bram_en_int_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAEEAFAAAAAAEE"
)
port map (
I0 => I_WRAP_BRST_n_25,
I1 => bram_addr_ld_en,
I2 => p_0_in13_in,
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_3_n_0
);
bram_en_int_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"000F007F0000007F"
)
port map (
I0 => pend_rd_op,
I1 => rd_adv_buf67_out,
I2 => \rd_data_sm_cs[0]_i_3_n_0\,
I3 => bram_en_int_i_9_n_0,
I4 => bram_addr_ld_en,
I5 => bram_en_int_i_10_n_0,
O => bram_en_int_i_4_n_0
);
bram_en_int_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"1010111111111110"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(3),
I2 => bram_en_int_i_11_n_0,
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(1),
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_6_n_0
);
bram_en_int_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"5500050544444444"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => axi_rd_burst_two_reg_n_0,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => \rd_data_sm_cs[3]_i_7_n_0\,
I4 => rd_adv_buf67_out,
I5 => rd_data_sm_cs(0),
O => bram_en_int_i_7_n_0
);
bram_en_int_i_9: unisim.vcomponents.LUT6
generic map(
INIT => X"1111111111111000"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
I2 => \^s_axi_rvalid\,
I3 => s_axi_rready,
I4 => brst_zero,
I5 => end_brst_rd,
O => bram_en_int_i_9_n_0
);
bram_en_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_int_i_1_n_0,
Q => \^bram_en_b\,
R => \^bram_rst_a\
);
\brst_cnt[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"D1DDD111"
)
port map (
I0 => brst_cnt(0),
I1 => bram_addr_ld_en,
I2 => axi_arlen_pipe(0),
I3 => axi_araddr_full,
I4 => s_axi_arlen(0),
O => \brst_cnt[0]_i_1_n_0\
);
\brst_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8FFB800B800B8FF"
)
port map (
I0 => axi_arlen_pipe(1),
I1 => axi_araddr_full,
I2 => s_axi_arlen(1),
I3 => bram_addr_ld_en,
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[1]_i_1_n_0\
);
\brst_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_1,
I1 => bram_addr_ld_en,
I2 => brst_cnt(2),
I3 => brst_cnt(1),
I4 => brst_cnt(0),
O => \brst_cnt[2]_i_1_n_0\
);
\brst_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B8B8B8B8B88B"
)
port map (
I0 => I_WRAP_BRST_n_2,
I1 => bram_addr_ld_en,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(0),
I5 => brst_cnt(1),
O => \brst_cnt[3]_i_1_n_0\
);
\brst_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(4),
I1 => axi_araddr_full,
I2 => s_axi_arlen(4),
I3 => bram_addr_ld_en,
I4 => brst_cnt(4),
I5 => \brst_cnt[4]_i_2_n_0\,
O => \brst_cnt[4]_i_1_n_0\
);
\brst_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => brst_cnt(2),
I1 => brst_cnt(0),
I2 => brst_cnt(1),
I3 => brst_cnt(3),
O => \brst_cnt[4]_i_2_n_0\
);
\brst_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B800B8FFB8FFB800"
)
port map (
I0 => axi_arlen_pipe(5),
I1 => axi_araddr_full,
I2 => s_axi_arlen(5),
I3 => bram_addr_ld_en,
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[5]_i_1_n_0\
);
\brst_cnt[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B88BB8B8"
)
port map (
I0 => \brst_cnt[6]_i_2_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(6),
I3 => brst_cnt(5),
I4 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[6]_i_1_n_0\
);
\brst_cnt[6]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(6),
I1 => axi_araddr_full,
I2 => s_axi_arlen(6),
O => \brst_cnt[6]_i_2_n_0\
);
\brst_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_7,
O => \brst_cnt[7]_i_1_n_0\
);
\brst_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8B8B88BB8B8B8B8"
)
port map (
I0 => \brst_cnt[7]_i_3_n_0\,
I1 => bram_addr_ld_en,
I2 => brst_cnt(7),
I3 => brst_cnt(6),
I4 => brst_cnt(5),
I5 => \brst_cnt[7]_i_4_n_0\,
O => \brst_cnt[7]_i_2_n_0\
);
\brst_cnt[7]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_arlen_pipe(7),
I1 => axi_araddr_full,
I2 => s_axi_arlen(7),
O => \brst_cnt[7]_i_3_n_0\
);
\brst_cnt[7]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => brst_cnt(3),
I1 => brst_cnt(1),
I2 => brst_cnt(0),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
O => \brst_cnt[7]_i_4_n_0\
);
brst_cnt_max_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_cnt_max,
Q => brst_cnt_max_d1,
R => \^bram_rst_a\
);
\brst_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[0]_i_1_n_0\,
Q => brst_cnt(0),
R => \^bram_rst_a\
);
\brst_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[1]_i_1_n_0\,
Q => brst_cnt(1),
R => \^bram_rst_a\
);
\brst_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[2]_i_1_n_0\,
Q => brst_cnt(2),
R => \^bram_rst_a\
);
\brst_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[3]_i_1_n_0\,
Q => brst_cnt(3),
R => \^bram_rst_a\
);
\brst_cnt_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[4]_i_1_n_0\,
Q => brst_cnt(4),
R => \^bram_rst_a\
);
\brst_cnt_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[5]_i_1_n_0\,
Q => brst_cnt(5),
R => \^bram_rst_a\
);
\brst_cnt_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[6]_i_1_n_0\,
Q => brst_cnt(6),
R => \^bram_rst_a\
);
\brst_cnt_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \brst_cnt[7]_i_1_n_0\,
D => \brst_cnt[7]_i_2_n_0\,
Q => brst_cnt(7),
R => \^bram_rst_a\
);
brst_one_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000E0EE0000"
)
port map (
I0 => brst_one,
I1 => brst_one0,
I2 => axi_rd_burst_two,
I3 => bram_addr_ld_en,
I4 => s_axi_aresetn,
I5 => last_bram_addr_i_6_n_0,
O => brst_one_i_1_n_0
);
brst_one_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"80FF808080808080"
)
port map (
I0 => bram_addr_ld_en,
I1 => I_WRAP_BRST_n_4,
I2 => axi_rd_burst_i_2_n_0,
I3 => brst_cnt(0),
I4 => brst_cnt(1),
I5 => last_bram_addr_i_8_n_0,
O => brst_one0
);
brst_one_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_one_i_1_n_0,
Q => brst_one,
R => '0'
);
brst_zero_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"00E0"
)
port map (
I0 => brst_zero,
I1 => last_bram_addr_i_6_n_0,
I2 => s_axi_aresetn,
I3 => brst_zero_i_2_n_0,
O => brst_zero_i_1_n_0
);
brst_zero_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8A80AAAA"
)
port map (
I0 => bram_addr_ld_en,
I1 => axi_arlen_pipe(0),
I2 => axi_araddr_full,
I3 => s_axi_arlen(0),
I4 => axi_rd_burst_i_2_n_0,
O => brst_zero_i_2_n_0
);
brst_zero_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => brst_zero_i_1_n_0,
Q => brst_zero,
R => '0'
);
curr_fixed_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_arburst(0),
I1 => axi_arburst_pipe(0),
I2 => s_axi_arburst(1),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(1),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_fixed_burst,
Q => curr_fixed_burst_reg,
R => \^bram_rst_a\
);
curr_wrap_burst_reg_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_arburst(1),
I1 => axi_arburst_pipe(1),
I2 => s_axi_arburst(0),
I3 => axi_araddr_full,
I4 => axi_arburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_wrap_burst,
Q => curr_wrap_burst_reg,
R => \^bram_rst_a\
);
disable_b2b_brst_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF000D0000"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(3),
I4 => disable_b2b_brst_i_2_n_0,
I5 => disable_b2b_brst_i_3_n_0,
O => disable_b2b_brst_cmb
);
disable_b2b_brst_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(1),
O => disable_b2b_brst_i_2_n_0
);
disable_b2b_brst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F6EF0000F6EFF6EF"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(3),
I3 => rd_data_sm_cs(0),
I4 => disable_b2b_brst,
I5 => disable_b2b_brst_i_4_n_0,
O => disable_b2b_brst_i_3_n_0
);
disable_b2b_brst_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"DFDFDFDFDFDFDFFF"
)
port map (
I0 => pend_rd_op_i_6_n_0,
I1 => rd_adv_buf67_out,
I2 => rd_data_sm_cs(0),
I3 => brst_zero,
I4 => end_brst_rd,
I5 => brst_one,
O => disable_b2b_brst_i_4_n_0
);
disable_b2b_brst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => disable_b2b_brst_cmb,
Q => disable_b2b_brst,
R => \^bram_rst_a\
);
end_brst_rd_clr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFEFEFF10100000"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => bram_addr_ld_en,
I4 => rd_data_sm_cs(0),
I5 => end_brst_rd_clr,
O => end_brst_rd_clr_i_1_n_0
);
end_brst_rd_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_clr_i_1_n_0,
Q => end_brst_rd_clr,
R => \^bram_rst_a\
);
end_brst_rd_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"0020F020"
)
port map (
I0 => brst_cnt_max,
I1 => brst_cnt_max_d1,
I2 => s_axi_aresetn,
I3 => end_brst_rd,
I4 => end_brst_rd_clr,
O => end_brst_rd_i_1_n_0
);
end_brst_rd_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => end_brst_rd_i_1_n_0,
Q => end_brst_rd,
R => '0'
);
last_bram_addr_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF1F110000"
)
port map (
I0 => last_bram_addr_i_2_n_0,
I1 => rd_data_sm_cs(2),
I2 => last_bram_addr_i_3_n_0,
I3 => last_bram_addr_i_4_n_0,
I4 => last_bram_addr_i_5_n_0,
I5 => last_bram_addr_i_6_n_0,
O => last_bram_addr0
);
last_bram_addr_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"EF00EFFFEFFFEFFF"
)
port map (
I0 => axi_rd_burst,
I1 => axi_rd_burst_two_reg_n_0,
I2 => rd_adv_buf67_out,
I3 => rd_data_sm_cs(3),
I4 => bram_addr_ld_en,
I5 => last_bram_addr_i_7_n_0,
O => last_bram_addr_i_2_n_0
);
last_bram_addr_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"DDDDDDDDFFFCFFFF"
)
port map (
I0 => last_bram_addr_i_7_n_0,
I1 => I_WRAP_BRST_n_28,
I2 => axi_rd_burst,
I3 => axi_rd_burst_two_reg_n_0,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => last_bram_addr_i_3_n_0
);
last_bram_addr_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"8880"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => bram_addr_ld_en,
I3 => pend_rd_op,
O => last_bram_addr_i_4_n_0
);
last_bram_addr_i_5: unisim.vcomponents.LUT3
generic map(
INIT => X"81"
)
port map (
I0 => rd_data_sm_cs(2),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
O => last_bram_addr_i_5_n_0
);
last_bram_addr_i_6: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => last_bram_addr_i_8_n_0,
I1 => brst_cnt(0),
I2 => brst_cnt(1),
O => last_bram_addr_i_6_n_0
);
last_bram_addr_i_7: unisim.vcomponents.LUT4
generic map(
INIT => X"02A2"
)
port map (
I0 => axi_rd_burst_i_2_n_0,
I1 => s_axi_arlen(0),
I2 => axi_araddr_full,
I3 => axi_arlen_pipe(0),
O => last_bram_addr_i_7_n_0
);
last_bram_addr_i_8: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => I_WRAP_BRST_n_7,
I1 => last_bram_addr_i_9_n_0,
I2 => brst_cnt(3),
I3 => brst_cnt(2),
I4 => brst_cnt(4),
I5 => brst_cnt(7),
O => last_bram_addr_i_8_n_0
);
last_bram_addr_i_9: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => brst_cnt(6),
I1 => brst_cnt(5),
O => last_bram_addr_i_9_n_0
);
last_bram_addr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => last_bram_addr0,
Q => last_bram_addr,
R => \^bram_rst_a\
);
no_ar_ack_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAA88C8AAAA"
)
port map (
I0 => no_ar_ack,
I1 => rd_data_sm_cs(1),
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_28,
O => no_ar_ack_i_1_n_0
);
no_ar_ack_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => no_ar_ack_i_1_n_0,
Q => no_ar_ack,
R => \^bram_rst_a\
);
pend_rd_op_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EFAAEFEF20AA2020"
)
port map (
I0 => pend_rd_op_i_2_n_0,
I1 => pend_rd_op_i_3_n_0,
I2 => pend_rd_op_i_4_n_0,
I3 => pend_rd_op_i_5_n_0,
I4 => pend_rd_op_i_6_n_0,
I5 => pend_rd_op,
O => pend_rd_op_i_1_n_0
);
pend_rd_op_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0FFCC8C80CCCC8C8"
)
port map (
I0 => p_0_in13_in,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => pend_rd_op_i_7_n_0,
O => pend_rd_op_i_2_n_0
);
pend_rd_op_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00030005"
)
port map (
I0 => pend_rd_op_i_8_n_0,
I1 => pend_rd_op_i_7_n_0,
I2 => bram_addr_ld_en,
I3 => rd_data_sm_cs(1),
I4 => rd_data_sm_cs(0),
I5 => I_WRAP_BRST_n_28,
O => pend_rd_op_i_3_n_0
);
pend_rd_op_i_4: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF00EA"
)
port map (
I0 => bram_addr_ld_en,
I1 => end_brst_rd,
I2 => ar_active,
I3 => rd_data_sm_cs(0),
I4 => pend_rd_op_i_9_n_0,
O => pend_rd_op_i_4_n_0
);
pend_rd_op_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0303070733F3FFFF"
)
port map (
I0 => p_0_in13_in,
I1 => rd_data_sm_cs(0),
I2 => rd_data_sm_cs(1),
I3 => \^s_axi_rlast\,
I4 => pend_rd_op,
I5 => bram_addr_ld_en,
O => pend_rd_op_i_5_n_0
);
pend_rd_op_i_6: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
O => pend_rd_op_i_6_n_0
);
pend_rd_op_i_7: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => ar_active,
I1 => end_brst_rd,
O => pend_rd_op_i_7_n_0
);
pend_rd_op_i_8: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => pend_rd_op,
I1 => \^s_axi_rlast\,
O => pend_rd_op_i_8_n_0
);
pend_rd_op_i_9: unisim.vcomponents.LUT5
generic map(
INIT => X"8000FFFF"
)
port map (
I0 => pend_rd_op,
I1 => s_axi_rready,
I2 => \^s_axi_rvalid\,
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
O => pend_rd_op_i_9_n_0
);
pend_rd_op_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => pend_rd_op_i_1_n_0,
Q => pend_rd_op,
R => \^bram_rst_a\
);
\rd_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF54005555"
)
port map (
I0 => \rd_data_sm_cs[0]_i_2_n_0\,
I1 => pend_rd_op,
I2 => bram_addr_ld_en,
I3 => rd_adv_buf67_out,
I4 => \rd_data_sm_cs[0]_i_3_n_0\,
I5 => \rd_data_sm_cs[0]_i_4_n_0\,
O => \rd_data_sm_cs[0]_i_1_n_0\
);
\rd_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAAAAAFEAAFEAA"
)
port map (
I0 => I_WRAP_BRST_n_28,
I1 => act_rd_burst_two,
I2 => act_rd_burst,
I3 => disable_b2b_brst_i_2_n_0,
I4 => bram_addr_ld_en,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[0]_i_2_n_0\
);
\rd_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[0]_i_3_n_0\
);
\rd_data_sm_cs[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"000300BF0003008F"
)
port map (
I0 => rd_adv_buf67_out,
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(3),
I5 => p_0_in13_in,
O => \rd_data_sm_cs[0]_i_4_n_0\
);
\rd_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABAAABAFFFFAABA"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => I_WRAP_BRST_n_28,
I2 => \rd_data_sm_cs[2]_i_5_n_0\,
I3 => rd_data_sm_cs(0),
I4 => I_WRAP_BRST_n_24,
I5 => \rd_data_sm_cs[1]_i_3_n_0\,
O => \rd_data_sm_cs[1]_i_1_n_0\
);
\rd_data_sm_cs[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"C0CCCCCC88888888"
)
port map (
I0 => axi_rd_burst_two_reg_n_0,
I1 => rd_data_sm_cs(1),
I2 => I_WRAP_BRST_n_27,
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
I5 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[1]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAABAAABAEAFAAAB"
)
port map (
I0 => \rd_data_sm_cs[2]_i_2_n_0\,
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(3),
I3 => \rd_data_sm_cs[2]_i_3_n_0\,
I4 => \rd_data_sm_cs[2]_i_4_n_0\,
I5 => \rd_data_sm_cs[2]_i_5_n_0\,
O => \rd_data_sm_cs[2]_i_1_n_0\
);
\rd_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000DF00000"
)
port map (
I0 => bram_addr_ld_en,
I1 => \rd_data_sm_cs[3]_i_6_n_0\,
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(2),
I5 => rd_data_sm_cs(3),
O => \rd_data_sm_cs[2]_i_2_n_0\
);
\rd_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00C0FFFF33F3BBBB"
)
port map (
I0 => axi_rd_burst,
I1 => rd_data_sm_cs(0),
I2 => rd_adv_buf67_out,
I3 => I_WRAP_BRST_n_27,
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => \rd_data_sm_cs[2]_i_3_n_0\
);
\rd_data_sm_cs[2]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[2]_i_4_n_0\
);
\rd_data_sm_cs[2]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => brst_zero,
I1 => end_brst_rd,
O => \rd_data_sm_cs[2]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8F80FF8F8F80F080"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \rd_data_sm_cs[3]_i_3_n_0\,
I3 => bram_addr_ld_en,
I4 => \rd_data_sm_cs[3]_i_4_n_0\,
I5 => \rd_data_sm_cs[3]_i_5_n_0\,
O => rd_data_sm_ns
);
\rd_data_sm_cs[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000004050005040"
)
port map (
I0 => I_WRAP_BRST_n_28,
I1 => bram_addr_ld_en,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => \rd_data_sm_cs[3]_i_6_n_0\,
I5 => rd_adv_buf67_out,
O => \rd_data_sm_cs[3]_i_2_n_0\
);
\rd_data_sm_cs[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4052"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(1),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_3_n_0\
);
\rd_data_sm_cs[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0035"
)
port map (
I0 => rd_data_sm_cs(1),
I1 => rd_data_sm_cs(3),
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
O => \rd_data_sm_cs[3]_i_4_n_0\
);
\rd_data_sm_cs[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF5EFFFF"
)
port map (
I0 => rd_data_sm_cs(0),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(1),
I3 => rd_data_sm_cs(3),
I4 => rd_adv_buf67_out,
I5 => \rd_data_sm_cs[3]_i_7_n_0\,
O => \rd_data_sm_cs[3]_i_5_n_0\
);
\rd_data_sm_cs[3]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"1FFF"
)
port map (
I0 => act_rd_burst_two,
I1 => act_rd_burst,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \rd_data_sm_cs[3]_i_6_n_0\
);
\rd_data_sm_cs[3]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => brst_zero,
I1 => axi_b2b_brst,
I2 => end_brst_rd,
O => \rd_data_sm_cs[3]_i_7_n_0\
);
\rd_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[0]_i_1_n_0\,
Q => rd_data_sm_cs(0),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[1]_i_1_n_0\,
Q => rd_data_sm_cs(1),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[2]_i_1_n_0\,
Q => rd_data_sm_cs(2),
R => \^bram_rst_a\
);
\rd_data_sm_cs_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => rd_data_sm_ns,
D => \rd_data_sm_cs[3]_i_2_n_0\,
Q => rd_data_sm_cs(3),
R => \^bram_rst_a\
);
rd_skid_buf_ld_reg_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1110011001100110"
)
port map (
I0 => rd_data_sm_cs(3),
I1 => rd_data_sm_cs(2),
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(1),
I4 => s_axi_rready,
I5 => \^s_axi_rvalid\,
O => rd_skid_buf_ld_cmb
);
rd_skid_buf_ld_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rd_skid_buf_ld_cmb,
Q => rd_skid_buf_ld_reg,
R => \^bram_rst_a\
);
rddata_mux_sel_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FE02"
)
port map (
I0 => rddata_mux_sel_cmb,
I1 => rd_data_sm_cs(3),
I2 => rddata_mux_sel_i_3_n_0,
I3 => rddata_mux_sel,
O => rddata_mux_sel_i_1_n_0
);
rddata_mux_sel_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F010F00F00F000"
)
port map (
I0 => act_rd_burst,
I1 => act_rd_burst_two,
I2 => rd_data_sm_cs(2),
I3 => rd_data_sm_cs(0),
I4 => rd_data_sm_cs(1),
I5 => rd_adv_buf67_out,
O => rddata_mux_sel_cmb
);
rddata_mux_sel_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"F700070FF70F070F"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => rd_data_sm_cs(0),
I3 => rd_data_sm_cs(2),
I4 => rd_data_sm_cs(1),
I5 => axi_rd_burst_two_reg_n_0,
O => rddata_mux_sel_i_3_n_0
);
rddata_mux_sel_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => rddata_mux_sel_i_1_n_0,
Q => rddata_mux_sel,
R => \^bram_rst_a\
);
s_axi_arready_INST_0: unisim.vcomponents.LUT4
generic map(
INIT => X"EAAA"
)
port map (
I0 => axi_arready_int,
I1 => \^s_axi_rvalid\,
I2 => s_axi_rready,
I3 => axi_early_arready_int,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
port (
axi_aresetn_d2 : out STD_LOGIC;
axi_aresetn_re_reg : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\GEN_AW_DUAL.aw_active_reg_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_aresetn : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl is
signal BID_FIFO_n_0 : STD_LOGIC;
signal BID_FIFO_n_10 : STD_LOGIC;
signal BID_FIFO_n_11 : STD_LOGIC;
signal BID_FIFO_n_12 : STD_LOGIC;
signal BID_FIFO_n_13 : STD_LOGIC;
signal BID_FIFO_n_14 : STD_LOGIC;
signal BID_FIFO_n_15 : STD_LOGIC;
signal BID_FIFO_n_3 : STD_LOGIC;
signal BID_FIFO_n_4 : STD_LOGIC;
signal BID_FIFO_n_5 : STD_LOGIC;
signal BID_FIFO_n_6 : STD_LOGIC;
signal BID_FIFO_n_7 : STD_LOGIC;
signal BID_FIFO_n_8 : STD_LOGIC;
signal BID_FIFO_n_9 : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\ : STD_LOGIC;
signal \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_1_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_AWREADY.axi_awready_int_i_3_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.aw_active_i_2_n_0\ : STD_LOGIC;
signal \^gen_aw_dual.aw_active_reg_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\ : STD_LOGIC;
signal \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\ : STD_LOGIC;
signal \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\ : STD_LOGIC;
signal \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\ : STD_LOGIC;
signal \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\ : STD_LOGIC;
signal \I_RD_CHNL/axi_aresetn_d1\ : STD_LOGIC;
signal I_WRAP_BRST_n_0 : STD_LOGIC;
signal I_WRAP_BRST_n_10 : STD_LOGIC;
signal I_WRAP_BRST_n_11 : STD_LOGIC;
signal I_WRAP_BRST_n_12 : STD_LOGIC;
signal I_WRAP_BRST_n_13 : STD_LOGIC;
signal I_WRAP_BRST_n_14 : STD_LOGIC;
signal I_WRAP_BRST_n_15 : STD_LOGIC;
signal I_WRAP_BRST_n_16 : STD_LOGIC;
signal I_WRAP_BRST_n_17 : STD_LOGIC;
signal I_WRAP_BRST_n_19 : STD_LOGIC;
signal I_WRAP_BRST_n_2 : STD_LOGIC;
signal I_WRAP_BRST_n_20 : STD_LOGIC;
signal I_WRAP_BRST_n_21 : STD_LOGIC;
signal I_WRAP_BRST_n_22 : STD_LOGIC;
signal I_WRAP_BRST_n_23 : STD_LOGIC;
signal I_WRAP_BRST_n_7 : STD_LOGIC;
signal I_WRAP_BRST_n_8 : STD_LOGIC;
signal I_WRAP_BRST_n_9 : STD_LOGIC;
signal aw_active : STD_LOGIC;
signal \^axi_aresetn_d2\ : STD_LOGIC;
signal axi_aresetn_re : STD_LOGIC;
signal \^axi_aresetn_re_reg\ : STD_LOGIC;
signal axi_awaddr_full : STD_LOGIC;
signal axi_awburst_pipe : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_awid_pipe : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_awlen_pipe : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_awlen_pipe_1_or_2 : STD_LOGIC;
signal axi_awsize_pipe : STD_LOGIC_VECTOR ( 1 to 1 );
signal axi_bvalid_int_i_1_n_0 : STD_LOGIC;
signal axi_wdata_full_cmb : STD_LOGIC;
signal axi_wdata_full_cmb114_out : STD_LOGIC;
signal axi_wdata_full_reg : STD_LOGIC;
signal axi_wr_burst : STD_LOGIC;
signal axi_wr_burst_cmb : STD_LOGIC;
signal axi_wr_burst_cmb0 : STD_LOGIC;
signal axi_wr_burst_i_1_n_0 : STD_LOGIC;
signal axi_wr_burst_i_3_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_1_n_0 : STD_LOGIC;
signal axi_wready_int_mod_i_3_n_0 : STD_LOGIC;
signal bid_gets_fifo_load : STD_LOGIC;
signal bid_gets_fifo_load_d1 : STD_LOGIC;
signal bid_gets_fifo_load_d1_i_2_n_0 : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 13 downto 0 );
signal bram_addr_inc : STD_LOGIC;
signal bram_addr_ld : STD_LOGIC_VECTOR ( 13 downto 10 );
signal bram_addr_ld_en : STD_LOGIC;
signal bram_addr_ld_en_mod : STD_LOGIC;
signal bram_addr_rst_cmb : STD_LOGIC;
signal bram_en_cmb : STD_LOGIC;
signal bvalid_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \bvalid_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \bvalid_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal bvalid_cnt_inc : STD_LOGIC;
signal bvalid_cnt_inc11_out : STD_LOGIC;
signal clr_bram_we : STD_LOGIC;
signal clr_bram_we_cmb : STD_LOGIC;
signal curr_awlen_reg_1_or_2 : STD_LOGIC;
signal curr_awlen_reg_1_or_20 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_2_n_0 : STD_LOGIC;
signal curr_awlen_reg_1_or_2_i_3_n_0 : STD_LOGIC;
signal curr_fixed_burst : STD_LOGIC;
signal curr_fixed_burst_reg : STD_LOGIC;
signal curr_wrap_burst : STD_LOGIC;
signal curr_wrap_burst_reg : STD_LOGIC;
signal delay_aw_active_clr : STD_LOGIC;
signal last_data_ack_mod : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_9_out : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal wr_addr_sm_cs : STD_LOGIC;
signal wr_data_sm_cs : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute RTL_KEEP : string;
attribute RTL_KEEP of wr_data_sm_cs : signal is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\ : label is "soft_lutpair65";
attribute KEEP : string;
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\ : label is "yes";
attribute KEEP of \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\ : label is "yes";
attribute SOFT_HLUTNM of \GEN_AW_DUAL.last_data_ack_mod_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of bid_gets_fifo_load_d1_i_2 : label is "soft_lutpair63";
attribute SOFT_HLUTNM of curr_fixed_burst_reg_i_2 : label is "soft_lutpair62";
attribute SOFT_HLUTNM of curr_wrap_burst_reg_i_2 : label is "soft_lutpair62";
begin
\GEN_AW_DUAL.aw_active_reg_0\ <= \^gen_aw_dual.aw_active_reg_0\;
axi_aresetn_d2 <= \^axi_aresetn_d2\;
axi_aresetn_re_reg <= \^axi_aresetn_re_reg\;
bram_addr_a(13 downto 0) <= \^bram_addr_a\(13 downto 0);
s_axi_awready <= \^s_axi_awready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_wready <= \^s_axi_wready\;
BID_FIFO: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_SRL_FIFO
port map (
D(11) => BID_FIFO_n_4,
D(10) => BID_FIFO_n_5,
D(9) => BID_FIFO_n_6,
D(8) => BID_FIFO_n_7,
D(7) => BID_FIFO_n_8,
D(6) => BID_FIFO_n_9,
D(5) => BID_FIFO_n_10,
D(4) => BID_FIFO_n_11,
D(3) => BID_FIFO_n_12,
D(2) => BID_FIFO_n_13,
D(1) => BID_FIFO_n_14,
D(0) => BID_FIFO_n_15,
E(0) => BID_FIFO_n_0,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
Q(11 downto 0) => axi_awid_pipe(11 downto 0),
SR(0) => SR(0),
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_bvalid_int_reg => \^s_axi_bvalid\,
axi_wdata_full_cmb114_out => axi_wdata_full_cmb114_out,
axi_wr_burst => axi_wr_burst,
bid_gets_fifo_load => bid_gets_fifo_load,
bid_gets_fifo_load_d1 => bid_gets_fifo_load_d1,
bid_gets_fifo_load_d1_reg => BID_FIFO_n_3,
bram_addr_ld_en => bram_addr_ld_en,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
bvalid_cnt_inc => bvalid_cnt_inc,
\bvalid_cnt_reg[1]\ => bid_gets_fifo_load_d1_i_2_n_0,
\bvalid_cnt_reg[2]\ => I_WRAP_BRST_n_20,
\bvalid_cnt_reg[2]_0\ => I_WRAP_BRST_n_19,
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awready => \^s_axi_awready\,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_wlast => s_axi_wlast,
s_axi_wvalid => s_axi_wvalid,
wr_addr_sm_cs => wr_addr_sm_cs
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(0),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"05051F1A"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => axi_wr_burst_cmb0,
I2 => wr_data_sm_cs(0),
I3 => axi_wdata_full_cmb114_out,
I4 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"5515"
)
port map (
I0 => I_WRAP_BRST_n_21,
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
O => axi_wr_burst_cmb0
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(1),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000554000555540"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => s_axi_wlast,
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(2),
I5 => axi_wr_burst,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\,
I1 => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\,
I2 => wr_data_sm_cs(2),
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"44010001"
)
port map (
I0 => wr_data_sm_cs(2),
I1 => wr_data_sm_cs(1),
I2 => axi_wdata_full_cmb114_out,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_2_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"7774777774744444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(0),
I5 => s_axi_wvalid,
O => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_3_n_0\
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[0]_i_1_n_0\,
Q => wr_data_sm_cs(0),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[1]_i_1_n_0\,
Q => wr_data_sm_cs(1),
R => SR(0)
);
\FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \FSM_sequential_GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.wr_data_sm_cs[2]_i_1_n_0\,
Q => wr_data_sm_cs(2),
R => SR(0)
);
\GEN_AWREADY.axi_aresetn_d1_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_aresetn,
Q => \I_RD_CHNL/axi_aresetn_d1\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_d2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \I_RD_CHNL/axi_aresetn_d1\,
Q => \^axi_aresetn_d2\,
R => '0'
);
\GEN_AWREADY.axi_aresetn_re_reg_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_aresetn,
I1 => \I_RD_CHNL/axi_aresetn_d1\,
O => axi_aresetn_re
);
\GEN_AWREADY.axi_aresetn_re_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_aresetn_re,
Q => \^axi_aresetn_re_reg\,
R => '0'
);
\GEN_AWREADY.axi_awready_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFBFFFFFAA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => bram_addr_ld_en,
I4 => \^axi_aresetn_re_reg\,
I5 => \^s_axi_awready\,
O => \GEN_AWREADY.axi_awready_int_i_1_n_0\
);
\GEN_AWREADY.axi_awready_int_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"5444444400000000"
)
port map (
I0 => \GEN_AWREADY.axi_awready_int_i_3_n_0\,
I1 => aw_active,
I2 => bvalid_cnt(1),
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => s_axi_awvalid,
O => \GEN_AWREADY.axi_awready_int_i_2_n_0\
);
\GEN_AWREADY.axi_awready_int_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"AABABABABABABABA"
)
port map (
I0 => wr_addr_sm_cs,
I1 => I_WRAP_BRST_n_21,
I2 => last_data_ack_mod,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \GEN_AWREADY.axi_awready_int_i_3_n_0\
);
\GEN_AWREADY.axi_awready_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AWREADY.axi_awready_int_i_1_n_0\,
Q => \^s_axi_awready\,
R => SR(0)
);
\GEN_AW_DUAL.aw_active_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi_aresetn_d2\,
O => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.aw_active_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF7FFFFFF0000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => wr_data_sm_cs(2),
I3 => delay_aw_active_clr,
I4 => bram_addr_ld_en,
I5 => aw_active,
O => \GEN_AW_DUAL.aw_active_i_2_n_0\
);
\GEN_AW_DUAL.aw_active_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.aw_active_i_2_n_0\,
Q => aw_active,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_DUAL.last_data_ack_mod_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => p_18_out
);
\GEN_AW_DUAL.last_data_ack_mod_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => p_18_out,
Q => last_data_ack_mod,
R => SR(0)
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000100000"
)
port map (
I0 => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\,
I1 => wr_addr_sm_cs,
I2 => s_axi_awvalid,
I3 => axi_awaddr_full,
I4 => I_WRAP_BRST_n_20,
I5 => aw_active,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000040"
)
port map (
I0 => I_WRAP_BRST_n_20,
I1 => last_data_ack_mod,
I2 => axi_awaddr_full,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => axi_awlen_pipe_1_or_2,
I5 => curr_awlen_reg_1_or_2,
O => \GEN_AW_DUAL.wr_addr_sm_cs_i_2_n_0\
);
\GEN_AW_DUAL.wr_addr_sm_cs_reg\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_DUAL.wr_addr_sm_cs_i_1_n_0\,
Q => wr_addr_sm_cs,
R => \^gen_aw_dual.aw_active_reg_0\
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(8),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(9),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(10),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(11),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(12),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(13),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(0),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(1),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(2),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(3),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(4),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(5),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(6),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awaddr(7),
Q => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"4000EA00"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => s_axi_aresetn,
I4 => bram_addr_ld_en,
O => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awaddr_full_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awaddr_full_i_1_n_0\,
Q => axi_awaddr_full,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BF00BF00BF00FF40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
I3 => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
I4 => s_axi_awburst(0),
I5 => s_axi_awburst(1),
O => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_i_1_n_0\,
Q => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(0),
Q => axi_awburst_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awburst(1),
Q => axi_awburst_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(0),
Q => axi_awid_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(10),
Q => axi_awid_pipe(10),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(11),
Q => axi_awid_pipe(11),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(1),
Q => axi_awid_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(2),
Q => axi_awid_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(3),
Q => axi_awid_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(4),
Q => axi_awid_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(5),
Q => axi_awid_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(6),
Q => axi_awid_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(7),
Q => axi_awid_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(8),
Q => axi_awid_pipe(8),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awid_pipe_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awid(9),
Q => axi_awid_pipe(9),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => axi_awaddr_full,
I1 => \GEN_AWREADY.axi_awready_int_i_2_n_0\,
I2 => \^axi_aresetn_d2\,
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0002"
)
port map (
I0 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I1 => s_axi_awlen(3),
I2 => s_axi_awlen(2),
I3 => s_axi_awlen(1),
O => p_9_out
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => s_axi_awlen(4),
I1 => s_axi_awlen(6),
I2 => s_axi_awlen(7),
I3 => s_axi_awlen(5),
O => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => p_9_out,
Q => axi_awlen_pipe_1_or_2,
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(0),
Q => axi_awlen_pipe(0),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(1),
Q => axi_awlen_pipe(1),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(2),
Q => axi_awlen_pipe(2),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(3),
Q => axi_awlen_pipe(3),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(4),
Q => axi_awlen_pipe(4),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(5),
Q => axi_awlen_pipe(5),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(6),
Q => axi_awlen_pipe(6),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awlen_pipe_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => s_axi_awlen(7),
Q => axi_awlen_pipe(7),
R => '0'
);
\GEN_AW_PIPE_DUAL.axi_awsize_pipe_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_AW_PIPE_DUAL.axi_awlen_pipe[7]_i_1_n_0\,
D => '1',
Q => axi_awsize_pipe(1),
R => '0'
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFFFFFFFFFF"
)
port map (
I0 => \^bram_addr_a\(4),
I1 => \^bram_addr_a\(1),
I2 => \^bram_addr_a\(0),
I3 => \^bram_addr_a\(2),
I4 => \^bram_addr_a\(3),
I5 => \^bram_addr_a\(5),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F7FFFFFF"
)
port map (
I0 => \^bram_addr_a\(6),
I1 => \^bram_addr_a\(4),
I2 => I_WRAP_BRST_n_17,
I3 => \^bram_addr_a\(5),
I4 => \^bram_addr_a\(7),
O => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => s_axi_wvalid,
O => bram_addr_inc
);
\GEN_DUAL_ADDR_CNT.bram_addr_int[15]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"1000"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(0),
I3 => wr_data_sm_cs(1),
O => bram_addr_rst_cmb
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_8,
Q => \^bram_addr_a\(8),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_7,
Q => \^bram_addr_a\(9),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(10),
Q => \^bram_addr_a\(10),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(11),
Q => \^bram_addr_a\(11),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(12),
Q => \^bram_addr_a\(12),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en_mod,
D => bram_addr_ld(13),
Q => \^bram_addr_a\(13),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_16,
Q => \^bram_addr_a\(0),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_15,
Q => \^bram_addr_a\(1),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_14,
Q => \^bram_addr_a\(2),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_13,
Q => \^bram_addr_a\(3),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_12,
Q => \^bram_addr_a\(4),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_11,
Q => \^bram_addr_a\(5),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_10,
Q => \^bram_addr_a\(6),
R => I_WRAP_BRST_n_0
);
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => I_WRAP_BRST_n_2,
D => I_WRAP_BRST_n_9,
Q => \^bram_addr_a\(7),
R => I_WRAP_BRST_n_0
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"15FF1500"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
O => axi_wdata_full_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.axi_wdata_full_reg_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wdata_full_cmb,
Q => axi_wdata_full_reg,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4777477444444444"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I1 => wr_data_sm_cs(2),
I2 => wr_data_sm_cs(1),
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => s_axi_wvalid,
O => bram_en_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"15"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bram_en_cmb,
Q => bram_en_a,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0010001000101110"
)
port map (
I0 => wr_data_sm_cs(0),
I1 => wr_data_sm_cs(1),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I5 => axi_wr_burst,
O => clr_bram_we_cmb
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => s_axi_wlast,
I2 => s_axi_wvalid,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.clr_bram_we_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => clr_bram_we_cmb,
Q => clr_bram_we,
R => SR(0)
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEAAFEFF02AA0200"
)
port map (
I0 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\,
I1 => axi_wr_burst,
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(2),
I4 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\,
I5 => delay_aw_active_clr,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000222E"
)
port map (
I0 => s_axi_wlast,
I1 => wr_data_sm_cs(2),
I2 => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.bram_en_int_i_2_n_0\,
I3 => wr_data_sm_cs(0),
I4 => wr_data_sm_cs(1),
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_2_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8B338B0088008800"
)
port map (
I0 => delay_aw_active_clr,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => axi_wdata_full_cmb114_out,
I5 => bvalid_cnt_inc11_out,
O => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_3_n_0\
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_wlast,
O => bvalid_cnt_inc11_out
);
\GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \GEN_WDATA_SM_NO_ECC_DUAL_REG_WREADY.delay_aw_active_clr_i_1_n_0\,
Q => delay_aw_active_clr,
R => SR(0)
);
\GEN_WRDATA[0].bram_wrdata_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(0),
Q => bram_wrdata_a(0),
R => '0'
);
\GEN_WRDATA[10].bram_wrdata_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(10),
Q => bram_wrdata_a(10),
R => '0'
);
\GEN_WRDATA[11].bram_wrdata_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(11),
Q => bram_wrdata_a(11),
R => '0'
);
\GEN_WRDATA[12].bram_wrdata_int_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(12),
Q => bram_wrdata_a(12),
R => '0'
);
\GEN_WRDATA[13].bram_wrdata_int_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(13),
Q => bram_wrdata_a(13),
R => '0'
);
\GEN_WRDATA[14].bram_wrdata_int_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(14),
Q => bram_wrdata_a(14),
R => '0'
);
\GEN_WRDATA[15].bram_wrdata_int_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(15),
Q => bram_wrdata_a(15),
R => '0'
);
\GEN_WRDATA[16].bram_wrdata_int_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(16),
Q => bram_wrdata_a(16),
R => '0'
);
\GEN_WRDATA[17].bram_wrdata_int_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(17),
Q => bram_wrdata_a(17),
R => '0'
);
\GEN_WRDATA[18].bram_wrdata_int_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(18),
Q => bram_wrdata_a(18),
R => '0'
);
\GEN_WRDATA[19].bram_wrdata_int_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(19),
Q => bram_wrdata_a(19),
R => '0'
);
\GEN_WRDATA[1].bram_wrdata_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(1),
Q => bram_wrdata_a(1),
R => '0'
);
\GEN_WRDATA[20].bram_wrdata_int_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(20),
Q => bram_wrdata_a(20),
R => '0'
);
\GEN_WRDATA[21].bram_wrdata_int_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(21),
Q => bram_wrdata_a(21),
R => '0'
);
\GEN_WRDATA[22].bram_wrdata_int_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(22),
Q => bram_wrdata_a(22),
R => '0'
);
\GEN_WRDATA[23].bram_wrdata_int_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(23),
Q => bram_wrdata_a(23),
R => '0'
);
\GEN_WRDATA[24].bram_wrdata_int_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(24),
Q => bram_wrdata_a(24),
R => '0'
);
\GEN_WRDATA[25].bram_wrdata_int_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(25),
Q => bram_wrdata_a(25),
R => '0'
);
\GEN_WRDATA[26].bram_wrdata_int_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(26),
Q => bram_wrdata_a(26),
R => '0'
);
\GEN_WRDATA[27].bram_wrdata_int_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(27),
Q => bram_wrdata_a(27),
R => '0'
);
\GEN_WRDATA[28].bram_wrdata_int_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(28),
Q => bram_wrdata_a(28),
R => '0'
);
\GEN_WRDATA[29].bram_wrdata_int_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(29),
Q => bram_wrdata_a(29),
R => '0'
);
\GEN_WRDATA[2].bram_wrdata_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(2),
Q => bram_wrdata_a(2),
R => '0'
);
\GEN_WRDATA[30].bram_wrdata_int_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(30),
Q => bram_wrdata_a(30),
R => '0'
);
\GEN_WRDATA[31].bram_wrdata_int_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(31),
Q => bram_wrdata_a(31),
R => '0'
);
\GEN_WRDATA[3].bram_wrdata_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(3),
Q => bram_wrdata_a(3),
R => '0'
);
\GEN_WRDATA[4].bram_wrdata_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(4),
Q => bram_wrdata_a(4),
R => '0'
);
\GEN_WRDATA[5].bram_wrdata_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(5),
Q => bram_wrdata_a(5),
R => '0'
);
\GEN_WRDATA[6].bram_wrdata_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(6),
Q => bram_wrdata_a(6),
R => '0'
);
\GEN_WRDATA[7].bram_wrdata_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(7),
Q => bram_wrdata_a(7),
R => '0'
);
\GEN_WRDATA[8].bram_wrdata_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(8),
Q => bram_wrdata_a(8),
R => '0'
);
\GEN_WRDATA[9].bram_wrdata_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wdata(9),
Q => bram_wrdata_a(9),
R => '0'
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"D0FF"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
I2 => clr_bram_we,
I3 => s_axi_aresetn,
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(2),
O => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(0),
Q => bram_we_a(0),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(1),
Q => bram_we_a(1),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(2),
Q => bram_we_a(2),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
\GEN_WR_NO_ECC.bram_we_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => \GEN_WR_NO_ECC.bram_we_int[3]_i_2_n_0\,
D => s_axi_wstrb(3),
Q => bram_we_a(3),
R => \GEN_WR_NO_ECC.bram_we_int[3]_i_1_n_0\
);
I_WRAP_BRST: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wrap_brst
port map (
D(13 downto 10) => bram_addr_ld(13 downto 10),
D(9) => I_WRAP_BRST_n_7,
D(8) => I_WRAP_BRST_n_8,
D(7) => I_WRAP_BRST_n_9,
D(6) => I_WRAP_BRST_n_10,
D(5) => I_WRAP_BRST_n_11,
D(4) => I_WRAP_BRST_n_12,
D(3) => I_WRAP_BRST_n_13,
D(2) => I_WRAP_BRST_n_14,
D(1) => I_WRAP_BRST_n_15,
D(0) => I_WRAP_BRST_n_16,
E(0) => I_WRAP_BRST_n_2,
\GEN_AWREADY.axi_aresetn_d2_reg\ => \^axi_aresetn_d2\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[10].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[11].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[12].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[13].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[14].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[15].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[2].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[3].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[4].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[5].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[6].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[7].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[8].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\ => \GEN_AW_PIPE_DUAL.GEN_AWADDR[9].axi_awaddr_pipe_reg\,
\GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg\ => \GEN_AW_PIPE_DUAL.axi_awburst_pipe_fixed_reg_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[6]\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[10]_i_2__0_n_0\,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]\ => I_WRAP_BRST_n_17,
\GEN_DUAL_ADDR_CNT.bram_addr_int_reg[8]_0\ => \GEN_DUAL_ADDR_CNT.bram_addr_int[11]_i_3__0_n_0\,
Q(3 downto 0) => axi_awlen_pipe(3 downto 0),
SR(0) => I_WRAP_BRST_n_0,
aw_active => aw_active,
axi_awaddr_full => axi_awaddr_full,
axi_awlen_pipe_1_or_2 => axi_awlen_pipe_1_or_2,
axi_awsize_pipe(0) => axi_awsize_pipe(1),
bram_addr_a(9 downto 0) => \^bram_addr_a\(9 downto 0),
bram_addr_inc => bram_addr_inc,
bram_addr_ld_en => bram_addr_ld_en,
bram_addr_ld_en_mod => bram_addr_ld_en_mod,
bram_addr_rst_cmb => bram_addr_rst_cmb,
bvalid_cnt(2 downto 0) => bvalid_cnt(2 downto 0),
curr_awlen_reg_1_or_2 => curr_awlen_reg_1_or_2,
curr_fixed_burst => curr_fixed_burst,
curr_fixed_burst_reg => curr_fixed_burst_reg,
curr_fixed_burst_reg_reg => I_WRAP_BRST_n_22,
curr_wrap_burst => curr_wrap_burst,
curr_wrap_burst_reg => curr_wrap_burst_reg,
curr_wrap_burst_reg_reg => I_WRAP_BRST_n_23,
last_data_ack_mod => last_data_ack_mod,
\out\(2 downto 0) => wr_data_sm_cs(2 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_aresetn_0(0) => SR(0),
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_wvalid => s_axi_wvalid,
\save_init_bram_addr_ld_reg[15]_0\ => I_WRAP_BRST_n_19,
\save_init_bram_addr_ld_reg[15]_1\ => I_WRAP_BRST_n_20,
\save_init_bram_addr_ld_reg[15]_2\ => I_WRAP_BRST_n_21,
wr_addr_sm_cs => wr_addr_sm_cs
);
\axi_bid_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_15,
Q => s_axi_bid(0),
R => SR(0)
);
\axi_bid_int_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_5,
Q => s_axi_bid(10),
R => SR(0)
);
\axi_bid_int_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_4,
Q => s_axi_bid(11),
R => SR(0)
);
\axi_bid_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_14,
Q => s_axi_bid(1),
R => SR(0)
);
\axi_bid_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_13,
Q => s_axi_bid(2),
R => SR(0)
);
\axi_bid_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_12,
Q => s_axi_bid(3),
R => SR(0)
);
\axi_bid_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_11,
Q => s_axi_bid(4),
R => SR(0)
);
\axi_bid_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_10,
Q => s_axi_bid(5),
R => SR(0)
);
\axi_bid_int_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_9,
Q => s_axi_bid(6),
R => SR(0)
);
\axi_bid_int_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_8,
Q => s_axi_bid(7),
R => SR(0)
);
\axi_bid_int_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_7,
Q => s_axi_bid(8),
R => SR(0)
);
\axi_bid_int_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => BID_FIFO_n_0,
D => BID_FIFO_n_6,
Q => s_axi_bid(9),
R => SR(0)
);
axi_bvalid_int_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAA8A88"
)
port map (
I0 => s_axi_aresetn,
I1 => bvalid_cnt_inc,
I2 => BID_FIFO_n_3,
I3 => bvalid_cnt(0),
I4 => bvalid_cnt(2),
I5 => bvalid_cnt(1),
O => axi_bvalid_int_i_1_n_0
);
axi_bvalid_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_bvalid_int_i_1_n_0,
Q => \^s_axi_bvalid\,
R => '0'
);
axi_wr_burst_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => axi_wr_burst_cmb,
I1 => axi_wr_burst_i_3_n_0,
I2 => axi_wr_burst,
O => axi_wr_burst_i_1_n_0
);
axi_wr_burst_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"3088FCBB"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(1),
I2 => axi_wr_burst_cmb0,
I3 => wr_data_sm_cs(0),
I4 => s_axi_wlast,
O => axi_wr_burst_cmb
);
axi_wr_burst_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000AAAAA222"
)
port map (
I0 => s_axi_wvalid,
I1 => wr_data_sm_cs(0),
I2 => axi_wr_burst_cmb0,
I3 => s_axi_wlast,
I4 => wr_data_sm_cs(1),
I5 => wr_data_sm_cs(2),
O => axi_wr_burst_i_3_n_0
);
axi_wr_burst_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wr_burst_i_1_n_0,
Q => axi_wr_burst,
R => SR(0)
);
axi_wready_int_mod_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"EA00EAFF00000000"
)
port map (
I0 => axi_wdata_full_cmb114_out,
I1 => axi_awaddr_full,
I2 => bram_addr_ld_en,
I3 => wr_data_sm_cs(2),
I4 => axi_wready_int_mod_i_3_n_0,
I5 => s_axi_aresetn,
O => axi_wready_int_mod_i_1_n_0
);
axi_wready_int_mod_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"F8F9F0F0"
)
port map (
I0 => wr_data_sm_cs(1),
I1 => wr_data_sm_cs(0),
I2 => axi_wdata_full_reg,
I3 => axi_wdata_full_cmb114_out,
I4 => s_axi_wvalid,
O => axi_wready_int_mod_i_3_n_0
);
axi_wready_int_mod_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => axi_wready_int_mod_i_1_n_0,
Q => \^s_axi_wready\,
R => '0'
);
bid_gets_fifo_load_d1_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => bvalid_cnt(1),
I1 => bvalid_cnt(2),
I2 => bvalid_cnt(0),
O => bid_gets_fifo_load_d1_i_2_n_0
);
bid_gets_fifo_load_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => bid_gets_fifo_load,
Q => bid_gets_fifo_load_d1,
R => SR(0)
);
\bvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"95956A6A95956AAA"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[0]_i_1_n_0\
);
\bvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D5D5BFBF2A2A4000"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[1]_i_1_n_0\
);
\bvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"D52AFF00FF00BF00"
)
port map (
I0 => bvalid_cnt_inc,
I1 => s_axi_bready,
I2 => \^s_axi_bvalid\,
I3 => bvalid_cnt(2),
I4 => bvalid_cnt(0),
I5 => bvalid_cnt(1),
O => \bvalid_cnt[2]_i_1_n_0\
);
\bvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[0]_i_1_n_0\,
Q => bvalid_cnt(0),
R => SR(0)
);
\bvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[1]_i_1_n_0\,
Q => bvalid_cnt(1),
R => SR(0)
);
\bvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \bvalid_cnt[2]_i_1_n_0\,
Q => bvalid_cnt(2),
R => SR(0)
);
curr_awlen_reg_1_or_2_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"00A0000000A0E0E0"
)
port map (
I0 => curr_awlen_reg_1_or_2_i_2_n_0,
I1 => \GEN_AW_PIPE_DUAL.axi_awlen_pipe_1_or_2_i_2_n_0\,
I2 => curr_awlen_reg_1_or_2_i_3_n_0,
I3 => axi_awlen_pipe(3),
I4 => axi_awaddr_full,
I5 => s_axi_awlen(3),
O => curr_awlen_reg_1_or_20
);
curr_awlen_reg_1_or_2_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00000004"
)
port map (
I0 => axi_awlen_pipe(7),
I1 => axi_awaddr_full,
I2 => axi_awlen_pipe(5),
I3 => axi_awlen_pipe(4),
I4 => axi_awlen_pipe(6),
O => curr_awlen_reg_1_or_2_i_2_n_0
);
curr_awlen_reg_1_or_2_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awlen(2),
I1 => axi_awlen_pipe(2),
I2 => s_axi_awlen(1),
I3 => axi_awaddr_full,
I4 => axi_awlen_pipe(1),
O => curr_awlen_reg_1_or_2_i_3_n_0
);
curr_awlen_reg_1_or_2_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bram_addr_ld_en,
D => curr_awlen_reg_1_or_20,
Q => curr_awlen_reg_1_or_2,
R => SR(0)
);
curr_fixed_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"00053305"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_fixed_burst
);
curr_fixed_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_22,
Q => curr_fixed_burst_reg,
R => '0'
);
curr_wrap_burst_reg_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => s_axi_awburst(1),
I1 => axi_awburst_pipe(1),
I2 => s_axi_awburst(0),
I3 => axi_awaddr_full,
I4 => axi_awburst_pipe(0),
O => curr_wrap_burst
);
curr_wrap_burst_reg_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => I_WRAP_BRST_n_23,
Q => curr_wrap_burst_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi is
signal I_WR_CHNL_n_36 : STD_LOGIC;
signal axi_aresetn_d2 : STD_LOGIC;
signal axi_aresetn_re_reg : STD_LOGIC;
signal \^bram_rst_a\ : STD_LOGIC;
begin
bram_rst_a <= \^bram_rst_a\;
I_RD_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_chnl
port map (
\GEN_AWREADY.axi_aresetn_d2_reg\ => I_WR_CHNL_n_36,
Q(13 downto 0) => bram_addr_b(13 downto 0),
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
I_WR_CHNL: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_chnl
port map (
\GEN_AW_DUAL.aw_active_reg_0\ => I_WR_CHNL_n_36,
SR(0) => \^bram_rst_a\,
axi_aresetn_d2 => axi_aresetn_d2,
axi_aresetn_re_reg => axi_aresetn_re_reg,
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_en_a => bram_en_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_rlast : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_addr_a : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wlast : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 13 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top is
begin
\GEN_AXI4.I_FULL_AXI\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_full_axi
port map (
bram_addr_a(13 downto 0) => bram_addr_a(13 downto 0),
bram_addr_b(13 downto 0) => bram_addr_b(13 downto 0),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(13 downto 0) => s_axi_araddr(13 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(13 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
ecc_interrupt : out STD_LOGIC;
ecc_ue : out STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_ctrl_awvalid : in STD_LOGIC;
s_axi_ctrl_awready : out STD_LOGIC;
s_axi_ctrl_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_wvalid : in STD_LOGIC;
s_axi_ctrl_wready : out STD_LOGIC;
s_axi_ctrl_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_bvalid : out STD_LOGIC;
s_axi_ctrl_bready : in STD_LOGIC;
s_axi_ctrl_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_arvalid : in STD_LOGIC;
s_axi_ctrl_arready : out STD_LOGIC;
s_axi_ctrl_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_ctrl_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_ctrl_rvalid : out STD_LOGIC;
s_axi_ctrl_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is 0;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl : entity is "yes";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl is
signal \<const0>\ : STD_LOGIC;
signal \^bram_addr_a\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_addr_b\ : STD_LOGIC_VECTOR ( 15 downto 2 );
signal \^bram_rst_a\ : STD_LOGIC;
signal \^s_axi_aclk\ : STD_LOGIC;
begin
\^s_axi_aclk\ <= s_axi_aclk;
bram_addr_a(15 downto 2) <= \^bram_addr_a\(15 downto 2);
bram_addr_a(1) <= \<const0>\;
bram_addr_a(0) <= \<const0>\;
bram_addr_b(15 downto 2) <= \^bram_addr_b\(15 downto 2);
bram_addr_b(1) <= \<const0>\;
bram_addr_b(0) <= \<const0>\;
bram_clk_a <= \^s_axi_aclk\;
bram_clk_b <= \^s_axi_aclk\;
bram_rst_a <= \^bram_rst_a\;
bram_rst_b <= \^bram_rst_a\;
bram_we_b(3) <= \<const0>\;
bram_we_b(2) <= \<const0>\;
bram_we_b(1) <= \<const0>\;
bram_we_b(0) <= \<const0>\;
bram_wrdata_b(31) <= \<const0>\;
bram_wrdata_b(30) <= \<const0>\;
bram_wrdata_b(29) <= \<const0>\;
bram_wrdata_b(28) <= \<const0>\;
bram_wrdata_b(27) <= \<const0>\;
bram_wrdata_b(26) <= \<const0>\;
bram_wrdata_b(25) <= \<const0>\;
bram_wrdata_b(24) <= \<const0>\;
bram_wrdata_b(23) <= \<const0>\;
bram_wrdata_b(22) <= \<const0>\;
bram_wrdata_b(21) <= \<const0>\;
bram_wrdata_b(20) <= \<const0>\;
bram_wrdata_b(19) <= \<const0>\;
bram_wrdata_b(18) <= \<const0>\;
bram_wrdata_b(17) <= \<const0>\;
bram_wrdata_b(16) <= \<const0>\;
bram_wrdata_b(15) <= \<const0>\;
bram_wrdata_b(14) <= \<const0>\;
bram_wrdata_b(13) <= \<const0>\;
bram_wrdata_b(12) <= \<const0>\;
bram_wrdata_b(11) <= \<const0>\;
bram_wrdata_b(10) <= \<const0>\;
bram_wrdata_b(9) <= \<const0>\;
bram_wrdata_b(8) <= \<const0>\;
bram_wrdata_b(7) <= \<const0>\;
bram_wrdata_b(6) <= \<const0>\;
bram_wrdata_b(5) <= \<const0>\;
bram_wrdata_b(4) <= \<const0>\;
bram_wrdata_b(3) <= \<const0>\;
bram_wrdata_b(2) <= \<const0>\;
bram_wrdata_b(1) <= \<const0>\;
bram_wrdata_b(0) <= \<const0>\;
ecc_interrupt <= \<const0>\;
ecc_ue <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_ctrl_arready <= \<const0>\;
s_axi_ctrl_awready <= \<const0>\;
s_axi_ctrl_bresp(1) <= \<const0>\;
s_axi_ctrl_bresp(0) <= \<const0>\;
s_axi_ctrl_bvalid <= \<const0>\;
s_axi_ctrl_rdata(31) <= \<const0>\;
s_axi_ctrl_rdata(30) <= \<const0>\;
s_axi_ctrl_rdata(29) <= \<const0>\;
s_axi_ctrl_rdata(28) <= \<const0>\;
s_axi_ctrl_rdata(27) <= \<const0>\;
s_axi_ctrl_rdata(26) <= \<const0>\;
s_axi_ctrl_rdata(25) <= \<const0>\;
s_axi_ctrl_rdata(24) <= \<const0>\;
s_axi_ctrl_rdata(23) <= \<const0>\;
s_axi_ctrl_rdata(22) <= \<const0>\;
s_axi_ctrl_rdata(21) <= \<const0>\;
s_axi_ctrl_rdata(20) <= \<const0>\;
s_axi_ctrl_rdata(19) <= \<const0>\;
s_axi_ctrl_rdata(18) <= \<const0>\;
s_axi_ctrl_rdata(17) <= \<const0>\;
s_axi_ctrl_rdata(16) <= \<const0>\;
s_axi_ctrl_rdata(15) <= \<const0>\;
s_axi_ctrl_rdata(14) <= \<const0>\;
s_axi_ctrl_rdata(13) <= \<const0>\;
s_axi_ctrl_rdata(12) <= \<const0>\;
s_axi_ctrl_rdata(11) <= \<const0>\;
s_axi_ctrl_rdata(10) <= \<const0>\;
s_axi_ctrl_rdata(9) <= \<const0>\;
s_axi_ctrl_rdata(8) <= \<const0>\;
s_axi_ctrl_rdata(7) <= \<const0>\;
s_axi_ctrl_rdata(6) <= \<const0>\;
s_axi_ctrl_rdata(5) <= \<const0>\;
s_axi_ctrl_rdata(4) <= \<const0>\;
s_axi_ctrl_rdata(3) <= \<const0>\;
s_axi_ctrl_rdata(2) <= \<const0>\;
s_axi_ctrl_rdata(1) <= \<const0>\;
s_axi_ctrl_rdata(0) <= \<const0>\;
s_axi_ctrl_rresp(1) <= \<const0>\;
s_axi_ctrl_rresp(0) <= \<const0>\;
s_axi_ctrl_rvalid <= \<const0>\;
s_axi_ctrl_wready <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gext_inst.abcv4_0_ext_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl_top
port map (
bram_addr_a(13 downto 0) => \^bram_addr_a\(15 downto 2),
bram_addr_b(13 downto 0) => \^bram_addr_b\(15 downto 2),
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => \^bram_rst_a\,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
s_axi_aclk => \^s_axi_aclk\,
s_axi_araddr(13 downto 0) => s_axi_araddr(15 downto 2),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(13 downto 0) => s_axi_awaddr(15 downto 2),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC;
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC;
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
bram_rst_a : out STD_LOGIC;
bram_clk_a : out STD_LOGIC;
bram_en_a : out STD_LOGIC;
bram_we_a : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_a : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_a : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_a : in STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rst_b : out STD_LOGIC;
bram_clk_b : out STD_LOGIC;
bram_en_b : out STD_LOGIC;
bram_we_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
bram_addr_b : out STD_LOGIC_VECTOR ( 15 downto 0 );
bram_wrdata_b : out STD_LOGIC_VECTOR ( 31 downto 0 );
bram_rddata_b : in STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_0,axi_bram_ctrl,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_bram_ctrl,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_U0_ecc_interrupt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_ecc_ue_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_ctrl_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ctrl_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_ctrl_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_BRAM_ADDR_WIDTH : integer;
attribute C_BRAM_ADDR_WIDTH of U0 : label is 14;
attribute C_BRAM_INST_MODE : string;
attribute C_BRAM_INST_MODE of U0 : label is "EXTERNAL";
attribute C_ECC : integer;
attribute C_ECC of U0 : label is 0;
attribute C_ECC_ONOFF_RESET_VALUE : integer;
attribute C_ECC_ONOFF_RESET_VALUE of U0 : label is 0;
attribute C_ECC_TYPE : integer;
attribute C_ECC_TYPE of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FAULT_INJECT : integer;
attribute C_FAULT_INJECT of U0 : label is 0;
attribute C_MEMORY_DEPTH : integer;
attribute C_MEMORY_DEPTH of U0 : label is 16384;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of U0 : label is 0;
attribute C_SINGLE_PORT_BRAM : integer;
attribute C_SINGLE_PORT_BRAM of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 16;
attribute C_S_AXI_CTRL_ADDR_WIDTH : integer;
attribute C_S_AXI_CTRL_ADDR_WIDTH of U0 : label is 32;
attribute C_S_AXI_CTRL_DATA_WIDTH : integer;
attribute C_S_AXI_CTRL_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_S_AXI_ID_WIDTH : integer;
attribute C_S_AXI_ID_WIDTH of U0 : label is 12;
attribute C_S_AXI_PROTOCOL : string;
attribute C_S_AXI_PROTOCOL of U0 : label is "AXI4";
attribute C_S_AXI_SUPPORTS_NARROW_BURST : integer;
attribute C_S_AXI_SUPPORTS_NARROW_BURST of U0 : label is 0;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_bram_ctrl
port map (
bram_addr_a(15 downto 0) => bram_addr_a(15 downto 0),
bram_addr_b(15 downto 0) => bram_addr_b(15 downto 0),
bram_clk_a => bram_clk_a,
bram_clk_b => bram_clk_b,
bram_en_a => bram_en_a,
bram_en_b => bram_en_b,
bram_rddata_a(31 downto 0) => bram_rddata_a(31 downto 0),
bram_rddata_b(31 downto 0) => bram_rddata_b(31 downto 0),
bram_rst_a => bram_rst_a,
bram_rst_b => bram_rst_b,
bram_we_a(3 downto 0) => bram_we_a(3 downto 0),
bram_we_b(3 downto 0) => bram_we_b(3 downto 0),
bram_wrdata_a(31 downto 0) => bram_wrdata_a(31 downto 0),
bram_wrdata_b(31 downto 0) => bram_wrdata_b(31 downto 0),
ecc_interrupt => NLW_U0_ecc_interrupt_UNCONNECTED,
ecc_ue => NLW_U0_ecc_ue_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(15 downto 0) => s_axi_araddr(15 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock => s_axi_arlock,
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(15 downto 0) => s_axi_awaddr(15 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock => s_axi_awlock,
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_ctrl_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_arready => NLW_U0_s_axi_ctrl_arready_UNCONNECTED,
s_axi_ctrl_arvalid => '0',
s_axi_ctrl_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_awready => NLW_U0_s_axi_ctrl_awready_UNCONNECTED,
s_axi_ctrl_awvalid => '0',
s_axi_ctrl_bready => '0',
s_axi_ctrl_bresp(1 downto 0) => NLW_U0_s_axi_ctrl_bresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_bvalid => NLW_U0_s_axi_ctrl_bvalid_UNCONNECTED,
s_axi_ctrl_rdata(31 downto 0) => NLW_U0_s_axi_ctrl_rdata_UNCONNECTED(31 downto 0),
s_axi_ctrl_rready => '0',
s_axi_ctrl_rresp(1 downto 0) => NLW_U0_s_axi_ctrl_rresp_UNCONNECTED(1 downto 0),
s_axi_ctrl_rvalid => NLW_U0_s_axi_ctrl_rvalid_UNCONNECTED,
s_axi_ctrl_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_ctrl_wready => NLW_U0_s_axi_ctrl_wready_UNCONNECTED,
s_axi_ctrl_wvalid => '0',
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
| mit | dd26f6bfc5912e9d992b1107d9b44e99 | 0.545297 | 2.566338 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.ipdefs/ip_0/RecComp_cnn_lab_convolve_kernel_1_0/hdl/vhdl/convolve_kernel.vhd | 1 | 806,728 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.3
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity convolve_kernel is
generic (
C_S_AXI_CONTROL_ADDR_WIDTH : INTEGER := 4;
C_S_AXI_CONTROL_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
bufw_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_EN_A : OUT STD_LOGIC;
bufw_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Clk_A : OUT STD_LOGIC;
bufw_0_Rst_A : OUT STD_LOGIC;
bufw_0_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_EN_B : OUT STD_LOGIC;
bufw_0_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_0_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_0_Clk_B : OUT STD_LOGIC;
bufw_0_Rst_B : OUT STD_LOGIC;
bufw_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_EN_A : OUT STD_LOGIC;
bufw_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Clk_A : OUT STD_LOGIC;
bufw_1_Rst_A : OUT STD_LOGIC;
bufw_1_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_EN_B : OUT STD_LOGIC;
bufw_1_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_1_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_1_Clk_B : OUT STD_LOGIC;
bufw_1_Rst_B : OUT STD_LOGIC;
bufw_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_EN_A : OUT STD_LOGIC;
bufw_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Clk_A : OUT STD_LOGIC;
bufw_2_Rst_A : OUT STD_LOGIC;
bufw_2_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_EN_B : OUT STD_LOGIC;
bufw_2_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_2_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_2_Clk_B : OUT STD_LOGIC;
bufw_2_Rst_B : OUT STD_LOGIC;
bufw_3_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_EN_A : OUT STD_LOGIC;
bufw_3_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_3_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Clk_A : OUT STD_LOGIC;
bufw_3_Rst_A : OUT STD_LOGIC;
bufw_3_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_EN_B : OUT STD_LOGIC;
bufw_3_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_3_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_3_Clk_B : OUT STD_LOGIC;
bufw_3_Rst_B : OUT STD_LOGIC;
bufw_4_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_EN_A : OUT STD_LOGIC;
bufw_4_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_4_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Clk_A : OUT STD_LOGIC;
bufw_4_Rst_A : OUT STD_LOGIC;
bufw_4_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_EN_B : OUT STD_LOGIC;
bufw_4_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_4_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_4_Clk_B : OUT STD_LOGIC;
bufw_4_Rst_B : OUT STD_LOGIC;
bufw_5_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_5_EN_A : OUT STD_LOGIC;
bufw_5_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_5_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_5_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_5_Clk_A : OUT STD_LOGIC;
bufw_5_Rst_A : OUT STD_LOGIC;
bufw_5_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_5_EN_B : OUT STD_LOGIC;
bufw_5_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_5_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_5_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_5_Clk_B : OUT STD_LOGIC;
bufw_5_Rst_B : OUT STD_LOGIC;
bufw_6_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_6_EN_A : OUT STD_LOGIC;
bufw_6_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_6_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_6_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_6_Clk_A : OUT STD_LOGIC;
bufw_6_Rst_A : OUT STD_LOGIC;
bufw_6_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_6_EN_B : OUT STD_LOGIC;
bufw_6_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_6_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_6_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_6_Clk_B : OUT STD_LOGIC;
bufw_6_Rst_B : OUT STD_LOGIC;
bufw_7_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_7_EN_A : OUT STD_LOGIC;
bufw_7_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_7_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_7_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_7_Clk_A : OUT STD_LOGIC;
bufw_7_Rst_A : OUT STD_LOGIC;
bufw_7_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_7_EN_B : OUT STD_LOGIC;
bufw_7_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_7_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_7_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_7_Clk_B : OUT STD_LOGIC;
bufw_7_Rst_B : OUT STD_LOGIC;
bufw_8_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_8_EN_A : OUT STD_LOGIC;
bufw_8_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_8_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_8_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_8_Clk_A : OUT STD_LOGIC;
bufw_8_Rst_A : OUT STD_LOGIC;
bufw_8_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_8_EN_B : OUT STD_LOGIC;
bufw_8_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_8_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_8_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_8_Clk_B : OUT STD_LOGIC;
bufw_8_Rst_B : OUT STD_LOGIC;
bufw_9_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_9_EN_A : OUT STD_LOGIC;
bufw_9_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_9_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_9_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_9_Clk_A : OUT STD_LOGIC;
bufw_9_Rst_A : OUT STD_LOGIC;
bufw_9_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_9_EN_B : OUT STD_LOGIC;
bufw_9_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_9_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_9_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_9_Clk_B : OUT STD_LOGIC;
bufw_9_Rst_B : OUT STD_LOGIC;
bufw_10_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_10_EN_A : OUT STD_LOGIC;
bufw_10_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_10_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_10_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_10_Clk_A : OUT STD_LOGIC;
bufw_10_Rst_A : OUT STD_LOGIC;
bufw_10_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_10_EN_B : OUT STD_LOGIC;
bufw_10_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_10_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_10_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_10_Clk_B : OUT STD_LOGIC;
bufw_10_Rst_B : OUT STD_LOGIC;
bufw_11_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_11_EN_A : OUT STD_LOGIC;
bufw_11_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_11_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_11_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_11_Clk_A : OUT STD_LOGIC;
bufw_11_Rst_A : OUT STD_LOGIC;
bufw_11_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_11_EN_B : OUT STD_LOGIC;
bufw_11_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_11_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_11_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_11_Clk_B : OUT STD_LOGIC;
bufw_11_Rst_B : OUT STD_LOGIC;
bufw_12_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_12_EN_A : OUT STD_LOGIC;
bufw_12_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_12_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_12_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_12_Clk_A : OUT STD_LOGIC;
bufw_12_Rst_A : OUT STD_LOGIC;
bufw_12_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_12_EN_B : OUT STD_LOGIC;
bufw_12_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufw_12_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufw_12_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufw_12_Clk_B : OUT STD_LOGIC;
bufw_12_Rst_B : OUT STD_LOGIC;
bufi_0_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_EN_A : OUT STD_LOGIC;
bufi_0_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_0_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Clk_A : OUT STD_LOGIC;
bufi_0_Rst_A : OUT STD_LOGIC;
bufi_0_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_EN_B : OUT STD_LOGIC;
bufi_0_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_0_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_0_Clk_B : OUT STD_LOGIC;
bufi_0_Rst_B : OUT STD_LOGIC;
bufi_1_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_EN_A : OUT STD_LOGIC;
bufi_1_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_1_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Clk_A : OUT STD_LOGIC;
bufi_1_Rst_A : OUT STD_LOGIC;
bufi_1_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_EN_B : OUT STD_LOGIC;
bufi_1_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_1_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_1_Clk_B : OUT STD_LOGIC;
bufi_1_Rst_B : OUT STD_LOGIC;
bufi_2_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_EN_A : OUT STD_LOGIC;
bufi_2_WEN_A : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_2_Din_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Dout_A : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Clk_A : OUT STD_LOGIC;
bufi_2_Rst_A : OUT STD_LOGIC;
bufi_2_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_EN_B : OUT STD_LOGIC;
bufi_2_WEN_B : OUT STD_LOGIC_VECTOR (3 downto 0);
bufi_2_Din_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Dout_B : IN STD_LOGIC_VECTOR (31 downto 0);
bufi_2_Clk_B : OUT STD_LOGIC;
bufi_2_Rst_B : OUT STD_LOGIC;
bufo_Addr_A : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_A : OUT STD_LOGIC;
bufo_WEN_A : OUT STD_LOGIC_VECTOR (63 downto 0);
bufo_Din_A : OUT STD_LOGIC_VECTOR (511 downto 0);
bufo_Dout_A : IN STD_LOGIC_VECTOR (511 downto 0);
bufo_Clk_A : OUT STD_LOGIC;
bufo_Rst_A : OUT STD_LOGIC;
bufo_Addr_B : OUT STD_LOGIC_VECTOR (31 downto 0);
bufo_EN_B : OUT STD_LOGIC;
bufo_WEN_B : OUT STD_LOGIC_VECTOR (63 downto 0);
bufo_Din_B : OUT STD_LOGIC_VECTOR (511 downto 0);
bufo_Dout_B : IN STD_LOGIC_VECTOR (511 downto 0);
bufo_Clk_B : OUT STD_LOGIC;
bufo_Rst_B : OUT STD_LOGIC;
s_axi_control_AWVALID : IN STD_LOGIC;
s_axi_control_AWREADY : OUT STD_LOGIC;
s_axi_control_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_WVALID : IN STD_LOGIC;
s_axi_control_WREADY : OUT STD_LOGIC;
s_axi_control_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH/8-1 downto 0);
s_axi_control_ARVALID : IN STD_LOGIC;
s_axi_control_ARREADY : OUT STD_LOGIC;
s_axi_control_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_CONTROL_ADDR_WIDTH-1 downto 0);
s_axi_control_RVALID : OUT STD_LOGIC;
s_axi_control_RREADY : IN STD_LOGIC;
s_axi_control_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_CONTROL_DATA_WIDTH-1 downto 0);
s_axi_control_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_control_BVALID : OUT STD_LOGIC;
s_axi_control_BREADY : IN STD_LOGIC;
s_axi_control_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of convolve_kernel is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"convolve_kernel,hls_ip_2017_3,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=3.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.384000,HLS_SYN_LAT=5467,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=117,HLS_SYN_FF=72137,HLS_SYN_LUT=50295}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000010";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000100";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (9 downto 0) := "0000001000";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (9 downto 0) := "0000010000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (9 downto 0) := "0000100000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (9 downto 0) := "0001000000";
constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (9 downto 0) := "0010000000";
constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (9 downto 0) := "0100000000";
constant ap_ST_fsm_state76 : STD_LOGIC_VECTOR (9 downto 0) := "1000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv10_0 : STD_LOGIC_VECTOR (9 downto 0) := "0000000000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_FFFFFFFFFFFFFFFF : STD_LOGIC_VECTOR (63 downto 0) := "1111111111111111111111111111111111111111111111111111111111111111";
constant ap_const_lv32_20 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000100000";
constant ap_const_lv32_3F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000111111";
constant ap_const_lv32_40 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001000000";
constant ap_const_lv32_5F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011111";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_7F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111111";
constant ap_const_lv32_80 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010000000";
constant ap_const_lv32_9F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010011111";
constant ap_const_lv32_A0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010100000";
constant ap_const_lv32_BF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010111111";
constant ap_const_lv32_C0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011000000";
constant ap_const_lv32_DF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011011111";
constant ap_const_lv32_E0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011100000";
constant ap_const_lv32_FF : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000011111111";
constant ap_const_lv32_100 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100000000";
constant ap_const_lv32_11F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100011111";
constant ap_const_lv32_120 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100100000";
constant ap_const_lv32_13F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000100111111";
constant ap_const_lv32_140 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101000000";
constant ap_const_lv32_15F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101011111";
constant ap_const_lv32_160 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101100000";
constant ap_const_lv32_17F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000101111111";
constant ap_const_lv32_180 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110000000";
constant ap_const_lv32_19F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000110011111";
constant ap_const_lv3_1 : STD_LOGIC_VECTOR (2 downto 0) := "001";
constant ap_const_lv3_2 : STD_LOGIC_VECTOR (2 downto 0) := "010";
constant ap_const_lv3_3 : STD_LOGIC_VECTOR (2 downto 0) := "011";
constant ap_const_lv4_4 : STD_LOGIC_VECTOR (3 downto 0) := "0100";
constant ap_const_lv4_5 : STD_LOGIC_VECTOR (3 downto 0) := "0101";
constant ap_const_lv4_6 : STD_LOGIC_VECTOR (3 downto 0) := "0110";
constant ap_const_lv4_7 : STD_LOGIC_VECTOR (3 downto 0) := "0111";
constant ap_const_lv10_2A3 : STD_LOGIC_VECTOR (9 downto 0) := "1010100011";
constant ap_const_lv10_1 : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
constant ap_const_lv8_87 : STD_LOGIC_VECTOR (7 downto 0) := "10000111";
constant ap_const_lv5_1B : STD_LOGIC_VECTOR (4 downto 0) := "11011";
constant ap_const_lv8_1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv5_1 : STD_LOGIC_VECTOR (4 downto 0) := "00001";
constant ap_const_lv6_19 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_const_lv4_0 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
constant ap_const_lv7_32 : STD_LOGIC_VECTOR (6 downto 0) := "0110010";
constant ap_const_lv3_4 : STD_LOGIC_VECTOR (2 downto 0) := "100";
constant ap_const_lv56_0 : STD_LOGIC_VECTOR (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
constant ap_const_lv8_2 : STD_LOGIC_VECTOR (7 downto 0) := "00000010";
constant ap_const_lv8_3 : STD_LOGIC_VECTOR (7 downto 0) := "00000011";
constant ap_const_lv8_4 : STD_LOGIC_VECTOR (7 downto 0) := "00000100";
constant ap_const_lv8_5 : STD_LOGIC_VECTOR (7 downto 0) := "00000101";
constant ap_const_lv8_6 : STD_LOGIC_VECTOR (7 downto 0) := "00000110";
constant ap_const_lv8_7 : STD_LOGIC_VECTOR (7 downto 0) := "00000111";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (9 downto 0) := "0000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal ap_ready : STD_LOGIC;
signal indvar_flatten1_reg_885 : STD_LOGIC_VECTOR (9 downto 0);
signal i_reg_896 : STD_LOGIC_VECTOR (2 downto 0);
signal indvar_flatten_reg_908 : STD_LOGIC_VECTOR (7 downto 0);
signal j_reg_919 : STD_LOGIC_VECTOR (2 downto 0);
signal row_b_reg_931 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_12_1_fu_1499_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_1_reg_3141 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_block_state2_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state10_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state18_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_state26_pp0_stage0_iter3 : BOOLEAN;
signal ap_block_state34_pp0_stage0_iter4 : BOOLEAN;
signal ap_block_state42_pp0_stage0_iter5 : BOOLEAN;
signal ap_block_state50_pp0_stage0_iter6 : BOOLEAN;
signal ap_block_state58_pp0_stage0_iter7 : BOOLEAN;
signal ap_block_state66_pp0_stage0_iter8 : BOOLEAN;
signal ap_block_state74_pp0_stage0_iter9 : BOOLEAN;
signal ap_block_pp0_stage0_11001 : BOOLEAN;
signal tmp_12_2_fu_1505_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_2_reg_3146 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_3_fu_1511_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_3_reg_3151 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_4_fu_1517_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_4_reg_3156 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_5_fu_1523_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_5_reg_3161 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_6_fu_1529_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_6_reg_3166 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_7_fu_1535_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_7_reg_3171 : STD_LOGIC_VECTOR (3 downto 0);
signal exitcond_flatten1_fu_1541_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter4_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter6_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_next1_fu_1547_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal indvar_flatten_next1_reg_3180 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_enable_reg_pp0_iter0 : STD_LOGIC := '0';
signal i_1_fu_1553_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal i_1_reg_3185 : STD_LOGIC_VECTOR (2 downto 0);
signal exitcond_flatten_fu_1559_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal exitcond_flatten_reg_3190 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_fu_1565_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_5_reg_3206 : STD_LOGIC_VECTOR (0 downto 0);
signal indvar_flatten_op_fu_1571_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal indvar_flatten_op_reg_3211 : STD_LOGIC_VECTOR (7 downto 0);
signal j_mid_fu_1577_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal j_mid_reg_3216 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state3_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state11_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_state19_pp0_stage1_iter2 : BOOLEAN;
signal ap_block_state27_pp0_stage1_iter3 : BOOLEAN;
signal ap_block_state35_pp0_stage1_iter4 : BOOLEAN;
signal ap_block_state43_pp0_stage1_iter5 : BOOLEAN;
signal ap_block_state51_pp0_stage1_iter6 : BOOLEAN;
signal ap_block_state59_pp0_stage1_iter7 : BOOLEAN;
signal ap_block_state67_pp0_stage1_iter8 : BOOLEAN;
signal ap_block_state75_pp0_stage1_iter9 : BOOLEAN;
signal ap_block_pp0_stage1_11001 : BOOLEAN;
signal tmp_1_mid2_v_fu_1584_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_1_mid2_v_reg_3225 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_7_mid_fu_1595_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_7_mid_reg_3233 : STD_LOGIC_VECTOR (0 downto 0);
signal row_b_mid2_fu_1605_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_mid2_reg_3245 : STD_LOGIC_VECTOR (4 downto 0);
signal ap_reg_pp0_iter1_row_b_mid2_reg_3245 : STD_LOGIC_VECTOR (4 downto 0);
signal indvar_flatten_next_fu_1613_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal indvar_flatten_next_reg_3252 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_1_fu_1633_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_1_reg_3257 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state4_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state12_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_state20_pp0_stage2_iter2 : BOOLEAN;
signal ap_block_state28_pp0_stage2_iter3 : BOOLEAN;
signal ap_block_state36_pp0_stage2_iter4 : BOOLEAN;
signal ap_block_state44_pp0_stage2_iter5 : BOOLEAN;
signal ap_block_state52_pp0_stage2_iter6 : BOOLEAN;
signal ap_block_state60_pp0_stage2_iter7 : BOOLEAN;
signal ap_block_state68_pp0_stage2_iter8 : BOOLEAN;
signal ap_block_pp0_stage2_11001 : BOOLEAN;
signal j_1_fu_1642_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal j_1_reg_3264 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_s_fu_1647_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_s_reg_3270 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_1_fu_1652_p2 : STD_LOGIC_VECTOR (4 downto 0);
signal row_b_1_reg_3276 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_2_fu_1657_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_reg_3281 : STD_LOGIC_VECTOR (5 downto 0);
signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
signal ap_block_state5_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state13_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_state21_pp0_stage3_iter2 : BOOLEAN;
signal ap_block_state29_pp0_stage3_iter3 : BOOLEAN;
signal ap_block_state37_pp0_stage3_iter4 : BOOLEAN;
signal ap_block_state45_pp0_stage3_iter5 : BOOLEAN;
signal ap_block_state53_pp0_stage3_iter6 : BOOLEAN;
signal ap_block_state61_pp0_stage3_iter7 : BOOLEAN;
signal ap_block_state69_pp0_stage3_iter8 : BOOLEAN;
signal ap_block_pp0_stage3_11001 : BOOLEAN;
signal tmp_5_mid2_fu_1662_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_5_mid2_reg_3286 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_1_mid1_fu_1667_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_1_mid1_reg_3294 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_90_fu_1694_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_90_reg_3299 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_3_fu_1706_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_3_reg_3311 : STD_LOGIC_VECTOR (6 downto 0);
signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
signal ap_block_state6_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state14_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_state22_pp0_stage4_iter2 : BOOLEAN;
signal ap_block_state30_pp0_stage4_iter3 : BOOLEAN;
signal ap_block_state38_pp0_stage4_iter4 : BOOLEAN;
signal ap_block_state46_pp0_stage4_iter5 : BOOLEAN;
signal ap_block_state54_pp0_stage4_iter6 : BOOLEAN;
signal ap_block_state62_pp0_stage4_iter7 : BOOLEAN;
signal ap_block_state70_pp0_stage4_iter8 : BOOLEAN;
signal ap_block_pp0_stage4_11001 : BOOLEAN;
signal tmp_5_mid2_cast2_fu_1721_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_5_mid2_cast2_reg_3316 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_6_fu_1727_p2 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_6_reg_3321 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_8_fu_1732_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_8_reg_3326 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_12_2_mid1_fu_1748_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_2_mid1_reg_3331 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_130_fu_1753_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_130_reg_3336 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_170_fu_1758_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_170_reg_3341 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state7_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state15_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_state23_pp0_stage5_iter2 : BOOLEAN;
signal ap_block_state31_pp0_stage5_iter3 : BOOLEAN;
signal ap_block_state39_pp0_stage5_iter4 : BOOLEAN;
signal ap_block_state47_pp0_stage5_iter5 : BOOLEAN;
signal ap_block_state55_pp0_stage5_iter6 : BOOLEAN;
signal ap_block_state63_pp0_stage5_iter7 : BOOLEAN;
signal ap_block_state71_pp0_stage5_iter8 : BOOLEAN;
signal ap_block_pp0_stage5_11001 : BOOLEAN;
signal tmp_7_fu_1807_p2 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_7_reg_3356 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_12_4_mid1_fu_1840_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_4_mid1_reg_3481 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_5_mid1_fu_1846_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_5_mid1_reg_3486 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_6_mid1_fu_1852_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_6_mid1_reg_3491 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_7_mid1_fu_1858_p2 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_12_7_mid1_reg_3496 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_210_fu_1876_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_210_reg_3511 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_250_fu_1881_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_250_reg_3516 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
signal ap_block_state8_pp0_stage6_iter0 : BOOLEAN;
signal ap_block_state16_pp0_stage6_iter1 : BOOLEAN;
signal ap_block_state24_pp0_stage6_iter2 : BOOLEAN;
signal ap_block_state32_pp0_stage6_iter3 : BOOLEAN;
signal ap_block_state40_pp0_stage6_iter4 : BOOLEAN;
signal ap_block_state48_pp0_stage6_iter5 : BOOLEAN;
signal ap_block_state56_pp0_stage6_iter6 : BOOLEAN;
signal ap_block_state64_pp0_stage6_iter7 : BOOLEAN;
signal ap_block_state72_pp0_stage6_iter8 : BOOLEAN;
signal ap_block_pp0_stage6_11001 : BOOLEAN;
signal tmp_290_fu_1978_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_290_reg_3616 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_330_fu_1983_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_330_reg_3621 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_331_fu_1988_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_331_reg_3626 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_332_fu_1993_p2 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_332_reg_3631 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
signal ap_block_state9_pp0_stage7_iter0 : BOOLEAN;
signal ap_block_state17_pp0_stage7_iter1 : BOOLEAN;
signal ap_block_state25_pp0_stage7_iter2 : BOOLEAN;
signal ap_block_state33_pp0_stage7_iter3 : BOOLEAN;
signal ap_block_state41_pp0_stage7_iter4 : BOOLEAN;
signal ap_block_state49_pp0_stage7_iter5 : BOOLEAN;
signal ap_block_state57_pp0_stage7_iter6 : BOOLEAN;
signal ap_block_state65_pp0_stage7_iter7 : BOOLEAN;
signal ap_block_state73_pp0_stage7_iter8 : BOOLEAN;
signal ap_block_pp0_stage7_11001 : BOOLEAN;
signal bufw_0_load_reg_3686 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_reg_3693 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_load_1_reg_3710 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_reg_3718 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_reg_3735 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_load_reg_3752 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_load_1_reg_3759 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_load_reg_3767 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_load_1_reg_3774 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_load_reg_3782 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_load_1_reg_3789 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_load_reg_3797 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_load_1_reg_3804 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_load_reg_3812 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_load_1_reg_3819 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_load_reg_3827 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_load_1_reg_3834 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_load_reg_3842 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_load_1_reg_3849 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_load_reg_3857 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_load_1_reg_3864 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_load_reg_3872 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_load_1_reg_3879 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_load_reg_3887 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_load_1_reg_3894 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_load_reg_3902 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_load_1_reg_3909 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_load_reg_3917 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_load_1_reg_3924 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_1_reg_3931 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_1_reg_3948 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_1_reg_3965 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_load_2_reg_4012 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal bufw_1_load_2_reg_4019 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_load_2_reg_4026 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_load_2_reg_4033 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_load_2_reg_4040 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_load_2_reg_4047 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_load_2_reg_4054 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_load_2_reg_4061 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_load_2_reg_4068 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_load_2_reg_4075 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_load_2_reg_4082 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_load_2_reg_4089 : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_load_2_reg_4096 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_2_reg_4103 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_2_reg_4120 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_2_reg_4137 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_3_reg_4154 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_3_reg_4171 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_3_reg_4188 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_4_reg_4205 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_4_reg_4222 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_4_reg_4239 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_5_reg_4256 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_5_reg_4273 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_5_reg_4290 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_333_fu_2022_p3 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_333_reg_4307 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_reg_4317 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_1_reg_4322 : STD_LOGIC_VECTOR (7 downto 0);
signal bufi_0_load_6_reg_4327 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_6_reg_4344 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_6_reg_4361 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_load_7_reg_4378 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_load_7_reg_4395 : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_load_7_reg_4412 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_2_reg_4429 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_3_reg_4434 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_4_reg_4439 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_5_reg_4444 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_350_fu_2105_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_350_reg_4449 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_13_reg_4454 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_16_reg_4459 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_reg_4464 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_reg_4469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_reg_4474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_28_reg_4479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_reg_4484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_34_reg_4489 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_37_reg_4494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_40_reg_4499 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_43_reg_4504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_46_reg_4509 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_352_fu_2109_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_352_reg_4514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_53_reg_4519 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_56_reg_4524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_59_reg_4529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_62_reg_4534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_65_reg_4539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_68_reg_4544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_71_reg_4549 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_74_reg_4554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_77_reg_4559 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_80_reg_4564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_83_reg_4569 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_86_reg_4574 : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_bufo_addr_6_reg_4579 : STD_LOGIC_VECTOR (7 downto 0);
signal bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter2_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter3_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter4_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter5_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter6_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter7_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_reg_pp0_iter8_bufo_addr_7_reg_4584 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_353_fu_2141_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_353_reg_4589 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_93_reg_4594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_96_reg_4599 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_99_reg_4604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_102_reg_4609 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_105_reg_4614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_108_reg_4619 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_111_reg_4624 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_114_reg_4629 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_117_reg_4634 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_120_reg_4639 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_123_reg_4644 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_126_reg_4649 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_354_fu_2145_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_354_reg_4654 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_133_reg_4659 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_136_reg_4664 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_139_reg_4669 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_142_reg_4674 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_145_reg_4679 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_148_reg_4684 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_151_reg_4689 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_154_reg_4694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_157_reg_4699 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_160_reg_4704 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_163_reg_4709 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_166_reg_4714 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_355_fu_2149_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_355_reg_4719 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_173_reg_4724 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_176_reg_4729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_179_reg_4734 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_182_reg_4739 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_185_reg_4744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_188_reg_4749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_191_reg_4754 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_194_reg_4759 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_197_reg_4764 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_200_reg_4769 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_203_reg_4774 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_206_reg_4779 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_356_fu_2153_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_356_reg_4784 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_213_reg_4789 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_216_reg_4794 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_219_reg_4799 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_222_reg_4804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_225_reg_4809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_228_reg_4814 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_231_reg_4819 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_234_reg_4824 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_237_reg_4829 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_240_reg_4834 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_243_reg_4839 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_246_reg_4844 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1099_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_349_reg_4849 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1103_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_0_1_reg_4854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1107_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_1_reg_4859 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1111_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_1_1_reg_4864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1115_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_2_reg_4869 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1119_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_2_1_reg_4874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1123_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_3_reg_4879 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1127_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_3_1_reg_4884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1131_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_4_reg_4889 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1135_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_4_1_reg_4894 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1139_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_5_reg_4899 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1143_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_5_1_reg_4904 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1147_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_6_reg_4909 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1151_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_6_1_reg_4914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1155_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_7_reg_4919 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1159_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_7_1_reg_4924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1163_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_8_reg_4929 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1167_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_8_1_reg_4934 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1171_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_9_reg_4939 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1175_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_9_1_reg_4944 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1179_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_s_reg_4949 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1183_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_10_1_reg_4954 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1187_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_10_reg_4959 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1191_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_11_1_reg_4964 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1195_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_11_reg_4969 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1199_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_12_1_reg_4974 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1203_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_reg_4979 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1207_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_1_reg_4984 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1211_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_2_reg_4989 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1215_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_3_reg_4994 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1219_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_4_reg_4999 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1223_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_5_reg_5004 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1227_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_6_reg_5009 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1231_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_7_reg_5014 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1235_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_8_reg_5019 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1239_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_9_reg_5024 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1243_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_s_reg_5029 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1247_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_10_reg_5034 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1251_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_11_reg_5039 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_357_fu_2157_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_357_reg_5044 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_253_reg_5049 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_256_reg_5054 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_259_reg_5059 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_262_reg_5064 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_265_reg_5069 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_268_reg_5074 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_271_reg_5079 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_274_reg_5084 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_277_reg_5089 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_280_reg_5094 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_283_reg_5099 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_286_reg_5104 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_358_fu_2161_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_358_reg_5109 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_293_reg_5114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_296_reg_5119 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_299_reg_5124 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_302_reg_5129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_305_reg_5134 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_308_reg_5139 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_311_reg_5144 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_314_reg_5149 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_317_reg_5154 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_320_reg_5159 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_323_reg_5164 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_326_reg_5169 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_11_fu_2165_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_14_fu_2169_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_17_fu_2173_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_2177_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_23_fu_2181_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_26_fu_2185_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_29_fu_2189_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_32_fu_2193_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_35_fu_2197_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_38_fu_2201_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_41_fu_2205_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_44_fu_2209_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_47_fu_2213_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_51_fu_2217_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_0_1_reg_5244 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_fu_2221_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_1_1_reg_5254 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_57_fu_2225_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_2_1_reg_5264 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_60_fu_2229_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_3_1_reg_5274 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_63_fu_2233_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_4_1_reg_5284 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_66_fu_2237_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_5_1_reg_5294 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_69_fu_2241_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_6_1_reg_5304 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_72_fu_2245_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_7_1_reg_5314 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_75_fu_2249_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_8_1_reg_5324 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_78_fu_2253_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_9_1_reg_5334 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_81_fu_2257_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_10_1_reg_5344 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_84_fu_2261_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_11_1_reg_5354 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_87_fu_2265_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_12_1_reg_5364 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_reg_5369 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_1_reg_5374 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_2_reg_5379 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_3_reg_5384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_4_reg_5389 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_5_reg_5394 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_6_reg_5399 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_7_reg_5404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_8_reg_5409 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_9_reg_5414 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_s_reg_5419 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_10_reg_5424 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_11_reg_5429 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_reg_5434 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_1_reg_5439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_2_reg_5444 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_3_reg_5449 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_4_reg_5454 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_5_reg_5459 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_6_reg_5464 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_7_reg_5469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_8_reg_5474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_9_reg_5479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_s_reg_5484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_10_reg_5489 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_11_reg_5494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_91_fu_2269_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_0_1_reg_5504 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_94_fu_2273_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_1_1_reg_5514 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_97_fu_2277_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_2_1_reg_5524 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_100_fu_2281_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_3_1_reg_5534 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_103_fu_2285_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_4_1_reg_5544 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_106_fu_2289_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_5_1_reg_5554 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_109_fu_2293_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_6_1_reg_5564 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_112_fu_2297_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_7_1_reg_5574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_115_fu_2301_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_8_1_reg_5584 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_118_fu_2305_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_9_1_reg_5594 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_121_fu_2309_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_10_1_reg_5604 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_124_fu_2313_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_11_1_reg_5614 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_127_fu_2317_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_12_1_reg_5624 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_131_fu_2321_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_134_fu_2325_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_137_fu_2329_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_140_fu_2333_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_143_fu_2337_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_146_fu_2341_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_149_fu_2345_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_152_fu_2349_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_155_fu_2353_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_158_fu_2357_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_161_fu_2361_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_164_fu_2365_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_167_fu_2369_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_reg_5694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_1_reg_5699 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_2_reg_5704 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_3_reg_5709 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_4_reg_5714 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_5_reg_5719 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_6_reg_5724 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_7_reg_5729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_8_reg_5734 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_9_reg_5739 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_s_reg_5744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_10_reg_5749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_11_reg_5754 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_reg_5759 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_1_reg_5764 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_2_reg_5769 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_3_reg_5774 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_4_reg_5779 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_5_reg_5784 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_6_reg_5789 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_7_reg_5794 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_8_reg_5799 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_9_reg_5804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_s_reg_5809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_10_reg_5814 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_11_reg_5819 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_0_1_reg_5824 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_1_1_reg_5829 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_2_1_reg_5834 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_3_1_reg_5839 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_4_1_reg_5844 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_5_1_reg_5849 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_6_1_reg_5854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_7_1_reg_5859 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_8_1_reg_5864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_9_1_reg_5869 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_10_1_reg_5874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_11_1_reg_5879 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_12_1_reg_5884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_171_fu_2373_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_174_fu_2377_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_177_fu_2381_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_180_fu_2385_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_183_fu_2389_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_186_fu_2393_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_189_fu_2397_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_192_fu_2401_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_195_fu_2405_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_198_fu_2409_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_201_fu_2413_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_204_fu_2417_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_207_fu_2421_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_211_fu_2425_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_214_fu_2429_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_217_fu_2433_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_220_fu_2437_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_223_fu_2441_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_226_fu_2445_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_229_fu_2449_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_232_fu_2453_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_235_fu_2457_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_238_fu_2461_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_241_fu_2465_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_244_fu_2469_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_247_fu_2473_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_reg_6019 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_1_reg_6024 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_2_reg_6029 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_3_reg_6034 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_4_reg_6039 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_5_reg_6044 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_6_reg_6049 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_7_reg_6054 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_8_reg_6059 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_9_reg_6064 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_s_reg_6069 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_10_reg_6074 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_11_reg_6079 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_reg_6084 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_1_reg_6089 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_2_reg_6094 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_3_reg_6099 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_4_reg_6104 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_5_reg_6109 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_6_reg_6114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_7_reg_6119 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_8_reg_6124 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_9_reg_6129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_s_reg_6134 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_10_reg_6139 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_11_reg_6144 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_0_1_reg_6149 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_1_1_reg_6154 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_2_1_reg_6159 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_3_1_reg_6164 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_4_1_reg_6169 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_5_1_reg_6174 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_6_1_reg_6179 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_7_1_reg_6184 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_8_1_reg_6189 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_9_1_reg_6194 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_10_1_reg_6199 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_11_1_reg_6204 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_12_1_reg_6209 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_0_1_reg_6214 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_1_1_reg_6219 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_2_1_reg_6224 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_3_1_reg_6229 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_4_1_reg_6234 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_5_1_reg_6239 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_6_1_reg_6244 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_7_1_reg_6249 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_8_1_reg_6254 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_9_1_reg_6259 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_10_1_reg_6264 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_11_1_reg_6269 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_12_1_reg_6274 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_251_fu_2477_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_0_1_reg_6284 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_254_fu_2481_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_1_1_reg_6294 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_257_fu_2485_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_2_1_reg_6304 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_260_fu_2489_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_3_1_reg_6314 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_263_fu_2493_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_4_1_reg_6324 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_266_fu_2497_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_5_1_reg_6334 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_269_fu_2501_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_6_1_reg_6344 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_272_fu_2505_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_7_1_reg_6354 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_275_fu_2509_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_8_1_reg_6364 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_278_fu_2513_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_9_1_reg_6374 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_281_fu_2517_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_10_1_reg_6384 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_284_fu_2521_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_11_1_reg_6394 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_287_fu_2525_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_12_1_reg_6404 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_291_fu_2529_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_294_fu_2533_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_297_fu_2537_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_300_fu_2541_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_303_fu_2545_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_306_fu_2549_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_309_fu_2553_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_312_fu_2557_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_315_fu_2561_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_318_fu_2565_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_321_fu_2569_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_324_fu_2573_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_327_fu_2577_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_0_2_reg_6474 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_0_2_reg_6474 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_1_2_reg_6479 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_1_2_reg_6479 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_2_2_reg_6484 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_2_2_reg_6484 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_3_2_reg_6489 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_3_2_reg_6489 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_4_2_reg_6494 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_4_2_reg_6494 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_5_2_reg_6499 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_5_2_reg_6499 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_6_2_reg_6504 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_6_2_reg_6504 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_7_2_reg_6509 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_7_2_reg_6509 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_8_2_reg_6514 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_8_2_reg_6514 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_9_2_reg_6519 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_9_2_reg_6519 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_10_2_reg_6524 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_10_2_reg_6524 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_11_2_reg_6529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_11_2_reg_6529 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_0_12_2_reg_6534 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_0_12_2_reg_6534 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_0_2_reg_6539 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_0_2_reg_6539 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_1_2_reg_6544 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_1_2_reg_6544 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_2_2_reg_6549 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_2_2_reg_6549 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_3_2_reg_6554 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_3_2_reg_6554 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_4_2_reg_6559 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_4_2_reg_6559 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_5_2_reg_6564 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_5_2_reg_6564 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_6_2_reg_6569 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_6_2_reg_6569 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_7_2_reg_6574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_7_2_reg_6574 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_8_2_reg_6579 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_8_2_reg_6579 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_9_2_reg_6584 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_9_2_reg_6584 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_10_2_reg_6589 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_10_2_reg_6589 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_11_2_reg_6594 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_11_2_reg_6594 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_1_12_2_reg_6599 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_1_12_2_reg_6599 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_0_1_reg_6604 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_1_1_reg_6609 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_2_1_reg_6614 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_3_1_reg_6619 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_4_1_reg_6624 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_5_1_reg_6629 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_6_1_reg_6634 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_7_1_reg_6639 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_8_1_reg_6644 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_9_1_reg_6649 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_10_1_reg_6654 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_11_1_reg_6659 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_12_1_reg_6664 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_0_2_reg_6669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_0_2_reg_6669 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_1_2_reg_6674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_1_2_reg_6674 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_2_2_reg_6679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_2_2_reg_6679 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_3_2_reg_6684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_3_2_reg_6684 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_4_2_reg_6689 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_4_2_reg_6689 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_5_2_reg_6694 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_5_2_reg_6694 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_6_2_reg_6699 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_6_2_reg_6699 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_7_2_reg_6704 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_7_2_reg_6704 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_8_2_reg_6709 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_8_2_reg_6709 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_9_2_reg_6714 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_9_2_reg_6714 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_10_2_reg_6719 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_10_2_reg_6719 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_11_2_reg_6724 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_11_2_reg_6724 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_2_12_2_reg_6729 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_2_12_2_reg_6729 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_0_2_reg_6734 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_0_2_reg_6734 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_1_2_reg_6739 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_1_2_reg_6739 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_2_2_reg_6744 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_2_2_reg_6744 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_3_2_reg_6749 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_3_2_reg_6749 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_4_2_reg_6754 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_4_2_reg_6754 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_5_2_reg_6759 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_5_2_reg_6759 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_6_2_reg_6764 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_6_2_reg_6764 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_7_2_reg_6769 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_7_2_reg_6769 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_8_2_reg_6774 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_8_2_reg_6774 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_9_2_reg_6779 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_9_2_reg_6779 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_10_2_reg_6784 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_10_2_reg_6784 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_11_2_reg_6789 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_11_2_reg_6789 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_3_12_2_reg_6794 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_3_12_2_reg_6794 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_0_2_reg_6799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_0_2_reg_6799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_0_2_reg_6799 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_1_2_reg_6804 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_1_2_reg_6804 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_1_2_reg_6804 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_2_2_reg_6809 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_2_2_reg_6809 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_2_2_reg_6809 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_3_2_reg_6814 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_3_2_reg_6814 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_3_2_reg_6814 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_4_2_reg_6819 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_4_2_reg_6819 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_4_2_reg_6819 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_5_2_reg_6824 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_5_2_reg_6824 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_5_2_reg_6824 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_6_2_reg_6829 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_6_2_reg_6829 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_6_2_reg_6829 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_7_2_reg_6834 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_7_2_reg_6834 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_7_2_reg_6834 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_8_2_reg_6839 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_8_2_reg_6839 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_8_2_reg_6839 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_9_2_reg_6844 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_9_2_reg_6844 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_9_2_reg_6844 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_10_2_reg_6849 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_10_2_reg_6849 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_10_2_reg_6849 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_11_2_reg_6854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_11_2_reg_6854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_11_2_reg_6854 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_4_12_2_reg_6859 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_4_12_2_reg_6859 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_4_12_2_reg_6859 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_0_2_reg_6864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_0_2_reg_6864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_0_2_reg_6864 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_1_2_reg_6869 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_1_2_reg_6869 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_1_2_reg_6869 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_2_2_reg_6874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_2_2_reg_6874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_2_2_reg_6874 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_3_2_reg_6879 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_3_2_reg_6879 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_3_2_reg_6879 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_4_2_reg_6884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_4_2_reg_6884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_4_2_reg_6884 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_5_2_reg_6889 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_5_2_reg_6889 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_5_2_reg_6889 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_6_2_reg_6894 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_6_2_reg_6894 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_6_2_reg_6894 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_7_2_reg_6899 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_7_2_reg_6899 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_7_2_reg_6899 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_8_2_reg_6904 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_8_2_reg_6904 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_8_2_reg_6904 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_9_2_reg_6909 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_9_2_reg_6909 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_9_2_reg_6909 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_10_2_reg_6914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_10_2_reg_6914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_10_2_reg_6914 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_11_2_reg_6919 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_11_2_reg_6919 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_11_2_reg_6919 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_5_12_2_reg_6924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_5_12_2_reg_6924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_5_12_2_reg_6924 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_0_2_reg_6929 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_0_2_reg_6929 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_0_2_reg_6929 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_1_2_reg_6934 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_1_2_reg_6934 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_1_2_reg_6934 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_2_2_reg_6939 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_2_2_reg_6939 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_2_2_reg_6939 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_3_2_reg_6944 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_3_2_reg_6944 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_3_2_reg_6944 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_4_2_reg_6949 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_4_2_reg_6949 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_4_2_reg_6949 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_5_2_reg_6954 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_5_2_reg_6954 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_5_2_reg_6954 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_6_2_reg_6959 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_6_2_reg_6959 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_6_2_reg_6959 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_7_2_reg_6964 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_7_2_reg_6964 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_7_2_reg_6964 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_8_2_reg_6969 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_8_2_reg_6969 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_8_2_reg_6969 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_9_2_reg_6974 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_9_2_reg_6974 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_9_2_reg_6974 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_10_2_reg_6979 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_10_2_reg_6979 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_10_2_reg_6979 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_11_2_reg_6984 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_11_2_reg_6984 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_11_2_reg_6984 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_6_12_2_reg_6989 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_6_12_2_reg_6989 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_6_12_2_reg_6989 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_0_2_reg_6994 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_0_2_reg_6994 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_0_2_reg_6994 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_1_2_reg_6999 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_1_2_reg_6999 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_1_2_reg_6999 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_2_2_reg_7004 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_2_2_reg_7004 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_2_2_reg_7004 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_3_2_reg_7009 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_3_2_reg_7009 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_3_2_reg_7009 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_4_2_reg_7014 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_4_2_reg_7014 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_4_2_reg_7014 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_5_2_reg_7019 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_5_2_reg_7019 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_5_2_reg_7019 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_6_2_reg_7024 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_6_2_reg_7024 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_6_2_reg_7024 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_7_2_reg_7029 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_7_2_reg_7029 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_7_2_reg_7029 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_8_2_reg_7034 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_8_2_reg_7034 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_8_2_reg_7034 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_9_2_reg_7039 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_9_2_reg_7039 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_9_2_reg_7039 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_10_2_reg_7044 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_10_2_reg_7044 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_10_2_reg_7044 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_11_2_reg_7049 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_11_2_reg_7049 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_11_2_reg_7049 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_19_7_12_2_reg_7054 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter3_tmp_19_7_12_2_reg_7054 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter4_tmp_19_7_12_2_reg_7054 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_943_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_351_reg_7059 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter3 : STD_LOGIC := '0';
signal grp_fu_947_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_1_reg_7064 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_951_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_2_reg_7069 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_955_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_3_reg_7074 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_959_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_4_reg_7079 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_963_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_5_reg_7084 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_967_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_6_reg_7089 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_971_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_7_reg_7094 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_975_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_8_reg_7099 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_979_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_9_reg_7104 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_983_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_s_reg_7109 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_987_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_10_reg_7114 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_991_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_11_reg_7119 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_995_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_reg_7124 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_999_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_1_reg_7129 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1003_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_2_reg_7134 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1007_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_3_reg_7139 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1011_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_4_reg_7144 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1015_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_5_reg_7149 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1019_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_6_reg_7154 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1023_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_7_reg_7159 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1027_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_8_reg_7164 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1031_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_9_reg_7169 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1035_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_s_reg_7174 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1039_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_10_reg_7179 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1043_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_11_reg_7184 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_reg_7189 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_1_reg_7194 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_2_reg_7199 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_3_reg_7204 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_4_reg_7209 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_5_reg_7214 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_6_reg_7219 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_7_reg_7224 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_8_reg_7229 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_9_reg_7234 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_s_reg_7239 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_10_reg_7244 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_11_reg_7249 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_reg_7254 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_1_reg_7259 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_2_reg_7264 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_3_reg_7269 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_4_reg_7274 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_5_reg_7279 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_6_reg_7284 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_7_reg_7289 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_8_reg_7294 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_9_reg_7299 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_s_reg_7304 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_10_reg_7309 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_11_reg_7314 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_reg_7319 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_1_reg_7324 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_2_reg_7329 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_3_reg_7334 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_4_reg_7339 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_5_reg_7344 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_6_reg_7349 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_7_reg_7354 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_8_reg_7359 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_9_reg_7364 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_s_reg_7369 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_10_reg_7374 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_11_reg_7379 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_reg_7384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_1_reg_7389 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_2_reg_7394 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_3_reg_7399 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_4_reg_7404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_5_reg_7409 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_6_reg_7414 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_7_reg_7419 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_8_reg_7424 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_9_reg_7429 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_s_reg_7434 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_10_reg_7439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_11_reg_7444 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_reg_7449 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter4 : STD_LOGIC := '0';
signal tmp_20_6_1_reg_7454 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_2_reg_7459 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_3_reg_7464 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_4_reg_7469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_5_reg_7474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_6_reg_7479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_7_reg_7484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_8_reg_7489 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_9_reg_7494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_s_reg_7499 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_10_reg_7504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_11_reg_7509 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_reg_7514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_1_reg_7519 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_2_reg_7524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_3_reg_7529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_4_reg_7534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_5_reg_7539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_6_reg_7544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_7_reg_7549 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_8_reg_7554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_9_reg_7559 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_s_reg_7564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_10_reg_7569 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_11_reg_7574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_0_1_reg_7579 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter5 : STD_LOGIC := '0';
signal tmp_20_0_1_1_reg_7584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_2_1_reg_7589 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_3_1_reg_7594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_4_1_reg_7599 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_5_1_reg_7604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_6_1_reg_7609 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_7_1_reg_7614 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_8_1_reg_7619 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_9_1_reg_7624 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_10_1_reg_7629 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_11_1_reg_7634 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_12_1_reg_7639 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_0_1_reg_7644 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_1_1_reg_7649 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_2_1_reg_7654 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_3_1_reg_7659 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_4_1_reg_7664 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_5_1_reg_7669 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_6_1_reg_7674 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_7_1_reg_7679 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_8_1_reg_7684 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_9_1_reg_7689 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_10_1_reg_7694 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_11_1_reg_7699 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_12_1_reg_7704 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_0_1_reg_7709 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_1_1_reg_7714 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_2_1_reg_7719 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_3_1_reg_7724 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_4_1_reg_7729 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_5_1_reg_7734 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_6_1_reg_7739 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_7_1_reg_7744 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_8_1_reg_7749 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_9_1_reg_7754 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_10_1_reg_7759 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_11_1_reg_7764 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_12_1_reg_7769 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_0_1_reg_7774 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_1_1_reg_7779 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_2_1_reg_7784 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_3_1_reg_7789 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_4_1_reg_7794 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_5_1_reg_7799 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_6_1_reg_7804 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_7_1_reg_7809 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_8_1_reg_7814 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_9_1_reg_7819 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_10_1_reg_7824 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_11_1_reg_7829 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_12_1_reg_7834 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1047_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_0_1_reg_7839 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1051_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_1_1_reg_7844 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1055_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_2_1_reg_7849 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1059_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_3_1_reg_7854 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1063_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_4_1_reg_7859 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1067_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_5_1_reg_7864 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1071_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_6_1_reg_7869 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1075_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_7_1_reg_7874 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1079_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_8_1_reg_7879 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1083_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_9_1_reg_7884 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1087_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_10_1_reg_7889 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1091_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_11_1_reg_7894 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1095_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_12_1_reg_7899 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_0_1_reg_7904 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_1_1_reg_7909 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_2_1_reg_7914 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_3_1_reg_7919 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_4_1_reg_7924 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_5_1_reg_7929 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_6_1_reg_7934 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_7_1_reg_7939 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_8_1_reg_7944 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_9_1_reg_7949 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_10_1_reg_7954 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_11_1_reg_7959 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_12_1_reg_7964 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_0_1_reg_7969 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_1_1_reg_7974 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_2_1_reg_7979 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_3_1_reg_7984 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_4_1_reg_7989 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_5_1_reg_7994 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_6_1_reg_7999 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_7_1_reg_8004 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_8_1_reg_8009 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_9_1_reg_8014 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_10_1_reg_8019 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_11_1_reg_8024 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_12_1_reg_8029 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_0_1_reg_8034 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter6 : STD_LOGIC := '0';
signal tmp_20_7_1_1_reg_8039 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_2_1_reg_8044 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_3_1_reg_8049 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_4_1_reg_8054 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_5_1_reg_8059 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_6_1_reg_8064 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_7_1_reg_8069 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_8_1_reg_8074 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_9_1_reg_8079 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_10_1_reg_8084 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_11_1_reg_8089 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_12_1_reg_8094 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_0_2_reg_8099 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter7 : STD_LOGIC := '0';
signal tmp_20_0_1_2_reg_8104 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_2_2_reg_8109 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_3_2_reg_8114 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_4_2_reg_8119 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_5_2_reg_8124 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_6_2_reg_8129 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_7_2_reg_8134 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_8_2_reg_8139 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_9_2_reg_8144 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_10_2_reg_8149 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_11_2_reg_8154 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_0_12_2_reg_8159 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_0_2_reg_8164 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_1_2_reg_8169 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_2_2_reg_8174 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_3_2_reg_8179 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_4_2_reg_8184 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_5_2_reg_8189 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_6_2_reg_8194 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_7_2_reg_8199 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_8_2_reg_8204 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_9_2_reg_8209 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_10_2_reg_8214 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_11_2_reg_8219 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_1_12_2_reg_8224 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_0_2_reg_8229 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_1_2_reg_8234 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_2_2_reg_8239 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_3_2_reg_8244 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_4_2_reg_8249 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_5_2_reg_8254 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_6_2_reg_8259 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_7_2_reg_8264 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_8_2_reg_8269 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_9_2_reg_8274 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_10_2_reg_8279 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_11_2_reg_8284 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_2_12_2_reg_8289 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_0_2_reg_8294 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_1_2_reg_8299 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_2_2_reg_8304 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_3_2_reg_8309 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_4_2_reg_8314 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_5_2_reg_8319 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_6_2_reg_8324 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_7_2_reg_8329 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_8_2_reg_8334 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_9_2_reg_8339 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_10_2_reg_8344 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_11_2_reg_8349 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_3_12_2_reg_8354 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_0_2_reg_8359 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_1_2_reg_8364 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_2_2_reg_8369 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_3_2_reg_8374 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_4_2_reg_8379 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_5_2_reg_8384 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_6_2_reg_8389 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_7_2_reg_8394 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_8_2_reg_8399 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_9_2_reg_8404 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_10_2_reg_8409 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_11_2_reg_8414 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_4_12_2_reg_8419 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_0_2_reg_8424 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_1_2_reg_8429 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_2_2_reg_8434 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_3_2_reg_8439 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_4_2_reg_8444 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_5_2_reg_8449 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_6_2_reg_8454 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_7_2_reg_8459 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_8_2_reg_8464 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_9_2_reg_8469 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_10_2_reg_8474 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_11_2_reg_8479 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_5_12_2_reg_8484 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_0_2_reg_8489 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_enable_reg_pp0_iter8 : STD_LOGIC := '0';
signal tmp_20_6_1_2_reg_8494 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_2_2_reg_8499 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_3_2_reg_8504 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_4_2_reg_8509 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_5_2_reg_8514 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_6_2_reg_8519 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_7_2_reg_8524 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_8_2_reg_8529 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_9_2_reg_8534 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_10_2_reg_8539 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_11_2_reg_8544 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_6_12_2_reg_8549 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_0_2_reg_8554 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_1_2_reg_8559 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_2_2_reg_8564 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_3_2_reg_8569 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_4_2_reg_8574 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_5_2_reg_8579 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_6_2_reg_8584 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_7_2_reg_8589 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_8_2_reg_8594 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_9_2_reg_8599 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_10_2_reg_8604 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_11_2_reg_8609 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_7_12_2_reg_8614 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_pp0_stage0_subdone : BOOLEAN;
signal ap_condition_pp0_exit_iter0_state2 : STD_LOGIC;
signal ap_block_pp0_stage7_subdone : BOOLEAN;
signal ap_block_pp0_stage1_subdone : BOOLEAN;
signal ap_enable_reg_pp0_iter9 : STD_LOGIC := '0';
signal ap_phi_mux_indvar_flatten1_phi_fu_889_p4 : STD_LOGIC_VECTOR (9 downto 0);
signal ap_block_pp0_stage0 : BOOLEAN;
signal ap_phi_mux_i_phi_fu_900_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_phi_mux_indvar_flatten_phi_fu_912_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_phi_mux_j_phi_fu_923_p4 : STD_LOGIC_VECTOR (2 downto 0);
signal ap_phi_mux_row_b_phi_fu_935_p4 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_6_cast_fu_1775_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage5 : BOOLEAN;
signal tmp_8_cast_fu_1791_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_334_cast_fu_1864_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_335_cast_fu_1870_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_330_cast_fu_1910_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage6 : BOOLEAN;
signal tmp_336_cast_fu_1966_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_337_cast_fu_1972_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_338_cast_fu_1998_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage7 : BOOLEAN;
signal tmp_339_cast_fu_2004_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_340_cast_fu_2010_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_341_cast_fu_2016_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_334_fu_2029_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage2 : BOOLEAN;
signal tmp_336_fu_2040_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_338_fu_2054_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage3 : BOOLEAN;
signal tmp_340_fu_2068_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_342_fu_2082_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_block_pp0_stage4 : BOOLEAN;
signal tmp_344_fu_2096_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_346_fu_2118_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_348_fu_2132_p3 : STD_LOGIC_VECTOR (63 downto 0);
signal bufw_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_0_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_0_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_1_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufi_2_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_1_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_2_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_3_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_4_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_5_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_6_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_7_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_8_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_9_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_10_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_11_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufw_12_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_Addr_A_orig : STD_LOGIC_VECTOR (31 downto 0);
signal bufo_Addr_B_orig : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_49_fu_2620_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_89_fu_2690_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_129_fu_2760_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_169_fu_2830_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_209_fu_2900_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_249_fu_2970_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_289_fu_3040_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal ap_block_pp0_stage1 : BOOLEAN;
signal tmp_329_fu_3110_p14 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_943_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_943_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_947_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_947_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_951_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_951_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_955_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_955_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_959_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_959_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_963_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_963_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_967_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_967_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_971_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_971_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_975_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_975_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_979_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_979_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_983_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_983_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_987_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_987_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_991_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_991_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_995_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_995_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_999_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_999_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1003_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1003_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1007_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1007_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1011_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1011_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1015_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1015_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1019_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1019_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1023_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1023_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1027_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1027_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1031_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1031_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1035_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1035_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1039_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1039_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1043_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1043_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1047_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1047_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1051_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1051_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1055_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1055_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1059_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1059_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1063_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1063_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1067_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1067_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1071_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1071_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1075_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1075_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1079_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1079_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1083_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1083_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1087_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1087_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1091_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1091_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1095_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1095_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1099_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1099_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1103_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1103_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1107_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1107_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1111_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1111_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1115_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1115_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1119_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1119_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1123_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1123_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1127_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1127_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1131_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1131_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1135_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1135_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1139_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1139_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1143_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1143_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1147_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1147_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1151_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1151_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1155_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1155_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1159_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1159_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1163_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1163_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1167_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1167_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1171_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1171_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1175_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1175_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1179_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1179_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1183_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1183_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1187_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1187_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1191_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1191_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1195_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1195_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1199_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1199_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1203_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1203_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1207_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1207_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1211_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1211_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1215_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1215_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1219_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1219_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1223_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1223_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1227_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1227_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1231_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1231_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1235_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1235_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1239_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1239_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1243_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1243_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1247_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1247_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1251_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1251_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_1255_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1265_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1275_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1285_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1295_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1305_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1315_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1325_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1335_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1345_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1355_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1365_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1375_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1385_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1395_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1405_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1415_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1425_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1435_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1445_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1455_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1465_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1475_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal grp_fu_1485_p1 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_6_cast2_fu_1495_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal not_exitcond_flatten_fu_1590_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_1600_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_fu_1622_p3 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_1_mid2_cast_fu_1619_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl2_cast_fu_1629_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_cast_mid2_fu_1639_p1 : STD_LOGIC_VECTOR (4 downto 0);
signal tmp_10_fu_1672_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_50_fu_1683_p3 : STD_LOGIC_VECTOR (6 downto 0);
signal p_shl_cast_fu_1679_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal p_shl1_cast_fu_1690_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_1_cast_fu_1700_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_5_mid2_cast_fu_1724_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal tmp_2_cast_fu_1703_p1 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_13_1_mid_fu_1712_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_13_1_mid2_fu_1738_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_5_mid2_cast1_fu_1718_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_1_mid2_cast_fu_1744_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_2_mid_fu_1763_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_13_2_mid2_fu_1814_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_12_3_mid1_fu_1824_p2 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_13_3_mid_fu_1769_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_13_3_mid2_fu_1829_p3 : STD_LOGIC_VECTOR (2 downto 0);
signal tmp_6_cast2_mid1_fu_1811_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_2_mid2_cast_fu_1820_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_3_mid2_cast_fu_1836_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_4_mid_fu_1886_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_4_mid2_fu_1926_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_5_mid_fu_1892_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_5_mid2_fu_1936_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_6_mid_fu_1898_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_6_mid2_fu_1946_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_7_mid_fu_1904_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_7_mid2_fu_1956_p3 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_13_4_mid2_cast_fu_1932_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_5_mid2_cast_fu_1942_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_6_mid2_cast_fu_1952_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_13_7_mid2_cast_fu_1962_p1 : STD_LOGIC_VECTOR (9 downto 0);
signal tmp_335_fu_2034_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_337_fu_2049_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_339_fu_2063_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_341_fu_2077_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_343_fu_2091_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_350_fu_2105_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_352_fu_2109_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_345_fu_2113_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_347_fu_2127_p2 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_353_fu_2141_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_354_fu_2145_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_355_fu_2149_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_356_fu_2153_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_357_fu_2157_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_358_fu_2161_p0 : STD_LOGIC_VECTOR (415 downto 0);
signal tmp_48_fu_2617_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_45_fu_2614_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_42_fu_2611_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_39_fu_2608_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_36_fu_2605_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_33_fu_2602_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_30_fu_2599_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_fu_2596_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_24_fu_2593_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_21_fu_2590_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_18_fu_2587_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_15_fu_2584_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_12_fu_2581_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_88_fu_2687_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_85_fu_2684_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_82_fu_2681_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_79_fu_2678_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_76_fu_2675_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_73_fu_2672_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_70_fu_2669_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_67_fu_2666_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_64_fu_2663_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_61_fu_2660_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_58_fu_2657_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_55_fu_2654_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_52_fu_2651_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_128_fu_2757_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_125_fu_2754_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_122_fu_2751_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_119_fu_2748_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_116_fu_2745_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_113_fu_2742_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_110_fu_2739_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_107_fu_2736_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_104_fu_2733_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_101_fu_2730_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_98_fu_2727_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_95_fu_2724_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_92_fu_2721_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_168_fu_2827_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_165_fu_2824_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_162_fu_2821_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_159_fu_2818_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_156_fu_2815_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_153_fu_2812_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_150_fu_2809_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_147_fu_2806_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_144_fu_2803_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_141_fu_2800_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_138_fu_2797_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_135_fu_2794_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_132_fu_2791_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_208_fu_2897_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_205_fu_2894_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_202_fu_2891_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_199_fu_2888_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_196_fu_2885_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_193_fu_2882_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_190_fu_2879_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_187_fu_2876_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_184_fu_2873_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_181_fu_2870_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_178_fu_2867_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_175_fu_2864_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_172_fu_2861_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_248_fu_2967_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_245_fu_2964_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_242_fu_2961_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_239_fu_2958_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_236_fu_2955_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_233_fu_2952_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_230_fu_2949_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_227_fu_2946_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_224_fu_2943_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_221_fu_2940_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_218_fu_2937_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_215_fu_2934_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_212_fu_2931_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_288_fu_3037_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_285_fu_3034_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_282_fu_3031_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_279_fu_3028_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_276_fu_3025_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_273_fu_3022_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_270_fu_3019_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_267_fu_3016_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_264_fu_3013_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_261_fu_3010_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_258_fu_3007_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_255_fu_3004_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_252_fu_3001_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_328_fu_3107_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_325_fu_3104_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_322_fu_3101_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_319_fu_3098_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_316_fu_3095_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_313_fu_3092_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_310_fu_3089_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_307_fu_3086_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_304_fu_3083_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_301_fu_3080_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_298_fu_3077_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_295_fu_3074_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_292_fu_3071_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_CS_fsm_state76 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state76 : signal is "none";
signal ap_NS_fsm : STD_LOGIC_VECTOR (9 downto 0);
signal ap_block_pp0_stage2_subdone : BOOLEAN;
signal ap_block_pp0_stage3_subdone : BOOLEAN;
signal ap_block_pp0_stage4_subdone : BOOLEAN;
signal ap_block_pp0_stage5_subdone : BOOLEAN;
signal ap_block_pp0_stage6_subdone : BOOLEAN;
signal ap_idle_pp0 : STD_LOGIC;
signal ap_enable_pp0 : STD_LOGIC;
component convolve_kernel_fbkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_fcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component convolve_kernel_control_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC );
end component;
begin
convolve_kernel_control_s_axi_U : component convolve_kernel_control_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_CONTROL_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_CONTROL_DATA_WIDTH)
port map (
AWVALID => s_axi_control_AWVALID,
AWREADY => s_axi_control_AWREADY,
AWADDR => s_axi_control_AWADDR,
WVALID => s_axi_control_WVALID,
WREADY => s_axi_control_WREADY,
WDATA => s_axi_control_WDATA,
WSTRB => s_axi_control_WSTRB,
ARVALID => s_axi_control_ARVALID,
ARREADY => s_axi_control_ARREADY,
ARADDR => s_axi_control_ARADDR,
RVALID => s_axi_control_RVALID,
RREADY => s_axi_control_RREADY,
RDATA => s_axi_control_RDATA,
RRESP => s_axi_control_RRESP,
BVALID => s_axi_control_BVALID,
BREADY => s_axi_control_BREADY,
BRESP => s_axi_control_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ap_const_logic_1,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle);
convolve_kernel_fbkb_U1 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_943_p0,
din1 => grp_fu_943_p1,
ce => ap_const_logic_1,
dout => grp_fu_943_p2);
convolve_kernel_fbkb_U2 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_947_p0,
din1 => grp_fu_947_p1,
ce => ap_const_logic_1,
dout => grp_fu_947_p2);
convolve_kernel_fbkb_U3 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_951_p0,
din1 => grp_fu_951_p1,
ce => ap_const_logic_1,
dout => grp_fu_951_p2);
convolve_kernel_fbkb_U4 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_955_p0,
din1 => grp_fu_955_p1,
ce => ap_const_logic_1,
dout => grp_fu_955_p2);
convolve_kernel_fbkb_U5 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_959_p0,
din1 => grp_fu_959_p1,
ce => ap_const_logic_1,
dout => grp_fu_959_p2);
convolve_kernel_fbkb_U6 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_963_p0,
din1 => grp_fu_963_p1,
ce => ap_const_logic_1,
dout => grp_fu_963_p2);
convolve_kernel_fbkb_U7 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_967_p0,
din1 => grp_fu_967_p1,
ce => ap_const_logic_1,
dout => grp_fu_967_p2);
convolve_kernel_fbkb_U8 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_971_p0,
din1 => grp_fu_971_p1,
ce => ap_const_logic_1,
dout => grp_fu_971_p2);
convolve_kernel_fbkb_U9 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_975_p0,
din1 => grp_fu_975_p1,
ce => ap_const_logic_1,
dout => grp_fu_975_p2);
convolve_kernel_fbkb_U10 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_979_p0,
din1 => grp_fu_979_p1,
ce => ap_const_logic_1,
dout => grp_fu_979_p2);
convolve_kernel_fbkb_U11 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_983_p0,
din1 => grp_fu_983_p1,
ce => ap_const_logic_1,
dout => grp_fu_983_p2);
convolve_kernel_fbkb_U12 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_987_p0,
din1 => grp_fu_987_p1,
ce => ap_const_logic_1,
dout => grp_fu_987_p2);
convolve_kernel_fbkb_U13 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_991_p0,
din1 => grp_fu_991_p1,
ce => ap_const_logic_1,
dout => grp_fu_991_p2);
convolve_kernel_fbkb_U14 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_995_p0,
din1 => grp_fu_995_p1,
ce => ap_const_logic_1,
dout => grp_fu_995_p2);
convolve_kernel_fbkb_U15 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_999_p0,
din1 => grp_fu_999_p1,
ce => ap_const_logic_1,
dout => grp_fu_999_p2);
convolve_kernel_fbkb_U16 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1003_p0,
din1 => grp_fu_1003_p1,
ce => ap_const_logic_1,
dout => grp_fu_1003_p2);
convolve_kernel_fbkb_U17 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1007_p0,
din1 => grp_fu_1007_p1,
ce => ap_const_logic_1,
dout => grp_fu_1007_p2);
convolve_kernel_fbkb_U18 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1011_p0,
din1 => grp_fu_1011_p1,
ce => ap_const_logic_1,
dout => grp_fu_1011_p2);
convolve_kernel_fbkb_U19 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1015_p0,
din1 => grp_fu_1015_p1,
ce => ap_const_logic_1,
dout => grp_fu_1015_p2);
convolve_kernel_fbkb_U20 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1019_p0,
din1 => grp_fu_1019_p1,
ce => ap_const_logic_1,
dout => grp_fu_1019_p2);
convolve_kernel_fbkb_U21 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1023_p0,
din1 => grp_fu_1023_p1,
ce => ap_const_logic_1,
dout => grp_fu_1023_p2);
convolve_kernel_fbkb_U22 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1027_p0,
din1 => grp_fu_1027_p1,
ce => ap_const_logic_1,
dout => grp_fu_1027_p2);
convolve_kernel_fbkb_U23 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1031_p0,
din1 => grp_fu_1031_p1,
ce => ap_const_logic_1,
dout => grp_fu_1031_p2);
convolve_kernel_fbkb_U24 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1035_p0,
din1 => grp_fu_1035_p1,
ce => ap_const_logic_1,
dout => grp_fu_1035_p2);
convolve_kernel_fbkb_U25 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1039_p0,
din1 => grp_fu_1039_p1,
ce => ap_const_logic_1,
dout => grp_fu_1039_p2);
convolve_kernel_fbkb_U26 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1043_p0,
din1 => grp_fu_1043_p1,
ce => ap_const_logic_1,
dout => grp_fu_1043_p2);
convolve_kernel_fbkb_U27 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1047_p0,
din1 => grp_fu_1047_p1,
ce => ap_const_logic_1,
dout => grp_fu_1047_p2);
convolve_kernel_fbkb_U28 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1051_p0,
din1 => grp_fu_1051_p1,
ce => ap_const_logic_1,
dout => grp_fu_1051_p2);
convolve_kernel_fbkb_U29 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1055_p0,
din1 => grp_fu_1055_p1,
ce => ap_const_logic_1,
dout => grp_fu_1055_p2);
convolve_kernel_fbkb_U30 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1059_p0,
din1 => grp_fu_1059_p1,
ce => ap_const_logic_1,
dout => grp_fu_1059_p2);
convolve_kernel_fbkb_U31 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1063_p0,
din1 => grp_fu_1063_p1,
ce => ap_const_logic_1,
dout => grp_fu_1063_p2);
convolve_kernel_fbkb_U32 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1067_p0,
din1 => grp_fu_1067_p1,
ce => ap_const_logic_1,
dout => grp_fu_1067_p2);
convolve_kernel_fbkb_U33 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1071_p0,
din1 => grp_fu_1071_p1,
ce => ap_const_logic_1,
dout => grp_fu_1071_p2);
convolve_kernel_fbkb_U34 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1075_p0,
din1 => grp_fu_1075_p1,
ce => ap_const_logic_1,
dout => grp_fu_1075_p2);
convolve_kernel_fbkb_U35 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1079_p0,
din1 => grp_fu_1079_p1,
ce => ap_const_logic_1,
dout => grp_fu_1079_p2);
convolve_kernel_fbkb_U36 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1083_p0,
din1 => grp_fu_1083_p1,
ce => ap_const_logic_1,
dout => grp_fu_1083_p2);
convolve_kernel_fbkb_U37 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1087_p0,
din1 => grp_fu_1087_p1,
ce => ap_const_logic_1,
dout => grp_fu_1087_p2);
convolve_kernel_fbkb_U38 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1091_p0,
din1 => grp_fu_1091_p1,
ce => ap_const_logic_1,
dout => grp_fu_1091_p2);
convolve_kernel_fbkb_U39 : component convolve_kernel_fbkb
generic map (
ID => 1,
NUM_STAGE => 14,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1095_p0,
din1 => grp_fu_1095_p1,
ce => ap_const_logic_1,
dout => grp_fu_1095_p2);
convolve_kernel_fcud_U40 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1099_p0,
din1 => grp_fu_1099_p1,
ce => ap_const_logic_1,
dout => grp_fu_1099_p2);
convolve_kernel_fcud_U41 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1103_p0,
din1 => grp_fu_1103_p1,
ce => ap_const_logic_1,
dout => grp_fu_1103_p2);
convolve_kernel_fcud_U42 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1107_p0,
din1 => grp_fu_1107_p1,
ce => ap_const_logic_1,
dout => grp_fu_1107_p2);
convolve_kernel_fcud_U43 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1111_p0,
din1 => grp_fu_1111_p1,
ce => ap_const_logic_1,
dout => grp_fu_1111_p2);
convolve_kernel_fcud_U44 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1115_p0,
din1 => grp_fu_1115_p1,
ce => ap_const_logic_1,
dout => grp_fu_1115_p2);
convolve_kernel_fcud_U45 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1119_p0,
din1 => grp_fu_1119_p1,
ce => ap_const_logic_1,
dout => grp_fu_1119_p2);
convolve_kernel_fcud_U46 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1123_p0,
din1 => grp_fu_1123_p1,
ce => ap_const_logic_1,
dout => grp_fu_1123_p2);
convolve_kernel_fcud_U47 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1127_p0,
din1 => grp_fu_1127_p1,
ce => ap_const_logic_1,
dout => grp_fu_1127_p2);
convolve_kernel_fcud_U48 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1131_p0,
din1 => grp_fu_1131_p1,
ce => ap_const_logic_1,
dout => grp_fu_1131_p2);
convolve_kernel_fcud_U49 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1135_p0,
din1 => grp_fu_1135_p1,
ce => ap_const_logic_1,
dout => grp_fu_1135_p2);
convolve_kernel_fcud_U50 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1139_p0,
din1 => grp_fu_1139_p1,
ce => ap_const_logic_1,
dout => grp_fu_1139_p2);
convolve_kernel_fcud_U51 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1143_p0,
din1 => grp_fu_1143_p1,
ce => ap_const_logic_1,
dout => grp_fu_1143_p2);
convolve_kernel_fcud_U52 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1147_p0,
din1 => grp_fu_1147_p1,
ce => ap_const_logic_1,
dout => grp_fu_1147_p2);
convolve_kernel_fcud_U53 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1151_p0,
din1 => grp_fu_1151_p1,
ce => ap_const_logic_1,
dout => grp_fu_1151_p2);
convolve_kernel_fcud_U54 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1155_p0,
din1 => grp_fu_1155_p1,
ce => ap_const_logic_1,
dout => grp_fu_1155_p2);
convolve_kernel_fcud_U55 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1159_p0,
din1 => grp_fu_1159_p1,
ce => ap_const_logic_1,
dout => grp_fu_1159_p2);
convolve_kernel_fcud_U56 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1163_p0,
din1 => grp_fu_1163_p1,
ce => ap_const_logic_1,
dout => grp_fu_1163_p2);
convolve_kernel_fcud_U57 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1167_p0,
din1 => grp_fu_1167_p1,
ce => ap_const_logic_1,
dout => grp_fu_1167_p2);
convolve_kernel_fcud_U58 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1171_p0,
din1 => grp_fu_1171_p1,
ce => ap_const_logic_1,
dout => grp_fu_1171_p2);
convolve_kernel_fcud_U59 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1175_p0,
din1 => grp_fu_1175_p1,
ce => ap_const_logic_1,
dout => grp_fu_1175_p2);
convolve_kernel_fcud_U60 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1179_p0,
din1 => grp_fu_1179_p1,
ce => ap_const_logic_1,
dout => grp_fu_1179_p2);
convolve_kernel_fcud_U61 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1183_p0,
din1 => grp_fu_1183_p1,
ce => ap_const_logic_1,
dout => grp_fu_1183_p2);
convolve_kernel_fcud_U62 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1187_p0,
din1 => grp_fu_1187_p1,
ce => ap_const_logic_1,
dout => grp_fu_1187_p2);
convolve_kernel_fcud_U63 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1191_p0,
din1 => grp_fu_1191_p1,
ce => ap_const_logic_1,
dout => grp_fu_1191_p2);
convolve_kernel_fcud_U64 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1195_p0,
din1 => grp_fu_1195_p1,
ce => ap_const_logic_1,
dout => grp_fu_1195_p2);
convolve_kernel_fcud_U65 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1199_p0,
din1 => grp_fu_1199_p1,
ce => ap_const_logic_1,
dout => grp_fu_1199_p2);
convolve_kernel_fcud_U66 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1203_p0,
din1 => grp_fu_1203_p1,
ce => ap_const_logic_1,
dout => grp_fu_1203_p2);
convolve_kernel_fcud_U67 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1207_p0,
din1 => grp_fu_1207_p1,
ce => ap_const_logic_1,
dout => grp_fu_1207_p2);
convolve_kernel_fcud_U68 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1211_p0,
din1 => grp_fu_1211_p1,
ce => ap_const_logic_1,
dout => grp_fu_1211_p2);
convolve_kernel_fcud_U69 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1215_p0,
din1 => grp_fu_1215_p1,
ce => ap_const_logic_1,
dout => grp_fu_1215_p2);
convolve_kernel_fcud_U70 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1219_p0,
din1 => grp_fu_1219_p1,
ce => ap_const_logic_1,
dout => grp_fu_1219_p2);
convolve_kernel_fcud_U71 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1223_p0,
din1 => grp_fu_1223_p1,
ce => ap_const_logic_1,
dout => grp_fu_1223_p2);
convolve_kernel_fcud_U72 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1227_p0,
din1 => grp_fu_1227_p1,
ce => ap_const_logic_1,
dout => grp_fu_1227_p2);
convolve_kernel_fcud_U73 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1231_p0,
din1 => grp_fu_1231_p1,
ce => ap_const_logic_1,
dout => grp_fu_1231_p2);
convolve_kernel_fcud_U74 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1235_p0,
din1 => grp_fu_1235_p1,
ce => ap_const_logic_1,
dout => grp_fu_1235_p2);
convolve_kernel_fcud_U75 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1239_p0,
din1 => grp_fu_1239_p1,
ce => ap_const_logic_1,
dout => grp_fu_1239_p2);
convolve_kernel_fcud_U76 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1243_p0,
din1 => grp_fu_1243_p1,
ce => ap_const_logic_1,
dout => grp_fu_1243_p2);
convolve_kernel_fcud_U77 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1247_p0,
din1 => grp_fu_1247_p1,
ce => ap_const_logic_1,
dout => grp_fu_1247_p2);
convolve_kernel_fcud_U78 : component convolve_kernel_fcud
generic map (
ID => 1,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_1251_p0,
din1 => grp_fu_1251_p1,
ce => ap_const_logic_1,
dout => grp_fu_1251_p2);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage0_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_0;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter0 <= ap_const_logic_1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
if ((ap_const_logic_1 = ap_condition_pp0_exit_iter0_state2)) then
ap_enable_reg_pp0_iter1 <= (ap_condition_pp0_exit_iter0_state2 xor ap_const_logic_1);
elsif ((ap_const_boolean_1 = ap_const_boolean_1)) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter3 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter4 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter5 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter5 <= ap_enable_reg_pp0_iter4;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter6 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter6 <= ap_enable_reg_pp0_iter5;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter7 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter7 <= ap_enable_reg_pp0_iter6;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter8 <= ap_const_logic_0;
else
if (((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_enable_reg_pp0_iter8 <= ap_enable_reg_pp0_iter7;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
else
if ((((ap_block_pp0_stage7_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage1_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
ap_enable_reg_pp0_iter9 <= ap_enable_reg_pp0_iter8;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_enable_reg_pp0_iter9 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
i_reg_896_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
i_reg_896 <= tmp_1_mid2_v_reg_3225;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
i_reg_896 <= ap_const_lv3_0;
end if;
end if;
end process;
indvar_flatten1_reg_885_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
indvar_flatten1_reg_885 <= indvar_flatten_next1_reg_3180;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten1_reg_885 <= ap_const_lv10_0;
end if;
end if;
end process;
indvar_flatten_reg_908_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
indvar_flatten_reg_908 <= indvar_flatten_next_reg_3252;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
indvar_flatten_reg_908 <= ap_const_lv8_0;
end if;
end if;
end process;
j_reg_919_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
j_reg_919 <= tmp_5_mid2_reg_3286;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
j_reg_919 <= ap_const_lv3_0;
end if;
end if;
end process;
row_b_reg_931_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
row_b_reg_931 <= row_b_1_reg_3276;
elsif (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
row_b_reg_931 <= ap_const_lv5_0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 <= exitcond_flatten1_reg_3176;
ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter1_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter2_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244 <= tmp_19_1_0_1_reg_5244;
ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344 <= tmp_19_1_10_1_reg_5344;
ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354 <= tmp_19_1_11_1_reg_5354;
ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364 <= tmp_19_1_12_1_reg_5364;
ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254 <= tmp_19_1_1_1_reg_5254;
ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264 <= tmp_19_1_2_1_reg_5264;
ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274 <= tmp_19_1_3_1_reg_5274;
ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284 <= tmp_19_1_4_1_reg_5284;
ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294 <= tmp_19_1_5_1_reg_5294;
ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304 <= tmp_19_1_6_1_reg_5304;
ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314 <= tmp_19_1_7_1_reg_5314;
ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324 <= tmp_19_1_8_1_reg_5324;
ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334 <= tmp_19_1_9_1_reg_5334;
ap_reg_pp0_iter4_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter3_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter4_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter6_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter5_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter6_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter7_exitcond_flatten1_reg_3176;
ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 <= ap_reg_pp0_iter8_exitcond_flatten1_reg_3176;
exitcond_flatten1_reg_3176 <= exitcond_flatten1_fu_1541_p2;
tmp_12_1_reg_3141 <= tmp_12_1_fu_1499_p2;
tmp_12_2_reg_3146 <= tmp_12_2_fu_1505_p2;
tmp_12_3_reg_3151 <= tmp_12_3_fu_1511_p2;
tmp_12_4_reg_3156 <= tmp_12_4_fu_1517_p2;
tmp_12_5_reg_3161 <= tmp_12_5_fu_1523_p2;
tmp_12_6_reg_3166 <= tmp_12_6_fu_1529_p2;
tmp_12_7_reg_3171 <= tmp_12_7_fu_1535_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
ap_reg_pp0_iter1_row_b_mid2_reg_3245 <= row_b_mid2_reg_3245;
ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504 <= tmp_19_2_0_1_reg_5504;
ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604 <= tmp_19_2_10_1_reg_5604;
ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614 <= tmp_19_2_11_1_reg_5614;
ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624 <= tmp_19_2_12_1_reg_5624;
ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514 <= tmp_19_2_1_1_reg_5514;
ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524 <= tmp_19_2_2_1_reg_5524;
ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534 <= tmp_19_2_3_1_reg_5534;
ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544 <= tmp_19_2_4_1_reg_5544;
ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554 <= tmp_19_2_5_1_reg_5554;
ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564 <= tmp_19_2_6_1_reg_5564;
ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574 <= tmp_19_2_7_1_reg_5574;
ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584 <= tmp_19_2_8_1_reg_5584;
ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594 <= tmp_19_2_9_1_reg_5594;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
ap_reg_pp0_iter2_bufo_addr_1_reg_4322(7 downto 3) <= bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter2_bufo_addr_reg_4317(7 downto 3) <= bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824 <= tmp_19_3_0_1_reg_5824;
ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874 <= tmp_19_3_10_1_reg_5874;
ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879 <= tmp_19_3_11_1_reg_5879;
ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884 <= tmp_19_3_12_1_reg_5884;
ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829 <= tmp_19_3_1_1_reg_5829;
ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834 <= tmp_19_3_2_1_reg_5834;
ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839 <= tmp_19_3_3_1_reg_5839;
ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844 <= tmp_19_3_4_1_reg_5844;
ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849 <= tmp_19_3_5_1_reg_5849;
ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854 <= tmp_19_3_6_1_reg_5854;
ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859 <= tmp_19_3_7_1_reg_5859;
ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864 <= tmp_19_3_8_1_reg_5864;
ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869 <= tmp_19_3_9_1_reg_5869;
ap_reg_pp0_iter4_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter4_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_reg_4317(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_1_reg_4322(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_1_reg_4322(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_reg_4317(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_reg_4317(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
ap_reg_pp0_iter2_bufo_addr_2_reg_4429(7 downto 3) <= bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter2_bufo_addr_3_reg_4434(7 downto 3) <= bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149 <= tmp_19_4_0_1_reg_6149;
ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199 <= tmp_19_4_10_1_reg_6199;
ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204 <= tmp_19_4_11_1_reg_6204;
ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209 <= tmp_19_4_12_1_reg_6209;
ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154 <= tmp_19_4_1_1_reg_6154;
ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159 <= tmp_19_4_2_1_reg_6159;
ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164 <= tmp_19_4_3_1_reg_6164;
ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169 <= tmp_19_4_4_1_reg_6169;
ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174 <= tmp_19_4_5_1_reg_6174;
ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179 <= tmp_19_4_6_1_reg_6179;
ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184 <= tmp_19_4_7_1_reg_6184;
ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189 <= tmp_19_4_8_1_reg_6189;
ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194 <= tmp_19_4_9_1_reg_6194;
ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214 <= tmp_19_5_0_1_reg_6214;
ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264 <= tmp_19_5_10_1_reg_6264;
ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269 <= tmp_19_5_11_1_reg_6269;
ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274 <= tmp_19_5_12_1_reg_6274;
ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219 <= tmp_19_5_1_1_reg_6219;
ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224 <= tmp_19_5_2_1_reg_6224;
ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229 <= tmp_19_5_3_1_reg_6229;
ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234 <= tmp_19_5_4_1_reg_6234;
ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239 <= tmp_19_5_5_1_reg_6239;
ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244 <= tmp_19_5_6_1_reg_6244;
ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249 <= tmp_19_5_7_1_reg_6249;
ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254 <= tmp_19_5_8_1_reg_6254;
ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259 <= tmp_19_5_9_1_reg_6259;
ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284 <= tmp_19_6_0_1_reg_6284;
ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384 <= tmp_19_6_10_1_reg_6384;
ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394 <= tmp_19_6_11_1_reg_6394;
ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404 <= tmp_19_6_12_1_reg_6404;
ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294 <= tmp_19_6_1_1_reg_6294;
ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304 <= tmp_19_6_2_1_reg_6304;
ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314 <= tmp_19_6_3_1_reg_6314;
ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324 <= tmp_19_6_4_1_reg_6324;
ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334 <= tmp_19_6_5_1_reg_6334;
ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344 <= tmp_19_6_6_1_reg_6344;
ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354 <= tmp_19_6_7_1_reg_6354;
ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364 <= tmp_19_6_8_1_reg_6364;
ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374 <= tmp_19_6_9_1_reg_6374;
ap_reg_pp0_iter4_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter4_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_3_reg_4434(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_2_reg_4429(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_2_reg_4429(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_3_reg_4434(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_3_reg_4434(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
ap_reg_pp0_iter2_bufo_addr_4_reg_4439(7 downto 3) <= bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter2_bufo_addr_5_reg_4444(7 downto 3) <= bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter3_tmp_19_0_0_2_reg_6474 <= tmp_19_0_0_2_reg_6474;
ap_reg_pp0_iter3_tmp_19_0_10_2_reg_6524 <= tmp_19_0_10_2_reg_6524;
ap_reg_pp0_iter3_tmp_19_0_11_2_reg_6529 <= tmp_19_0_11_2_reg_6529;
ap_reg_pp0_iter3_tmp_19_0_12_2_reg_6534 <= tmp_19_0_12_2_reg_6534;
ap_reg_pp0_iter3_tmp_19_0_1_2_reg_6479 <= tmp_19_0_1_2_reg_6479;
ap_reg_pp0_iter3_tmp_19_0_2_2_reg_6484 <= tmp_19_0_2_2_reg_6484;
ap_reg_pp0_iter3_tmp_19_0_3_2_reg_6489 <= tmp_19_0_3_2_reg_6489;
ap_reg_pp0_iter3_tmp_19_0_4_2_reg_6494 <= tmp_19_0_4_2_reg_6494;
ap_reg_pp0_iter3_tmp_19_0_5_2_reg_6499 <= tmp_19_0_5_2_reg_6499;
ap_reg_pp0_iter3_tmp_19_0_6_2_reg_6504 <= tmp_19_0_6_2_reg_6504;
ap_reg_pp0_iter3_tmp_19_0_7_2_reg_6509 <= tmp_19_0_7_2_reg_6509;
ap_reg_pp0_iter3_tmp_19_0_8_2_reg_6514 <= tmp_19_0_8_2_reg_6514;
ap_reg_pp0_iter3_tmp_19_0_9_2_reg_6519 <= tmp_19_0_9_2_reg_6519;
ap_reg_pp0_iter3_tmp_19_1_0_2_reg_6539 <= tmp_19_1_0_2_reg_6539;
ap_reg_pp0_iter3_tmp_19_1_10_2_reg_6589 <= tmp_19_1_10_2_reg_6589;
ap_reg_pp0_iter3_tmp_19_1_11_2_reg_6594 <= tmp_19_1_11_2_reg_6594;
ap_reg_pp0_iter3_tmp_19_1_12_2_reg_6599 <= tmp_19_1_12_2_reg_6599;
ap_reg_pp0_iter3_tmp_19_1_1_2_reg_6544 <= tmp_19_1_1_2_reg_6544;
ap_reg_pp0_iter3_tmp_19_1_2_2_reg_6549 <= tmp_19_1_2_2_reg_6549;
ap_reg_pp0_iter3_tmp_19_1_3_2_reg_6554 <= tmp_19_1_3_2_reg_6554;
ap_reg_pp0_iter3_tmp_19_1_4_2_reg_6559 <= tmp_19_1_4_2_reg_6559;
ap_reg_pp0_iter3_tmp_19_1_5_2_reg_6564 <= tmp_19_1_5_2_reg_6564;
ap_reg_pp0_iter3_tmp_19_1_6_2_reg_6569 <= tmp_19_1_6_2_reg_6569;
ap_reg_pp0_iter3_tmp_19_1_7_2_reg_6574 <= tmp_19_1_7_2_reg_6574;
ap_reg_pp0_iter3_tmp_19_1_8_2_reg_6579 <= tmp_19_1_8_2_reg_6579;
ap_reg_pp0_iter3_tmp_19_1_9_2_reg_6584 <= tmp_19_1_9_2_reg_6584;
ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604 <= tmp_19_7_0_1_reg_6604;
ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654 <= tmp_19_7_10_1_reg_6654;
ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659 <= tmp_19_7_11_1_reg_6659;
ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664 <= tmp_19_7_12_1_reg_6664;
ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609 <= tmp_19_7_1_1_reg_6609;
ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614 <= tmp_19_7_2_1_reg_6614;
ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619 <= tmp_19_7_3_1_reg_6619;
ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624 <= tmp_19_7_4_1_reg_6624;
ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629 <= tmp_19_7_5_1_reg_6629;
ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634 <= tmp_19_7_6_1_reg_6634;
ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639 <= tmp_19_7_7_1_reg_6639;
ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644 <= tmp_19_7_8_1_reg_6644;
ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649 <= tmp_19_7_9_1_reg_6649;
ap_reg_pp0_iter4_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter4_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474 <= ap_reg_pp0_iter3_tmp_19_0_0_2_reg_6474;
ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524 <= ap_reg_pp0_iter3_tmp_19_0_10_2_reg_6524;
ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529 <= ap_reg_pp0_iter3_tmp_19_0_11_2_reg_6529;
ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534 <= ap_reg_pp0_iter3_tmp_19_0_12_2_reg_6534;
ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479 <= ap_reg_pp0_iter3_tmp_19_0_1_2_reg_6479;
ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484 <= ap_reg_pp0_iter3_tmp_19_0_2_2_reg_6484;
ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489 <= ap_reg_pp0_iter3_tmp_19_0_3_2_reg_6489;
ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494 <= ap_reg_pp0_iter3_tmp_19_0_4_2_reg_6494;
ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499 <= ap_reg_pp0_iter3_tmp_19_0_5_2_reg_6499;
ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504 <= ap_reg_pp0_iter3_tmp_19_0_6_2_reg_6504;
ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509 <= ap_reg_pp0_iter3_tmp_19_0_7_2_reg_6509;
ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514 <= ap_reg_pp0_iter3_tmp_19_0_8_2_reg_6514;
ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519 <= ap_reg_pp0_iter3_tmp_19_0_9_2_reg_6519;
ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539 <= ap_reg_pp0_iter3_tmp_19_1_0_2_reg_6539;
ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589 <= ap_reg_pp0_iter3_tmp_19_1_10_2_reg_6589;
ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594 <= ap_reg_pp0_iter3_tmp_19_1_11_2_reg_6594;
ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599 <= ap_reg_pp0_iter3_tmp_19_1_12_2_reg_6599;
ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544 <= ap_reg_pp0_iter3_tmp_19_1_1_2_reg_6544;
ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549 <= ap_reg_pp0_iter3_tmp_19_1_2_2_reg_6549;
ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554 <= ap_reg_pp0_iter3_tmp_19_1_3_2_reg_6554;
ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559 <= ap_reg_pp0_iter3_tmp_19_1_4_2_reg_6559;
ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564 <= ap_reg_pp0_iter3_tmp_19_1_5_2_reg_6564;
ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569 <= ap_reg_pp0_iter3_tmp_19_1_6_2_reg_6569;
ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574 <= ap_reg_pp0_iter3_tmp_19_1_7_2_reg_6574;
ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579 <= ap_reg_pp0_iter3_tmp_19_1_8_2_reg_6579;
ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584 <= ap_reg_pp0_iter3_tmp_19_1_9_2_reg_6584;
ap_reg_pp0_iter5_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_5_reg_4444(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_4_reg_4439(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_4_reg_4439(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_5_reg_4444(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_5_reg_4444(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
ap_reg_pp0_iter2_bufo_addr_6_reg_4579(7 downto 3) <= bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter2_bufo_addr_7_reg_4584(7 downto 3) <= bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter3_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter2_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter3_tmp_19_2_0_2_reg_6669 <= tmp_19_2_0_2_reg_6669;
ap_reg_pp0_iter3_tmp_19_2_10_2_reg_6719 <= tmp_19_2_10_2_reg_6719;
ap_reg_pp0_iter3_tmp_19_2_11_2_reg_6724 <= tmp_19_2_11_2_reg_6724;
ap_reg_pp0_iter3_tmp_19_2_12_2_reg_6729 <= tmp_19_2_12_2_reg_6729;
ap_reg_pp0_iter3_tmp_19_2_1_2_reg_6674 <= tmp_19_2_1_2_reg_6674;
ap_reg_pp0_iter3_tmp_19_2_2_2_reg_6679 <= tmp_19_2_2_2_reg_6679;
ap_reg_pp0_iter3_tmp_19_2_3_2_reg_6684 <= tmp_19_2_3_2_reg_6684;
ap_reg_pp0_iter3_tmp_19_2_4_2_reg_6689 <= tmp_19_2_4_2_reg_6689;
ap_reg_pp0_iter3_tmp_19_2_5_2_reg_6694 <= tmp_19_2_5_2_reg_6694;
ap_reg_pp0_iter3_tmp_19_2_6_2_reg_6699 <= tmp_19_2_6_2_reg_6699;
ap_reg_pp0_iter3_tmp_19_2_7_2_reg_6704 <= tmp_19_2_7_2_reg_6704;
ap_reg_pp0_iter3_tmp_19_2_8_2_reg_6709 <= tmp_19_2_8_2_reg_6709;
ap_reg_pp0_iter3_tmp_19_2_9_2_reg_6714 <= tmp_19_2_9_2_reg_6714;
ap_reg_pp0_iter3_tmp_19_3_0_2_reg_6734 <= tmp_19_3_0_2_reg_6734;
ap_reg_pp0_iter3_tmp_19_3_10_2_reg_6784 <= tmp_19_3_10_2_reg_6784;
ap_reg_pp0_iter3_tmp_19_3_11_2_reg_6789 <= tmp_19_3_11_2_reg_6789;
ap_reg_pp0_iter3_tmp_19_3_12_2_reg_6794 <= tmp_19_3_12_2_reg_6794;
ap_reg_pp0_iter3_tmp_19_3_1_2_reg_6739 <= tmp_19_3_1_2_reg_6739;
ap_reg_pp0_iter3_tmp_19_3_2_2_reg_6744 <= tmp_19_3_2_2_reg_6744;
ap_reg_pp0_iter3_tmp_19_3_3_2_reg_6749 <= tmp_19_3_3_2_reg_6749;
ap_reg_pp0_iter3_tmp_19_3_4_2_reg_6754 <= tmp_19_3_4_2_reg_6754;
ap_reg_pp0_iter3_tmp_19_3_5_2_reg_6759 <= tmp_19_3_5_2_reg_6759;
ap_reg_pp0_iter3_tmp_19_3_6_2_reg_6764 <= tmp_19_3_6_2_reg_6764;
ap_reg_pp0_iter3_tmp_19_3_7_2_reg_6769 <= tmp_19_3_7_2_reg_6769;
ap_reg_pp0_iter3_tmp_19_3_8_2_reg_6774 <= tmp_19_3_8_2_reg_6774;
ap_reg_pp0_iter3_tmp_19_3_9_2_reg_6779 <= tmp_19_3_9_2_reg_6779;
ap_reg_pp0_iter3_tmp_19_4_0_2_reg_6799 <= tmp_19_4_0_2_reg_6799;
ap_reg_pp0_iter3_tmp_19_4_10_2_reg_6849 <= tmp_19_4_10_2_reg_6849;
ap_reg_pp0_iter3_tmp_19_4_11_2_reg_6854 <= tmp_19_4_11_2_reg_6854;
ap_reg_pp0_iter3_tmp_19_4_12_2_reg_6859 <= tmp_19_4_12_2_reg_6859;
ap_reg_pp0_iter3_tmp_19_4_1_2_reg_6804 <= tmp_19_4_1_2_reg_6804;
ap_reg_pp0_iter3_tmp_19_4_2_2_reg_6809 <= tmp_19_4_2_2_reg_6809;
ap_reg_pp0_iter3_tmp_19_4_3_2_reg_6814 <= tmp_19_4_3_2_reg_6814;
ap_reg_pp0_iter3_tmp_19_4_4_2_reg_6819 <= tmp_19_4_4_2_reg_6819;
ap_reg_pp0_iter3_tmp_19_4_5_2_reg_6824 <= tmp_19_4_5_2_reg_6824;
ap_reg_pp0_iter3_tmp_19_4_6_2_reg_6829 <= tmp_19_4_6_2_reg_6829;
ap_reg_pp0_iter3_tmp_19_4_7_2_reg_6834 <= tmp_19_4_7_2_reg_6834;
ap_reg_pp0_iter3_tmp_19_4_8_2_reg_6839 <= tmp_19_4_8_2_reg_6839;
ap_reg_pp0_iter3_tmp_19_4_9_2_reg_6844 <= tmp_19_4_9_2_reg_6844;
ap_reg_pp0_iter4_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter4_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter3_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669 <= ap_reg_pp0_iter3_tmp_19_2_0_2_reg_6669;
ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719 <= ap_reg_pp0_iter3_tmp_19_2_10_2_reg_6719;
ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724 <= ap_reg_pp0_iter3_tmp_19_2_11_2_reg_6724;
ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729 <= ap_reg_pp0_iter3_tmp_19_2_12_2_reg_6729;
ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674 <= ap_reg_pp0_iter3_tmp_19_2_1_2_reg_6674;
ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679 <= ap_reg_pp0_iter3_tmp_19_2_2_2_reg_6679;
ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684 <= ap_reg_pp0_iter3_tmp_19_2_3_2_reg_6684;
ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689 <= ap_reg_pp0_iter3_tmp_19_2_4_2_reg_6689;
ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694 <= ap_reg_pp0_iter3_tmp_19_2_5_2_reg_6694;
ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699 <= ap_reg_pp0_iter3_tmp_19_2_6_2_reg_6699;
ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704 <= ap_reg_pp0_iter3_tmp_19_2_7_2_reg_6704;
ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709 <= ap_reg_pp0_iter3_tmp_19_2_8_2_reg_6709;
ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714 <= ap_reg_pp0_iter3_tmp_19_2_9_2_reg_6714;
ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734 <= ap_reg_pp0_iter3_tmp_19_3_0_2_reg_6734;
ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784 <= ap_reg_pp0_iter3_tmp_19_3_10_2_reg_6784;
ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789 <= ap_reg_pp0_iter3_tmp_19_3_11_2_reg_6789;
ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794 <= ap_reg_pp0_iter3_tmp_19_3_12_2_reg_6794;
ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739 <= ap_reg_pp0_iter3_tmp_19_3_1_2_reg_6739;
ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744 <= ap_reg_pp0_iter3_tmp_19_3_2_2_reg_6744;
ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749 <= ap_reg_pp0_iter3_tmp_19_3_3_2_reg_6749;
ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754 <= ap_reg_pp0_iter3_tmp_19_3_4_2_reg_6754;
ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759 <= ap_reg_pp0_iter3_tmp_19_3_5_2_reg_6759;
ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764 <= ap_reg_pp0_iter3_tmp_19_3_6_2_reg_6764;
ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769 <= ap_reg_pp0_iter3_tmp_19_3_7_2_reg_6769;
ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774 <= ap_reg_pp0_iter3_tmp_19_3_8_2_reg_6774;
ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779 <= ap_reg_pp0_iter3_tmp_19_3_9_2_reg_6779;
ap_reg_pp0_iter4_tmp_19_4_0_2_reg_6799 <= ap_reg_pp0_iter3_tmp_19_4_0_2_reg_6799;
ap_reg_pp0_iter4_tmp_19_4_10_2_reg_6849 <= ap_reg_pp0_iter3_tmp_19_4_10_2_reg_6849;
ap_reg_pp0_iter4_tmp_19_4_11_2_reg_6854 <= ap_reg_pp0_iter3_tmp_19_4_11_2_reg_6854;
ap_reg_pp0_iter4_tmp_19_4_12_2_reg_6859 <= ap_reg_pp0_iter3_tmp_19_4_12_2_reg_6859;
ap_reg_pp0_iter4_tmp_19_4_1_2_reg_6804 <= ap_reg_pp0_iter3_tmp_19_4_1_2_reg_6804;
ap_reg_pp0_iter4_tmp_19_4_2_2_reg_6809 <= ap_reg_pp0_iter3_tmp_19_4_2_2_reg_6809;
ap_reg_pp0_iter4_tmp_19_4_3_2_reg_6814 <= ap_reg_pp0_iter3_tmp_19_4_3_2_reg_6814;
ap_reg_pp0_iter4_tmp_19_4_4_2_reg_6819 <= ap_reg_pp0_iter3_tmp_19_4_4_2_reg_6819;
ap_reg_pp0_iter4_tmp_19_4_5_2_reg_6824 <= ap_reg_pp0_iter3_tmp_19_4_5_2_reg_6824;
ap_reg_pp0_iter4_tmp_19_4_6_2_reg_6829 <= ap_reg_pp0_iter3_tmp_19_4_6_2_reg_6829;
ap_reg_pp0_iter4_tmp_19_4_7_2_reg_6834 <= ap_reg_pp0_iter3_tmp_19_4_7_2_reg_6834;
ap_reg_pp0_iter4_tmp_19_4_8_2_reg_6839 <= ap_reg_pp0_iter3_tmp_19_4_8_2_reg_6839;
ap_reg_pp0_iter4_tmp_19_4_9_2_reg_6844 <= ap_reg_pp0_iter3_tmp_19_4_9_2_reg_6844;
ap_reg_pp0_iter5_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter5_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter4_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799 <= ap_reg_pp0_iter4_tmp_19_4_0_2_reg_6799;
ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849 <= ap_reg_pp0_iter4_tmp_19_4_10_2_reg_6849;
ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854 <= ap_reg_pp0_iter4_tmp_19_4_11_2_reg_6854;
ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859 <= ap_reg_pp0_iter4_tmp_19_4_12_2_reg_6859;
ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804 <= ap_reg_pp0_iter4_tmp_19_4_1_2_reg_6804;
ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809 <= ap_reg_pp0_iter4_tmp_19_4_2_2_reg_6809;
ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814 <= ap_reg_pp0_iter4_tmp_19_4_3_2_reg_6814;
ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819 <= ap_reg_pp0_iter4_tmp_19_4_4_2_reg_6819;
ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824 <= ap_reg_pp0_iter4_tmp_19_4_5_2_reg_6824;
ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829 <= ap_reg_pp0_iter4_tmp_19_4_6_2_reg_6829;
ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834 <= ap_reg_pp0_iter4_tmp_19_4_7_2_reg_6834;
ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839 <= ap_reg_pp0_iter4_tmp_19_4_8_2_reg_6839;
ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844 <= ap_reg_pp0_iter4_tmp_19_4_9_2_reg_6844;
ap_reg_pp0_iter6_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter6_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter5_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter7_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter6_bufo_addr_7_reg_4584(7 downto 3);
ap_reg_pp0_iter8_bufo_addr_6_reg_4579(7 downto 3) <= ap_reg_pp0_iter7_bufo_addr_6_reg_4579(7 downto 3);
ap_reg_pp0_iter8_bufo_addr_7_reg_4584(7 downto 3) <= ap_reg_pp0_iter7_bufo_addr_7_reg_4584(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854 <= tmp_19_0_0_1_reg_4854;
ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954 <= tmp_19_0_10_1_reg_4954;
ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964 <= tmp_19_0_11_1_reg_4964;
ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974 <= tmp_19_0_12_1_reg_4974;
ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864 <= tmp_19_0_1_1_reg_4864;
ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874 <= tmp_19_0_2_1_reg_4874;
ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884 <= tmp_19_0_3_1_reg_4884;
ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894 <= tmp_19_0_4_1_reg_4894;
ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904 <= tmp_19_0_5_1_reg_4904;
ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914 <= tmp_19_0_6_1_reg_4914;
ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924 <= tmp_19_0_7_1_reg_4924;
ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934 <= tmp_19_0_8_1_reg_4934;
ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944 <= tmp_19_0_9_1_reg_4944;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
ap_reg_pp0_iter3_tmp_19_5_0_2_reg_6864 <= tmp_19_5_0_2_reg_6864;
ap_reg_pp0_iter3_tmp_19_5_10_2_reg_6914 <= tmp_19_5_10_2_reg_6914;
ap_reg_pp0_iter3_tmp_19_5_11_2_reg_6919 <= tmp_19_5_11_2_reg_6919;
ap_reg_pp0_iter3_tmp_19_5_12_2_reg_6924 <= tmp_19_5_12_2_reg_6924;
ap_reg_pp0_iter3_tmp_19_5_1_2_reg_6869 <= tmp_19_5_1_2_reg_6869;
ap_reg_pp0_iter3_tmp_19_5_2_2_reg_6874 <= tmp_19_5_2_2_reg_6874;
ap_reg_pp0_iter3_tmp_19_5_3_2_reg_6879 <= tmp_19_5_3_2_reg_6879;
ap_reg_pp0_iter3_tmp_19_5_4_2_reg_6884 <= tmp_19_5_4_2_reg_6884;
ap_reg_pp0_iter3_tmp_19_5_5_2_reg_6889 <= tmp_19_5_5_2_reg_6889;
ap_reg_pp0_iter3_tmp_19_5_6_2_reg_6894 <= tmp_19_5_6_2_reg_6894;
ap_reg_pp0_iter3_tmp_19_5_7_2_reg_6899 <= tmp_19_5_7_2_reg_6899;
ap_reg_pp0_iter3_tmp_19_5_8_2_reg_6904 <= tmp_19_5_8_2_reg_6904;
ap_reg_pp0_iter3_tmp_19_5_9_2_reg_6909 <= tmp_19_5_9_2_reg_6909;
ap_reg_pp0_iter3_tmp_19_6_0_2_reg_6929 <= tmp_19_6_0_2_reg_6929;
ap_reg_pp0_iter3_tmp_19_6_10_2_reg_6979 <= tmp_19_6_10_2_reg_6979;
ap_reg_pp0_iter3_tmp_19_6_11_2_reg_6984 <= tmp_19_6_11_2_reg_6984;
ap_reg_pp0_iter3_tmp_19_6_12_2_reg_6989 <= tmp_19_6_12_2_reg_6989;
ap_reg_pp0_iter3_tmp_19_6_1_2_reg_6934 <= tmp_19_6_1_2_reg_6934;
ap_reg_pp0_iter3_tmp_19_6_2_2_reg_6939 <= tmp_19_6_2_2_reg_6939;
ap_reg_pp0_iter3_tmp_19_6_3_2_reg_6944 <= tmp_19_6_3_2_reg_6944;
ap_reg_pp0_iter3_tmp_19_6_4_2_reg_6949 <= tmp_19_6_4_2_reg_6949;
ap_reg_pp0_iter3_tmp_19_6_5_2_reg_6954 <= tmp_19_6_5_2_reg_6954;
ap_reg_pp0_iter3_tmp_19_6_6_2_reg_6959 <= tmp_19_6_6_2_reg_6959;
ap_reg_pp0_iter3_tmp_19_6_7_2_reg_6964 <= tmp_19_6_7_2_reg_6964;
ap_reg_pp0_iter3_tmp_19_6_8_2_reg_6969 <= tmp_19_6_8_2_reg_6969;
ap_reg_pp0_iter3_tmp_19_6_9_2_reg_6974 <= tmp_19_6_9_2_reg_6974;
ap_reg_pp0_iter3_tmp_19_7_0_2_reg_6994 <= tmp_19_7_0_2_reg_6994;
ap_reg_pp0_iter3_tmp_19_7_10_2_reg_7044 <= tmp_19_7_10_2_reg_7044;
ap_reg_pp0_iter3_tmp_19_7_11_2_reg_7049 <= tmp_19_7_11_2_reg_7049;
ap_reg_pp0_iter3_tmp_19_7_12_2_reg_7054 <= tmp_19_7_12_2_reg_7054;
ap_reg_pp0_iter3_tmp_19_7_1_2_reg_6999 <= tmp_19_7_1_2_reg_6999;
ap_reg_pp0_iter3_tmp_19_7_2_2_reg_7004 <= tmp_19_7_2_2_reg_7004;
ap_reg_pp0_iter3_tmp_19_7_3_2_reg_7009 <= tmp_19_7_3_2_reg_7009;
ap_reg_pp0_iter3_tmp_19_7_4_2_reg_7014 <= tmp_19_7_4_2_reg_7014;
ap_reg_pp0_iter3_tmp_19_7_5_2_reg_7019 <= tmp_19_7_5_2_reg_7019;
ap_reg_pp0_iter3_tmp_19_7_6_2_reg_7024 <= tmp_19_7_6_2_reg_7024;
ap_reg_pp0_iter3_tmp_19_7_7_2_reg_7029 <= tmp_19_7_7_2_reg_7029;
ap_reg_pp0_iter3_tmp_19_7_8_2_reg_7034 <= tmp_19_7_8_2_reg_7034;
ap_reg_pp0_iter3_tmp_19_7_9_2_reg_7039 <= tmp_19_7_9_2_reg_7039;
ap_reg_pp0_iter4_tmp_19_5_0_2_reg_6864 <= ap_reg_pp0_iter3_tmp_19_5_0_2_reg_6864;
ap_reg_pp0_iter4_tmp_19_5_10_2_reg_6914 <= ap_reg_pp0_iter3_tmp_19_5_10_2_reg_6914;
ap_reg_pp0_iter4_tmp_19_5_11_2_reg_6919 <= ap_reg_pp0_iter3_tmp_19_5_11_2_reg_6919;
ap_reg_pp0_iter4_tmp_19_5_12_2_reg_6924 <= ap_reg_pp0_iter3_tmp_19_5_12_2_reg_6924;
ap_reg_pp0_iter4_tmp_19_5_1_2_reg_6869 <= ap_reg_pp0_iter3_tmp_19_5_1_2_reg_6869;
ap_reg_pp0_iter4_tmp_19_5_2_2_reg_6874 <= ap_reg_pp0_iter3_tmp_19_5_2_2_reg_6874;
ap_reg_pp0_iter4_tmp_19_5_3_2_reg_6879 <= ap_reg_pp0_iter3_tmp_19_5_3_2_reg_6879;
ap_reg_pp0_iter4_tmp_19_5_4_2_reg_6884 <= ap_reg_pp0_iter3_tmp_19_5_4_2_reg_6884;
ap_reg_pp0_iter4_tmp_19_5_5_2_reg_6889 <= ap_reg_pp0_iter3_tmp_19_5_5_2_reg_6889;
ap_reg_pp0_iter4_tmp_19_5_6_2_reg_6894 <= ap_reg_pp0_iter3_tmp_19_5_6_2_reg_6894;
ap_reg_pp0_iter4_tmp_19_5_7_2_reg_6899 <= ap_reg_pp0_iter3_tmp_19_5_7_2_reg_6899;
ap_reg_pp0_iter4_tmp_19_5_8_2_reg_6904 <= ap_reg_pp0_iter3_tmp_19_5_8_2_reg_6904;
ap_reg_pp0_iter4_tmp_19_5_9_2_reg_6909 <= ap_reg_pp0_iter3_tmp_19_5_9_2_reg_6909;
ap_reg_pp0_iter4_tmp_19_6_0_2_reg_6929 <= ap_reg_pp0_iter3_tmp_19_6_0_2_reg_6929;
ap_reg_pp0_iter4_tmp_19_6_10_2_reg_6979 <= ap_reg_pp0_iter3_tmp_19_6_10_2_reg_6979;
ap_reg_pp0_iter4_tmp_19_6_11_2_reg_6984 <= ap_reg_pp0_iter3_tmp_19_6_11_2_reg_6984;
ap_reg_pp0_iter4_tmp_19_6_12_2_reg_6989 <= ap_reg_pp0_iter3_tmp_19_6_12_2_reg_6989;
ap_reg_pp0_iter4_tmp_19_6_1_2_reg_6934 <= ap_reg_pp0_iter3_tmp_19_6_1_2_reg_6934;
ap_reg_pp0_iter4_tmp_19_6_2_2_reg_6939 <= ap_reg_pp0_iter3_tmp_19_6_2_2_reg_6939;
ap_reg_pp0_iter4_tmp_19_6_3_2_reg_6944 <= ap_reg_pp0_iter3_tmp_19_6_3_2_reg_6944;
ap_reg_pp0_iter4_tmp_19_6_4_2_reg_6949 <= ap_reg_pp0_iter3_tmp_19_6_4_2_reg_6949;
ap_reg_pp0_iter4_tmp_19_6_5_2_reg_6954 <= ap_reg_pp0_iter3_tmp_19_6_5_2_reg_6954;
ap_reg_pp0_iter4_tmp_19_6_6_2_reg_6959 <= ap_reg_pp0_iter3_tmp_19_6_6_2_reg_6959;
ap_reg_pp0_iter4_tmp_19_6_7_2_reg_6964 <= ap_reg_pp0_iter3_tmp_19_6_7_2_reg_6964;
ap_reg_pp0_iter4_tmp_19_6_8_2_reg_6969 <= ap_reg_pp0_iter3_tmp_19_6_8_2_reg_6969;
ap_reg_pp0_iter4_tmp_19_6_9_2_reg_6974 <= ap_reg_pp0_iter3_tmp_19_6_9_2_reg_6974;
ap_reg_pp0_iter4_tmp_19_7_0_2_reg_6994 <= ap_reg_pp0_iter3_tmp_19_7_0_2_reg_6994;
ap_reg_pp0_iter4_tmp_19_7_10_2_reg_7044 <= ap_reg_pp0_iter3_tmp_19_7_10_2_reg_7044;
ap_reg_pp0_iter4_tmp_19_7_11_2_reg_7049 <= ap_reg_pp0_iter3_tmp_19_7_11_2_reg_7049;
ap_reg_pp0_iter4_tmp_19_7_12_2_reg_7054 <= ap_reg_pp0_iter3_tmp_19_7_12_2_reg_7054;
ap_reg_pp0_iter4_tmp_19_7_1_2_reg_6999 <= ap_reg_pp0_iter3_tmp_19_7_1_2_reg_6999;
ap_reg_pp0_iter4_tmp_19_7_2_2_reg_7004 <= ap_reg_pp0_iter3_tmp_19_7_2_2_reg_7004;
ap_reg_pp0_iter4_tmp_19_7_3_2_reg_7009 <= ap_reg_pp0_iter3_tmp_19_7_3_2_reg_7009;
ap_reg_pp0_iter4_tmp_19_7_4_2_reg_7014 <= ap_reg_pp0_iter3_tmp_19_7_4_2_reg_7014;
ap_reg_pp0_iter4_tmp_19_7_5_2_reg_7019 <= ap_reg_pp0_iter3_tmp_19_7_5_2_reg_7019;
ap_reg_pp0_iter4_tmp_19_7_6_2_reg_7024 <= ap_reg_pp0_iter3_tmp_19_7_6_2_reg_7024;
ap_reg_pp0_iter4_tmp_19_7_7_2_reg_7029 <= ap_reg_pp0_iter3_tmp_19_7_7_2_reg_7029;
ap_reg_pp0_iter4_tmp_19_7_8_2_reg_7034 <= ap_reg_pp0_iter3_tmp_19_7_8_2_reg_7034;
ap_reg_pp0_iter4_tmp_19_7_9_2_reg_7039 <= ap_reg_pp0_iter3_tmp_19_7_9_2_reg_7039;
ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864 <= ap_reg_pp0_iter4_tmp_19_5_0_2_reg_6864;
ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914 <= ap_reg_pp0_iter4_tmp_19_5_10_2_reg_6914;
ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919 <= ap_reg_pp0_iter4_tmp_19_5_11_2_reg_6919;
ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924 <= ap_reg_pp0_iter4_tmp_19_5_12_2_reg_6924;
ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869 <= ap_reg_pp0_iter4_tmp_19_5_1_2_reg_6869;
ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874 <= ap_reg_pp0_iter4_tmp_19_5_2_2_reg_6874;
ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879 <= ap_reg_pp0_iter4_tmp_19_5_3_2_reg_6879;
ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884 <= ap_reg_pp0_iter4_tmp_19_5_4_2_reg_6884;
ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889 <= ap_reg_pp0_iter4_tmp_19_5_5_2_reg_6889;
ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894 <= ap_reg_pp0_iter4_tmp_19_5_6_2_reg_6894;
ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899 <= ap_reg_pp0_iter4_tmp_19_5_7_2_reg_6899;
ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904 <= ap_reg_pp0_iter4_tmp_19_5_8_2_reg_6904;
ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909 <= ap_reg_pp0_iter4_tmp_19_5_9_2_reg_6909;
ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929 <= ap_reg_pp0_iter4_tmp_19_6_0_2_reg_6929;
ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979 <= ap_reg_pp0_iter4_tmp_19_6_10_2_reg_6979;
ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984 <= ap_reg_pp0_iter4_tmp_19_6_11_2_reg_6984;
ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989 <= ap_reg_pp0_iter4_tmp_19_6_12_2_reg_6989;
ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934 <= ap_reg_pp0_iter4_tmp_19_6_1_2_reg_6934;
ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939 <= ap_reg_pp0_iter4_tmp_19_6_2_2_reg_6939;
ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944 <= ap_reg_pp0_iter4_tmp_19_6_3_2_reg_6944;
ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949 <= ap_reg_pp0_iter4_tmp_19_6_4_2_reg_6949;
ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954 <= ap_reg_pp0_iter4_tmp_19_6_5_2_reg_6954;
ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959 <= ap_reg_pp0_iter4_tmp_19_6_6_2_reg_6959;
ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964 <= ap_reg_pp0_iter4_tmp_19_6_7_2_reg_6964;
ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969 <= ap_reg_pp0_iter4_tmp_19_6_8_2_reg_6969;
ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974 <= ap_reg_pp0_iter4_tmp_19_6_9_2_reg_6974;
ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994 <= ap_reg_pp0_iter4_tmp_19_7_0_2_reg_6994;
ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044 <= ap_reg_pp0_iter4_tmp_19_7_10_2_reg_7044;
ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049 <= ap_reg_pp0_iter4_tmp_19_7_11_2_reg_7049;
ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054 <= ap_reg_pp0_iter4_tmp_19_7_12_2_reg_7054;
ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999 <= ap_reg_pp0_iter4_tmp_19_7_1_2_reg_6999;
ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004 <= ap_reg_pp0_iter4_tmp_19_7_2_2_reg_7004;
ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009 <= ap_reg_pp0_iter4_tmp_19_7_3_2_reg_7009;
ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014 <= ap_reg_pp0_iter4_tmp_19_7_4_2_reg_7014;
ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019 <= ap_reg_pp0_iter4_tmp_19_7_5_2_reg_7019;
ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024 <= ap_reg_pp0_iter4_tmp_19_7_6_2_reg_7024;
ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029 <= ap_reg_pp0_iter4_tmp_19_7_7_2_reg_7029;
ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034 <= ap_reg_pp0_iter4_tmp_19_7_8_2_reg_7034;
ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039 <= ap_reg_pp0_iter4_tmp_19_7_9_2_reg_7039;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_load_1_reg_3931 <= bufi_0_Dout_B;
bufi_0_load_reg_3693 <= bufi_0_Dout_A;
bufi_1_load_1_reg_3948 <= bufi_1_Dout_B;
bufi_1_load_reg_3718 <= bufi_1_Dout_A;
bufi_2_load_1_reg_3965 <= bufi_2_Dout_B;
bufi_2_load_reg_3735 <= bufi_2_Dout_A;
bufw_0_load_1_reg_3710 <= bufw_0_Dout_B;
bufw_0_load_reg_3686 <= bufw_0_Dout_A;
bufw_10_load_1_reg_3894 <= bufw_10_Dout_B;
bufw_10_load_reg_3887 <= bufw_10_Dout_A;
bufw_11_load_1_reg_3909 <= bufw_11_Dout_B;
bufw_11_load_reg_3902 <= bufw_11_Dout_A;
bufw_12_load_1_reg_3924 <= bufw_12_Dout_B;
bufw_12_load_reg_3917 <= bufw_12_Dout_A;
bufw_1_load_1_reg_3759 <= bufw_1_Dout_B;
bufw_1_load_reg_3752 <= bufw_1_Dout_A;
bufw_2_load_1_reg_3774 <= bufw_2_Dout_B;
bufw_2_load_reg_3767 <= bufw_2_Dout_A;
bufw_3_load_1_reg_3789 <= bufw_3_Dout_B;
bufw_3_load_reg_3782 <= bufw_3_Dout_A;
bufw_4_load_1_reg_3804 <= bufw_4_Dout_B;
bufw_4_load_reg_3797 <= bufw_4_Dout_A;
bufw_5_load_1_reg_3819 <= bufw_5_Dout_B;
bufw_5_load_reg_3812 <= bufw_5_Dout_A;
bufw_6_load_1_reg_3834 <= bufw_6_Dout_B;
bufw_6_load_reg_3827 <= bufw_6_Dout_A;
bufw_7_load_1_reg_3849 <= bufw_7_Dout_B;
bufw_7_load_reg_3842 <= bufw_7_Dout_A;
bufw_8_load_1_reg_3864 <= bufw_8_Dout_B;
bufw_8_load_reg_3857 <= bufw_8_Dout_A;
bufw_9_load_1_reg_3879 <= bufw_9_Dout_B;
bufw_9_load_reg_3872 <= bufw_9_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_0_load_2_reg_4103 <= bufi_0_Dout_A;
bufi_0_load_3_reg_4154 <= bufi_0_Dout_B;
bufi_1_load_2_reg_4120 <= bufi_1_Dout_A;
bufi_1_load_3_reg_4171 <= bufi_1_Dout_B;
bufi_2_load_2_reg_4137 <= bufi_2_Dout_A;
bufi_2_load_3_reg_4188 <= bufi_2_Dout_B;
bufw_0_load_2_reg_4012 <= bufw_0_Dout_A;
bufw_10_load_2_reg_4082 <= bufw_10_Dout_A;
bufw_11_load_2_reg_4089 <= bufw_11_Dout_A;
bufw_12_load_2_reg_4096 <= bufw_12_Dout_A;
bufw_1_load_2_reg_4019 <= bufw_1_Dout_A;
bufw_2_load_2_reg_4026 <= bufw_2_Dout_A;
bufw_3_load_2_reg_4033 <= bufw_3_Dout_A;
bufw_4_load_2_reg_4040 <= bufw_4_Dout_A;
bufw_5_load_2_reg_4047 <= bufw_5_Dout_A;
bufw_6_load_2_reg_4054 <= bufw_6_Dout_A;
bufw_7_load_2_reg_4061 <= bufw_7_Dout_A;
bufw_8_load_2_reg_4068 <= bufw_8_Dout_A;
bufw_9_load_2_reg_4075 <= bufw_9_Dout_A;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
bufi_0_load_4_reg_4205 <= bufi_0_Dout_A;
bufi_0_load_5_reg_4256 <= bufi_0_Dout_B;
bufi_1_load_4_reg_4222 <= bufi_1_Dout_A;
bufi_1_load_5_reg_4273 <= bufi_1_Dout_B;
bufi_2_load_4_reg_4239 <= bufi_2_Dout_A;
bufi_2_load_5_reg_4290 <= bufi_2_Dout_B;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
bufi_0_load_6_reg_4327 <= bufi_0_Dout_A;
bufi_0_load_7_reg_4378 <= bufi_0_Dout_B;
bufi_1_load_6_reg_4344 <= bufi_1_Dout_A;
bufi_1_load_7_reg_4395 <= bufi_1_Dout_B;
bufi_2_load_6_reg_4361 <= bufi_2_Dout_A;
bufi_2_load_7_reg_4412 <= bufi_2_Dout_B;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
bufo_addr_1_reg_4322(7 downto 3) <= tmp_336_fu_2040_p3(8 - 1 downto 0)(7 downto 3);
bufo_addr_reg_4317(7 downto 3) <= tmp_334_fu_2029_p1(8 - 1 downto 0)(7 downto 3);
tmp_333_reg_4307(7 downto 3) <= tmp_333_fu_2022_p3(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
bufo_addr_2_reg_4429(7 downto 3) <= tmp_338_fu_2054_p3(8 - 1 downto 0)(7 downto 3);
bufo_addr_3_reg_4434(7 downto 3) <= tmp_340_fu_2068_p3(8 - 1 downto 0)(7 downto 3);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
bufo_addr_4_reg_4439(7 downto 3) <= tmp_342_fu_2082_p3(8 - 1 downto 0)(7 downto 3);
bufo_addr_5_reg_4444(7 downto 3) <= tmp_344_fu_2096_p3(8 - 1 downto 0)(7 downto 3);
tmp_350_reg_4449 <= tmp_350_fu_2105_p1;
tmp_352_reg_4514 <= tmp_352_fu_2109_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufo_addr_6_reg_4579(7 downto 3) <= tmp_346_fu_2118_p3(8 - 1 downto 0)(7 downto 3);
bufo_addr_7_reg_4584(7 downto 3) <= tmp_348_fu_2132_p3(8 - 1 downto 0)(7 downto 3);
tmp_353_reg_4589 <= tmp_353_fu_2141_p1;
tmp_354_reg_4654 <= tmp_354_fu_2145_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((exitcond_flatten1_fu_1541_p2 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
exitcond_flatten_reg_3190 <= exitcond_flatten_fu_1559_p2;
i_1_reg_3185 <= i_1_fu_1553_p2;
indvar_flatten_op_reg_3211 <= indvar_flatten_op_fu_1571_p2;
tmp_5_reg_3206 <= tmp_5_fu_1565_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
indvar_flatten_next1_reg_3180 <= indvar_flatten_next1_fu_1547_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
indvar_flatten_next_reg_3252 <= indvar_flatten_next_fu_1613_p3;
tmp_1_mid2_v_reg_3225 <= tmp_1_mid2_v_fu_1584_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
j_1_reg_3264 <= j_1_fu_1642_p2;
tmp_1_reg_3257 <= tmp_1_fu_1633_p2;
tmp_s_reg_3270 <= tmp_s_fu_1647_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
j_mid_reg_3216 <= j_mid_fu_1577_p3;
row_b_mid2_reg_3245 <= row_b_mid2_fu_1605_p3;
tmp_7_mid_reg_3233 <= tmp_7_mid_fu_1595_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
row_b_1_reg_3276 <= row_b_1_fu_1652_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
tmp_102_reg_4609 <= grp_fu_1285_p1(159 downto 128);
tmp_105_reg_4614 <= grp_fu_1295_p1(191 downto 160);
tmp_108_reg_4619 <= grp_fu_1305_p1(223 downto 192);
tmp_111_reg_4624 <= grp_fu_1315_p1(255 downto 224);
tmp_114_reg_4629 <= grp_fu_1325_p1(287 downto 256);
tmp_117_reg_4634 <= grp_fu_1335_p1(319 downto 288);
tmp_120_reg_4639 <= grp_fu_1345_p1(351 downto 320);
tmp_123_reg_4644 <= grp_fu_1355_p1(383 downto 352);
tmp_126_reg_4649 <= grp_fu_1365_p1(415 downto 384);
tmp_133_reg_4659 <= grp_fu_1375_p1(63 downto 32);
tmp_136_reg_4664 <= grp_fu_1385_p1(95 downto 64);
tmp_139_reg_4669 <= grp_fu_1395_p1(127 downto 96);
tmp_142_reg_4674 <= grp_fu_1405_p1(159 downto 128);
tmp_145_reg_4679 <= grp_fu_1415_p1(191 downto 160);
tmp_148_reg_4684 <= grp_fu_1425_p1(223 downto 192);
tmp_151_reg_4689 <= grp_fu_1435_p1(255 downto 224);
tmp_154_reg_4694 <= grp_fu_1445_p1(287 downto 256);
tmp_157_reg_4699 <= grp_fu_1455_p1(319 downto 288);
tmp_160_reg_4704 <= grp_fu_1465_p1(351 downto 320);
tmp_163_reg_4709 <= grp_fu_1475_p1(383 downto 352);
tmp_166_reg_4714 <= grp_fu_1485_p1(415 downto 384);
tmp_93_reg_4594 <= grp_fu_1255_p1(63 downto 32);
tmp_96_reg_4599 <= grp_fu_1265_p1(95 downto 64);
tmp_99_reg_4604 <= grp_fu_1275_p1(127 downto 96);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (tmp_7_mid_reg_3233 = ap_const_lv1_1) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
tmp_12_1_mid1_reg_3294 <= tmp_12_1_mid1_fu_1667_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (tmp_7_mid_reg_3233 = ap_const_lv1_1) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
tmp_12_2_mid1_reg_3331 <= tmp_12_2_mid1_fu_1748_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (tmp_7_mid_reg_3233 = ap_const_lv1_1) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
tmp_12_4_mid1_reg_3481 <= tmp_12_4_mid1_fu_1840_p2;
tmp_12_5_mid1_reg_3486 <= tmp_12_5_mid1_fu_1846_p2;
tmp_12_6_mid1_reg_3491 <= tmp_12_6_mid1_fu_1852_p2;
tmp_12_7_mid1_reg_3496 <= tmp_12_7_mid1_fu_1858_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
tmp_130_reg_3336 <= tmp_130_fu_1753_p2;
tmp_170_reg_3341 <= tmp_170_fu_1758_p2;
tmp_3_reg_3311 <= tmp_3_fu_1706_p2;
tmp_5_mid2_cast2_reg_3316(2 downto 0) <= tmp_5_mid2_cast2_fu_1721_p1(2 downto 0);
tmp_6_reg_3321 <= tmp_6_fu_1727_p2;
tmp_8_reg_3326 <= tmp_8_fu_1732_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
tmp_13_reg_4454 <= grp_fu_1255_p1(63 downto 32);
tmp_16_reg_4459 <= grp_fu_1265_p1(95 downto 64);
tmp_19_reg_4464 <= grp_fu_1275_p1(127 downto 96);
tmp_22_reg_4469 <= grp_fu_1285_p1(159 downto 128);
tmp_25_reg_4474 <= grp_fu_1295_p1(191 downto 160);
tmp_28_reg_4479 <= grp_fu_1305_p1(223 downto 192);
tmp_31_reg_4484 <= grp_fu_1315_p1(255 downto 224);
tmp_34_reg_4489 <= grp_fu_1325_p1(287 downto 256);
tmp_37_reg_4494 <= grp_fu_1335_p1(319 downto 288);
tmp_40_reg_4499 <= grp_fu_1345_p1(351 downto 320);
tmp_43_reg_4504 <= grp_fu_1355_p1(383 downto 352);
tmp_46_reg_4509 <= grp_fu_1365_p1(415 downto 384);
tmp_53_reg_4519 <= grp_fu_1375_p1(63 downto 32);
tmp_56_reg_4524 <= grp_fu_1385_p1(95 downto 64);
tmp_59_reg_4529 <= grp_fu_1395_p1(127 downto 96);
tmp_62_reg_4534 <= grp_fu_1405_p1(159 downto 128);
tmp_65_reg_4539 <= grp_fu_1415_p1(191 downto 160);
tmp_68_reg_4544 <= grp_fu_1425_p1(223 downto 192);
tmp_71_reg_4549 <= grp_fu_1435_p1(255 downto 224);
tmp_74_reg_4554 <= grp_fu_1445_p1(287 downto 256);
tmp_77_reg_4559 <= grp_fu_1455_p1(319 downto 288);
tmp_80_reg_4564 <= grp_fu_1465_p1(351 downto 320);
tmp_83_reg_4569 <= grp_fu_1475_p1(383 downto 352);
tmp_86_reg_4574 <= grp_fu_1485_p1(415 downto 384);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
tmp_173_reg_4724 <= grp_fu_1255_p1(63 downto 32);
tmp_176_reg_4729 <= grp_fu_1265_p1(95 downto 64);
tmp_179_reg_4734 <= grp_fu_1275_p1(127 downto 96);
tmp_182_reg_4739 <= grp_fu_1285_p1(159 downto 128);
tmp_185_reg_4744 <= grp_fu_1295_p1(191 downto 160);
tmp_188_reg_4749 <= grp_fu_1305_p1(223 downto 192);
tmp_191_reg_4754 <= grp_fu_1315_p1(255 downto 224);
tmp_194_reg_4759 <= grp_fu_1325_p1(287 downto 256);
tmp_197_reg_4764 <= grp_fu_1335_p1(319 downto 288);
tmp_200_reg_4769 <= grp_fu_1345_p1(351 downto 320);
tmp_203_reg_4774 <= grp_fu_1355_p1(383 downto 352);
tmp_206_reg_4779 <= grp_fu_1365_p1(415 downto 384);
tmp_213_reg_4789 <= grp_fu_1375_p1(63 downto 32);
tmp_216_reg_4794 <= grp_fu_1385_p1(95 downto 64);
tmp_219_reg_4799 <= grp_fu_1395_p1(127 downto 96);
tmp_222_reg_4804 <= grp_fu_1405_p1(159 downto 128);
tmp_225_reg_4809 <= grp_fu_1415_p1(191 downto 160);
tmp_228_reg_4814 <= grp_fu_1425_p1(223 downto 192);
tmp_231_reg_4819 <= grp_fu_1435_p1(255 downto 224);
tmp_234_reg_4824 <= grp_fu_1445_p1(287 downto 256);
tmp_237_reg_4829 <= grp_fu_1455_p1(319 downto 288);
tmp_240_reg_4834 <= grp_fu_1465_p1(351 downto 320);
tmp_243_reg_4839 <= grp_fu_1475_p1(383 downto 352);
tmp_246_reg_4844 <= grp_fu_1485_p1(415 downto 384);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
tmp_19_0_0_1_reg_4854 <= grp_fu_1103_p2;
tmp_19_0_10_1_reg_4954 <= grp_fu_1183_p2;
tmp_19_0_10_reg_4959 <= grp_fu_1187_p2;
tmp_19_0_11_1_reg_4964 <= grp_fu_1191_p2;
tmp_19_0_11_reg_4969 <= grp_fu_1195_p2;
tmp_19_0_12_1_reg_4974 <= grp_fu_1199_p2;
tmp_19_0_1_1_reg_4864 <= grp_fu_1111_p2;
tmp_19_0_1_reg_4859 <= grp_fu_1107_p2;
tmp_19_0_2_1_reg_4874 <= grp_fu_1119_p2;
tmp_19_0_2_reg_4869 <= grp_fu_1115_p2;
tmp_19_0_3_1_reg_4884 <= grp_fu_1127_p2;
tmp_19_0_3_reg_4879 <= grp_fu_1123_p2;
tmp_19_0_4_1_reg_4894 <= grp_fu_1135_p2;
tmp_19_0_4_reg_4889 <= grp_fu_1131_p2;
tmp_19_0_5_1_reg_4904 <= grp_fu_1143_p2;
tmp_19_0_5_reg_4899 <= grp_fu_1139_p2;
tmp_19_0_6_1_reg_4914 <= grp_fu_1151_p2;
tmp_19_0_6_reg_4909 <= grp_fu_1147_p2;
tmp_19_0_7_1_reg_4924 <= grp_fu_1159_p2;
tmp_19_0_7_reg_4919 <= grp_fu_1155_p2;
tmp_19_0_8_1_reg_4934 <= grp_fu_1167_p2;
tmp_19_0_8_reg_4929 <= grp_fu_1163_p2;
tmp_19_0_9_1_reg_4944 <= grp_fu_1175_p2;
tmp_19_0_9_reg_4939 <= grp_fu_1171_p2;
tmp_19_0_s_reg_4949 <= grp_fu_1179_p2;
tmp_19_1_10_reg_5034 <= grp_fu_1247_p2;
tmp_19_1_11_reg_5039 <= grp_fu_1251_p2;
tmp_19_1_1_reg_4984 <= grp_fu_1207_p2;
tmp_19_1_2_reg_4989 <= grp_fu_1211_p2;
tmp_19_1_3_reg_4994 <= grp_fu_1215_p2;
tmp_19_1_4_reg_4999 <= grp_fu_1219_p2;
tmp_19_1_5_reg_5004 <= grp_fu_1223_p2;
tmp_19_1_6_reg_5009 <= grp_fu_1227_p2;
tmp_19_1_7_reg_5014 <= grp_fu_1231_p2;
tmp_19_1_8_reg_5019 <= grp_fu_1235_p2;
tmp_19_1_9_reg_5024 <= grp_fu_1239_p2;
tmp_19_1_reg_4979 <= grp_fu_1203_p2;
tmp_19_1_s_reg_5029 <= grp_fu_1243_p2;
tmp_253_reg_5049 <= grp_fu_1255_p1(63 downto 32);
tmp_256_reg_5054 <= grp_fu_1265_p1(95 downto 64);
tmp_259_reg_5059 <= grp_fu_1275_p1(127 downto 96);
tmp_262_reg_5064 <= grp_fu_1285_p1(159 downto 128);
tmp_265_reg_5069 <= grp_fu_1295_p1(191 downto 160);
tmp_268_reg_5074 <= grp_fu_1305_p1(223 downto 192);
tmp_271_reg_5079 <= grp_fu_1315_p1(255 downto 224);
tmp_274_reg_5084 <= grp_fu_1325_p1(287 downto 256);
tmp_277_reg_5089 <= grp_fu_1335_p1(319 downto 288);
tmp_280_reg_5094 <= grp_fu_1345_p1(351 downto 320);
tmp_283_reg_5099 <= grp_fu_1355_p1(383 downto 352);
tmp_286_reg_5104 <= grp_fu_1365_p1(415 downto 384);
tmp_293_reg_5114 <= grp_fu_1375_p1(63 downto 32);
tmp_296_reg_5119 <= grp_fu_1385_p1(95 downto 64);
tmp_299_reg_5124 <= grp_fu_1395_p1(127 downto 96);
tmp_302_reg_5129 <= grp_fu_1405_p1(159 downto 128);
tmp_305_reg_5134 <= grp_fu_1415_p1(191 downto 160);
tmp_308_reg_5139 <= grp_fu_1425_p1(223 downto 192);
tmp_311_reg_5144 <= grp_fu_1435_p1(255 downto 224);
tmp_314_reg_5149 <= grp_fu_1445_p1(287 downto 256);
tmp_317_reg_5154 <= grp_fu_1455_p1(319 downto 288);
tmp_320_reg_5159 <= grp_fu_1465_p1(351 downto 320);
tmp_323_reg_5164 <= grp_fu_1475_p1(383 downto 352);
tmp_326_reg_5169 <= grp_fu_1485_p1(415 downto 384);
tmp_349_reg_4849 <= grp_fu_1099_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_0_0_2_reg_6474 <= grp_fu_1099_p2;
tmp_19_0_10_2_reg_6524 <= grp_fu_1139_p2;
tmp_19_0_11_2_reg_6529 <= grp_fu_1143_p2;
tmp_19_0_12_2_reg_6534 <= grp_fu_1147_p2;
tmp_19_0_1_2_reg_6479 <= grp_fu_1103_p2;
tmp_19_0_2_2_reg_6484 <= grp_fu_1107_p2;
tmp_19_0_3_2_reg_6489 <= grp_fu_1111_p2;
tmp_19_0_4_2_reg_6494 <= grp_fu_1115_p2;
tmp_19_0_5_2_reg_6499 <= grp_fu_1119_p2;
tmp_19_0_6_2_reg_6504 <= grp_fu_1123_p2;
tmp_19_0_7_2_reg_6509 <= grp_fu_1127_p2;
tmp_19_0_8_2_reg_6514 <= grp_fu_1131_p2;
tmp_19_0_9_2_reg_6519 <= grp_fu_1135_p2;
tmp_19_1_0_2_reg_6539 <= grp_fu_1151_p2;
tmp_19_1_10_2_reg_6589 <= grp_fu_1191_p2;
tmp_19_1_11_2_reg_6594 <= grp_fu_1195_p2;
tmp_19_1_12_2_reg_6599 <= grp_fu_1199_p2;
tmp_19_1_1_2_reg_6544 <= grp_fu_1155_p2;
tmp_19_1_2_2_reg_6549 <= grp_fu_1159_p2;
tmp_19_1_3_2_reg_6554 <= grp_fu_1163_p2;
tmp_19_1_4_2_reg_6559 <= grp_fu_1167_p2;
tmp_19_1_5_2_reg_6564 <= grp_fu_1171_p2;
tmp_19_1_6_2_reg_6569 <= grp_fu_1175_p2;
tmp_19_1_7_2_reg_6574 <= grp_fu_1179_p2;
tmp_19_1_8_2_reg_6579 <= grp_fu_1183_p2;
tmp_19_1_9_2_reg_6584 <= grp_fu_1187_p2;
tmp_19_7_0_1_reg_6604 <= grp_fu_1203_p2;
tmp_19_7_10_1_reg_6654 <= grp_fu_1243_p2;
tmp_19_7_11_1_reg_6659 <= grp_fu_1247_p2;
tmp_19_7_12_1_reg_6664 <= grp_fu_1251_p2;
tmp_19_7_1_1_reg_6609 <= grp_fu_1207_p2;
tmp_19_7_2_1_reg_6614 <= grp_fu_1211_p2;
tmp_19_7_3_1_reg_6619 <= grp_fu_1215_p2;
tmp_19_7_4_1_reg_6624 <= grp_fu_1219_p2;
tmp_19_7_5_1_reg_6629 <= grp_fu_1223_p2;
tmp_19_7_6_1_reg_6634 <= grp_fu_1227_p2;
tmp_19_7_7_1_reg_6639 <= grp_fu_1231_p2;
tmp_19_7_8_1_reg_6644 <= grp_fu_1235_p2;
tmp_19_7_9_1_reg_6649 <= grp_fu_1239_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_1_0_1_reg_5244 <= grp_fu_1099_p2;
tmp_19_1_10_1_reg_5344 <= grp_fu_1139_p2;
tmp_19_1_11_1_reg_5354 <= grp_fu_1143_p2;
tmp_19_1_12_1_reg_5364 <= grp_fu_1147_p2;
tmp_19_1_1_1_reg_5254 <= grp_fu_1103_p2;
tmp_19_1_2_1_reg_5264 <= grp_fu_1107_p2;
tmp_19_1_3_1_reg_5274 <= grp_fu_1111_p2;
tmp_19_1_4_1_reg_5284 <= grp_fu_1115_p2;
tmp_19_1_5_1_reg_5294 <= grp_fu_1119_p2;
tmp_19_1_6_1_reg_5304 <= grp_fu_1123_p2;
tmp_19_1_7_1_reg_5314 <= grp_fu_1127_p2;
tmp_19_1_8_1_reg_5324 <= grp_fu_1131_p2;
tmp_19_1_9_1_reg_5334 <= grp_fu_1135_p2;
tmp_19_2_10_reg_5424 <= grp_fu_1195_p2;
tmp_19_2_11_reg_5429 <= grp_fu_1199_p2;
tmp_19_2_1_reg_5374 <= grp_fu_1155_p2;
tmp_19_2_2_reg_5379 <= grp_fu_1159_p2;
tmp_19_2_3_reg_5384 <= grp_fu_1163_p2;
tmp_19_2_4_reg_5389 <= grp_fu_1167_p2;
tmp_19_2_5_reg_5394 <= grp_fu_1171_p2;
tmp_19_2_6_reg_5399 <= grp_fu_1175_p2;
tmp_19_2_7_reg_5404 <= grp_fu_1179_p2;
tmp_19_2_8_reg_5409 <= grp_fu_1183_p2;
tmp_19_2_9_reg_5414 <= grp_fu_1187_p2;
tmp_19_2_reg_5369 <= grp_fu_1151_p2;
tmp_19_2_s_reg_5419 <= grp_fu_1191_p2;
tmp_19_3_10_reg_5489 <= grp_fu_1247_p2;
tmp_19_3_11_reg_5494 <= grp_fu_1251_p2;
tmp_19_3_1_reg_5439 <= grp_fu_1207_p2;
tmp_19_3_2_reg_5444 <= grp_fu_1211_p2;
tmp_19_3_3_reg_5449 <= grp_fu_1215_p2;
tmp_19_3_4_reg_5454 <= grp_fu_1219_p2;
tmp_19_3_5_reg_5459 <= grp_fu_1223_p2;
tmp_19_3_6_reg_5464 <= grp_fu_1227_p2;
tmp_19_3_7_reg_5469 <= grp_fu_1231_p2;
tmp_19_3_8_reg_5474 <= grp_fu_1235_p2;
tmp_19_3_9_reg_5479 <= grp_fu_1239_p2;
tmp_19_3_reg_5434 <= grp_fu_1203_p2;
tmp_19_3_s_reg_5484 <= grp_fu_1243_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_2_0_1_reg_5504 <= grp_fu_1099_p2;
tmp_19_2_10_1_reg_5604 <= grp_fu_1139_p2;
tmp_19_2_11_1_reg_5614 <= grp_fu_1143_p2;
tmp_19_2_12_1_reg_5624 <= grp_fu_1147_p2;
tmp_19_2_1_1_reg_5514 <= grp_fu_1103_p2;
tmp_19_2_2_1_reg_5524 <= grp_fu_1107_p2;
tmp_19_2_3_1_reg_5534 <= grp_fu_1111_p2;
tmp_19_2_4_1_reg_5544 <= grp_fu_1115_p2;
tmp_19_2_5_1_reg_5554 <= grp_fu_1119_p2;
tmp_19_2_6_1_reg_5564 <= grp_fu_1123_p2;
tmp_19_2_7_1_reg_5574 <= grp_fu_1127_p2;
tmp_19_2_8_1_reg_5584 <= grp_fu_1131_p2;
tmp_19_2_9_1_reg_5594 <= grp_fu_1135_p2;
tmp_19_4_10_reg_5749 <= grp_fu_1195_p2;
tmp_19_4_11_reg_5754 <= grp_fu_1199_p2;
tmp_19_4_1_reg_5699 <= grp_fu_1155_p2;
tmp_19_4_2_reg_5704 <= grp_fu_1159_p2;
tmp_19_4_3_reg_5709 <= grp_fu_1163_p2;
tmp_19_4_4_reg_5714 <= grp_fu_1167_p2;
tmp_19_4_5_reg_5719 <= grp_fu_1171_p2;
tmp_19_4_6_reg_5724 <= grp_fu_1175_p2;
tmp_19_4_7_reg_5729 <= grp_fu_1179_p2;
tmp_19_4_8_reg_5734 <= grp_fu_1183_p2;
tmp_19_4_9_reg_5739 <= grp_fu_1187_p2;
tmp_19_4_reg_5694 <= grp_fu_1151_p2;
tmp_19_4_s_reg_5744 <= grp_fu_1191_p2;
tmp_19_5_10_reg_5814 <= grp_fu_1247_p2;
tmp_19_5_11_reg_5819 <= grp_fu_1251_p2;
tmp_19_5_1_reg_5764 <= grp_fu_1207_p2;
tmp_19_5_2_reg_5769 <= grp_fu_1211_p2;
tmp_19_5_3_reg_5774 <= grp_fu_1215_p2;
tmp_19_5_4_reg_5779 <= grp_fu_1219_p2;
tmp_19_5_5_reg_5784 <= grp_fu_1223_p2;
tmp_19_5_6_reg_5789 <= grp_fu_1227_p2;
tmp_19_5_7_reg_5794 <= grp_fu_1231_p2;
tmp_19_5_8_reg_5799 <= grp_fu_1235_p2;
tmp_19_5_9_reg_5804 <= grp_fu_1239_p2;
tmp_19_5_reg_5759 <= grp_fu_1203_p2;
tmp_19_5_s_reg_5809 <= grp_fu_1243_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_2_0_2_reg_6669 <= grp_fu_1099_p2;
tmp_19_2_10_2_reg_6719 <= grp_fu_1139_p2;
tmp_19_2_11_2_reg_6724 <= grp_fu_1143_p2;
tmp_19_2_12_2_reg_6729 <= grp_fu_1147_p2;
tmp_19_2_1_2_reg_6674 <= grp_fu_1103_p2;
tmp_19_2_2_2_reg_6679 <= grp_fu_1107_p2;
tmp_19_2_3_2_reg_6684 <= grp_fu_1111_p2;
tmp_19_2_4_2_reg_6689 <= grp_fu_1115_p2;
tmp_19_2_5_2_reg_6694 <= grp_fu_1119_p2;
tmp_19_2_6_2_reg_6699 <= grp_fu_1123_p2;
tmp_19_2_7_2_reg_6704 <= grp_fu_1127_p2;
tmp_19_2_8_2_reg_6709 <= grp_fu_1131_p2;
tmp_19_2_9_2_reg_6714 <= grp_fu_1135_p2;
tmp_19_3_0_2_reg_6734 <= grp_fu_1151_p2;
tmp_19_3_10_2_reg_6784 <= grp_fu_1191_p2;
tmp_19_3_11_2_reg_6789 <= grp_fu_1195_p2;
tmp_19_3_12_2_reg_6794 <= grp_fu_1199_p2;
tmp_19_3_1_2_reg_6739 <= grp_fu_1155_p2;
tmp_19_3_2_2_reg_6744 <= grp_fu_1159_p2;
tmp_19_3_3_2_reg_6749 <= grp_fu_1163_p2;
tmp_19_3_4_2_reg_6754 <= grp_fu_1167_p2;
tmp_19_3_5_2_reg_6759 <= grp_fu_1171_p2;
tmp_19_3_6_2_reg_6764 <= grp_fu_1175_p2;
tmp_19_3_7_2_reg_6769 <= grp_fu_1179_p2;
tmp_19_3_8_2_reg_6774 <= grp_fu_1183_p2;
tmp_19_3_9_2_reg_6779 <= grp_fu_1187_p2;
tmp_19_4_0_2_reg_6799 <= grp_fu_1203_p2;
tmp_19_4_10_2_reg_6849 <= grp_fu_1243_p2;
tmp_19_4_11_2_reg_6854 <= grp_fu_1247_p2;
tmp_19_4_12_2_reg_6859 <= grp_fu_1251_p2;
tmp_19_4_1_2_reg_6804 <= grp_fu_1207_p2;
tmp_19_4_2_2_reg_6809 <= grp_fu_1211_p2;
tmp_19_4_3_2_reg_6814 <= grp_fu_1215_p2;
tmp_19_4_4_2_reg_6819 <= grp_fu_1219_p2;
tmp_19_4_5_2_reg_6824 <= grp_fu_1223_p2;
tmp_19_4_6_2_reg_6829 <= grp_fu_1227_p2;
tmp_19_4_7_2_reg_6834 <= grp_fu_1231_p2;
tmp_19_4_8_2_reg_6839 <= grp_fu_1235_p2;
tmp_19_4_9_2_reg_6844 <= grp_fu_1239_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_3_0_1_reg_5824 <= grp_fu_1099_p2;
tmp_19_3_10_1_reg_5874 <= grp_fu_1139_p2;
tmp_19_3_11_1_reg_5879 <= grp_fu_1143_p2;
tmp_19_3_12_1_reg_5884 <= grp_fu_1147_p2;
tmp_19_3_1_1_reg_5829 <= grp_fu_1103_p2;
tmp_19_3_2_1_reg_5834 <= grp_fu_1107_p2;
tmp_19_3_3_1_reg_5839 <= grp_fu_1111_p2;
tmp_19_3_4_1_reg_5844 <= grp_fu_1115_p2;
tmp_19_3_5_1_reg_5849 <= grp_fu_1119_p2;
tmp_19_3_6_1_reg_5854 <= grp_fu_1123_p2;
tmp_19_3_7_1_reg_5859 <= grp_fu_1127_p2;
tmp_19_3_8_1_reg_5864 <= grp_fu_1131_p2;
tmp_19_3_9_1_reg_5869 <= grp_fu_1135_p2;
tmp_19_6_10_reg_6074 <= grp_fu_1195_p2;
tmp_19_6_11_reg_6079 <= grp_fu_1199_p2;
tmp_19_6_1_reg_6024 <= grp_fu_1155_p2;
tmp_19_6_2_reg_6029 <= grp_fu_1159_p2;
tmp_19_6_3_reg_6034 <= grp_fu_1163_p2;
tmp_19_6_4_reg_6039 <= grp_fu_1167_p2;
tmp_19_6_5_reg_6044 <= grp_fu_1171_p2;
tmp_19_6_6_reg_6049 <= grp_fu_1175_p2;
tmp_19_6_7_reg_6054 <= grp_fu_1179_p2;
tmp_19_6_8_reg_6059 <= grp_fu_1183_p2;
tmp_19_6_9_reg_6064 <= grp_fu_1187_p2;
tmp_19_6_reg_6019 <= grp_fu_1151_p2;
tmp_19_6_s_reg_6069 <= grp_fu_1191_p2;
tmp_19_7_10_reg_6139 <= grp_fu_1247_p2;
tmp_19_7_11_reg_6144 <= grp_fu_1251_p2;
tmp_19_7_1_reg_6089 <= grp_fu_1207_p2;
tmp_19_7_2_reg_6094 <= grp_fu_1211_p2;
tmp_19_7_3_reg_6099 <= grp_fu_1215_p2;
tmp_19_7_4_reg_6104 <= grp_fu_1219_p2;
tmp_19_7_5_reg_6109 <= grp_fu_1223_p2;
tmp_19_7_6_reg_6114 <= grp_fu_1227_p2;
tmp_19_7_7_reg_6119 <= grp_fu_1231_p2;
tmp_19_7_8_reg_6124 <= grp_fu_1235_p2;
tmp_19_7_9_reg_6129 <= grp_fu_1239_p2;
tmp_19_7_reg_6084 <= grp_fu_1203_p2;
tmp_19_7_s_reg_6134 <= grp_fu_1243_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_4_0_1_reg_6149 <= grp_fu_1099_p2;
tmp_19_4_10_1_reg_6199 <= grp_fu_1139_p2;
tmp_19_4_11_1_reg_6204 <= grp_fu_1143_p2;
tmp_19_4_12_1_reg_6209 <= grp_fu_1147_p2;
tmp_19_4_1_1_reg_6154 <= grp_fu_1103_p2;
tmp_19_4_2_1_reg_6159 <= grp_fu_1107_p2;
tmp_19_4_3_1_reg_6164 <= grp_fu_1111_p2;
tmp_19_4_4_1_reg_6169 <= grp_fu_1115_p2;
tmp_19_4_5_1_reg_6174 <= grp_fu_1119_p2;
tmp_19_4_6_1_reg_6179 <= grp_fu_1123_p2;
tmp_19_4_7_1_reg_6184 <= grp_fu_1127_p2;
tmp_19_4_8_1_reg_6189 <= grp_fu_1131_p2;
tmp_19_4_9_1_reg_6194 <= grp_fu_1135_p2;
tmp_19_5_0_1_reg_6214 <= grp_fu_1151_p2;
tmp_19_5_10_1_reg_6264 <= grp_fu_1191_p2;
tmp_19_5_11_1_reg_6269 <= grp_fu_1195_p2;
tmp_19_5_12_1_reg_6274 <= grp_fu_1199_p2;
tmp_19_5_1_1_reg_6219 <= grp_fu_1155_p2;
tmp_19_5_2_1_reg_6224 <= grp_fu_1159_p2;
tmp_19_5_3_1_reg_6229 <= grp_fu_1163_p2;
tmp_19_5_4_1_reg_6234 <= grp_fu_1167_p2;
tmp_19_5_5_1_reg_6239 <= grp_fu_1171_p2;
tmp_19_5_6_1_reg_6244 <= grp_fu_1175_p2;
tmp_19_5_7_1_reg_6249 <= grp_fu_1179_p2;
tmp_19_5_8_1_reg_6254 <= grp_fu_1183_p2;
tmp_19_5_9_1_reg_6259 <= grp_fu_1187_p2;
tmp_19_6_0_1_reg_6284 <= grp_fu_1203_p2;
tmp_19_6_10_1_reg_6384 <= grp_fu_1243_p2;
tmp_19_6_11_1_reg_6394 <= grp_fu_1247_p2;
tmp_19_6_12_1_reg_6404 <= grp_fu_1251_p2;
tmp_19_6_1_1_reg_6294 <= grp_fu_1207_p2;
tmp_19_6_2_1_reg_6304 <= grp_fu_1211_p2;
tmp_19_6_3_1_reg_6314 <= grp_fu_1215_p2;
tmp_19_6_4_1_reg_6324 <= grp_fu_1219_p2;
tmp_19_6_5_1_reg_6334 <= grp_fu_1223_p2;
tmp_19_6_6_1_reg_6344 <= grp_fu_1227_p2;
tmp_19_6_7_1_reg_6354 <= grp_fu_1231_p2;
tmp_19_6_8_1_reg_6364 <= grp_fu_1235_p2;
tmp_19_6_9_1_reg_6374 <= grp_fu_1239_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter2_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
tmp_19_5_0_2_reg_6864 <= grp_fu_1099_p2;
tmp_19_5_10_2_reg_6914 <= grp_fu_1139_p2;
tmp_19_5_11_2_reg_6919 <= grp_fu_1143_p2;
tmp_19_5_12_2_reg_6924 <= grp_fu_1147_p2;
tmp_19_5_1_2_reg_6869 <= grp_fu_1103_p2;
tmp_19_5_2_2_reg_6874 <= grp_fu_1107_p2;
tmp_19_5_3_2_reg_6879 <= grp_fu_1111_p2;
tmp_19_5_4_2_reg_6884 <= grp_fu_1115_p2;
tmp_19_5_5_2_reg_6889 <= grp_fu_1119_p2;
tmp_19_5_6_2_reg_6894 <= grp_fu_1123_p2;
tmp_19_5_7_2_reg_6899 <= grp_fu_1127_p2;
tmp_19_5_8_2_reg_6904 <= grp_fu_1131_p2;
tmp_19_5_9_2_reg_6909 <= grp_fu_1135_p2;
tmp_19_6_0_2_reg_6929 <= grp_fu_1151_p2;
tmp_19_6_10_2_reg_6979 <= grp_fu_1191_p2;
tmp_19_6_11_2_reg_6984 <= grp_fu_1195_p2;
tmp_19_6_12_2_reg_6989 <= grp_fu_1199_p2;
tmp_19_6_1_2_reg_6934 <= grp_fu_1155_p2;
tmp_19_6_2_2_reg_6939 <= grp_fu_1159_p2;
tmp_19_6_3_2_reg_6944 <= grp_fu_1163_p2;
tmp_19_6_4_2_reg_6949 <= grp_fu_1167_p2;
tmp_19_6_5_2_reg_6954 <= grp_fu_1171_p2;
tmp_19_6_6_2_reg_6959 <= grp_fu_1175_p2;
tmp_19_6_7_2_reg_6964 <= grp_fu_1179_p2;
tmp_19_6_8_2_reg_6969 <= grp_fu_1183_p2;
tmp_19_6_9_2_reg_6974 <= grp_fu_1187_p2;
tmp_19_7_0_2_reg_6994 <= grp_fu_1203_p2;
tmp_19_7_10_2_reg_7044 <= grp_fu_1243_p2;
tmp_19_7_11_2_reg_7049 <= grp_fu_1247_p2;
tmp_19_7_12_2_reg_7054 <= grp_fu_1251_p2;
tmp_19_7_1_2_reg_6999 <= grp_fu_1207_p2;
tmp_19_7_2_2_reg_7004 <= grp_fu_1211_p2;
tmp_19_7_3_2_reg_7009 <= grp_fu_1215_p2;
tmp_19_7_4_2_reg_7014 <= grp_fu_1219_p2;
tmp_19_7_5_2_reg_7019 <= grp_fu_1223_p2;
tmp_19_7_6_2_reg_7024 <= grp_fu_1227_p2;
tmp_19_7_7_2_reg_7029 <= grp_fu_1231_p2;
tmp_19_7_8_2_reg_7034 <= grp_fu_1235_p2;
tmp_19_7_9_2_reg_7039 <= grp_fu_1239_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_0_0_1_reg_7579 <= grp_fu_943_p2;
tmp_20_0_10_1_reg_7629 <= grp_fu_983_p2;
tmp_20_0_11_1_reg_7634 <= grp_fu_987_p2;
tmp_20_0_12_1_reg_7639 <= grp_fu_991_p2;
tmp_20_0_1_1_reg_7584 <= grp_fu_947_p2;
tmp_20_0_2_1_reg_7589 <= grp_fu_951_p2;
tmp_20_0_3_1_reg_7594 <= grp_fu_955_p2;
tmp_20_0_4_1_reg_7599 <= grp_fu_959_p2;
tmp_20_0_5_1_reg_7604 <= grp_fu_963_p2;
tmp_20_0_6_1_reg_7609 <= grp_fu_967_p2;
tmp_20_0_7_1_reg_7614 <= grp_fu_971_p2;
tmp_20_0_8_1_reg_7619 <= grp_fu_975_p2;
tmp_20_0_9_1_reg_7624 <= grp_fu_979_p2;
tmp_20_1_0_1_reg_7644 <= grp_fu_995_p2;
tmp_20_1_10_1_reg_7694 <= grp_fu_1035_p2;
tmp_20_1_11_1_reg_7699 <= grp_fu_1039_p2;
tmp_20_1_12_1_reg_7704 <= grp_fu_1043_p2;
tmp_20_1_1_1_reg_7649 <= grp_fu_999_p2;
tmp_20_1_2_1_reg_7654 <= grp_fu_1003_p2;
tmp_20_1_3_1_reg_7659 <= grp_fu_1007_p2;
tmp_20_1_4_1_reg_7664 <= grp_fu_1011_p2;
tmp_20_1_5_1_reg_7669 <= grp_fu_1015_p2;
tmp_20_1_6_1_reg_7674 <= grp_fu_1019_p2;
tmp_20_1_7_1_reg_7679 <= grp_fu_1023_p2;
tmp_20_1_8_1_reg_7684 <= grp_fu_1027_p2;
tmp_20_1_9_1_reg_7689 <= grp_fu_1031_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_20_0_0_2_reg_8099 <= grp_fu_943_p2;
tmp_20_0_10_2_reg_8149 <= grp_fu_983_p2;
tmp_20_0_11_2_reg_8154 <= grp_fu_987_p2;
tmp_20_0_12_2_reg_8159 <= grp_fu_991_p2;
tmp_20_0_1_2_reg_8104 <= grp_fu_947_p2;
tmp_20_0_2_2_reg_8109 <= grp_fu_951_p2;
tmp_20_0_3_2_reg_8114 <= grp_fu_955_p2;
tmp_20_0_4_2_reg_8119 <= grp_fu_959_p2;
tmp_20_0_5_2_reg_8124 <= grp_fu_963_p2;
tmp_20_0_6_2_reg_8129 <= grp_fu_967_p2;
tmp_20_0_7_2_reg_8134 <= grp_fu_971_p2;
tmp_20_0_8_2_reg_8139 <= grp_fu_975_p2;
tmp_20_0_9_2_reg_8144 <= grp_fu_979_p2;
tmp_20_1_0_2_reg_8164 <= grp_fu_995_p2;
tmp_20_1_10_2_reg_8214 <= grp_fu_1035_p2;
tmp_20_1_11_2_reg_8219 <= grp_fu_1039_p2;
tmp_20_1_12_2_reg_8224 <= grp_fu_1043_p2;
tmp_20_1_1_2_reg_8169 <= grp_fu_999_p2;
tmp_20_1_2_2_reg_8174 <= grp_fu_1003_p2;
tmp_20_1_3_2_reg_8179 <= grp_fu_1007_p2;
tmp_20_1_4_2_reg_8184 <= grp_fu_1011_p2;
tmp_20_1_5_2_reg_8189 <= grp_fu_1015_p2;
tmp_20_1_6_2_reg_8194 <= grp_fu_1019_p2;
tmp_20_1_7_2_reg_8199 <= grp_fu_1023_p2;
tmp_20_1_8_2_reg_8204 <= grp_fu_1027_p2;
tmp_20_1_9_2_reg_8209 <= grp_fu_1031_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp_20_0_10_reg_7114 <= grp_fu_987_p2;
tmp_20_0_11_reg_7119 <= grp_fu_991_p2;
tmp_20_0_1_reg_7064 <= grp_fu_947_p2;
tmp_20_0_2_reg_7069 <= grp_fu_951_p2;
tmp_20_0_3_reg_7074 <= grp_fu_955_p2;
tmp_20_0_4_reg_7079 <= grp_fu_959_p2;
tmp_20_0_5_reg_7084 <= grp_fu_963_p2;
tmp_20_0_6_reg_7089 <= grp_fu_967_p2;
tmp_20_0_7_reg_7094 <= grp_fu_971_p2;
tmp_20_0_8_reg_7099 <= grp_fu_975_p2;
tmp_20_0_9_reg_7104 <= grp_fu_979_p2;
tmp_20_0_s_reg_7109 <= grp_fu_983_p2;
tmp_20_1_10_reg_7179 <= grp_fu_1039_p2;
tmp_20_1_11_reg_7184 <= grp_fu_1043_p2;
tmp_20_1_1_reg_7129 <= grp_fu_999_p2;
tmp_20_1_2_reg_7134 <= grp_fu_1003_p2;
tmp_20_1_3_reg_7139 <= grp_fu_1007_p2;
tmp_20_1_4_reg_7144 <= grp_fu_1011_p2;
tmp_20_1_5_reg_7149 <= grp_fu_1015_p2;
tmp_20_1_6_reg_7154 <= grp_fu_1019_p2;
tmp_20_1_7_reg_7159 <= grp_fu_1023_p2;
tmp_20_1_8_reg_7164 <= grp_fu_1027_p2;
tmp_20_1_9_reg_7169 <= grp_fu_1031_p2;
tmp_20_1_reg_7124 <= grp_fu_995_p2;
tmp_20_1_s_reg_7174 <= grp_fu_1035_p2;
tmp_351_reg_7059 <= grp_fu_943_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_2_0_1_reg_7709 <= grp_fu_943_p2;
tmp_20_2_10_1_reg_7759 <= grp_fu_983_p2;
tmp_20_2_11_1_reg_7764 <= grp_fu_987_p2;
tmp_20_2_12_1_reg_7769 <= grp_fu_991_p2;
tmp_20_2_1_1_reg_7714 <= grp_fu_947_p2;
tmp_20_2_2_1_reg_7719 <= grp_fu_951_p2;
tmp_20_2_3_1_reg_7724 <= grp_fu_955_p2;
tmp_20_2_4_1_reg_7729 <= grp_fu_959_p2;
tmp_20_2_5_1_reg_7734 <= grp_fu_963_p2;
tmp_20_2_6_1_reg_7739 <= grp_fu_967_p2;
tmp_20_2_7_1_reg_7744 <= grp_fu_971_p2;
tmp_20_2_8_1_reg_7749 <= grp_fu_975_p2;
tmp_20_2_9_1_reg_7754 <= grp_fu_979_p2;
tmp_20_3_0_1_reg_7774 <= grp_fu_995_p2;
tmp_20_3_10_1_reg_7824 <= grp_fu_1035_p2;
tmp_20_3_11_1_reg_7829 <= grp_fu_1039_p2;
tmp_20_3_12_1_reg_7834 <= grp_fu_1043_p2;
tmp_20_3_1_1_reg_7779 <= grp_fu_999_p2;
tmp_20_3_2_1_reg_7784 <= grp_fu_1003_p2;
tmp_20_3_3_1_reg_7789 <= grp_fu_1007_p2;
tmp_20_3_4_1_reg_7794 <= grp_fu_1011_p2;
tmp_20_3_5_1_reg_7799 <= grp_fu_1015_p2;
tmp_20_3_6_1_reg_7804 <= grp_fu_1019_p2;
tmp_20_3_7_1_reg_7809 <= grp_fu_1023_p2;
tmp_20_3_8_1_reg_7814 <= grp_fu_1027_p2;
tmp_20_3_9_1_reg_7819 <= grp_fu_1031_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_20_2_0_2_reg_8229 <= grp_fu_943_p2;
tmp_20_2_10_2_reg_8279 <= grp_fu_983_p2;
tmp_20_2_11_2_reg_8284 <= grp_fu_987_p2;
tmp_20_2_12_2_reg_8289 <= grp_fu_991_p2;
tmp_20_2_1_2_reg_8234 <= grp_fu_947_p2;
tmp_20_2_2_2_reg_8239 <= grp_fu_951_p2;
tmp_20_2_3_2_reg_8244 <= grp_fu_955_p2;
tmp_20_2_4_2_reg_8249 <= grp_fu_959_p2;
tmp_20_2_5_2_reg_8254 <= grp_fu_963_p2;
tmp_20_2_6_2_reg_8259 <= grp_fu_967_p2;
tmp_20_2_7_2_reg_8264 <= grp_fu_971_p2;
tmp_20_2_8_2_reg_8269 <= grp_fu_975_p2;
tmp_20_2_9_2_reg_8274 <= grp_fu_979_p2;
tmp_20_3_0_2_reg_8294 <= grp_fu_995_p2;
tmp_20_3_10_2_reg_8344 <= grp_fu_1035_p2;
tmp_20_3_11_2_reg_8349 <= grp_fu_1039_p2;
tmp_20_3_12_2_reg_8354 <= grp_fu_1043_p2;
tmp_20_3_1_2_reg_8299 <= grp_fu_999_p2;
tmp_20_3_2_2_reg_8304 <= grp_fu_1003_p2;
tmp_20_3_3_2_reg_8309 <= grp_fu_1007_p2;
tmp_20_3_4_2_reg_8314 <= grp_fu_1011_p2;
tmp_20_3_5_2_reg_8319 <= grp_fu_1015_p2;
tmp_20_3_6_2_reg_8324 <= grp_fu_1019_p2;
tmp_20_3_7_2_reg_8329 <= grp_fu_1023_p2;
tmp_20_3_8_2_reg_8334 <= grp_fu_1027_p2;
tmp_20_3_9_2_reg_8339 <= grp_fu_1031_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp_20_2_10_reg_7244 <= grp_fu_987_p2;
tmp_20_2_11_reg_7249 <= grp_fu_991_p2;
tmp_20_2_1_reg_7194 <= grp_fu_947_p2;
tmp_20_2_2_reg_7199 <= grp_fu_951_p2;
tmp_20_2_3_reg_7204 <= grp_fu_955_p2;
tmp_20_2_4_reg_7209 <= grp_fu_959_p2;
tmp_20_2_5_reg_7214 <= grp_fu_963_p2;
tmp_20_2_6_reg_7219 <= grp_fu_967_p2;
tmp_20_2_7_reg_7224 <= grp_fu_971_p2;
tmp_20_2_8_reg_7229 <= grp_fu_975_p2;
tmp_20_2_9_reg_7234 <= grp_fu_979_p2;
tmp_20_2_reg_7189 <= grp_fu_943_p2;
tmp_20_2_s_reg_7239 <= grp_fu_983_p2;
tmp_20_3_10_reg_7309 <= grp_fu_1039_p2;
tmp_20_3_11_reg_7314 <= grp_fu_1043_p2;
tmp_20_3_1_reg_7259 <= grp_fu_999_p2;
tmp_20_3_2_reg_7264 <= grp_fu_1003_p2;
tmp_20_3_3_reg_7269 <= grp_fu_1007_p2;
tmp_20_3_4_reg_7274 <= grp_fu_1011_p2;
tmp_20_3_5_reg_7279 <= grp_fu_1015_p2;
tmp_20_3_6_reg_7284 <= grp_fu_1019_p2;
tmp_20_3_7_reg_7289 <= grp_fu_1023_p2;
tmp_20_3_8_reg_7294 <= grp_fu_1027_p2;
tmp_20_3_9_reg_7299 <= grp_fu_1031_p2;
tmp_20_3_reg_7254 <= grp_fu_995_p2;
tmp_20_3_s_reg_7304 <= grp_fu_1035_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_4_0_1_reg_7839 <= grp_fu_1047_p2;
tmp_20_4_10_1_reg_7889 <= grp_fu_1087_p2;
tmp_20_4_11_1_reg_7894 <= grp_fu_1091_p2;
tmp_20_4_12_1_reg_7899 <= grp_fu_1095_p2;
tmp_20_4_1_1_reg_7844 <= grp_fu_1051_p2;
tmp_20_4_2_1_reg_7849 <= grp_fu_1055_p2;
tmp_20_4_3_1_reg_7854 <= grp_fu_1059_p2;
tmp_20_4_4_1_reg_7859 <= grp_fu_1063_p2;
tmp_20_4_5_1_reg_7864 <= grp_fu_1067_p2;
tmp_20_4_6_1_reg_7869 <= grp_fu_1071_p2;
tmp_20_4_7_1_reg_7874 <= grp_fu_1075_p2;
tmp_20_4_8_1_reg_7879 <= grp_fu_1079_p2;
tmp_20_4_9_1_reg_7884 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_20_4_0_2_reg_8359 <= grp_fu_1047_p2;
tmp_20_4_10_2_reg_8409 <= grp_fu_1087_p2;
tmp_20_4_11_2_reg_8414 <= grp_fu_1091_p2;
tmp_20_4_12_2_reg_8419 <= grp_fu_1095_p2;
tmp_20_4_1_2_reg_8364 <= grp_fu_1051_p2;
tmp_20_4_2_2_reg_8369 <= grp_fu_1055_p2;
tmp_20_4_3_2_reg_8374 <= grp_fu_1059_p2;
tmp_20_4_4_2_reg_8379 <= grp_fu_1063_p2;
tmp_20_4_5_2_reg_8384 <= grp_fu_1067_p2;
tmp_20_4_6_2_reg_8389 <= grp_fu_1071_p2;
tmp_20_4_7_2_reg_8394 <= grp_fu_1075_p2;
tmp_20_4_8_2_reg_8399 <= grp_fu_1079_p2;
tmp_20_4_9_2_reg_8404 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
tmp_20_4_10_reg_7374 <= grp_fu_987_p2;
tmp_20_4_11_reg_7379 <= grp_fu_991_p2;
tmp_20_4_1_reg_7324 <= grp_fu_947_p2;
tmp_20_4_2_reg_7329 <= grp_fu_951_p2;
tmp_20_4_3_reg_7334 <= grp_fu_955_p2;
tmp_20_4_4_reg_7339 <= grp_fu_959_p2;
tmp_20_4_5_reg_7344 <= grp_fu_963_p2;
tmp_20_4_6_reg_7349 <= grp_fu_967_p2;
tmp_20_4_7_reg_7354 <= grp_fu_971_p2;
tmp_20_4_8_reg_7359 <= grp_fu_975_p2;
tmp_20_4_9_reg_7364 <= grp_fu_979_p2;
tmp_20_4_reg_7319 <= grp_fu_943_p2;
tmp_20_4_s_reg_7369 <= grp_fu_983_p2;
tmp_20_5_10_reg_7439 <= grp_fu_1039_p2;
tmp_20_5_11_reg_7444 <= grp_fu_1043_p2;
tmp_20_5_1_reg_7389 <= grp_fu_999_p2;
tmp_20_5_2_reg_7394 <= grp_fu_1003_p2;
tmp_20_5_3_reg_7399 <= grp_fu_1007_p2;
tmp_20_5_4_reg_7404 <= grp_fu_1011_p2;
tmp_20_5_5_reg_7409 <= grp_fu_1015_p2;
tmp_20_5_6_reg_7414 <= grp_fu_1019_p2;
tmp_20_5_7_reg_7419 <= grp_fu_1023_p2;
tmp_20_5_8_reg_7424 <= grp_fu_1027_p2;
tmp_20_5_9_reg_7429 <= grp_fu_1031_p2;
tmp_20_5_reg_7384 <= grp_fu_995_p2;
tmp_20_5_s_reg_7434 <= grp_fu_1035_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_5_0_1_reg_7904 <= grp_fu_1047_p2;
tmp_20_5_10_1_reg_7954 <= grp_fu_1087_p2;
tmp_20_5_11_1_reg_7959 <= grp_fu_1091_p2;
tmp_20_5_12_1_reg_7964 <= grp_fu_1095_p2;
tmp_20_5_1_1_reg_7909 <= grp_fu_1051_p2;
tmp_20_5_2_1_reg_7914 <= grp_fu_1055_p2;
tmp_20_5_3_1_reg_7919 <= grp_fu_1059_p2;
tmp_20_5_4_1_reg_7924 <= grp_fu_1063_p2;
tmp_20_5_5_1_reg_7929 <= grp_fu_1067_p2;
tmp_20_5_6_1_reg_7934 <= grp_fu_1071_p2;
tmp_20_5_7_1_reg_7939 <= grp_fu_1075_p2;
tmp_20_5_8_1_reg_7944 <= grp_fu_1079_p2;
tmp_20_5_9_1_reg_7949 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
tmp_20_5_0_2_reg_8424 <= grp_fu_1047_p2;
tmp_20_5_10_2_reg_8474 <= grp_fu_1087_p2;
tmp_20_5_11_2_reg_8479 <= grp_fu_1091_p2;
tmp_20_5_12_2_reg_8484 <= grp_fu_1095_p2;
tmp_20_5_1_2_reg_8429 <= grp_fu_1051_p2;
tmp_20_5_2_2_reg_8434 <= grp_fu_1055_p2;
tmp_20_5_3_2_reg_8439 <= grp_fu_1059_p2;
tmp_20_5_4_2_reg_8444 <= grp_fu_1063_p2;
tmp_20_5_5_2_reg_8449 <= grp_fu_1067_p2;
tmp_20_5_6_2_reg_8454 <= grp_fu_1071_p2;
tmp_20_5_7_2_reg_8459 <= grp_fu_1075_p2;
tmp_20_5_8_2_reg_8464 <= grp_fu_1079_p2;
tmp_20_5_9_2_reg_8469 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
tmp_20_6_0_1_reg_7969 <= grp_fu_1047_p2;
tmp_20_6_10_1_reg_8019 <= grp_fu_1087_p2;
tmp_20_6_11_1_reg_8024 <= grp_fu_1091_p2;
tmp_20_6_12_1_reg_8029 <= grp_fu_1095_p2;
tmp_20_6_1_1_reg_7974 <= grp_fu_1051_p2;
tmp_20_6_2_1_reg_7979 <= grp_fu_1055_p2;
tmp_20_6_3_1_reg_7984 <= grp_fu_1059_p2;
tmp_20_6_4_1_reg_7989 <= grp_fu_1063_p2;
tmp_20_6_5_1_reg_7994 <= grp_fu_1067_p2;
tmp_20_6_6_1_reg_7999 <= grp_fu_1071_p2;
tmp_20_6_7_1_reg_8004 <= grp_fu_1075_p2;
tmp_20_6_8_1_reg_8009 <= grp_fu_1079_p2;
tmp_20_6_9_1_reg_8014 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
tmp_20_6_0_2_reg_8489 <= grp_fu_1047_p2;
tmp_20_6_10_2_reg_8539 <= grp_fu_1087_p2;
tmp_20_6_11_2_reg_8544 <= grp_fu_1091_p2;
tmp_20_6_12_2_reg_8549 <= grp_fu_1095_p2;
tmp_20_6_1_2_reg_8494 <= grp_fu_1051_p2;
tmp_20_6_2_2_reg_8499 <= grp_fu_1055_p2;
tmp_20_6_3_2_reg_8504 <= grp_fu_1059_p2;
tmp_20_6_4_2_reg_8509 <= grp_fu_1063_p2;
tmp_20_6_5_2_reg_8514 <= grp_fu_1067_p2;
tmp_20_6_6_2_reg_8519 <= grp_fu_1071_p2;
tmp_20_6_7_2_reg_8524 <= grp_fu_1075_p2;
tmp_20_6_8_2_reg_8529 <= grp_fu_1079_p2;
tmp_20_6_9_2_reg_8534 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter3_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
tmp_20_6_10_reg_7504 <= grp_fu_987_p2;
tmp_20_6_11_reg_7509 <= grp_fu_991_p2;
tmp_20_6_1_reg_7454 <= grp_fu_947_p2;
tmp_20_6_2_reg_7459 <= grp_fu_951_p2;
tmp_20_6_3_reg_7464 <= grp_fu_955_p2;
tmp_20_6_4_reg_7469 <= grp_fu_959_p2;
tmp_20_6_5_reg_7474 <= grp_fu_963_p2;
tmp_20_6_6_reg_7479 <= grp_fu_967_p2;
tmp_20_6_7_reg_7484 <= grp_fu_971_p2;
tmp_20_6_8_reg_7489 <= grp_fu_975_p2;
tmp_20_6_9_reg_7494 <= grp_fu_979_p2;
tmp_20_6_reg_7449 <= grp_fu_943_p2;
tmp_20_6_s_reg_7499 <= grp_fu_983_p2;
tmp_20_7_10_reg_7569 <= grp_fu_1039_p2;
tmp_20_7_11_reg_7574 <= grp_fu_1043_p2;
tmp_20_7_1_reg_7519 <= grp_fu_999_p2;
tmp_20_7_2_reg_7524 <= grp_fu_1003_p2;
tmp_20_7_3_reg_7529 <= grp_fu_1007_p2;
tmp_20_7_4_reg_7534 <= grp_fu_1011_p2;
tmp_20_7_5_reg_7539 <= grp_fu_1015_p2;
tmp_20_7_6_reg_7544 <= grp_fu_1019_p2;
tmp_20_7_7_reg_7549 <= grp_fu_1023_p2;
tmp_20_7_8_reg_7554 <= grp_fu_1027_p2;
tmp_20_7_9_reg_7559 <= grp_fu_1031_p2;
tmp_20_7_reg_7514 <= grp_fu_995_p2;
tmp_20_7_s_reg_7564 <= grp_fu_1035_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_reg_pp0_iter5_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
tmp_20_7_0_1_reg_8034 <= grp_fu_1047_p2;
tmp_20_7_10_1_reg_8084 <= grp_fu_1087_p2;
tmp_20_7_11_1_reg_8089 <= grp_fu_1091_p2;
tmp_20_7_12_1_reg_8094 <= grp_fu_1095_p2;
tmp_20_7_1_1_reg_8039 <= grp_fu_1051_p2;
tmp_20_7_2_1_reg_8044 <= grp_fu_1055_p2;
tmp_20_7_3_1_reg_8049 <= grp_fu_1059_p2;
tmp_20_7_4_1_reg_8054 <= grp_fu_1063_p2;
tmp_20_7_5_1_reg_8059 <= grp_fu_1067_p2;
tmp_20_7_6_1_reg_8064 <= grp_fu_1071_p2;
tmp_20_7_7_1_reg_8069 <= grp_fu_1075_p2;
tmp_20_7_8_1_reg_8074 <= grp_fu_1079_p2;
tmp_20_7_9_1_reg_8079 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter8_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8))) then
tmp_20_7_0_2_reg_8554 <= grp_fu_1047_p2;
tmp_20_7_10_2_reg_8604 <= grp_fu_1087_p2;
tmp_20_7_11_2_reg_8609 <= grp_fu_1091_p2;
tmp_20_7_12_2_reg_8614 <= grp_fu_1095_p2;
tmp_20_7_1_2_reg_8559 <= grp_fu_1051_p2;
tmp_20_7_2_2_reg_8564 <= grp_fu_1055_p2;
tmp_20_7_3_2_reg_8569 <= grp_fu_1059_p2;
tmp_20_7_4_2_reg_8574 <= grp_fu_1063_p2;
tmp_20_7_5_2_reg_8579 <= grp_fu_1067_p2;
tmp_20_7_6_2_reg_8584 <= grp_fu_1071_p2;
tmp_20_7_7_2_reg_8589 <= grp_fu_1075_p2;
tmp_20_7_8_2_reg_8594 <= grp_fu_1079_p2;
tmp_20_7_9_2_reg_8599 <= grp_fu_1083_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
tmp_210_reg_3511 <= tmp_210_fu_1876_p2;
tmp_250_reg_3516 <= tmp_250_fu_1881_p2;
tmp_7_reg_3356 <= tmp_7_fu_1807_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
tmp_290_reg_3616 <= tmp_290_fu_1978_p2;
tmp_330_reg_3621 <= tmp_330_fu_1983_p2;
tmp_331_reg_3626 <= tmp_331_fu_1988_p2;
tmp_332_reg_3631 <= tmp_332_fu_1993_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
tmp_2_reg_3281 <= tmp_2_fu_1657_p2;
tmp_90_reg_3299(9 downto 2) <= tmp_90_fu_1694_p2(9 downto 2);
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
tmp_355_reg_4719 <= tmp_355_fu_2149_p1;
tmp_356_reg_4784 <= tmp_356_fu_2153_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter1_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
tmp_357_reg_5044 <= tmp_357_fu_2157_p1;
tmp_358_reg_5109 <= tmp_358_fu_2161_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
tmp_5_mid2_reg_3286 <= tmp_5_mid2_fu_1662_p3;
end if;
end if;
end process;
tmp_90_reg_3299(1 downto 0) <= "00";
tmp_5_mid2_cast2_reg_3316(6 downto 3) <= "0000";
tmp_333_reg_4307(2 downto 0) <= "000";
bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter2_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter3_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter4_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter5_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter6_bufo_addr_reg_4317(2 downto 0) <= "000";
ap_reg_pp0_iter7_bufo_addr_reg_4317(2 downto 0) <= "000";
bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter2_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter3_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter4_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter5_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter6_bufo_addr_1_reg_4322(2 downto 0) <= "001";
ap_reg_pp0_iter7_bufo_addr_1_reg_4322(2 downto 0) <= "001";
bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter2_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter3_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter4_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter5_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter6_bufo_addr_2_reg_4429(2 downto 0) <= "010";
ap_reg_pp0_iter7_bufo_addr_2_reg_4429(2 downto 0) <= "010";
bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter2_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter3_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter4_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter5_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter6_bufo_addr_3_reg_4434(2 downto 0) <= "011";
ap_reg_pp0_iter7_bufo_addr_3_reg_4434(2 downto 0) <= "011";
bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter2_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter3_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter4_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter5_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter6_bufo_addr_4_reg_4439(2 downto 0) <= "100";
ap_reg_pp0_iter7_bufo_addr_4_reg_4439(2 downto 0) <= "100";
bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter2_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter3_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter4_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter5_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter6_bufo_addr_5_reg_4444(2 downto 0) <= "101";
ap_reg_pp0_iter7_bufo_addr_5_reg_4444(2 downto 0) <= "101";
bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter2_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter3_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter4_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter5_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter6_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter7_bufo_addr_6_reg_4579(2 downto 0) <= "110";
ap_reg_pp0_iter8_bufo_addr_6_reg_4579(2 downto 0) <= "110";
bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter2_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter3_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter4_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter5_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter6_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter7_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_reg_pp0_iter8_bufo_addr_7_reg_4584(2 downto 0) <= "111";
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, exitcond_flatten1_fu_1541_p2, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter8, ap_block_pp0_stage0_subdone, ap_block_pp0_stage7_subdone, ap_block_pp0_stage1_subdone, ap_enable_reg_pp0_iter9, ap_block_pp0_stage2_subdone, ap_block_pp0_stage3_subdone, ap_block_pp0_stage4_subdone, ap_block_pp0_stage5_subdone, ap_block_pp0_stage6_subdone)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_pp0_stage0 =>
if ((not(((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (exitcond_flatten1_fu_1541_p2 = ap_const_lv1_1) and (ap_block_pp0_stage0_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) and (ap_block_pp0_stage0_subdone = ap_const_boolean_0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
elsif (((ap_enable_reg_pp0_iter1 = ap_const_logic_0) and (exitcond_flatten1_fu_1541_p2 = ap_const_lv1_1) and (ap_block_pp0_stage0_subdone = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
ap_NS_fsm <= ap_ST_fsm_state76;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if ((not(((ap_block_pp0_stage1_subdone = ap_const_boolean_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) and (ap_block_pp0_stage1_subdone = ap_const_boolean_0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
elsif (((ap_block_pp0_stage1_subdone = ap_const_boolean_0) and (ap_enable_reg_pp0_iter8 = ap_const_logic_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
ap_NS_fsm <= ap_ST_fsm_state76;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if ((ap_block_pp0_stage5_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_pp0_stage6 =>
if ((ap_block_pp0_stage6_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
end if;
when ap_ST_fsm_pp0_stage7 =>
if ((ap_block_pp0_stage7_subdone = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
end if;
when ap_ST_fsm_state76 =>
ap_NS_fsm <= ap_ST_fsm_state1;
when others =>
ap_NS_fsm <= "XXXXXXXXXX";
end case;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(3);
ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(4);
ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(5);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(6);
ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(7);
ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(8);
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state76 <= ap_CS_fsm(9);
ap_block_pp0_stage0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_11001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_subdone <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage6_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage7_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage1_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state20_pp0_stage2_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage3_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage4_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage5_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage6_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage7_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage0_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage1_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage2_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state29_pp0_stage3_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage0_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state30_pp0_stage4_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state31_pp0_stage5_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state32_pp0_stage6_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state33_pp0_stage7_iter3 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state34_pp0_stage0_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state35_pp0_stage1_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state36_pp0_stage2_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state37_pp0_stage3_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state38_pp0_stage4_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state39_pp0_stage5_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state40_pp0_stage6_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state41_pp0_stage7_iter4 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state42_pp0_stage0_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state43_pp0_stage1_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state44_pp0_stage2_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state45_pp0_stage3_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state46_pp0_stage4_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state47_pp0_stage5_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state48_pp0_stage6_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state49_pp0_stage7_iter5 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state50_pp0_stage0_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state51_pp0_stage1_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state52_pp0_stage2_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state53_pp0_stage3_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state54_pp0_stage4_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state55_pp0_stage5_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state56_pp0_stage6_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state57_pp0_stage7_iter6 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state58_pp0_stage0_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state59_pp0_stage1_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state60_pp0_stage2_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state61_pp0_stage3_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state62_pp0_stage4_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state63_pp0_stage5_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state64_pp0_stage6_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state65_pp0_stage7_iter7 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state66_pp0_stage0_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state67_pp0_stage1_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state68_pp0_stage2_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state69_pp0_stage3_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state70_pp0_stage4_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state71_pp0_stage5_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state72_pp0_stage6_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state73_pp0_stage7_iter8 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state74_pp0_stage0_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state75_pp0_stage1_iter9 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_condition_pp0_exit_iter0_state2_assign_proc : process(exitcond_flatten1_fu_1541_p2)
begin
if ((exitcond_flatten1_fu_1541_p2 = ap_const_lv1_1)) then
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_1;
else
ap_condition_pp0_exit_iter0_state2 <= ap_const_logic_0;
end if;
end process;
ap_done_assign_proc : process(ap_CS_fsm_state76)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state76)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter9) and (ap_const_logic_0 = ap_enable_reg_pp0_iter8) and (ap_const_logic_0 = ap_enable_reg_pp0_iter7) and (ap_const_logic_0 = ap_enable_reg_pp0_iter6) and (ap_const_logic_0 = ap_enable_reg_pp0_iter5) and (ap_const_logic_0 = ap_enable_reg_pp0_iter4) and (ap_const_logic_0 = ap_enable_reg_pp0_iter3) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_phi_mux_i_phi_fu_900_p4_assign_proc : process(i_reg_896, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, tmp_1_mid2_v_reg_3225, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_i_phi_fu_900_p4 <= tmp_1_mid2_v_reg_3225;
else
ap_phi_mux_i_phi_fu_900_p4 <= i_reg_896;
end if;
end process;
ap_phi_mux_indvar_flatten1_phi_fu_889_p4_assign_proc : process(indvar_flatten1_reg_885, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, indvar_flatten_next1_reg_3180, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_indvar_flatten1_phi_fu_889_p4 <= indvar_flatten_next1_reg_3180;
else
ap_phi_mux_indvar_flatten1_phi_fu_889_p4 <= indvar_flatten1_reg_885;
end if;
end process;
ap_phi_mux_indvar_flatten_phi_fu_912_p4_assign_proc : process(indvar_flatten_reg_908, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, indvar_flatten_next_reg_3252, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_indvar_flatten_phi_fu_912_p4 <= indvar_flatten_next_reg_3252;
else
ap_phi_mux_indvar_flatten_phi_fu_912_p4 <= indvar_flatten_reg_908;
end if;
end process;
ap_phi_mux_j_phi_fu_923_p4_assign_proc : process(j_reg_919, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, tmp_5_mid2_reg_3286, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_j_phi_fu_923_p4 <= tmp_5_mid2_reg_3286;
else
ap_phi_mux_j_phi_fu_923_p4 <= j_reg_919;
end if;
end process;
ap_phi_mux_row_b_phi_fu_935_p4_assign_proc : process(row_b_reg_931, ap_CS_fsm_pp0_stage0, exitcond_flatten1_reg_3176, row_b_1_reg_3276, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
ap_phi_mux_row_b_phi_fu_935_p4 <= row_b_1_reg_3276;
else
ap_phi_mux_row_b_phi_fu_935_p4 <= row_b_reg_931;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state76)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state76)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
bufi_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_0_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_334_cast_fu_1864_p1, ap_block_pp0_stage6, tmp_336_cast_fu_1966_p1, tmp_338_cast_fu_1998_p1, ap_block_pp0_stage7, tmp_340_cast_fu_2010_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_0_Addr_A_orig <= tmp_340_cast_fu_2010_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_A_orig <= tmp_338_cast_fu_1998_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_A_orig <= tmp_336_cast_fu_1966_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_A_orig <= tmp_334_cast_fu_1864_p1(32 - 1 downto 0);
else
bufi_0_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_0_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_0_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_0_Addr_B_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_335_cast_fu_1870_p1, ap_block_pp0_stage6, tmp_337_cast_fu_1972_p1, ap_block_pp0_stage7, tmp_339_cast_fu_2004_p1, tmp_341_cast_fu_2016_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_0_Addr_B_orig <= tmp_341_cast_fu_2016_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_B_orig <= tmp_339_cast_fu_2004_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_B_orig <= tmp_337_cast_fu_1972_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_0_Addr_B_orig <= tmp_335_cast_fu_1870_p1(32 - 1 downto 0);
else
bufi_0_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_0_Clk_A <= ap_clk;
bufi_0_Clk_B <= ap_clk;
bufi_0_Din_A <= ap_const_lv32_0;
bufi_0_Din_B <= ap_const_lv32_0;
bufi_0_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_0_EN_A <= ap_const_logic_1;
else
bufi_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_0_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_0_EN_B <= ap_const_logic_1;
else
bufi_0_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_0_Rst_A <= ap_rst_n_inv;
bufi_0_Rst_B <= ap_rst_n_inv;
bufi_0_WEN_A <= ap_const_lv4_0;
bufi_0_WEN_B <= ap_const_lv4_0;
bufi_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_1_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_334_cast_fu_1864_p1, ap_block_pp0_stage6, tmp_336_cast_fu_1966_p1, tmp_338_cast_fu_1998_p1, ap_block_pp0_stage7, tmp_340_cast_fu_2010_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_1_Addr_A_orig <= tmp_340_cast_fu_2010_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_A_orig <= tmp_338_cast_fu_1998_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_A_orig <= tmp_336_cast_fu_1966_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_A_orig <= tmp_334_cast_fu_1864_p1(32 - 1 downto 0);
else
bufi_1_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_1_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_1_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_1_Addr_B_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_335_cast_fu_1870_p1, ap_block_pp0_stage6, tmp_337_cast_fu_1972_p1, ap_block_pp0_stage7, tmp_339_cast_fu_2004_p1, tmp_341_cast_fu_2016_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_1_Addr_B_orig <= tmp_341_cast_fu_2016_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_B_orig <= tmp_339_cast_fu_2004_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_B_orig <= tmp_337_cast_fu_1972_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_1_Addr_B_orig <= tmp_335_cast_fu_1870_p1(32 - 1 downto 0);
else
bufi_1_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_1_Clk_A <= ap_clk;
bufi_1_Clk_B <= ap_clk;
bufi_1_Din_A <= ap_const_lv32_0;
bufi_1_Din_B <= ap_const_lv32_0;
bufi_1_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_1_EN_A <= ap_const_logic_1;
else
bufi_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_1_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_1_EN_B <= ap_const_logic_1;
else
bufi_1_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_1_Rst_A <= ap_rst_n_inv;
bufi_1_Rst_B <= ap_rst_n_inv;
bufi_1_WEN_A <= ap_const_lv4_0;
bufi_1_WEN_B <= ap_const_lv4_0;
bufi_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufi_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_2_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_334_cast_fu_1864_p1, ap_block_pp0_stage6, tmp_336_cast_fu_1966_p1, tmp_338_cast_fu_1998_p1, ap_block_pp0_stage7, tmp_340_cast_fu_2010_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_2_Addr_A_orig <= tmp_340_cast_fu_2010_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_A_orig <= tmp_338_cast_fu_1998_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_A_orig <= tmp_336_cast_fu_1966_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_A_orig <= tmp_334_cast_fu_1864_p1(32 - 1 downto 0);
else
bufi_2_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_2_Addr_B <= std_logic_vector(shift_left(unsigned(bufi_2_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufi_2_Addr_B_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, tmp_335_cast_fu_1870_p1, ap_block_pp0_stage6, tmp_337_cast_fu_1972_p1, ap_block_pp0_stage7, tmp_339_cast_fu_2004_p1, tmp_341_cast_fu_2016_p1)
begin
if (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufi_2_Addr_B_orig <= tmp_341_cast_fu_2016_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_B_orig <= tmp_339_cast_fu_2004_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_B_orig <= tmp_337_cast_fu_1972_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0))) then
bufi_2_Addr_B_orig <= tmp_335_cast_fu_1870_p1(32 - 1 downto 0);
else
bufi_2_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufi_2_Clk_A <= ap_clk;
bufi_2_Clk_B <= ap_clk;
bufi_2_Din_A <= ap_const_lv32_0;
bufi_2_Din_B <= ap_const_lv32_0;
bufi_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_2_EN_A <= ap_const_logic_1;
else
bufi_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufi_2_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufi_2_EN_B <= ap_const_logic_1;
else
bufi_2_EN_B <= ap_const_logic_0;
end if;
end process;
bufi_2_Rst_A <= ap_rst_n_inv;
bufi_2_Rst_B <= ap_rst_n_inv;
bufi_2_WEN_A <= ap_const_lv4_0;
bufi_2_WEN_B <= ap_const_lv4_0;
bufo_Addr_A <= std_logic_vector(shift_left(unsigned(bufo_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
bufo_Addr_A_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_reg_pp0_iter7_bufo_addr_reg_4317, ap_reg_pp0_iter7_bufo_addr_2_reg_4429, ap_reg_pp0_iter7_bufo_addr_4_reg_4439, ap_reg_pp0_iter8_bufo_addr_6_reg_4579, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, tmp_334_fu_2029_p1, ap_block_pp0_stage2, tmp_338_fu_2054_p3, ap_block_pp0_stage3, tmp_342_fu_2082_p3, ap_block_pp0_stage4, tmp_346_fu_2118_p3, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter8_bufo_addr_6_reg_4579),32));
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_4_reg_4439),32));
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_2_reg_4429),32));
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Addr_A_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_reg_4317),32));
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufo_Addr_A_orig <= tmp_346_fu_2118_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
bufo_Addr_A_orig <= tmp_342_fu_2082_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
bufo_Addr_A_orig <= tmp_338_fu_2054_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
bufo_Addr_A_orig <= tmp_334_fu_2029_p1(32 - 1 downto 0);
else
bufo_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_Addr_B <= std_logic_vector(shift_left(unsigned(bufo_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_6(31-1 downto 0)))));
bufo_Addr_B_orig_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter1, ap_reg_pp0_iter7_bufo_addr_1_reg_4322, ap_reg_pp0_iter7_bufo_addr_3_reg_4434, ap_reg_pp0_iter7_bufo_addr_5_reg_4444, ap_reg_pp0_iter8_bufo_addr_7_reg_4584, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, tmp_336_fu_2040_p3, ap_block_pp0_stage3, tmp_340_fu_2068_p3, ap_block_pp0_stage4, tmp_344_fu_2096_p3, tmp_348_fu_2132_p3, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
bufo_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter8_bufo_addr_7_reg_4584),32));
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufo_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_5_reg_4444),32));
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_3_reg_4434),32));
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Addr_B_orig <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_reg_pp0_iter7_bufo_addr_1_reg_4322),32));
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufo_Addr_B_orig <= tmp_348_fu_2132_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
bufo_Addr_B_orig <= tmp_344_fu_2096_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
bufo_Addr_B_orig <= tmp_340_fu_2068_p3(32 - 1 downto 0);
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
bufo_Addr_B_orig <= tmp_336_fu_2040_p3(32 - 1 downto 0);
else
bufo_Addr_B_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_Clk_A <= ap_clk;
bufo_Clk_B <= ap_clk;
bufo_Din_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0, ap_block_pp0_stage6, ap_block_pp0_stage7, tmp_49_fu_2620_p14, tmp_129_fu_2760_p14, tmp_209_fu_2900_p14, tmp_289_fu_3040_p14, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
bufo_Din_A <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_289_fu_3040_p14),512));
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufo_Din_A <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_209_fu_2900_p14),512));
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Din_A <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_129_fu_2760_p14),512));
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Din_A <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_49_fu_2620_p14),512));
else
bufo_Din_A <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_Din_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9, ap_block_pp0_stage0, ap_block_pp0_stage6, ap_block_pp0_stage7, tmp_89_fu_2690_p14, tmp_169_fu_2830_p14, tmp_249_fu_2970_p14, ap_block_pp0_stage1, tmp_329_fu_3110_p14)
begin
if (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9))) then
bufo_Din_B <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_329_fu_3110_p14),512));
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
bufo_Din_B <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_249_fu_2970_p14),512));
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Din_B <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_169_fu_2830_p14),512));
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7))) then
bufo_Din_B <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_89_fu_2690_p14),512));
else
bufo_Din_B <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufo_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_11001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufo_EN_A <= ap_const_logic_1;
else
bufo_EN_A <= ap_const_logic_0;
end if;
end process;
bufo_EN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_11001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_11001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_11001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufo_EN_B <= ap_const_logic_1;
else
bufo_EN_B <= ap_const_logic_0;
end if;
end process;
bufo_Rst_A <= ap_rst_n_inv;
bufo_Rst_B <= ap_rst_n_inv;
bufo_WEN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_reg_pp0_iter7_exitcond_flatten1_reg_3176, ap_reg_pp0_iter9_exitcond_flatten1_reg_3176, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)) or ((ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufo_WEN_A <= ap_const_lv64_FFFFFFFFFFFFFFFF;
else
bufo_WEN_A <= ap_const_lv64_0;
end if;
end process;
bufo_WEN_B_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_reg_pp0_iter7_exitcond_flatten1_reg_3176, ap_reg_pp0_iter9_exitcond_flatten1_reg_3176, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter7, ap_enable_reg_pp0_iter8, ap_enable_reg_pp0_iter9)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter7)) or ((ap_block_pp0_stage1_11001 = ap_const_boolean_0) and (ap_reg_pp0_iter9_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter9)) or ((ap_reg_pp0_iter7_exitcond_flatten1_reg_3176 = ap_const_lv1_0) and (ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter8) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufo_WEN_B <= ap_const_lv64_FFFFFFFFFFFFFFFF;
else
bufo_WEN_B <= ap_const_lv64_0;
end if;
end process;
bufw_0_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_0_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_0_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_0_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_0_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_0_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_0_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_0_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_0_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_0_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_0_Clk_A <= ap_clk;
bufw_0_Clk_B <= ap_clk;
bufw_0_Din_A <= ap_const_lv32_0;
bufw_0_Din_B <= ap_const_lv32_0;
bufw_0_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_0_EN_A <= ap_const_logic_1;
else
bufw_0_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_0_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_0_EN_B <= ap_const_logic_1;
else
bufw_0_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_0_Rst_A <= ap_rst_n_inv;
bufw_0_Rst_B <= ap_rst_n_inv;
bufw_0_WEN_A <= ap_const_lv4_0;
bufw_0_WEN_B <= ap_const_lv4_0;
bufw_10_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_10_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_10_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_10_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_10_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_10_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_10_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_10_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_10_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_10_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_10_Clk_A <= ap_clk;
bufw_10_Clk_B <= ap_clk;
bufw_10_Din_A <= ap_const_lv32_0;
bufw_10_Din_B <= ap_const_lv32_0;
bufw_10_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_10_EN_A <= ap_const_logic_1;
else
bufw_10_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_10_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_10_EN_B <= ap_const_logic_1;
else
bufw_10_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_10_Rst_A <= ap_rst_n_inv;
bufw_10_Rst_B <= ap_rst_n_inv;
bufw_10_WEN_A <= ap_const_lv4_0;
bufw_10_WEN_B <= ap_const_lv4_0;
bufw_11_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_11_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_11_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_11_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_11_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_11_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_11_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_11_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_11_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_11_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_11_Clk_A <= ap_clk;
bufw_11_Clk_B <= ap_clk;
bufw_11_Din_A <= ap_const_lv32_0;
bufw_11_Din_B <= ap_const_lv32_0;
bufw_11_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_11_EN_A <= ap_const_logic_1;
else
bufw_11_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_11_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_11_EN_B <= ap_const_logic_1;
else
bufw_11_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_11_Rst_A <= ap_rst_n_inv;
bufw_11_Rst_B <= ap_rst_n_inv;
bufw_11_WEN_A <= ap_const_lv4_0;
bufw_11_WEN_B <= ap_const_lv4_0;
bufw_12_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_12_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_12_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_12_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_12_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_12_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_12_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_12_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_12_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_12_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_12_Clk_A <= ap_clk;
bufw_12_Clk_B <= ap_clk;
bufw_12_Din_A <= ap_const_lv32_0;
bufw_12_Din_B <= ap_const_lv32_0;
bufw_12_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_12_EN_A <= ap_const_logic_1;
else
bufw_12_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_12_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_12_EN_B <= ap_const_logic_1;
else
bufw_12_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_12_Rst_A <= ap_rst_n_inv;
bufw_12_Rst_B <= ap_rst_n_inv;
bufw_12_WEN_A <= ap_const_lv4_0;
bufw_12_WEN_B <= ap_const_lv4_0;
bufw_1_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_1_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_1_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_1_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_1_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_1_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_1_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_1_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_1_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_1_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_1_Clk_A <= ap_clk;
bufw_1_Clk_B <= ap_clk;
bufw_1_Din_A <= ap_const_lv32_0;
bufw_1_Din_B <= ap_const_lv32_0;
bufw_1_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_1_EN_A <= ap_const_logic_1;
else
bufw_1_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_1_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_1_EN_B <= ap_const_logic_1;
else
bufw_1_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_1_Rst_A <= ap_rst_n_inv;
bufw_1_Rst_B <= ap_rst_n_inv;
bufw_1_WEN_A <= ap_const_lv4_0;
bufw_1_WEN_B <= ap_const_lv4_0;
bufw_2_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_2_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_2_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_2_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_2_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_2_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_2_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_2_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_2_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_2_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_2_Clk_A <= ap_clk;
bufw_2_Clk_B <= ap_clk;
bufw_2_Din_A <= ap_const_lv32_0;
bufw_2_Din_B <= ap_const_lv32_0;
bufw_2_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_2_EN_A <= ap_const_logic_1;
else
bufw_2_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_2_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_2_EN_B <= ap_const_logic_1;
else
bufw_2_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_2_Rst_A <= ap_rst_n_inv;
bufw_2_Rst_B <= ap_rst_n_inv;
bufw_2_WEN_A <= ap_const_lv4_0;
bufw_2_WEN_B <= ap_const_lv4_0;
bufw_3_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_3_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_3_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_3_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_3_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_3_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_3_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_3_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_3_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_3_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_3_Clk_A <= ap_clk;
bufw_3_Clk_B <= ap_clk;
bufw_3_Din_A <= ap_const_lv32_0;
bufw_3_Din_B <= ap_const_lv32_0;
bufw_3_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_3_EN_A <= ap_const_logic_1;
else
bufw_3_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_3_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_3_EN_B <= ap_const_logic_1;
else
bufw_3_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_3_Rst_A <= ap_rst_n_inv;
bufw_3_Rst_B <= ap_rst_n_inv;
bufw_3_WEN_A <= ap_const_lv4_0;
bufw_3_WEN_B <= ap_const_lv4_0;
bufw_4_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_4_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_4_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_4_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_4_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_4_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_4_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_4_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_4_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_4_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_4_Clk_A <= ap_clk;
bufw_4_Clk_B <= ap_clk;
bufw_4_Din_A <= ap_const_lv32_0;
bufw_4_Din_B <= ap_const_lv32_0;
bufw_4_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_4_EN_A <= ap_const_logic_1;
else
bufw_4_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_4_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_4_EN_B <= ap_const_logic_1;
else
bufw_4_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_4_Rst_A <= ap_rst_n_inv;
bufw_4_Rst_B <= ap_rst_n_inv;
bufw_4_WEN_A <= ap_const_lv4_0;
bufw_4_WEN_B <= ap_const_lv4_0;
bufw_5_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_5_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_5_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_5_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_5_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_5_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_5_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_5_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_5_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_5_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_5_Clk_A <= ap_clk;
bufw_5_Clk_B <= ap_clk;
bufw_5_Din_A <= ap_const_lv32_0;
bufw_5_Din_B <= ap_const_lv32_0;
bufw_5_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_5_EN_A <= ap_const_logic_1;
else
bufw_5_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_5_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_5_EN_B <= ap_const_logic_1;
else
bufw_5_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_5_Rst_A <= ap_rst_n_inv;
bufw_5_Rst_B <= ap_rst_n_inv;
bufw_5_WEN_A <= ap_const_lv4_0;
bufw_5_WEN_B <= ap_const_lv4_0;
bufw_6_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_6_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_6_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_6_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_6_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_6_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_6_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_6_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_6_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_6_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_6_Clk_A <= ap_clk;
bufw_6_Clk_B <= ap_clk;
bufw_6_Din_A <= ap_const_lv32_0;
bufw_6_Din_B <= ap_const_lv32_0;
bufw_6_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_6_EN_A <= ap_const_logic_1;
else
bufw_6_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_6_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_6_EN_B <= ap_const_logic_1;
else
bufw_6_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_6_Rst_A <= ap_rst_n_inv;
bufw_6_Rst_B <= ap_rst_n_inv;
bufw_6_WEN_A <= ap_const_lv4_0;
bufw_6_WEN_B <= ap_const_lv4_0;
bufw_7_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_7_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_7_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_7_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_7_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_7_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_7_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_7_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_7_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_7_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_7_Clk_A <= ap_clk;
bufw_7_Clk_B <= ap_clk;
bufw_7_Din_A <= ap_const_lv32_0;
bufw_7_Din_B <= ap_const_lv32_0;
bufw_7_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_7_EN_A <= ap_const_logic_1;
else
bufw_7_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_7_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_7_EN_B <= ap_const_logic_1;
else
bufw_7_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_7_Rst_A <= ap_rst_n_inv;
bufw_7_Rst_B <= ap_rst_n_inv;
bufw_7_WEN_A <= ap_const_lv4_0;
bufw_7_WEN_B <= ap_const_lv4_0;
bufw_8_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_8_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_8_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_8_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_8_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_8_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_8_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_8_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_8_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_8_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_8_Clk_A <= ap_clk;
bufw_8_Clk_B <= ap_clk;
bufw_8_Din_A <= ap_const_lv32_0;
bufw_8_Din_B <= ap_const_lv32_0;
bufw_8_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_8_EN_A <= ap_const_logic_1;
else
bufw_8_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_8_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_8_EN_B <= ap_const_logic_1;
else
bufw_8_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_8_Rst_A <= ap_rst_n_inv;
bufw_8_Rst_B <= ap_rst_n_inv;
bufw_8_WEN_A <= ap_const_lv4_0;
bufw_8_WEN_B <= ap_const_lv4_0;
bufw_9_Addr_A <= std_logic_vector(shift_left(unsigned(bufw_9_Addr_A_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_9_Addr_A_orig_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, tmp_6_cast_fu_1775_p1, ap_block_pp0_stage5, tmp_330_cast_fu_1910_p1, ap_block_pp0_stage6)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
bufw_9_Addr_A_orig <= tmp_330_cast_fu_1910_p1(32 - 1 downto 0);
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
bufw_9_Addr_A_orig <= tmp_6_cast_fu_1775_p1(32 - 1 downto 0);
else
bufw_9_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
bufw_9_Addr_A_orig <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
bufw_9_Addr_B <= std_logic_vector(shift_left(unsigned(bufw_9_Addr_B_orig),to_integer(unsigned('0' & ap_const_lv32_2(31-1 downto 0)))));
bufw_9_Addr_B_orig <= tmp_8_cast_fu_1791_p1(32 - 1 downto 0);
bufw_9_Clk_A <= ap_clk;
bufw_9_Clk_B <= ap_clk;
bufw_9_Din_A <= ap_const_lv32_0;
bufw_9_Din_B <= ap_const_lv32_0;
bufw_9_EN_A_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_block_pp0_stage0_11001, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001, ap_enable_reg_pp0_iter1)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage0_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
bufw_9_EN_A <= ap_const_logic_1;
else
bufw_9_EN_A <= ap_const_logic_0;
end if;
end process;
bufw_9_EN_B_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_11001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_11001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_11001)
begin
if ((((ap_block_pp0_stage7_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage6_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)) or ((ap_block_pp0_stage5_11001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0)))) then
bufw_9_EN_B <= ap_const_logic_1;
else
bufw_9_EN_B <= ap_const_logic_0;
end if;
end process;
bufw_9_Rst_A <= ap_rst_n_inv;
bufw_9_Rst_B <= ap_rst_n_inv;
bufw_9_WEN_A <= ap_const_lv4_0;
bufw_9_WEN_B <= ap_const_lv4_0;
exitcond_flatten1_fu_1541_p2 <= "1" when (ap_phi_mux_indvar_flatten1_phi_fu_889_p4 = ap_const_lv10_2A3) else "0";
exitcond_flatten_fu_1559_p2 <= "1" when (ap_phi_mux_indvar_flatten_phi_fu_912_p4 = ap_const_lv8_87) else "0";
grp_fu_1003_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_57_fu_2225_p1, tmp_137_fu_2329_p1, tmp_217_fu_2433_p1, tmp_297_fu_2537_p1, ap_enable_reg_pp0_iter3, tmp_20_1_2_reg_7134, tmp_20_3_2_reg_7264, ap_enable_reg_pp0_iter5, tmp_20_1_2_1_reg_7654, tmp_20_3_2_1_reg_7784, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1003_p0 <= tmp_20_3_2_1_reg_7784;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1003_p0 <= tmp_20_1_2_1_reg_7654;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1003_p0 <= tmp_20_3_2_reg_7264;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1003_p0 <= tmp_20_1_2_reg_7134;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p0 <= tmp_297_fu_2537_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p0 <= tmp_217_fu_2433_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p0 <= tmp_137_fu_2329_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p0 <= tmp_57_fu_2225_p1;
else
grp_fu_1003_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1003_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_2_reg_4989, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264, tmp_19_3_2_reg_5444, tmp_19_5_2_reg_5769, ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834, tmp_19_7_2_reg_6094, ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549, ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1003_p1 <= ap_reg_pp0_iter4_tmp_19_3_2_2_reg_6744;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1003_p1 <= ap_reg_pp0_iter4_tmp_19_1_2_2_reg_6549;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1003_p1 <= ap_reg_pp0_iter3_tmp_19_3_2_1_reg_5834;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1003_p1 <= ap_reg_pp0_iter3_tmp_19_1_2_1_reg_5264;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p1 <= tmp_19_7_2_reg_6094;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p1 <= tmp_19_5_2_reg_5769;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p1 <= tmp_19_3_2_reg_5444;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1003_p1 <= tmp_19_1_2_reg_4989;
else
grp_fu_1003_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1007_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_60_fu_2229_p1, tmp_140_fu_2333_p1, tmp_220_fu_2437_p1, tmp_300_fu_2541_p1, ap_enable_reg_pp0_iter3, tmp_20_1_3_reg_7139, tmp_20_3_3_reg_7269, ap_enable_reg_pp0_iter5, tmp_20_1_3_1_reg_7659, tmp_20_3_3_1_reg_7789, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1007_p0 <= tmp_20_3_3_1_reg_7789;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1007_p0 <= tmp_20_1_3_1_reg_7659;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1007_p0 <= tmp_20_3_3_reg_7269;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1007_p0 <= tmp_20_1_3_reg_7139;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p0 <= tmp_300_fu_2541_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p0 <= tmp_220_fu_2437_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p0 <= tmp_140_fu_2333_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p0 <= tmp_60_fu_2229_p1;
else
grp_fu_1007_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1007_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_3_reg_4994, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274, tmp_19_3_3_reg_5449, tmp_19_5_3_reg_5774, ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839, tmp_19_7_3_reg_6099, ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554, ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1007_p1 <= ap_reg_pp0_iter4_tmp_19_3_3_2_reg_6749;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1007_p1 <= ap_reg_pp0_iter4_tmp_19_1_3_2_reg_6554;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1007_p1 <= ap_reg_pp0_iter3_tmp_19_3_3_1_reg_5839;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1007_p1 <= ap_reg_pp0_iter3_tmp_19_1_3_1_reg_5274;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p1 <= tmp_19_7_3_reg_6099;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p1 <= tmp_19_5_3_reg_5774;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p1 <= tmp_19_3_3_reg_5449;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1007_p1 <= tmp_19_1_3_reg_4994;
else
grp_fu_1007_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1011_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_63_fu_2233_p1, tmp_143_fu_2337_p1, tmp_223_fu_2441_p1, tmp_303_fu_2545_p1, ap_enable_reg_pp0_iter3, tmp_20_1_4_reg_7144, tmp_20_3_4_reg_7274, ap_enable_reg_pp0_iter5, tmp_20_1_4_1_reg_7664, tmp_20_3_4_1_reg_7794, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1011_p0 <= tmp_20_3_4_1_reg_7794;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1011_p0 <= tmp_20_1_4_1_reg_7664;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1011_p0 <= tmp_20_3_4_reg_7274;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1011_p0 <= tmp_20_1_4_reg_7144;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p0 <= tmp_303_fu_2545_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p0 <= tmp_223_fu_2441_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p0 <= tmp_143_fu_2337_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p0 <= tmp_63_fu_2233_p1;
else
grp_fu_1011_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1011_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_4_reg_4999, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284, tmp_19_3_4_reg_5454, tmp_19_5_4_reg_5779, ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844, tmp_19_7_4_reg_6104, ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559, ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1011_p1 <= ap_reg_pp0_iter4_tmp_19_3_4_2_reg_6754;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1011_p1 <= ap_reg_pp0_iter4_tmp_19_1_4_2_reg_6559;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1011_p1 <= ap_reg_pp0_iter3_tmp_19_3_4_1_reg_5844;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1011_p1 <= ap_reg_pp0_iter3_tmp_19_1_4_1_reg_5284;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p1 <= tmp_19_7_4_reg_6104;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p1 <= tmp_19_5_4_reg_5779;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p1 <= tmp_19_3_4_reg_5454;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1011_p1 <= tmp_19_1_4_reg_4999;
else
grp_fu_1011_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1015_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_66_fu_2237_p1, tmp_146_fu_2341_p1, tmp_226_fu_2445_p1, tmp_306_fu_2549_p1, ap_enable_reg_pp0_iter3, tmp_20_1_5_reg_7149, tmp_20_3_5_reg_7279, ap_enable_reg_pp0_iter5, tmp_20_1_5_1_reg_7669, tmp_20_3_5_1_reg_7799, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1015_p0 <= tmp_20_3_5_1_reg_7799;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1015_p0 <= tmp_20_1_5_1_reg_7669;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1015_p0 <= tmp_20_3_5_reg_7279;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1015_p0 <= tmp_20_1_5_reg_7149;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p0 <= tmp_306_fu_2549_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p0 <= tmp_226_fu_2445_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p0 <= tmp_146_fu_2341_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p0 <= tmp_66_fu_2237_p1;
else
grp_fu_1015_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1015_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_5_reg_5004, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294, tmp_19_3_5_reg_5459, tmp_19_5_5_reg_5784, ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849, tmp_19_7_5_reg_6109, ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564, ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1015_p1 <= ap_reg_pp0_iter4_tmp_19_3_5_2_reg_6759;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1015_p1 <= ap_reg_pp0_iter4_tmp_19_1_5_2_reg_6564;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1015_p1 <= ap_reg_pp0_iter3_tmp_19_3_5_1_reg_5849;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1015_p1 <= ap_reg_pp0_iter3_tmp_19_1_5_1_reg_5294;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p1 <= tmp_19_7_5_reg_6109;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p1 <= tmp_19_5_5_reg_5784;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p1 <= tmp_19_3_5_reg_5459;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1015_p1 <= tmp_19_1_5_reg_5004;
else
grp_fu_1015_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1019_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_69_fu_2241_p1, tmp_149_fu_2345_p1, tmp_229_fu_2449_p1, tmp_309_fu_2553_p1, ap_enable_reg_pp0_iter3, tmp_20_1_6_reg_7154, tmp_20_3_6_reg_7284, ap_enable_reg_pp0_iter5, tmp_20_1_6_1_reg_7674, tmp_20_3_6_1_reg_7804, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1019_p0 <= tmp_20_3_6_1_reg_7804;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1019_p0 <= tmp_20_1_6_1_reg_7674;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1019_p0 <= tmp_20_3_6_reg_7284;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1019_p0 <= tmp_20_1_6_reg_7154;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p0 <= tmp_309_fu_2553_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p0 <= tmp_229_fu_2449_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p0 <= tmp_149_fu_2345_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p0 <= tmp_69_fu_2241_p1;
else
grp_fu_1019_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1019_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_6_reg_5009, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304, tmp_19_3_6_reg_5464, tmp_19_5_6_reg_5789, ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854, tmp_19_7_6_reg_6114, ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569, ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1019_p1 <= ap_reg_pp0_iter4_tmp_19_3_6_2_reg_6764;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1019_p1 <= ap_reg_pp0_iter4_tmp_19_1_6_2_reg_6569;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1019_p1 <= ap_reg_pp0_iter3_tmp_19_3_6_1_reg_5854;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1019_p1 <= ap_reg_pp0_iter3_tmp_19_1_6_1_reg_5304;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p1 <= tmp_19_7_6_reg_6114;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p1 <= tmp_19_5_6_reg_5789;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p1 <= tmp_19_3_6_reg_5464;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1019_p1 <= tmp_19_1_6_reg_5009;
else
grp_fu_1019_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1023_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_72_fu_2245_p1, tmp_152_fu_2349_p1, tmp_232_fu_2453_p1, tmp_312_fu_2557_p1, ap_enable_reg_pp0_iter3, tmp_20_1_7_reg_7159, tmp_20_3_7_reg_7289, ap_enable_reg_pp0_iter5, tmp_20_1_7_1_reg_7679, tmp_20_3_7_1_reg_7809, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1023_p0 <= tmp_20_3_7_1_reg_7809;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1023_p0 <= tmp_20_1_7_1_reg_7679;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1023_p0 <= tmp_20_3_7_reg_7289;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1023_p0 <= tmp_20_1_7_reg_7159;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p0 <= tmp_312_fu_2557_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p0 <= tmp_232_fu_2453_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p0 <= tmp_152_fu_2349_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p0 <= tmp_72_fu_2245_p1;
else
grp_fu_1023_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1023_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_7_reg_5014, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314, tmp_19_3_7_reg_5469, tmp_19_5_7_reg_5794, ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859, tmp_19_7_7_reg_6119, ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574, ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1023_p1 <= ap_reg_pp0_iter4_tmp_19_3_7_2_reg_6769;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1023_p1 <= ap_reg_pp0_iter4_tmp_19_1_7_2_reg_6574;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1023_p1 <= ap_reg_pp0_iter3_tmp_19_3_7_1_reg_5859;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1023_p1 <= ap_reg_pp0_iter3_tmp_19_1_7_1_reg_5314;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p1 <= tmp_19_7_7_reg_6119;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p1 <= tmp_19_5_7_reg_5794;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p1 <= tmp_19_3_7_reg_5469;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1023_p1 <= tmp_19_1_7_reg_5014;
else
grp_fu_1023_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1027_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_75_fu_2249_p1, tmp_155_fu_2353_p1, tmp_235_fu_2457_p1, tmp_315_fu_2561_p1, ap_enable_reg_pp0_iter3, tmp_20_1_8_reg_7164, tmp_20_3_8_reg_7294, ap_enable_reg_pp0_iter5, tmp_20_1_8_1_reg_7684, tmp_20_3_8_1_reg_7814, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1027_p0 <= tmp_20_3_8_1_reg_7814;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1027_p0 <= tmp_20_1_8_1_reg_7684;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1027_p0 <= tmp_20_3_8_reg_7294;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1027_p0 <= tmp_20_1_8_reg_7164;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p0 <= tmp_315_fu_2561_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p0 <= tmp_235_fu_2457_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p0 <= tmp_155_fu_2353_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p0 <= tmp_75_fu_2249_p1;
else
grp_fu_1027_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1027_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_8_reg_5019, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324, tmp_19_3_8_reg_5474, tmp_19_5_8_reg_5799, ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864, tmp_19_7_8_reg_6124, ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579, ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1027_p1 <= ap_reg_pp0_iter4_tmp_19_3_8_2_reg_6774;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1027_p1 <= ap_reg_pp0_iter4_tmp_19_1_8_2_reg_6579;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1027_p1 <= ap_reg_pp0_iter3_tmp_19_3_8_1_reg_5864;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1027_p1 <= ap_reg_pp0_iter3_tmp_19_1_8_1_reg_5324;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p1 <= tmp_19_7_8_reg_6124;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p1 <= tmp_19_5_8_reg_5799;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p1 <= tmp_19_3_8_reg_5474;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1027_p1 <= tmp_19_1_8_reg_5019;
else
grp_fu_1027_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1031_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_78_fu_2253_p1, tmp_158_fu_2357_p1, tmp_238_fu_2461_p1, tmp_318_fu_2565_p1, ap_enable_reg_pp0_iter3, tmp_20_1_9_reg_7169, tmp_20_3_9_reg_7299, ap_enable_reg_pp0_iter5, tmp_20_1_9_1_reg_7689, tmp_20_3_9_1_reg_7819, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1031_p0 <= tmp_20_3_9_1_reg_7819;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1031_p0 <= tmp_20_1_9_1_reg_7689;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1031_p0 <= tmp_20_3_9_reg_7299;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1031_p0 <= tmp_20_1_9_reg_7169;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p0 <= tmp_318_fu_2565_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p0 <= tmp_238_fu_2461_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p0 <= tmp_158_fu_2357_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p0 <= tmp_78_fu_2253_p1;
else
grp_fu_1031_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1031_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_9_reg_5024, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334, tmp_19_3_9_reg_5479, tmp_19_5_9_reg_5804, ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869, tmp_19_7_9_reg_6129, ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584, ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1031_p1 <= ap_reg_pp0_iter4_tmp_19_3_9_2_reg_6779;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1031_p1 <= ap_reg_pp0_iter4_tmp_19_1_9_2_reg_6584;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1031_p1 <= ap_reg_pp0_iter3_tmp_19_3_9_1_reg_5869;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1031_p1 <= ap_reg_pp0_iter3_tmp_19_1_9_1_reg_5334;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p1 <= tmp_19_7_9_reg_6129;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p1 <= tmp_19_5_9_reg_5804;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p1 <= tmp_19_3_9_reg_5479;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1031_p1 <= tmp_19_1_9_reg_5024;
else
grp_fu_1031_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1035_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_81_fu_2257_p1, tmp_161_fu_2361_p1, tmp_241_fu_2465_p1, tmp_321_fu_2569_p1, ap_enable_reg_pp0_iter3, tmp_20_1_s_reg_7174, tmp_20_3_s_reg_7304, ap_enable_reg_pp0_iter5, tmp_20_1_10_1_reg_7694, tmp_20_3_10_1_reg_7824, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1035_p0 <= tmp_20_3_10_1_reg_7824;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1035_p0 <= tmp_20_1_10_1_reg_7694;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1035_p0 <= tmp_20_3_s_reg_7304;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1035_p0 <= tmp_20_1_s_reg_7174;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p0 <= tmp_321_fu_2569_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p0 <= tmp_241_fu_2465_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p0 <= tmp_161_fu_2361_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p0 <= tmp_81_fu_2257_p1;
else
grp_fu_1035_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1035_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_s_reg_5029, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344, tmp_19_3_s_reg_5484, tmp_19_5_s_reg_5809, ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874, tmp_19_7_s_reg_6134, ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589, ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1035_p1 <= ap_reg_pp0_iter4_tmp_19_3_10_2_reg_6784;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1035_p1 <= ap_reg_pp0_iter4_tmp_19_1_10_2_reg_6589;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1035_p1 <= ap_reg_pp0_iter3_tmp_19_3_10_1_reg_5874;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1035_p1 <= ap_reg_pp0_iter3_tmp_19_1_10_1_reg_5344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p1 <= tmp_19_7_s_reg_6134;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p1 <= tmp_19_5_s_reg_5809;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p1 <= tmp_19_3_s_reg_5484;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1035_p1 <= tmp_19_1_s_reg_5029;
else
grp_fu_1035_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1039_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_84_fu_2261_p1, tmp_164_fu_2365_p1, tmp_244_fu_2469_p1, tmp_324_fu_2573_p1, ap_enable_reg_pp0_iter3, tmp_20_1_10_reg_7179, tmp_20_3_10_reg_7309, ap_enable_reg_pp0_iter5, tmp_20_1_11_1_reg_7699, tmp_20_3_11_1_reg_7829, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1039_p0 <= tmp_20_3_11_1_reg_7829;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1039_p0 <= tmp_20_1_11_1_reg_7699;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1039_p0 <= tmp_20_3_10_reg_7309;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1039_p0 <= tmp_20_1_10_reg_7179;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p0 <= tmp_324_fu_2573_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p0 <= tmp_244_fu_2469_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p0 <= tmp_164_fu_2365_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p0 <= tmp_84_fu_2261_p1;
else
grp_fu_1039_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1039_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_10_reg_5034, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354, tmp_19_3_10_reg_5489, tmp_19_5_10_reg_5814, ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879, tmp_19_7_10_reg_6139, ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594, ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1039_p1 <= ap_reg_pp0_iter4_tmp_19_3_11_2_reg_6789;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1039_p1 <= ap_reg_pp0_iter4_tmp_19_1_11_2_reg_6594;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1039_p1 <= ap_reg_pp0_iter3_tmp_19_3_11_1_reg_5879;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1039_p1 <= ap_reg_pp0_iter3_tmp_19_1_11_1_reg_5354;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p1 <= tmp_19_7_10_reg_6139;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p1 <= tmp_19_5_10_reg_5814;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p1 <= tmp_19_3_10_reg_5489;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1039_p1 <= tmp_19_1_10_reg_5034;
else
grp_fu_1039_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1043_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_87_fu_2265_p1, tmp_167_fu_2369_p1, tmp_247_fu_2473_p1, tmp_327_fu_2577_p1, ap_enable_reg_pp0_iter3, tmp_20_1_11_reg_7184, tmp_20_3_11_reg_7314, ap_enable_reg_pp0_iter5, tmp_20_1_12_1_reg_7704, tmp_20_3_12_1_reg_7834, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1043_p0 <= tmp_20_3_12_1_reg_7834;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1043_p0 <= tmp_20_1_12_1_reg_7704;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1043_p0 <= tmp_20_3_11_reg_7314;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1043_p0 <= tmp_20_1_11_reg_7184;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p0 <= tmp_327_fu_2577_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p0 <= tmp_247_fu_2473_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p0 <= tmp_167_fu_2369_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p0 <= tmp_87_fu_2265_p1;
else
grp_fu_1043_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1043_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_11_reg_5039, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364, tmp_19_3_11_reg_5494, tmp_19_5_11_reg_5819, ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884, tmp_19_7_11_reg_6144, ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599, ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1043_p1 <= ap_reg_pp0_iter4_tmp_19_3_12_2_reg_6794;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1043_p1 <= ap_reg_pp0_iter4_tmp_19_1_12_2_reg_6599;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1043_p1 <= ap_reg_pp0_iter3_tmp_19_3_12_1_reg_5884;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_1043_p1 <= ap_reg_pp0_iter3_tmp_19_1_12_1_reg_5364;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p1 <= tmp_19_7_11_reg_6144;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p1 <= tmp_19_5_11_reg_5819;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p1 <= tmp_19_3_11_reg_5494;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_1043_p1 <= tmp_19_1_11_reg_5039;
else
grp_fu_1043_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1047_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_reg_7319, tmp_20_5_reg_7384, tmp_20_6_reg_7449, ap_enable_reg_pp0_iter4, tmp_20_7_reg_7514, ap_enable_reg_pp0_iter5, tmp_20_4_0_1_reg_7839, tmp_20_5_0_1_reg_7904, tmp_20_6_0_1_reg_7969, tmp_20_7_0_1_reg_8034, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1047_p0 <= tmp_20_7_0_1_reg_8034;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1047_p0 <= tmp_20_6_0_1_reg_7969;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1047_p0 <= tmp_20_5_0_1_reg_7904;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1047_p0 <= tmp_20_4_0_1_reg_7839;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p0 <= tmp_20_7_reg_7514;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p0 <= tmp_20_6_reg_7449;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p0 <= tmp_20_5_reg_7384;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p0 <= tmp_20_4_reg_7319;
else
grp_fu_1047_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1047_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149, ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214, ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284, ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604, ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799, ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864, ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929, ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter5_tmp_19_7_0_2_reg_6994;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter5_tmp_19_6_0_2_reg_6929;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter5_tmp_19_5_0_2_reg_6864;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter5_tmp_19_4_0_2_reg_6799;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter3_tmp_19_7_0_1_reg_6604;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter3_tmp_19_6_0_1_reg_6284;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter3_tmp_19_5_0_1_reg_6214;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1047_p1 <= ap_reg_pp0_iter3_tmp_19_4_0_1_reg_6149;
else
grp_fu_1047_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1051_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_1_reg_7324, tmp_20_5_1_reg_7389, ap_enable_reg_pp0_iter4, tmp_20_6_1_reg_7454, tmp_20_7_1_reg_7519, ap_enable_reg_pp0_iter5, tmp_20_4_1_1_reg_7844, tmp_20_5_1_1_reg_7909, tmp_20_6_1_1_reg_7974, ap_enable_reg_pp0_iter6, tmp_20_7_1_1_reg_8039, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1051_p0 <= tmp_20_7_1_1_reg_8039;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1051_p0 <= tmp_20_6_1_1_reg_7974;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1051_p0 <= tmp_20_5_1_1_reg_7909;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1051_p0 <= tmp_20_4_1_1_reg_7844;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p0 <= tmp_20_7_1_reg_7519;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p0 <= tmp_20_6_1_reg_7454;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p0 <= tmp_20_5_1_reg_7389;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p0 <= tmp_20_4_1_reg_7324;
else
grp_fu_1051_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1051_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154, ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219, ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294, ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609, ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804, ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869, ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934, ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter5_tmp_19_7_1_2_reg_6999;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter5_tmp_19_6_1_2_reg_6934;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter5_tmp_19_5_1_2_reg_6869;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter5_tmp_19_4_1_2_reg_6804;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter3_tmp_19_7_1_1_reg_6609;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter3_tmp_19_6_1_1_reg_6294;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter3_tmp_19_5_1_1_reg_6219;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1051_p1 <= ap_reg_pp0_iter3_tmp_19_4_1_1_reg_6154;
else
grp_fu_1051_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1055_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_2_reg_7329, tmp_20_5_2_reg_7394, ap_enable_reg_pp0_iter4, tmp_20_6_2_reg_7459, tmp_20_7_2_reg_7524, ap_enable_reg_pp0_iter5, tmp_20_4_2_1_reg_7849, tmp_20_5_2_1_reg_7914, tmp_20_6_2_1_reg_7979, ap_enable_reg_pp0_iter6, tmp_20_7_2_1_reg_8044, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1055_p0 <= tmp_20_7_2_1_reg_8044;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1055_p0 <= tmp_20_6_2_1_reg_7979;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1055_p0 <= tmp_20_5_2_1_reg_7914;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1055_p0 <= tmp_20_4_2_1_reg_7849;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p0 <= tmp_20_7_2_reg_7524;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p0 <= tmp_20_6_2_reg_7459;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p0 <= tmp_20_5_2_reg_7394;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p0 <= tmp_20_4_2_reg_7329;
else
grp_fu_1055_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1055_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159, ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224, ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304, ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614, ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809, ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874, ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939, ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter5_tmp_19_7_2_2_reg_7004;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter5_tmp_19_6_2_2_reg_6939;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter5_tmp_19_5_2_2_reg_6874;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter5_tmp_19_4_2_2_reg_6809;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter3_tmp_19_7_2_1_reg_6614;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter3_tmp_19_6_2_1_reg_6304;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter3_tmp_19_5_2_1_reg_6224;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1055_p1 <= ap_reg_pp0_iter3_tmp_19_4_2_1_reg_6159;
else
grp_fu_1055_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1059_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_3_reg_7334, tmp_20_5_3_reg_7399, ap_enable_reg_pp0_iter4, tmp_20_6_3_reg_7464, tmp_20_7_3_reg_7529, ap_enable_reg_pp0_iter5, tmp_20_4_3_1_reg_7854, tmp_20_5_3_1_reg_7919, tmp_20_6_3_1_reg_7984, ap_enable_reg_pp0_iter6, tmp_20_7_3_1_reg_8049, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1059_p0 <= tmp_20_7_3_1_reg_8049;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1059_p0 <= tmp_20_6_3_1_reg_7984;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1059_p0 <= tmp_20_5_3_1_reg_7919;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1059_p0 <= tmp_20_4_3_1_reg_7854;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p0 <= tmp_20_7_3_reg_7529;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p0 <= tmp_20_6_3_reg_7464;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p0 <= tmp_20_5_3_reg_7399;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p0 <= tmp_20_4_3_reg_7334;
else
grp_fu_1059_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1059_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164, ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229, ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314, ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619, ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814, ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879, ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944, ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter5_tmp_19_7_3_2_reg_7009;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter5_tmp_19_6_3_2_reg_6944;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter5_tmp_19_5_3_2_reg_6879;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter5_tmp_19_4_3_2_reg_6814;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter3_tmp_19_7_3_1_reg_6619;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter3_tmp_19_6_3_1_reg_6314;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter3_tmp_19_5_3_1_reg_6229;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1059_p1 <= ap_reg_pp0_iter3_tmp_19_4_3_1_reg_6164;
else
grp_fu_1059_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1063_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_4_reg_7339, tmp_20_5_4_reg_7404, ap_enable_reg_pp0_iter4, tmp_20_6_4_reg_7469, tmp_20_7_4_reg_7534, ap_enable_reg_pp0_iter5, tmp_20_4_4_1_reg_7859, tmp_20_5_4_1_reg_7924, tmp_20_6_4_1_reg_7989, ap_enable_reg_pp0_iter6, tmp_20_7_4_1_reg_8054, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1063_p0 <= tmp_20_7_4_1_reg_8054;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1063_p0 <= tmp_20_6_4_1_reg_7989;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1063_p0 <= tmp_20_5_4_1_reg_7924;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1063_p0 <= tmp_20_4_4_1_reg_7859;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p0 <= tmp_20_7_4_reg_7534;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p0 <= tmp_20_6_4_reg_7469;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p0 <= tmp_20_5_4_reg_7404;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p0 <= tmp_20_4_4_reg_7339;
else
grp_fu_1063_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1063_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169, ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234, ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324, ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624, ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819, ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884, ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949, ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter5_tmp_19_7_4_2_reg_7014;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter5_tmp_19_6_4_2_reg_6949;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter5_tmp_19_5_4_2_reg_6884;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter5_tmp_19_4_4_2_reg_6819;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter3_tmp_19_7_4_1_reg_6624;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter3_tmp_19_6_4_1_reg_6324;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter3_tmp_19_5_4_1_reg_6234;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1063_p1 <= ap_reg_pp0_iter3_tmp_19_4_4_1_reg_6169;
else
grp_fu_1063_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1067_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_5_reg_7344, tmp_20_5_5_reg_7409, ap_enable_reg_pp0_iter4, tmp_20_6_5_reg_7474, tmp_20_7_5_reg_7539, ap_enable_reg_pp0_iter5, tmp_20_4_5_1_reg_7864, tmp_20_5_5_1_reg_7929, tmp_20_6_5_1_reg_7994, ap_enable_reg_pp0_iter6, tmp_20_7_5_1_reg_8059, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1067_p0 <= tmp_20_7_5_1_reg_8059;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1067_p0 <= tmp_20_6_5_1_reg_7994;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1067_p0 <= tmp_20_5_5_1_reg_7929;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1067_p0 <= tmp_20_4_5_1_reg_7864;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p0 <= tmp_20_7_5_reg_7539;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p0 <= tmp_20_6_5_reg_7474;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p0 <= tmp_20_5_5_reg_7409;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p0 <= tmp_20_4_5_reg_7344;
else
grp_fu_1067_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1067_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174, ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239, ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334, ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629, ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824, ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889, ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954, ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter5_tmp_19_7_5_2_reg_7019;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter5_tmp_19_6_5_2_reg_6954;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter5_tmp_19_5_5_2_reg_6889;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter5_tmp_19_4_5_2_reg_6824;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter3_tmp_19_7_5_1_reg_6629;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter3_tmp_19_6_5_1_reg_6334;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter3_tmp_19_5_5_1_reg_6239;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1067_p1 <= ap_reg_pp0_iter3_tmp_19_4_5_1_reg_6174;
else
grp_fu_1067_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1071_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_6_reg_7349, tmp_20_5_6_reg_7414, ap_enable_reg_pp0_iter4, tmp_20_6_6_reg_7479, tmp_20_7_6_reg_7544, ap_enable_reg_pp0_iter5, tmp_20_4_6_1_reg_7869, tmp_20_5_6_1_reg_7934, tmp_20_6_6_1_reg_7999, ap_enable_reg_pp0_iter6, tmp_20_7_6_1_reg_8064, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1071_p0 <= tmp_20_7_6_1_reg_8064;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1071_p0 <= tmp_20_6_6_1_reg_7999;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1071_p0 <= tmp_20_5_6_1_reg_7934;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1071_p0 <= tmp_20_4_6_1_reg_7869;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p0 <= tmp_20_7_6_reg_7544;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p0 <= tmp_20_6_6_reg_7479;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p0 <= tmp_20_5_6_reg_7414;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p0 <= tmp_20_4_6_reg_7349;
else
grp_fu_1071_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1071_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179, ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244, ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344, ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634, ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829, ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894, ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959, ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter5_tmp_19_7_6_2_reg_7024;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter5_tmp_19_6_6_2_reg_6959;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter5_tmp_19_5_6_2_reg_6894;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter5_tmp_19_4_6_2_reg_6829;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter3_tmp_19_7_6_1_reg_6634;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter3_tmp_19_6_6_1_reg_6344;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter3_tmp_19_5_6_1_reg_6244;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1071_p1 <= ap_reg_pp0_iter3_tmp_19_4_6_1_reg_6179;
else
grp_fu_1071_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1075_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_7_reg_7354, tmp_20_5_7_reg_7419, ap_enable_reg_pp0_iter4, tmp_20_6_7_reg_7484, tmp_20_7_7_reg_7549, ap_enable_reg_pp0_iter5, tmp_20_4_7_1_reg_7874, tmp_20_5_7_1_reg_7939, tmp_20_6_7_1_reg_8004, ap_enable_reg_pp0_iter6, tmp_20_7_7_1_reg_8069, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1075_p0 <= tmp_20_7_7_1_reg_8069;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1075_p0 <= tmp_20_6_7_1_reg_8004;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1075_p0 <= tmp_20_5_7_1_reg_7939;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1075_p0 <= tmp_20_4_7_1_reg_7874;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p0 <= tmp_20_7_7_reg_7549;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p0 <= tmp_20_6_7_reg_7484;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p0 <= tmp_20_5_7_reg_7419;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p0 <= tmp_20_4_7_reg_7354;
else
grp_fu_1075_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1075_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184, ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249, ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354, ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639, ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834, ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899, ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964, ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter5_tmp_19_7_7_2_reg_7029;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter5_tmp_19_6_7_2_reg_6964;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter5_tmp_19_5_7_2_reg_6899;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter5_tmp_19_4_7_2_reg_6834;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter3_tmp_19_7_7_1_reg_6639;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter3_tmp_19_6_7_1_reg_6354;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter3_tmp_19_5_7_1_reg_6249;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1075_p1 <= ap_reg_pp0_iter3_tmp_19_4_7_1_reg_6184;
else
grp_fu_1075_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1079_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_8_reg_7359, tmp_20_5_8_reg_7424, ap_enable_reg_pp0_iter4, tmp_20_6_8_reg_7489, tmp_20_7_8_reg_7554, ap_enable_reg_pp0_iter5, tmp_20_4_8_1_reg_7879, tmp_20_5_8_1_reg_7944, tmp_20_6_8_1_reg_8009, ap_enable_reg_pp0_iter6, tmp_20_7_8_1_reg_8074, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1079_p0 <= tmp_20_7_8_1_reg_8074;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1079_p0 <= tmp_20_6_8_1_reg_8009;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1079_p0 <= tmp_20_5_8_1_reg_7944;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1079_p0 <= tmp_20_4_8_1_reg_7879;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p0 <= tmp_20_7_8_reg_7554;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p0 <= tmp_20_6_8_reg_7489;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p0 <= tmp_20_5_8_reg_7424;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p0 <= tmp_20_4_8_reg_7359;
else
grp_fu_1079_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1079_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189, ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254, ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364, ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644, ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839, ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904, ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969, ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter5_tmp_19_7_8_2_reg_7034;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter5_tmp_19_6_8_2_reg_6969;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter5_tmp_19_5_8_2_reg_6904;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter5_tmp_19_4_8_2_reg_6839;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter3_tmp_19_7_8_1_reg_6644;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter3_tmp_19_6_8_1_reg_6364;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter3_tmp_19_5_8_1_reg_6254;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1079_p1 <= ap_reg_pp0_iter3_tmp_19_4_8_1_reg_6189;
else
grp_fu_1079_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1083_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_9_reg_7364, tmp_20_5_9_reg_7429, ap_enable_reg_pp0_iter4, tmp_20_6_9_reg_7494, tmp_20_7_9_reg_7559, ap_enable_reg_pp0_iter5, tmp_20_4_9_1_reg_7884, tmp_20_5_9_1_reg_7949, tmp_20_6_9_1_reg_8014, ap_enable_reg_pp0_iter6, tmp_20_7_9_1_reg_8079, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1083_p0 <= tmp_20_7_9_1_reg_8079;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1083_p0 <= tmp_20_6_9_1_reg_8014;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1083_p0 <= tmp_20_5_9_1_reg_7949;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1083_p0 <= tmp_20_4_9_1_reg_7884;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p0 <= tmp_20_7_9_reg_7559;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p0 <= tmp_20_6_9_reg_7494;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p0 <= tmp_20_5_9_reg_7429;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p0 <= tmp_20_4_9_reg_7364;
else
grp_fu_1083_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1083_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194, ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259, ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374, ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649, ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844, ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909, ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974, ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter5_tmp_19_7_9_2_reg_7039;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter5_tmp_19_6_9_2_reg_6974;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter5_tmp_19_5_9_2_reg_6909;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter5_tmp_19_4_9_2_reg_6844;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter3_tmp_19_7_9_1_reg_6649;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter3_tmp_19_6_9_1_reg_6374;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter3_tmp_19_5_9_1_reg_6259;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1083_p1 <= ap_reg_pp0_iter3_tmp_19_4_9_1_reg_6194;
else
grp_fu_1083_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1087_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_s_reg_7369, tmp_20_5_s_reg_7434, ap_enable_reg_pp0_iter4, tmp_20_6_s_reg_7499, tmp_20_7_s_reg_7564, ap_enable_reg_pp0_iter5, tmp_20_4_10_1_reg_7889, tmp_20_5_10_1_reg_7954, tmp_20_6_10_1_reg_8019, ap_enable_reg_pp0_iter6, tmp_20_7_10_1_reg_8084, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1087_p0 <= tmp_20_7_10_1_reg_8084;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1087_p0 <= tmp_20_6_10_1_reg_8019;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1087_p0 <= tmp_20_5_10_1_reg_7954;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1087_p0 <= tmp_20_4_10_1_reg_7889;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p0 <= tmp_20_7_s_reg_7564;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p0 <= tmp_20_6_s_reg_7499;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p0 <= tmp_20_5_s_reg_7434;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p0 <= tmp_20_4_s_reg_7369;
else
grp_fu_1087_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1087_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199, ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264, ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384, ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654, ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849, ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914, ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979, ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter5_tmp_19_7_10_2_reg_7044;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter5_tmp_19_6_10_2_reg_6979;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter5_tmp_19_5_10_2_reg_6914;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter5_tmp_19_4_10_2_reg_6849;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter3_tmp_19_7_10_1_reg_6654;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter3_tmp_19_6_10_1_reg_6384;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter3_tmp_19_5_10_1_reg_6264;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1087_p1 <= ap_reg_pp0_iter3_tmp_19_4_10_1_reg_6199;
else
grp_fu_1087_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1091_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_10_reg_7374, tmp_20_5_10_reg_7439, ap_enable_reg_pp0_iter4, tmp_20_6_10_reg_7504, tmp_20_7_10_reg_7569, ap_enable_reg_pp0_iter5, tmp_20_4_11_1_reg_7894, tmp_20_5_11_1_reg_7959, tmp_20_6_11_1_reg_8024, ap_enable_reg_pp0_iter6, tmp_20_7_11_1_reg_8089, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1091_p0 <= tmp_20_7_11_1_reg_8089;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1091_p0 <= tmp_20_6_11_1_reg_8024;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1091_p0 <= tmp_20_5_11_1_reg_7959;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1091_p0 <= tmp_20_4_11_1_reg_7894;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p0 <= tmp_20_7_10_reg_7569;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p0 <= tmp_20_6_10_reg_7504;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p0 <= tmp_20_5_10_reg_7439;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p0 <= tmp_20_4_10_reg_7374;
else
grp_fu_1091_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1091_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204, ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269, ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394, ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659, ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854, ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919, ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984, ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter5_tmp_19_7_11_2_reg_7049;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter5_tmp_19_6_11_2_reg_6984;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter5_tmp_19_5_11_2_reg_6919;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter5_tmp_19_4_11_2_reg_6854;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter3_tmp_19_7_11_1_reg_6659;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter3_tmp_19_6_11_1_reg_6394;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter3_tmp_19_5_11_1_reg_6269;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1091_p1 <= ap_reg_pp0_iter3_tmp_19_4_11_1_reg_6204;
else
grp_fu_1091_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1095_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_4_11_reg_7379, tmp_20_5_11_reg_7444, ap_enable_reg_pp0_iter4, tmp_20_6_11_reg_7509, tmp_20_7_11_reg_7574, ap_enable_reg_pp0_iter5, tmp_20_4_12_1_reg_7899, tmp_20_5_12_1_reg_7964, tmp_20_6_12_1_reg_8029, ap_enable_reg_pp0_iter6, tmp_20_7_12_1_reg_8094, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1095_p0 <= tmp_20_7_12_1_reg_8094;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1095_p0 <= tmp_20_6_12_1_reg_8029;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1095_p0 <= tmp_20_5_12_1_reg_7964;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1095_p0 <= tmp_20_4_12_1_reg_7899;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p0 <= tmp_20_7_11_reg_7574;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p0 <= tmp_20_6_11_reg_7509;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p0 <= tmp_20_5_11_reg_7444;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p0 <= tmp_20_4_11_reg_7379;
else
grp_fu_1095_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1095_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209, ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274, ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404, ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664, ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859, ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924, ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989, ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054, ap_enable_reg_pp0_iter4, ap_enable_reg_pp0_iter5, ap_enable_reg_pp0_iter6, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter5_tmp_19_7_12_2_reg_7054;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter6))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter5_tmp_19_6_12_2_reg_6989;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter5_tmp_19_5_12_2_reg_6924;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter5_tmp_19_4_12_2_reg_6859;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter3_tmp_19_7_12_1_reg_6664;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter3_tmp_19_6_12_1_reg_6404;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter3_tmp_19_5_12_1_reg_6274;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter4))) then
grp_fu_1095_p1 <= ap_reg_pp0_iter3_tmp_19_4_12_1_reg_6209;
else
grp_fu_1095_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1099_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_0_load_reg_3686, bufw_0_load_1_reg_3710, bufw_0_load_2_reg_4012, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1099_p0 <= bufw_0_load_2_reg_4012;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1099_p0 <= bufw_0_load_1_reg_3710;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1099_p0 <= bufw_0_load_reg_3686;
else
grp_fu_1099_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1099_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1099_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1099_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1099_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1099_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1099_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1099_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1099_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1099_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1099_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1099_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1103_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_0_load_1_reg_3710, bufw_1_load_1_reg_3759, ap_enable_reg_pp0_iter1, bufw_1_load_2_reg_4019, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1103_p0 <= bufw_1_load_2_reg_4019;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1103_p0 <= bufw_1_load_1_reg_3759;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1103_p0 <= bufw_0_load_1_reg_3710;
else
grp_fu_1103_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1103_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1103_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1103_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1103_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1103_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1103_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1103_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1103_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1103_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1103_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1103_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1107_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_1_load_reg_3752, bufw_2_load_1_reg_3774, ap_enable_reg_pp0_iter1, bufw_2_load_2_reg_4026, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1107_p0 <= bufw_2_load_2_reg_4026;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1107_p0 <= bufw_2_load_1_reg_3774;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1107_p0 <= bufw_1_load_reg_3752;
else
grp_fu_1107_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1107_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1107_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1107_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1107_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1107_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1107_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1107_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1107_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1107_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1107_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1107_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1111_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_1_load_1_reg_3759, bufw_3_load_1_reg_3789, ap_enable_reg_pp0_iter1, bufw_3_load_2_reg_4033, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1111_p0 <= bufw_3_load_2_reg_4033;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1111_p0 <= bufw_3_load_1_reg_3789;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1111_p0 <= bufw_1_load_1_reg_3759;
else
grp_fu_1111_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1111_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1111_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1111_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1111_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1111_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1111_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1111_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1111_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1111_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1111_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1111_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1115_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_2_load_reg_3767, bufw_4_load_1_reg_3804, ap_enable_reg_pp0_iter1, bufw_4_load_2_reg_4040, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1115_p0 <= bufw_4_load_2_reg_4040;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1115_p0 <= bufw_4_load_1_reg_3804;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1115_p0 <= bufw_2_load_reg_3767;
else
grp_fu_1115_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1115_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1115_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1115_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1115_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1115_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1115_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1115_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1115_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1115_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1115_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1115_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1119_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_2_load_1_reg_3774, bufw_5_load_1_reg_3819, ap_enable_reg_pp0_iter1, bufw_5_load_2_reg_4047, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1119_p0 <= bufw_5_load_2_reg_4047;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1119_p0 <= bufw_5_load_1_reg_3819;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1119_p0 <= bufw_2_load_1_reg_3774;
else
grp_fu_1119_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1119_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1119_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1119_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1119_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1119_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1119_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1119_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1119_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1119_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1119_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1119_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1123_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_3_load_reg_3782, bufw_6_load_1_reg_3834, ap_enable_reg_pp0_iter1, bufw_6_load_2_reg_4054, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1123_p0 <= bufw_6_load_2_reg_4054;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1123_p0 <= bufw_6_load_1_reg_3834;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1123_p0 <= bufw_3_load_reg_3782;
else
grp_fu_1123_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1123_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1123_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1123_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1123_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1123_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1123_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1123_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1123_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1123_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1123_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1123_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1127_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_3_load_1_reg_3789, bufw_7_load_1_reg_3849, ap_enable_reg_pp0_iter1, bufw_7_load_2_reg_4061, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1127_p0 <= bufw_7_load_2_reg_4061;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1127_p0 <= bufw_7_load_1_reg_3849;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1127_p0 <= bufw_3_load_1_reg_3789;
else
grp_fu_1127_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1127_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1127_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1127_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1127_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1127_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1127_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1127_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1127_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1127_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1127_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1127_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1131_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_4_load_reg_3797, bufw_8_load_1_reg_3864, ap_enable_reg_pp0_iter1, bufw_8_load_2_reg_4068, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1131_p0 <= bufw_8_load_2_reg_4068;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1131_p0 <= bufw_8_load_1_reg_3864;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1131_p0 <= bufw_4_load_reg_3797;
else
grp_fu_1131_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1131_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1131_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1131_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1131_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1131_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1131_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1131_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1131_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1131_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1131_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1131_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1135_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_4_load_1_reg_3804, bufw_9_load_1_reg_3879, ap_enable_reg_pp0_iter1, bufw_9_load_2_reg_4075, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1135_p0 <= bufw_9_load_2_reg_4075;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1135_p0 <= bufw_9_load_1_reg_3879;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1135_p0 <= bufw_4_load_1_reg_3804;
else
grp_fu_1135_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1135_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1135_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1135_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1135_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1135_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1135_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1135_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1135_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1135_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1135_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1135_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1139_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_5_load_reg_3812, bufw_10_load_1_reg_3894, ap_enable_reg_pp0_iter1, bufw_10_load_2_reg_4082, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1139_p0 <= bufw_10_load_2_reg_4082;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1139_p0 <= bufw_10_load_1_reg_3894;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1139_p0 <= bufw_5_load_reg_3812;
else
grp_fu_1139_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1139_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1139_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1139_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1139_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1139_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1139_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1139_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1139_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1139_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1139_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1139_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1143_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_5_load_1_reg_3819, bufw_11_load_1_reg_3909, ap_enable_reg_pp0_iter1, bufw_11_load_2_reg_4089, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1143_p0 <= bufw_11_load_2_reg_4089;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1143_p0 <= bufw_11_load_1_reg_3909;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1143_p0 <= bufw_5_load_1_reg_3819;
else
grp_fu_1143_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1143_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1143_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1143_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1143_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1143_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1143_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1143_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1143_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1143_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1143_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1143_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1147_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_6_load_reg_3827, bufw_12_load_1_reg_3924, ap_enable_reg_pp0_iter1, bufw_12_load_2_reg_4096, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1147_p0 <= bufw_12_load_2_reg_4096;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1147_p0 <= bufw_12_load_1_reg_3924;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1147_p0 <= bufw_6_load_reg_3827;
else
grp_fu_1147_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1147_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_reg_3735, bufi_1_load_1_reg_3948, ap_enable_reg_pp0_iter1, bufi_1_load_2_reg_4120, bufi_2_load_2_reg_4137, bufi_1_load_3_reg_4171, bufi_1_load_4_reg_4222, bufi_2_load_5_reg_4290, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1147_p1 <= bufi_2_load_5_reg_4290;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1147_p1 <= bufi_2_load_2_reg_4137;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1147_p1 <= bufi_2_load_reg_3735;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1147_p1 <= bufi_1_load_4_reg_4222;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1147_p1 <= bufi_1_load_3_reg_4171;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1147_p1 <= bufi_1_load_2_reg_4120;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1147_p1 <= bufi_1_load_1_reg_3948;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1147_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1147_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1147_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1151_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_0_load_reg_3686, bufw_0_load_1_reg_3710, bufw_6_load_1_reg_3834, bufw_0_load_2_reg_4012, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1151_p0 <= bufw_0_load_2_reg_4012;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1151_p0 <= bufw_0_load_1_reg_3710;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1151_p0 <= bufw_0_load_reg_3686;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1151_p0 <= bufw_6_load_1_reg_3834;
else
grp_fu_1151_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1151_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1151_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1151_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1151_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1151_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1151_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1151_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1151_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1151_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1151_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1151_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1155_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_1_load_reg_3752, bufw_1_load_1_reg_3759, bufw_7_load_reg_3842, ap_enable_reg_pp0_iter1, bufw_1_load_2_reg_4019, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1155_p0 <= bufw_1_load_2_reg_4019;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1155_p0 <= bufw_1_load_1_reg_3759;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1155_p0 <= bufw_1_load_reg_3752;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1155_p0 <= bufw_7_load_reg_3842;
else
grp_fu_1155_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1155_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1155_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1155_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1155_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1155_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1155_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1155_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1155_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1155_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1155_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1155_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1159_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_2_load_reg_3767, bufw_2_load_1_reg_3774, bufw_7_load_1_reg_3849, ap_enable_reg_pp0_iter1, bufw_2_load_2_reg_4026, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1159_p0 <= bufw_2_load_2_reg_4026;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1159_p0 <= bufw_2_load_1_reg_3774;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1159_p0 <= bufw_2_load_reg_3767;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1159_p0 <= bufw_7_load_1_reg_3849;
else
grp_fu_1159_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1159_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1159_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1159_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1159_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1159_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1159_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1159_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1159_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1159_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1159_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1159_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1163_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_3_load_reg_3782, bufw_3_load_1_reg_3789, bufw_8_load_reg_3857, ap_enable_reg_pp0_iter1, bufw_3_load_2_reg_4033, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1163_p0 <= bufw_3_load_2_reg_4033;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1163_p0 <= bufw_3_load_1_reg_3789;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1163_p0 <= bufw_3_load_reg_3782;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1163_p0 <= bufw_8_load_reg_3857;
else
grp_fu_1163_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1163_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1163_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1163_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1163_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1163_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1163_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1163_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1163_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1163_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1163_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1163_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1167_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_4_load_reg_3797, bufw_4_load_1_reg_3804, bufw_8_load_1_reg_3864, ap_enable_reg_pp0_iter1, bufw_4_load_2_reg_4040, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1167_p0 <= bufw_4_load_2_reg_4040;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1167_p0 <= bufw_4_load_1_reg_3804;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1167_p0 <= bufw_4_load_reg_3797;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1167_p0 <= bufw_8_load_1_reg_3864;
else
grp_fu_1167_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1167_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1167_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1167_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1167_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1167_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1167_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1167_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1167_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1167_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1167_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1167_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1171_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_5_load_reg_3812, bufw_5_load_1_reg_3819, bufw_9_load_reg_3872, ap_enable_reg_pp0_iter1, bufw_5_load_2_reg_4047, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1171_p0 <= bufw_5_load_2_reg_4047;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1171_p0 <= bufw_5_load_1_reg_3819;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1171_p0 <= bufw_5_load_reg_3812;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1171_p0 <= bufw_9_load_reg_3872;
else
grp_fu_1171_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1171_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1171_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1171_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1171_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1171_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1171_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1171_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1171_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1171_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1171_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1171_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1175_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_6_load_reg_3827, bufw_6_load_1_reg_3834, bufw_9_load_1_reg_3879, ap_enable_reg_pp0_iter1, bufw_6_load_2_reg_4054, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1175_p0 <= bufw_6_load_2_reg_4054;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1175_p0 <= bufw_6_load_1_reg_3834;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1175_p0 <= bufw_6_load_reg_3827;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1175_p0 <= bufw_9_load_1_reg_3879;
else
grp_fu_1175_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1175_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1175_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1175_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1175_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1175_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1175_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1175_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1175_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1175_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1175_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1175_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1179_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_7_load_reg_3842, bufw_7_load_1_reg_3849, bufw_10_load_reg_3887, ap_enable_reg_pp0_iter1, bufw_7_load_2_reg_4061, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1179_p0 <= bufw_7_load_2_reg_4061;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1179_p0 <= bufw_7_load_1_reg_3849;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1179_p0 <= bufw_7_load_reg_3842;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1179_p0 <= bufw_10_load_reg_3887;
else
grp_fu_1179_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1179_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1179_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1179_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1179_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1179_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1179_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1179_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1179_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1179_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1179_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1179_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1183_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_8_load_reg_3857, bufw_8_load_1_reg_3864, bufw_10_load_1_reg_3894, ap_enable_reg_pp0_iter1, bufw_8_load_2_reg_4068, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1183_p0 <= bufw_8_load_2_reg_4068;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1183_p0 <= bufw_8_load_1_reg_3864;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1183_p0 <= bufw_8_load_reg_3857;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1183_p0 <= bufw_10_load_1_reg_3894;
else
grp_fu_1183_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1183_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1183_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1183_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1183_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1183_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1183_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1183_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1183_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1183_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1183_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1183_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1187_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_9_load_reg_3872, bufw_9_load_1_reg_3879, bufw_11_load_reg_3902, ap_enable_reg_pp0_iter1, bufw_9_load_2_reg_4075, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1187_p0 <= bufw_9_load_2_reg_4075;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1187_p0 <= bufw_9_load_1_reg_3879;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1187_p0 <= bufw_9_load_reg_3872;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1187_p0 <= bufw_11_load_reg_3902;
else
grp_fu_1187_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1187_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1187_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1187_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1187_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1187_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1187_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1187_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1187_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1187_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1187_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1187_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1191_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_10_load_reg_3887, bufw_10_load_1_reg_3894, bufw_11_load_1_reg_3909, ap_enable_reg_pp0_iter1, bufw_10_load_2_reg_4082, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1191_p0 <= bufw_10_load_2_reg_4082;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1191_p0 <= bufw_10_load_1_reg_3894;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1191_p0 <= bufw_10_load_reg_3887;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1191_p0 <= bufw_11_load_1_reg_3909;
else
grp_fu_1191_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1191_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1191_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1191_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1191_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1191_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1191_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1191_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1191_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1191_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1191_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1191_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1195_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_11_load_reg_3902, bufw_11_load_1_reg_3909, bufw_12_load_reg_3917, ap_enable_reg_pp0_iter1, bufw_11_load_2_reg_4089, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1195_p0 <= bufw_11_load_2_reg_4089;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1195_p0 <= bufw_11_load_1_reg_3909;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1195_p0 <= bufw_11_load_reg_3902;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1195_p0 <= bufw_12_load_reg_3917;
else
grp_fu_1195_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1195_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_reg_3693, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1195_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1195_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1195_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1195_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1195_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1195_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1195_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1195_p1 <= bufi_0_load_reg_3693;
else
grp_fu_1195_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1195_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1199_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_12_load_reg_3917, bufw_12_load_1_reg_3924, ap_enable_reg_pp0_iter1, bufw_12_load_2_reg_4096, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)) or ((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)))) then
grp_fu_1199_p0 <= bufw_12_load_2_reg_4096;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)))) then
grp_fu_1199_p0 <= bufw_12_load_reg_3917;
elsif ((((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1199_p0 <= bufw_12_load_1_reg_3924;
else
grp_fu_1199_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1199_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_1_load_reg_3718, bufi_2_load_1_reg_3965, ap_enable_reg_pp0_iter1, bufi_0_load_2_reg_4103, bufi_2_load_3_reg_4188, bufi_0_load_4_reg_4205, bufi_1_load_5_reg_4273, bufi_0_load_6_reg_4327, bufi_2_load_6_reg_4361, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1199_p1 <= bufi_2_load_6_reg_4361;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1199_p1 <= bufi_2_load_3_reg_4188;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1199_p1 <= bufi_2_load_1_reg_3965;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1199_p1 <= bufi_1_load_5_reg_4273;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1199_p1 <= bufi_0_load_6_reg_4327;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1199_p1 <= bufi_0_load_4_reg_4205;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1199_p1 <= bufi_0_load_2_reg_4103;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1199_p1 <= bufi_1_load_reg_3718;
else
grp_fu_1199_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1199_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1203_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_0_load_reg_3686, bufw_0_load_1_reg_3710, bufw_0_load_2_reg_4012, ap_enable_reg_pp0_iter1, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1203_p0 <= bufw_0_load_2_reg_4012;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1203_p0 <= bufw_0_load_1_reg_3710;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1203_p0 <= bufw_0_load_reg_3686;
else
grp_fu_1203_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1203_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1203_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1203_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1203_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1203_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1203_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1203_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1203_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1203_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1203_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1203_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1207_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_1_load_reg_3752, bufw_1_load_1_reg_3759, ap_enable_reg_pp0_iter1, bufw_1_load_2_reg_4019, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1207_p0 <= bufw_1_load_2_reg_4019;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1207_p0 <= bufw_1_load_1_reg_3759;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1207_p0 <= bufw_1_load_reg_3752;
else
grp_fu_1207_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1207_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1207_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1207_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1207_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1207_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1207_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1207_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1207_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1207_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1207_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1207_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1211_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_2_load_reg_3767, bufw_2_load_1_reg_3774, ap_enable_reg_pp0_iter1, bufw_2_load_2_reg_4026, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1211_p0 <= bufw_2_load_2_reg_4026;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1211_p0 <= bufw_2_load_1_reg_3774;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1211_p0 <= bufw_2_load_reg_3767;
else
grp_fu_1211_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1211_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1211_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1211_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1211_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1211_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1211_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1211_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1211_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1211_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1211_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1211_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1215_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_3_load_reg_3782, bufw_3_load_1_reg_3789, ap_enable_reg_pp0_iter1, bufw_3_load_2_reg_4033, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1215_p0 <= bufw_3_load_2_reg_4033;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1215_p0 <= bufw_3_load_1_reg_3789;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1215_p0 <= bufw_3_load_reg_3782;
else
grp_fu_1215_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1215_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1215_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1215_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1215_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1215_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1215_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1215_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1215_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1215_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1215_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1215_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1219_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_4_load_reg_3797, bufw_4_load_1_reg_3804, ap_enable_reg_pp0_iter1, bufw_4_load_2_reg_4040, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1219_p0 <= bufw_4_load_2_reg_4040;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1219_p0 <= bufw_4_load_1_reg_3804;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1219_p0 <= bufw_4_load_reg_3797;
else
grp_fu_1219_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1219_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1219_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1219_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1219_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1219_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1219_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1219_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1219_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1219_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1219_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1219_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1223_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_5_load_reg_3812, bufw_5_load_1_reg_3819, ap_enable_reg_pp0_iter1, bufw_5_load_2_reg_4047, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1223_p0 <= bufw_5_load_2_reg_4047;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1223_p0 <= bufw_5_load_1_reg_3819;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1223_p0 <= bufw_5_load_reg_3812;
else
grp_fu_1223_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1223_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1223_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1223_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1223_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1223_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1223_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1223_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1223_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1223_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1223_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1223_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1227_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_6_load_reg_3827, bufw_6_load_1_reg_3834, ap_enable_reg_pp0_iter1, bufw_6_load_2_reg_4054, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1227_p0 <= bufw_6_load_2_reg_4054;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1227_p0 <= bufw_6_load_1_reg_3834;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1227_p0 <= bufw_6_load_reg_3827;
else
grp_fu_1227_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1227_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1227_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1227_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1227_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1227_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1227_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1227_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1227_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1227_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1227_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1227_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1231_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_7_load_reg_3842, bufw_7_load_1_reg_3849, ap_enable_reg_pp0_iter1, bufw_7_load_2_reg_4061, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1231_p0 <= bufw_7_load_2_reg_4061;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1231_p0 <= bufw_7_load_1_reg_3849;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1231_p0 <= bufw_7_load_reg_3842;
else
grp_fu_1231_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1231_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1231_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1231_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1231_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1231_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1231_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1231_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1231_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1231_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1231_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1231_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1235_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_8_load_reg_3857, bufw_8_load_1_reg_3864, ap_enable_reg_pp0_iter1, bufw_8_load_2_reg_4068, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1235_p0 <= bufw_8_load_2_reg_4068;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1235_p0 <= bufw_8_load_1_reg_3864;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1235_p0 <= bufw_8_load_reg_3857;
else
grp_fu_1235_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1235_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1235_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1235_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1235_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1235_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1235_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1235_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1235_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1235_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1235_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1235_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1239_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_9_load_reg_3872, bufw_9_load_1_reg_3879, ap_enable_reg_pp0_iter1, bufw_9_load_2_reg_4075, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1239_p0 <= bufw_9_load_2_reg_4075;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1239_p0 <= bufw_9_load_1_reg_3879;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1239_p0 <= bufw_9_load_reg_3872;
else
grp_fu_1239_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1239_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1239_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1239_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1239_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1239_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1239_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1239_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1239_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1239_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1239_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1239_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1243_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_10_load_reg_3887, bufw_10_load_1_reg_3894, ap_enable_reg_pp0_iter1, bufw_10_load_2_reg_4082, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1243_p0 <= bufw_10_load_2_reg_4082;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1243_p0 <= bufw_10_load_1_reg_3894;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1243_p0 <= bufw_10_load_reg_3887;
else
grp_fu_1243_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1243_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1243_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1243_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1243_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1243_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1243_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1243_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1243_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1243_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1243_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1243_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1247_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_11_load_reg_3902, bufw_11_load_1_reg_3909, ap_enable_reg_pp0_iter1, bufw_11_load_2_reg_4089, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1247_p0 <= bufw_11_load_2_reg_4089;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1247_p0 <= bufw_11_load_1_reg_3909;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1247_p0 <= bufw_11_load_reg_3902;
else
grp_fu_1247_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1247_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1247_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1247_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1247_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1247_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1247_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1247_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1247_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1247_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1247_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1247_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1251_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufw_12_load_reg_3917, bufw_12_load_1_reg_3924, ap_enable_reg_pp0_iter1, bufw_12_load_2_reg_4096, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7)) or ((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6)))) then
grp_fu_1251_p0 <= bufw_12_load_2_reg_4096;
elsif ((((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5)) or ((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4)))) then
grp_fu_1251_p0 <= bufw_12_load_1_reg_3924;
elsif ((((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3)) or ((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2)) or ((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1)) or ((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0)))) then
grp_fu_1251_p0 <= bufw_12_load_reg_3917;
else
grp_fu_1251_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1251_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, bufi_0_load_1_reg_3931, ap_enable_reg_pp0_iter1, bufi_0_load_3_reg_4154, bufi_2_load_4_reg_4239, bufi_0_load_5_reg_4256, bufi_1_load_6_reg_4344, bufi_0_load_7_reg_4378, bufi_1_load_7_reg_4395, bufi_2_load_7_reg_4412, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter1)) then
if (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7))) then
grp_fu_1251_p1 <= bufi_2_load_7_reg_4412;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6))) then
grp_fu_1251_p1 <= bufi_2_load_4_reg_4239;
elsif (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5))) then
grp_fu_1251_p1 <= bufi_1_load_7_reg_4395;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4))) then
grp_fu_1251_p1 <= bufi_1_load_6_reg_4344;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3))) then
grp_fu_1251_p1 <= bufi_0_load_7_reg_4378;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2))) then
grp_fu_1251_p1 <= bufi_0_load_5_reg_4256;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1))) then
grp_fu_1251_p1 <= bufi_0_load_3_reg_4154;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0))) then
grp_fu_1251_p1 <= bufi_0_load_1_reg_3931;
else
grp_fu_1251_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
else
grp_fu_1251_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_1255_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1265_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1275_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1285_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1295_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1305_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1315_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1325_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1335_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1345_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1355_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1365_p1 <= bufo_Dout_A(416 - 1 downto 0);
grp_fu_1375_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1385_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1395_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1405_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1415_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1425_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1435_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1445_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1455_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1465_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1475_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_1485_p1 <= bufo_Dout_B(416 - 1 downto 0);
grp_fu_943_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_11_fu_2165_p1, ap_enable_reg_pp0_iter2, tmp_91_fu_2269_p1, tmp_171_fu_2373_p1, tmp_251_fu_2477_p1, tmp_351_reg_7059, ap_enable_reg_pp0_iter3, tmp_20_2_reg_7189, tmp_20_0_0_1_reg_7579, ap_enable_reg_pp0_iter5, tmp_20_2_0_1_reg_7709, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_943_p0 <= tmp_20_2_0_1_reg_7709;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_943_p0 <= tmp_20_0_0_1_reg_7579;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_943_p0 <= tmp_20_2_reg_7189;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_943_p0 <= tmp_351_reg_7059;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p0 <= tmp_251_fu_2477_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p0 <= tmp_171_fu_2373_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p0 <= tmp_91_fu_2269_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p0 <= tmp_11_fu_2165_p1;
else
grp_fu_943_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_943_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_349_reg_4849, ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854, ap_enable_reg_pp0_iter2, tmp_19_2_reg_5369, ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504, tmp_19_4_reg_5694, tmp_19_6_reg_6019, ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474, ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_943_p1 <= ap_reg_pp0_iter4_tmp_19_2_0_2_reg_6669;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_943_p1 <= ap_reg_pp0_iter4_tmp_19_0_0_2_reg_6474;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_943_p1 <= ap_reg_pp0_iter3_tmp_19_2_0_1_reg_5504;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_943_p1 <= ap_reg_pp0_iter2_tmp_19_0_0_1_reg_4854;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p1 <= tmp_19_6_reg_6019;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p1 <= tmp_19_4_reg_5694;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p1 <= tmp_19_2_reg_5369;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_943_p1 <= tmp_349_reg_4849;
else
grp_fu_943_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_947_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_14_fu_2169_p1, ap_enable_reg_pp0_iter2, tmp_94_fu_2273_p1, tmp_174_fu_2377_p1, tmp_254_fu_2481_p1, ap_enable_reg_pp0_iter3, tmp_20_0_1_reg_7064, tmp_20_2_1_reg_7194, ap_enable_reg_pp0_iter5, tmp_20_0_1_1_reg_7584, tmp_20_2_1_1_reg_7714, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_947_p0 <= tmp_20_2_1_1_reg_7714;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_947_p0 <= tmp_20_0_1_1_reg_7584;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_947_p0 <= tmp_20_2_1_reg_7194;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_947_p0 <= tmp_20_0_1_reg_7064;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p0 <= tmp_254_fu_2481_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p0 <= tmp_174_fu_2377_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p0 <= tmp_94_fu_2273_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p0 <= tmp_14_fu_2169_p1;
else
grp_fu_947_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_947_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_1_reg_4859, ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864, ap_enable_reg_pp0_iter2, tmp_19_2_1_reg_5374, ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514, tmp_19_4_1_reg_5699, tmp_19_6_1_reg_6024, ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479, ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_947_p1 <= ap_reg_pp0_iter4_tmp_19_2_1_2_reg_6674;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_947_p1 <= ap_reg_pp0_iter4_tmp_19_0_1_2_reg_6479;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_947_p1 <= ap_reg_pp0_iter3_tmp_19_2_1_1_reg_5514;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_947_p1 <= ap_reg_pp0_iter2_tmp_19_0_1_1_reg_4864;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p1 <= tmp_19_6_1_reg_6024;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p1 <= tmp_19_4_1_reg_5699;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p1 <= tmp_19_2_1_reg_5374;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_947_p1 <= tmp_19_0_1_reg_4859;
else
grp_fu_947_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_951_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_17_fu_2173_p1, ap_enable_reg_pp0_iter2, tmp_97_fu_2277_p1, tmp_177_fu_2381_p1, tmp_257_fu_2485_p1, ap_enable_reg_pp0_iter3, tmp_20_0_2_reg_7069, tmp_20_2_2_reg_7199, ap_enable_reg_pp0_iter5, tmp_20_0_2_1_reg_7589, tmp_20_2_2_1_reg_7719, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_951_p0 <= tmp_20_2_2_1_reg_7719;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_951_p0 <= tmp_20_0_2_1_reg_7589;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_951_p0 <= tmp_20_2_2_reg_7199;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_951_p0 <= tmp_20_0_2_reg_7069;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p0 <= tmp_257_fu_2485_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p0 <= tmp_177_fu_2381_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p0 <= tmp_97_fu_2277_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p0 <= tmp_17_fu_2173_p1;
else
grp_fu_951_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_951_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_2_reg_4869, ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874, ap_enable_reg_pp0_iter2, tmp_19_2_2_reg_5379, ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524, tmp_19_4_2_reg_5704, tmp_19_6_2_reg_6029, ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484, ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_951_p1 <= ap_reg_pp0_iter4_tmp_19_2_2_2_reg_6679;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_951_p1 <= ap_reg_pp0_iter4_tmp_19_0_2_2_reg_6484;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_951_p1 <= ap_reg_pp0_iter3_tmp_19_2_2_1_reg_5524;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_951_p1 <= ap_reg_pp0_iter2_tmp_19_0_2_1_reg_4874;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p1 <= tmp_19_6_2_reg_6029;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p1 <= tmp_19_4_2_reg_5704;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p1 <= tmp_19_2_2_reg_5379;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_951_p1 <= tmp_19_0_2_reg_4869;
else
grp_fu_951_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_955_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_20_fu_2177_p1, ap_enable_reg_pp0_iter2, tmp_100_fu_2281_p1, tmp_180_fu_2385_p1, tmp_260_fu_2489_p1, ap_enable_reg_pp0_iter3, tmp_20_0_3_reg_7074, tmp_20_2_3_reg_7204, ap_enable_reg_pp0_iter5, tmp_20_0_3_1_reg_7594, tmp_20_2_3_1_reg_7724, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_955_p0 <= tmp_20_2_3_1_reg_7724;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_955_p0 <= tmp_20_0_3_1_reg_7594;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_955_p0 <= tmp_20_2_3_reg_7204;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_955_p0 <= tmp_20_0_3_reg_7074;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p0 <= tmp_260_fu_2489_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p0 <= tmp_180_fu_2385_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p0 <= tmp_100_fu_2281_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p0 <= tmp_20_fu_2177_p1;
else
grp_fu_955_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_955_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_3_reg_4879, ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884, ap_enable_reg_pp0_iter2, tmp_19_2_3_reg_5384, ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534, tmp_19_4_3_reg_5709, tmp_19_6_3_reg_6034, ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489, ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_955_p1 <= ap_reg_pp0_iter4_tmp_19_2_3_2_reg_6684;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_955_p1 <= ap_reg_pp0_iter4_tmp_19_0_3_2_reg_6489;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_955_p1 <= ap_reg_pp0_iter3_tmp_19_2_3_1_reg_5534;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_955_p1 <= ap_reg_pp0_iter2_tmp_19_0_3_1_reg_4884;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p1 <= tmp_19_6_3_reg_6034;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p1 <= tmp_19_4_3_reg_5709;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p1 <= tmp_19_2_3_reg_5384;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_955_p1 <= tmp_19_0_3_reg_4879;
else
grp_fu_955_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_959_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_23_fu_2181_p1, ap_enable_reg_pp0_iter2, tmp_103_fu_2285_p1, tmp_183_fu_2389_p1, tmp_263_fu_2493_p1, ap_enable_reg_pp0_iter3, tmp_20_0_4_reg_7079, tmp_20_2_4_reg_7209, ap_enable_reg_pp0_iter5, tmp_20_0_4_1_reg_7599, tmp_20_2_4_1_reg_7729, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_959_p0 <= tmp_20_2_4_1_reg_7729;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_959_p0 <= tmp_20_0_4_1_reg_7599;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_959_p0 <= tmp_20_2_4_reg_7209;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_959_p0 <= tmp_20_0_4_reg_7079;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p0 <= tmp_263_fu_2493_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p0 <= tmp_183_fu_2389_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p0 <= tmp_103_fu_2285_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p0 <= tmp_23_fu_2181_p1;
else
grp_fu_959_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_959_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_4_reg_4889, ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894, ap_enable_reg_pp0_iter2, tmp_19_2_4_reg_5389, ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544, tmp_19_4_4_reg_5714, tmp_19_6_4_reg_6039, ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494, ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_959_p1 <= ap_reg_pp0_iter4_tmp_19_2_4_2_reg_6689;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_959_p1 <= ap_reg_pp0_iter4_tmp_19_0_4_2_reg_6494;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_959_p1 <= ap_reg_pp0_iter3_tmp_19_2_4_1_reg_5544;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_959_p1 <= ap_reg_pp0_iter2_tmp_19_0_4_1_reg_4894;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p1 <= tmp_19_6_4_reg_6039;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p1 <= tmp_19_4_4_reg_5714;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p1 <= tmp_19_2_4_reg_5389;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_959_p1 <= tmp_19_0_4_reg_4889;
else
grp_fu_959_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_963_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_26_fu_2185_p1, ap_enable_reg_pp0_iter2, tmp_106_fu_2289_p1, tmp_186_fu_2393_p1, tmp_266_fu_2497_p1, ap_enable_reg_pp0_iter3, tmp_20_0_5_reg_7084, tmp_20_2_5_reg_7214, ap_enable_reg_pp0_iter5, tmp_20_0_5_1_reg_7604, tmp_20_2_5_1_reg_7734, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_963_p0 <= tmp_20_2_5_1_reg_7734;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_963_p0 <= tmp_20_0_5_1_reg_7604;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_963_p0 <= tmp_20_2_5_reg_7214;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_963_p0 <= tmp_20_0_5_reg_7084;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p0 <= tmp_266_fu_2497_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p0 <= tmp_186_fu_2393_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p0 <= tmp_106_fu_2289_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p0 <= tmp_26_fu_2185_p1;
else
grp_fu_963_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_963_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_5_reg_4899, ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904, ap_enable_reg_pp0_iter2, tmp_19_2_5_reg_5394, ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554, tmp_19_4_5_reg_5719, tmp_19_6_5_reg_6044, ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499, ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_963_p1 <= ap_reg_pp0_iter4_tmp_19_2_5_2_reg_6694;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_963_p1 <= ap_reg_pp0_iter4_tmp_19_0_5_2_reg_6499;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_963_p1 <= ap_reg_pp0_iter3_tmp_19_2_5_1_reg_5554;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_963_p1 <= ap_reg_pp0_iter2_tmp_19_0_5_1_reg_4904;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p1 <= tmp_19_6_5_reg_6044;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p1 <= tmp_19_4_5_reg_5719;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p1 <= tmp_19_2_5_reg_5394;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_963_p1 <= tmp_19_0_5_reg_4899;
else
grp_fu_963_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_967_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_29_fu_2189_p1, ap_enable_reg_pp0_iter2, tmp_109_fu_2293_p1, tmp_189_fu_2397_p1, tmp_269_fu_2501_p1, ap_enable_reg_pp0_iter3, tmp_20_0_6_reg_7089, tmp_20_2_6_reg_7219, ap_enable_reg_pp0_iter5, tmp_20_0_6_1_reg_7609, tmp_20_2_6_1_reg_7739, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_967_p0 <= tmp_20_2_6_1_reg_7739;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_967_p0 <= tmp_20_0_6_1_reg_7609;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_967_p0 <= tmp_20_2_6_reg_7219;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_967_p0 <= tmp_20_0_6_reg_7089;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p0 <= tmp_269_fu_2501_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p0 <= tmp_189_fu_2397_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p0 <= tmp_109_fu_2293_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p0 <= tmp_29_fu_2189_p1;
else
grp_fu_967_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_967_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_6_reg_4909, ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914, ap_enable_reg_pp0_iter2, tmp_19_2_6_reg_5399, ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564, tmp_19_4_6_reg_5724, tmp_19_6_6_reg_6049, ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504, ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_967_p1 <= ap_reg_pp0_iter4_tmp_19_2_6_2_reg_6699;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_967_p1 <= ap_reg_pp0_iter4_tmp_19_0_6_2_reg_6504;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_967_p1 <= ap_reg_pp0_iter3_tmp_19_2_6_1_reg_5564;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_967_p1 <= ap_reg_pp0_iter2_tmp_19_0_6_1_reg_4914;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p1 <= tmp_19_6_6_reg_6049;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p1 <= tmp_19_4_6_reg_5724;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p1 <= tmp_19_2_6_reg_5399;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_967_p1 <= tmp_19_0_6_reg_4909;
else
grp_fu_967_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_971_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_32_fu_2193_p1, ap_enable_reg_pp0_iter2, tmp_112_fu_2297_p1, tmp_192_fu_2401_p1, tmp_272_fu_2505_p1, ap_enable_reg_pp0_iter3, tmp_20_0_7_reg_7094, tmp_20_2_7_reg_7224, ap_enable_reg_pp0_iter5, tmp_20_0_7_1_reg_7614, tmp_20_2_7_1_reg_7744, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_971_p0 <= tmp_20_2_7_1_reg_7744;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_971_p0 <= tmp_20_0_7_1_reg_7614;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_971_p0 <= tmp_20_2_7_reg_7224;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_971_p0 <= tmp_20_0_7_reg_7094;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p0 <= tmp_272_fu_2505_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p0 <= tmp_192_fu_2401_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p0 <= tmp_112_fu_2297_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p0 <= tmp_32_fu_2193_p1;
else
grp_fu_971_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_971_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_7_reg_4919, ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924, ap_enable_reg_pp0_iter2, tmp_19_2_7_reg_5404, ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574, tmp_19_4_7_reg_5729, tmp_19_6_7_reg_6054, ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509, ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_971_p1 <= ap_reg_pp0_iter4_tmp_19_2_7_2_reg_6704;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_971_p1 <= ap_reg_pp0_iter4_tmp_19_0_7_2_reg_6509;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_971_p1 <= ap_reg_pp0_iter3_tmp_19_2_7_1_reg_5574;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_971_p1 <= ap_reg_pp0_iter2_tmp_19_0_7_1_reg_4924;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p1 <= tmp_19_6_7_reg_6054;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p1 <= tmp_19_4_7_reg_5729;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p1 <= tmp_19_2_7_reg_5404;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_971_p1 <= tmp_19_0_7_reg_4919;
else
grp_fu_971_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_975_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_35_fu_2197_p1, ap_enable_reg_pp0_iter2, tmp_115_fu_2301_p1, tmp_195_fu_2405_p1, tmp_275_fu_2509_p1, ap_enable_reg_pp0_iter3, tmp_20_0_8_reg_7099, tmp_20_2_8_reg_7229, ap_enable_reg_pp0_iter5, tmp_20_0_8_1_reg_7619, tmp_20_2_8_1_reg_7749, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_975_p0 <= tmp_20_2_8_1_reg_7749;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_975_p0 <= tmp_20_0_8_1_reg_7619;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_975_p0 <= tmp_20_2_8_reg_7229;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_975_p0 <= tmp_20_0_8_reg_7099;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p0 <= tmp_275_fu_2509_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p0 <= tmp_195_fu_2405_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p0 <= tmp_115_fu_2301_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p0 <= tmp_35_fu_2197_p1;
else
grp_fu_975_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_975_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_8_reg_4929, ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934, ap_enable_reg_pp0_iter2, tmp_19_2_8_reg_5409, ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584, tmp_19_4_8_reg_5734, tmp_19_6_8_reg_6059, ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514, ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_975_p1 <= ap_reg_pp0_iter4_tmp_19_2_8_2_reg_6709;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_975_p1 <= ap_reg_pp0_iter4_tmp_19_0_8_2_reg_6514;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_975_p1 <= ap_reg_pp0_iter3_tmp_19_2_8_1_reg_5584;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_975_p1 <= ap_reg_pp0_iter2_tmp_19_0_8_1_reg_4934;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p1 <= tmp_19_6_8_reg_6059;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p1 <= tmp_19_4_8_reg_5734;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p1 <= tmp_19_2_8_reg_5409;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_975_p1 <= tmp_19_0_8_reg_4929;
else
grp_fu_975_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_979_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_38_fu_2201_p1, ap_enable_reg_pp0_iter2, tmp_118_fu_2305_p1, tmp_198_fu_2409_p1, tmp_278_fu_2513_p1, ap_enable_reg_pp0_iter3, tmp_20_0_9_reg_7104, tmp_20_2_9_reg_7234, ap_enable_reg_pp0_iter5, tmp_20_0_9_1_reg_7624, tmp_20_2_9_1_reg_7754, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_979_p0 <= tmp_20_2_9_1_reg_7754;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_979_p0 <= tmp_20_0_9_1_reg_7624;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_979_p0 <= tmp_20_2_9_reg_7234;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_979_p0 <= tmp_20_0_9_reg_7104;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p0 <= tmp_278_fu_2513_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p0 <= tmp_198_fu_2409_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p0 <= tmp_118_fu_2305_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p0 <= tmp_38_fu_2201_p1;
else
grp_fu_979_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_979_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_9_reg_4939, ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944, ap_enable_reg_pp0_iter2, tmp_19_2_9_reg_5414, ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594, tmp_19_4_9_reg_5739, tmp_19_6_9_reg_6064, ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519, ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_979_p1 <= ap_reg_pp0_iter4_tmp_19_2_9_2_reg_6714;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_979_p1 <= ap_reg_pp0_iter4_tmp_19_0_9_2_reg_6519;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_979_p1 <= ap_reg_pp0_iter3_tmp_19_2_9_1_reg_5594;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_979_p1 <= ap_reg_pp0_iter2_tmp_19_0_9_1_reg_4944;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p1 <= tmp_19_6_9_reg_6064;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p1 <= tmp_19_4_9_reg_5739;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p1 <= tmp_19_2_9_reg_5414;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_979_p1 <= tmp_19_0_9_reg_4939;
else
grp_fu_979_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_983_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_41_fu_2205_p1, ap_enable_reg_pp0_iter2, tmp_121_fu_2309_p1, tmp_201_fu_2413_p1, tmp_281_fu_2517_p1, ap_enable_reg_pp0_iter3, tmp_20_0_s_reg_7109, tmp_20_2_s_reg_7239, ap_enable_reg_pp0_iter5, tmp_20_0_10_1_reg_7629, tmp_20_2_10_1_reg_7759, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_983_p0 <= tmp_20_2_10_1_reg_7759;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_983_p0 <= tmp_20_0_10_1_reg_7629;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_983_p0 <= tmp_20_2_s_reg_7239;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_983_p0 <= tmp_20_0_s_reg_7109;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p0 <= tmp_281_fu_2517_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p0 <= tmp_201_fu_2413_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p0 <= tmp_121_fu_2309_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p0 <= tmp_41_fu_2205_p1;
else
grp_fu_983_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_983_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_s_reg_4949, ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954, ap_enable_reg_pp0_iter2, tmp_19_2_s_reg_5419, ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604, tmp_19_4_s_reg_5744, tmp_19_6_s_reg_6069, ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524, ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_983_p1 <= ap_reg_pp0_iter4_tmp_19_2_10_2_reg_6719;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_983_p1 <= ap_reg_pp0_iter4_tmp_19_0_10_2_reg_6524;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_983_p1 <= ap_reg_pp0_iter3_tmp_19_2_10_1_reg_5604;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_983_p1 <= ap_reg_pp0_iter2_tmp_19_0_10_1_reg_4954;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p1 <= tmp_19_6_s_reg_6069;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p1 <= tmp_19_4_s_reg_5744;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p1 <= tmp_19_2_s_reg_5419;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_983_p1 <= tmp_19_0_s_reg_4949;
else
grp_fu_983_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_987_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_44_fu_2209_p1, ap_enable_reg_pp0_iter2, tmp_124_fu_2313_p1, tmp_204_fu_2417_p1, tmp_284_fu_2521_p1, ap_enable_reg_pp0_iter3, tmp_20_0_10_reg_7114, tmp_20_2_10_reg_7244, ap_enable_reg_pp0_iter5, tmp_20_0_11_1_reg_7634, tmp_20_2_11_1_reg_7764, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_987_p0 <= tmp_20_2_11_1_reg_7764;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_987_p0 <= tmp_20_0_11_1_reg_7634;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_987_p0 <= tmp_20_2_10_reg_7244;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_987_p0 <= tmp_20_0_10_reg_7114;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p0 <= tmp_284_fu_2521_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p0 <= tmp_204_fu_2417_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p0 <= tmp_124_fu_2313_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p0 <= tmp_44_fu_2209_p1;
else
grp_fu_987_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_987_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_10_reg_4959, ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964, ap_enable_reg_pp0_iter2, tmp_19_2_10_reg_5424, ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614, tmp_19_4_10_reg_5749, tmp_19_6_10_reg_6074, ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529, ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_987_p1 <= ap_reg_pp0_iter4_tmp_19_2_11_2_reg_6724;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_987_p1 <= ap_reg_pp0_iter4_tmp_19_0_11_2_reg_6529;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_987_p1 <= ap_reg_pp0_iter3_tmp_19_2_11_1_reg_5614;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_987_p1 <= ap_reg_pp0_iter2_tmp_19_0_11_1_reg_4964;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p1 <= tmp_19_6_10_reg_6074;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p1 <= tmp_19_4_10_reg_5749;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p1 <= tmp_19_2_10_reg_5424;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_987_p1 <= tmp_19_0_10_reg_4959;
else
grp_fu_987_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_991_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_47_fu_2213_p1, ap_enable_reg_pp0_iter2, tmp_127_fu_2317_p1, tmp_207_fu_2421_p1, tmp_287_fu_2525_p1, ap_enable_reg_pp0_iter3, tmp_20_0_11_reg_7119, tmp_20_2_11_reg_7249, ap_enable_reg_pp0_iter5, tmp_20_0_12_1_reg_7639, tmp_20_2_12_1_reg_7769, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_991_p0 <= tmp_20_2_12_1_reg_7769;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_991_p0 <= tmp_20_0_12_1_reg_7639;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_991_p0 <= tmp_20_2_11_reg_7249;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_991_p0 <= tmp_20_0_11_reg_7119;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p0 <= tmp_287_fu_2525_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p0 <= tmp_207_fu_2421_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p0 <= tmp_127_fu_2317_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p0 <= tmp_47_fu_2213_p1;
else
grp_fu_991_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_991_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_0_11_reg_4969, ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974, ap_enable_reg_pp0_iter2, tmp_19_2_11_reg_5429, ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624, tmp_19_4_11_reg_5754, tmp_19_6_11_reg_6079, ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534, ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_991_p1 <= ap_reg_pp0_iter4_tmp_19_2_12_2_reg_6729;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_991_p1 <= ap_reg_pp0_iter4_tmp_19_0_12_2_reg_6534;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_991_p1 <= ap_reg_pp0_iter3_tmp_19_2_12_1_reg_5624;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_991_p1 <= ap_reg_pp0_iter2_tmp_19_0_12_1_reg_4974;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p1 <= tmp_19_6_11_reg_6079;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p1 <= tmp_19_4_11_reg_5754;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p1 <= tmp_19_2_11_reg_5429;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_991_p1 <= tmp_19_0_11_reg_4969;
else
grp_fu_991_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_995_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_51_fu_2217_p1, ap_enable_reg_pp0_iter2, tmp_131_fu_2321_p1, tmp_211_fu_2425_p1, tmp_291_fu_2529_p1, ap_enable_reg_pp0_iter3, tmp_20_1_reg_7124, tmp_20_3_reg_7254, ap_enable_reg_pp0_iter5, tmp_20_1_0_1_reg_7644, tmp_20_3_0_1_reg_7774, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_995_p0 <= tmp_20_3_0_1_reg_7774;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_995_p0 <= tmp_20_1_0_1_reg_7644;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_995_p0 <= tmp_20_3_reg_7254;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_995_p0 <= tmp_20_1_reg_7124;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p0 <= tmp_291_fu_2529_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p0 <= tmp_211_fu_2425_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p0 <= tmp_131_fu_2321_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p0 <= tmp_51_fu_2217_p1;
else
grp_fu_995_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_995_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_reg_4979, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244, tmp_19_3_reg_5434, tmp_19_5_reg_5759, ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824, tmp_19_7_reg_6084, ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539, ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_995_p1 <= ap_reg_pp0_iter4_tmp_19_3_0_2_reg_6734;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_995_p1 <= ap_reg_pp0_iter4_tmp_19_1_0_2_reg_6539;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_995_p1 <= ap_reg_pp0_iter3_tmp_19_3_0_1_reg_5824;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_995_p1 <= ap_reg_pp0_iter3_tmp_19_1_0_1_reg_5244;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p1 <= tmp_19_7_reg_6084;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p1 <= tmp_19_5_reg_5759;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p1 <= tmp_19_3_reg_5434;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_995_p1 <= tmp_19_1_reg_4979;
else
grp_fu_995_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_999_p0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, ap_enable_reg_pp0_iter2, tmp_54_fu_2221_p1, tmp_134_fu_2325_p1, tmp_214_fu_2429_p1, tmp_294_fu_2533_p1, ap_enable_reg_pp0_iter3, tmp_20_1_1_reg_7129, tmp_20_3_1_reg_7259, ap_enable_reg_pp0_iter5, tmp_20_1_1_1_reg_7649, tmp_20_3_1_1_reg_7779, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_999_p0 <= tmp_20_3_1_1_reg_7779;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_999_p0 <= tmp_20_1_1_1_reg_7649;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_999_p0 <= tmp_20_3_1_reg_7259;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_999_p0 <= tmp_20_1_1_reg_7129;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p0 <= tmp_294_fu_2533_p1;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p0 <= tmp_214_fu_2429_p1;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p0 <= tmp_134_fu_2325_p1;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p0 <= tmp_54_fu_2221_p1;
else
grp_fu_999_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_999_p1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage6, ap_CS_fsm_pp0_stage7, tmp_19_1_1_reg_4984, ap_enable_reg_pp0_iter2, ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254, tmp_19_3_1_reg_5439, tmp_19_5_1_reg_5764, ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829, tmp_19_7_1_reg_6089, ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544, ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739, ap_enable_reg_pp0_iter3, ap_enable_reg_pp0_iter5, ap_block_pp0_stage0, ap_block_pp0_stage5, ap_block_pp0_stage6, ap_block_pp0_stage7, ap_block_pp0_stage2, ap_block_pp0_stage3, ap_block_pp0_stage4, ap_block_pp0_stage1)
begin
if (((ap_block_pp0_stage5 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_999_p1 <= ap_reg_pp0_iter4_tmp_19_3_1_2_reg_6739;
elsif (((ap_block_pp0_stage4 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter5))) then
grp_fu_999_p1 <= ap_reg_pp0_iter4_tmp_19_1_1_2_reg_6544;
elsif (((ap_block_pp0_stage7 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_999_p1 <= ap_reg_pp0_iter3_tmp_19_3_1_1_reg_5829;
elsif (((ap_block_pp0_stage6 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_const_logic_1 = ap_enable_reg_pp0_iter3))) then
grp_fu_999_p1 <= ap_reg_pp0_iter3_tmp_19_1_1_1_reg_5254;
elsif (((ap_block_pp0_stage3 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p1 <= tmp_19_7_1_reg_6089;
elsif (((ap_block_pp0_stage2 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p1 <= tmp_19_5_1_reg_5764;
elsif (((ap_block_pp0_stage1 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p1 <= tmp_19_3_1_reg_5439;
elsif (((ap_block_pp0_stage0 = ap_const_boolean_0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
grp_fu_999_p1 <= tmp_19_1_1_reg_4984;
else
grp_fu_999_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
i_1_fu_1553_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(ap_phi_mux_i_phi_fu_900_p4));
indvar_flatten_next1_fu_1547_p2 <= std_logic_vector(unsigned(ap_phi_mux_indvar_flatten1_phi_fu_889_p4) + unsigned(ap_const_lv10_1));
indvar_flatten_next_fu_1613_p3 <=
ap_const_lv8_1 when (exitcond_flatten_reg_3190(0) = '1') else
indvar_flatten_op_reg_3211;
indvar_flatten_op_fu_1571_p2 <= std_logic_vector(unsigned(ap_const_lv8_1) + unsigned(ap_phi_mux_indvar_flatten_phi_fu_912_p4));
j_1_fu_1642_p2 <= std_logic_vector(unsigned(ap_const_lv3_1) + unsigned(j_mid_reg_3216));
j_mid_fu_1577_p3 <=
ap_const_lv3_0 when (exitcond_flatten_reg_3190(0) = '1') else
j_reg_919;
not_exitcond_flatten_fu_1590_p2 <= (exitcond_flatten_reg_3190 xor ap_const_lv1_1);
p_shl1_cast_fu_1690_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_50_fu_1683_p3),10));
p_shl2_cast_fu_1629_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_fu_1622_p3),6));
p_shl_cast_fu_1679_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_10_fu_1672_p3),10));
row_b_1_fu_1652_p2 <= std_logic_vector(unsigned(ap_const_lv5_1) + unsigned(row_b_mid2_reg_3245));
row_b_mid2_fu_1605_p3 <=
ap_const_lv5_0 when (tmp_4_fu_1600_p2(0) = '1') else
row_b_reg_931;
tmp_100_fu_2281_p1 <= tmp_99_reg_4604;
tmp_101_fu_2730_p1 <= tmp_20_2_3_2_reg_8244;
tmp_103_fu_2285_p1 <= tmp_102_reg_4609;
tmp_104_fu_2733_p1 <= tmp_20_2_4_2_reg_8249;
tmp_106_fu_2289_p1 <= tmp_105_reg_4614;
tmp_107_fu_2736_p1 <= tmp_20_2_5_2_reg_8254;
tmp_109_fu_2293_p1 <= tmp_108_reg_4619;
tmp_10_fu_1672_p3 <= (tmp_s_reg_3270 & ap_const_lv4_0);
tmp_110_fu_2739_p1 <= tmp_20_2_6_2_reg_8259;
tmp_112_fu_2297_p1 <= tmp_111_reg_4624;
tmp_113_fu_2742_p1 <= tmp_20_2_7_2_reg_8264;
tmp_115_fu_2301_p1 <= tmp_114_reg_4629;
tmp_116_fu_2745_p1 <= tmp_20_2_8_2_reg_8269;
tmp_118_fu_2305_p1 <= tmp_117_reg_4634;
tmp_119_fu_2748_p1 <= tmp_20_2_9_2_reg_8274;
tmp_11_fu_2165_p1 <= tmp_350_reg_4449;
tmp_121_fu_2309_p1 <= tmp_120_reg_4639;
tmp_122_fu_2751_p1 <= tmp_20_2_10_2_reg_8279;
tmp_124_fu_2313_p1 <= tmp_123_reg_4644;
tmp_125_fu_2754_p1 <= tmp_20_2_11_2_reg_8284;
tmp_127_fu_2317_p1 <= tmp_126_reg_4649;
tmp_128_fu_2757_p1 <= tmp_20_2_12_2_reg_8289;
tmp_129_fu_2760_p14 <= ((((((((((((tmp_128_fu_2757_p1 & tmp_125_fu_2754_p1) & tmp_122_fu_2751_p1) & tmp_119_fu_2748_p1) & tmp_116_fu_2745_p1) & tmp_113_fu_2742_p1) & tmp_110_fu_2739_p1) & tmp_107_fu_2736_p1) & tmp_104_fu_2733_p1) & tmp_101_fu_2730_p1) & tmp_98_fu_2727_p1) & tmp_95_fu_2724_p1) & tmp_92_fu_2721_p1);
tmp_12_1_fu_1499_p2 <= std_logic_vector(unsigned(ap_phi_mux_j_phi_fu_923_p4) + unsigned(ap_const_lv3_1));
tmp_12_1_mid1_fu_1667_p2 <= std_logic_vector(unsigned(ap_const_lv3_2) + unsigned(j_mid_reg_3216));
tmp_12_2_fu_1505_p2 <= std_logic_vector(unsigned(ap_phi_mux_j_phi_fu_923_p4) + unsigned(ap_const_lv3_2));
tmp_12_2_mid1_fu_1748_p2 <= std_logic_vector(unsigned(ap_const_lv3_3) + unsigned(j_mid_reg_3216));
tmp_12_3_fu_1511_p2 <= std_logic_vector(unsigned(ap_phi_mux_j_phi_fu_923_p4) + unsigned(ap_const_lv3_3));
tmp_12_3_mid1_fu_1824_p2 <= (j_mid_reg_3216 xor ap_const_lv3_4);
tmp_12_4_fu_1517_p2 <= std_logic_vector(unsigned(tmp_6_cast2_fu_1495_p1) + unsigned(ap_const_lv4_4));
tmp_12_4_mid1_fu_1840_p2 <= std_logic_vector(unsigned(ap_const_lv4_4) + unsigned(tmp_6_cast2_mid1_fu_1811_p1));
tmp_12_5_fu_1523_p2 <= std_logic_vector(unsigned(tmp_6_cast2_fu_1495_p1) + unsigned(ap_const_lv4_5));
tmp_12_5_mid1_fu_1846_p2 <= std_logic_vector(unsigned(ap_const_lv4_5) + unsigned(tmp_6_cast2_mid1_fu_1811_p1));
tmp_12_6_fu_1529_p2 <= std_logic_vector(unsigned(tmp_6_cast2_fu_1495_p1) + unsigned(ap_const_lv4_6));
tmp_12_6_mid1_fu_1852_p2 <= std_logic_vector(unsigned(ap_const_lv4_6) + unsigned(tmp_6_cast2_mid1_fu_1811_p1));
tmp_12_7_fu_1535_p2 <= std_logic_vector(unsigned(tmp_6_cast2_fu_1495_p1) + unsigned(ap_const_lv4_7));
tmp_12_7_mid1_fu_1858_p2 <= std_logic_vector(unsigned(ap_const_lv4_7) + unsigned(tmp_6_cast2_mid1_fu_1811_p1));
tmp_12_fu_2581_p1 <= tmp_20_0_0_2_reg_8099;
tmp_130_fu_1753_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_5_mid2_cast1_fu_1718_p1));
tmp_131_fu_2321_p1 <= tmp_354_reg_4654;
tmp_132_fu_2791_p1 <= tmp_20_3_0_2_reg_8294;
tmp_134_fu_2325_p1 <= tmp_133_reg_4659;
tmp_135_fu_2794_p1 <= tmp_20_3_1_2_reg_8299;
tmp_137_fu_2329_p1 <= tmp_136_reg_4664;
tmp_138_fu_2797_p1 <= tmp_20_3_2_2_reg_8304;
tmp_13_1_mid2_cast_fu_1744_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_1_mid2_fu_1738_p3),10));
tmp_13_1_mid2_fu_1738_p3 <=
tmp_12_1_mid1_reg_3294 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_1_mid_fu_1712_p3;
tmp_13_1_mid_fu_1712_p3 <=
ap_const_lv3_1 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_1_reg_3141;
tmp_13_2_mid2_cast_fu_1820_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_2_mid2_fu_1814_p3),10));
tmp_13_2_mid2_fu_1814_p3 <=
tmp_12_2_mid1_reg_3331 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_2_mid_fu_1763_p3;
tmp_13_2_mid_fu_1763_p3 <=
ap_const_lv3_2 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_2_reg_3146;
tmp_13_3_mid2_cast_fu_1836_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_3_mid2_fu_1829_p3),10));
tmp_13_3_mid2_fu_1829_p3 <=
tmp_12_3_mid1_fu_1824_p2 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_3_mid_fu_1769_p3;
tmp_13_3_mid_fu_1769_p3 <=
ap_const_lv3_3 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_3_reg_3151;
tmp_13_4_mid2_cast_fu_1932_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_4_mid2_fu_1926_p3),10));
tmp_13_4_mid2_fu_1926_p3 <=
tmp_12_4_mid1_reg_3481 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_4_mid_fu_1886_p3;
tmp_13_4_mid_fu_1886_p3 <=
ap_const_lv4_4 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_4_reg_3156;
tmp_13_5_mid2_cast_fu_1942_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_5_mid2_fu_1936_p3),10));
tmp_13_5_mid2_fu_1936_p3 <=
tmp_12_5_mid1_reg_3486 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_5_mid_fu_1892_p3;
tmp_13_5_mid_fu_1892_p3 <=
ap_const_lv4_5 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_5_reg_3161;
tmp_13_6_mid2_cast_fu_1952_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_6_mid2_fu_1946_p3),10));
tmp_13_6_mid2_fu_1946_p3 <=
tmp_12_6_mid1_reg_3491 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_6_mid_fu_1898_p3;
tmp_13_6_mid_fu_1898_p3 <=
ap_const_lv4_6 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_6_reg_3166;
tmp_13_7_mid2_cast_fu_1962_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_13_7_mid2_fu_1956_p3),10));
tmp_13_7_mid2_fu_1956_p3 <=
tmp_12_7_mid1_reg_3496 when (tmp_7_mid_reg_3233(0) = '1') else
tmp_13_7_mid_fu_1904_p3;
tmp_13_7_mid_fu_1904_p3 <=
ap_const_lv4_7 when (exitcond_flatten_reg_3190(0) = '1') else
tmp_12_7_reg_3171;
tmp_140_fu_2333_p1 <= tmp_139_reg_4669;
tmp_141_fu_2800_p1 <= tmp_20_3_3_2_reg_8309;
tmp_143_fu_2337_p1 <= tmp_142_reg_4674;
tmp_144_fu_2803_p1 <= tmp_20_3_4_2_reg_8314;
tmp_146_fu_2341_p1 <= tmp_145_reg_4679;
tmp_147_fu_2806_p1 <= tmp_20_3_5_2_reg_8319;
tmp_149_fu_2345_p1 <= tmp_148_reg_4684;
tmp_14_fu_2169_p1 <= tmp_13_reg_4454;
tmp_150_fu_2809_p1 <= tmp_20_3_6_2_reg_8324;
tmp_152_fu_2349_p1 <= tmp_151_reg_4689;
tmp_153_fu_2812_p1 <= tmp_20_3_7_2_reg_8329;
tmp_155_fu_2353_p1 <= tmp_154_reg_4694;
tmp_156_fu_2815_p1 <= tmp_20_3_8_2_reg_8334;
tmp_158_fu_2357_p1 <= tmp_157_reg_4699;
tmp_159_fu_2818_p1 <= tmp_20_3_9_2_reg_8339;
tmp_15_fu_2584_p1 <= tmp_20_0_1_2_reg_8104;
tmp_161_fu_2361_p1 <= tmp_160_reg_4704;
tmp_162_fu_2821_p1 <= tmp_20_3_10_2_reg_8344;
tmp_164_fu_2365_p1 <= tmp_163_reg_4709;
tmp_165_fu_2824_p1 <= tmp_20_3_11_2_reg_8349;
tmp_167_fu_2369_p1 <= tmp_166_reg_4714;
tmp_168_fu_2827_p1 <= tmp_20_3_12_2_reg_8354;
tmp_169_fu_2830_p14 <= ((((((((((((tmp_168_fu_2827_p1 & tmp_165_fu_2824_p1) & tmp_162_fu_2821_p1) & tmp_159_fu_2818_p1) & tmp_156_fu_2815_p1) & tmp_153_fu_2812_p1) & tmp_150_fu_2809_p1) & tmp_147_fu_2806_p1) & tmp_144_fu_2803_p1) & tmp_141_fu_2800_p1) & tmp_138_fu_2797_p1) & tmp_135_fu_2794_p1) & tmp_132_fu_2791_p1);
tmp_170_fu_1758_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_1_mid2_cast_fu_1744_p1));
tmp_171_fu_2373_p1 <= tmp_355_reg_4719;
tmp_172_fu_2861_p1 <= tmp_20_4_0_2_reg_8359;
tmp_174_fu_2377_p1 <= tmp_173_reg_4724;
tmp_175_fu_2864_p1 <= tmp_20_4_1_2_reg_8364;
tmp_177_fu_2381_p1 <= tmp_176_reg_4729;
tmp_178_fu_2867_p1 <= tmp_20_4_2_2_reg_8369;
tmp_17_fu_2173_p1 <= tmp_16_reg_4459;
tmp_180_fu_2385_p1 <= tmp_179_reg_4734;
tmp_181_fu_2870_p1 <= tmp_20_4_3_2_reg_8374;
tmp_183_fu_2389_p1 <= tmp_182_reg_4739;
tmp_184_fu_2873_p1 <= tmp_20_4_4_2_reg_8379;
tmp_186_fu_2393_p1 <= tmp_185_reg_4744;
tmp_187_fu_2876_p1 <= tmp_20_4_5_2_reg_8384;
tmp_189_fu_2397_p1 <= tmp_188_reg_4749;
tmp_18_fu_2587_p1 <= tmp_20_0_2_2_reg_8109;
tmp_190_fu_2879_p1 <= tmp_20_4_6_2_reg_8389;
tmp_192_fu_2401_p1 <= tmp_191_reg_4754;
tmp_193_fu_2882_p1 <= tmp_20_4_7_2_reg_8394;
tmp_195_fu_2405_p1 <= tmp_194_reg_4759;
tmp_196_fu_2885_p1 <= tmp_20_4_8_2_reg_8399;
tmp_198_fu_2409_p1 <= tmp_197_reg_4764;
tmp_199_fu_2888_p1 <= tmp_20_4_9_2_reg_8404;
tmp_1_cast_fu_1700_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_reg_3257),7));
tmp_1_fu_1633_p2 <= std_logic_vector(unsigned(tmp_1_mid2_cast_fu_1619_p1) + unsigned(p_shl2_cast_fu_1629_p1));
tmp_1_mid2_cast_fu_1619_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_mid2_v_reg_3225),6));
tmp_1_mid2_v_fu_1584_p3 <=
i_1_reg_3185 when (exitcond_flatten_reg_3190(0) = '1') else
i_reg_896;
tmp_201_fu_2413_p1 <= tmp_200_reg_4769;
tmp_202_fu_2891_p1 <= tmp_20_4_10_2_reg_8409;
tmp_204_fu_2417_p1 <= tmp_203_reg_4774;
tmp_205_fu_2894_p1 <= tmp_20_4_11_2_reg_8414;
tmp_207_fu_2421_p1 <= tmp_206_reg_4779;
tmp_208_fu_2897_p1 <= tmp_20_4_12_2_reg_8419;
tmp_209_fu_2900_p14 <= ((((((((((((tmp_208_fu_2897_p1 & tmp_205_fu_2894_p1) & tmp_202_fu_2891_p1) & tmp_199_fu_2888_p1) & tmp_196_fu_2885_p1) & tmp_193_fu_2882_p1) & tmp_190_fu_2879_p1) & tmp_187_fu_2876_p1) & tmp_184_fu_2873_p1) & tmp_181_fu_2870_p1) & tmp_178_fu_2867_p1) & tmp_175_fu_2864_p1) & tmp_172_fu_2861_p1);
tmp_20_fu_2177_p1 <= tmp_19_reg_4464;
tmp_210_fu_1876_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_2_mid2_cast_fu_1820_p1));
tmp_211_fu_2425_p1 <= tmp_356_reg_4784;
tmp_212_fu_2931_p1 <= tmp_20_5_0_2_reg_8424;
tmp_214_fu_2429_p1 <= tmp_213_reg_4789;
tmp_215_fu_2934_p1 <= tmp_20_5_1_2_reg_8429;
tmp_217_fu_2433_p1 <= tmp_216_reg_4794;
tmp_218_fu_2937_p1 <= tmp_20_5_2_2_reg_8434;
tmp_21_fu_2590_p1 <= tmp_20_0_3_2_reg_8114;
tmp_220_fu_2437_p1 <= tmp_219_reg_4799;
tmp_221_fu_2940_p1 <= tmp_20_5_3_2_reg_8439;
tmp_223_fu_2441_p1 <= tmp_222_reg_4804;
tmp_224_fu_2943_p1 <= tmp_20_5_4_2_reg_8444;
tmp_226_fu_2445_p1 <= tmp_225_reg_4809;
tmp_227_fu_2946_p1 <= tmp_20_5_5_2_reg_8449;
tmp_229_fu_2449_p1 <= tmp_228_reg_4814;
tmp_230_fu_2949_p1 <= tmp_20_5_6_2_reg_8454;
tmp_232_fu_2453_p1 <= tmp_231_reg_4819;
tmp_233_fu_2952_p1 <= tmp_20_5_7_2_reg_8459;
tmp_235_fu_2457_p1 <= tmp_234_reg_4824;
tmp_236_fu_2955_p1 <= tmp_20_5_8_2_reg_8464;
tmp_238_fu_2461_p1 <= tmp_237_reg_4829;
tmp_239_fu_2958_p1 <= tmp_20_5_9_2_reg_8469;
tmp_23_fu_2181_p1 <= tmp_22_reg_4469;
tmp_241_fu_2465_p1 <= tmp_240_reg_4834;
tmp_242_fu_2961_p1 <= tmp_20_5_10_2_reg_8474;
tmp_244_fu_2469_p1 <= tmp_243_reg_4839;
tmp_245_fu_2964_p1 <= tmp_20_5_11_2_reg_8479;
tmp_247_fu_2473_p1 <= tmp_246_reg_4844;
tmp_248_fu_2967_p1 <= tmp_20_5_12_2_reg_8484;
tmp_249_fu_2970_p14 <= ((((((((((((tmp_248_fu_2967_p1 & tmp_245_fu_2964_p1) & tmp_242_fu_2961_p1) & tmp_239_fu_2958_p1) & tmp_236_fu_2955_p1) & tmp_233_fu_2952_p1) & tmp_230_fu_2949_p1) & tmp_227_fu_2946_p1) & tmp_224_fu_2943_p1) & tmp_221_fu_2940_p1) & tmp_218_fu_2937_p1) & tmp_215_fu_2934_p1) & tmp_212_fu_2931_p1);
tmp_24_fu_2593_p1 <= tmp_20_0_4_2_reg_8119;
tmp_250_fu_1881_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_3_mid2_cast_fu_1836_p1));
tmp_251_fu_2477_p1 <= tmp_357_reg_5044;
tmp_252_fu_3001_p1 <= tmp_20_6_0_2_reg_8489;
tmp_254_fu_2481_p1 <= tmp_253_reg_5049;
tmp_255_fu_3004_p1 <= tmp_20_6_1_2_reg_8494;
tmp_257_fu_2485_p1 <= tmp_256_reg_5054;
tmp_258_fu_3007_p1 <= tmp_20_6_2_2_reg_8499;
tmp_260_fu_2489_p1 <= tmp_259_reg_5059;
tmp_261_fu_3010_p1 <= tmp_20_6_3_2_reg_8504;
tmp_263_fu_2493_p1 <= tmp_262_reg_5064;
tmp_264_fu_3013_p1 <= tmp_20_6_4_2_reg_8509;
tmp_266_fu_2497_p1 <= tmp_265_reg_5069;
tmp_267_fu_3016_p1 <= tmp_20_6_5_2_reg_8514;
tmp_269_fu_2501_p1 <= tmp_268_reg_5074;
tmp_26_fu_2185_p1 <= tmp_25_reg_4474;
tmp_270_fu_3019_p1 <= tmp_20_6_6_2_reg_8519;
tmp_272_fu_2505_p1 <= tmp_271_reg_5079;
tmp_273_fu_3022_p1 <= tmp_20_6_7_2_reg_8524;
tmp_275_fu_2509_p1 <= tmp_274_reg_5084;
tmp_276_fu_3025_p1 <= tmp_20_6_8_2_reg_8529;
tmp_278_fu_2513_p1 <= tmp_277_reg_5089;
tmp_279_fu_3028_p1 <= tmp_20_6_9_2_reg_8534;
tmp_27_fu_2596_p1 <= tmp_20_0_5_2_reg_8124;
tmp_281_fu_2517_p1 <= tmp_280_reg_5094;
tmp_282_fu_3031_p1 <= tmp_20_6_10_2_reg_8539;
tmp_284_fu_2521_p1 <= tmp_283_reg_5099;
tmp_285_fu_3034_p1 <= tmp_20_6_11_2_reg_8544;
tmp_287_fu_2525_p1 <= tmp_286_reg_5104;
tmp_288_fu_3037_p1 <= tmp_20_6_12_2_reg_8549;
tmp_289_fu_3040_p14 <= ((((((((((((tmp_288_fu_3037_p1 & tmp_285_fu_3034_p1) & tmp_282_fu_3031_p1) & tmp_279_fu_3028_p1) & tmp_276_fu_3025_p1) & tmp_273_fu_3022_p1) & tmp_270_fu_3019_p1) & tmp_267_fu_3016_p1) & tmp_264_fu_3013_p1) & tmp_261_fu_3010_p1) & tmp_258_fu_3007_p1) & tmp_255_fu_3004_p1) & tmp_252_fu_3001_p1);
tmp_290_fu_1978_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_4_mid2_cast_fu_1932_p1));
tmp_291_fu_2529_p1 <= tmp_358_reg_5109;
tmp_292_fu_3071_p1 <= tmp_20_7_0_2_reg_8554;
tmp_294_fu_2533_p1 <= tmp_293_reg_5114;
tmp_295_fu_3074_p1 <= tmp_20_7_1_2_reg_8559;
tmp_297_fu_2537_p1 <= tmp_296_reg_5119;
tmp_298_fu_3077_p1 <= tmp_20_7_2_2_reg_8564;
tmp_29_fu_2189_p1 <= tmp_28_reg_4479;
tmp_2_cast_fu_1703_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_2_reg_3281),7));
tmp_2_cast_mid2_fu_1639_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_1_mid2_v_reg_3225),5));
tmp_2_fu_1657_p2 <= std_logic_vector(unsigned(ap_const_lv6_19) + unsigned(tmp_1_reg_3257));
tmp_300_fu_2541_p1 <= tmp_299_reg_5124;
tmp_301_fu_3080_p1 <= tmp_20_7_3_2_reg_8569;
tmp_303_fu_2545_p1 <= tmp_302_reg_5129;
tmp_304_fu_3083_p1 <= tmp_20_7_4_2_reg_8574;
tmp_306_fu_2549_p1 <= tmp_305_reg_5134;
tmp_307_fu_3086_p1 <= tmp_20_7_5_2_reg_8579;
tmp_309_fu_2553_p1 <= tmp_308_reg_5139;
tmp_30_fu_2599_p1 <= tmp_20_0_6_2_reg_8129;
tmp_310_fu_3089_p1 <= tmp_20_7_6_2_reg_8584;
tmp_312_fu_2557_p1 <= tmp_311_reg_5144;
tmp_313_fu_3092_p1 <= tmp_20_7_7_2_reg_8589;
tmp_315_fu_2561_p1 <= tmp_314_reg_5149;
tmp_316_fu_3095_p1 <= tmp_20_7_8_2_reg_8594;
tmp_318_fu_2565_p1 <= tmp_317_reg_5154;
tmp_319_fu_3098_p1 <= tmp_20_7_9_2_reg_8599;
tmp_321_fu_2569_p1 <= tmp_320_reg_5159;
tmp_322_fu_3101_p1 <= tmp_20_7_10_2_reg_8604;
tmp_324_fu_2573_p1 <= tmp_323_reg_5164;
tmp_325_fu_3104_p1 <= tmp_20_7_11_2_reg_8609;
tmp_327_fu_2577_p1 <= tmp_326_reg_5169;
tmp_328_fu_3107_p1 <= tmp_20_7_12_2_reg_8614;
tmp_329_fu_3110_p14 <= ((((((((((((tmp_328_fu_3107_p1 & tmp_325_fu_3104_p1) & tmp_322_fu_3101_p1) & tmp_319_fu_3098_p1) & tmp_316_fu_3095_p1) & tmp_313_fu_3092_p1) & tmp_310_fu_3089_p1) & tmp_307_fu_3086_p1) & tmp_304_fu_3083_p1) & tmp_301_fu_3080_p1) & tmp_298_fu_3077_p1) & tmp_295_fu_3074_p1) & tmp_292_fu_3071_p1);
tmp_32_fu_2193_p1 <= tmp_31_reg_4484;
tmp_330_cast_fu_1910_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_7_reg_3356),64));
tmp_330_fu_1983_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_5_mid2_cast_fu_1942_p1));
tmp_331_fu_1988_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_6_mid2_cast_fu_1952_p1));
tmp_332_fu_1993_p2 <= std_logic_vector(unsigned(tmp_90_reg_3299) + unsigned(tmp_13_7_mid2_cast_fu_1962_p1));
tmp_333_fu_2022_p3 <= (ap_reg_pp0_iter1_row_b_mid2_reg_3245 & ap_const_lv3_0);
tmp_334_cast_fu_1864_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_130_reg_3336),64));
tmp_334_fu_2029_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_333_fu_2022_p3),64));
tmp_335_cast_fu_1870_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(tmp_170_reg_3341),64));
tmp_335_fu_2034_p2 <= (tmp_333_fu_2022_p3 or ap_const_lv8_1);
tmp_336_cast_fu_1966_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_210_reg_3511),64));
tmp_336_fu_2040_p3 <= (ap_const_lv56_0 & tmp_335_fu_2034_p2);
tmp_337_cast_fu_1972_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_250_reg_3516),64));
tmp_337_fu_2049_p2 <= (tmp_333_reg_4307 or ap_const_lv8_2);
tmp_338_cast_fu_1998_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_290_reg_3616),64));
tmp_338_fu_2054_p3 <= (ap_const_lv56_0 & tmp_337_fu_2049_p2);
tmp_339_cast_fu_2004_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_330_reg_3621),64));
tmp_339_fu_2063_p2 <= (tmp_333_reg_4307 or ap_const_lv8_3);
tmp_33_fu_2602_p1 <= tmp_20_0_7_2_reg_8134;
tmp_340_cast_fu_2010_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_331_reg_3626),64));
tmp_340_fu_2068_p3 <= (ap_const_lv56_0 & tmp_339_fu_2063_p2);
tmp_341_cast_fu_2016_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_332_reg_3631),64));
tmp_341_fu_2077_p2 <= (tmp_333_reg_4307 or ap_const_lv8_4);
tmp_342_fu_2082_p3 <= (ap_const_lv56_0 & tmp_341_fu_2077_p2);
tmp_343_fu_2091_p2 <= (tmp_333_reg_4307 or ap_const_lv8_5);
tmp_344_fu_2096_p3 <= (ap_const_lv56_0 & tmp_343_fu_2091_p2);
tmp_345_fu_2113_p2 <= (tmp_333_reg_4307 or ap_const_lv8_6);
tmp_346_fu_2118_p3 <= (ap_const_lv56_0 & tmp_345_fu_2113_p2);
tmp_347_fu_2127_p2 <= (tmp_333_reg_4307 or ap_const_lv8_7);
tmp_348_fu_2132_p3 <= (ap_const_lv56_0 & tmp_347_fu_2127_p2);
tmp_350_fu_2105_p0 <= bufo_Dout_A(416 - 1 downto 0);
tmp_350_fu_2105_p1 <= tmp_350_fu_2105_p0(32 - 1 downto 0);
tmp_352_fu_2109_p0 <= bufo_Dout_B(416 - 1 downto 0);
tmp_352_fu_2109_p1 <= tmp_352_fu_2109_p0(32 - 1 downto 0);
tmp_353_fu_2141_p0 <= bufo_Dout_A(416 - 1 downto 0);
tmp_353_fu_2141_p1 <= tmp_353_fu_2141_p0(32 - 1 downto 0);
tmp_354_fu_2145_p0 <= bufo_Dout_B(416 - 1 downto 0);
tmp_354_fu_2145_p1 <= tmp_354_fu_2145_p0(32 - 1 downto 0);
tmp_355_fu_2149_p0 <= bufo_Dout_A(416 - 1 downto 0);
tmp_355_fu_2149_p1 <= tmp_355_fu_2149_p0(32 - 1 downto 0);
tmp_356_fu_2153_p0 <= bufo_Dout_B(416 - 1 downto 0);
tmp_356_fu_2153_p1 <= tmp_356_fu_2153_p0(32 - 1 downto 0);
tmp_357_fu_2157_p0 <= bufo_Dout_A(416 - 1 downto 0);
tmp_357_fu_2157_p1 <= tmp_357_fu_2157_p0(32 - 1 downto 0);
tmp_358_fu_2161_p0 <= bufo_Dout_B(416 - 1 downto 0);
tmp_358_fu_2161_p1 <= tmp_358_fu_2161_p0(32 - 1 downto 0);
tmp_35_fu_2197_p1 <= tmp_34_reg_4489;
tmp_36_fu_2605_p1 <= tmp_20_0_8_2_reg_8139;
tmp_38_fu_2201_p1 <= tmp_37_reg_4494;
tmp_39_fu_2608_p1 <= tmp_20_0_9_2_reg_8144;
tmp_3_fu_1706_p2 <= std_logic_vector(unsigned(ap_const_lv7_32) + unsigned(tmp_1_cast_fu_1700_p1));
tmp_41_fu_2205_p1 <= tmp_40_reg_4499;
tmp_42_fu_2611_p1 <= tmp_20_0_10_2_reg_8149;
tmp_44_fu_2209_p1 <= tmp_43_reg_4504;
tmp_45_fu_2614_p1 <= tmp_20_0_11_2_reg_8154;
tmp_47_fu_2213_p1 <= tmp_46_reg_4509;
tmp_48_fu_2617_p1 <= tmp_20_0_12_2_reg_8159;
tmp_49_fu_2620_p14 <= ((((((((((((tmp_48_fu_2617_p1 & tmp_45_fu_2614_p1) & tmp_42_fu_2611_p1) & tmp_39_fu_2608_p1) & tmp_36_fu_2605_p1) & tmp_33_fu_2602_p1) & tmp_30_fu_2599_p1) & tmp_27_fu_2596_p1) & tmp_24_fu_2593_p1) & tmp_21_fu_2590_p1) & tmp_18_fu_2587_p1) & tmp_15_fu_2584_p1) & tmp_12_fu_2581_p1);
tmp_4_fu_1600_p2 <= (tmp_7_mid_fu_1595_p2 or exitcond_flatten_reg_3190);
tmp_50_fu_1683_p3 <= (tmp_s_reg_3270 & ap_const_lv2_0);
tmp_51_fu_2217_p1 <= tmp_352_reg_4514;
tmp_52_fu_2651_p1 <= tmp_20_1_0_2_reg_8164;
tmp_54_fu_2221_p1 <= tmp_53_reg_4519;
tmp_55_fu_2654_p1 <= tmp_20_1_1_2_reg_8169;
tmp_57_fu_2225_p1 <= tmp_56_reg_4524;
tmp_58_fu_2657_p1 <= tmp_20_1_2_2_reg_8174;
tmp_5_fu_1565_p2 <= "1" when (ap_phi_mux_row_b_phi_fu_935_p4 = ap_const_lv5_1B) else "0";
tmp_5_mid2_cast1_fu_1718_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_mid2_reg_3286),10));
tmp_5_mid2_cast2_fu_1721_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_mid2_reg_3286),7));
tmp_5_mid2_cast_fu_1724_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_5_mid2_reg_3286),6));
tmp_5_mid2_fu_1662_p3 <=
j_1_reg_3264 when (tmp_7_mid_reg_3233(0) = '1') else
j_mid_reg_3216;
tmp_60_fu_2229_p1 <= tmp_59_reg_4529;
tmp_61_fu_2660_p1 <= tmp_20_1_3_2_reg_8179;
tmp_63_fu_2233_p1 <= tmp_62_reg_4534;
tmp_64_fu_2663_p1 <= tmp_20_1_4_2_reg_8184;
tmp_66_fu_2237_p1 <= tmp_65_reg_4539;
tmp_67_fu_2666_p1 <= tmp_20_1_5_2_reg_8189;
tmp_69_fu_2241_p1 <= tmp_68_reg_4544;
tmp_6_cast2_fu_1495_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(ap_phi_mux_j_phi_fu_923_p4),4));
tmp_6_cast2_mid1_fu_1811_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(j_1_reg_3264),4));
tmp_6_cast_fu_1775_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_6_reg_3321),64));
tmp_6_fu_1727_p2 <= std_logic_vector(unsigned(tmp_1_reg_3257) + unsigned(tmp_5_mid2_cast_fu_1724_p1));
tmp_70_fu_2669_p1 <= tmp_20_1_6_2_reg_8194;
tmp_72_fu_2245_p1 <= tmp_71_reg_4549;
tmp_73_fu_2672_p1 <= tmp_20_1_7_2_reg_8199;
tmp_75_fu_2249_p1 <= tmp_74_reg_4554;
tmp_76_fu_2675_p1 <= tmp_20_1_8_2_reg_8204;
tmp_78_fu_2253_p1 <= tmp_77_reg_4559;
tmp_79_fu_2678_p1 <= tmp_20_1_9_2_reg_8209;
tmp_7_fu_1807_p2 <= std_logic_vector(unsigned(tmp_3_reg_3311) + unsigned(tmp_5_mid2_cast2_reg_3316));
tmp_7_mid_fu_1595_p2 <= (tmp_5_reg_3206 and not_exitcond_flatten_fu_1590_p2);
tmp_81_fu_2257_p1 <= tmp_80_reg_4564;
tmp_82_fu_2681_p1 <= tmp_20_1_10_2_reg_8214;
tmp_84_fu_2261_p1 <= tmp_83_reg_4569;
tmp_85_fu_2684_p1 <= tmp_20_1_11_2_reg_8219;
tmp_87_fu_2265_p1 <= tmp_86_reg_4574;
tmp_88_fu_2687_p1 <= tmp_20_1_12_2_reg_8224;
tmp_89_fu_2690_p14 <= ((((((((((((tmp_88_fu_2687_p1 & tmp_85_fu_2684_p1) & tmp_82_fu_2681_p1) & tmp_79_fu_2678_p1) & tmp_76_fu_2675_p1) & tmp_73_fu_2672_p1) & tmp_70_fu_2669_p1) & tmp_67_fu_2666_p1) & tmp_64_fu_2663_p1) & tmp_61_fu_2660_p1) & tmp_58_fu_2657_p1) & tmp_55_fu_2654_p1) & tmp_52_fu_2651_p1);
tmp_8_cast_fu_1791_p1 <= std_logic_vector(IEEE.numeric_std.resize(unsigned(tmp_8_reg_3326),64));
tmp_8_fu_1732_p2 <= std_logic_vector(unsigned(tmp_2_cast_fu_1703_p1) + unsigned(tmp_5_mid2_cast2_fu_1721_p1));
tmp_90_fu_1694_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_1679_p1) - unsigned(p_shl1_cast_fu_1690_p1));
tmp_91_fu_2269_p1 <= tmp_353_reg_4589;
tmp_92_fu_2721_p1 <= tmp_20_2_0_2_reg_8229;
tmp_94_fu_2273_p1 <= tmp_93_reg_4594;
tmp_95_fu_2724_p1 <= tmp_20_2_1_2_reg_8234;
tmp_97_fu_2277_p1 <= tmp_96_reg_4599;
tmp_98_fu_2727_p1 <= tmp_20_2_2_2_reg_8239;
tmp_fu_1622_p3 <= (tmp_1_mid2_v_reg_3225 & ap_const_lv2_0);
tmp_s_fu_1647_p2 <= std_logic_vector(unsigned(tmp_2_cast_mid2_fu_1639_p1) + unsigned(row_b_mid2_reg_3245));
end behav;
| mit | 48e70715296fe7aec228da332e96570d | 0.623418 | 2.442617 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/stratixii/clkgen_stratixii.vhd | 1 | 6,703 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity stratix2_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of stratix2_pll is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Stratix II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_stratixii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_stratixii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
-- altera pll
component stratix2_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
e0 : out std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : stratix2_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_stratixii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_stratixii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
| gpl-2.0 | 9d701f0091573c7600dba7b058400ffd | 0.584962 | 3.513103 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-terasic-de0-nano/leon3mp.vhd | 1 | 20,867 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2012 Aeroflex Gaisler
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.i2c.all;
use gaisler.spi.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS;
dbguart : integer := CFG_DUART;
pclow : integer := CFG_PCLOW
);
port (
clock_50 : in std_logic;
led : inout std_logic_vector(7 downto 0);
key : in std_logic_vector(1 downto 0);
sw : in std_logic_vector(3 downto 0);
dram_ba : out std_logic_vector(1 downto 0);
dram_dqm : out std_logic_vector(1 downto 0);
dram_ras_n : out std_ulogic;
dram_cas_n : out std_ulogic;
dram_cke : out std_ulogic;
dram_clk : out std_ulogic;
dram_we_n : out std_ulogic;
dram_cs_n : out std_ulogic;
dram_dq : inout std_logic_vector(15 downto 0);
dram_addr : out std_logic_vector(12 downto 0);
epcs_data0 : in std_ulogic;
epcs_dclk : out std_ulogic;
epcs_ncso : out std_ulogic;
epcs_asdo : out std_ulogic;
i2c_sclk : inout std_logic;
i2c_sdat : inout std_logic;
g_sensor_cs_n : out std_ulogic;
g_sensor_int : in std_ulogic;
adc_cs_n : out std_ulogic;
adc_saddr : out std_ulogic;
adc_sclk : out std_ulogic;
adc_sdat : in std_ulogic;
gpio_2 : inout std_logic_vector(12 downto 0);
gpio_2_in : in std_logic_vector(2 downto 0);
gpio_1_in : in std_logic_vector(1 downto 0);
gpio_1 : inout std_logic_vector(33 downto 0);
gpio_0_in : in std_logic_vector(1 downto 0);
gpio_0 : inout std_logic_vector(33 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc, gnd : std_logic_vector(4 downto 0);
signal clkm, rstn, rstraw, sdclkl, lclk, rst, clklck : std_ulogic;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal fpi : grfpu_in_vector_type;
signal fpo : grfpu_out_vector_type;
signal stati : ahbstat_in_type;
signal gpti : gptimer_in_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal gpio0i, gpio1i, gpio2i : gpio_in_type;
signal gpio0o, gpio1o, gpio2o : gpio_out_type;
signal dsubren : std_ulogic;
signal tck, tms, tdi, tdo : std_logic;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz, used in clkgen
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV;
constant IOAEN : integer := 1;
constant OEPOL : integer := padoen_polarity(padtech);
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
clk_pad : clkpad generic map (tech => padtech) port map (clock_50, lclk);
clkgen0 : entity work.clkgen_de0
generic map (clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV,
clk_freq => BOARD_FREQ, sdramen => CFG_SDCTRL)
port map (inclk0 => lclk, c0 => clkm, c0_2x => open, e0 => sdclkl,
locked => clklck);
sdclk_pad : outpad generic map (tech => padtech, slew => 1)
port map (dram_clk, sdclkl);
resetn_pad : inpad generic map (tech => padtech) port map (key(0), rst);
rst0 : rstgen -- reset generator (reset is active LOW)
port map (rst, clkm, clklck, rstn, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_JTAG,
nahbs => 6)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
----- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
nosh : if CFG_GRFPUSH = 0 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
sh : if CFG_GRFPUSH = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3sh -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
0, 0, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), fpi(i), fpo(i));
end generate;
grfpush0 : grfpushwx generic map ((CFG_FPU-1), CFG_NCPU, fabtech)
port map (clkm, rstn, fpi, fpo);
end generate;
errorn_pad : outpad generic map (tech => padtech) port map (led(6), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0,
kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsuen_pad : inpad generic map (tech => padtech) port map (sw(0), dsui.enable);
dsubre_pad : inpad generic map (tech => padtech) port map (key(1), dsubren);
dsui.break <= not dsubren;
dsuact_pad : outpad generic map (tech => padtech) port map (led(7), dsuo.active);
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
sdctrl0 : if CFG_SDCTRL = 1 generate -- 16-bit SDRAM controller
sdc : entity work.sdctrl16
generic map (hindex => 3, haddr => 16#400#, hmask => 16#FE0#,
ioaddr => 1, fast => 0, pwron => 0, invclk => 0,
sdbits => 16, pageburst => 2)
port map (rstn, clkm, ahbsi, ahbso(3), sdi, sdo);
sa_pad : outpadv generic map (width => 13, tech => padtech)
port map (dram_addr, sdo.address(14 downto 2));
ba0_pad : outpadv generic map (tech => padtech, width => 2)
port map (dram_ba, sdo.address(16 downto 15));
sd_pad : iopadvv generic map (width => 16, tech => padtech, oepol => OEPOL)
port map (dram_dq(15 downto 0), sdo.data(15 downto 0), sdo.vbdrive(15 downto 0), sdi.data(15 downto 0));
sdcke_pad : outpad generic map (tech => padtech)
port map (dram_cke, sdo.sdcke(0));
sdwen_pad : outpad generic map (tech => padtech)
port map (dram_we_n, sdo.sdwen);
sdcsn_pad : outpad generic map (tech => padtech)
port map (dram_cs_n, sdo.sdcsn(0));
sdras_pad : outpad generic map (tech => padtech)
port map (dram_ras_n, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (dram_cas_n, sdo.casn);
sddqm_pad : outpadv generic map (tech => padtech, width => 2)
port map (dram_dqm, sdo.dqm(1 downto 0));
end generate;
spimctrl0: if CFG_SPIMCTRL /= 0 generate -- SPI Memory Controller
spimc : spimctrl
generic map (hindex => 0, hirq => 10, faddr => 16#000#, fmask => 16#f00#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => OEPOL,sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD, dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT, scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER, pwrupcnt => CFG_SPIMCTRL_PWRUPCNT,
offset => CFG_SPIMCTRL_OFFSET)
port map (rstn, clkm, ahbsi, ahbso(0), spmi, spmo);
end generate;
nospimctrl0 : if CFG_SPIMCTRL = 0 generate spmo <= spimctrl_out_none; end generate;
miso_pad : inpad generic map (tech => padtech)
port map (epcs_data0, spmi.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (epcs_asdo, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (epcs_dclk, spmo.sck);
slvsel0_pad : outpad generic map (tech => padtech)
port map (epcs_ncso, spmo.csn);
----------------------------------------------------------------------
--- AHB ROM ---------------------------------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 and CFG_SPIMCTRL = 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map (rstn, clkm, ahbsi, ahbso(0));
end generate;
noprom : if CFG_AHBROMEN = 0 and CFG_SPIMCTRL = 0 generate
ahbso(0) <= ahbs_none;
end generate;
----------------------------------------------------------------------
--- APB Bridge and various peripherals ------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
apbo(0) <= apb_none; -- Typically occupied by memory controller
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, flow => 0,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
u1i.rxd <= '1';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 4, paddr => 4, pmask => 16#FFF#,
pirq => 3, filter => 3, dynfilt => 1)
port map (rstn, clkm, apbi, apbo(4), i2ci, i2co);
end generate;
noi2cm: if CFG_I2C_ENABLE = 0 generate
i2co.scloen <= '1'; i2co.sdaoen <= '1';
i2co.scl <= '0'; i2co.sda <= '0';
end generate;
i2c_scl_pad : iopad generic map (tech => padtech)
port map (i2c_sclk, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (i2c_sdat, i2co.sda, i2co.sdaoen, i2ci.sda);
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 5, paddr => 5, pmask => 16#fff#, pirq => 5,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(5), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
spii.astart <= '0';
miso_pad : inpad generic map (tech => padtech)
port map (adc_sdat, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (adc_saddr, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (adc_sclk, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (adc_cs_n, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (adc_sdat, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (adc_saddr, vcc(0));
sck_pad : outpad generic map (tech => padtech)
port map (adc_sclk, gnd(0));
slvsel_pad : outpad generic map (tech => padtech)
port map (adc_cs_n, vcc(0));
end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GRGPIO0 port
grgpio0: grgpio
generic map( pindex => 9, paddr => 9, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map( rstn, clkm, apbi, apbo(9), gpio0i, gpio0o);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio_0(i), gpio0o.dout(i), gpio0o.oen(i), gpio0i.din(i));
end generate;
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
gpio1 : if CFG_GRGPIO2_ENABLE /= 0 generate -- GRGPIO1 port
grgpio1: grgpio
generic map( pindex => 10, paddr => 10, imask => CFG_GRGPIO2_IMASK, nbits => CFG_GRGPIO2_WIDTH)
port map( rstn, clkm, apbi, apbo(10), gpio1i, gpio1o);
pio_pads : for i in 0 to CFG_GRGPIO2_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio_1(i), gpio1o.dout(i), gpio1o.oen(i), gpio1i.din(i));
end generate;
end generate;
nogpio1: if CFG_GRGPIO2_ENABLE = 0 generate apbo(10) <= apb_none; end generate;
grgpio2: grgpio -- GRGPIO2 port
generic map( pindex => 11, paddr => 11, imask => 2**30, nbits => 31)
port map( rstn, clkm, apbi, apbo(11), gpio2i, gpio2o);
gpio_2_pads : iopadvv generic map (tech => padtech, width => 13)
port map (gpio_2(12 downto 0), gpio2o.dout(12 downto 0), gpio2o.oen(12 downto 0),
gpio2i.din(12 downto 0));
gpio_2_inpads : inpadv generic map (tech => padtech, width => 3)
port map (gpio_2_in, gpio2i.din(15 downto 13));
gpio_0_pads : iopadvv generic map (tech => padtech, width => 2)
port map (gpio_0(33 downto 32), gpio2o.dout(17 downto 16), gpio2o.oen(17 downto 16),
gpio2i.din(17 downto 16));
gpio_0_inpads : inpadv generic map (tech => padtech, width => 2)
port map (gpio_0_in, gpio2i.din(19 downto 18));
gpio_1_pads : iopadvv generic map (tech => padtech, width => 2)
port map (gpio_1(33 downto 32), gpio2o.dout(21 downto 20), gpio2o.oen(21 downto 20),
gpio2i.din(21 downto 20));
gpio_1_inpads : inpadv generic map (tech => padtech, width => 2)
port map (gpio_1_in, gpio2i.din(23 downto 22));
led_pads : iopadvv generic map (tech => padtech, width => 6)
port map (led(5 downto 0), gpio2o.dout(29 downto 24), gpio2o.oen(29 downto 24),
gpio2i.din(29 downto 24));
g_sensor_int_pad : inpad generic map (tech => padtech)
port map (g_sensor_int, gpio2i.din(30));
-- g_sensor_cs_n_pad : outpad generic map (tech => padtech)
-- port map (g_sensor_cs_n, gpio2o.dout(31));
g_sensor_cs_n <= '1';
-- gpio2i.din(31) <= gpio2o.dout(31);
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 1, nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
port map (rstn, clkm, ahbsi, ahbso(4));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(4) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0 : ahbrep generic map (hindex => 5, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(5));
-- pragma translate_on
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera DE0-EP4CE22 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | fdf746da74fffeecc03b3304f87ef72b | 0.559592 | 3.60335 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-ep1c20/testbench.vhd | 1 | 11,804 | ------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
clkout : out std_ulogic;
pllref : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
ramsn : out std_ulogic;
ramoen : out std_ulogic;
rwen : out std_ulogic;
mben : out std_logic_vector (3 downto 0);
iosn : out std_ulogic;
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
sa : out std_logic_vector(11 downto 0);
sd : inout std_logic_vector(31 downto 0);
sdclk : out std_ulogic;
sdcke : out std_ulogic; -- sdram clock enable
sdcsn : out std_ulogic; -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
sdba : out std_logic_vector (1 downto 0);
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsubren : in std_ulogic;
dsuact : out std_ulogic;
rxd1 : in std_ulogic; -- UART1 rx data
txd1 : out std_ulogic; -- UART1 tx data
-- for smc lan chip
eth_aen : out std_ulogic;
eth_readn : out std_ulogic;
eth_writen : out std_ulogic;
eth_nbe : out std_logic_vector (3 downto 0);
eth_lclk : out std_ulogic;
eth_nads : out std_logic;
eth_ncycle : out std_logic;
eth_wnr : out std_logic;
eth_nvlbus : out std_logic;
eth_nrdyrtn : out std_logic;
eth_ndatacs : out std_logic
);
end component;
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector (3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal sdba : std_logic_vector(1 downto 0);
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
pllref <= clkout;
d3 : leon3mp
generic map ( fabtech, memtech, padtech, clktech, ncpu,
disas, dbguart, pclow )
port map (rst, clk, clkout, pllref, error, address, data,
ramsn, ramoen, rwen, mben, iosn,
romsn, oen, writen,
sa(11 downto 0), sd, sdclk, sdcke, sdcsn, sdwen, sdrasn, sdcasn, sddqm, sdba,
dsutx, dsurx, dsubren, dsuact,
rxd1, txd1,
eth_aen, eth_readn, eth_writen, eth_nbe);
-- optional sdram
sd1 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, rwen, oen);
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn,
rwen, ramoen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
| gpl-2.0 | 1fa1d6dc3a84d04f9275a22d2b6f0544 | 0.570739 | 3.218103 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/ddr1spax_ddr.vhd | 1 | 40,484 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr1spax_ddr
-- File: ddr1spax_ddr.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Merged 16/32/64-bit DDR/mobile-DDR backend
-- Based on ddrsp*a and ddr2spax_ddr
--------------------------------------------------------------------------------
-- Added features from the original ddrspa:
-- * Separated AHB,DDR parts of controller like for DDR2SPA
-- * 64/32/16 bit interfaces in the same entity
-- * Checkbit support for use with ft_ddr2spax_ahb front-end.
-- * Extended timing fields plus tRAS setting to meet DDR400 timing.
-- * Configurable burst length
-- * Support for PHY:s with read data valid signaling and extra latency
-- Incompatibility/differences to the original ddrspa:
-- * The mobile DDR had an undocumented feature that tRFC was extended with 8
-- cycles if the TRP bit was set. This is replaced by the extended
-- timing fields.
-- * ddrsp16a used a separate read-clock supplied only from the Spartan PHY.
-- * Reads/writes are made as multiple length-2 burst commands.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr1spax_ddr is
generic (
ddrbits : integer := 32;
burstlen : integer := 8;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 8;
pwron : integer := 0;
oepol : integer := 0;
mobile : integer := 0;
confapi : integer := 0;
conf0 : integer := 0;
conf1 : integer := 0;
nosync : integer := 0;
ddr_syncrst: integer range 0 to 1 := 0;
chkbits : integer := 0;
hasdqvalid : integer := 0;
readdly : integer := 0;
regoutput : integer := 1;
ddr400 : integer := 1;
rstdel : integer := 200;
phyptctrl : integer := 0;
scantest : integer := 0
);
port (
ddr_rst : in std_ulogic;
clk_ddr : in std_ulogic;
request : in ddr_request_type;
start_tog: in std_logic;
response : out ddr_response_type;
sdi : in ddrctrl_in_type;
sdo : out ddrctrl_out_type;
wbraddr : out std_logic_vector(log2((16*burstlen)/ddrbits) downto 0);
wbrdata : in std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwaddr : out std_logic_vector(log2((16*burstlen)/ddrbits)-1 downto 0);
rbwdata : out std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
rbwrite : out std_logic;
reqsel : in std_ulogic;
frequest : in ddr_request_type;
response2: out ddr_response_type;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic
);
end ddr1spax_ddr;
architecture rtl of ddr1spax_ddr is
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ddrw: integer := log2(ddrbits*2);
constant l2ddr_burstlen: integer := l2blen-l2ddrw;
-- constant oepols: std_logic := tosl(oepol);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_rabits: integer := 1+l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant wbuf_rdbits: integer := 2*ddrbits;
-- Read buffer dimensions
constant rbuf_wabits: integer := l2blen-l2ddrw; -- log2((burstlen*32)/(2*ddrbits));
constant rbuf_wdbits: integer := 2*(ddrbits+chkbits);
type ddrstate is (dsidle,dsact1,dsact2,dsact3,dswr1,dswr2,dswr3,dswr4,dswr5,dswr6,
dsrd1,dsrd2,dsrd3,dsrd4,dsreg1,dsreg2,dscmd1,dscmd2,dspdown1,dspdown2,dsref1,
dssrr1,dssrr2);
type ddrinitstate is (disrstdel,disidle,disrun,disfinished);
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
trcd : std_ulogic; -- tCD : 2/3 clock cycles
trfc : std_logic_vector(4 downto 0);
trp : std_logic_vector(1 downto 0); -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(11 downto 0);
renable : std_ulogic;
dllrst : std_ulogic;
refon : std_ulogic;
cke : std_ulogic;
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
ds : std_logic_vector(5 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
mobileen : std_logic; -- Mobile SD support, Mobile SD enabled
txsr : std_logic_vector(5 downto 0); -- Exit Self Refresh timing
txp : std_logic_vector(1 downto 0); -- Exit Power-Down timing
tcke : std_logic; -- Clock enable timing
cl : std_logic; -- CAS latency 2/3 (0/1)
conf : std_logic_vector(63 downto 0); -- PHY control
tras : std_logic_vector(1 downto 0); -- tRAS minimum (6-9 cycles)
twr : std_logic; -- tWR write recovery, 2/3 cycles
end record;
type ddr_reg_type is record
s : ddrstate;
initstate : ddrinitstate;
cfg : sdram_cfg_type;
resp,resp2 : ddr_response_type;
req1,req2 : ddr_request_type;
start1,start2 : std_logic;
start3 : std_logic;
ramaddr : std_logic_vector(rbuf_wabits-1 downto 0);
readpipe : std_logic_vector(4+readdly downto 0);
initpos : std_logic_vector(2 downto 0);
cmdctr : std_logic_vector(7 downto 0);
readdone : std_logic;
refctr : std_logic_vector(17 downto 0);
refpend : std_logic;
idlectr : std_logic_vector(3 downto 0);
pdowns : std_logic_vector(1 downto 0);
sdo_casn : std_logic;
sdo_rasn : std_logic;
sdo_wen : std_logic;
sdo_csn : std_logic_vector(1 downto 0);
sdo_ba : std_logic_vector(1 downto 0);
sdo_address : std_logic_vector(14 downto 0);
sdo_data : std_logic_vector(2*ddrbits-1 downto 0);
sdo_dqm : std_logic_vector(ddrbits/4-1 downto 0);
sdo_cb : std_logic_vector(2*chkbits downto 0);
sdo_ck : std_logic_vector(2 downto 0);
sdo_bdrive : std_logic;
sdo_qdrive : std_logic;
end record;
signal dr,ndr: ddr_reg_type;
constant onev: std_logic_vector(15 downto 0) := x"FFFF";
constant zerov: std_logic_vector(15 downto 0) := x"0000";
signal arst : std_ulogic;
begin
arst <= testrst when (scantest/=0 and ddr_syncrst=0) and testen='1' else ddr_rst;
ddrcomb: process(ddr_rst,sdi,request,frequest,start_tog,dr,wbrdata,testen,testoen)
variable dv: ddr_reg_type;
variable o: ddrctrl_out_type;
variable rbw: std_logic;
variable rbwd: std_logic_vector(2*(ddrbits+chkbits)-1 downto 0);
variable vstart, vstartd, vdone, incdone: std_logic;
variable vrctr: std_logic_vector(3 downto 0);
variable vreq,vreqf: ddr_request_type;
variable regsd1 : std_logic_vector(31 downto 0);
variable regsd2 : std_logic_vector(31 downto 0);
variable regsd3 : std_logic_vector(31 downto 0);
variable lastreadcmd: std_logic;
variable lastwrite : std_logic;
variable vmaskfirst, vmasklast: std_logic_vector(ddrbits/4-1 downto 0);
variable ea: std_logic_vector(3 downto 2);
variable inc_sdoaddr, inc_ramaddr: std_logic;
variable datavalid: std_logic;
variable vcsf: std_logic_vector(1 downto 0);
variable vrowf: std_logic_vector(14 downto 0);
variable vbankf: std_logic_vector(1 downto 0);
variable vcol,vcoladdr: std_logic_vector(14 downto 1);
variable seqin,seqout: std_logic_vector(3 downto 0);
variable regrdata: std_logic_vector(2*ddrbits-1 downto 0);
variable regad: std_logic_vector(2 downto 0);
variable wrdreg1,wrdreg2,wrdreg3: std_logic_vector(31 downto 0);
variable reqselv: std_logic_vector(3 downto 0);
begin
---------------------------------------------------------------------------
-- Init vars
---------------------------------------------------------------------------
dv := dr;
o := ddrctrl_out_none;
o.bdrive := '1'; o.qdrive := '1';
vdone := dr.resp.done_tog or dr.resp2.done_tog;
vrctr := dr.resp.rctr_gray or dr.resp2.rctr_gray;
incdone := '0';
lastreadcmd := '0';
lastwrite := '0';
reqselv := reqsel & reqsel & reqsel & reqsel;
-- Config registers
regsd1 := (others => '0');
regsd1(31 downto 15) := dr.cfg.refon & dr.cfg.trp(0) & dr.cfg.trfc(2 downto 0) &
dr.cfg.trcd & dr.cfg.bsize & dr.cfg.csize & dr.cfg.command &
dr.cfg.dllrst & dr.cfg.renable & dr.cfg.cke;
regsd1(11 downto 0) := dr.cfg.refresh;
regsd2 := (others => '0');
regsd2(8 downto 0) := conv_std_logic_vector(MHz, 9);
regsd2(14 downto 12) := conv_std_logic_vector(log2(ddrbits/8),3);
if mobile/=0 then regsd2(15):='1'; end if;-- Mobile DDR support
regsd2(19 downto 16) := conv_std_logic_vector(confapi, 4);
regsd3 := (others => '0');
regsd3(31) := dr.cfg.mobileen; -- Mobile DDR enable
regsd3(30) := dr.cfg.cl;
regsd3(24 downto 19) := dr.cfg.tcke & dr.cfg.txsr(3 downto 0) & dr.cfg.txp(0);
regsd3(18 downto 16) := dr.cfg.pmode;
regsd3( 7 downto 0) := dr.cfg.ds(2 downto 0) & dr.cfg.tcsr(1 downto 0)
& dr.cfg.pasr(2 downto 0);
-- Extended timing fields for DDR400
if ddr400 /= 0 then
regsd2(20) := '1'; -- Ext. fields available
regsd3(29 downto 28) := dr.cfg.tras;
regsd3(27 downto 26) := dr.cfg.txsr(5 downto 4);
regsd3(25) := dr.cfg.txp(1);
regsd3(11) := dr.cfg.twr;
regsd3(10) := dr.cfg.trp(1);
regsd3(9 downto 8) := dr.cfg.trfc(4 downto 3);
end if;
-- Data path
rbw := '0';
rbwd := (others => '0');
rbwd(ddrbits-1 downto 0) := sdi.data(ddrbits-1 downto 0);
rbwd(2*ddrbits+chkbits-1 downto ddrbits+chkbits) :=
sdi.data(2*ddrbits-1 downto ddrbits);
if chkbits > 0 then
rbwd(ddrbits+chkbits-1 downto ddrbits) := sdi.cb(chkbits-1 downto 0);
rbwd(2*(ddrbits+chkbits)-1 downto 2*ddrbits+chkbits) :=
sdi.cb(2*chkbits-1 downto chkbits);
end if;
dv.sdo_data(ddrbits-1 downto 0) := wbrdata(ddrbits-1 downto 0);
dv.sdo_data(2*ddrbits-1 downto ddrbits) :=
wbrdata(2*ddrbits+chkbits-1 downto ddrbits+chkbits);
dv.sdo_cb(chkbits) := '0'; -- dummy bit just to ensure length>0
if chkbits > 0 then
dv.sdo_cb(chkbits-1 downto 0) := wbrdata(ddrbits+chkbits-1 downto ddrbits);
dv.sdo_cb(2*chkbits-1 downto chkbits) :=
wbrdata(2*(ddrbits+chkbits)-1 downto 2*ddrbits+chkbits);
end if;
---------------------------------------------------------------------------
-- Request handling logic
---------------------------------------------------------------------------
-- Sync request inputs
dv.req1 := request;
dv.req2 := dr.req1;
dv.start1 := start_tog;
dv.start2 := dr.start1;
dv.start3 := dr.start2;
vstart := dr.start2;
vstartd := dr.start3;
vreq := dr.req2;
vreqf := dr.req1;
if nosync/=0 then
vstart:=start_tog;
vstartd:=start_tog;
vreq:=request;
vreqf:=request;
end if;
if nosync > 1 then
vreqf := frequest;
end if;
-- Address muxing
vcsf(0) := genmux(dr.cfg.bsize, vreqf.startaddr(30 downto 23));
vcsf(1) := not vcsf(0);
vbankf := genmux(dr.cfg.bsize, vreqf.startaddr(29 downto 22)) &
genmux(dr.cfg.bsize, vreqf.startaddr(28 downto 21));
case dr.cfg.csize is
when "00" => vrowf := vreqf.startaddr(19+l2ddrw downto 5+l2ddrw);
when "01" => vrowf := vreqf.startaddr(20+l2ddrw downto 6+l2ddrw);
when "10" => vrowf := vreqf.startaddr(21+l2ddrw downto 7+l2ddrw);
when others => vrowf := vreqf.startaddr(22+l2ddrw downto 8+l2ddrw);
end case;
vcol := vreq.startaddr(l2ddrw+10 downto l2ddrw-3);
-- vcoladdr==vcol when dr.ramaddr==lsb of vcol
vcoladdr := vcol(14 downto rbuf_wabits+1) & dr.ramaddr;
-- Generate data mask
-- Mask for 32-bit and larger bursts and single access
vmaskfirst := (others => '0');
vmasklast := (others => '0');
ea := vreq.endaddr(3 downto 2);
if vreq.hsize(1 downto 0)="11" then ea(2):='1'; end if;
if vreq.hsize(2)='1' then ea(3 downto 2):="11"; end if;
case ddrbits is
when 64 =>
-- 64-bit DDR width
case vreq.startaddr(3 downto 2) is
when "11" => vmaskfirst := "1111111111110000";
when "10" => vmaskfirst := "1111111100000000";
when "01" => vmaskfirst := "1111000000000000";
when others => vmaskfirst := "0000000000000000";
end case;
case ea(3 downto 2) is
when "11" => vmasklast := "0000000000000000";
when "10" => vmasklast := "0000000000001111";
when "01" => vmasklast := "0000000011111111";
when others => vmasklast := "0000111111111111";
end case;
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "1100110011001100";
else
vmaskfirst := vmaskfirst or "0011001100110011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "1010101010101010";
else
vmaskfirst := vmaskfirst or "0101010101010101";
end if;
end if;
when 32 =>
-- 32-bit DDR width
case vreq.startaddr(2) is
when '1' => vmaskfirst := "11110000";
when others => vmaskfirst := "00000000";
end case;
case ea(2) is
when '1' => vmasklast := "00000000";
when others => vmasklast := "00001111";
end case;
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "11001100";
else
vmaskfirst := vmaskfirst or "00110011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "10101010";
else
vmaskfirst := vmaskfirst or "01010101";
end if;
end if;
when others =>
-- 16-bit DDR width
if vreq.hsize(2 downto 1)="00" then
if vreq.startaddr(1)='1' then
vmaskfirst := vmaskfirst or "1100";
else
vmaskfirst := vmaskfirst or "0011";
end if;
end if;
if vreq.hsize="000" then
if vreq.startaddr(0)='1' then
vmaskfirst := vmaskfirst or "1010";
else
vmaskfirst := vmaskfirst or "0101";
end if;
end if;
end case;
-- Register read/write data muxing
regrdata := (others => '0');
case ddrbits is
when 64 =>
regad := vreq.startaddr(4 downto 2);
regrdata := regsd1 & regsd2 & regsd3 & x"00000000";
if confapi /= 0 and regad(2)='1' then
regrdata(95 downto 32) := dr.cfg.conf(31 downto 0) & dr.cfg.conf(63 downto 32);
end if;
wrdreg1 := wbrdata(128+chkbits-1 downto 96+chkbits);
wrdreg2 := wbrdata(96+chkbits-1 downto 64+chkbits);
wrdreg3 := wbrdata(63 downto 32);
when 32 =>
regad := dr.ramaddr(1 downto 0) & vreq.startaddr(2);
if regad(1)='0' then
regrdata := regsd1 & regsd2;
if confapi /= 0 and regad(2)='1' then
regrdata := regsd1 & dr.cfg.conf(31 downto 0);
end if;
else
regrdata := regsd3 & regsd2;
if confapi /= 0 and regad(2)='1' then
regrdata := dr.cfg.conf(63 downto 0);
end if;
end if;
wrdreg1 := wbrdata(64+chkbits-1 downto 32+chkbits);
wrdreg2 := wbrdata(31 downto 0);
wrdreg3 := wbrdata(64+chkbits-1 downto 32+chkbits);
when others =>
regad := dr.ramaddr(2 downto 0);
case regad is
when "000"|"100" => regrdata := regsd1;
when "001" => regrdata := regsd2;
when "010" => regrdata := regsd3;
when "101" =>
if confapi /= 0 then
regrdata := dr.cfg.conf(31 downto 0);
else
regrdata := regsd2;
end if;
when "110" =>
if confapi /= 0 then
regrdata := dr.cfg.conf(63 downto 32);
else
regrdata := regsd3;
end if;
when others => regrdata := regsd3;
end case;
wrdreg1 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
wrdreg2 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
wrdreg3 := wbrdata(31+chkbits downto 16+chkbits) & wbrdata(15 downto 0);
end case;
---------------------------------------------------------------------------
-- Main DDR-SDRAM access FSM
---------------------------------------------------------------------------
dv.sdo_ck := "111";
dv.sdo_rasn := '1';
dv.sdo_casn := '1';
dv.sdo_wen := '1';
dv.sdo_dqm := (others => '1');
dv.sdo_bdrive := '1';
dv.sdo_qdrive := '1';
inc_sdoaddr := '0';
inc_ramaddr := '0';
dv.readpipe := dr.readpipe(3+readdly downto 0) & '0';
datavalid := '0';
if hasdqvalid/=0 then
datavalid := sdi.datavalid;
if dr.s/=dsrd1 and dr.s/=dsrd2 and dr.s/=dsrd3 and dr.s/=dsrd4 and dr.s/=dssrr2 then
datavalid := '0';
end if;
end if;
if hasdqvalid=0 then
if dr.cfg.cl='0' then
datavalid := dr.readpipe(3+readdly);
else
datavalid := dr.readpipe(4+readdly);
end if;
end if;
if datavalid='1' and dr.s/=dsidle then
inc_ramaddr := '1';
rbw := '1';
vrctr(l2ddr_burstlen-1 downto 0) :=
nextgray(vrctr(l2ddr_burstlen-1 downto 0));
if dr.ramaddr=onev(dr.ramaddr'length-1 downto 0) then
dv.readdone := '1';
incdone:='1';
vrctr := "0000";
end if;
end if;
if dr.sdo_address((l2blen-l2ddrw) downto 1)=onev((l2blen-l2ddrw) downto 1) then
lastreadcmd := '1';
end if;
if dr.ramaddr=vreq.endaddr((l2blen-3)-1 downto (l2ddrw-3)) then
lastwrite := '1';
end if;
-- Update EMR when ds, tcsr or pasr change
if dr.cfg.command="000" and
( dr.cfg.ds(2 downto 0) /= dr.cfg.ds(5 downto 3) or
dr.cfg.tcsr(1 downto 0) /= dr.cfg.tcsr(3 downto 2) or
dr.cfg.pasr(2 downto 0) /= dr.cfg.pasr(5 downto 3) ) then
dv.cfg.command := "111";
end if;
-- Auto-refresh counter
dv.refctr := std_logic_vector(unsigned(dr.refctr)+1);
if (dr.refctr(11 downto 0)=dr.cfg.refresh and dr.cfg.refon='1') then
dv.refpend := '1';
dv.refctr := (others => '0');
end if;
if dr.initstate/=disrstdel and (dr.cfg.refon='0' or dr.cfg.pmode(1)='1') then
dv.refpend := '0';
dv.refctr := (others => '0');
end if;
dv.idlectr := "0000";
dv.pdowns(0) := '0';
if not (dr.cmdctr=(dr.cmdctr'range => '0')) and dr.pdowns(0)='0' then
dv.cmdctr := std_logic_vector(unsigned(dr.cmdctr)-1);
end if;
case dr.s is
when dsidle =>
vrctr := "0000";
dv.sdo_ck := "111";
if dr.cfg.pmode /= "000" then
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
dv.sdo_csn := "11";
if dr.refpend='1' then
dv.sdo_csn := "00";
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.s := dsref1;
dv.refpend := '0';
elsif vstart /= vdone and dr.cfg.renable='0' then
-- Transfer
dv.sdo_csn := vcsf;
dv.sdo_address := vrowf;
dv.sdo_ba := vbankf;
dv.sdo_rasn := '0' or vreqf.hio;
dv.s := dsact1;
elsif dr.cfg.command /= "000" then
dv.s := dscmd1;
elsif dr.idlectr="1111" then
dv.s := dspdown1;
end if;
when dsact1 =>
dv.ramaddr := vcol(rbuf_wabits downto 1);
if ddr400 /= 0 then
dv.cmdctr(2 downto 0) := "1" & dr.cfg.tras; -- t(RAS)-2t(CK) = TRAS+6-2 = TRAS+4
else
dv.cmdctr(2 downto 0) := "10" & dr.cfg.trcd;
end if;
dv.readdone := '0';
if dr.cfg.trcd='1' then
dv.s := dsact2;
else
dv.s := dsact3;
end if;
if vreq.hio='1' then
dv.s := dsreg1;
end if;
when dsact2 =>
dv.s := dsact3;
when dsact3 =>
dv.sdo_casn := '0';
dv.sdo_wen := not vreq.hwrite;
dv.sdo_qdrive := not vreq.hwrite;
-- dv.sdo_address := vcol(12 downto 10) & '0' & vcol(9 downto 1) & '0';
-- Since part of column is stored in ramaddr in dsact1, use that to
-- reduce fanout on vreq.startaddr
dv.sdo_address := vcoladdr(13 downto 10) & '0' & vcoladdr(9 downto 1) & '0';
if vreq.hwrite='1' then
dv.s := dswr1;
else
dv.s := dsrd1;
dv.readpipe(0) := '1';
end if;
when dswr1 =>
-- NOP,NOP,[WR]: issue either WR+D or NOP+D
dv.sdo_bdrive := '0';
dv.sdo_qdrive := '0';
inc_sdoaddr := '1';
inc_ramaddr := '1';
if lastwrite='1' then
dv.sdo_dqm := vmaskfirst or vmasklast;
dv.s := dswr3;
else
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.sdo_dqm := vmaskfirst;
dv.s := dswr2;
end if;
when dswr2 =>
dv.sdo_dqm := (others => '0');
dv.sdo_bdrive := '0';
dv.sdo_qdrive := '0';
inc_sdoaddr := '1';
inc_ramaddr := '1';
if lastwrite='0' then
dv.sdo_casn := '0';
dv.sdo_wen := '0';
else
dv.s := dswr3;
dv.sdo_dqm := vmasklast;
end if;
when dswr3 =>
-- ...,WR+D,WR+D,[NOP+D]: issue NOP
dv.sdo_qdrive := '0';
dv.sdo_dqm := (others => '1');
dv.s := dswr4;
incdone := '1';
when dswr4 =>
-- Issue more NOP:s to meet tWR
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
if dr.idlectr(0)=dr.cfg.twr then
dv.s := dswr5;
end if;
when dswr5 =>
-- Issue NOP:s until tRAS met.
if dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dswr6;
end if;
when dswr6 =>
-- PRE: issue one or two NOP:s depending on trp setting
if dr.idlectr(1 downto 0)=dr.cfg.trp then
dv.s := dsidle;
else
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
when dsrd1 =>
inc_sdoaddr := '1';
if lastreadcmd='0' then
dv.sdo_casn := '0';
dv.readpipe(0):='1';
elsif dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dsrd3;
else
dv.s := dsrd2;
end if;
when dsrd2 =>
if dr.cmdctr(2 downto 0)="000" then
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.s := dsrd3;
end if;
when dsrd3 =>
if dr.idlectr(1 downto 0)=dr.cfg.trp then
if dv.readdone='1' then
dv.s := dsidle;
else
dv.s := dsrd4;
end if;
else
dv.idlectr := std_logic_vector(unsigned(dr.idlectr)+1);
end if;
when dsrd4 =>
if dv.readdone='1' then
dv.s := dsidle;
end if;
when dsreg1 =>
rbw := '1';
rbwd(2*ddrbits+chkbits-1 downto ddrbits+chkbits) := regrdata(2*ddrbits-1 downto ddrbits);
rbwd(ddrbits-1 downto 0) := regrdata(ddrbits-1 downto 0);
if vreq.hwrite='1' then
dv.s := dsreg2;
elsif regad="100" and dr.cfg.mobileen='1' then
dv.sdo_address := (others => '0');
dv.sdo_ba := "01";
dv.sdo_csn := "10";
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.s := dssrr1;
dv.cmdctr(0) := '1';
null;
else
incdone := '1';
dv.s := dsidle;
end if;
when dsreg2 =>
case regad is
when "000" =>
dv.cfg.refon := wrdreg1(31);
dv.cfg.trp(0) := wrdreg1(30);
dv.cfg.trfc(2 downto 0) := wrdreg1(29 downto 27);
dv.cfg.trcd := wrdreg1(26);
dv.cfg.bsize := wrdreg1(25 downto 23);
dv.cfg.csize := wrdreg1(22 downto 21);
dv.cfg.command := wrdreg1(20 downto 18);
dv.cfg.dllrst := wrdreg1(17);
dv.cfg.renable := wrdreg1(16);
dv.cfg.cke := wrdreg1(15);
dv.cfg.refresh := wrdreg1(11 downto 0);
when "010" =>
dv.cfg.mobileen := wrdreg3(31);
dv.cfg.cl := wrdreg3(30);
dv.cfg.tcke := wrdreg3(24);
dv.cfg.txsr(3 downto 0) := wrdreg3(23 downto 20);
dv.cfg.txp(0) := wrdreg3(19);
dv.cfg.pmode := wrdreg3(18 downto 16);
dv.cfg.ds (5 downto 3) := wrdreg3(7 downto 5);
dv.cfg.tcsr(3 downto 2) := wrdreg3(4 downto 3);
dv.cfg.pasr(5 downto 3) := wrdreg3(2 downto 0);
-- Extended DDR400 fields
dv.cfg.tras := wrdreg3(29 downto 28);
dv.cfg.txsr(5 downto 4) := wrdreg3(27 downto 26);
dv.cfg.txp(1) := wrdreg3(25);
dv.cfg.twr := wrdreg3(11);
dv.cfg.trp(1) := wrdreg3(10);
dv.cfg.trfc(4 downto 3) := wrdreg3(9 downto 8);
when "101" =>
if confapi /= 0 then
dv.cfg.conf(31 downto 0) := wrdreg2;
end if;
when "110" =>
if confapi /= 0 then
dv.cfg.conf(63 downto 32) := wrdreg3;
end if;
when others =>
null;
end case;
incdone := '1';
dv.s := dsidle;
when dscmd1 =>
dv.sdo_csn := (others => '0');
dv.sdo_address(10) := '1';
dv.cfg.command := "000";
dv.s := dscmd2;
case dr.cfg.command is
when "010" => -- PRECHARGE ALL
dv.sdo_rasn := '0';
dv.sdo_wen := '0';
dv.cmdctr(1 downto 0) := "11";
when "100" => -- AUTO-REFRESH
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.cmdctr(4 downto 0) := dr.cfg.trfc;
when "110" => -- MODE REGISTER
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
dv.sdo_ba := "00";
dv.sdo_address := "00000000" & "01" & dr.cfg.cl & "0001";
if dr.cfg.mobileen='0' then
dv.sdo_address(8) := dr.cfg.dllrst;
end if;
if dr.cfg.dllrst='1' then
dv.cmdctr := std_logic_vector(to_unsigned(200,dr.cmdctr'length));
end if;
when "111" => -- EXT. MODE REGISTER
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
dv.sdo_wen := '0';
if dr.cfg.mobileen='1' then
dv.sdo_ba := "10";
dv.sdo_address := "0000000" & dr.cfg.ds(5 downto 3) & dr.cfg.tcsr(3 downto 2)
& dr.cfg.pasr(5 downto 3);
else
dv.sdo_ba := "01";
dv.sdo_address := "000000000000000"; -- bit0=0 -> DLL enable
end if;
dv.cfg.pasr(2 downto 0) := dr.cfg.pasr(5 downto 3);
dv.cfg.ds(2 downto 0) := dr.cfg.ds(5 downto 3);
dv.cfg.tcsr(1 downto 0) := dr.cfg.tcsr(3 downto 2);
when others => null;
end case;
when dscmd2 =>
if dr.cmdctr=(dr.cmdctr'range => '0') then
dv.s := dsidle;
end if;
when dspdown1 =>
dv.sdo_csn := "00";
if dr.cfg.pmode(0)='1' or dr.cfg.pmode(1)='1' then
dv.cfg.cke := '0';
end if;
if dr.cfg.pmode(1)='1' then
dv.sdo_rasn := '0';
dv.sdo_casn := '0';
end if;
if dr.cfg.pmode(2)='1' and dr.cfg.pmode(0)='1' then
dv.sdo_wen := '0';
end if;
if dr.cfg.pmode(0)='1' then
dv.cmdctr(1 downto 0) := dr.cfg.txp;
end if;
if dr.cfg.pmode(1)='1' then
if dr.cfg.mobileen='1' then
dv.cmdctr(5 downto 0) := dr.cfg.txsr;
else
dv.cmdctr(7 downto 0) := std_logic_vector(to_unsigned(200,8));
end if;
end if;
dv.pdowns(1) := '0';
dv.s := dspdown2;
when dspdown2 =>
dv.pdowns(0) := '1';
if dr.pdowns(0)='0' and dr.cmdctr=(dr.cmdctr'range => '0') then
dv.pdowns(1):='1';
end if;
if dr.cfg.pmode(2)='1' and dr.cfg.pmode(0)='0' then
dv.sdo_ck := "000";
end if;
if dr.cfg.pmode(1)='1' then
dv.refpend := '1';
end if;
if (dr.refpend='1' and dr.cfg.pmode(1)='0') or vstart /= vdone then
if (dr.pdowns(0) or not dr.cfg.tcke)='1' then
dv.cfg.cke := '1';
if dr.pdowns(1)='1' then
dv.s := dsidle;
else
dv.s := dscmd2;
dv.pdowns(0) := '0';
end if;
end if;
end if;
when dsref1 =>
dv.s := dscmd2;
dv.cmdctr(4 downto 0) := dr.cfg.trfc;
when dssrr1 =>
if dr.cmdctr(0)='0' then
dv.sdo_casn := '0';
dv.readpipe(0):='1';
dv.s := dssrr2;
end if;
when dssrr2 =>
if datavalid='1' then
incdone := '1';
dv.s := dsidle;
end if;
end case;
if inc_sdoaddr='1' then
dv.sdo_address(l2blen-l2ddrw downto 1) :=
std_logic_vector(unsigned(dr.sdo_address(l2blen-l2ddrw downto 1))+1);
end if;
if inc_ramaddr='1' then
dv.ramaddr := std_logic_vector(unsigned(dr.ramaddr)+1);
end if;
-- Update the done flags
dv.resp.done_tog := (dr.resp.done_tog xor incdone) and (not reqsel);
dv.resp.rctr_gray := vrctr and (not reqselv);
dv.resp2.done_tog := (dr.resp2.done_tog xor incdone) and reqsel;
dv.resp2.rctr_gray := vrctr and reqselv;
---------------------------------------------------------------------------
-- DDR Init Sequence FSM
---------------------------------------------------------------------------
-- Command sequence lookup table
seqin := dr.cfg.mobileen & dr.initpos;
case seqin is
-- Mobile DDR
when "1100" => seqout := "0010"; -- PRECHARGE ALL
when "1011" => seqout := "0100"; -- AUTO REFRESH #1
when "1010" => seqout := "0100"; -- AUTO REFRESH #2
when "1001" => seqout := "0110"; -- MODE REG
when "1000" => seqout := "0111"; -- EXT MODE REG
-- Normal DDR
when "0110" => seqout := "0010"; -- PRECHARGE ALL
when "0101" => seqout := "0111"; -- EXT MODE REG En DLL
when "0100" => seqout := "1110"; -- MODE REG Rst DLL
when "0011" => seqout := "0010"; -- PRECHARGE ALL
when "0010" => seqout := "0100"; -- AUTO REFRESH #1
when "0001" => seqout := "0100"; -- AUTO REFRESH #2
when "0000" => seqout := "0110"; -- MODE REG NoRst DLL
when others => seqout := "0000";
end case;
case dr.initstate is
when disrstdel =>
if dr.refctr=std_logic_vector(to_unsigned(MHz*rstdel,dr.refctr'length)) then
dv.initstate := disidle;
if pwron=0 then dv.cfg.renable:='0'; end if;
end if;
-- Bypass reset delay by writing anything to regsd2
if vstartd='1' and (vreq.hio='1' and vreq.hwrite='1' and vreq.endaddr(4 downto 2)="001") then
dv.initstate := disidle;
if pwron=0 then dv.cfg.renable:='0'; end if;
end if;
when disidle =>
if dr.cfg.renable='1' then
dv.cfg.cke := '1';
if dr.cfg.cke='1' then
dv.initpos := "111";
dv.initstate := disrun;
end if;
end if;
when disrun =>
if dr.cfg.command="000" then
dv.cfg.dllrst := seqout(3);
dv.cfg.command := seqout(2 downto 0);
dv.initpos := std_logic_vector(unsigned(dr.initpos)-1);
if dr.initpos="000" then
dv.initstate := disfinished;
end if;
end if;
when disfinished =>
if dr.cfg.command="000" then
dv.cfg.renable := '0';
dv.cfg.refon := '1';
dv.initstate := disidle;
end if;
end case;
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
if ddr_rst='0' then
dv.s := dsidle;
dv.cmdctr := (others => '0');
dv.refctr := (others => '0');
dv.resp := ddr_response_none;
dv.resp2 := ddr_response_none;
dv.initstate := disrstdel;
dv.refpend := '0';
-- Reset cfg record
dv.cfg.command := "000";
dv.cfg.csize := conv_std_logic_vector(col-9, 2);
dv.cfg.bsize := conv_std_logic_vector(log2(Mbyte/8), 3);
dv.cfg.refon := '0';
dv.cfg.refresh := conv_std_logic_vector(7800*MHz/1000, 12);
dv.cfg.dllrst := '0';
dv.cfg.pasr := (others => '0');
dv.cfg.tcsr := (others => '0');
dv.cfg.ds := (others => '0');
dv.cfg.pmode := (others => '0');
dv.cfg.txsr := conv_std_logic_vector(120*MHz/1000, 6);
dv.cfg.txp := "01";
dv.cfg.cl := '0'; -- CL = 3/2 -- ****
dv.cfg.tcke := '1';
if MHz > 100 then
dv.cfg.trcd := '1';
else dv.cfg.trcd := '0';
end if;
if MHz > 100 then
dv.cfg.trp := "01";
else dv.cfg.trp := "00";
end if;
dv.cfg.renable := '1'; -- Updated in disrstdel state
if mobile >= 2 then
dv.cfg.mobileen := '1'; -- Default: Mobile DDR
else dv.cfg.mobileen := '0';
end if;
if mobile >= 2 then
dv.cfg.trfc := conv_std_logic_vector(98*MHz/1000-2, 5);
else dv.cfg.trfc := conv_std_logic_vector(75*MHz/1000-2, 5);
end if;
if ddr_syncrst /= 0 then
dv.sdo_ck := "000";
if mobile >= 2 then
dv.cfg.cke := '1';
else dv.cfg.cke := '0';
end if;
end if;
if confapi /= 0 then
dv.cfg.conf(31 downto 0) := conv_std_logic_vector(conf0, 32); --x"0000A0A0";
dv.cfg.conf(63 downto 32) := conv_std_logic_vector(conf1, 32); --x"00060606";
else
dv.cfg.conf := (others => '0');
end if;
if MHz > 175 then
dv.cfg.tras := "10";
elsif MHz > 150 then
dv.cfg.tras := "01";
else
dv.cfg.tras := "00";
end if;
if MHz > 133 then
dv.cfg.twr := '1';
else
dv.cfg.twr := '0';
end if;
dv.sdo_csn := "11";
dv.sdo_dqm := (others => '1');
dv.sdo_wen := '1';
dv.sdo_rasn := '1';
dv.sdo_casn := '1';
-- Extra reset for X-sensitive techs
dv.ramaddr := (others => '0');
end if;
---------------------------------------------------------------------------
-- Static logic/forced regs, etc
---------------------------------------------------------------------------
-- Force mobile disable/enabled
if mobile=0 then dv.cfg.mobileen := '0'; end if;
if mobile=3 then dv.cfg.mobileen := '1'; end if;
if mobile=0 then
dv.cfg.pasr := (others => '0');
dv.cfg.tcsr := (others => '0');
dv.cfg.ds := (others => '0');
dv.cfg.pmode := (others => '0');
dv.cfg.txp := "00";
dv.cfg.txsr := (others => '0');
dv.cfg.tcke := '0';
end if;
if ddr400=0 then
dv.cfg.tras := "00";
dv.cfg.txsr(5 downto 4) := "00";
dv.cfg.txp(1) := '0';
dv.cfg.trp(1) := '0';
dv.cfg.trfc(4 downto 3) := "00";
dv.cfg.twr := '0';
end if;
-- Assign sdo
o.bdrive := '1'; o.qdrive := '1'; --Temp.
o.sdck := dr.sdo_ck;
if ddr_syncrst/=0 and phyptctrl/=0 then
o.sdck := o.sdck and (o.sdck'range => ddr_rst);
end if;
if regoutput /= 0 then
o.casn := dr.sdo_casn;
o.rasn := dr.sdo_rasn;
o.sdwen := dr.sdo_wen;
o.sdcsn := dr.sdo_csn;
o.ba := '0' & dr.sdo_ba;
o.address := dr.sdo_address;
o.sdcke := (others => dr.cfg.cke);
if ddr_syncrst /= 0 and phyptctrl /= 0 then
if ddr_rst='0' then
if mobile >= 2 then o.sdcke := (others => '1');
else o.sdcke := (others => '0');
end if;
end if;
end if;
o.data(2*ddrbits-1 downto 0) := dr.sdo_data;
o.dqm(ddrbits/4-1 downto 0) := dr.sdo_dqm;
if chkbits > 0 then
o.cb(2*chkbits-1 downto 0) := dr.sdo_cb(2*chkbits-1 downto 0);
end if;
o.bdrive := dr.sdo_bdrive;
o.qdrive := dr.sdo_qdrive;
else
o.casn := dv.sdo_casn;
o.rasn := dv.sdo_rasn;
o.sdwen := dv.sdo_wen;
o.sdcsn := dv.sdo_csn;
o.ba := '0' & dv.sdo_ba;
o.address := dv.sdo_address;
o.sdcke := (others => dv.cfg.cke);
o.data(2*ddrbits-1 downto 0) := dv.sdo_data;
o.dqm(ddrbits/4-1 downto 0) := dv.sdo_dqm;
if chkbits > 0 then
o.cb(2*chkbits-1 downto 0) := dv.sdo_cb(2*chkbits-1 downto 0);
end if;
o.bdrive := dv.sdo_bdrive;
o.qdrive := dv.sdo_qdrive;
end if;
for x in 7 downto 0 loop
o.cbdqm(x) := o.dqm(2*x);
end loop;
-- Diag access
if vreq.maskcb='1' then
o.cbdqm := (others => '1');
end if;
if vreq.maskdata='1' then
o.dqm := (others => '1');
end if;
if scantest/=0 and phyptctrl/=0 then
if testen='1' then
o.bdrive := testoen;
o.qdrive := testoen;
end if;
end if;
---------------------------------------------------------------------------
-- Drive outputs
---------------------------------------------------------------------------
ndr <= dv;
sdo <= o;
response <= dr.resp;
response2 <= dr.resp2;
rbwrite <= rbw;
rbwaddr <= dr.ramaddr;
rbwdata <= rbwd;
wbraddr <= vdone & dv.ramaddr;
end process;
ddrregs: process(clk_ddr,arst)
begin
if rising_edge(clk_ddr) then
dr <= ndr;
end if;
if ddr_syncrst=0 and arst='0' then
dr.sdo_ck <= "000";
if mobile >= 2 then
dr.cfg.cke <= '1';
else dr.cfg.cke <= '0';
end if;
end if;
end process;
end;
| gpl-2.0 | fade51ceee157af58c1ef1bba8f4b24f | 0.50867 | 3.521266 | false | false | false | false |
JimLewis/OSVVM | TbUtilPkg.vhd | 1 | 37,308 | --
-- File Name: TbUtilPkg.vhd
-- Design Unit Name: TbUtilPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Package Defines
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2021 2021.02 Added AckType, RdyType, RequestTransaction, WaitForTransaction for AckType/RdyType
-- 12/2020 2020.12 Added IfElse functions for string and integer.
-- Added Increment function for integer
-- 01/2020 2020.01 Updated Licenses to Apache
-- 08/2018 2018.08 Updated WaitForTransaction to allow 0 time transactions
-- 04/2018 2018.04 Added RequestTransaction, WaitForTransaction, Toggle, WaitForToggle for bit.
-- Added Increment and WaitForToggle for integer.
-- 11/2016 2016.11 First Public Release Version
-- Updated naming for consistency.
-- 10/2013 2013.10 Split out Text Utilities
-- 11/1999: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 1999 - 2021 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
library osvvm ;
use osvvm.AlertLogPkg.all ;
use osvvm.TranscriptPkg.all ;
use osvvm.ResolutionPkg.all ;
package TbUtilPkg is
constant CLK_ACTIVE : std_logic := '1' ;
constant t_sim_resolution : time := std.env.resolution_limit ; -- VHDL-2008
-- constant t_sim_resolution : time := 1 ns ; -- for non VHDL-2008 simulators
------------------------------------------------------------
-- ZeroOneHot, OneHot
-- OneHot: return true if exactly one value is 1
-- ZeroOneHot: return false when more than one value is a 1
------------------------------------------------------------
function OneHot ( constant A : in std_logic_vector ) return boolean ;
function ZeroOneHot ( constant A : in std_logic_vector ) return boolean ;
------------------------------------------------------------
-- IfElse
-- Crutch until VHDL-2019 conditional initialization
-- If condition is true return first parameter otherwise return second
------------------------------------------------------------
function IfElse(Expr : boolean ; A, B : std_logic_vector) return std_logic_vector ;
function IfElse(Expr : boolean ; A, B : integer) return integer ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- RequestTransaction - Transaction initiation in transaction procedure
-- WaitForTransaction - Transaction execution control in VC
------------------------------------------------------------
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- std_logic
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out std_logic ;
signal Ack : In std_logic
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- bit
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out bit ;
signal Ack : In bit
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In bit ;
signal Ack : Out bit
) ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- integer
------------------------------------------------------------
subtype RdyType is resolved_max integer range 0 to integer'high ;
subtype AckType is resolved_max integer range -1 to integer'high ;
procedure RequestTransaction (
signal Rdy : InOut RdyType ;
signal Ack : In AckType
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In RdyType ;
signal Ack : InOut AckType
) ;
------------------------------------------------------------
-- WaitForTransaction
-- Specializations for interrupt handling
-- Currently only std_logic based
------------------------------------------------------------
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic ;
signal TimeOut : In std_logic ;
constant Polarity : In std_logic := '1'
) ;
-- Variation for model that stops waiting when IntReq is asserted
-- Intended for models that need to switch between instruction streams
-- such as a CPU when interrupt is pending
procedure WaitForTransactionOrIrq (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal IntReq : In std_logic
) ;
-- Set Ack to Model starting value
procedure StartTransaction ( signal Ack : Out std_logic ) ;
-- Set Ack to Model finishing value
procedure FinishTransaction ( signal Ack : Out std_logic ) ;
-- If a transaction is pending, return true
function TransactionPending ( signal Rdy : In std_logic ) return boolean ;
-- Variation for clockless models
procedure WaitForTransaction (
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) ;
------------------------------------------------------------
-- Toggle, WaitForToggle
-- Used for communicating between processes
------------------------------------------------------------
procedure Toggle (
signal Sig : InOut std_logic ;
constant DelayVal : time
) ;
procedure Toggle ( signal Sig : InOut std_logic ) ;
procedure ToggleHS ( signal Sig : InOut std_logic ) ;
function IsToggle ( signal Sig : In std_logic ) return boolean ;
procedure WaitForToggle ( signal Sig : In std_logic ) ;
-- Bit type versions
procedure Toggle ( signal Sig : InOut bit ; constant DelayVal : time ) ;
procedure Toggle ( signal Sig : InOut bit ) ;
procedure ToggleHS ( signal Sig : InOut bit ) ;
function IsToggle ( signal Sig : In bit ) return boolean ;
procedure WaitForToggle ( signal Sig : In bit ) ;
-- Integer type versions
procedure Increment ( signal Sig : InOut integer ; constant RollOverValue : in integer := 0) ;
function Increment (constant Sig : in integer ; constant Amount : in integer := 1) return integer ;
procedure WaitForToggle ( signal Sig : In integer ) ;
------------------------------------------------------------
-- WaitForBarrier
-- Barrier Synchronization
-- Multiple processes call it, it finishes when all have called it
------------------------------------------------------------
procedure WaitForBarrier ( signal Sig : InOut std_logic ) ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; constant TimeOut : time ) ;
-- resolved_barrier : summing resolution used in conjunction with integer based barriers
function resolved_barrier ( s : integer_vector ) return integer ;
subtype integer_barrier is resolved_barrier integer ;
-- Usage of integer barriers requires resolved_barrier. Initialization to 1 recommended, but not required
-- signal barrier1 : resolved_barrier integer := 1 ; -- using the resolution function
-- signal barrier2 : integer_barrier := 1 ; -- using the subtype that already applies the resolution function
procedure WaitForBarrier ( signal Sig : InOut integer ) ;
procedure WaitForBarrier ( signal Sig : InOut integer ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') ;
procedure WaitForBarrier ( signal Sig : InOut integer ; constant TimeOut : time ) ;
-- Using separate signals
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncIn : in std_logic ) ;
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncInV : in std_logic_vector ) ;
------------------------------------------------------------
-- WaitForClock
-- Sync to Clock - after a delay, after a number of clocks
------------------------------------------------------------
procedure WaitForClock ( signal Clk : in std_logic ; constant Delay : in time ) ;
procedure WaitForClock ( signal Clk : in std_logic ; constant NumberOfClocks : in integer := 1) ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in boolean ) ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in std_logic ; constant Polarity : std_logic := '1' ) ;
------------------------------------------------------------
-- WaitForLevel
-- Find a signal at a level
------------------------------------------------------------
procedure WaitForLevel ( signal A : in boolean ) ;
procedure WaitForLevel ( signal A : in std_logic ; Polarity : std_logic := '1' ) ;
------------------------------------------------------------
-- CreateClock, CreateReset
-- Note these do not exit
------------------------------------------------------------
procedure CreateClock (
signal Clk : inout std_logic ;
constant Period : time ;
constant DutyCycle : real := 0.5
) ;
procedure CheckClockPeriod (
constant AlertLogID : AlertLogIDType ;
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) ;
procedure CheckClockPeriod (
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) ;
procedure CreateReset (
signal Reset : out std_logic ;
constant ResetActive : in std_logic ;
signal Clk : in std_logic ;
constant Period : time ;
constant tpd : time
) ;
procedure LogReset (
constant AlertLogID : AlertLogIDType ;
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) ;
procedure LogReset (
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) ;
------------------------------------------------------------
-- Deprecated subprogram names
-- Maintaining backward compatibility using aliases
------------------------------------------------------------
-- History of RequestTransaction / WaitForTransaction
alias RequestAction is RequestTransaction [std_logic, std_logic] ;
alias WaitForRequest is WaitForTransaction [std_logic, std_logic, std_logic] ;
-- History of WaitForToggle
alias WaitOnToggle is WaitForToggle [std_logic] ;
-- History of WaitForBarrier
alias WayPointBlock is WaitForBarrier [std_logic] ;
alias SyncTo is WaitForBarrier2[std_logic, std_logic] ;
alias SyncTo is WaitForBarrier2[std_logic, std_logic_vector] ;
-- Backward compatible name
alias SyncToClk is WaitForClock [std_logic, time] ;
------------------------------------------------------------
-- Deprecated
-- WaitForAck, StrobeAck
-- Replaced by WaitForToggle and Toggle
------------------------------------------------------------
procedure WaitForAck ( signal Ack : In std_logic ) ;
procedure StrobeAck ( signal Ack : Out std_logic ) ;
end TbUtilPkg ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body TbUtilPkg is
------------------------------------------------------------
-- ZeroOneHot, OneHot
-- OneHot: return true if exactly one value is 1
-- ZeroOneHot: return false when more than one value is a 1
------------------------------------------------------------
function OneHot ( constant A : in std_logic_vector ) return boolean is
variable found_one : boolean := FALSE ;
begin
for i in A'range loop
if A(i) = '1' or A(i) = 'H' then
if found_one then
return FALSE ;
end if ;
found_one := TRUE ;
end if ;
end loop ;
return found_one ; -- found a one
end function OneHot ;
function ZeroOneHot ( constant A : in std_logic_vector ) return boolean is
variable found_one : boolean := FALSE ;
begin
for i in A'range loop
if A(i) = '1' or A(i) = 'H' then
if found_one then
return FALSE ;
end if ;
found_one := TRUE ;
end if ;
end loop ;
return TRUE ; -- all zero or found a one
end function ZeroOneHot ;
------------------------------------------------------------
-- IfElse
-- Crutch until VHDL-2019 conditional initialization
-- If condition is true return first parameter otherwise return second
------------------------------------------------------------
function IfElse(Expr : boolean ; A, B : std_logic_vector) return std_logic_vector is
begin
if Expr then
return A ;
else
return B ;
end if ;
end function IfElse ;
function IfElse(Expr : boolean ; A, B : integer) return integer is
begin
if Expr then
return A ;
else
return B ;
end if ;
end function IfElse ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- RequestTransaction - Transaction initiation in transaction procedure
-- WaitForTransaction - Transaction execution control in VC
------------------------------------------------------------
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- std_logic
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out std_logic ;
signal Ack : In std_logic
) is
begin
-- Record contains new transaction
Rdy <= '1' ;
-- Find Ack low = '0'
wait until Ack = '0' ;
-- Prepare for Next Transaction
Rdy <= '0' ;
-- Transaction Done
wait until Ack = '1' ;
end procedure RequestTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
end if ;
-- align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- Allow transactions without time passing
end procedure WaitForTransaction ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- bit
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out bit ;
signal Ack : In bit
) is
begin
-- Record contains new transaction
Rdy <= '1' ;
-- Find Ack low = '0'
wait until Ack = '0' ;
-- Prepare for Next Transaction
Rdy <= '0' ;
-- Transaction Done
wait until Ack = '1' ;
end procedure RequestTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In bit ;
signal Ack : Out bit
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
-- align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- Allow transactions without time passing
end procedure WaitForTransaction ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- integer
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : InOut RdyType ;
signal Ack : In AckType
) is
begin
-- Initiate Transaction Request
Rdy <= Increment(Rdy) ;
wait for 0 ns ;
-- Wait for Transaction Completion
wait until Rdy = Ack ;
end procedure RequestTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In RdyType ;
signal Ack : InOut AckType
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= Increment(Ack) ;
AckTime := NOW ;
-- Find Start of Transaction
wait until Ack /= Rdy ;
-- Align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
end procedure WaitForTransaction ;
------------------------------------------------------------
-- WaitForTransaction
-- Specializations for interrupt handling
-- Currently only std_logic based
------------------------------------------------------------
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic ;
signal TimeOut : In std_logic ;
constant Polarity : In std_logic := '1'
) is
variable AckTime : time ;
variable FoundRdy : boolean ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Ready or Time out
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if (Rdy /= '1' and TimeOut /= Polarity) then
wait until Rdy = '1' or TimeOut = Polarity ;
end if ;
FoundRdy := Rdy = '1' ;
-- align to clock if Rdy or TimeOut does not happen within delta cycles from Ack
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
if FoundRdy then
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- Allow transactions without time passing
end if ;
end procedure WaitForTransaction ;
-- Variation for model that stops waiting when IntReq is asserted
-- Intended for models that need to switch between instruction streams
-- such as a CPU when interrupt is pending
procedure WaitForTransactionOrIrq (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal IntReq : In std_logic
) is
variable AckTime : time ;
constant POLARITY : std_logic := '1' ;
begin
AckTime := NOW ;
-- Find Ready or Time out
wait for 0 ns ; -- allow Rdy from previous cycle to clear
if (Rdy /= '1' and IntReq /= POLARITY) then
wait until Rdy = '1' or IntReq = POLARITY ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
-- align to clock if Rdy or IntReq does not happen within delta cycles from Ack
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
end procedure ;
-- Set Ack to Model starting value
-- Pairs with WaitForTransactionOrIrq above
procedure StartTransaction ( signal Ack : Out std_logic ) is
begin
Ack <= '0' ;
wait for 0 ns ; -- Allow transactions without time passing
end procedure StartTransaction ;
-- Set Ack to Model finishing value
-- Pairs with WaitForTransactionOrIrq above
procedure FinishTransaction ( signal Ack : Out std_logic ) is
begin
-- End of Cycle
Ack <= '1' ;
wait for 0 ns ; -- Allow Ack to update
end procedure FinishTransaction ;
-- If a transaction is pending, return true
-- Used to detect presence of transaction stream,
-- such as an interrupt handler
function TransactionPending (
signal Rdy : In std_logic
) return boolean is
begin
return Rdy = '1' ;
end function TransactionPending ;
-- Variation for clockless models
procedure WaitForTransaction (
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- allow 0 time transactions
end procedure WaitForTransaction ;
------------------------------------------------------------
-- Toggle, WaitForToggle
-- Used for communicating between processes
------------------------------------------------------------
type stdulogic_indexby_stdulogic is array (std_ulogic) of std_ulogic;
constant toggle_sl_table : stdulogic_indexby_stdulogic := (
'0' => '1',
'L' => '1',
others => '0'
);
procedure Toggle (
signal Sig : InOut std_logic ;
constant DelayVal : time
) is
variable iDelayVal : time ;
begin
if DelayVal > t_sim_resolution then
iDelayVal := DelayVal - t_sim_resolution ;
else
iDelayVal := 0 sec ;
AlertIf(OSVVM_ALERTLOG_ID, DelayVal < 0 sec, "osvvm.TbUtilPkg.Toggle: Delay value < 0 ns") ;
end if ;
Sig <= toggle_sl_table(Sig) after iDelayVal ;
end procedure Toggle ;
procedure Toggle ( signal Sig : InOut std_logic ) is
begin
Sig <= toggle_sl_table(Sig) ;
end procedure Toggle ;
procedure ToggleHS ( signal Sig : InOut std_logic ) is
begin
Sig <= toggle_sl_table(Sig) ;
wait for 0 ns ; -- Sig toggles
wait for 0 ns ; -- new values updated into record
end procedure ToggleHS ;
function IsToggle ( signal Sig : In std_logic ) return boolean is
begin
return Sig'event ;
end function IsToggle ;
procedure WaitForToggle ( signal Sig : In std_logic ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
-- Bit type versions
procedure Toggle ( signal Sig : InOut bit ; constant DelayVal : time ) is
variable iDelayVal : time ;
begin
if DelayVal > t_sim_resolution then
iDelayVal := DelayVal - t_sim_resolution ;
else
iDelayVal := 0 sec ;
AlertIf(OSVVM_ALERTLOG_ID, DelayVal < 0 sec,
"osvvm.TbUtilPkg.Toggle: Delay value < 0 ns", WARNING) ;
end if ;
Sig <= not Sig after iDelayVal ;
end procedure Toggle ;
procedure Toggle ( signal Sig : InOut bit ) is
begin
Sig <= not Sig ;
end procedure Toggle ;
procedure ToggleHS ( signal Sig : InOut bit ) is
begin
Sig <= not Sig ;
wait for 0 ns ; -- Sig toggles
wait for 0 ns ; -- new values updated into record
end procedure ToggleHS ;
function IsToggle ( signal Sig : In bit ) return boolean is
begin
return Sig'event ;
end function IsToggle ;
procedure WaitForToggle ( signal Sig : In bit ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
-- Integer type versions
procedure Increment (signal Sig : InOut integer ; constant RollOverValue : in integer := 0) is
begin
--!! if Sig = integer'high then
if Sig = 2**30-1 then -- for consistency with function increment
Sig <= RollOverValue ;
else
Sig <= Sig + 1 ;
end if ;
end procedure Increment ;
function Increment (constant Sig : in integer ; constant Amount : in integer := 1) return integer is
begin
return (Sig + Amount) mod 2**30 ;
end function Increment ;
procedure WaitForToggle ( signal Sig : In integer ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
------------------------------------------------------------
-- WaitForBarrier
-- Barrier Synchronization
-- Multiple processes call it, it finishes when all have called it
------------------------------------------------------------
procedure WaitForBarrier ( signal Sig : InOut std_logic ) is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' or TimeOut = Polarity ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; constant TimeOut : time ) is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' for TimeOut ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
------------------------------------------------------------
-- resolved_barrier
-- summing resolution used in conjunction with integer based barriers
function resolved_barrier ( s : integer_vector ) return integer is
variable result : integer := 0 ;
begin
for i in s'RANGE loop
-- if s(i) /= integer'left then
-- result := result + s(i);
-- else
if s(i) /= 0 then
result := result + 1; -- removes the initialization requirement
end if ;
end loop ;
return result ;
end function resolved_barrier ;
-- Usage of integer barriers requires resolved_barrier. Initialization to 1 recommended, but not required
-- signal barrier1 : resolved_barrier integer := 1 ; -- using the resolution function
-- signal barrier2 : integer_barrier := 1 ; -- using the subtype that already applies the resolution function
procedure WaitForBarrier ( signal Sig : InOut integer ) is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut integer ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 or TimeOut = Polarity ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut integer ; constant TimeOut : time ) is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 for TimeOut ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
-- Using separate signals
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncIn : in std_logic ) is
begin
-- Activate Rdy
SyncOut <= '1' ;
-- Make sure our Rdy is seen
wait for 0 ns ;
-- Wait until other process' Rdy is at level 1
if SyncIn /= '1' then
wait until SyncIn = '1' ;
end if ;
-- Deactivate Rdy
SyncOut <= '0' ;
end procedure WaitForBarrier2 ;
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncInV : in std_logic_vector ) is
constant ALL_ONE : std_logic_vector(SyncInV'Range) := (others => '1');
begin
-- Activate Rdy
SyncOut <= '1' ;
-- Make sure our Rdy is seen
wait for 0 ns ;
-- Wait until all other process' Rdy is at level 1
if SyncInV /= ALL_ONE then
wait until SyncInV = ALL_ONE ;
end if ;
-- Deactivate Rdy
SyncOut <= '0' ;
end procedure WaitForBarrier2 ;
------------------------------------------------------------
-- WaitForClock
-- Sync to Clock - after a delay, after a number of clocks
------------------------------------------------------------
procedure WaitForClock ( signal Clk : in std_logic ; constant Delay : in time ) is
begin
if delay > t_sim_resolution then
wait for delay - t_sim_resolution ;
end if ;
wait until Clk = CLK_ACTIVE ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; constant NumberOfClocks : in integer := 1) is
begin
for i in 1 to NumberOfClocks loop
wait until Clk = CLK_ACTIVE ;
end loop ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in boolean ) is
begin
wait on Clk until Clk = CLK_ACTIVE and Enable ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in std_logic ; constant Polarity : std_logic := '1' ) is
begin
wait on Clk until Clk = CLK_ACTIVE and Enable = Polarity ;
end procedure WaitForClock ;
------------------------------------------------------------
-- WaitForLevel
-- Find a signal at a level
------------------------------------------------------------
procedure WaitForLevel ( signal A : in boolean ) is
begin
if not A then
wait until A ;
end if ;
end procedure WaitForLevel ;
procedure WaitForLevel ( signal A : in std_logic ; Polarity : std_logic := '1' ) is
begin
if A /= Polarity then
-- wait on A until A = Polarity ;
if Polarity = '1' then
wait until A = '1' ;
else
wait until A = '0' ;
end if ;
end if ;
end procedure WaitForLevel ;
------------------------------------------------------------
-- CreateClock, CreateReset
-- Note these do not exit
------------------------------------------------------------
procedure CreateClock (
signal Clk : inout std_logic ;
constant Period : time ;
constant DutyCycle : real := 0.5
) is
constant HIGH_TIME : time := Period * DutyCycle ;
constant LOW_TIME : time := Period - HIGH_TIME ;
begin
if HIGH_TIME = LOW_TIME then
loop
Clk <= toggle_sl_table(Clk) after HIGH_TIME ;
wait on Clk ;
end loop ;
else
-- Schedule s.t. all assignments after the first occur on delta cycle 0
Clk <= '0', '1' after LOW_TIME ;
wait for period - 1 ns ; -- allows after on future Clk <= '0'
loop
Clk <= '0' after 1 ns, '1' after LOW_TIME + 1 ns ;
wait for period ;
end loop ;
end if ;
end procedure CreateClock ;
procedure CheckClockPeriod (
constant AlertLogID : AlertLogIDType ;
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) is
variable LastLogTime, ObservedPeriod : time ;
begin
wait until Clk = CLK_ACTIVE ;
LastLogTime := now ;
-- Check First HowMany clocks
for i in 1 to HowMany loop
wait until Clk = CLK_ACTIVE ;
ObservedPeriod := now - LastLogTime ;
AffirmIf(AlertLogID, ObservedPeriod = Period,
"CheckClockPeriod: " & ClkName & " Period: " & to_string(ObservedPeriod) &
" = Expected " & to_string(Period)) ;
LastLogTime := now ;
end loop ;
wait ;
end procedure CheckClockPeriod ;
procedure CheckClockPeriod (
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) is
begin
CheckClockPeriod (
AlertLogID => ALERTLOG_DEFAULT_ID,
Clk => Clk,
Period => Period,
ClkName => ClkName,
HowMany => HowMany
) ;
end procedure CheckClockPeriod ;
procedure CreateReset (
signal Reset : out std_logic ;
constant ResetActive : in std_logic ;
signal Clk : in std_logic ;
constant Period : time ;
constant tpd : time
) is
begin
wait until Clk = CLK_ACTIVE ;
Reset <= ResetActive after tpd ;
wait for Period - t_sim_resolution ;
wait until Clk = CLK_ACTIVE ;
Reset <= not ResetActive after tpd ;
wait ;
end procedure CreateReset ;
procedure LogReset (
constant AlertLogID : AlertLogIDType ;
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) is
begin
-- Does not log the value of Reset at time 0.
for_ever : loop
wait on Reset ;
if Reset = ResetActive then
LOG(AlertLogID, ResetName & " now active", INFO) ;
print("") ;
elsif Reset = not ResetActive then
LOG(AlertLogID, ResetName & " now inactive", INFO) ;
print("") ;
else
LOG(AlertLogID, ResetName & " = " & to_string(Reset), INFO) ;
print("") ;
end if ;
end loop for_ever ;
end procedure LogReset ;
procedure LogReset (
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) is
begin
LogReset (
AlertLogID => ALERTLOG_DEFAULT_ID,
Reset => Reset,
ResetActive => ResetActive,
ResetName => ResetName,
LogLevel => LogLevel
) ;
end procedure LogReset ;
------------------------------------------------------------
-- Deprecated
-- WaitForAck, StrobeAck
-- Replaced by WaitForToggle and Toggle
------------------------------------------------------------
procedure WaitForAck ( signal Ack : In std_logic ) is
begin
-- Wait for Model to be done
wait until Ack = '1' ;
wait for 0 ns ;
end procedure ;
procedure StrobeAck ( signal Ack : Out std_logic ) is
begin
-- Model done, drive rising edge on Ack
Ack <= '0' ;
wait for 0 ns ;
Ack <= '1' ;
wait for 0 ns ;
end procedure ;
end TbUtilPkg ;
| artistic-2.0 | f4b39a39edbedfa327a1e85caebae597 | 0.547899 | 4.628784 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/eth/wrapper/greth_gbit_gen.vhd | 1 | 13,666 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_gbit_gen
-- File: greth_gbit_gen.vhd
-- Author: Marko Isomaki
-- Description: Generic Gigabit Ethernet MAC
------------------------------------------------------------------------------
library ieee;
library grlib;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library eth;
use eth.ethcomp.all;
entity greth_gbit_gen is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 1;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
sim : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
--ahb mst in
hgrant : in std_ulogic;
hready : in std_ulogic;
hresp : in std_logic_vector(1 downto 0);
hrdata : in std_logic_vector(31 downto 0);
--ahb mst out
hbusreq : out std_ulogic;
hlock : out std_ulogic;
htrans : out std_logic_vector(1 downto 0);
haddr : out std_logic_vector(31 downto 0);
hwrite : out std_ulogic;
hsize : out std_logic_vector(2 downto 0);
hburst : out std_logic_vector(2 downto 0);
hprot : out std_logic_vector(3 downto 0);
hwdata : out std_logic_vector(31 downto 0);
--edcl ahb mst in
ehgrant : in std_ulogic;
ehready : in std_ulogic;
ehresp : in std_logic_vector(1 downto 0);
ehrdata : in std_logic_vector(31 downto 0);
--edcl ahb mst out
ehbusreq : out std_ulogic;
ehlock : out std_ulogic;
ehtrans : out std_logic_vector(1 downto 0);
ehaddr : out std_logic_vector(31 downto 0);
ehwrite : out std_ulogic;
ehsize : out std_logic_vector(2 downto 0);
ehburst : out std_logic_vector(2 downto 0);
ehprot : out std_logic_vector(3 downto 0);
ehwdata : out std_logic_vector(31 downto 0);
--apb slv in
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
--apb slv out
prdata : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
gtx_clk : in std_ulogic;
tx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rx_clk : in std_ulogic;
rxd : in std_logic_vector(7 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_crs : in std_ulogic;
rx_en : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(7 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
gbit : out std_ulogic
);
end entity;
architecture rtl of greth_gbit_gen is
--host constants
constant fifosize : integer := 512;
constant fabits : integer := log2(fifosize);
constant fsize : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(fifosize, fabits+1);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufsize : integer := ebuf(log2(edclbufsz));
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(8 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(8 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(8 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(8 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
begin
gtxc0: greth_gbitc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
sim => sim,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahbg,
ramdebug => ramdebug,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => hgrant,
hready => hready,
hresp => hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => hbusreq,
hlock => hlock,
htrans => htrans,
haddr => haddr,
hwrite => hwrite,
hsize => hsize,
hburst => hburst,
hprot => hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ehgrant,
ehready => ehready,
ehresp => ehresp,
ehrdata => ehrdata,
--edcl ahb mst out
ehbusreq => ehbusreq,
ehlock => ehlock,
ehtrans => ehtrans,
ehaddr => ehaddr,
ehwrite => ehwrite,
ehsize => ehsize,
ehburst => ehburst,
ehprot => ehprot,
ehwdata => ehwdata,
--apb slv in
psel => psel,
penable => penable,
paddr => paddr,
pwrite => pwrite,
pwdata => pwdata,
--apb slv out
prdata => prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
gtx_clk => gtx_clk,
tx_clk => tx_clk,
tx_dv => tx_dv,
rx_clk => rx_clk,
rxd => rxd,
rx_dv => rx_dv,
rx_er => rx_er,
rx_col => rx_col,
rx_crs => rx_crs,
rx_en => rx_en,
mdio_i => mdio_i,
phyrstaddr => phyrstaddr,
mdint => mdint,
--ethernet output signals
reset => reset,
txd => txd,
tx_en => tx_en,
tx_er => tx_er,
mdc => mdc,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
--scantest
testrst => testrst,
testen => testen,
testoen => testoen,
edcladdr => edcladdr,
edclsepahb => edclsepahb,
edcldisable => edcldisable,
speed => speed,
gbit => gbit);
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
ft1 : if ft /= 0 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, txrenable, txraddress(fabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(fabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
edclramft1 : if (edcl /= 0) and (edclft /= 0) generate
r0 : syncram_2pft generic map (memtech, eabits, 16, 0, 0, edclft) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2pft generic map (memtech, eabits, 16, 0, 0, edclft) port map (
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
end architecture;
| gpl-2.0 | 5dfe11894208538990271b21435853ad | 0.509074 | 4.162656 | false | false | false | false |
khaledhassan/vhdl-examples | multiplexer/mux_4x1_tb.vhd | 1 | 3,084 | -- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Testbench for the 4-to-1 multiplexer.
library ieee;
use ieee.std_logic_1164.all;
entity mux_4x1_tb is
end mux_4x1_tb;
architecture TB of mux_4x1_tb is
signal sel : std_logic_vector(1 downto 0);
signal output, in0, in1, in2, in3 : std_logic_vector(0 downto 0);
begin
-- Instantiate the unit under test (UUT)
UUT : entity work.mux_4x1
generic map (
WIDTH => 1
)
port map (
output => output,
sel => sel,
in0 => in0,
in1 => in1,
in2 => in2,
in3 => in3
);
-- Stimulus process
process
begin
in0(0) <= '0';
in1(0) <= '0';
in2(0) <= '0';
in3(0) <= '0';
sel <= "00";
wait for 10 ns;
in0(0) <= '0';
in1(0) <= '0';
in2(0) <= '0';
in3(0) <= '0';
sel <= "01";
wait for 10 ns;
in0(0) <= '0';
in1(0) <= '0';
in2(0) <= '0';
in3(0) <= '0';
sel <= "10";
wait for 10 ns;
in0(0) <= '0';
in1(0) <= '0';
in2(0) <= '0';
in3(0) <= '0';
sel <= "11";
wait for 10 ns;
in0(0) <= '1';
in1(0) <= '0';
in2(0) <= '0';
in3(0) <= '0';
sel <= "00";
wait for 10 ns;
in0(0) <= '0';
in1(0) <= '1';
in2(0) <= '0';
in3(0) <= '0';
sel <= "01";
wait for 10 ns;
in0(0) <= '0';
in1(0) <= '0';
in2(0) <= '1';
in3(0) <= '0';
sel <= "10";
wait for 10 ns;
in0(0) <= '0';
in1(0) <= '0';
in2(0) <= '0';
in3(0) <= '1';
sel <= "11";
wait for 10 ns;
wait;
end process;
end TB; | mit | 8a39d9a1d41784a4374decbaa9f25308 | 0.511673 | 3.484746 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_rst_processing_system7_0_100M_0/synth/design_1_rst_processing_system7_0_100M_0.vhd | 1 | 8,259 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 12
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_12;
USE proc_sys_reset_v5_0_12.proc_sys_reset;
ENTITY design_1_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_processing_system7_0_100M_0;
ARCHITECTURE design_1_rst_processing_system7_0_100M_0_arch OF design_1_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "design_1_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "design_1_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=12,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_aresetn: SIGNAL IS "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF interconnect_aresetn: SIGNAL IS "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF peripheral_reset: SIGNAL IS "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF bus_struct_reset: SIGNAL IS "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_reset: SIGNAL IS "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF mb_debug_sys_rst: SIGNAL IS "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF aux_reset_in: SIGNAL IS "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF ext_reset_in: SIGNAL IS "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF slowest_sync_clk: SIGNAL IS "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_processing_system7_0_100M_0_arch;
| mit | 7d2c263ff636309b74654aba7cb1362a | 0.732655 | 3.529487 | false | false | false | false |
thinkoco/de1_soc_opencl | de1soc_sharedonly_vga/system/system_inst.vhd | 1 | 20,729 | component system is
port (
clk_50_clk : in std_logic := 'X'; -- clk
kernel_clk_clk : out std_logic; -- clk
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
peripheral_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
peripheral_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
peripheral_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
peripheral_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
peripheral_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
peripheral_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
peripheral_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
peripheral_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
peripheral_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
peripheral_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
peripheral_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
peripheral_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
peripheral_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
peripheral_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
peripheral_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
peripheral_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
peripheral_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
peripheral_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
peripheral_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
peripheral_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
peripheral_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
peripheral_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
peripheral_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
peripheral_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
peripheral_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
peripheral_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
peripheral_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
peripheral_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
peripheral_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
peripheral_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
peripheral_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
peripheral_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
peripheral_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
peripheral_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
peripheral_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
peripheral_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
peripheral_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
reset_50_reset_n : in std_logic := 'X'; -- reset_n
acl_iface_alt_vip_itc_0_clocked_video_vid_clk : in std_logic := 'X'; -- vid_clk
acl_iface_alt_vip_itc_0_clocked_video_vid_data : out std_logic_vector(31 downto 0); -- vid_data
acl_iface_alt_vip_itc_0_clocked_video_underflow : out std_logic; -- underflow
acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid : out std_logic; -- vid_datavalid
acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync : out std_logic; -- vid_v_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync : out std_logic; -- vid_h_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_f : out std_logic; -- vid_f
acl_iface_alt_vip_itc_0_clocked_video_vid_h : out std_logic; -- vid_h
acl_iface_alt_vip_itc_0_clocked_video_vid_v : out std_logic; -- vid_v
acl_iface_clock_130_clk : in std_logic := 'X' -- clk
);
end component system;
u0 : component system
port map (
clk_50_clk => CONNECTED_TO_clk_50_clk, -- clk_50.clk
kernel_clk_clk => CONNECTED_TO_kernel_clk_clk, -- kernel_clk.clk
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
peripheral_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_peripheral_hps_io_emac1_inst_TX_CLK, -- peripheral.hps_io_emac1_inst_TX_CLK
peripheral_hps_io_emac1_inst_TXD0 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
peripheral_hps_io_emac1_inst_TXD1 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
peripheral_hps_io_emac1_inst_TXD2 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
peripheral_hps_io_emac1_inst_TXD3 => CONNECTED_TO_peripheral_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
peripheral_hps_io_emac1_inst_RXD0 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
peripheral_hps_io_emac1_inst_MDIO => CONNECTED_TO_peripheral_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
peripheral_hps_io_emac1_inst_MDC => CONNECTED_TO_peripheral_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
peripheral_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_peripheral_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
peripheral_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_peripheral_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
peripheral_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_peripheral_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
peripheral_hps_io_emac1_inst_RXD1 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
peripheral_hps_io_emac1_inst_RXD2 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
peripheral_hps_io_emac1_inst_RXD3 => CONNECTED_TO_peripheral_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
peripheral_hps_io_sdio_inst_CMD => CONNECTED_TO_peripheral_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
peripheral_hps_io_sdio_inst_D0 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
peripheral_hps_io_sdio_inst_D1 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
peripheral_hps_io_sdio_inst_CLK => CONNECTED_TO_peripheral_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
peripheral_hps_io_sdio_inst_D2 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
peripheral_hps_io_sdio_inst_D3 => CONNECTED_TO_peripheral_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
peripheral_hps_io_usb1_inst_D0 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
peripheral_hps_io_usb1_inst_D1 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
peripheral_hps_io_usb1_inst_D2 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
peripheral_hps_io_usb1_inst_D3 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
peripheral_hps_io_usb1_inst_D4 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
peripheral_hps_io_usb1_inst_D5 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
peripheral_hps_io_usb1_inst_D6 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
peripheral_hps_io_usb1_inst_D7 => CONNECTED_TO_peripheral_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
peripheral_hps_io_usb1_inst_CLK => CONNECTED_TO_peripheral_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
peripheral_hps_io_usb1_inst_STP => CONNECTED_TO_peripheral_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
peripheral_hps_io_usb1_inst_DIR => CONNECTED_TO_peripheral_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
peripheral_hps_io_usb1_inst_NXT => CONNECTED_TO_peripheral_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
peripheral_hps_io_uart0_inst_RX => CONNECTED_TO_peripheral_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
peripheral_hps_io_uart0_inst_TX => CONNECTED_TO_peripheral_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
peripheral_hps_io_i2c1_inst_SDA => CONNECTED_TO_peripheral_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
peripheral_hps_io_i2c1_inst_SCL => CONNECTED_TO_peripheral_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
peripheral_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_peripheral_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
reset_50_reset_n => CONNECTED_TO_reset_50_reset_n, -- reset_50.reset_n
acl_iface_alt_vip_itc_0_clocked_video_vid_clk => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_clk, -- acl_iface_alt_vip_itc_0_clocked_video.vid_clk
acl_iface_alt_vip_itc_0_clocked_video_vid_data => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_data, -- .vid_data
acl_iface_alt_vip_itc_0_clocked_video_underflow => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_underflow, -- .underflow
acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_datavalid, -- .vid_datavalid
acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_v_sync, -- .vid_v_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_h_sync, -- .vid_h_sync
acl_iface_alt_vip_itc_0_clocked_video_vid_f => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_f, -- .vid_f
acl_iface_alt_vip_itc_0_clocked_video_vid_h => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_h, -- .vid_h
acl_iface_alt_vip_itc_0_clocked_video_vid_v => CONNECTED_TO_acl_iface_alt_vip_itc_0_clocked_video_vid_v, -- .vid_v
acl_iface_clock_130_clk => CONNECTED_TO_acl_iface_clock_130_clk -- acl_iface_clock_130.clk
);
| apache-2.0 | 2c289598e2fc2527b42bd045bc8a5f5c | 0.387911 | 4.020365 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-asic/leon3core.vhd | 1 | 32,942 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Fredrik Ringhage, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.i2c.all;
use gaisler.spi.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.net.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3core is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
scantest : integer := CFG_SCAN
);
port (
resetn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
clk : in std_ulogic;
clkapb : in std_ulogic;
clklock : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
dataen : out std_logic_vector(31 downto 0);
cbin : in std_logic_vector(7 downto 0);
cbout : out std_logic_vector(7 downto 0);
cben : out std_logic_vector(7 downto 0);
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
wdogn : out std_ulogic;
gpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
i2c_sclout : out std_ulogic;
i2c_sclen : out std_ulogic;
i2c_sclin : in std_ulogic;
i2c_sdaout : out std_ulogic;
i2c_sdaen : out std_ulogic;
i2c_sdain : in std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector(1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdioin : in std_logic;
emdioout : out std_logic;
emdioen : out std_logic;
emdc : out std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tdoen : out std_ulogic;
scanen : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic;
chain_tck : out std_ulogic;
chain_tckn : out std_ulogic;
chain_tdi : out std_ulogic;
chain_tdo : in std_ulogic;
bsshft : out std_ulogic;
bscapt : out std_ulogic;
bsupdi : out std_ulogic;
bsupdo : out std_ulogic;
bsdrive : out std_ulogic;
bshighz : out std_ulogic
);
end;
architecture rtl of leon3core is
--constant is_asic : integer := 1 - is_fpga(fabtech);
--constant blength : integer := 12;
--constant CFG_NCLKS : integer := 7;
constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal rstn, rstraw : std_ulogic;
signal rstapbn, rstapbraw : std_ulogic;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi, gpioi2 : gpio_in_type;
signal gpioo, gpioo2 : gpio_out_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
-- signal tck, tms, tdi, tdo : std_ulogic;
signal jtck, jtckn, jtdi, jrst, jtdo, jcapt, jshft, jupd, jiupd: std_ulogic;
signal jninst: std_logic_vector(7 downto 0);
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_rxclk : std_logic_vector(CFG_SPW_NUM*2-1 downto 0);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stati : ahbstat_in_type;
-- SPW Clock Gating signals
signal enphy : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal spwrstn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gspwclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal rxclko : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal lspwclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal spwclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal rxclkphyo : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal disclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal disrxclk0 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal disrxclk1 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal distxclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal distxclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal grxclk0 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal grxclk1 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gtxclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gtxclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal grst : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal crst : std_logic_vector(CFG_SPW_NUM-1 downto 0);
constant IOAEN : integer := 0;
constant CFG_SDEN : integer := CFG_MCTRL_LEON2;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;
constant OEPOL : integer := padoen_polarity(padtech);
constant CPU_FREQ : integer := 100000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
wpo.wprothit <= '0'; -- no write protection
rstgen0 : rstgen -- reset generator
generic map (syncrst => CFG_NOASYNC, scanen => scantest, syncin => 1)
port map (resetn, clk, clklock, rstn, rstraw, testrst);
rstgen1 : rstgen -- reset generator
generic map (syncrst => CFG_NOASYNC, scanen => scantest, syncin => 1)
port map (resetn, clkapb, clklock, rstapbn, rstapbraw, testrst);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahbctrl0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso,
testen, testrst, scanen, testoen);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
leon3s0 : leon3cg -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clk, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clk);
end generate;
errorn <= dbgo(0).error when OEPOL = 0 else not dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clk, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= dsuen; dsui.break <= dsubre; dsuact <= dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
ahbuart0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clk, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= dsurx; dsutx <= duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, part => JTAG_EXAMPLE_PART,
hindex => CFG_NCPU+CFG_AHB_UART, scantest => scantest, oepol => OEPOL)
port map(rstn, clk, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
jtck, jtdi, open, jrst, jcapt, jshft, jupd, jtdo, trst, tdoen, '0', jtckn, jninst, jiupd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
address <= memo.address(27 downto 0);
ramsn <= memo.ramsn(4 downto 0); romsn <= memo.romsn(1 downto 0);
oen <= memo.oen; rwen <= memo.wrn; ramoen <= memo.ramoen(4 downto 0);
writen <= memo.writen; read <= memo.read; iosn <= memo.iosn;
dataout <= memo.data(31 downto 0); dataen <= memo.vbdrive(31 downto 0);
memi.data(31 downto 0) <= datain;
sdwen <= sdo.sdwen; sdrasn <= sdo.rasn; sdcasn <= sdo.casn;
sddqm <= sdo.dqm(3 downto 0); sdcsn <= sdo.sdcsn;
cbout <= memo.cb(7 downto 0); cben <= memo.vcdrive(7 downto 0);
memi.bwidth <= prom32 & '0';
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
mctrl0 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE,
oepol => OEPOL)
port map (rstn, clk, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdo.sdcsn <= (others => '1');
end generate;
memi.writen <= '1'; memi.wrn <= "1111";
memi.brdyn <= brdyn; memi.bexcn <= bexcn;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- None PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
memo.ramsn <= (others => '1'); memo.romsn <= (others => '1');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apbctrl0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstapbn, clkapb, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
apbuart0 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstapbn, clkapb, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
txd1 <= u1o.txd; u1i.rxd <= rxd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 9, fifosize => CFG_UART2_FIFO)
port map (rstapbn, clkapb, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clk, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
gptimer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstapbn, clkapb, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
wdogn <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 6, paddr => 6, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH, oepol => OEPOL, syncrst => CFG_NOASYNC)
port map( rstapbn, clkapb, apbi, apbo(6), gpioi, gpioo);
gpioout <= gpioo.dout(CFG_GRGPIO_WIDTH-1 downto 0);
gpioen <= gpioo.oen(CFG_GRGPIO_WIDTH-1 downto 0);
gpioi.din(CFG_GRGPIO_WIDTH-1 downto 0) <= gpioin;
end generate;
nogpio : if CFG_GRGPIO_ENABLE = 0 generate apbo(5) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 5, paddr => 5, pmask => 16#FFF#, pirq => 13, filter => 9)
port map (rstapbn, clkapb, apbi, apbo(5), i2ci, i2co);
i2c_sclout <= i2co.scl;
i2c_sclen <= i2co.scloen;
i2ci.scl <= i2c_sclin;
i2c_sdaout <= i2co.sda;
i2c_sdaen <= i2co.sdaoen;
i2ci.sda <= i2c_sdain;
end generate i2cm;
noi2cm: if CFG_I2C_ENABLE = 0 generate apbo(5) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spictrl0 : spictrl
generic map(
pindex => 8,
paddr => 8,
pmask => 16#fff#,
pirq => 8,
fdepth => CFG_SPICTRL_FIFO,
slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS,
oepol => oepol,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => CFG_SPICTRL_TWEN,
maxwlen => CFG_SPICTRL_MAXWLEN,
syncram => CFG_SPICTRL_SYNCRAM,
memtech => memtech,
ft => CFG_SPICTRL_FT,
scantest => scantest)
port map(
rstn => rstapbn,
clk => clkapb,
apbi => apbi,
apbo => apbo(8),
spii => spii,
spio => spio,
slvsel => spi_slvsel);
spii.sck <= '0';
spii.mosi <= '0';
spii.miso <= spi_miso;
spi_mosi <= spio.mosi;
spi_sck <= spio.sck;
spii.astart <= '0'; --unused
spii.spisel <= '1'; --unused (master only)
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate apbo(14) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat
generic map (pindex => 15, paddr => 15, pirq => 1, nftslv => CFG_AHBSTATN)
port map (rstn, clk, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-------------------------------------------------------------------------------
-- JTAG Boundary scan
-------------------------------------------------------------------------------
bscangen: if CFG_BOUNDSCAN_EN /= 0 generate
xtapgen: if CFG_AHB_JTAG = 0 generate
t0: tap
generic map (tech => fabtech, irlen => 6, scantest => scantest, oepol => OEPOL)
port map (trst,tck,tms,tdi,tdo,
jtck,jtdi,open,jrst,jcapt,jshft,jupd,open,open,'1',jtdo,'0',jninst,jiupd,jtckn,testen,testrst,testoen,tdoen,'0');
end generate;
bc0: bscanctrl
port map (
trst,jtck,jtckn,jtdi,jninst,jiupd,jrst,jcapt,jshft,jupd,jtdo,
chain_tdi, chain_tdo, bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz,
gnd(0), testen, testrst);
chain_tck <= jtck;
chain_tckn <= jtckn;
end generate;
nobscangen: if CFG_BOUNDSCAN_EN = 0 generate
chain_tck <= '0';
chain_tckn <= '0';
chain_tdi <= '0';
bsshft <= '0';
bscapt <= '0';
bsupdi <= '0';
bsupdo <= '0';
bsdrive <= '0';
bshighz <= '0';
end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
swloop : for i in 0 to CFG_SPW_NUM-1 generate
spwi(i).clkdiv10 <=
"000" & gpioo.val(10 downto 8) & "11" when spw_clksel(1 downto 0) = "11" else
"0000" & gpioo.val(10 downto 8) & '1' when spw_clksel(1 downto 0) = "10" else
"00000" & gpioo.val(10 downto 8);
spwi(i).timerrstval <=
'0' & gpioo.val(15 downto 11) & "111111" when clksel(1 downto 0) = "11" else
"00" & gpioo.val(15 downto 11) & "11111" when clksel(1 downto 0) = "10" else
"000" & gpioo.val(15 downto 11) & "1111";
spwi(i).dcrstval <=
"00" & gpioo.val(15 downto 11) & "111" when clksel(1 downto 0) = "11" else
"000" & gpioo.val(15 downto 11) & "10" when clksel(1 downto 0) = "10" else
"0000" & gpioo.val(15 downto 11) & '0';
-- GRSPW PHY #1
spw1_input: if CFG_SPW_GRSPW = 1 generate
x : process
begin
assert false
report "ASIC Leon3 Ref design do not support GRSPW #1"
severity failure;
wait;
end process;
end generate spw1_input;
-- GRSPW PHY #2
spw2_input: if CFG_SPW_GRSPW = 2 generate
------------------------------------------------------------------------------
-- SpW Physical layer
------------------------------------------------------------------------------
--phy_loop : for i in 0 to CFG_SPWRTR_SPWPORTS-1 generate
rstphy0 : rstgen
generic map(
acthigh => 0, -- CFG_RSTGEN_ACTHIGH,
syncrst => CFG_NOASYNC, -- CFG_RSTGEN_SYNCRST,
scanen => scantest,
syncin => 1)
port map (
rstin => rstn,
clk => spw_clk,
clklock => clklock,
rstout => spwrstn(i),
rstoutraw => open,
testrst => testrst,
testen => testen);
-- Only add clockgating to tech lib which supports clock gates
clkgatephygen : if (has_clkand(fabtech) = 1) generate
-- Sync clock to clock domain
spwclkreg : process(spw_clk) is
begin
if rising_edge(spw_clk) then
-- Only disable phy when rx and tx is disabled
-- TODO: Add SW register to enable/disable the router
enphy(i) <= '1';
end if;
end process;
-- Disable spw phy clock when port is not used
spw_phy0_enable : clkand
generic map (
tech => fabtech,
ren => 0)
port map (
i => spw_clk,
en => enphy(i),
o => gspwclk(i),
tsten => testen);
-- Select rx clock (Should be removed by optimization if RX and TX clock is same i.e. normal case for ASIC)
spw_rxclk(i) <= spw_clk when (CFG_SPW_RTSAME = 1) else rxclkphyo(i);
end generate;
noclkgategen : if (has_clkand(fabtech) = 0) generate
enphy(i) <= '1';
gspwclk(i) <= spw_clk;
spw_rxclk(i) <= spw_clk when (CFG_SPW_RTSAME = 1) else rxclkphyo(i);
end generate;
notecclkmux : if (has_clkmux(fabtech) = 0) generate
spwclkn(i) <= spw_clk when (testen = '1' and scantest = 1) else not spw_clk;
end generate;
tecclkmux : if (has_clkmux(fabtech) = 1) generate
-- Use SET protected cells
spwclkni0: clkinv generic map (tech => fabtech) port map (spw_clk, lspwclkn(i));
spwclknm0 : clkmux generic map (tech => fabtech) port map (lspwclkn(i),spw_clk,testen,spwclkn(i));
end generate;
spw_phy0 : grspw2_phy
generic map(
scantest => scantest,
tech => fabtech,
input_type => CFG_SPW_INPUT)
port map(
rstn => spwrstn(i),
rxclki => gspwclk(i),
rxclkin => spwclkn(i),
nrxclki => spwclkn(i),
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => rxclkphyo(i),
testrst => testrst,
testen => testen);
dtmp(i) <= spw_rxd(i); stmp(i) <= spw_rxs(i);
spw_txd(i) <= spwo(i).d(0); spw_txs(i) <= spwo(i).s(0);
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
--end generate;
end generate spw2_input;
spw1_codec: if CFG_SPW_GRSPW = 1 generate
x : process
begin
assert false
report "ASIC Leon3 Ref design do not support GRSPW #1"
severity failure;
wait;
end process;
end generate spw1_codec;
spw2_codec: if CFG_SPW_GRSPW = 2 generate
rstcodec0 : rstgen
generic map(
acthigh => 0, -- CFG_RSTGEN_ACTHIGH,
syncrst => CFG_NOASYNC, -- CFG_RSTGEN_SYNCRST,
scanen => scantest,
syncin => 1)
port map (
rstin => rstn,
clk => spw_clk,
clklock => clklock,
rstout => crst(i),
rstoutraw => open,
testrst => testrst,
testen => testen);
-- TODO: Fix SW control signals
disclk(i) <= '0';
disrxclk0(i) <= '0';
disrxclk1(i) <= '0';
distxclk(i) <= '0';
distxclkn(i) <= '0';
port0_clkgate : grspw_codec_clockgate
generic map (
tech => fabtech,
scantest => scantest,
ports => CFG_SPW_PORTS,
output_type => CFG_SPW_OUTPUT,
clkgate => 1
)
port map (
rst => crst(i),
clk => spw_clk,
rxclk0 => spw_rxclk(i),
rxclk1 => '0',
txclk => spw_clk,
txclkn => '0',
testen => testen,
testrst => testrst,
disableclk => disclk(i),
disablerxclk0 => disrxclk0(i),
disablerxclk1 => disrxclk1(i),
disabletxclk => distxclk(i),
disabletxclkn => distxclkn(i),
grst => grst(i),
gclk => gclk(i),
grxclk0 => grxclk0(i),
grxclk1 => grxclk1(i),
gtxclk => gtxclk(i),
gtxclkn => gtxclkn(i)
);
grspw0 : grspw2
generic map(
tech => fabtech, -- : integer range 0 to NTECH := inferred;
hindex => maxahbmsp+i, -- : integer range 0 to NAHBMST-1 := 0;
pindex => i+10, -- : integer range 0 to NAPBSLV-1 := 0;
paddr => i+10, -- : integer range 0 to 16#FFF# := 0;
--pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq => i+10, -- : integer range 0 to NAHBIRQ-1 := 0;
rmap => CFG_SPW_RMAP, -- : integer range 0 to 2 := 0;
rmapcrc => CFG_SPW_RMAPCRC, -- : integer range 0 to 1 := 0;
fifosize1 => CFG_SPW_AHBFIFO, -- : integer range 4 to 32 := 32;
fifosize2 => CFG_SPW_RXFIFO, -- : integer range 16 to 64 := 64;
rxclkbuftype => 0, -- : integer range 0 to 2 := 0;
rxunaligned => CFG_SPW_RXUNAL, -- : integer range 0 to 1 := 0;
rmapbufs => CFG_SPW_RMAPBUF, -- : integer range 2 to 8 := 4;
ft => CFG_SPW_FT, -- : integer range 0 to 2 := 0;
scantest => scantest, -- : integer range 0 to 1 := 0;
ports => CFG_SPW_PORTS, -- : integer range 1 to 2 := 1;
dmachan => CFG_SPW_DMACHAN, -- : integer range 1 to 4 := 1;
memtech => memtech, -- : integer range 0 to NTECH := DEFMEMTECH;
techfifo => has_2pram(memtech), -- : integer range 0 to 1 := 1;
input_type => CFG_SPW_INPUT, -- : integer range 0 to 4 := 0;
output_type => CFG_SPW_OUTPUT, -- : integer range 0 to 2 := 0;
rxtx_sameclk => CFG_SPW_RTSAME, -- : integer range 0 to 1 := 0;
netlist => CFG_SPW_NETLIST -- : integer range 0 to 1 := 0;
)
port map (
rst => grst(i),
clk => gclk(i),
rxclk0 => grxclk0(i),
rxclk1 => grxclk1(i),
txclk => gtxclk(i),
txclkn => gtxclkn(i),
ahbmi => ahbmi,
ahbmo => ahbmo(maxahbmsp+i),
apbi => apbi,
apbo => apbo(i+10),
swni => spwi(i),
swno => spwo(i)
);
end generate spw2_codec;
end generate;
end generate;
nospw : if CFG_SPW_EN = 0 generate
spw_txd <= (others => '0');
spw_txs <= (others => '0');
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 13, paddr => 13, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(rst => rstn, clk => clk, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
ethi.gtx_clk <= gtx_clk;
ethi.rx_clk <= erx_clk;
ethi.rxd(7 downto 0) <= erxd;
ethi.rx_dv <= erx_dv;
ethi.tx_clk <= etx_clk;
etxd <= etho.txd(7 downto 0);
etx_en <= etho.tx_en;
etx_er <= etho.tx_er;
ethi.mdint <= emdint;
ethi.mdio_i <= emdioin;
emdioout <= etho.mdio_o;
emdioen <= etho.mdio_oe;
emdc <= etho.mdc;
ethi.rx_er <= erx_er;
ethi.rx_col <= erx_col;
ethi.rx_crs <= erx_crs;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
noam1 : for i in maxahbm to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- noap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1-CFG_AHBSTAT
-- generate apbo(i) <= apb_none; end generate;
noah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 ASIC Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 967735ec3245696a55dc8cc4587f2c41 | 0.521735 | 3.63799 | false | true | false | false |
freecores/mdct | source/DCT1D.vhd | 1 | 13,445 | --------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT1D
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : DCT1D.VHD
-- Created : Sat Mar 5 7:37 2006
--
--------------------------------------------------------------------------------
--
-- Description : 1D Discrete Cosine Transform (1st stage)
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library WORK;
use WORK.MDCT_PKG.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity DCT1D is
port(
clk : in STD_LOGIC;
rst : in std_logic;
dcti : in std_logic_vector(IP_W-1 downto 0);
idv : in STD_LOGIC;
romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
odv : out STD_LOGIC;
dcto : out std_logic_vector(OP_W-1 downto 0);
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
ramwe : out STD_LOGIC;
wmemsel : out STD_LOGIC
);
end DCT1D;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture RTL of DCT1D is
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
signal databuf_reg : INPUT_DATA;
signal latchbuf_reg : INPUT_DATA;
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
signal ramwe_s : STD_LOGIC;
signal wmemsel_reg : STD_LOGIC;
signal stage2_reg : STD_LOGIC;
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
begin
ramwe_sg:
ramwe <= ramwe_s;
ramdatai_sg:
ramdatai <= ramdatai_s;
-- temporary
odv_sg:
odv <= ramwe_s;
dcto_sg:
dcto <= ramdatai_s(RAMDATA_W-1) & ramdatai_s(RAMDATA_W-1) & ramdatai_s;
wmemsel_sg:
wmemsel <= wmemsel_reg;
process(clk)
begin
if clk = '1' and clk'event then
if rst = '1' then
inpcnt_reg <= (others => '0');
latchbuf_reg <= (others => (others => '0'));
databuf_reg <= (others => (others => '0'));
stage2_reg <= '0';
stage2_cnt_reg <= (others => '1');
ramdatai_s <= (others => '0');
ramwe_s <= '0';
ramwaddro <= (others => '0');
col_reg <= (others => '0');
row_reg <= (others => '0');
wmemsel_reg <= '0';
col_2_reg <= (others => '0');
else
stage2_reg <= '0';
ramwe_s <= '0';
--------------------------------
-- 1st stage
--------------------------------
if idv = '1' then
inpcnt_reg <= inpcnt_reg + 1;
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
if inpcnt_reg = N-1 then
-- after this sum databuf_reg is in range of -256 to 254 (min to max)
databuf_reg(0) <= latchbuf_reg(1)+(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(1) <= latchbuf_reg(2)+latchbuf_reg(7);
databuf_reg(2) <= latchbuf_reg(3)+latchbuf_reg(6);
databuf_reg(3) <= latchbuf_reg(4)+latchbuf_reg(5);
databuf_reg(4) <= latchbuf_reg(1)-(SIGNED('0' & dcti) - LEVEL_SHIFT);
databuf_reg(5) <= latchbuf_reg(2)-latchbuf_reg(7);
databuf_reg(6) <= latchbuf_reg(3)-latchbuf_reg(6);
databuf_reg(7) <= latchbuf_reg(4)-latchbuf_reg(5);
stage2_reg <= '1';
end if;
end if;
--------------------------------
--------------------------------
-- 2nd stage
--------------------------------
if stage2_cnt_reg < N then
if stage2_cnt_reg(0) = '0' then
ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romedatao0),DA_W) +
(RESIZE(SIGNED(romedatao1),DA_W-1) & '0') +
(RESIZE(SIGNED(romedatao2),DA_W-2) & "00") +
(RESIZE(SIGNED(romedatao3),DA_W-3) & "000") +
(RESIZE(SIGNED(romedatao4),DA_W-4) & "0000") +
(RESIZE(SIGNED(romedatao5),DA_W-5) & "00000") +
(RESIZE(SIGNED(romedatao6),DA_W-6) & "000000") +
(RESIZE(SIGNED(romedatao7),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romedatao8),DA_W-8) & "00000000"),
DA_W)(DA_W-1 downto 12));
else
ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
(RESIZE(SIGNED(romodatao0),DA_W) +
(RESIZE(SIGNED(romodatao1),DA_W-1) & '0') +
(RESIZE(SIGNED(romodatao2),DA_W-2) & "00") +
(RESIZE(SIGNED(romodatao3),DA_W-3) & "000") +
(RESIZE(SIGNED(romodatao4),DA_W-4) & "0000") +
(RESIZE(SIGNED(romodatao5),DA_W-5) & "00000") +
(RESIZE(SIGNED(romodatao6),DA_W-6) & "000000") +
(RESIZE(SIGNED(romodatao7),DA_W-7) & "0000000") -
(RESIZE(SIGNED(romodatao8),DA_W-8) & "00000000"),
DA_W)(DA_W-1 downto 12));
end if;
stage2_cnt_reg <= stage2_cnt_reg + 1;
-- write RAM
ramwe_s <= '1';
-- reverse col/row order for transposition purpose
ramwaddro <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
-- increment column counter
col_reg <= col_reg + 1;
col_2_reg <= col_2_reg + 1;
-- finished processing one input row
if col_reg = 0 then
row_reg <= row_reg + 1;
-- switch to 2nd memory
if row_reg = N - 1 then
wmemsel_reg <= not wmemsel_reg;
col_reg <= (others => '0');
end if;
end if;
end if;
if stage2_reg = '1' then
stage2_cnt_reg <= (others => '0');
col_reg <= (0=>'1',others => '0');
col_2_reg <= (others => '0');
end if;
----------------------------------
end if;
end if;
end process;
-- read precomputed MAC results from LUT
romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(0) &
databuf_reg(1)(0) &
databuf_reg(2)(0) &
databuf_reg(3)(0);
romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(1) &
databuf_reg(1)(1) &
databuf_reg(2)(1) &
databuf_reg(3)(1);
romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(2) &
databuf_reg(1)(2) &
databuf_reg(2)(2) &
databuf_reg(3)(2);
romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(3) &
databuf_reg(1)(3) &
databuf_reg(2)(3) &
databuf_reg(3)(3);
romeaddro4 <= STD_LOGIC_VECTOR( col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(4) &
databuf_reg(1)(4) &
databuf_reg(2)(4) &
databuf_reg(3)(4);
romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(5) &
databuf_reg(1)(5) &
databuf_reg(2)(5) &
databuf_reg(3)(5);
romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(6) &
databuf_reg(1)(6) &
databuf_reg(2)(6) &
databuf_reg(3)(6);
romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(7) &
databuf_reg(1)(7) &
databuf_reg(2)(7) &
databuf_reg(3)(7);
romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(0)(8) &
databuf_reg(1)(8) &
databuf_reg(2)(8) &
databuf_reg(3)(8);
-- odd
romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(0) &
databuf_reg(5)(0) &
databuf_reg(6)(0) &
databuf_reg(7)(0);
romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(1) &
databuf_reg(5)(1) &
databuf_reg(6)(1) &
databuf_reg(7)(1);
romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(2) &
databuf_reg(5)(2) &
databuf_reg(6)(2) &
databuf_reg(7)(2);
romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(3) &
databuf_reg(5)(3) &
databuf_reg(6)(3) &
databuf_reg(7)(3);
romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(4) &
databuf_reg(5)(4) &
databuf_reg(6)(4) &
databuf_reg(7)(4);
romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(5) &
databuf_reg(5)(5) &
databuf_reg(6)(5) &
databuf_reg(7)(5);
romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(6) &
databuf_reg(5)(6) &
databuf_reg(6)(6) &
databuf_reg(7)(6);
romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(7) &
databuf_reg(5)(7) &
databuf_reg(6)(7) &
databuf_reg(7)(7);
romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
databuf_reg(4)(8) &
databuf_reg(5)(8) &
databuf_reg(6)(8) &
databuf_reg(7)(8);
end RTL;
--------------------------------------------------------------------------------
| lgpl-3.0 | 2a24f4b67b009b12751d5327baf53439 | 0.463816 | 3.615219 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/spi/spi2ahb_apb.vhd | 1 | 6,817 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb_apb
-- File: spi2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from SPI.
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.spi.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity spi2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb_apb;
architecture rtl of spi2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPI2AHB, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
spi2ahbi : spi2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal spi2ahbo : spi2ahb_out_type;
begin
bridge : spi2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter,
cpol => cpol, cpha => cpha)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
spii => spii, spio => spio, spi2ahbi => r.spi2ahbi,
spi2ahbo => spi2ahbo);
comb: process (r, rstn, apbi, spi2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := spi2ahbo.prot; v.dmax := spi2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.spi2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.spi2ahbi.haddr;
when MASK_OFF => apbout := r.spi2ahbi.hmask;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.spi2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.spi2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.spi2ahbi.hmask := apbi.pwdata;
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((spi2ahbo.dma and not r.dmax) or
(spi2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or spi2ahbo.prot; v.wr := spi2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.spi2ahbi.en := conv_std_logic(resen = 1);
v.spi2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.spi2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in spi2ahbx...
end architecture rtl;
| gpl-2.0 | 13d60b76a54931ba860b18bd582447f1 | 0.535426 | 3.797772 | false | false | false | false |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/serdes.vhd | 3 | 5,243 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity serdes is
port(
clk : in std_logic;
rst : in std_logic;
input_0 : in std_logic;
input_1 : in std_logic;
input_2 : in std_logic;
input_3 : in std_logic;
input_4 : in std_logic;
input_5 : in std_logic;
input_6 : in std_logic;
input_7 : in std_logic;
output : out std_logic
);
end entity serdes;
architecture rtl of serdes is
signal clk_100 : std_logic;
signal clk_100_s : std_logic;
signal clk_400 : std_logic;
signal clk_400_s : std_logic;
signal clk_400_n : std_logic;
signal clk_400_n_s : std_logic;
signal clkfbin : std_logic;
signal clkfbout : std_logic;
begin
oserdese2_inst : oserdese2
generic map (
data_rate_oq => "ddr", -- ddr, sdr
data_rate_tq => "sdr", -- ddr, buf, sdr
data_width => 8, -- parallel data width (2-8,10,14)
init_oq => '0', -- initial value of oq output (1'b0,1'b1)
init_tq => '0', -- initial value of tq output (1'b0,1'b1)
serdes_mode => "master", -- master, slave
srval_oq => '0', -- oq output value when sr is used (1'b0,1'b1)
srval_tq => '0', -- tq output value when sr is used (1'b0,1'b1)
tbyte_ctl => "false", -- enable tristate byte operation (false, true)
tbyte_src => "false", -- tristate byte source (false, true)
tristate_width => 1 -- 3-state converter width (1,4)
)
port map (
ofb => open, -- 1-bit output: feedback path for data
oq => output, -- 1-bit output: data path output
-- shiftout1 / shiftout2: 1-bit (each) output: data output expansion (1-bit each)
shiftout1 => open,
shiftout2 => open,
tbyteout => open, -- 1-bit output: byte group tristate
tfb => open, -- 1-bit output: 3-state control
tq => open, -- 1-bit output: 3-state control
clk => clk_400, -- 1-bit input: high speed clock
clkdiv => clk_100, -- 1-bit input: divided clock
-- d1 - d8: 1-bit (each) input: parallel data inputs (1-bit each)
d1 => input_0,
d2 => input_1,
d3 => input_2,
d4 => input_3,
d5 => input_4,
d6 => input_5,
d7 => input_6,
d8 => input_7,
oce => '1', -- 1-bit input: output data clock enable
rst => '0', -- 1-bit input: reset
-- shiftin1 / shiftin2: 1-bit (each) input: data input expansion (1-bit each)
shiftin1 => '0',
shiftin2 => '0',
-- t1 - t4: 1-bit (each) input: parallel 3-state inputs
t1 => '0',
t2 => '0',
t3 => '0',
t4 => '0',
tbytein => '0', -- 1-bit input: byte group tristate
tce => '1' -- 1-bit input: 3-state clock enable
);
plle2_base_inst : plle2_base generic map (
bandwidth => "optimized", -- optimized, high, low
clkfbout_mult => 8, -- multiply value for all clkout, (2-64)
clkfbout_phase => 0.0, -- phase offset in degrees of clkfb, (-360.000-360.000).
clkin1_period => 10.0, -- input clock period in ns to ps resolution (i.e. 33.333 is 30 mhz).
-- clkout0_divide - clkout5_divide: divide amount for each clkout (1-128)
clkout0_divide => 8,
clkout1_divide => 2,
clkout2_divide => 2,
clkout3_divide => 1,
clkout4_divide => 1,
clkout5_divide => 1,
-- clkout0_duty_cycle - clkout5_duty_cycle: duty cycle for each clkout (0.001-0.999).
clkout0_duty_cycle => 0.5,
clkout1_duty_cycle => 0.5,
clkout2_duty_cycle => 0.5,
clkout3_duty_cycle => 0.5,
clkout4_duty_cycle => 0.5,
clkout5_duty_cycle => 0.5,
-- clkout0_phase - clkout5_phase: phase offset for each clkout (-360.000-360.000).
clkout0_phase => 0.0,
clkout1_phase => 0.0,
clkout2_phase => 180.0,
clkout3_phase => 0.0,
clkout4_phase => 0.0,
clkout5_phase => 0.0,
divclk_divide => 1, -- master division value, (1-56)
ref_jitter1 => 0.0, -- reference input jitter in ui, (0.000-0.999).
startup_wait => "false" -- delay done until pll locks, ("true"/"false")
)
port map (
-- clock outputs: 1-bit (each) output: user configurable clock outputs
clkout0 => clk_100_s,
clkout1 => clk_400_s,
clkout2 => clk_400_n_s,
clkout3 => open,
clkout4 => open,
clkout5 => open,
-- feedback clocks: 1-bit (each) output: clock feedback ports
clkfbout => clkfbout, -- 1-bit output: feedback clock
-- status port: 1-bit (each) output: pll status ports
locked => open, -- 1-bit output: lock
-- clock input: 1-bit (each) input: clock input
clkin1 => clk, -- 1-bit input: input clock
-- control ports: 1-bit (each) input: pll control ports
pwrdwn => '0', -- 1-bit input: power-down
rst => '0', -- 1-bit input: reset
-- feedback clocks: 1-bit (each) input: clock feedback ports
clkfbin => clkfbin -- 1-bit input: feedback clock
);
bufg_inst_1 : bufg
port map (
o => clk_100, -- 1-bit output: clock output
i => clk_100_s -- 1-bit input: clock input
);
bufg_inst_2 : bufg
port map (
o => clk_400, -- 1-bit output: clock output
i => clk_400_s -- 1-bit input: clock input
);
bufg_inst_3 : bufg
port map (
o => clk_400_n, -- 1-bit output: clock output
i => clk_400_n_s -- 1-bit input: clock input
);
bufg_inst_4 : bufg
port map (
o => clkfbin,
i => clkfbout
);
end rtl;
| mit | 45dd3857e5f9ca491555e154132e056b | 0.60061 | 3.048256 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.cache/ip/2017.3/747b0ef18f7ea24b/ip_design_lms_pcore_0_0_sim_netlist.vhdl | 1 | 877,760 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:38 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_lms_pcore_0_0_sim_netlist.vhdl
-- Design : ip_design_lms_pcore_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS is
port (
mul_temp_16 : out STD_LOGIC_VECTOR ( 15 downto 0 );
filter_sum : out STD_LOGIC_VECTOR ( 15 downto 0 );
\write_reg_x_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
cop_dut_enable : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\write_reg_d_k_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
DI : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 14 downto 0 );
\write_reg_d_k_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS is
signal \ARG__0_i_1_n_0\ : STD_LOGIC;
signal \ARG__0_n_100\ : STD_LOGIC;
signal \ARG__0_n_101\ : STD_LOGIC;
signal \ARG__0_n_102\ : STD_LOGIC;
signal \ARG__0_n_103\ : STD_LOGIC;
signal \ARG__0_n_104\ : STD_LOGIC;
signal \ARG__0_n_105\ : STD_LOGIC;
signal \ARG__0_n_92\ : STD_LOGIC;
signal \ARG__0_n_93\ : STD_LOGIC;
signal \ARG__0_n_94\ : STD_LOGIC;
signal \ARG__0_n_95\ : STD_LOGIC;
signal \ARG__0_n_96\ : STD_LOGIC;
signal \ARG__0_n_97\ : STD_LOGIC;
signal \ARG__0_n_98\ : STD_LOGIC;
signal \ARG__0_n_99\ : STD_LOGIC;
signal \ARG__10_i_1_n_0\ : STD_LOGIC;
signal \ARG__10_n_100\ : STD_LOGIC;
signal \ARG__10_n_101\ : STD_LOGIC;
signal \ARG__10_n_102\ : STD_LOGIC;
signal \ARG__10_n_103\ : STD_LOGIC;
signal \ARG__10_n_104\ : STD_LOGIC;
signal \ARG__10_n_105\ : STD_LOGIC;
signal \ARG__10_n_92\ : STD_LOGIC;
signal \ARG__10_n_93\ : STD_LOGIC;
signal \ARG__10_n_94\ : STD_LOGIC;
signal \ARG__10_n_95\ : STD_LOGIC;
signal \ARG__10_n_96\ : STD_LOGIC;
signal \ARG__10_n_97\ : STD_LOGIC;
signal \ARG__10_n_98\ : STD_LOGIC;
signal \ARG__10_n_99\ : STD_LOGIC;
signal \ARG__11_i_1_n_0\ : STD_LOGIC;
signal \ARG__11_n_100\ : STD_LOGIC;
signal \ARG__11_n_101\ : STD_LOGIC;
signal \ARG__11_n_102\ : STD_LOGIC;
signal \ARG__11_n_103\ : STD_LOGIC;
signal \ARG__11_n_104\ : STD_LOGIC;
signal \ARG__11_n_105\ : STD_LOGIC;
signal \ARG__11_n_76\ : STD_LOGIC;
signal \ARG__11_n_77\ : STD_LOGIC;
signal \ARG__11_n_78\ : STD_LOGIC;
signal \ARG__11_n_79\ : STD_LOGIC;
signal \ARG__11_n_80\ : STD_LOGIC;
signal \ARG__11_n_81\ : STD_LOGIC;
signal \ARG__11_n_82\ : STD_LOGIC;
signal \ARG__11_n_83\ : STD_LOGIC;
signal \ARG__11_n_84\ : STD_LOGIC;
signal \ARG__11_n_85\ : STD_LOGIC;
signal \ARG__11_n_86\ : STD_LOGIC;
signal \ARG__11_n_87\ : STD_LOGIC;
signal \ARG__11_n_88\ : STD_LOGIC;
signal \ARG__11_n_89\ : STD_LOGIC;
signal \ARG__11_n_90\ : STD_LOGIC;
signal \ARG__11_n_91\ : STD_LOGIC;
signal \ARG__11_n_92\ : STD_LOGIC;
signal \ARG__11_n_93\ : STD_LOGIC;
signal \ARG__11_n_94\ : STD_LOGIC;
signal \ARG__11_n_95\ : STD_LOGIC;
signal \ARG__11_n_96\ : STD_LOGIC;
signal \ARG__11_n_97\ : STD_LOGIC;
signal \ARG__11_n_98\ : STD_LOGIC;
signal \ARG__11_n_99\ : STD_LOGIC;
signal \ARG__12_i_1_n_0\ : STD_LOGIC;
signal \ARG__12_n_100\ : STD_LOGIC;
signal \ARG__12_n_101\ : STD_LOGIC;
signal \ARG__12_n_102\ : STD_LOGIC;
signal \ARG__12_n_103\ : STD_LOGIC;
signal \ARG__12_n_104\ : STD_LOGIC;
signal \ARG__12_n_105\ : STD_LOGIC;
signal \ARG__12_n_92\ : STD_LOGIC;
signal \ARG__12_n_93\ : STD_LOGIC;
signal \ARG__12_n_94\ : STD_LOGIC;
signal \ARG__12_n_95\ : STD_LOGIC;
signal \ARG__12_n_96\ : STD_LOGIC;
signal \ARG__12_n_97\ : STD_LOGIC;
signal \ARG__12_n_98\ : STD_LOGIC;
signal \ARG__12_n_99\ : STD_LOGIC;
signal \ARG__13_i_1_n_0\ : STD_LOGIC;
signal \ARG__13_n_100\ : STD_LOGIC;
signal \ARG__13_n_101\ : STD_LOGIC;
signal \ARG__13_n_102\ : STD_LOGIC;
signal \ARG__13_n_103\ : STD_LOGIC;
signal \ARG__13_n_104\ : STD_LOGIC;
signal \ARG__13_n_105\ : STD_LOGIC;
signal \ARG__13_n_76\ : STD_LOGIC;
signal \ARG__13_n_77\ : STD_LOGIC;
signal \ARG__13_n_78\ : STD_LOGIC;
signal \ARG__13_n_79\ : STD_LOGIC;
signal \ARG__13_n_80\ : STD_LOGIC;
signal \ARG__13_n_81\ : STD_LOGIC;
signal \ARG__13_n_82\ : STD_LOGIC;
signal \ARG__13_n_83\ : STD_LOGIC;
signal \ARG__13_n_84\ : STD_LOGIC;
signal \ARG__13_n_85\ : STD_LOGIC;
signal \ARG__13_n_86\ : STD_LOGIC;
signal \ARG__13_n_87\ : STD_LOGIC;
signal \ARG__13_n_88\ : STD_LOGIC;
signal \ARG__13_n_89\ : STD_LOGIC;
signal \ARG__13_n_90\ : STD_LOGIC;
signal \ARG__13_n_91\ : STD_LOGIC;
signal \ARG__13_n_92\ : STD_LOGIC;
signal \ARG__13_n_93\ : STD_LOGIC;
signal \ARG__13_n_94\ : STD_LOGIC;
signal \ARG__13_n_95\ : STD_LOGIC;
signal \ARG__13_n_96\ : STD_LOGIC;
signal \ARG__13_n_97\ : STD_LOGIC;
signal \ARG__13_n_98\ : STD_LOGIC;
signal \ARG__13_n_99\ : STD_LOGIC;
signal \ARG__14_i_1_n_0\ : STD_LOGIC;
signal \ARG__14_n_100\ : STD_LOGIC;
signal \ARG__14_n_101\ : STD_LOGIC;
signal \ARG__14_n_102\ : STD_LOGIC;
signal \ARG__14_n_103\ : STD_LOGIC;
signal \ARG__14_n_104\ : STD_LOGIC;
signal \ARG__14_n_105\ : STD_LOGIC;
signal \ARG__14_n_92\ : STD_LOGIC;
signal \ARG__14_n_93\ : STD_LOGIC;
signal \ARG__14_n_94\ : STD_LOGIC;
signal \ARG__14_n_95\ : STD_LOGIC;
signal \ARG__14_n_96\ : STD_LOGIC;
signal \ARG__14_n_97\ : STD_LOGIC;
signal \ARG__14_n_98\ : STD_LOGIC;
signal \ARG__14_n_99\ : STD_LOGIC;
signal \ARG__15_i_1_n_0\ : STD_LOGIC;
signal \ARG__15_n_100\ : STD_LOGIC;
signal \ARG__15_n_101\ : STD_LOGIC;
signal \ARG__15_n_102\ : STD_LOGIC;
signal \ARG__15_n_103\ : STD_LOGIC;
signal \ARG__15_n_104\ : STD_LOGIC;
signal \ARG__15_n_105\ : STD_LOGIC;
signal \ARG__15_n_76\ : STD_LOGIC;
signal \ARG__15_n_77\ : STD_LOGIC;
signal \ARG__15_n_78\ : STD_LOGIC;
signal \ARG__15_n_79\ : STD_LOGIC;
signal \ARG__15_n_80\ : STD_LOGIC;
signal \ARG__15_n_81\ : STD_LOGIC;
signal \ARG__15_n_82\ : STD_LOGIC;
signal \ARG__15_n_83\ : STD_LOGIC;
signal \ARG__15_n_84\ : STD_LOGIC;
signal \ARG__15_n_85\ : STD_LOGIC;
signal \ARG__15_n_86\ : STD_LOGIC;
signal \ARG__15_n_87\ : STD_LOGIC;
signal \ARG__15_n_88\ : STD_LOGIC;
signal \ARG__15_n_89\ : STD_LOGIC;
signal \ARG__15_n_90\ : STD_LOGIC;
signal \ARG__15_n_91\ : STD_LOGIC;
signal \ARG__15_n_92\ : STD_LOGIC;
signal \ARG__15_n_93\ : STD_LOGIC;
signal \ARG__15_n_94\ : STD_LOGIC;
signal \ARG__15_n_95\ : STD_LOGIC;
signal \ARG__15_n_96\ : STD_LOGIC;
signal \ARG__15_n_97\ : STD_LOGIC;
signal \ARG__15_n_98\ : STD_LOGIC;
signal \ARG__15_n_99\ : STD_LOGIC;
signal \ARG__16_i_1_n_0\ : STD_LOGIC;
signal \ARG__16_n_100\ : STD_LOGIC;
signal \ARG__16_n_101\ : STD_LOGIC;
signal \ARG__16_n_102\ : STD_LOGIC;
signal \ARG__16_n_103\ : STD_LOGIC;
signal \ARG__16_n_104\ : STD_LOGIC;
signal \ARG__16_n_105\ : STD_LOGIC;
signal \ARG__16_n_92\ : STD_LOGIC;
signal \ARG__16_n_93\ : STD_LOGIC;
signal \ARG__16_n_94\ : STD_LOGIC;
signal \ARG__16_n_95\ : STD_LOGIC;
signal \ARG__16_n_96\ : STD_LOGIC;
signal \ARG__16_n_97\ : STD_LOGIC;
signal \ARG__16_n_98\ : STD_LOGIC;
signal \ARG__16_n_99\ : STD_LOGIC;
signal \ARG__17_i_1_n_0\ : STD_LOGIC;
signal \ARG__17_n_100\ : STD_LOGIC;
signal \ARG__17_n_101\ : STD_LOGIC;
signal \ARG__17_n_102\ : STD_LOGIC;
signal \ARG__17_n_103\ : STD_LOGIC;
signal \ARG__17_n_104\ : STD_LOGIC;
signal \ARG__17_n_105\ : STD_LOGIC;
signal \ARG__17_n_76\ : STD_LOGIC;
signal \ARG__17_n_77\ : STD_LOGIC;
signal \ARG__17_n_78\ : STD_LOGIC;
signal \ARG__17_n_79\ : STD_LOGIC;
signal \ARG__17_n_80\ : STD_LOGIC;
signal \ARG__17_n_81\ : STD_LOGIC;
signal \ARG__17_n_82\ : STD_LOGIC;
signal \ARG__17_n_83\ : STD_LOGIC;
signal \ARG__17_n_84\ : STD_LOGIC;
signal \ARG__17_n_85\ : STD_LOGIC;
signal \ARG__17_n_86\ : STD_LOGIC;
signal \ARG__17_n_87\ : STD_LOGIC;
signal \ARG__17_n_88\ : STD_LOGIC;
signal \ARG__17_n_89\ : STD_LOGIC;
signal \ARG__17_n_90\ : STD_LOGIC;
signal \ARG__17_n_91\ : STD_LOGIC;
signal \ARG__17_n_92\ : STD_LOGIC;
signal \ARG__17_n_93\ : STD_LOGIC;
signal \ARG__17_n_94\ : STD_LOGIC;
signal \ARG__17_n_95\ : STD_LOGIC;
signal \ARG__17_n_96\ : STD_LOGIC;
signal \ARG__17_n_97\ : STD_LOGIC;
signal \ARG__17_n_98\ : STD_LOGIC;
signal \ARG__17_n_99\ : STD_LOGIC;
signal \ARG__18_i_1_n_0\ : STD_LOGIC;
signal \ARG__18_n_100\ : STD_LOGIC;
signal \ARG__18_n_101\ : STD_LOGIC;
signal \ARG__18_n_102\ : STD_LOGIC;
signal \ARG__18_n_103\ : STD_LOGIC;
signal \ARG__18_n_104\ : STD_LOGIC;
signal \ARG__18_n_105\ : STD_LOGIC;
signal \ARG__18_n_92\ : STD_LOGIC;
signal \ARG__18_n_93\ : STD_LOGIC;
signal \ARG__18_n_94\ : STD_LOGIC;
signal \ARG__18_n_95\ : STD_LOGIC;
signal \ARG__18_n_96\ : STD_LOGIC;
signal \ARG__18_n_97\ : STD_LOGIC;
signal \ARG__18_n_98\ : STD_LOGIC;
signal \ARG__18_n_99\ : STD_LOGIC;
signal \ARG__19_i_1_n_0\ : STD_LOGIC;
signal \ARG__19_n_100\ : STD_LOGIC;
signal \ARG__19_n_101\ : STD_LOGIC;
signal \ARG__19_n_102\ : STD_LOGIC;
signal \ARG__19_n_103\ : STD_LOGIC;
signal \ARG__19_n_104\ : STD_LOGIC;
signal \ARG__19_n_105\ : STD_LOGIC;
signal \ARG__19_n_76\ : STD_LOGIC;
signal \ARG__19_n_77\ : STD_LOGIC;
signal \ARG__19_n_78\ : STD_LOGIC;
signal \ARG__19_n_79\ : STD_LOGIC;
signal \ARG__19_n_80\ : STD_LOGIC;
signal \ARG__19_n_81\ : STD_LOGIC;
signal \ARG__19_n_82\ : STD_LOGIC;
signal \ARG__19_n_83\ : STD_LOGIC;
signal \ARG__19_n_84\ : STD_LOGIC;
signal \ARG__19_n_85\ : STD_LOGIC;
signal \ARG__19_n_86\ : STD_LOGIC;
signal \ARG__19_n_87\ : STD_LOGIC;
signal \ARG__19_n_88\ : STD_LOGIC;
signal \ARG__19_n_89\ : STD_LOGIC;
signal \ARG__19_n_90\ : STD_LOGIC;
signal \ARG__19_n_91\ : STD_LOGIC;
signal \ARG__19_n_92\ : STD_LOGIC;
signal \ARG__19_n_93\ : STD_LOGIC;
signal \ARG__19_n_94\ : STD_LOGIC;
signal \ARG__19_n_95\ : STD_LOGIC;
signal \ARG__19_n_96\ : STD_LOGIC;
signal \ARG__19_n_97\ : STD_LOGIC;
signal \ARG__19_n_98\ : STD_LOGIC;
signal \ARG__19_n_99\ : STD_LOGIC;
signal \ARG__1_i_1_n_0\ : STD_LOGIC;
signal \ARG__1_n_100\ : STD_LOGIC;
signal \ARG__1_n_101\ : STD_LOGIC;
signal \ARG__1_n_102\ : STD_LOGIC;
signal \ARG__1_n_103\ : STD_LOGIC;
signal \ARG__1_n_104\ : STD_LOGIC;
signal \ARG__1_n_105\ : STD_LOGIC;
signal \ARG__1_n_76\ : STD_LOGIC;
signal \ARG__1_n_77\ : STD_LOGIC;
signal \ARG__1_n_78\ : STD_LOGIC;
signal \ARG__1_n_79\ : STD_LOGIC;
signal \ARG__1_n_80\ : STD_LOGIC;
signal \ARG__1_n_81\ : STD_LOGIC;
signal \ARG__1_n_82\ : STD_LOGIC;
signal \ARG__1_n_83\ : STD_LOGIC;
signal \ARG__1_n_84\ : STD_LOGIC;
signal \ARG__1_n_85\ : STD_LOGIC;
signal \ARG__1_n_86\ : STD_LOGIC;
signal \ARG__1_n_87\ : STD_LOGIC;
signal \ARG__1_n_88\ : STD_LOGIC;
signal \ARG__1_n_89\ : STD_LOGIC;
signal \ARG__1_n_90\ : STD_LOGIC;
signal \ARG__1_n_91\ : STD_LOGIC;
signal \ARG__1_n_92\ : STD_LOGIC;
signal \ARG__1_n_93\ : STD_LOGIC;
signal \ARG__1_n_94\ : STD_LOGIC;
signal \ARG__1_n_95\ : STD_LOGIC;
signal \ARG__1_n_96\ : STD_LOGIC;
signal \ARG__1_n_97\ : STD_LOGIC;
signal \ARG__1_n_98\ : STD_LOGIC;
signal \ARG__1_n_99\ : STD_LOGIC;
signal \ARG__20_i_1_n_0\ : STD_LOGIC;
signal \ARG__20_n_100\ : STD_LOGIC;
signal \ARG__20_n_101\ : STD_LOGIC;
signal \ARG__20_n_102\ : STD_LOGIC;
signal \ARG__20_n_103\ : STD_LOGIC;
signal \ARG__20_n_104\ : STD_LOGIC;
signal \ARG__20_n_105\ : STD_LOGIC;
signal \ARG__20_n_92\ : STD_LOGIC;
signal \ARG__20_n_93\ : STD_LOGIC;
signal \ARG__20_n_94\ : STD_LOGIC;
signal \ARG__20_n_95\ : STD_LOGIC;
signal \ARG__20_n_96\ : STD_LOGIC;
signal \ARG__20_n_97\ : STD_LOGIC;
signal \ARG__20_n_98\ : STD_LOGIC;
signal \ARG__20_n_99\ : STD_LOGIC;
signal \ARG__21_i_1_n_0\ : STD_LOGIC;
signal \ARG__21_n_100\ : STD_LOGIC;
signal \ARG__21_n_101\ : STD_LOGIC;
signal \ARG__21_n_102\ : STD_LOGIC;
signal \ARG__21_n_103\ : STD_LOGIC;
signal \ARG__21_n_104\ : STD_LOGIC;
signal \ARG__21_n_105\ : STD_LOGIC;
signal \ARG__21_n_76\ : STD_LOGIC;
signal \ARG__21_n_77\ : STD_LOGIC;
signal \ARG__21_n_78\ : STD_LOGIC;
signal \ARG__21_n_79\ : STD_LOGIC;
signal \ARG__21_n_80\ : STD_LOGIC;
signal \ARG__21_n_81\ : STD_LOGIC;
signal \ARG__21_n_82\ : STD_LOGIC;
signal \ARG__21_n_83\ : STD_LOGIC;
signal \ARG__21_n_84\ : STD_LOGIC;
signal \ARG__21_n_85\ : STD_LOGIC;
signal \ARG__21_n_86\ : STD_LOGIC;
signal \ARG__21_n_87\ : STD_LOGIC;
signal \ARG__21_n_88\ : STD_LOGIC;
signal \ARG__21_n_89\ : STD_LOGIC;
signal \ARG__21_n_90\ : STD_LOGIC;
signal \ARG__21_n_91\ : STD_LOGIC;
signal \ARG__21_n_92\ : STD_LOGIC;
signal \ARG__21_n_93\ : STD_LOGIC;
signal \ARG__21_n_94\ : STD_LOGIC;
signal \ARG__21_n_95\ : STD_LOGIC;
signal \ARG__21_n_96\ : STD_LOGIC;
signal \ARG__21_n_97\ : STD_LOGIC;
signal \ARG__21_n_98\ : STD_LOGIC;
signal \ARG__21_n_99\ : STD_LOGIC;
signal \ARG__22_i_1_n_0\ : STD_LOGIC;
signal \ARG__22_n_100\ : STD_LOGIC;
signal \ARG__22_n_101\ : STD_LOGIC;
signal \ARG__22_n_102\ : STD_LOGIC;
signal \ARG__22_n_103\ : STD_LOGIC;
signal \ARG__22_n_104\ : STD_LOGIC;
signal \ARG__22_n_105\ : STD_LOGIC;
signal \ARG__22_n_92\ : STD_LOGIC;
signal \ARG__22_n_93\ : STD_LOGIC;
signal \ARG__22_n_94\ : STD_LOGIC;
signal \ARG__22_n_95\ : STD_LOGIC;
signal \ARG__22_n_96\ : STD_LOGIC;
signal \ARG__22_n_97\ : STD_LOGIC;
signal \ARG__22_n_98\ : STD_LOGIC;
signal \ARG__22_n_99\ : STD_LOGIC;
signal \ARG__23_i_1_n_0\ : STD_LOGIC;
signal \ARG__23_n_100\ : STD_LOGIC;
signal \ARG__23_n_101\ : STD_LOGIC;
signal \ARG__23_n_102\ : STD_LOGIC;
signal \ARG__23_n_103\ : STD_LOGIC;
signal \ARG__23_n_104\ : STD_LOGIC;
signal \ARG__23_n_105\ : STD_LOGIC;
signal \ARG__23_n_76\ : STD_LOGIC;
signal \ARG__23_n_77\ : STD_LOGIC;
signal \ARG__23_n_78\ : STD_LOGIC;
signal \ARG__23_n_79\ : STD_LOGIC;
signal \ARG__23_n_80\ : STD_LOGIC;
signal \ARG__23_n_81\ : STD_LOGIC;
signal \ARG__23_n_82\ : STD_LOGIC;
signal \ARG__23_n_83\ : STD_LOGIC;
signal \ARG__23_n_84\ : STD_LOGIC;
signal \ARG__23_n_85\ : STD_LOGIC;
signal \ARG__23_n_86\ : STD_LOGIC;
signal \ARG__23_n_87\ : STD_LOGIC;
signal \ARG__23_n_88\ : STD_LOGIC;
signal \ARG__23_n_89\ : STD_LOGIC;
signal \ARG__23_n_90\ : STD_LOGIC;
signal \ARG__23_n_91\ : STD_LOGIC;
signal \ARG__23_n_92\ : STD_LOGIC;
signal \ARG__23_n_93\ : STD_LOGIC;
signal \ARG__23_n_94\ : STD_LOGIC;
signal \ARG__23_n_95\ : STD_LOGIC;
signal \ARG__23_n_96\ : STD_LOGIC;
signal \ARG__23_n_97\ : STD_LOGIC;
signal \ARG__23_n_98\ : STD_LOGIC;
signal \ARG__23_n_99\ : STD_LOGIC;
signal \ARG__24_i_1_n_0\ : STD_LOGIC;
signal \ARG__24_n_100\ : STD_LOGIC;
signal \ARG__24_n_101\ : STD_LOGIC;
signal \ARG__24_n_102\ : STD_LOGIC;
signal \ARG__24_n_103\ : STD_LOGIC;
signal \ARG__24_n_104\ : STD_LOGIC;
signal \ARG__24_n_105\ : STD_LOGIC;
signal \ARG__24_n_92\ : STD_LOGIC;
signal \ARG__24_n_93\ : STD_LOGIC;
signal \ARG__24_n_94\ : STD_LOGIC;
signal \ARG__24_n_95\ : STD_LOGIC;
signal \ARG__24_n_96\ : STD_LOGIC;
signal \ARG__24_n_97\ : STD_LOGIC;
signal \ARG__24_n_98\ : STD_LOGIC;
signal \ARG__24_n_99\ : STD_LOGIC;
signal \ARG__25_i_1_n_0\ : STD_LOGIC;
signal \ARG__25_n_100\ : STD_LOGIC;
signal \ARG__25_n_101\ : STD_LOGIC;
signal \ARG__25_n_102\ : STD_LOGIC;
signal \ARG__25_n_103\ : STD_LOGIC;
signal \ARG__25_n_104\ : STD_LOGIC;
signal \ARG__25_n_105\ : STD_LOGIC;
signal \ARG__25_n_76\ : STD_LOGIC;
signal \ARG__25_n_77\ : STD_LOGIC;
signal \ARG__25_n_78\ : STD_LOGIC;
signal \ARG__25_n_79\ : STD_LOGIC;
signal \ARG__25_n_80\ : STD_LOGIC;
signal \ARG__25_n_81\ : STD_LOGIC;
signal \ARG__25_n_82\ : STD_LOGIC;
signal \ARG__25_n_83\ : STD_LOGIC;
signal \ARG__25_n_84\ : STD_LOGIC;
signal \ARG__25_n_85\ : STD_LOGIC;
signal \ARG__25_n_86\ : STD_LOGIC;
signal \ARG__25_n_87\ : STD_LOGIC;
signal \ARG__25_n_88\ : STD_LOGIC;
signal \ARG__25_n_89\ : STD_LOGIC;
signal \ARG__25_n_90\ : STD_LOGIC;
signal \ARG__25_n_91\ : STD_LOGIC;
signal \ARG__25_n_92\ : STD_LOGIC;
signal \ARG__25_n_93\ : STD_LOGIC;
signal \ARG__25_n_94\ : STD_LOGIC;
signal \ARG__25_n_95\ : STD_LOGIC;
signal \ARG__25_n_96\ : STD_LOGIC;
signal \ARG__25_n_97\ : STD_LOGIC;
signal \ARG__25_n_98\ : STD_LOGIC;
signal \ARG__25_n_99\ : STD_LOGIC;
signal \ARG__26_i_1_n_0\ : STD_LOGIC;
signal \ARG__26_n_100\ : STD_LOGIC;
signal \ARG__26_n_101\ : STD_LOGIC;
signal \ARG__26_n_102\ : STD_LOGIC;
signal \ARG__26_n_103\ : STD_LOGIC;
signal \ARG__26_n_104\ : STD_LOGIC;
signal \ARG__26_n_105\ : STD_LOGIC;
signal \ARG__26_n_92\ : STD_LOGIC;
signal \ARG__26_n_93\ : STD_LOGIC;
signal \ARG__26_n_94\ : STD_LOGIC;
signal \ARG__26_n_95\ : STD_LOGIC;
signal \ARG__26_n_96\ : STD_LOGIC;
signal \ARG__26_n_97\ : STD_LOGIC;
signal \ARG__26_n_98\ : STD_LOGIC;
signal \ARG__26_n_99\ : STD_LOGIC;
signal \ARG__27_i_1_n_0\ : STD_LOGIC;
signal \ARG__27_n_100\ : STD_LOGIC;
signal \ARG__27_n_101\ : STD_LOGIC;
signal \ARG__27_n_102\ : STD_LOGIC;
signal \ARG__27_n_103\ : STD_LOGIC;
signal \ARG__27_n_104\ : STD_LOGIC;
signal \ARG__27_n_105\ : STD_LOGIC;
signal \ARG__27_n_76\ : STD_LOGIC;
signal \ARG__27_n_77\ : STD_LOGIC;
signal \ARG__27_n_78\ : STD_LOGIC;
signal \ARG__27_n_79\ : STD_LOGIC;
signal \ARG__27_n_80\ : STD_LOGIC;
signal \ARG__27_n_81\ : STD_LOGIC;
signal \ARG__27_n_82\ : STD_LOGIC;
signal \ARG__27_n_83\ : STD_LOGIC;
signal \ARG__27_n_84\ : STD_LOGIC;
signal \ARG__27_n_85\ : STD_LOGIC;
signal \ARG__27_n_86\ : STD_LOGIC;
signal \ARG__27_n_87\ : STD_LOGIC;
signal \ARG__27_n_88\ : STD_LOGIC;
signal \ARG__27_n_89\ : STD_LOGIC;
signal \ARG__27_n_90\ : STD_LOGIC;
signal \ARG__27_n_91\ : STD_LOGIC;
signal \ARG__27_n_92\ : STD_LOGIC;
signal \ARG__27_n_93\ : STD_LOGIC;
signal \ARG__27_n_94\ : STD_LOGIC;
signal \ARG__27_n_95\ : STD_LOGIC;
signal \ARG__27_n_96\ : STD_LOGIC;
signal \ARG__27_n_97\ : STD_LOGIC;
signal \ARG__27_n_98\ : STD_LOGIC;
signal \ARG__27_n_99\ : STD_LOGIC;
signal \ARG__28_i_1_n_0\ : STD_LOGIC;
signal \ARG__28_n_100\ : STD_LOGIC;
signal \ARG__28_n_101\ : STD_LOGIC;
signal \ARG__28_n_102\ : STD_LOGIC;
signal \ARG__28_n_103\ : STD_LOGIC;
signal \ARG__28_n_104\ : STD_LOGIC;
signal \ARG__28_n_105\ : STD_LOGIC;
signal \ARG__28_n_92\ : STD_LOGIC;
signal \ARG__28_n_93\ : STD_LOGIC;
signal \ARG__28_n_94\ : STD_LOGIC;
signal \ARG__28_n_95\ : STD_LOGIC;
signal \ARG__28_n_96\ : STD_LOGIC;
signal \ARG__28_n_97\ : STD_LOGIC;
signal \ARG__28_n_98\ : STD_LOGIC;
signal \ARG__28_n_99\ : STD_LOGIC;
signal \ARG__29_i_1_n_0\ : STD_LOGIC;
signal \ARG__29_n_100\ : STD_LOGIC;
signal \ARG__29_n_101\ : STD_LOGIC;
signal \ARG__29_n_102\ : STD_LOGIC;
signal \ARG__29_n_103\ : STD_LOGIC;
signal \ARG__29_n_104\ : STD_LOGIC;
signal \ARG__29_n_105\ : STD_LOGIC;
signal \ARG__29_n_76\ : STD_LOGIC;
signal \ARG__29_n_77\ : STD_LOGIC;
signal \ARG__29_n_78\ : STD_LOGIC;
signal \ARG__29_n_79\ : STD_LOGIC;
signal \ARG__29_n_80\ : STD_LOGIC;
signal \ARG__29_n_81\ : STD_LOGIC;
signal \ARG__29_n_82\ : STD_LOGIC;
signal \ARG__29_n_83\ : STD_LOGIC;
signal \ARG__29_n_84\ : STD_LOGIC;
signal \ARG__29_n_85\ : STD_LOGIC;
signal \ARG__29_n_86\ : STD_LOGIC;
signal \ARG__29_n_87\ : STD_LOGIC;
signal \ARG__29_n_88\ : STD_LOGIC;
signal \ARG__29_n_89\ : STD_LOGIC;
signal \ARG__29_n_90\ : STD_LOGIC;
signal \ARG__29_n_91\ : STD_LOGIC;
signal \ARG__29_n_92\ : STD_LOGIC;
signal \ARG__29_n_93\ : STD_LOGIC;
signal \ARG__29_n_94\ : STD_LOGIC;
signal \ARG__29_n_95\ : STD_LOGIC;
signal \ARG__29_n_96\ : STD_LOGIC;
signal \ARG__29_n_97\ : STD_LOGIC;
signal \ARG__29_n_98\ : STD_LOGIC;
signal \ARG__29_n_99\ : STD_LOGIC;
signal \ARG__2_i_1_n_0\ : STD_LOGIC;
signal \ARG__2_n_100\ : STD_LOGIC;
signal \ARG__2_n_101\ : STD_LOGIC;
signal \ARG__2_n_102\ : STD_LOGIC;
signal \ARG__2_n_103\ : STD_LOGIC;
signal \ARG__2_n_104\ : STD_LOGIC;
signal \ARG__2_n_105\ : STD_LOGIC;
signal \ARG__2_n_92\ : STD_LOGIC;
signal \ARG__2_n_93\ : STD_LOGIC;
signal \ARG__2_n_94\ : STD_LOGIC;
signal \ARG__2_n_95\ : STD_LOGIC;
signal \ARG__2_n_96\ : STD_LOGIC;
signal \ARG__2_n_97\ : STD_LOGIC;
signal \ARG__2_n_98\ : STD_LOGIC;
signal \ARG__2_n_99\ : STD_LOGIC;
signal \ARG__30_i_1_n_0\ : STD_LOGIC;
signal \ARG__30_n_100\ : STD_LOGIC;
signal \ARG__30_n_101\ : STD_LOGIC;
signal \ARG__30_n_102\ : STD_LOGIC;
signal \ARG__30_n_103\ : STD_LOGIC;
signal \ARG__30_n_104\ : STD_LOGIC;
signal \ARG__30_n_105\ : STD_LOGIC;
signal \ARG__30_n_92\ : STD_LOGIC;
signal \ARG__30_n_93\ : STD_LOGIC;
signal \ARG__30_n_94\ : STD_LOGIC;
signal \ARG__30_n_95\ : STD_LOGIC;
signal \ARG__30_n_96\ : STD_LOGIC;
signal \ARG__30_n_97\ : STD_LOGIC;
signal \ARG__30_n_98\ : STD_LOGIC;
signal \ARG__30_n_99\ : STD_LOGIC;
signal \ARG__31\ : STD_LOGIC_VECTOR ( 32 downto 17 );
signal \ARG__3_i_1_n_0\ : STD_LOGIC;
signal \ARG__3_n_100\ : STD_LOGIC;
signal \ARG__3_n_101\ : STD_LOGIC;
signal \ARG__3_n_102\ : STD_LOGIC;
signal \ARG__3_n_103\ : STD_LOGIC;
signal \ARG__3_n_104\ : STD_LOGIC;
signal \ARG__3_n_105\ : STD_LOGIC;
signal \ARG__3_n_76\ : STD_LOGIC;
signal \ARG__3_n_77\ : STD_LOGIC;
signal \ARG__3_n_78\ : STD_LOGIC;
signal \ARG__3_n_79\ : STD_LOGIC;
signal \ARG__3_n_80\ : STD_LOGIC;
signal \ARG__3_n_81\ : STD_LOGIC;
signal \ARG__3_n_82\ : STD_LOGIC;
signal \ARG__3_n_83\ : STD_LOGIC;
signal \ARG__3_n_84\ : STD_LOGIC;
signal \ARG__3_n_85\ : STD_LOGIC;
signal \ARG__3_n_86\ : STD_LOGIC;
signal \ARG__3_n_87\ : STD_LOGIC;
signal \ARG__3_n_88\ : STD_LOGIC;
signal \ARG__3_n_89\ : STD_LOGIC;
signal \ARG__3_n_90\ : STD_LOGIC;
signal \ARG__3_n_91\ : STD_LOGIC;
signal \ARG__3_n_92\ : STD_LOGIC;
signal \ARG__3_n_93\ : STD_LOGIC;
signal \ARG__3_n_94\ : STD_LOGIC;
signal \ARG__3_n_95\ : STD_LOGIC;
signal \ARG__3_n_96\ : STD_LOGIC;
signal \ARG__3_n_97\ : STD_LOGIC;
signal \ARG__3_n_98\ : STD_LOGIC;
signal \ARG__3_n_99\ : STD_LOGIC;
signal \ARG__4_i_1_n_0\ : STD_LOGIC;
signal \ARG__4_n_100\ : STD_LOGIC;
signal \ARG__4_n_101\ : STD_LOGIC;
signal \ARG__4_n_102\ : STD_LOGIC;
signal \ARG__4_n_103\ : STD_LOGIC;
signal \ARG__4_n_104\ : STD_LOGIC;
signal \ARG__4_n_105\ : STD_LOGIC;
signal \ARG__4_n_92\ : STD_LOGIC;
signal \ARG__4_n_93\ : STD_LOGIC;
signal \ARG__4_n_94\ : STD_LOGIC;
signal \ARG__4_n_95\ : STD_LOGIC;
signal \ARG__4_n_96\ : STD_LOGIC;
signal \ARG__4_n_97\ : STD_LOGIC;
signal \ARG__4_n_98\ : STD_LOGIC;
signal \ARG__4_n_99\ : STD_LOGIC;
signal \ARG__5_i_1_n_0\ : STD_LOGIC;
signal \ARG__5_n_100\ : STD_LOGIC;
signal \ARG__5_n_101\ : STD_LOGIC;
signal \ARG__5_n_102\ : STD_LOGIC;
signal \ARG__5_n_103\ : STD_LOGIC;
signal \ARG__5_n_104\ : STD_LOGIC;
signal \ARG__5_n_105\ : STD_LOGIC;
signal \ARG__5_n_76\ : STD_LOGIC;
signal \ARG__5_n_77\ : STD_LOGIC;
signal \ARG__5_n_78\ : STD_LOGIC;
signal \ARG__5_n_79\ : STD_LOGIC;
signal \ARG__5_n_80\ : STD_LOGIC;
signal \ARG__5_n_81\ : STD_LOGIC;
signal \ARG__5_n_82\ : STD_LOGIC;
signal \ARG__5_n_83\ : STD_LOGIC;
signal \ARG__5_n_84\ : STD_LOGIC;
signal \ARG__5_n_85\ : STD_LOGIC;
signal \ARG__5_n_86\ : STD_LOGIC;
signal \ARG__5_n_87\ : STD_LOGIC;
signal \ARG__5_n_88\ : STD_LOGIC;
signal \ARG__5_n_89\ : STD_LOGIC;
signal \ARG__5_n_90\ : STD_LOGIC;
signal \ARG__5_n_91\ : STD_LOGIC;
signal \ARG__5_n_92\ : STD_LOGIC;
signal \ARG__5_n_93\ : STD_LOGIC;
signal \ARG__5_n_94\ : STD_LOGIC;
signal \ARG__5_n_95\ : STD_LOGIC;
signal \ARG__5_n_96\ : STD_LOGIC;
signal \ARG__5_n_97\ : STD_LOGIC;
signal \ARG__5_n_98\ : STD_LOGIC;
signal \ARG__5_n_99\ : STD_LOGIC;
signal \ARG__6_i_1_n_0\ : STD_LOGIC;
signal \ARG__6_n_100\ : STD_LOGIC;
signal \ARG__6_n_101\ : STD_LOGIC;
signal \ARG__6_n_102\ : STD_LOGIC;
signal \ARG__6_n_103\ : STD_LOGIC;
signal \ARG__6_n_104\ : STD_LOGIC;
signal \ARG__6_n_105\ : STD_LOGIC;
signal \ARG__6_n_92\ : STD_LOGIC;
signal \ARG__6_n_93\ : STD_LOGIC;
signal \ARG__6_n_94\ : STD_LOGIC;
signal \ARG__6_n_95\ : STD_LOGIC;
signal \ARG__6_n_96\ : STD_LOGIC;
signal \ARG__6_n_97\ : STD_LOGIC;
signal \ARG__6_n_98\ : STD_LOGIC;
signal \ARG__6_n_99\ : STD_LOGIC;
signal \ARG__7_i_1_n_0\ : STD_LOGIC;
signal \ARG__7_n_100\ : STD_LOGIC;
signal \ARG__7_n_101\ : STD_LOGIC;
signal \ARG__7_n_102\ : STD_LOGIC;
signal \ARG__7_n_103\ : STD_LOGIC;
signal \ARG__7_n_104\ : STD_LOGIC;
signal \ARG__7_n_105\ : STD_LOGIC;
signal \ARG__7_n_76\ : STD_LOGIC;
signal \ARG__7_n_77\ : STD_LOGIC;
signal \ARG__7_n_78\ : STD_LOGIC;
signal \ARG__7_n_79\ : STD_LOGIC;
signal \ARG__7_n_80\ : STD_LOGIC;
signal \ARG__7_n_81\ : STD_LOGIC;
signal \ARG__7_n_82\ : STD_LOGIC;
signal \ARG__7_n_83\ : STD_LOGIC;
signal \ARG__7_n_84\ : STD_LOGIC;
signal \ARG__7_n_85\ : STD_LOGIC;
signal \ARG__7_n_86\ : STD_LOGIC;
signal \ARG__7_n_87\ : STD_LOGIC;
signal \ARG__7_n_88\ : STD_LOGIC;
signal \ARG__7_n_89\ : STD_LOGIC;
signal \ARG__7_n_90\ : STD_LOGIC;
signal \ARG__7_n_91\ : STD_LOGIC;
signal \ARG__7_n_92\ : STD_LOGIC;
signal \ARG__7_n_93\ : STD_LOGIC;
signal \ARG__7_n_94\ : STD_LOGIC;
signal \ARG__7_n_95\ : STD_LOGIC;
signal \ARG__7_n_96\ : STD_LOGIC;
signal \ARG__7_n_97\ : STD_LOGIC;
signal \ARG__7_n_98\ : STD_LOGIC;
signal \ARG__7_n_99\ : STD_LOGIC;
signal \ARG__8_i_1_n_0\ : STD_LOGIC;
signal \ARG__8_n_100\ : STD_LOGIC;
signal \ARG__8_n_101\ : STD_LOGIC;
signal \ARG__8_n_102\ : STD_LOGIC;
signal \ARG__8_n_103\ : STD_LOGIC;
signal \ARG__8_n_104\ : STD_LOGIC;
signal \ARG__8_n_105\ : STD_LOGIC;
signal \ARG__8_n_92\ : STD_LOGIC;
signal \ARG__8_n_93\ : STD_LOGIC;
signal \ARG__8_n_94\ : STD_LOGIC;
signal \ARG__8_n_95\ : STD_LOGIC;
signal \ARG__8_n_96\ : STD_LOGIC;
signal \ARG__8_n_97\ : STD_LOGIC;
signal \ARG__8_n_98\ : STD_LOGIC;
signal \ARG__8_n_99\ : STD_LOGIC;
signal \ARG__9_i_1_n_0\ : STD_LOGIC;
signal \ARG__9_n_100\ : STD_LOGIC;
signal \ARG__9_n_101\ : STD_LOGIC;
signal \ARG__9_n_102\ : STD_LOGIC;
signal \ARG__9_n_103\ : STD_LOGIC;
signal \ARG__9_n_104\ : STD_LOGIC;
signal \ARG__9_n_105\ : STD_LOGIC;
signal \ARG__9_n_76\ : STD_LOGIC;
signal \ARG__9_n_77\ : STD_LOGIC;
signal \ARG__9_n_78\ : STD_LOGIC;
signal \ARG__9_n_79\ : STD_LOGIC;
signal \ARG__9_n_80\ : STD_LOGIC;
signal \ARG__9_n_81\ : STD_LOGIC;
signal \ARG__9_n_82\ : STD_LOGIC;
signal \ARG__9_n_83\ : STD_LOGIC;
signal \ARG__9_n_84\ : STD_LOGIC;
signal \ARG__9_n_85\ : STD_LOGIC;
signal \ARG__9_n_86\ : STD_LOGIC;
signal \ARG__9_n_87\ : STD_LOGIC;
signal \ARG__9_n_88\ : STD_LOGIC;
signal \ARG__9_n_89\ : STD_LOGIC;
signal \ARG__9_n_90\ : STD_LOGIC;
signal \ARG__9_n_91\ : STD_LOGIC;
signal \ARG__9_n_92\ : STD_LOGIC;
signal \ARG__9_n_93\ : STD_LOGIC;
signal \ARG__9_n_94\ : STD_LOGIC;
signal \ARG__9_n_95\ : STD_LOGIC;
signal \ARG__9_n_96\ : STD_LOGIC;
signal \ARG__9_n_97\ : STD_LOGIC;
signal \ARG__9_n_98\ : STD_LOGIC;
signal \ARG__9_n_99\ : STD_LOGIC;
signal \ARG_carry__0_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__0_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__0_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__0_n_0\ : STD_LOGIC;
signal \ARG_carry__0_n_1\ : STD_LOGIC;
signal \ARG_carry__0_n_2\ : STD_LOGIC;
signal \ARG_carry__0_n_3\ : STD_LOGIC;
signal \ARG_carry__1_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__1_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__1_n_0\ : STD_LOGIC;
signal \ARG_carry__1_n_1\ : STD_LOGIC;
signal \ARG_carry__1_n_2\ : STD_LOGIC;
signal \ARG_carry__1_n_3\ : STD_LOGIC;
signal \ARG_carry__2_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_2_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_3_n_0\ : STD_LOGIC;
signal \ARG_carry__2_i_4_n_0\ : STD_LOGIC;
signal \ARG_carry__2_n_0\ : STD_LOGIC;
signal \ARG_carry__2_n_1\ : STD_LOGIC;
signal \ARG_carry__2_n_2\ : STD_LOGIC;
signal \ARG_carry__2_n_3\ : STD_LOGIC;
signal \ARG_carry__3_i_1_n_0\ : STD_LOGIC;
signal \ARG_carry__3_n_3\ : STD_LOGIC;
signal ARG_carry_n_0 : STD_LOGIC;
signal ARG_carry_n_1 : STD_LOGIC;
signal ARG_carry_n_2 : STD_LOGIC;
signal ARG_carry_n_3 : STD_LOGIC;
signal ARG_i_1_n_0 : STD_LOGIC;
signal ARG_n_100 : STD_LOGIC;
signal ARG_n_101 : STD_LOGIC;
signal ARG_n_102 : STD_LOGIC;
signal ARG_n_103 : STD_LOGIC;
signal ARG_n_104 : STD_LOGIC;
signal ARG_n_105 : STD_LOGIC;
signal ARG_n_92 : STD_LOGIC;
signal ARG_n_93 : STD_LOGIC;
signal ARG_n_94 : STD_LOGIC;
signal ARG_n_95 : STD_LOGIC;
signal ARG_n_96 : STD_LOGIC;
signal ARG_n_97 : STD_LOGIC;
signal ARG_n_98 : STD_LOGIC;
signal ARG_n_99 : STD_LOGIC;
signal RESIZE15 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE16 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE18 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE20 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE22 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE24 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE26 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE28 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE30 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE32 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE34 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE36 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE38 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE40 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE42 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal RESIZE44 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \add_temp_14__0_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__0_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__138_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__184_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__230_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_12_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_12_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_11_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_10_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_i_9_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__278_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__46_carry_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__0_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_i_8_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__1_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry__2_n_7\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_1_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_2_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_3_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_4_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_5_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_6_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_i_7_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_0\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_1\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_2\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_3\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_4\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_5\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_6\ : STD_LOGIC;
signal \add_temp_14__92_carry_n_7\ : STD_LOGIC;
signal \data_pipeline_tmp_reg[0]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[10]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[11]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[12]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[13]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[14]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[1]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[2]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[3]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[4]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[5]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[6]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[7]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[8]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \data_pipeline_tmp_reg[9]\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \in\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^mul_temp\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_1\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_10\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_10_n_100 : STD_LOGIC;
signal mul_temp_10_n_101 : STD_LOGIC;
signal mul_temp_10_n_102 : STD_LOGIC;
signal mul_temp_10_n_103 : STD_LOGIC;
signal mul_temp_10_n_104 : STD_LOGIC;
signal mul_temp_10_n_105 : STD_LOGIC;
signal mul_temp_10_n_74 : STD_LOGIC;
signal mul_temp_10_n_75 : STD_LOGIC;
signal mul_temp_10_n_76 : STD_LOGIC;
signal mul_temp_10_n_77 : STD_LOGIC;
signal mul_temp_10_n_78 : STD_LOGIC;
signal mul_temp_10_n_79 : STD_LOGIC;
signal mul_temp_10_n_80 : STD_LOGIC;
signal mul_temp_10_n_81 : STD_LOGIC;
signal mul_temp_10_n_82 : STD_LOGIC;
signal mul_temp_10_n_83 : STD_LOGIC;
signal mul_temp_10_n_84 : STD_LOGIC;
signal mul_temp_10_n_85 : STD_LOGIC;
signal mul_temp_10_n_86 : STD_LOGIC;
signal mul_temp_10_n_87 : STD_LOGIC;
signal mul_temp_10_n_88 : STD_LOGIC;
signal mul_temp_10_n_89 : STD_LOGIC;
signal mul_temp_10_n_90 : STD_LOGIC;
signal mul_temp_10_n_92 : STD_LOGIC;
signal mul_temp_10_n_93 : STD_LOGIC;
signal mul_temp_10_n_94 : STD_LOGIC;
signal mul_temp_10_n_95 : STD_LOGIC;
signal mul_temp_10_n_96 : STD_LOGIC;
signal mul_temp_10_n_97 : STD_LOGIC;
signal mul_temp_10_n_98 : STD_LOGIC;
signal mul_temp_10_n_99 : STD_LOGIC;
signal \^mul_temp_11\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_11_n_100 : STD_LOGIC;
signal mul_temp_11_n_101 : STD_LOGIC;
signal mul_temp_11_n_102 : STD_LOGIC;
signal mul_temp_11_n_103 : STD_LOGIC;
signal mul_temp_11_n_104 : STD_LOGIC;
signal mul_temp_11_n_105 : STD_LOGIC;
signal mul_temp_11_n_74 : STD_LOGIC;
signal mul_temp_11_n_75 : STD_LOGIC;
signal mul_temp_11_n_76 : STD_LOGIC;
signal mul_temp_11_n_77 : STD_LOGIC;
signal mul_temp_11_n_78 : STD_LOGIC;
signal mul_temp_11_n_79 : STD_LOGIC;
signal mul_temp_11_n_80 : STD_LOGIC;
signal mul_temp_11_n_81 : STD_LOGIC;
signal mul_temp_11_n_82 : STD_LOGIC;
signal mul_temp_11_n_83 : STD_LOGIC;
signal mul_temp_11_n_84 : STD_LOGIC;
signal mul_temp_11_n_85 : STD_LOGIC;
signal mul_temp_11_n_86 : STD_LOGIC;
signal mul_temp_11_n_87 : STD_LOGIC;
signal mul_temp_11_n_88 : STD_LOGIC;
signal mul_temp_11_n_89 : STD_LOGIC;
signal mul_temp_11_n_90 : STD_LOGIC;
signal mul_temp_11_n_92 : STD_LOGIC;
signal mul_temp_11_n_93 : STD_LOGIC;
signal mul_temp_11_n_94 : STD_LOGIC;
signal mul_temp_11_n_95 : STD_LOGIC;
signal mul_temp_11_n_96 : STD_LOGIC;
signal mul_temp_11_n_97 : STD_LOGIC;
signal mul_temp_11_n_98 : STD_LOGIC;
signal mul_temp_11_n_99 : STD_LOGIC;
signal \^mul_temp_12\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_12_n_100 : STD_LOGIC;
signal mul_temp_12_n_101 : STD_LOGIC;
signal mul_temp_12_n_102 : STD_LOGIC;
signal mul_temp_12_n_103 : STD_LOGIC;
signal mul_temp_12_n_104 : STD_LOGIC;
signal mul_temp_12_n_105 : STD_LOGIC;
signal mul_temp_12_n_74 : STD_LOGIC;
signal mul_temp_12_n_75 : STD_LOGIC;
signal mul_temp_12_n_76 : STD_LOGIC;
signal mul_temp_12_n_77 : STD_LOGIC;
signal mul_temp_12_n_78 : STD_LOGIC;
signal mul_temp_12_n_79 : STD_LOGIC;
signal mul_temp_12_n_80 : STD_LOGIC;
signal mul_temp_12_n_81 : STD_LOGIC;
signal mul_temp_12_n_82 : STD_LOGIC;
signal mul_temp_12_n_83 : STD_LOGIC;
signal mul_temp_12_n_84 : STD_LOGIC;
signal mul_temp_12_n_85 : STD_LOGIC;
signal mul_temp_12_n_86 : STD_LOGIC;
signal mul_temp_12_n_87 : STD_LOGIC;
signal mul_temp_12_n_88 : STD_LOGIC;
signal mul_temp_12_n_89 : STD_LOGIC;
signal mul_temp_12_n_90 : STD_LOGIC;
signal mul_temp_12_n_92 : STD_LOGIC;
signal mul_temp_12_n_93 : STD_LOGIC;
signal mul_temp_12_n_94 : STD_LOGIC;
signal mul_temp_12_n_95 : STD_LOGIC;
signal mul_temp_12_n_96 : STD_LOGIC;
signal mul_temp_12_n_97 : STD_LOGIC;
signal mul_temp_12_n_98 : STD_LOGIC;
signal mul_temp_12_n_99 : STD_LOGIC;
signal \^mul_temp_13\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_13_n_100 : STD_LOGIC;
signal mul_temp_13_n_101 : STD_LOGIC;
signal mul_temp_13_n_102 : STD_LOGIC;
signal mul_temp_13_n_103 : STD_LOGIC;
signal mul_temp_13_n_104 : STD_LOGIC;
signal mul_temp_13_n_105 : STD_LOGIC;
signal mul_temp_13_n_74 : STD_LOGIC;
signal mul_temp_13_n_75 : STD_LOGIC;
signal mul_temp_13_n_76 : STD_LOGIC;
signal mul_temp_13_n_77 : STD_LOGIC;
signal mul_temp_13_n_78 : STD_LOGIC;
signal mul_temp_13_n_79 : STD_LOGIC;
signal mul_temp_13_n_80 : STD_LOGIC;
signal mul_temp_13_n_81 : STD_LOGIC;
signal mul_temp_13_n_82 : STD_LOGIC;
signal mul_temp_13_n_83 : STD_LOGIC;
signal mul_temp_13_n_84 : STD_LOGIC;
signal mul_temp_13_n_85 : STD_LOGIC;
signal mul_temp_13_n_86 : STD_LOGIC;
signal mul_temp_13_n_87 : STD_LOGIC;
signal mul_temp_13_n_88 : STD_LOGIC;
signal mul_temp_13_n_89 : STD_LOGIC;
signal mul_temp_13_n_90 : STD_LOGIC;
signal mul_temp_13_n_92 : STD_LOGIC;
signal mul_temp_13_n_93 : STD_LOGIC;
signal mul_temp_13_n_94 : STD_LOGIC;
signal mul_temp_13_n_95 : STD_LOGIC;
signal mul_temp_13_n_96 : STD_LOGIC;
signal mul_temp_13_n_97 : STD_LOGIC;
signal mul_temp_13_n_98 : STD_LOGIC;
signal mul_temp_13_n_99 : STD_LOGIC;
signal \^mul_temp_14\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_14_n_100 : STD_LOGIC;
signal mul_temp_14_n_101 : STD_LOGIC;
signal mul_temp_14_n_102 : STD_LOGIC;
signal mul_temp_14_n_103 : STD_LOGIC;
signal mul_temp_14_n_104 : STD_LOGIC;
signal mul_temp_14_n_105 : STD_LOGIC;
signal mul_temp_14_n_74 : STD_LOGIC;
signal mul_temp_14_n_75 : STD_LOGIC;
signal mul_temp_14_n_76 : STD_LOGIC;
signal mul_temp_14_n_77 : STD_LOGIC;
signal mul_temp_14_n_78 : STD_LOGIC;
signal mul_temp_14_n_79 : STD_LOGIC;
signal mul_temp_14_n_80 : STD_LOGIC;
signal mul_temp_14_n_81 : STD_LOGIC;
signal mul_temp_14_n_82 : STD_LOGIC;
signal mul_temp_14_n_83 : STD_LOGIC;
signal mul_temp_14_n_84 : STD_LOGIC;
signal mul_temp_14_n_85 : STD_LOGIC;
signal mul_temp_14_n_86 : STD_LOGIC;
signal mul_temp_14_n_87 : STD_LOGIC;
signal mul_temp_14_n_88 : STD_LOGIC;
signal mul_temp_14_n_89 : STD_LOGIC;
signal mul_temp_14_n_90 : STD_LOGIC;
signal mul_temp_14_n_92 : STD_LOGIC;
signal mul_temp_14_n_93 : STD_LOGIC;
signal mul_temp_14_n_94 : STD_LOGIC;
signal mul_temp_14_n_95 : STD_LOGIC;
signal mul_temp_14_n_96 : STD_LOGIC;
signal mul_temp_14_n_97 : STD_LOGIC;
signal mul_temp_14_n_98 : STD_LOGIC;
signal mul_temp_14_n_99 : STD_LOGIC;
signal \^mul_temp_15\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_15_n_100 : STD_LOGIC;
signal mul_temp_15_n_101 : STD_LOGIC;
signal mul_temp_15_n_102 : STD_LOGIC;
signal mul_temp_15_n_103 : STD_LOGIC;
signal mul_temp_15_n_104 : STD_LOGIC;
signal mul_temp_15_n_105 : STD_LOGIC;
signal mul_temp_15_n_74 : STD_LOGIC;
signal mul_temp_15_n_75 : STD_LOGIC;
signal mul_temp_15_n_76 : STD_LOGIC;
signal mul_temp_15_n_77 : STD_LOGIC;
signal mul_temp_15_n_78 : STD_LOGIC;
signal mul_temp_15_n_79 : STD_LOGIC;
signal mul_temp_15_n_80 : STD_LOGIC;
signal mul_temp_15_n_81 : STD_LOGIC;
signal mul_temp_15_n_82 : STD_LOGIC;
signal mul_temp_15_n_83 : STD_LOGIC;
signal mul_temp_15_n_84 : STD_LOGIC;
signal mul_temp_15_n_85 : STD_LOGIC;
signal mul_temp_15_n_86 : STD_LOGIC;
signal mul_temp_15_n_87 : STD_LOGIC;
signal mul_temp_15_n_88 : STD_LOGIC;
signal mul_temp_15_n_89 : STD_LOGIC;
signal mul_temp_15_n_90 : STD_LOGIC;
signal mul_temp_15_n_92 : STD_LOGIC;
signal mul_temp_15_n_93 : STD_LOGIC;
signal mul_temp_15_n_94 : STD_LOGIC;
signal mul_temp_15_n_95 : STD_LOGIC;
signal mul_temp_15_n_96 : STD_LOGIC;
signal mul_temp_15_n_97 : STD_LOGIC;
signal mul_temp_15_n_98 : STD_LOGIC;
signal mul_temp_15_n_99 : STD_LOGIC;
signal \^mul_temp_16\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \^mul_temp_17\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_17_n_100 : STD_LOGIC;
signal mul_temp_17_n_101 : STD_LOGIC;
signal mul_temp_17_n_102 : STD_LOGIC;
signal mul_temp_17_n_103 : STD_LOGIC;
signal mul_temp_17_n_104 : STD_LOGIC;
signal mul_temp_17_n_105 : STD_LOGIC;
signal mul_temp_17_n_74 : STD_LOGIC;
signal mul_temp_17_n_75 : STD_LOGIC;
signal mul_temp_17_n_76 : STD_LOGIC;
signal mul_temp_17_n_77 : STD_LOGIC;
signal mul_temp_17_n_78 : STD_LOGIC;
signal mul_temp_17_n_79 : STD_LOGIC;
signal mul_temp_17_n_80 : STD_LOGIC;
signal mul_temp_17_n_81 : STD_LOGIC;
signal mul_temp_17_n_82 : STD_LOGIC;
signal mul_temp_17_n_83 : STD_LOGIC;
signal mul_temp_17_n_84 : STD_LOGIC;
signal mul_temp_17_n_85 : STD_LOGIC;
signal mul_temp_17_n_86 : STD_LOGIC;
signal mul_temp_17_n_87 : STD_LOGIC;
signal mul_temp_17_n_88 : STD_LOGIC;
signal mul_temp_17_n_89 : STD_LOGIC;
signal mul_temp_17_n_90 : STD_LOGIC;
signal mul_temp_17_n_92 : STD_LOGIC;
signal mul_temp_17_n_93 : STD_LOGIC;
signal mul_temp_17_n_94 : STD_LOGIC;
signal mul_temp_17_n_95 : STD_LOGIC;
signal mul_temp_17_n_96 : STD_LOGIC;
signal mul_temp_17_n_97 : STD_LOGIC;
signal mul_temp_17_n_98 : STD_LOGIC;
signal mul_temp_17_n_99 : STD_LOGIC;
signal \^mul_temp_18\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_18_n_100 : STD_LOGIC;
signal mul_temp_18_n_101 : STD_LOGIC;
signal mul_temp_18_n_102 : STD_LOGIC;
signal mul_temp_18_n_103 : STD_LOGIC;
signal mul_temp_18_n_104 : STD_LOGIC;
signal mul_temp_18_n_105 : STD_LOGIC;
signal mul_temp_18_n_74 : STD_LOGIC;
signal mul_temp_18_n_75 : STD_LOGIC;
signal mul_temp_18_n_76 : STD_LOGIC;
signal mul_temp_18_n_77 : STD_LOGIC;
signal mul_temp_18_n_78 : STD_LOGIC;
signal mul_temp_18_n_79 : STD_LOGIC;
signal mul_temp_18_n_80 : STD_LOGIC;
signal mul_temp_18_n_81 : STD_LOGIC;
signal mul_temp_18_n_82 : STD_LOGIC;
signal mul_temp_18_n_83 : STD_LOGIC;
signal mul_temp_18_n_84 : STD_LOGIC;
signal mul_temp_18_n_85 : STD_LOGIC;
signal mul_temp_18_n_86 : STD_LOGIC;
signal mul_temp_18_n_87 : STD_LOGIC;
signal mul_temp_18_n_88 : STD_LOGIC;
signal mul_temp_18_n_89 : STD_LOGIC;
signal mul_temp_18_n_90 : STD_LOGIC;
signal mul_temp_18_n_92 : STD_LOGIC;
signal mul_temp_18_n_93 : STD_LOGIC;
signal mul_temp_18_n_94 : STD_LOGIC;
signal mul_temp_18_n_95 : STD_LOGIC;
signal mul_temp_18_n_96 : STD_LOGIC;
signal mul_temp_18_n_97 : STD_LOGIC;
signal mul_temp_18_n_98 : STD_LOGIC;
signal mul_temp_18_n_99 : STD_LOGIC;
signal \^mul_temp_19\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_19_n_100 : STD_LOGIC;
signal mul_temp_19_n_101 : STD_LOGIC;
signal mul_temp_19_n_102 : STD_LOGIC;
signal mul_temp_19_n_103 : STD_LOGIC;
signal mul_temp_19_n_104 : STD_LOGIC;
signal mul_temp_19_n_105 : STD_LOGIC;
signal mul_temp_19_n_74 : STD_LOGIC;
signal mul_temp_19_n_75 : STD_LOGIC;
signal mul_temp_19_n_76 : STD_LOGIC;
signal mul_temp_19_n_77 : STD_LOGIC;
signal mul_temp_19_n_78 : STD_LOGIC;
signal mul_temp_19_n_79 : STD_LOGIC;
signal mul_temp_19_n_80 : STD_LOGIC;
signal mul_temp_19_n_81 : STD_LOGIC;
signal mul_temp_19_n_82 : STD_LOGIC;
signal mul_temp_19_n_83 : STD_LOGIC;
signal mul_temp_19_n_84 : STD_LOGIC;
signal mul_temp_19_n_85 : STD_LOGIC;
signal mul_temp_19_n_86 : STD_LOGIC;
signal mul_temp_19_n_87 : STD_LOGIC;
signal mul_temp_19_n_88 : STD_LOGIC;
signal mul_temp_19_n_89 : STD_LOGIC;
signal mul_temp_19_n_90 : STD_LOGIC;
signal mul_temp_19_n_92 : STD_LOGIC;
signal mul_temp_19_n_93 : STD_LOGIC;
signal mul_temp_19_n_94 : STD_LOGIC;
signal mul_temp_19_n_95 : STD_LOGIC;
signal mul_temp_19_n_96 : STD_LOGIC;
signal mul_temp_19_n_97 : STD_LOGIC;
signal mul_temp_19_n_98 : STD_LOGIC;
signal mul_temp_19_n_99 : STD_LOGIC;
signal mul_temp_1_n_100 : STD_LOGIC;
signal mul_temp_1_n_101 : STD_LOGIC;
signal mul_temp_1_n_102 : STD_LOGIC;
signal mul_temp_1_n_103 : STD_LOGIC;
signal mul_temp_1_n_104 : STD_LOGIC;
signal mul_temp_1_n_105 : STD_LOGIC;
signal mul_temp_1_n_74 : STD_LOGIC;
signal mul_temp_1_n_75 : STD_LOGIC;
signal mul_temp_1_n_76 : STD_LOGIC;
signal mul_temp_1_n_77 : STD_LOGIC;
signal mul_temp_1_n_78 : STD_LOGIC;
signal mul_temp_1_n_79 : STD_LOGIC;
signal mul_temp_1_n_80 : STD_LOGIC;
signal mul_temp_1_n_81 : STD_LOGIC;
signal mul_temp_1_n_82 : STD_LOGIC;
signal mul_temp_1_n_83 : STD_LOGIC;
signal mul_temp_1_n_84 : STD_LOGIC;
signal mul_temp_1_n_85 : STD_LOGIC;
signal mul_temp_1_n_86 : STD_LOGIC;
signal mul_temp_1_n_87 : STD_LOGIC;
signal mul_temp_1_n_88 : STD_LOGIC;
signal mul_temp_1_n_89 : STD_LOGIC;
signal mul_temp_1_n_90 : STD_LOGIC;
signal mul_temp_1_n_92 : STD_LOGIC;
signal mul_temp_1_n_93 : STD_LOGIC;
signal mul_temp_1_n_94 : STD_LOGIC;
signal mul_temp_1_n_95 : STD_LOGIC;
signal mul_temp_1_n_96 : STD_LOGIC;
signal mul_temp_1_n_97 : STD_LOGIC;
signal mul_temp_1_n_98 : STD_LOGIC;
signal mul_temp_1_n_99 : STD_LOGIC;
signal \^mul_temp_2\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_20\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_20_n_100 : STD_LOGIC;
signal mul_temp_20_n_101 : STD_LOGIC;
signal mul_temp_20_n_102 : STD_LOGIC;
signal mul_temp_20_n_103 : STD_LOGIC;
signal mul_temp_20_n_104 : STD_LOGIC;
signal mul_temp_20_n_105 : STD_LOGIC;
signal mul_temp_20_n_74 : STD_LOGIC;
signal mul_temp_20_n_75 : STD_LOGIC;
signal mul_temp_20_n_76 : STD_LOGIC;
signal mul_temp_20_n_77 : STD_LOGIC;
signal mul_temp_20_n_78 : STD_LOGIC;
signal mul_temp_20_n_79 : STD_LOGIC;
signal mul_temp_20_n_80 : STD_LOGIC;
signal mul_temp_20_n_81 : STD_LOGIC;
signal mul_temp_20_n_82 : STD_LOGIC;
signal mul_temp_20_n_83 : STD_LOGIC;
signal mul_temp_20_n_84 : STD_LOGIC;
signal mul_temp_20_n_85 : STD_LOGIC;
signal mul_temp_20_n_86 : STD_LOGIC;
signal mul_temp_20_n_87 : STD_LOGIC;
signal mul_temp_20_n_88 : STD_LOGIC;
signal mul_temp_20_n_89 : STD_LOGIC;
signal mul_temp_20_n_90 : STD_LOGIC;
signal mul_temp_20_n_92 : STD_LOGIC;
signal mul_temp_20_n_93 : STD_LOGIC;
signal mul_temp_20_n_94 : STD_LOGIC;
signal mul_temp_20_n_95 : STD_LOGIC;
signal mul_temp_20_n_96 : STD_LOGIC;
signal mul_temp_20_n_97 : STD_LOGIC;
signal mul_temp_20_n_98 : STD_LOGIC;
signal mul_temp_20_n_99 : STD_LOGIC;
signal \^mul_temp_21\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_21_n_100 : STD_LOGIC;
signal mul_temp_21_n_101 : STD_LOGIC;
signal mul_temp_21_n_102 : STD_LOGIC;
signal mul_temp_21_n_103 : STD_LOGIC;
signal mul_temp_21_n_104 : STD_LOGIC;
signal mul_temp_21_n_105 : STD_LOGIC;
signal mul_temp_21_n_74 : STD_LOGIC;
signal mul_temp_21_n_75 : STD_LOGIC;
signal mul_temp_21_n_76 : STD_LOGIC;
signal mul_temp_21_n_77 : STD_LOGIC;
signal mul_temp_21_n_78 : STD_LOGIC;
signal mul_temp_21_n_79 : STD_LOGIC;
signal mul_temp_21_n_80 : STD_LOGIC;
signal mul_temp_21_n_81 : STD_LOGIC;
signal mul_temp_21_n_82 : STD_LOGIC;
signal mul_temp_21_n_83 : STD_LOGIC;
signal mul_temp_21_n_84 : STD_LOGIC;
signal mul_temp_21_n_85 : STD_LOGIC;
signal mul_temp_21_n_86 : STD_LOGIC;
signal mul_temp_21_n_87 : STD_LOGIC;
signal mul_temp_21_n_88 : STD_LOGIC;
signal mul_temp_21_n_89 : STD_LOGIC;
signal mul_temp_21_n_90 : STD_LOGIC;
signal mul_temp_21_n_92 : STD_LOGIC;
signal mul_temp_21_n_93 : STD_LOGIC;
signal mul_temp_21_n_94 : STD_LOGIC;
signal mul_temp_21_n_95 : STD_LOGIC;
signal mul_temp_21_n_96 : STD_LOGIC;
signal mul_temp_21_n_97 : STD_LOGIC;
signal mul_temp_21_n_98 : STD_LOGIC;
signal mul_temp_21_n_99 : STD_LOGIC;
signal \^mul_temp_22\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_22_n_100 : STD_LOGIC;
signal mul_temp_22_n_101 : STD_LOGIC;
signal mul_temp_22_n_102 : STD_LOGIC;
signal mul_temp_22_n_103 : STD_LOGIC;
signal mul_temp_22_n_104 : STD_LOGIC;
signal mul_temp_22_n_105 : STD_LOGIC;
signal mul_temp_22_n_74 : STD_LOGIC;
signal mul_temp_22_n_75 : STD_LOGIC;
signal mul_temp_22_n_76 : STD_LOGIC;
signal mul_temp_22_n_77 : STD_LOGIC;
signal mul_temp_22_n_78 : STD_LOGIC;
signal mul_temp_22_n_79 : STD_LOGIC;
signal mul_temp_22_n_80 : STD_LOGIC;
signal mul_temp_22_n_81 : STD_LOGIC;
signal mul_temp_22_n_82 : STD_LOGIC;
signal mul_temp_22_n_83 : STD_LOGIC;
signal mul_temp_22_n_84 : STD_LOGIC;
signal mul_temp_22_n_85 : STD_LOGIC;
signal mul_temp_22_n_86 : STD_LOGIC;
signal mul_temp_22_n_87 : STD_LOGIC;
signal mul_temp_22_n_88 : STD_LOGIC;
signal mul_temp_22_n_89 : STD_LOGIC;
signal mul_temp_22_n_90 : STD_LOGIC;
signal mul_temp_22_n_92 : STD_LOGIC;
signal mul_temp_22_n_93 : STD_LOGIC;
signal mul_temp_22_n_94 : STD_LOGIC;
signal mul_temp_22_n_95 : STD_LOGIC;
signal mul_temp_22_n_96 : STD_LOGIC;
signal mul_temp_22_n_97 : STD_LOGIC;
signal mul_temp_22_n_98 : STD_LOGIC;
signal mul_temp_22_n_99 : STD_LOGIC;
signal \^mul_temp_23\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_23_n_100 : STD_LOGIC;
signal mul_temp_23_n_101 : STD_LOGIC;
signal mul_temp_23_n_102 : STD_LOGIC;
signal mul_temp_23_n_103 : STD_LOGIC;
signal mul_temp_23_n_104 : STD_LOGIC;
signal mul_temp_23_n_105 : STD_LOGIC;
signal mul_temp_23_n_74 : STD_LOGIC;
signal mul_temp_23_n_75 : STD_LOGIC;
signal mul_temp_23_n_76 : STD_LOGIC;
signal mul_temp_23_n_77 : STD_LOGIC;
signal mul_temp_23_n_78 : STD_LOGIC;
signal mul_temp_23_n_79 : STD_LOGIC;
signal mul_temp_23_n_80 : STD_LOGIC;
signal mul_temp_23_n_81 : STD_LOGIC;
signal mul_temp_23_n_82 : STD_LOGIC;
signal mul_temp_23_n_83 : STD_LOGIC;
signal mul_temp_23_n_84 : STD_LOGIC;
signal mul_temp_23_n_85 : STD_LOGIC;
signal mul_temp_23_n_86 : STD_LOGIC;
signal mul_temp_23_n_87 : STD_LOGIC;
signal mul_temp_23_n_88 : STD_LOGIC;
signal mul_temp_23_n_89 : STD_LOGIC;
signal mul_temp_23_n_90 : STD_LOGIC;
signal mul_temp_23_n_92 : STD_LOGIC;
signal mul_temp_23_n_93 : STD_LOGIC;
signal mul_temp_23_n_94 : STD_LOGIC;
signal mul_temp_23_n_95 : STD_LOGIC;
signal mul_temp_23_n_96 : STD_LOGIC;
signal mul_temp_23_n_97 : STD_LOGIC;
signal mul_temp_23_n_98 : STD_LOGIC;
signal mul_temp_23_n_99 : STD_LOGIC;
signal \^mul_temp_24\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_24_n_100 : STD_LOGIC;
signal mul_temp_24_n_101 : STD_LOGIC;
signal mul_temp_24_n_102 : STD_LOGIC;
signal mul_temp_24_n_103 : STD_LOGIC;
signal mul_temp_24_n_104 : STD_LOGIC;
signal mul_temp_24_n_105 : STD_LOGIC;
signal mul_temp_24_n_74 : STD_LOGIC;
signal mul_temp_24_n_75 : STD_LOGIC;
signal mul_temp_24_n_76 : STD_LOGIC;
signal mul_temp_24_n_77 : STD_LOGIC;
signal mul_temp_24_n_78 : STD_LOGIC;
signal mul_temp_24_n_79 : STD_LOGIC;
signal mul_temp_24_n_80 : STD_LOGIC;
signal mul_temp_24_n_81 : STD_LOGIC;
signal mul_temp_24_n_82 : STD_LOGIC;
signal mul_temp_24_n_83 : STD_LOGIC;
signal mul_temp_24_n_84 : STD_LOGIC;
signal mul_temp_24_n_85 : STD_LOGIC;
signal mul_temp_24_n_86 : STD_LOGIC;
signal mul_temp_24_n_87 : STD_LOGIC;
signal mul_temp_24_n_88 : STD_LOGIC;
signal mul_temp_24_n_89 : STD_LOGIC;
signal mul_temp_24_n_90 : STD_LOGIC;
signal mul_temp_24_n_92 : STD_LOGIC;
signal mul_temp_24_n_93 : STD_LOGIC;
signal mul_temp_24_n_94 : STD_LOGIC;
signal mul_temp_24_n_95 : STD_LOGIC;
signal mul_temp_24_n_96 : STD_LOGIC;
signal mul_temp_24_n_97 : STD_LOGIC;
signal mul_temp_24_n_98 : STD_LOGIC;
signal mul_temp_24_n_99 : STD_LOGIC;
signal \^mul_temp_25\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_25_n_100 : STD_LOGIC;
signal mul_temp_25_n_101 : STD_LOGIC;
signal mul_temp_25_n_102 : STD_LOGIC;
signal mul_temp_25_n_103 : STD_LOGIC;
signal mul_temp_25_n_104 : STD_LOGIC;
signal mul_temp_25_n_105 : STD_LOGIC;
signal mul_temp_25_n_74 : STD_LOGIC;
signal mul_temp_25_n_75 : STD_LOGIC;
signal mul_temp_25_n_76 : STD_LOGIC;
signal mul_temp_25_n_77 : STD_LOGIC;
signal mul_temp_25_n_78 : STD_LOGIC;
signal mul_temp_25_n_79 : STD_LOGIC;
signal mul_temp_25_n_80 : STD_LOGIC;
signal mul_temp_25_n_81 : STD_LOGIC;
signal mul_temp_25_n_82 : STD_LOGIC;
signal mul_temp_25_n_83 : STD_LOGIC;
signal mul_temp_25_n_84 : STD_LOGIC;
signal mul_temp_25_n_85 : STD_LOGIC;
signal mul_temp_25_n_86 : STD_LOGIC;
signal mul_temp_25_n_87 : STD_LOGIC;
signal mul_temp_25_n_88 : STD_LOGIC;
signal mul_temp_25_n_89 : STD_LOGIC;
signal mul_temp_25_n_90 : STD_LOGIC;
signal mul_temp_25_n_92 : STD_LOGIC;
signal mul_temp_25_n_93 : STD_LOGIC;
signal mul_temp_25_n_94 : STD_LOGIC;
signal mul_temp_25_n_95 : STD_LOGIC;
signal mul_temp_25_n_96 : STD_LOGIC;
signal mul_temp_25_n_97 : STD_LOGIC;
signal mul_temp_25_n_98 : STD_LOGIC;
signal mul_temp_25_n_99 : STD_LOGIC;
signal \^mul_temp_26\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_26_n_100 : STD_LOGIC;
signal mul_temp_26_n_101 : STD_LOGIC;
signal mul_temp_26_n_102 : STD_LOGIC;
signal mul_temp_26_n_103 : STD_LOGIC;
signal mul_temp_26_n_104 : STD_LOGIC;
signal mul_temp_26_n_105 : STD_LOGIC;
signal mul_temp_26_n_74 : STD_LOGIC;
signal mul_temp_26_n_75 : STD_LOGIC;
signal mul_temp_26_n_76 : STD_LOGIC;
signal mul_temp_26_n_77 : STD_LOGIC;
signal mul_temp_26_n_78 : STD_LOGIC;
signal mul_temp_26_n_79 : STD_LOGIC;
signal mul_temp_26_n_80 : STD_LOGIC;
signal mul_temp_26_n_81 : STD_LOGIC;
signal mul_temp_26_n_82 : STD_LOGIC;
signal mul_temp_26_n_83 : STD_LOGIC;
signal mul_temp_26_n_84 : STD_LOGIC;
signal mul_temp_26_n_85 : STD_LOGIC;
signal mul_temp_26_n_86 : STD_LOGIC;
signal mul_temp_26_n_87 : STD_LOGIC;
signal mul_temp_26_n_88 : STD_LOGIC;
signal mul_temp_26_n_89 : STD_LOGIC;
signal mul_temp_26_n_90 : STD_LOGIC;
signal mul_temp_26_n_92 : STD_LOGIC;
signal mul_temp_26_n_93 : STD_LOGIC;
signal mul_temp_26_n_94 : STD_LOGIC;
signal mul_temp_26_n_95 : STD_LOGIC;
signal mul_temp_26_n_96 : STD_LOGIC;
signal mul_temp_26_n_97 : STD_LOGIC;
signal mul_temp_26_n_98 : STD_LOGIC;
signal mul_temp_26_n_99 : STD_LOGIC;
signal \^mul_temp_27\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_27_n_100 : STD_LOGIC;
signal mul_temp_27_n_101 : STD_LOGIC;
signal mul_temp_27_n_102 : STD_LOGIC;
signal mul_temp_27_n_103 : STD_LOGIC;
signal mul_temp_27_n_104 : STD_LOGIC;
signal mul_temp_27_n_105 : STD_LOGIC;
signal mul_temp_27_n_74 : STD_LOGIC;
signal mul_temp_27_n_75 : STD_LOGIC;
signal mul_temp_27_n_76 : STD_LOGIC;
signal mul_temp_27_n_77 : STD_LOGIC;
signal mul_temp_27_n_78 : STD_LOGIC;
signal mul_temp_27_n_79 : STD_LOGIC;
signal mul_temp_27_n_80 : STD_LOGIC;
signal mul_temp_27_n_81 : STD_LOGIC;
signal mul_temp_27_n_82 : STD_LOGIC;
signal mul_temp_27_n_83 : STD_LOGIC;
signal mul_temp_27_n_84 : STD_LOGIC;
signal mul_temp_27_n_85 : STD_LOGIC;
signal mul_temp_27_n_86 : STD_LOGIC;
signal mul_temp_27_n_87 : STD_LOGIC;
signal mul_temp_27_n_88 : STD_LOGIC;
signal mul_temp_27_n_89 : STD_LOGIC;
signal mul_temp_27_n_90 : STD_LOGIC;
signal mul_temp_27_n_92 : STD_LOGIC;
signal mul_temp_27_n_93 : STD_LOGIC;
signal mul_temp_27_n_94 : STD_LOGIC;
signal mul_temp_27_n_95 : STD_LOGIC;
signal mul_temp_27_n_96 : STD_LOGIC;
signal mul_temp_27_n_97 : STD_LOGIC;
signal mul_temp_27_n_98 : STD_LOGIC;
signal mul_temp_27_n_99 : STD_LOGIC;
signal \^mul_temp_28\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_28_n_100 : STD_LOGIC;
signal mul_temp_28_n_101 : STD_LOGIC;
signal mul_temp_28_n_102 : STD_LOGIC;
signal mul_temp_28_n_103 : STD_LOGIC;
signal mul_temp_28_n_104 : STD_LOGIC;
signal mul_temp_28_n_105 : STD_LOGIC;
signal mul_temp_28_n_74 : STD_LOGIC;
signal mul_temp_28_n_75 : STD_LOGIC;
signal mul_temp_28_n_76 : STD_LOGIC;
signal mul_temp_28_n_77 : STD_LOGIC;
signal mul_temp_28_n_78 : STD_LOGIC;
signal mul_temp_28_n_79 : STD_LOGIC;
signal mul_temp_28_n_80 : STD_LOGIC;
signal mul_temp_28_n_81 : STD_LOGIC;
signal mul_temp_28_n_82 : STD_LOGIC;
signal mul_temp_28_n_83 : STD_LOGIC;
signal mul_temp_28_n_84 : STD_LOGIC;
signal mul_temp_28_n_85 : STD_LOGIC;
signal mul_temp_28_n_86 : STD_LOGIC;
signal mul_temp_28_n_87 : STD_LOGIC;
signal mul_temp_28_n_88 : STD_LOGIC;
signal mul_temp_28_n_89 : STD_LOGIC;
signal mul_temp_28_n_90 : STD_LOGIC;
signal mul_temp_28_n_92 : STD_LOGIC;
signal mul_temp_28_n_93 : STD_LOGIC;
signal mul_temp_28_n_94 : STD_LOGIC;
signal mul_temp_28_n_95 : STD_LOGIC;
signal mul_temp_28_n_96 : STD_LOGIC;
signal mul_temp_28_n_97 : STD_LOGIC;
signal mul_temp_28_n_98 : STD_LOGIC;
signal mul_temp_28_n_99 : STD_LOGIC;
signal \^mul_temp_29\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_29_n_100 : STD_LOGIC;
signal mul_temp_29_n_101 : STD_LOGIC;
signal mul_temp_29_n_102 : STD_LOGIC;
signal mul_temp_29_n_103 : STD_LOGIC;
signal mul_temp_29_n_104 : STD_LOGIC;
signal mul_temp_29_n_105 : STD_LOGIC;
signal mul_temp_29_n_74 : STD_LOGIC;
signal mul_temp_29_n_75 : STD_LOGIC;
signal mul_temp_29_n_76 : STD_LOGIC;
signal mul_temp_29_n_77 : STD_LOGIC;
signal mul_temp_29_n_78 : STD_LOGIC;
signal mul_temp_29_n_79 : STD_LOGIC;
signal mul_temp_29_n_80 : STD_LOGIC;
signal mul_temp_29_n_81 : STD_LOGIC;
signal mul_temp_29_n_82 : STD_LOGIC;
signal mul_temp_29_n_83 : STD_LOGIC;
signal mul_temp_29_n_84 : STD_LOGIC;
signal mul_temp_29_n_85 : STD_LOGIC;
signal mul_temp_29_n_86 : STD_LOGIC;
signal mul_temp_29_n_87 : STD_LOGIC;
signal mul_temp_29_n_88 : STD_LOGIC;
signal mul_temp_29_n_89 : STD_LOGIC;
signal mul_temp_29_n_90 : STD_LOGIC;
signal mul_temp_29_n_92 : STD_LOGIC;
signal mul_temp_29_n_93 : STD_LOGIC;
signal mul_temp_29_n_94 : STD_LOGIC;
signal mul_temp_29_n_95 : STD_LOGIC;
signal mul_temp_29_n_96 : STD_LOGIC;
signal mul_temp_29_n_97 : STD_LOGIC;
signal mul_temp_29_n_98 : STD_LOGIC;
signal mul_temp_29_n_99 : STD_LOGIC;
signal mul_temp_2_n_100 : STD_LOGIC;
signal mul_temp_2_n_101 : STD_LOGIC;
signal mul_temp_2_n_102 : STD_LOGIC;
signal mul_temp_2_n_103 : STD_LOGIC;
signal mul_temp_2_n_104 : STD_LOGIC;
signal mul_temp_2_n_105 : STD_LOGIC;
signal mul_temp_2_n_74 : STD_LOGIC;
signal mul_temp_2_n_75 : STD_LOGIC;
signal mul_temp_2_n_76 : STD_LOGIC;
signal mul_temp_2_n_77 : STD_LOGIC;
signal mul_temp_2_n_78 : STD_LOGIC;
signal mul_temp_2_n_79 : STD_LOGIC;
signal mul_temp_2_n_80 : STD_LOGIC;
signal mul_temp_2_n_81 : STD_LOGIC;
signal mul_temp_2_n_82 : STD_LOGIC;
signal mul_temp_2_n_83 : STD_LOGIC;
signal mul_temp_2_n_84 : STD_LOGIC;
signal mul_temp_2_n_85 : STD_LOGIC;
signal mul_temp_2_n_86 : STD_LOGIC;
signal mul_temp_2_n_87 : STD_LOGIC;
signal mul_temp_2_n_88 : STD_LOGIC;
signal mul_temp_2_n_89 : STD_LOGIC;
signal mul_temp_2_n_90 : STD_LOGIC;
signal mul_temp_2_n_92 : STD_LOGIC;
signal mul_temp_2_n_93 : STD_LOGIC;
signal mul_temp_2_n_94 : STD_LOGIC;
signal mul_temp_2_n_95 : STD_LOGIC;
signal mul_temp_2_n_96 : STD_LOGIC;
signal mul_temp_2_n_97 : STD_LOGIC;
signal mul_temp_2_n_98 : STD_LOGIC;
signal mul_temp_2_n_99 : STD_LOGIC;
signal \^mul_temp_3\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal \^mul_temp_30\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_30_n_100 : STD_LOGIC;
signal mul_temp_30_n_101 : STD_LOGIC;
signal mul_temp_30_n_102 : STD_LOGIC;
signal mul_temp_30_n_103 : STD_LOGIC;
signal mul_temp_30_n_104 : STD_LOGIC;
signal mul_temp_30_n_105 : STD_LOGIC;
signal mul_temp_30_n_74 : STD_LOGIC;
signal mul_temp_30_n_75 : STD_LOGIC;
signal mul_temp_30_n_76 : STD_LOGIC;
signal mul_temp_30_n_77 : STD_LOGIC;
signal mul_temp_30_n_78 : STD_LOGIC;
signal mul_temp_30_n_79 : STD_LOGIC;
signal mul_temp_30_n_80 : STD_LOGIC;
signal mul_temp_30_n_81 : STD_LOGIC;
signal mul_temp_30_n_82 : STD_LOGIC;
signal mul_temp_30_n_83 : STD_LOGIC;
signal mul_temp_30_n_84 : STD_LOGIC;
signal mul_temp_30_n_85 : STD_LOGIC;
signal mul_temp_30_n_86 : STD_LOGIC;
signal mul_temp_30_n_87 : STD_LOGIC;
signal mul_temp_30_n_88 : STD_LOGIC;
signal mul_temp_30_n_89 : STD_LOGIC;
signal mul_temp_30_n_90 : STD_LOGIC;
signal mul_temp_30_n_92 : STD_LOGIC;
signal mul_temp_30_n_93 : STD_LOGIC;
signal mul_temp_30_n_94 : STD_LOGIC;
signal mul_temp_30_n_95 : STD_LOGIC;
signal mul_temp_30_n_96 : STD_LOGIC;
signal mul_temp_30_n_97 : STD_LOGIC;
signal mul_temp_30_n_98 : STD_LOGIC;
signal mul_temp_30_n_99 : STD_LOGIC;
signal \^mul_temp_31\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_31_n_100 : STD_LOGIC;
signal mul_temp_31_n_101 : STD_LOGIC;
signal mul_temp_31_n_102 : STD_LOGIC;
signal mul_temp_31_n_103 : STD_LOGIC;
signal mul_temp_31_n_104 : STD_LOGIC;
signal mul_temp_31_n_105 : STD_LOGIC;
signal mul_temp_31_n_74 : STD_LOGIC;
signal mul_temp_31_n_75 : STD_LOGIC;
signal mul_temp_31_n_76 : STD_LOGIC;
signal mul_temp_31_n_77 : STD_LOGIC;
signal mul_temp_31_n_78 : STD_LOGIC;
signal mul_temp_31_n_79 : STD_LOGIC;
signal mul_temp_31_n_80 : STD_LOGIC;
signal mul_temp_31_n_81 : STD_LOGIC;
signal mul_temp_31_n_82 : STD_LOGIC;
signal mul_temp_31_n_83 : STD_LOGIC;
signal mul_temp_31_n_84 : STD_LOGIC;
signal mul_temp_31_n_85 : STD_LOGIC;
signal mul_temp_31_n_86 : STD_LOGIC;
signal mul_temp_31_n_87 : STD_LOGIC;
signal mul_temp_31_n_88 : STD_LOGIC;
signal mul_temp_31_n_89 : STD_LOGIC;
signal mul_temp_31_n_90 : STD_LOGIC;
signal mul_temp_31_n_92 : STD_LOGIC;
signal mul_temp_31_n_93 : STD_LOGIC;
signal mul_temp_31_n_94 : STD_LOGIC;
signal mul_temp_31_n_95 : STD_LOGIC;
signal mul_temp_31_n_96 : STD_LOGIC;
signal mul_temp_31_n_97 : STD_LOGIC;
signal mul_temp_31_n_98 : STD_LOGIC;
signal mul_temp_31_n_99 : STD_LOGIC;
signal \^mul_temp_32\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_32_n_100 : STD_LOGIC;
signal mul_temp_32_n_101 : STD_LOGIC;
signal mul_temp_32_n_102 : STD_LOGIC;
signal mul_temp_32_n_103 : STD_LOGIC;
signal mul_temp_32_n_104 : STD_LOGIC;
signal mul_temp_32_n_105 : STD_LOGIC;
signal mul_temp_32_n_74 : STD_LOGIC;
signal mul_temp_32_n_75 : STD_LOGIC;
signal mul_temp_32_n_76 : STD_LOGIC;
signal mul_temp_32_n_77 : STD_LOGIC;
signal mul_temp_32_n_78 : STD_LOGIC;
signal mul_temp_32_n_79 : STD_LOGIC;
signal mul_temp_32_n_80 : STD_LOGIC;
signal mul_temp_32_n_81 : STD_LOGIC;
signal mul_temp_32_n_82 : STD_LOGIC;
signal mul_temp_32_n_83 : STD_LOGIC;
signal mul_temp_32_n_84 : STD_LOGIC;
signal mul_temp_32_n_85 : STD_LOGIC;
signal mul_temp_32_n_86 : STD_LOGIC;
signal mul_temp_32_n_87 : STD_LOGIC;
signal mul_temp_32_n_88 : STD_LOGIC;
signal mul_temp_32_n_89 : STD_LOGIC;
signal mul_temp_32_n_90 : STD_LOGIC;
signal mul_temp_32_n_92 : STD_LOGIC;
signal mul_temp_32_n_93 : STD_LOGIC;
signal mul_temp_32_n_94 : STD_LOGIC;
signal mul_temp_32_n_95 : STD_LOGIC;
signal mul_temp_32_n_96 : STD_LOGIC;
signal mul_temp_32_n_97 : STD_LOGIC;
signal mul_temp_32_n_98 : STD_LOGIC;
signal mul_temp_32_n_99 : STD_LOGIC;
signal mul_temp_3_n_100 : STD_LOGIC;
signal mul_temp_3_n_101 : STD_LOGIC;
signal mul_temp_3_n_102 : STD_LOGIC;
signal mul_temp_3_n_103 : STD_LOGIC;
signal mul_temp_3_n_104 : STD_LOGIC;
signal mul_temp_3_n_105 : STD_LOGIC;
signal mul_temp_3_n_74 : STD_LOGIC;
signal mul_temp_3_n_75 : STD_LOGIC;
signal mul_temp_3_n_76 : STD_LOGIC;
signal mul_temp_3_n_77 : STD_LOGIC;
signal mul_temp_3_n_78 : STD_LOGIC;
signal mul_temp_3_n_79 : STD_LOGIC;
signal mul_temp_3_n_80 : STD_LOGIC;
signal mul_temp_3_n_81 : STD_LOGIC;
signal mul_temp_3_n_82 : STD_LOGIC;
signal mul_temp_3_n_83 : STD_LOGIC;
signal mul_temp_3_n_84 : STD_LOGIC;
signal mul_temp_3_n_85 : STD_LOGIC;
signal mul_temp_3_n_86 : STD_LOGIC;
signal mul_temp_3_n_87 : STD_LOGIC;
signal mul_temp_3_n_88 : STD_LOGIC;
signal mul_temp_3_n_89 : STD_LOGIC;
signal mul_temp_3_n_90 : STD_LOGIC;
signal mul_temp_3_n_92 : STD_LOGIC;
signal mul_temp_3_n_93 : STD_LOGIC;
signal mul_temp_3_n_94 : STD_LOGIC;
signal mul_temp_3_n_95 : STD_LOGIC;
signal mul_temp_3_n_96 : STD_LOGIC;
signal mul_temp_3_n_97 : STD_LOGIC;
signal mul_temp_3_n_98 : STD_LOGIC;
signal mul_temp_3_n_99 : STD_LOGIC;
signal \^mul_temp_4\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_4_n_100 : STD_LOGIC;
signal mul_temp_4_n_101 : STD_LOGIC;
signal mul_temp_4_n_102 : STD_LOGIC;
signal mul_temp_4_n_103 : STD_LOGIC;
signal mul_temp_4_n_104 : STD_LOGIC;
signal mul_temp_4_n_105 : STD_LOGIC;
signal mul_temp_4_n_74 : STD_LOGIC;
signal mul_temp_4_n_75 : STD_LOGIC;
signal mul_temp_4_n_76 : STD_LOGIC;
signal mul_temp_4_n_77 : STD_LOGIC;
signal mul_temp_4_n_78 : STD_LOGIC;
signal mul_temp_4_n_79 : STD_LOGIC;
signal mul_temp_4_n_80 : STD_LOGIC;
signal mul_temp_4_n_81 : STD_LOGIC;
signal mul_temp_4_n_82 : STD_LOGIC;
signal mul_temp_4_n_83 : STD_LOGIC;
signal mul_temp_4_n_84 : STD_LOGIC;
signal mul_temp_4_n_85 : STD_LOGIC;
signal mul_temp_4_n_86 : STD_LOGIC;
signal mul_temp_4_n_87 : STD_LOGIC;
signal mul_temp_4_n_88 : STD_LOGIC;
signal mul_temp_4_n_89 : STD_LOGIC;
signal mul_temp_4_n_90 : STD_LOGIC;
signal mul_temp_4_n_92 : STD_LOGIC;
signal mul_temp_4_n_93 : STD_LOGIC;
signal mul_temp_4_n_94 : STD_LOGIC;
signal mul_temp_4_n_95 : STD_LOGIC;
signal mul_temp_4_n_96 : STD_LOGIC;
signal mul_temp_4_n_97 : STD_LOGIC;
signal mul_temp_4_n_98 : STD_LOGIC;
signal mul_temp_4_n_99 : STD_LOGIC;
signal \^mul_temp_5\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_5_n_100 : STD_LOGIC;
signal mul_temp_5_n_101 : STD_LOGIC;
signal mul_temp_5_n_102 : STD_LOGIC;
signal mul_temp_5_n_103 : STD_LOGIC;
signal mul_temp_5_n_104 : STD_LOGIC;
signal mul_temp_5_n_105 : STD_LOGIC;
signal mul_temp_5_n_74 : STD_LOGIC;
signal mul_temp_5_n_75 : STD_LOGIC;
signal mul_temp_5_n_76 : STD_LOGIC;
signal mul_temp_5_n_77 : STD_LOGIC;
signal mul_temp_5_n_78 : STD_LOGIC;
signal mul_temp_5_n_79 : STD_LOGIC;
signal mul_temp_5_n_80 : STD_LOGIC;
signal mul_temp_5_n_81 : STD_LOGIC;
signal mul_temp_5_n_82 : STD_LOGIC;
signal mul_temp_5_n_83 : STD_LOGIC;
signal mul_temp_5_n_84 : STD_LOGIC;
signal mul_temp_5_n_85 : STD_LOGIC;
signal mul_temp_5_n_86 : STD_LOGIC;
signal mul_temp_5_n_87 : STD_LOGIC;
signal mul_temp_5_n_88 : STD_LOGIC;
signal mul_temp_5_n_89 : STD_LOGIC;
signal mul_temp_5_n_90 : STD_LOGIC;
signal mul_temp_5_n_92 : STD_LOGIC;
signal mul_temp_5_n_93 : STD_LOGIC;
signal mul_temp_5_n_94 : STD_LOGIC;
signal mul_temp_5_n_95 : STD_LOGIC;
signal mul_temp_5_n_96 : STD_LOGIC;
signal mul_temp_5_n_97 : STD_LOGIC;
signal mul_temp_5_n_98 : STD_LOGIC;
signal mul_temp_5_n_99 : STD_LOGIC;
signal \^mul_temp_6\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_6_n_100 : STD_LOGIC;
signal mul_temp_6_n_101 : STD_LOGIC;
signal mul_temp_6_n_102 : STD_LOGIC;
signal mul_temp_6_n_103 : STD_LOGIC;
signal mul_temp_6_n_104 : STD_LOGIC;
signal mul_temp_6_n_105 : STD_LOGIC;
signal mul_temp_6_n_74 : STD_LOGIC;
signal mul_temp_6_n_75 : STD_LOGIC;
signal mul_temp_6_n_76 : STD_LOGIC;
signal mul_temp_6_n_77 : STD_LOGIC;
signal mul_temp_6_n_78 : STD_LOGIC;
signal mul_temp_6_n_79 : STD_LOGIC;
signal mul_temp_6_n_80 : STD_LOGIC;
signal mul_temp_6_n_81 : STD_LOGIC;
signal mul_temp_6_n_82 : STD_LOGIC;
signal mul_temp_6_n_83 : STD_LOGIC;
signal mul_temp_6_n_84 : STD_LOGIC;
signal mul_temp_6_n_85 : STD_LOGIC;
signal mul_temp_6_n_86 : STD_LOGIC;
signal mul_temp_6_n_87 : STD_LOGIC;
signal mul_temp_6_n_88 : STD_LOGIC;
signal mul_temp_6_n_89 : STD_LOGIC;
signal mul_temp_6_n_90 : STD_LOGIC;
signal mul_temp_6_n_92 : STD_LOGIC;
signal mul_temp_6_n_93 : STD_LOGIC;
signal mul_temp_6_n_94 : STD_LOGIC;
signal mul_temp_6_n_95 : STD_LOGIC;
signal mul_temp_6_n_96 : STD_LOGIC;
signal mul_temp_6_n_97 : STD_LOGIC;
signal mul_temp_6_n_98 : STD_LOGIC;
signal mul_temp_6_n_99 : STD_LOGIC;
signal \^mul_temp_7\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_7_n_100 : STD_LOGIC;
signal mul_temp_7_n_101 : STD_LOGIC;
signal mul_temp_7_n_102 : STD_LOGIC;
signal mul_temp_7_n_103 : STD_LOGIC;
signal mul_temp_7_n_104 : STD_LOGIC;
signal mul_temp_7_n_105 : STD_LOGIC;
signal mul_temp_7_n_74 : STD_LOGIC;
signal mul_temp_7_n_75 : STD_LOGIC;
signal mul_temp_7_n_76 : STD_LOGIC;
signal mul_temp_7_n_77 : STD_LOGIC;
signal mul_temp_7_n_78 : STD_LOGIC;
signal mul_temp_7_n_79 : STD_LOGIC;
signal mul_temp_7_n_80 : STD_LOGIC;
signal mul_temp_7_n_81 : STD_LOGIC;
signal mul_temp_7_n_82 : STD_LOGIC;
signal mul_temp_7_n_83 : STD_LOGIC;
signal mul_temp_7_n_84 : STD_LOGIC;
signal mul_temp_7_n_85 : STD_LOGIC;
signal mul_temp_7_n_86 : STD_LOGIC;
signal mul_temp_7_n_87 : STD_LOGIC;
signal mul_temp_7_n_88 : STD_LOGIC;
signal mul_temp_7_n_89 : STD_LOGIC;
signal mul_temp_7_n_90 : STD_LOGIC;
signal mul_temp_7_n_92 : STD_LOGIC;
signal mul_temp_7_n_93 : STD_LOGIC;
signal mul_temp_7_n_94 : STD_LOGIC;
signal mul_temp_7_n_95 : STD_LOGIC;
signal mul_temp_7_n_96 : STD_LOGIC;
signal mul_temp_7_n_97 : STD_LOGIC;
signal mul_temp_7_n_98 : STD_LOGIC;
signal mul_temp_7_n_99 : STD_LOGIC;
signal \^mul_temp_8\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_8_n_100 : STD_LOGIC;
signal mul_temp_8_n_101 : STD_LOGIC;
signal mul_temp_8_n_102 : STD_LOGIC;
signal mul_temp_8_n_103 : STD_LOGIC;
signal mul_temp_8_n_104 : STD_LOGIC;
signal mul_temp_8_n_105 : STD_LOGIC;
signal mul_temp_8_n_74 : STD_LOGIC;
signal mul_temp_8_n_75 : STD_LOGIC;
signal mul_temp_8_n_76 : STD_LOGIC;
signal mul_temp_8_n_77 : STD_LOGIC;
signal mul_temp_8_n_78 : STD_LOGIC;
signal mul_temp_8_n_79 : STD_LOGIC;
signal mul_temp_8_n_80 : STD_LOGIC;
signal mul_temp_8_n_81 : STD_LOGIC;
signal mul_temp_8_n_82 : STD_LOGIC;
signal mul_temp_8_n_83 : STD_LOGIC;
signal mul_temp_8_n_84 : STD_LOGIC;
signal mul_temp_8_n_85 : STD_LOGIC;
signal mul_temp_8_n_86 : STD_LOGIC;
signal mul_temp_8_n_87 : STD_LOGIC;
signal mul_temp_8_n_88 : STD_LOGIC;
signal mul_temp_8_n_89 : STD_LOGIC;
signal mul_temp_8_n_90 : STD_LOGIC;
signal mul_temp_8_n_92 : STD_LOGIC;
signal mul_temp_8_n_93 : STD_LOGIC;
signal mul_temp_8_n_94 : STD_LOGIC;
signal mul_temp_8_n_95 : STD_LOGIC;
signal mul_temp_8_n_96 : STD_LOGIC;
signal mul_temp_8_n_97 : STD_LOGIC;
signal mul_temp_8_n_98 : STD_LOGIC;
signal mul_temp_8_n_99 : STD_LOGIC;
signal \^mul_temp_9\ : STD_LOGIC_VECTOR ( 14 to 14 );
signal mul_temp_9_n_100 : STD_LOGIC;
signal mul_temp_9_n_101 : STD_LOGIC;
signal mul_temp_9_n_102 : STD_LOGIC;
signal mul_temp_9_n_103 : STD_LOGIC;
signal mul_temp_9_n_104 : STD_LOGIC;
signal mul_temp_9_n_105 : STD_LOGIC;
signal mul_temp_9_n_74 : STD_LOGIC;
signal mul_temp_9_n_75 : STD_LOGIC;
signal mul_temp_9_n_76 : STD_LOGIC;
signal mul_temp_9_n_77 : STD_LOGIC;
signal mul_temp_9_n_78 : STD_LOGIC;
signal mul_temp_9_n_79 : STD_LOGIC;
signal mul_temp_9_n_80 : STD_LOGIC;
signal mul_temp_9_n_81 : STD_LOGIC;
signal mul_temp_9_n_82 : STD_LOGIC;
signal mul_temp_9_n_83 : STD_LOGIC;
signal mul_temp_9_n_84 : STD_LOGIC;
signal mul_temp_9_n_85 : STD_LOGIC;
signal mul_temp_9_n_86 : STD_LOGIC;
signal mul_temp_9_n_87 : STD_LOGIC;
signal mul_temp_9_n_88 : STD_LOGIC;
signal mul_temp_9_n_89 : STD_LOGIC;
signal mul_temp_9_n_90 : STD_LOGIC;
signal mul_temp_9_n_92 : STD_LOGIC;
signal mul_temp_9_n_93 : STD_LOGIC;
signal mul_temp_9_n_94 : STD_LOGIC;
signal mul_temp_9_n_95 : STD_LOGIC;
signal mul_temp_9_n_96 : STD_LOGIC;
signal mul_temp_9_n_97 : STD_LOGIC;
signal mul_temp_9_n_98 : STD_LOGIC;
signal mul_temp_9_n_99 : STD_LOGIC;
signal mul_temp_n_100 : STD_LOGIC;
signal mul_temp_n_101 : STD_LOGIC;
signal mul_temp_n_102 : STD_LOGIC;
signal mul_temp_n_103 : STD_LOGIC;
signal mul_temp_n_104 : STD_LOGIC;
signal mul_temp_n_105 : STD_LOGIC;
signal mul_temp_n_74 : STD_LOGIC;
signal mul_temp_n_75 : STD_LOGIC;
signal mul_temp_n_76 : STD_LOGIC;
signal mul_temp_n_77 : STD_LOGIC;
signal mul_temp_n_78 : STD_LOGIC;
signal mul_temp_n_79 : STD_LOGIC;
signal mul_temp_n_80 : STD_LOGIC;
signal mul_temp_n_81 : STD_LOGIC;
signal mul_temp_n_82 : STD_LOGIC;
signal mul_temp_n_83 : STD_LOGIC;
signal mul_temp_n_84 : STD_LOGIC;
signal mul_temp_n_85 : STD_LOGIC;
signal mul_temp_n_86 : STD_LOGIC;
signal mul_temp_n_87 : STD_LOGIC;
signal mul_temp_n_88 : STD_LOGIC;
signal mul_temp_n_89 : STD_LOGIC;
signal mul_temp_n_90 : STD_LOGIC;
signal mul_temp_n_92 : STD_LOGIC;
signal mul_temp_n_93 : STD_LOGIC;
signal mul_temp_n_94 : STD_LOGIC;
signal mul_temp_n_95 : STD_LOGIC;
signal mul_temp_n_96 : STD_LOGIC;
signal mul_temp_n_97 : STD_LOGIC;
signal mul_temp_n_98 : STD_LOGIC;
signal mul_temp_n_99 : STD_LOGIC;
signal \sub_temp_carry__0_n_0\ : STD_LOGIC;
signal \sub_temp_carry__0_n_1\ : STD_LOGIC;
signal \sub_temp_carry__0_n_2\ : STD_LOGIC;
signal \sub_temp_carry__0_n_3\ : STD_LOGIC;
signal \sub_temp_carry__1_n_0\ : STD_LOGIC;
signal \sub_temp_carry__1_n_1\ : STD_LOGIC;
signal \sub_temp_carry__1_n_2\ : STD_LOGIC;
signal \sub_temp_carry__1_n_3\ : STD_LOGIC;
signal \sub_temp_carry__2_n_1\ : STD_LOGIC;
signal \sub_temp_carry__2_n_2\ : STD_LOGIC;
signal \sub_temp_carry__2_n_3\ : STD_LOGIC;
signal sub_temp_carry_n_0 : STD_LOGIC;
signal sub_temp_carry_n_1 : STD_LOGIC;
signal sub_temp_carry_n_2 : STD_LOGIC;
signal sub_temp_carry_n_3 : STD_LOGIC;
signal \weight[0][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[0][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[10][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[11][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[12][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[13][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[14][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[15][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[1][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[2][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[3][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[4][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[5][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[6][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[7][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[8][8]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][0]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][12]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][4]_i_5_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_2_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_3_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_4_n_0\ : STD_LOGIC;
signal \weight[9][8]_i_5_n_0\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[0][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[0]_15\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[10][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[10][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[10]_9\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[11][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[11][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[11]_10\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[12][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[12][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[12]_11\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[13][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[13][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[13]_12\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[14][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[14][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[14]_13\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[15][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[15][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[15]_14\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[1][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[1][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[1]_0\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[2][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[2][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[2]_1\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[3][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[3][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[3]_2\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[4][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[4][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[4]_3\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[5][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[5][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[5]_4\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[6][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[6][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[6]_5\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[7][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[7][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[7]_6\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[8][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[8][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[8]_7\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \weight_reg[9][0]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][0]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][12]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][4]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_0\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_1\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_2\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_3\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_4\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_5\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_6\ : STD_LOGIC;
signal \weight_reg[9][8]_i_1_n_7\ : STD_LOGIC;
signal \weight_reg[9]_8\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_ARG_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_ARG_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_ARG_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_ARG_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_ARG_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 30 );
signal NLW_ARG_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__0_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__0_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__0_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__0_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__0_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__0_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__1_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__1_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__1_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__1_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__1_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__1_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__10_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__10_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__10_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__10_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__10_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__10_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__11_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__11_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__11_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__11_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__11_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__11_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__12_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__12_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__12_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__12_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__12_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__12_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__13_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__13_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__13_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__13_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__13_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__13_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__14_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__14_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__14_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__14_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__14_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__14_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__15_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__15_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__15_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__15_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__15_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__15_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__16_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__16_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__16_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__16_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__16_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__16_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__17_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__17_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__17_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__17_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__17_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__17_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__18_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__18_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__18_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__18_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__18_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__18_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__19_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__19_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__19_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__19_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__19_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__19_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__2_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__2_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__2_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__2_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__2_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__2_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__20_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__20_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__20_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__20_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__20_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__20_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__21_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__21_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__21_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__21_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__21_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__21_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__22_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__22_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__22_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__22_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__22_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__22_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__23_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__23_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__23_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__23_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__23_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__23_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__24_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__24_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__24_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__24_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__24_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__24_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__25_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__25_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__25_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__25_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__25_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__25_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__26_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__26_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__26_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__26_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__26_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__26_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__27_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__27_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__27_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__27_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__27_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__27_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__28_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__28_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__28_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__28_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__28_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__28_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__29_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__29_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__29_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__29_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__29_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__29_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__3_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__3_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__3_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__3_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__3_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__3_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__30_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__30_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__30_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__30_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__30_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__30_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__4_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__4_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__4_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__4_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__4_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__4_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__5_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__5_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__5_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__5_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__5_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__5_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__6_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__6_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__6_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__6_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__6_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__6_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__7_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__7_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__7_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__7_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__7_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__7_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__8_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__8_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__8_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__8_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__8_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__8_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_ARG__9_CARRYCASCOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_MULTSIGNOUT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_OVERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_PATTERNBDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_PATTERNDETECT_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_UNDERFLOW_UNCONNECTED\ : STD_LOGIC;
signal \NLW_ARG__9_ACOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 29 downto 0 );
signal \NLW_ARG__9_BCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_ARG__9_CARRYOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG__9_P_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 30 );
signal \NLW_ARG__9_PCOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_ARG_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_ARG_carry__3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_ARG_carry__3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_add_temp_14__0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__138_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__184_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__230_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__278_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__46_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_add_temp_14__92_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal NLW_mul_temp_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_1_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_1_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_1_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_1_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_1_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_10_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_10_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_10_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_10_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_10_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_11_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_11_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_11_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_11_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_11_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_12_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_12_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_12_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_12_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_12_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_13_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_13_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_13_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_13_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_13_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_14_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_14_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_14_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_14_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_14_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_15_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_15_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_15_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_15_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_15_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_17_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_17_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_17_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_17_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_17_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_18_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_18_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_18_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_18_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_18_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_19_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_19_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_19_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_19_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_19_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_2_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_2_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_2_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_2_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_2_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_20_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_20_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_20_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_20_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_20_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_21_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_21_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_21_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_21_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_21_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_22_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_22_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_22_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_22_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_22_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_23_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_23_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_23_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_23_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_23_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_24_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_24_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_24_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_24_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_24_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_25_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_25_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_25_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_25_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_25_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_26_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_26_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_26_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_26_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_26_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_27_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_27_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_27_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_27_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_27_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_28_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_28_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_28_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_28_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_28_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_29_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_29_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_29_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_29_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_29_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_3_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_3_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_3_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_3_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_3_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_30_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_30_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_30_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_30_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_30_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_31_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_31_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_31_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_31_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_31_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_32_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_32_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_32_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_32_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_32_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_4_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_4_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_4_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_4_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_4_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_5_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_5_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_5_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_5_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_5_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_6_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_6_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_6_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_6_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_6_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_7_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_7_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_7_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_7_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_7_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_8_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_8_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_8_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_8_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_8_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_OVERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_UNDERFLOW_UNCONNECTED : STD_LOGIC;
signal NLW_mul_temp_9_ACOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
signal NLW_mul_temp_9_BCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 0 );
signal NLW_mul_temp_9_CARRYOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_mul_temp_9_P_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 32 );
signal NLW_mul_temp_9_PCOUT_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \NLW_sub_temp_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of ARG : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__0\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__1\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__10\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__11\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__12\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__13\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__14\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__15\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__16\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__17\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__18\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__19\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__2\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__20\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__21\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__22\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__23\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__24\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__25\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__26\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__27\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__28\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__29\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__3\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__30\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__4\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__5\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__6\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__7\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__8\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of \ARG__9\ : label is "{SYNTH-13 {cell *THIS*}}";
attribute HLUTNM : string;
attribute HLUTNM of \add_temp_14__0_carry__0_i_1\ : label is "lutpair6";
attribute HLUTNM of \add_temp_14__0_carry__0_i_2\ : label is "lutpair5";
attribute HLUTNM of \add_temp_14__0_carry__0_i_3\ : label is "lutpair4";
attribute HLUTNM of \add_temp_14__0_carry__0_i_4\ : label is "lutpair3";
attribute HLUTNM of \add_temp_14__0_carry__0_i_5\ : label is "lutpair7";
attribute HLUTNM of \add_temp_14__0_carry__0_i_6\ : label is "lutpair6";
attribute HLUTNM of \add_temp_14__0_carry__0_i_7\ : label is "lutpair5";
attribute HLUTNM of \add_temp_14__0_carry__0_i_8\ : label is "lutpair4";
attribute HLUTNM of \add_temp_14__0_carry__1_i_1\ : label is "lutpair10";
attribute HLUTNM of \add_temp_14__0_carry__1_i_2\ : label is "lutpair9";
attribute HLUTNM of \add_temp_14__0_carry__1_i_3\ : label is "lutpair8";
attribute HLUTNM of \add_temp_14__0_carry__1_i_4\ : label is "lutpair7";
attribute HLUTNM of \add_temp_14__0_carry__1_i_5\ : label is "lutpair11";
attribute HLUTNM of \add_temp_14__0_carry__1_i_6\ : label is "lutpair10";
attribute HLUTNM of \add_temp_14__0_carry__1_i_7\ : label is "lutpair9";
attribute HLUTNM of \add_temp_14__0_carry__1_i_8\ : label is "lutpair8";
attribute HLUTNM of \add_temp_14__0_carry__2_i_1\ : label is "lutpair13";
attribute HLUTNM of \add_temp_14__0_carry__2_i_2\ : label is "lutpair12";
attribute HLUTNM of \add_temp_14__0_carry__2_i_3\ : label is "lutpair11";
attribute HLUTNM of \add_temp_14__0_carry__2_i_6\ : label is "lutpair13";
attribute HLUTNM of \add_temp_14__0_carry__2_i_7\ : label is "lutpair12";
attribute HLUTNM of \add_temp_14__0_carry_i_1\ : label is "lutpair2";
attribute HLUTNM of \add_temp_14__0_carry_i_2\ : label is "lutpair1";
attribute HLUTNM of \add_temp_14__0_carry_i_3\ : label is "lutpair0";
attribute HLUTNM of \add_temp_14__0_carry_i_4\ : label is "lutpair3";
attribute HLUTNM of \add_temp_14__0_carry_i_5\ : label is "lutpair2";
attribute HLUTNM of \add_temp_14__0_carry_i_6\ : label is "lutpair1";
attribute HLUTNM of \add_temp_14__0_carry_i_7\ : label is "lutpair0";
attribute HLUTNM of \add_temp_14__138_carry__0_i_1\ : label is "lutpair48";
attribute HLUTNM of \add_temp_14__138_carry__0_i_2\ : label is "lutpair47";
attribute HLUTNM of \add_temp_14__138_carry__0_i_3\ : label is "lutpair46";
attribute HLUTNM of \add_temp_14__138_carry__0_i_4\ : label is "lutpair45";
attribute HLUTNM of \add_temp_14__138_carry__0_i_5\ : label is "lutpair49";
attribute HLUTNM of \add_temp_14__138_carry__0_i_6\ : label is "lutpair48";
attribute HLUTNM of \add_temp_14__138_carry__0_i_7\ : label is "lutpair47";
attribute HLUTNM of \add_temp_14__138_carry__0_i_8\ : label is "lutpair46";
attribute HLUTNM of \add_temp_14__138_carry__1_i_1\ : label is "lutpair52";
attribute HLUTNM of \add_temp_14__138_carry__1_i_2\ : label is "lutpair51";
attribute HLUTNM of \add_temp_14__138_carry__1_i_3\ : label is "lutpair50";
attribute HLUTNM of \add_temp_14__138_carry__1_i_4\ : label is "lutpair49";
attribute HLUTNM of \add_temp_14__138_carry__1_i_5\ : label is "lutpair53";
attribute HLUTNM of \add_temp_14__138_carry__1_i_6\ : label is "lutpair52";
attribute HLUTNM of \add_temp_14__138_carry__1_i_7\ : label is "lutpair51";
attribute HLUTNM of \add_temp_14__138_carry__1_i_8\ : label is "lutpair50";
attribute HLUTNM of \add_temp_14__138_carry__2_i_1\ : label is "lutpair55";
attribute HLUTNM of \add_temp_14__138_carry__2_i_2\ : label is "lutpair54";
attribute HLUTNM of \add_temp_14__138_carry__2_i_3\ : label is "lutpair53";
attribute HLUTNM of \add_temp_14__138_carry__2_i_6\ : label is "lutpair55";
attribute HLUTNM of \add_temp_14__138_carry__2_i_7\ : label is "lutpair54";
attribute HLUTNM of \add_temp_14__138_carry_i_1\ : label is "lutpair44";
attribute HLUTNM of \add_temp_14__138_carry_i_2\ : label is "lutpair43";
attribute HLUTNM of \add_temp_14__138_carry_i_3\ : label is "lutpair42";
attribute HLUTNM of \add_temp_14__138_carry_i_4\ : label is "lutpair45";
attribute HLUTNM of \add_temp_14__138_carry_i_5\ : label is "lutpair44";
attribute HLUTNM of \add_temp_14__138_carry_i_6\ : label is "lutpair43";
attribute HLUTNM of \add_temp_14__138_carry_i_7\ : label is "lutpair42";
attribute HLUTNM of \add_temp_14__184_carry__0_i_1\ : label is "lutpair62";
attribute HLUTNM of \add_temp_14__184_carry__0_i_2\ : label is "lutpair61";
attribute HLUTNM of \add_temp_14__184_carry__0_i_3\ : label is "lutpair60";
attribute HLUTNM of \add_temp_14__184_carry__0_i_4\ : label is "lutpair59";
attribute HLUTNM of \add_temp_14__184_carry__0_i_5\ : label is "lutpair63";
attribute HLUTNM of \add_temp_14__184_carry__0_i_6\ : label is "lutpair62";
attribute HLUTNM of \add_temp_14__184_carry__0_i_7\ : label is "lutpair61";
attribute HLUTNM of \add_temp_14__184_carry__0_i_8\ : label is "lutpair60";
attribute HLUTNM of \add_temp_14__184_carry__1_i_1\ : label is "lutpair66";
attribute HLUTNM of \add_temp_14__184_carry__1_i_2\ : label is "lutpair65";
attribute HLUTNM of \add_temp_14__184_carry__1_i_3\ : label is "lutpair64";
attribute HLUTNM of \add_temp_14__184_carry__1_i_4\ : label is "lutpair63";
attribute HLUTNM of \add_temp_14__184_carry__1_i_5\ : label is "lutpair67";
attribute HLUTNM of \add_temp_14__184_carry__1_i_6\ : label is "lutpair66";
attribute HLUTNM of \add_temp_14__184_carry__1_i_7\ : label is "lutpair65";
attribute HLUTNM of \add_temp_14__184_carry__1_i_8\ : label is "lutpair64";
attribute HLUTNM of \add_temp_14__184_carry__2_i_1\ : label is "lutpair69";
attribute HLUTNM of \add_temp_14__184_carry__2_i_2\ : label is "lutpair68";
attribute HLUTNM of \add_temp_14__184_carry__2_i_3\ : label is "lutpair67";
attribute HLUTNM of \add_temp_14__184_carry__2_i_6\ : label is "lutpair69";
attribute HLUTNM of \add_temp_14__184_carry__2_i_7\ : label is "lutpair68";
attribute HLUTNM of \add_temp_14__184_carry_i_1\ : label is "lutpair58";
attribute HLUTNM of \add_temp_14__184_carry_i_2\ : label is "lutpair57";
attribute HLUTNM of \add_temp_14__184_carry_i_3\ : label is "lutpair56";
attribute HLUTNM of \add_temp_14__184_carry_i_4\ : label is "lutpair59";
attribute HLUTNM of \add_temp_14__184_carry_i_5\ : label is "lutpair58";
attribute HLUTNM of \add_temp_14__184_carry_i_6\ : label is "lutpair57";
attribute HLUTNM of \add_temp_14__184_carry_i_7\ : label is "lutpair56";
attribute HLUTNM of \add_temp_14__230_carry__0_i_1\ : label is "lutpair76";
attribute HLUTNM of \add_temp_14__230_carry__0_i_2\ : label is "lutpair75";
attribute HLUTNM of \add_temp_14__230_carry__0_i_3\ : label is "lutpair74";
attribute HLUTNM of \add_temp_14__230_carry__0_i_4\ : label is "lutpair73";
attribute HLUTNM of \add_temp_14__230_carry__0_i_5\ : label is "lutpair77";
attribute HLUTNM of \add_temp_14__230_carry__0_i_6\ : label is "lutpair76";
attribute HLUTNM of \add_temp_14__230_carry__0_i_7\ : label is "lutpair75";
attribute HLUTNM of \add_temp_14__230_carry__0_i_8\ : label is "lutpair74";
attribute HLUTNM of \add_temp_14__230_carry__1_i_1\ : label is "lutpair80";
attribute HLUTNM of \add_temp_14__230_carry__1_i_2\ : label is "lutpair79";
attribute HLUTNM of \add_temp_14__230_carry__1_i_3\ : label is "lutpair78";
attribute HLUTNM of \add_temp_14__230_carry__1_i_4\ : label is "lutpair77";
attribute HLUTNM of \add_temp_14__230_carry__1_i_5\ : label is "lutpair81";
attribute HLUTNM of \add_temp_14__230_carry__1_i_6\ : label is "lutpair80";
attribute HLUTNM of \add_temp_14__230_carry__1_i_7\ : label is "lutpair79";
attribute HLUTNM of \add_temp_14__230_carry__1_i_8\ : label is "lutpair78";
attribute HLUTNM of \add_temp_14__230_carry__2_i_1\ : label is "lutpair83";
attribute HLUTNM of \add_temp_14__230_carry__2_i_2\ : label is "lutpair82";
attribute HLUTNM of \add_temp_14__230_carry__2_i_3\ : label is "lutpair81";
attribute HLUTNM of \add_temp_14__230_carry__2_i_6\ : label is "lutpair83";
attribute HLUTNM of \add_temp_14__230_carry__2_i_7\ : label is "lutpair82";
attribute HLUTNM of \add_temp_14__230_carry_i_1\ : label is "lutpair72";
attribute HLUTNM of \add_temp_14__230_carry_i_2\ : label is "lutpair71";
attribute HLUTNM of \add_temp_14__230_carry_i_3\ : label is "lutpair70";
attribute HLUTNM of \add_temp_14__230_carry_i_4\ : label is "lutpair73";
attribute HLUTNM of \add_temp_14__230_carry_i_5\ : label is "lutpair72";
attribute HLUTNM of \add_temp_14__230_carry_i_6\ : label is "lutpair71";
attribute HLUTNM of \add_temp_14__230_carry_i_7\ : label is "lutpair70";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \add_temp_14__278_carry__1_i_10\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__1_i_11\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__2_i_8\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \add_temp_14__278_carry__2_i_9\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \add_temp_14__278_carry_i_10\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \add_temp_14__278_carry_i_9\ : label is "soft_lutpair6";
attribute HLUTNM of \add_temp_14__46_carry__0_i_1\ : label is "lutpair20";
attribute HLUTNM of \add_temp_14__46_carry__0_i_2\ : label is "lutpair19";
attribute HLUTNM of \add_temp_14__46_carry__0_i_3\ : label is "lutpair18";
attribute HLUTNM of \add_temp_14__46_carry__0_i_4\ : label is "lutpair17";
attribute HLUTNM of \add_temp_14__46_carry__0_i_5\ : label is "lutpair21";
attribute HLUTNM of \add_temp_14__46_carry__0_i_6\ : label is "lutpair20";
attribute HLUTNM of \add_temp_14__46_carry__0_i_7\ : label is "lutpair19";
attribute HLUTNM of \add_temp_14__46_carry__0_i_8\ : label is "lutpair18";
attribute HLUTNM of \add_temp_14__46_carry__1_i_1\ : label is "lutpair24";
attribute HLUTNM of \add_temp_14__46_carry__1_i_2\ : label is "lutpair23";
attribute HLUTNM of \add_temp_14__46_carry__1_i_3\ : label is "lutpair22";
attribute HLUTNM of \add_temp_14__46_carry__1_i_4\ : label is "lutpair21";
attribute HLUTNM of \add_temp_14__46_carry__1_i_5\ : label is "lutpair25";
attribute HLUTNM of \add_temp_14__46_carry__1_i_6\ : label is "lutpair24";
attribute HLUTNM of \add_temp_14__46_carry__1_i_7\ : label is "lutpair23";
attribute HLUTNM of \add_temp_14__46_carry__1_i_8\ : label is "lutpair22";
attribute HLUTNM of \add_temp_14__46_carry__2_i_1\ : label is "lutpair27";
attribute HLUTNM of \add_temp_14__46_carry__2_i_2\ : label is "lutpair26";
attribute HLUTNM of \add_temp_14__46_carry__2_i_3\ : label is "lutpair25";
attribute HLUTNM of \add_temp_14__46_carry__2_i_6\ : label is "lutpair27";
attribute HLUTNM of \add_temp_14__46_carry__2_i_7\ : label is "lutpair26";
attribute HLUTNM of \add_temp_14__46_carry_i_1\ : label is "lutpair16";
attribute HLUTNM of \add_temp_14__46_carry_i_2\ : label is "lutpair15";
attribute HLUTNM of \add_temp_14__46_carry_i_3\ : label is "lutpair14";
attribute HLUTNM of \add_temp_14__46_carry_i_4\ : label is "lutpair17";
attribute HLUTNM of \add_temp_14__46_carry_i_5\ : label is "lutpair16";
attribute HLUTNM of \add_temp_14__46_carry_i_6\ : label is "lutpair15";
attribute HLUTNM of \add_temp_14__46_carry_i_7\ : label is "lutpair14";
attribute HLUTNM of \add_temp_14__92_carry__0_i_1\ : label is "lutpair34";
attribute HLUTNM of \add_temp_14__92_carry__0_i_2\ : label is "lutpair33";
attribute HLUTNM of \add_temp_14__92_carry__0_i_3\ : label is "lutpair32";
attribute HLUTNM of \add_temp_14__92_carry__0_i_4\ : label is "lutpair31";
attribute HLUTNM of \add_temp_14__92_carry__0_i_5\ : label is "lutpair35";
attribute HLUTNM of \add_temp_14__92_carry__0_i_6\ : label is "lutpair34";
attribute HLUTNM of \add_temp_14__92_carry__0_i_7\ : label is "lutpair33";
attribute HLUTNM of \add_temp_14__92_carry__0_i_8\ : label is "lutpair32";
attribute HLUTNM of \add_temp_14__92_carry__1_i_1\ : label is "lutpair38";
attribute HLUTNM of \add_temp_14__92_carry__1_i_2\ : label is "lutpair37";
attribute HLUTNM of \add_temp_14__92_carry__1_i_3\ : label is "lutpair36";
attribute HLUTNM of \add_temp_14__92_carry__1_i_4\ : label is "lutpair35";
attribute HLUTNM of \add_temp_14__92_carry__1_i_5\ : label is "lutpair39";
attribute HLUTNM of \add_temp_14__92_carry__1_i_6\ : label is "lutpair38";
attribute HLUTNM of \add_temp_14__92_carry__1_i_7\ : label is "lutpair37";
attribute HLUTNM of \add_temp_14__92_carry__1_i_8\ : label is "lutpair36";
attribute HLUTNM of \add_temp_14__92_carry__2_i_1\ : label is "lutpair41";
attribute HLUTNM of \add_temp_14__92_carry__2_i_2\ : label is "lutpair40";
attribute HLUTNM of \add_temp_14__92_carry__2_i_3\ : label is "lutpair39";
attribute HLUTNM of \add_temp_14__92_carry__2_i_6\ : label is "lutpair41";
attribute HLUTNM of \add_temp_14__92_carry__2_i_7\ : label is "lutpair40";
attribute HLUTNM of \add_temp_14__92_carry_i_1\ : label is "lutpair30";
attribute HLUTNM of \add_temp_14__92_carry_i_2\ : label is "lutpair29";
attribute HLUTNM of \add_temp_14__92_carry_i_3\ : label is "lutpair28";
attribute HLUTNM of \add_temp_14__92_carry_i_4\ : label is "lutpair31";
attribute HLUTNM of \add_temp_14__92_carry_i_5\ : label is "lutpair30";
attribute HLUTNM of \add_temp_14__92_carry_i_6\ : label is "lutpair29";
attribute HLUTNM of \add_temp_14__92_carry_i_7\ : label is "lutpair28";
attribute METHODOLOGY_DRC_VIOS of mul_temp : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_1 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_10 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_11 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_12 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_13 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_14 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_15 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_17 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_18 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_19 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_2 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_20 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_21 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_22 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_23 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_24 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_25 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_26 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_27 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_28 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_29 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_3 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_30 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_31 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_32 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_4 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_5 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_6 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_7 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_8 : label is "{SYNTH-13 {cell *THIS*}}";
attribute METHODOLOGY_DRC_VIOS of mul_temp_9 : label is "{SYNTH-13 {cell *THIS*}}";
begin
mul_temp_16(15 downto 0) <= \^mul_temp_16\(15 downto 0);
ARG: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_ARG_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_ARG_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_18\(14),
C(12) => ARG_i_1_n_0,
C(11) => ARG_i_1_n_0,
C(10) => ARG_i_1_n_0,
C(9) => ARG_i_1_n_0,
C(8) => ARG_i_1_n_0,
C(7) => ARG_i_1_n_0,
C(6) => ARG_i_1_n_0,
C(5) => ARG_i_1_n_0,
C(4) => ARG_i_1_n_0,
C(3) => ARG_i_1_n_0,
C(2) => ARG_i_1_n_0,
C(1) => ARG_i_1_n_0,
C(0) => ARG_i_1_n_0,
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_ARG_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_ARG_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_ARG_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => NLW_ARG_OVERFLOW_UNCONNECTED,
P(47 downto 30) => NLW_ARG_P_UNCONNECTED(47 downto 30),
P(29 downto 14) => \in\(15 downto 0),
P(13) => ARG_n_92,
P(12) => ARG_n_93,
P(11) => ARG_n_94,
P(10) => ARG_n_95,
P(9) => ARG_n_96,
P(8) => ARG_n_97,
P(7) => ARG_n_98,
P(6) => ARG_n_99,
P(5) => ARG_n_100,
P(4) => ARG_n_101,
P(3) => ARG_n_102,
P(2) => ARG_n_103,
P(1) => ARG_n_104,
P(0) => ARG_n_105,
PATTERNBDETECT => NLW_ARG_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_ARG_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_ARG_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_ARG_UNDERFLOW_UNCONNECTED
);
\ARG__0\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__0_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[1]_0\(15),
B(16) => \weight_reg[1]_0\(15),
B(15 downto 0) => \weight_reg[1]_0\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__0_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_1\(14),
C(12) => \ARG__0_i_1_n_0\,
C(11) => \ARG__0_i_1_n_0\,
C(10) => \ARG__0_i_1_n_0\,
C(9) => \ARG__0_i_1_n_0\,
C(8) => \ARG__0_i_1_n_0\,
C(7) => \ARG__0_i_1_n_0\,
C(6) => \ARG__0_i_1_n_0\,
C(5) => \ARG__0_i_1_n_0\,
C(4) => \ARG__0_i_1_n_0\,
C(3) => \ARG__0_i_1_n_0\,
C(2) => \ARG__0_i_1_n_0\,
C(1) => \ARG__0_i_1_n_0\,
C(0) => \ARG__0_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__0_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__0_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__0_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__0_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__0_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE16(15 downto 0),
P(13) => \ARG__0_n_92\,
P(12) => \ARG__0_n_93\,
P(11) => \ARG__0_n_94\,
P(10) => \ARG__0_n_95\,
P(9) => \ARG__0_n_96\,
P(8) => \ARG__0_n_97\,
P(7) => \ARG__0_n_98\,
P(6) => \ARG__0_n_99\,
P(5) => \ARG__0_n_100\,
P(4) => \ARG__0_n_101\,
P(3) => \ARG__0_n_102\,
P(2) => \ARG__0_n_103\,
P(1) => \ARG__0_n_104\,
P(0) => \ARG__0_n_105\,
PATTERNBDETECT => \NLW_ARG__0_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__0_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__0_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__0_UNDERFLOW_UNCONNECTED\
);
\ARG__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_1\(14),
O => \ARG__0_i_1_n_0\
);
\ARG__1\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__1_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__1_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_19\(14),
C(12) => \ARG__1_i_1_n_0\,
C(11) => \ARG__1_i_1_n_0\,
C(10) => \ARG__1_i_1_n_0\,
C(9) => \ARG__1_i_1_n_0\,
C(8) => \ARG__1_i_1_n_0\,
C(7) => \ARG__1_i_1_n_0\,
C(6) => \ARG__1_i_1_n_0\,
C(5) => \ARG__1_i_1_n_0\,
C(4) => \ARG__1_i_1_n_0\,
C(3) => \ARG__1_i_1_n_0\,
C(2) => \ARG__1_i_1_n_0\,
C(1) => \ARG__1_i_1_n_0\,
C(0) => \ARG__1_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__1_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__1_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__1_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__1_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__1_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__1_n_76\,
P(28) => \ARG__1_n_77\,
P(27) => \ARG__1_n_78\,
P(26) => \ARG__1_n_79\,
P(25) => \ARG__1_n_80\,
P(24) => \ARG__1_n_81\,
P(23) => \ARG__1_n_82\,
P(22) => \ARG__1_n_83\,
P(21) => \ARG__1_n_84\,
P(20) => \ARG__1_n_85\,
P(19) => \ARG__1_n_86\,
P(18) => \ARG__1_n_87\,
P(17) => \ARG__1_n_88\,
P(16) => \ARG__1_n_89\,
P(15) => \ARG__1_n_90\,
P(14) => \ARG__1_n_91\,
P(13) => \ARG__1_n_92\,
P(12) => \ARG__1_n_93\,
P(11) => \ARG__1_n_94\,
P(10) => \ARG__1_n_95\,
P(9) => \ARG__1_n_96\,
P(8) => \ARG__1_n_97\,
P(7) => \ARG__1_n_98\,
P(6) => \ARG__1_n_99\,
P(5) => \ARG__1_n_100\,
P(4) => \ARG__1_n_101\,
P(3) => \ARG__1_n_102\,
P(2) => \ARG__1_n_103\,
P(1) => \ARG__1_n_104\,
P(0) => \ARG__1_n_105\,
PATTERNBDETECT => \NLW_ARG__1_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__1_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__1_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__1_UNDERFLOW_UNCONNECTED\
);
\ARG__10\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__10_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[6]_5\(15),
B(16) => \weight_reg[6]_5\(15),
B(15 downto 0) => \weight_reg[6]_5\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__10_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_6\(14),
C(12) => \ARG__10_i_1_n_0\,
C(11) => \ARG__10_i_1_n_0\,
C(10) => \ARG__10_i_1_n_0\,
C(9) => \ARG__10_i_1_n_0\,
C(8) => \ARG__10_i_1_n_0\,
C(7) => \ARG__10_i_1_n_0\,
C(6) => \ARG__10_i_1_n_0\,
C(5) => \ARG__10_i_1_n_0\,
C(4) => \ARG__10_i_1_n_0\,
C(3) => \ARG__10_i_1_n_0\,
C(2) => \ARG__10_i_1_n_0\,
C(1) => \ARG__10_i_1_n_0\,
C(0) => \ARG__10_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__10_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__10_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__10_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__10_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__10_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE26(15 downto 0),
P(13) => \ARG__10_n_92\,
P(12) => \ARG__10_n_93\,
P(11) => \ARG__10_n_94\,
P(10) => \ARG__10_n_95\,
P(9) => \ARG__10_n_96\,
P(8) => \ARG__10_n_97\,
P(7) => \ARG__10_n_98\,
P(6) => \ARG__10_n_99\,
P(5) => \ARG__10_n_100\,
P(4) => \ARG__10_n_101\,
P(3) => \ARG__10_n_102\,
P(2) => \ARG__10_n_103\,
P(1) => \ARG__10_n_104\,
P(0) => \ARG__10_n_105\,
PATTERNBDETECT => \NLW_ARG__10_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__10_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__10_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__10_UNDERFLOW_UNCONNECTED\
);
\ARG__10_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_6\(14),
O => \ARG__10_i_1_n_0\
);
\ARG__11\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__11_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__11_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_24\(14),
C(12) => \ARG__11_i_1_n_0\,
C(11) => \ARG__11_i_1_n_0\,
C(10) => \ARG__11_i_1_n_0\,
C(9) => \ARG__11_i_1_n_0\,
C(8) => \ARG__11_i_1_n_0\,
C(7) => \ARG__11_i_1_n_0\,
C(6) => \ARG__11_i_1_n_0\,
C(5) => \ARG__11_i_1_n_0\,
C(4) => \ARG__11_i_1_n_0\,
C(3) => \ARG__11_i_1_n_0\,
C(2) => \ARG__11_i_1_n_0\,
C(1) => \ARG__11_i_1_n_0\,
C(0) => \ARG__11_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__11_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__11_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__11_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__11_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__11_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__11_n_76\,
P(28) => \ARG__11_n_77\,
P(27) => \ARG__11_n_78\,
P(26) => \ARG__11_n_79\,
P(25) => \ARG__11_n_80\,
P(24) => \ARG__11_n_81\,
P(23) => \ARG__11_n_82\,
P(22) => \ARG__11_n_83\,
P(21) => \ARG__11_n_84\,
P(20) => \ARG__11_n_85\,
P(19) => \ARG__11_n_86\,
P(18) => \ARG__11_n_87\,
P(17) => \ARG__11_n_88\,
P(16) => \ARG__11_n_89\,
P(15) => \ARG__11_n_90\,
P(14) => \ARG__11_n_91\,
P(13) => \ARG__11_n_92\,
P(12) => \ARG__11_n_93\,
P(11) => \ARG__11_n_94\,
P(10) => \ARG__11_n_95\,
P(9) => \ARG__11_n_96\,
P(8) => \ARG__11_n_97\,
P(7) => \ARG__11_n_98\,
P(6) => \ARG__11_n_99\,
P(5) => \ARG__11_n_100\,
P(4) => \ARG__11_n_101\,
P(3) => \ARG__11_n_102\,
P(2) => \ARG__11_n_103\,
P(1) => \ARG__11_n_104\,
P(0) => \ARG__11_n_105\,
PATTERNBDETECT => \NLW_ARG__11_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__11_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__11_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__11_UNDERFLOW_UNCONNECTED\
);
\ARG__11_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_24\(14),
O => \ARG__11_i_1_n_0\
);
\ARG__12\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__12_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[7]_6\(15),
B(16) => \weight_reg[7]_6\(15),
B(15 downto 0) => \weight_reg[7]_6\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__12_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_7\(14),
C(12) => \ARG__12_i_1_n_0\,
C(11) => \ARG__12_i_1_n_0\,
C(10) => \ARG__12_i_1_n_0\,
C(9) => \ARG__12_i_1_n_0\,
C(8) => \ARG__12_i_1_n_0\,
C(7) => \ARG__12_i_1_n_0\,
C(6) => \ARG__12_i_1_n_0\,
C(5) => \ARG__12_i_1_n_0\,
C(4) => \ARG__12_i_1_n_0\,
C(3) => \ARG__12_i_1_n_0\,
C(2) => \ARG__12_i_1_n_0\,
C(1) => \ARG__12_i_1_n_0\,
C(0) => \ARG__12_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__12_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__12_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__12_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__12_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__12_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE28(15 downto 0),
P(13) => \ARG__12_n_92\,
P(12) => \ARG__12_n_93\,
P(11) => \ARG__12_n_94\,
P(10) => \ARG__12_n_95\,
P(9) => \ARG__12_n_96\,
P(8) => \ARG__12_n_97\,
P(7) => \ARG__12_n_98\,
P(6) => \ARG__12_n_99\,
P(5) => \ARG__12_n_100\,
P(4) => \ARG__12_n_101\,
P(3) => \ARG__12_n_102\,
P(2) => \ARG__12_n_103\,
P(1) => \ARG__12_n_104\,
P(0) => \ARG__12_n_105\,
PATTERNBDETECT => \NLW_ARG__12_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__12_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__12_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__12_UNDERFLOW_UNCONNECTED\
);
\ARG__12_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_7\(14),
O => \ARG__12_i_1_n_0\
);
\ARG__13\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__13_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__13_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_25\(14),
C(12) => \ARG__13_i_1_n_0\,
C(11) => \ARG__13_i_1_n_0\,
C(10) => \ARG__13_i_1_n_0\,
C(9) => \ARG__13_i_1_n_0\,
C(8) => \ARG__13_i_1_n_0\,
C(7) => \ARG__13_i_1_n_0\,
C(6) => \ARG__13_i_1_n_0\,
C(5) => \ARG__13_i_1_n_0\,
C(4) => \ARG__13_i_1_n_0\,
C(3) => \ARG__13_i_1_n_0\,
C(2) => \ARG__13_i_1_n_0\,
C(1) => \ARG__13_i_1_n_0\,
C(0) => \ARG__13_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__13_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__13_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__13_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__13_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__13_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__13_n_76\,
P(28) => \ARG__13_n_77\,
P(27) => \ARG__13_n_78\,
P(26) => \ARG__13_n_79\,
P(25) => \ARG__13_n_80\,
P(24) => \ARG__13_n_81\,
P(23) => \ARG__13_n_82\,
P(22) => \ARG__13_n_83\,
P(21) => \ARG__13_n_84\,
P(20) => \ARG__13_n_85\,
P(19) => \ARG__13_n_86\,
P(18) => \ARG__13_n_87\,
P(17) => \ARG__13_n_88\,
P(16) => \ARG__13_n_89\,
P(15) => \ARG__13_n_90\,
P(14) => \ARG__13_n_91\,
P(13) => \ARG__13_n_92\,
P(12) => \ARG__13_n_93\,
P(11) => \ARG__13_n_94\,
P(10) => \ARG__13_n_95\,
P(9) => \ARG__13_n_96\,
P(8) => \ARG__13_n_97\,
P(7) => \ARG__13_n_98\,
P(6) => \ARG__13_n_99\,
P(5) => \ARG__13_n_100\,
P(4) => \ARG__13_n_101\,
P(3) => \ARG__13_n_102\,
P(2) => \ARG__13_n_103\,
P(1) => \ARG__13_n_104\,
P(0) => \ARG__13_n_105\,
PATTERNBDETECT => \NLW_ARG__13_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__13_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__13_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__13_UNDERFLOW_UNCONNECTED\
);
\ARG__13_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_25\(14),
O => \ARG__13_i_1_n_0\
);
\ARG__14\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__14_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[8]_7\(15),
B(16) => \weight_reg[8]_7\(15),
B(15 downto 0) => \weight_reg[8]_7\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__14_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_8\(14),
C(12) => \ARG__14_i_1_n_0\,
C(11) => \ARG__14_i_1_n_0\,
C(10) => \ARG__14_i_1_n_0\,
C(9) => \ARG__14_i_1_n_0\,
C(8) => \ARG__14_i_1_n_0\,
C(7) => \ARG__14_i_1_n_0\,
C(6) => \ARG__14_i_1_n_0\,
C(5) => \ARG__14_i_1_n_0\,
C(4) => \ARG__14_i_1_n_0\,
C(3) => \ARG__14_i_1_n_0\,
C(2) => \ARG__14_i_1_n_0\,
C(1) => \ARG__14_i_1_n_0\,
C(0) => \ARG__14_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__14_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__14_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__14_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__14_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__14_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE30(15 downto 0),
P(13) => \ARG__14_n_92\,
P(12) => \ARG__14_n_93\,
P(11) => \ARG__14_n_94\,
P(10) => \ARG__14_n_95\,
P(9) => \ARG__14_n_96\,
P(8) => \ARG__14_n_97\,
P(7) => \ARG__14_n_98\,
P(6) => \ARG__14_n_99\,
P(5) => \ARG__14_n_100\,
P(4) => \ARG__14_n_101\,
P(3) => \ARG__14_n_102\,
P(2) => \ARG__14_n_103\,
P(1) => \ARG__14_n_104\,
P(0) => \ARG__14_n_105\,
PATTERNBDETECT => \NLW_ARG__14_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__14_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__14_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__14_UNDERFLOW_UNCONNECTED\
);
\ARG__14_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_8\(14),
O => \ARG__14_i_1_n_0\
);
\ARG__15\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__15_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__15_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_26\(14),
C(12) => \ARG__15_i_1_n_0\,
C(11) => \ARG__15_i_1_n_0\,
C(10) => \ARG__15_i_1_n_0\,
C(9) => \ARG__15_i_1_n_0\,
C(8) => \ARG__15_i_1_n_0\,
C(7) => \ARG__15_i_1_n_0\,
C(6) => \ARG__15_i_1_n_0\,
C(5) => \ARG__15_i_1_n_0\,
C(4) => \ARG__15_i_1_n_0\,
C(3) => \ARG__15_i_1_n_0\,
C(2) => \ARG__15_i_1_n_0\,
C(1) => \ARG__15_i_1_n_0\,
C(0) => \ARG__15_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__15_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__15_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__15_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__15_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__15_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__15_n_76\,
P(28) => \ARG__15_n_77\,
P(27) => \ARG__15_n_78\,
P(26) => \ARG__15_n_79\,
P(25) => \ARG__15_n_80\,
P(24) => \ARG__15_n_81\,
P(23) => \ARG__15_n_82\,
P(22) => \ARG__15_n_83\,
P(21) => \ARG__15_n_84\,
P(20) => \ARG__15_n_85\,
P(19) => \ARG__15_n_86\,
P(18) => \ARG__15_n_87\,
P(17) => \ARG__15_n_88\,
P(16) => \ARG__15_n_89\,
P(15) => \ARG__15_n_90\,
P(14) => \ARG__15_n_91\,
P(13) => \ARG__15_n_92\,
P(12) => \ARG__15_n_93\,
P(11) => \ARG__15_n_94\,
P(10) => \ARG__15_n_95\,
P(9) => \ARG__15_n_96\,
P(8) => \ARG__15_n_97\,
P(7) => \ARG__15_n_98\,
P(6) => \ARG__15_n_99\,
P(5) => \ARG__15_n_100\,
P(4) => \ARG__15_n_101\,
P(3) => \ARG__15_n_102\,
P(2) => \ARG__15_n_103\,
P(1) => \ARG__15_n_104\,
P(0) => \ARG__15_n_105\,
PATTERNBDETECT => \NLW_ARG__15_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__15_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__15_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__15_UNDERFLOW_UNCONNECTED\
);
\ARG__15_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_26\(14),
O => \ARG__15_i_1_n_0\
);
\ARG__16\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__16_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[9]_8\(15),
B(16) => \weight_reg[9]_8\(15),
B(15 downto 0) => \weight_reg[9]_8\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__16_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_9\(14),
C(12) => \ARG__16_i_1_n_0\,
C(11) => \ARG__16_i_1_n_0\,
C(10) => \ARG__16_i_1_n_0\,
C(9) => \ARG__16_i_1_n_0\,
C(8) => \ARG__16_i_1_n_0\,
C(7) => \ARG__16_i_1_n_0\,
C(6) => \ARG__16_i_1_n_0\,
C(5) => \ARG__16_i_1_n_0\,
C(4) => \ARG__16_i_1_n_0\,
C(3) => \ARG__16_i_1_n_0\,
C(2) => \ARG__16_i_1_n_0\,
C(1) => \ARG__16_i_1_n_0\,
C(0) => \ARG__16_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__16_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__16_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__16_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__16_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__16_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE32(15 downto 0),
P(13) => \ARG__16_n_92\,
P(12) => \ARG__16_n_93\,
P(11) => \ARG__16_n_94\,
P(10) => \ARG__16_n_95\,
P(9) => \ARG__16_n_96\,
P(8) => \ARG__16_n_97\,
P(7) => \ARG__16_n_98\,
P(6) => \ARG__16_n_99\,
P(5) => \ARG__16_n_100\,
P(4) => \ARG__16_n_101\,
P(3) => \ARG__16_n_102\,
P(2) => \ARG__16_n_103\,
P(1) => \ARG__16_n_104\,
P(0) => \ARG__16_n_105\,
PATTERNBDETECT => \NLW_ARG__16_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__16_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__16_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__16_UNDERFLOW_UNCONNECTED\
);
\ARG__16_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_9\(14),
O => \ARG__16_i_1_n_0\
);
\ARG__17\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__17_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__17_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_27\(14),
C(12) => \ARG__17_i_1_n_0\,
C(11) => \ARG__17_i_1_n_0\,
C(10) => \ARG__17_i_1_n_0\,
C(9) => \ARG__17_i_1_n_0\,
C(8) => \ARG__17_i_1_n_0\,
C(7) => \ARG__17_i_1_n_0\,
C(6) => \ARG__17_i_1_n_0\,
C(5) => \ARG__17_i_1_n_0\,
C(4) => \ARG__17_i_1_n_0\,
C(3) => \ARG__17_i_1_n_0\,
C(2) => \ARG__17_i_1_n_0\,
C(1) => \ARG__17_i_1_n_0\,
C(0) => \ARG__17_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__17_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__17_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__17_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__17_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__17_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__17_n_76\,
P(28) => \ARG__17_n_77\,
P(27) => \ARG__17_n_78\,
P(26) => \ARG__17_n_79\,
P(25) => \ARG__17_n_80\,
P(24) => \ARG__17_n_81\,
P(23) => \ARG__17_n_82\,
P(22) => \ARG__17_n_83\,
P(21) => \ARG__17_n_84\,
P(20) => \ARG__17_n_85\,
P(19) => \ARG__17_n_86\,
P(18) => \ARG__17_n_87\,
P(17) => \ARG__17_n_88\,
P(16) => \ARG__17_n_89\,
P(15) => \ARG__17_n_90\,
P(14) => \ARG__17_n_91\,
P(13) => \ARG__17_n_92\,
P(12) => \ARG__17_n_93\,
P(11) => \ARG__17_n_94\,
P(10) => \ARG__17_n_95\,
P(9) => \ARG__17_n_96\,
P(8) => \ARG__17_n_97\,
P(7) => \ARG__17_n_98\,
P(6) => \ARG__17_n_99\,
P(5) => \ARG__17_n_100\,
P(4) => \ARG__17_n_101\,
P(3) => \ARG__17_n_102\,
P(2) => \ARG__17_n_103\,
P(1) => \ARG__17_n_104\,
P(0) => \ARG__17_n_105\,
PATTERNBDETECT => \NLW_ARG__17_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__17_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__17_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__17_UNDERFLOW_UNCONNECTED\
);
\ARG__17_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_27\(14),
O => \ARG__17_i_1_n_0\
);
\ARG__18\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__18_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[10]_9\(15),
B(16) => \weight_reg[10]_9\(15),
B(15 downto 0) => \weight_reg[10]_9\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__18_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_10\(14),
C(12) => \ARG__18_i_1_n_0\,
C(11) => \ARG__18_i_1_n_0\,
C(10) => \ARG__18_i_1_n_0\,
C(9) => \ARG__18_i_1_n_0\,
C(8) => \ARG__18_i_1_n_0\,
C(7) => \ARG__18_i_1_n_0\,
C(6) => \ARG__18_i_1_n_0\,
C(5) => \ARG__18_i_1_n_0\,
C(4) => \ARG__18_i_1_n_0\,
C(3) => \ARG__18_i_1_n_0\,
C(2) => \ARG__18_i_1_n_0\,
C(1) => \ARG__18_i_1_n_0\,
C(0) => \ARG__18_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__18_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__18_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__18_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__18_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__18_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE34(15 downto 0),
P(13) => \ARG__18_n_92\,
P(12) => \ARG__18_n_93\,
P(11) => \ARG__18_n_94\,
P(10) => \ARG__18_n_95\,
P(9) => \ARG__18_n_96\,
P(8) => \ARG__18_n_97\,
P(7) => \ARG__18_n_98\,
P(6) => \ARG__18_n_99\,
P(5) => \ARG__18_n_100\,
P(4) => \ARG__18_n_101\,
P(3) => \ARG__18_n_102\,
P(2) => \ARG__18_n_103\,
P(1) => \ARG__18_n_104\,
P(0) => \ARG__18_n_105\,
PATTERNBDETECT => \NLW_ARG__18_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__18_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__18_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__18_UNDERFLOW_UNCONNECTED\
);
\ARG__18_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_10\(14),
O => \ARG__18_i_1_n_0\
);
\ARG__19\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__19_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__19_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_28\(14),
C(12) => \ARG__19_i_1_n_0\,
C(11) => \ARG__19_i_1_n_0\,
C(10) => \ARG__19_i_1_n_0\,
C(9) => \ARG__19_i_1_n_0\,
C(8) => \ARG__19_i_1_n_0\,
C(7) => \ARG__19_i_1_n_0\,
C(6) => \ARG__19_i_1_n_0\,
C(5) => \ARG__19_i_1_n_0\,
C(4) => \ARG__19_i_1_n_0\,
C(3) => \ARG__19_i_1_n_0\,
C(2) => \ARG__19_i_1_n_0\,
C(1) => \ARG__19_i_1_n_0\,
C(0) => \ARG__19_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__19_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__19_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__19_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__19_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__19_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__19_n_76\,
P(28) => \ARG__19_n_77\,
P(27) => \ARG__19_n_78\,
P(26) => \ARG__19_n_79\,
P(25) => \ARG__19_n_80\,
P(24) => \ARG__19_n_81\,
P(23) => \ARG__19_n_82\,
P(22) => \ARG__19_n_83\,
P(21) => \ARG__19_n_84\,
P(20) => \ARG__19_n_85\,
P(19) => \ARG__19_n_86\,
P(18) => \ARG__19_n_87\,
P(17) => \ARG__19_n_88\,
P(16) => \ARG__19_n_89\,
P(15) => \ARG__19_n_90\,
P(14) => \ARG__19_n_91\,
P(13) => \ARG__19_n_92\,
P(12) => \ARG__19_n_93\,
P(11) => \ARG__19_n_94\,
P(10) => \ARG__19_n_95\,
P(9) => \ARG__19_n_96\,
P(8) => \ARG__19_n_97\,
P(7) => \ARG__19_n_98\,
P(6) => \ARG__19_n_99\,
P(5) => \ARG__19_n_100\,
P(4) => \ARG__19_n_101\,
P(3) => \ARG__19_n_102\,
P(2) => \ARG__19_n_103\,
P(1) => \ARG__19_n_104\,
P(0) => \ARG__19_n_105\,
PATTERNBDETECT => \NLW_ARG__19_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__19_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__19_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__19_UNDERFLOW_UNCONNECTED\
);
\ARG__19_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_28\(14),
O => \ARG__19_i_1_n_0\
);
\ARG__1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_19\(14),
O => \ARG__1_i_1_n_0\
);
\ARG__2\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__2_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[2]_1\(15),
B(16) => \weight_reg[2]_1\(15),
B(15 downto 0) => \weight_reg[2]_1\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__2_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_2\(14),
C(12) => \ARG__2_i_1_n_0\,
C(11) => \ARG__2_i_1_n_0\,
C(10) => \ARG__2_i_1_n_0\,
C(9) => \ARG__2_i_1_n_0\,
C(8) => \ARG__2_i_1_n_0\,
C(7) => \ARG__2_i_1_n_0\,
C(6) => \ARG__2_i_1_n_0\,
C(5) => \ARG__2_i_1_n_0\,
C(4) => \ARG__2_i_1_n_0\,
C(3) => \ARG__2_i_1_n_0\,
C(2) => \ARG__2_i_1_n_0\,
C(1) => \ARG__2_i_1_n_0\,
C(0) => \ARG__2_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__2_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__2_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__2_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__2_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__2_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE18(15 downto 0),
P(13) => \ARG__2_n_92\,
P(12) => \ARG__2_n_93\,
P(11) => \ARG__2_n_94\,
P(10) => \ARG__2_n_95\,
P(9) => \ARG__2_n_96\,
P(8) => \ARG__2_n_97\,
P(7) => \ARG__2_n_98\,
P(6) => \ARG__2_n_99\,
P(5) => \ARG__2_n_100\,
P(4) => \ARG__2_n_101\,
P(3) => \ARG__2_n_102\,
P(2) => \ARG__2_n_103\,
P(1) => \ARG__2_n_104\,
P(0) => \ARG__2_n_105\,
PATTERNBDETECT => \NLW_ARG__2_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__2_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__2_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__2_UNDERFLOW_UNCONNECTED\
);
\ARG__20\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__20_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[11]_10\(15),
B(16) => \weight_reg[11]_10\(15),
B(15 downto 0) => \weight_reg[11]_10\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__20_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_11\(14),
C(12) => \ARG__20_i_1_n_0\,
C(11) => \ARG__20_i_1_n_0\,
C(10) => \ARG__20_i_1_n_0\,
C(9) => \ARG__20_i_1_n_0\,
C(8) => \ARG__20_i_1_n_0\,
C(7) => \ARG__20_i_1_n_0\,
C(6) => \ARG__20_i_1_n_0\,
C(5) => \ARG__20_i_1_n_0\,
C(4) => \ARG__20_i_1_n_0\,
C(3) => \ARG__20_i_1_n_0\,
C(2) => \ARG__20_i_1_n_0\,
C(1) => \ARG__20_i_1_n_0\,
C(0) => \ARG__20_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__20_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__20_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__20_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__20_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__20_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE36(15 downto 0),
P(13) => \ARG__20_n_92\,
P(12) => \ARG__20_n_93\,
P(11) => \ARG__20_n_94\,
P(10) => \ARG__20_n_95\,
P(9) => \ARG__20_n_96\,
P(8) => \ARG__20_n_97\,
P(7) => \ARG__20_n_98\,
P(6) => \ARG__20_n_99\,
P(5) => \ARG__20_n_100\,
P(4) => \ARG__20_n_101\,
P(3) => \ARG__20_n_102\,
P(2) => \ARG__20_n_103\,
P(1) => \ARG__20_n_104\,
P(0) => \ARG__20_n_105\,
PATTERNBDETECT => \NLW_ARG__20_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__20_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__20_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__20_UNDERFLOW_UNCONNECTED\
);
\ARG__20_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_11\(14),
O => \ARG__20_i_1_n_0\
);
\ARG__21\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__21_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__21_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_29\(14),
C(12) => \ARG__21_i_1_n_0\,
C(11) => \ARG__21_i_1_n_0\,
C(10) => \ARG__21_i_1_n_0\,
C(9) => \ARG__21_i_1_n_0\,
C(8) => \ARG__21_i_1_n_0\,
C(7) => \ARG__21_i_1_n_0\,
C(6) => \ARG__21_i_1_n_0\,
C(5) => \ARG__21_i_1_n_0\,
C(4) => \ARG__21_i_1_n_0\,
C(3) => \ARG__21_i_1_n_0\,
C(2) => \ARG__21_i_1_n_0\,
C(1) => \ARG__21_i_1_n_0\,
C(0) => \ARG__21_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__21_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__21_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__21_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__21_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__21_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__21_n_76\,
P(28) => \ARG__21_n_77\,
P(27) => \ARG__21_n_78\,
P(26) => \ARG__21_n_79\,
P(25) => \ARG__21_n_80\,
P(24) => \ARG__21_n_81\,
P(23) => \ARG__21_n_82\,
P(22) => \ARG__21_n_83\,
P(21) => \ARG__21_n_84\,
P(20) => \ARG__21_n_85\,
P(19) => \ARG__21_n_86\,
P(18) => \ARG__21_n_87\,
P(17) => \ARG__21_n_88\,
P(16) => \ARG__21_n_89\,
P(15) => \ARG__21_n_90\,
P(14) => \ARG__21_n_91\,
P(13) => \ARG__21_n_92\,
P(12) => \ARG__21_n_93\,
P(11) => \ARG__21_n_94\,
P(10) => \ARG__21_n_95\,
P(9) => \ARG__21_n_96\,
P(8) => \ARG__21_n_97\,
P(7) => \ARG__21_n_98\,
P(6) => \ARG__21_n_99\,
P(5) => \ARG__21_n_100\,
P(4) => \ARG__21_n_101\,
P(3) => \ARG__21_n_102\,
P(2) => \ARG__21_n_103\,
P(1) => \ARG__21_n_104\,
P(0) => \ARG__21_n_105\,
PATTERNBDETECT => \NLW_ARG__21_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__21_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__21_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__21_UNDERFLOW_UNCONNECTED\
);
\ARG__21_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_29\(14),
O => \ARG__21_i_1_n_0\
);
\ARG__22\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__22_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[12]_11\(15),
B(16) => \weight_reg[12]_11\(15),
B(15 downto 0) => \weight_reg[12]_11\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__22_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_12\(14),
C(12) => \ARG__22_i_1_n_0\,
C(11) => \ARG__22_i_1_n_0\,
C(10) => \ARG__22_i_1_n_0\,
C(9) => \ARG__22_i_1_n_0\,
C(8) => \ARG__22_i_1_n_0\,
C(7) => \ARG__22_i_1_n_0\,
C(6) => \ARG__22_i_1_n_0\,
C(5) => \ARG__22_i_1_n_0\,
C(4) => \ARG__22_i_1_n_0\,
C(3) => \ARG__22_i_1_n_0\,
C(2) => \ARG__22_i_1_n_0\,
C(1) => \ARG__22_i_1_n_0\,
C(0) => \ARG__22_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__22_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__22_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__22_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__22_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__22_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE38(15 downto 0),
P(13) => \ARG__22_n_92\,
P(12) => \ARG__22_n_93\,
P(11) => \ARG__22_n_94\,
P(10) => \ARG__22_n_95\,
P(9) => \ARG__22_n_96\,
P(8) => \ARG__22_n_97\,
P(7) => \ARG__22_n_98\,
P(6) => \ARG__22_n_99\,
P(5) => \ARG__22_n_100\,
P(4) => \ARG__22_n_101\,
P(3) => \ARG__22_n_102\,
P(2) => \ARG__22_n_103\,
P(1) => \ARG__22_n_104\,
P(0) => \ARG__22_n_105\,
PATTERNBDETECT => \NLW_ARG__22_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__22_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__22_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__22_UNDERFLOW_UNCONNECTED\
);
\ARG__22_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_12\(14),
O => \ARG__22_i_1_n_0\
);
\ARG__23\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__23_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__23_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_30\(14),
C(12) => \ARG__23_i_1_n_0\,
C(11) => \ARG__23_i_1_n_0\,
C(10) => \ARG__23_i_1_n_0\,
C(9) => \ARG__23_i_1_n_0\,
C(8) => \ARG__23_i_1_n_0\,
C(7) => \ARG__23_i_1_n_0\,
C(6) => \ARG__23_i_1_n_0\,
C(5) => \ARG__23_i_1_n_0\,
C(4) => \ARG__23_i_1_n_0\,
C(3) => \ARG__23_i_1_n_0\,
C(2) => \ARG__23_i_1_n_0\,
C(1) => \ARG__23_i_1_n_0\,
C(0) => \ARG__23_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__23_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__23_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__23_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__23_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__23_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__23_n_76\,
P(28) => \ARG__23_n_77\,
P(27) => \ARG__23_n_78\,
P(26) => \ARG__23_n_79\,
P(25) => \ARG__23_n_80\,
P(24) => \ARG__23_n_81\,
P(23) => \ARG__23_n_82\,
P(22) => \ARG__23_n_83\,
P(21) => \ARG__23_n_84\,
P(20) => \ARG__23_n_85\,
P(19) => \ARG__23_n_86\,
P(18) => \ARG__23_n_87\,
P(17) => \ARG__23_n_88\,
P(16) => \ARG__23_n_89\,
P(15) => \ARG__23_n_90\,
P(14) => \ARG__23_n_91\,
P(13) => \ARG__23_n_92\,
P(12) => \ARG__23_n_93\,
P(11) => \ARG__23_n_94\,
P(10) => \ARG__23_n_95\,
P(9) => \ARG__23_n_96\,
P(8) => \ARG__23_n_97\,
P(7) => \ARG__23_n_98\,
P(6) => \ARG__23_n_99\,
P(5) => \ARG__23_n_100\,
P(4) => \ARG__23_n_101\,
P(3) => \ARG__23_n_102\,
P(2) => \ARG__23_n_103\,
P(1) => \ARG__23_n_104\,
P(0) => \ARG__23_n_105\,
PATTERNBDETECT => \NLW_ARG__23_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__23_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__23_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__23_UNDERFLOW_UNCONNECTED\
);
\ARG__23_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_30\(14),
O => \ARG__23_i_1_n_0\
);
\ARG__24\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__24_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[13]_12\(15),
B(16) => \weight_reg[13]_12\(15),
B(15 downto 0) => \weight_reg[13]_12\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__24_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_13\(14),
C(12) => \ARG__24_i_1_n_0\,
C(11) => \ARG__24_i_1_n_0\,
C(10) => \ARG__24_i_1_n_0\,
C(9) => \ARG__24_i_1_n_0\,
C(8) => \ARG__24_i_1_n_0\,
C(7) => \ARG__24_i_1_n_0\,
C(6) => \ARG__24_i_1_n_0\,
C(5) => \ARG__24_i_1_n_0\,
C(4) => \ARG__24_i_1_n_0\,
C(3) => \ARG__24_i_1_n_0\,
C(2) => \ARG__24_i_1_n_0\,
C(1) => \ARG__24_i_1_n_0\,
C(0) => \ARG__24_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__24_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__24_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__24_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__24_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__24_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE40(15 downto 0),
P(13) => \ARG__24_n_92\,
P(12) => \ARG__24_n_93\,
P(11) => \ARG__24_n_94\,
P(10) => \ARG__24_n_95\,
P(9) => \ARG__24_n_96\,
P(8) => \ARG__24_n_97\,
P(7) => \ARG__24_n_98\,
P(6) => \ARG__24_n_99\,
P(5) => \ARG__24_n_100\,
P(4) => \ARG__24_n_101\,
P(3) => \ARG__24_n_102\,
P(2) => \ARG__24_n_103\,
P(1) => \ARG__24_n_104\,
P(0) => \ARG__24_n_105\,
PATTERNBDETECT => \NLW_ARG__24_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__24_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__24_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__24_UNDERFLOW_UNCONNECTED\
);
\ARG__24_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_13\(14),
O => \ARG__24_i_1_n_0\
);
\ARG__25\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__25_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__25_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_31\(14),
C(12) => \ARG__25_i_1_n_0\,
C(11) => \ARG__25_i_1_n_0\,
C(10) => \ARG__25_i_1_n_0\,
C(9) => \ARG__25_i_1_n_0\,
C(8) => \ARG__25_i_1_n_0\,
C(7) => \ARG__25_i_1_n_0\,
C(6) => \ARG__25_i_1_n_0\,
C(5) => \ARG__25_i_1_n_0\,
C(4) => \ARG__25_i_1_n_0\,
C(3) => \ARG__25_i_1_n_0\,
C(2) => \ARG__25_i_1_n_0\,
C(1) => \ARG__25_i_1_n_0\,
C(0) => \ARG__25_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__25_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__25_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__25_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__25_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__25_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__25_n_76\,
P(28) => \ARG__25_n_77\,
P(27) => \ARG__25_n_78\,
P(26) => \ARG__25_n_79\,
P(25) => \ARG__25_n_80\,
P(24) => \ARG__25_n_81\,
P(23) => \ARG__25_n_82\,
P(22) => \ARG__25_n_83\,
P(21) => \ARG__25_n_84\,
P(20) => \ARG__25_n_85\,
P(19) => \ARG__25_n_86\,
P(18) => \ARG__25_n_87\,
P(17) => \ARG__25_n_88\,
P(16) => \ARG__25_n_89\,
P(15) => \ARG__25_n_90\,
P(14) => \ARG__25_n_91\,
P(13) => \ARG__25_n_92\,
P(12) => \ARG__25_n_93\,
P(11) => \ARG__25_n_94\,
P(10) => \ARG__25_n_95\,
P(9) => \ARG__25_n_96\,
P(8) => \ARG__25_n_97\,
P(7) => \ARG__25_n_98\,
P(6) => \ARG__25_n_99\,
P(5) => \ARG__25_n_100\,
P(4) => \ARG__25_n_101\,
P(3) => \ARG__25_n_102\,
P(2) => \ARG__25_n_103\,
P(1) => \ARG__25_n_104\,
P(0) => \ARG__25_n_105\,
PATTERNBDETECT => \NLW_ARG__25_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__25_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__25_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__25_UNDERFLOW_UNCONNECTED\
);
\ARG__25_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_31\(14),
O => \ARG__25_i_1_n_0\
);
\ARG__26\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__26_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[14]_13\(15),
B(16) => \weight_reg[14]_13\(15),
B(15 downto 0) => \weight_reg[14]_13\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__26_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_14\(14),
C(12) => \ARG__26_i_1_n_0\,
C(11) => \ARG__26_i_1_n_0\,
C(10) => \ARG__26_i_1_n_0\,
C(9) => \ARG__26_i_1_n_0\,
C(8) => \ARG__26_i_1_n_0\,
C(7) => \ARG__26_i_1_n_0\,
C(6) => \ARG__26_i_1_n_0\,
C(5) => \ARG__26_i_1_n_0\,
C(4) => \ARG__26_i_1_n_0\,
C(3) => \ARG__26_i_1_n_0\,
C(2) => \ARG__26_i_1_n_0\,
C(1) => \ARG__26_i_1_n_0\,
C(0) => \ARG__26_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__26_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__26_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__26_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__26_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__26_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE42(15 downto 0),
P(13) => \ARG__26_n_92\,
P(12) => \ARG__26_n_93\,
P(11) => \ARG__26_n_94\,
P(10) => \ARG__26_n_95\,
P(9) => \ARG__26_n_96\,
P(8) => \ARG__26_n_97\,
P(7) => \ARG__26_n_98\,
P(6) => \ARG__26_n_99\,
P(5) => \ARG__26_n_100\,
P(4) => \ARG__26_n_101\,
P(3) => \ARG__26_n_102\,
P(2) => \ARG__26_n_103\,
P(1) => \ARG__26_n_104\,
P(0) => \ARG__26_n_105\,
PATTERNBDETECT => \NLW_ARG__26_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__26_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__26_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__26_UNDERFLOW_UNCONNECTED\
);
\ARG__26_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_14\(14),
O => \ARG__26_i_1_n_0\
);
\ARG__27\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__27_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__27_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_32\(14),
C(12) => \ARG__27_i_1_n_0\,
C(11) => \ARG__27_i_1_n_0\,
C(10) => \ARG__27_i_1_n_0\,
C(9) => \ARG__27_i_1_n_0\,
C(8) => \ARG__27_i_1_n_0\,
C(7) => \ARG__27_i_1_n_0\,
C(6) => \ARG__27_i_1_n_0\,
C(5) => \ARG__27_i_1_n_0\,
C(4) => \ARG__27_i_1_n_0\,
C(3) => \ARG__27_i_1_n_0\,
C(2) => \ARG__27_i_1_n_0\,
C(1) => \ARG__27_i_1_n_0\,
C(0) => \ARG__27_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__27_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__27_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__27_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__27_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__27_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__27_n_76\,
P(28) => \ARG__27_n_77\,
P(27) => \ARG__27_n_78\,
P(26) => \ARG__27_n_79\,
P(25) => \ARG__27_n_80\,
P(24) => \ARG__27_n_81\,
P(23) => \ARG__27_n_82\,
P(22) => \ARG__27_n_83\,
P(21) => \ARG__27_n_84\,
P(20) => \ARG__27_n_85\,
P(19) => \ARG__27_n_86\,
P(18) => \ARG__27_n_87\,
P(17) => \ARG__27_n_88\,
P(16) => \ARG__27_n_89\,
P(15) => \ARG__27_n_90\,
P(14) => \ARG__27_n_91\,
P(13) => \ARG__27_n_92\,
P(12) => \ARG__27_n_93\,
P(11) => \ARG__27_n_94\,
P(10) => \ARG__27_n_95\,
P(9) => \ARG__27_n_96\,
P(8) => \ARG__27_n_97\,
P(7) => \ARG__27_n_98\,
P(6) => \ARG__27_n_99\,
P(5) => \ARG__27_n_100\,
P(4) => \ARG__27_n_101\,
P(3) => \ARG__27_n_102\,
P(2) => \ARG__27_n_103\,
P(1) => \ARG__27_n_104\,
P(0) => \ARG__27_n_105\,
PATTERNBDETECT => \NLW_ARG__27_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__27_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__27_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__27_UNDERFLOW_UNCONNECTED\
);
\ARG__27_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_32\(14),
O => \ARG__27_i_1_n_0\
);
\ARG__28\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__28_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[15]_14\(15),
B(16) => \weight_reg[15]_14\(15),
B(15 downto 0) => \weight_reg[15]_14\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__28_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_15\(14),
C(12) => \ARG__28_i_1_n_0\,
C(11) => \ARG__28_i_1_n_0\,
C(10) => \ARG__28_i_1_n_0\,
C(9) => \ARG__28_i_1_n_0\,
C(8) => \ARG__28_i_1_n_0\,
C(7) => \ARG__28_i_1_n_0\,
C(6) => \ARG__28_i_1_n_0\,
C(5) => \ARG__28_i_1_n_0\,
C(4) => \ARG__28_i_1_n_0\,
C(3) => \ARG__28_i_1_n_0\,
C(2) => \ARG__28_i_1_n_0\,
C(1) => \ARG__28_i_1_n_0\,
C(0) => \ARG__28_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__28_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__28_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__28_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__28_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__28_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE44(15 downto 0),
P(13) => \ARG__28_n_92\,
P(12) => \ARG__28_n_93\,
P(11) => \ARG__28_n_94\,
P(10) => \ARG__28_n_95\,
P(9) => \ARG__28_n_96\,
P(8) => \ARG__28_n_97\,
P(7) => \ARG__28_n_98\,
P(6) => \ARG__28_n_99\,
P(5) => \ARG__28_n_100\,
P(4) => \ARG__28_n_101\,
P(3) => \ARG__28_n_102\,
P(2) => \ARG__28_n_103\,
P(1) => \ARG__28_n_104\,
P(0) => \ARG__28_n_105\,
PATTERNBDETECT => \NLW_ARG__28_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__28_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__28_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__28_UNDERFLOW_UNCONNECTED\
);
\ARG__28_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_15\(14),
O => \ARG__28_i_1_n_0\
);
\ARG__29\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__29_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__29_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_17\(14),
C(12) => \ARG__29_i_1_n_0\,
C(11) => \ARG__29_i_1_n_0\,
C(10) => \ARG__29_i_1_n_0\,
C(9) => \ARG__29_i_1_n_0\,
C(8) => \ARG__29_i_1_n_0\,
C(7) => \ARG__29_i_1_n_0\,
C(6) => \ARG__29_i_1_n_0\,
C(5) => \ARG__29_i_1_n_0\,
C(4) => \ARG__29_i_1_n_0\,
C(3) => \ARG__29_i_1_n_0\,
C(2) => \ARG__29_i_1_n_0\,
C(1) => \ARG__29_i_1_n_0\,
C(0) => \ARG__29_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__29_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__29_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__29_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__29_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__29_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__29_n_76\,
P(28) => \ARG__29_n_77\,
P(27) => \ARG__29_n_78\,
P(26) => \ARG__29_n_79\,
P(25) => \ARG__29_n_80\,
P(24) => \ARG__29_n_81\,
P(23) => \ARG__29_n_82\,
P(22) => \ARG__29_n_83\,
P(21) => \ARG__29_n_84\,
P(20) => \ARG__29_n_85\,
P(19) => \ARG__29_n_86\,
P(18) => \ARG__29_n_87\,
P(17) => \ARG__29_n_88\,
P(16) => \ARG__29_n_89\,
P(15) => \ARG__29_n_90\,
P(14) => \ARG__29_n_91\,
P(13) => \ARG__29_n_92\,
P(12) => \ARG__29_n_93\,
P(11) => \ARG__29_n_94\,
P(10) => \ARG__29_n_95\,
P(9) => \ARG__29_n_96\,
P(8) => \ARG__29_n_97\,
P(7) => \ARG__29_n_98\,
P(6) => \ARG__29_n_99\,
P(5) => \ARG__29_n_100\,
P(4) => \ARG__29_n_101\,
P(3) => \ARG__29_n_102\,
P(2) => \ARG__29_n_103\,
P(1) => \ARG__29_n_104\,
P(0) => \ARG__29_n_105\,
PATTERNBDETECT => \NLW_ARG__29_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__29_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__29_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__29_UNDERFLOW_UNCONNECTED\
);
\ARG__29_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_17\(14),
O => \ARG__29_i_1_n_0\
);
\ARG__2_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_2\(14),
O => \ARG__2_i_1_n_0\
);
\ARG__3\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__3_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__3_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_20\(14),
C(12) => \ARG__3_i_1_n_0\,
C(11) => \ARG__3_i_1_n_0\,
C(10) => \ARG__3_i_1_n_0\,
C(9) => \ARG__3_i_1_n_0\,
C(8) => \ARG__3_i_1_n_0\,
C(7) => \ARG__3_i_1_n_0\,
C(6) => \ARG__3_i_1_n_0\,
C(5) => \ARG__3_i_1_n_0\,
C(4) => \ARG__3_i_1_n_0\,
C(3) => \ARG__3_i_1_n_0\,
C(2) => \ARG__3_i_1_n_0\,
C(1) => \ARG__3_i_1_n_0\,
C(0) => \ARG__3_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__3_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__3_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__3_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__3_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__3_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__3_n_76\,
P(28) => \ARG__3_n_77\,
P(27) => \ARG__3_n_78\,
P(26) => \ARG__3_n_79\,
P(25) => \ARG__3_n_80\,
P(24) => \ARG__3_n_81\,
P(23) => \ARG__3_n_82\,
P(22) => \ARG__3_n_83\,
P(21) => \ARG__3_n_84\,
P(20) => \ARG__3_n_85\,
P(19) => \ARG__3_n_86\,
P(18) => \ARG__3_n_87\,
P(17) => \ARG__3_n_88\,
P(16) => \ARG__3_n_89\,
P(15) => \ARG__3_n_90\,
P(14) => \ARG__3_n_91\,
P(13) => \ARG__3_n_92\,
P(12) => \ARG__3_n_93\,
P(11) => \ARG__3_n_94\,
P(10) => \ARG__3_n_95\,
P(9) => \ARG__3_n_96\,
P(8) => \ARG__3_n_97\,
P(7) => \ARG__3_n_98\,
P(6) => \ARG__3_n_99\,
P(5) => \ARG__3_n_100\,
P(4) => \ARG__3_n_101\,
P(3) => \ARG__3_n_102\,
P(2) => \ARG__3_n_103\,
P(1) => \ARG__3_n_104\,
P(0) => \ARG__3_n_105\,
PATTERNBDETECT => \NLW_ARG__3_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__3_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__3_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__3_UNDERFLOW_UNCONNECTED\
);
\ARG__30\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__30_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[0]_15\(15),
B(16) => \weight_reg[0]_15\(15),
B(15 downto 0) => \weight_reg[0]_15\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__30_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp\(14),
C(12) => \ARG__30_i_1_n_0\,
C(11) => \ARG__30_i_1_n_0\,
C(10) => \ARG__30_i_1_n_0\,
C(9) => \ARG__30_i_1_n_0\,
C(8) => \ARG__30_i_1_n_0\,
C(7) => \ARG__30_i_1_n_0\,
C(6) => \ARG__30_i_1_n_0\,
C(5) => \ARG__30_i_1_n_0\,
C(4) => \ARG__30_i_1_n_0\,
C(3) => \ARG__30_i_1_n_0\,
C(2) => \ARG__30_i_1_n_0\,
C(1) => \ARG__30_i_1_n_0\,
C(0) => \ARG__30_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__30_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__30_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__30_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__30_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__30_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE15(15 downto 0),
P(13) => \ARG__30_n_92\,
P(12) => \ARG__30_n_93\,
P(11) => \ARG__30_n_94\,
P(10) => \ARG__30_n_95\,
P(9) => \ARG__30_n_96\,
P(8) => \ARG__30_n_97\,
P(7) => \ARG__30_n_98\,
P(6) => \ARG__30_n_99\,
P(5) => \ARG__30_n_100\,
P(4) => \ARG__30_n_101\,
P(3) => \ARG__30_n_102\,
P(2) => \ARG__30_n_103\,
P(1) => \ARG__30_n_104\,
P(0) => \ARG__30_n_105\,
PATTERNBDETECT => \NLW_ARG__30_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__30_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__30_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__30_UNDERFLOW_UNCONNECTED\
);
\ARG__30_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp\(14),
O => \ARG__30_i_1_n_0\
);
\ARG__3_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_20\(14),
O => \ARG__3_i_1_n_0\
);
\ARG__4\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__4_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[3]_2\(15),
B(16) => \weight_reg[3]_2\(15),
B(15 downto 0) => \weight_reg[3]_2\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__4_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_3\(14),
C(12) => \ARG__4_i_1_n_0\,
C(11) => \ARG__4_i_1_n_0\,
C(10) => \ARG__4_i_1_n_0\,
C(9) => \ARG__4_i_1_n_0\,
C(8) => \ARG__4_i_1_n_0\,
C(7) => \ARG__4_i_1_n_0\,
C(6) => \ARG__4_i_1_n_0\,
C(5) => \ARG__4_i_1_n_0\,
C(4) => \ARG__4_i_1_n_0\,
C(3) => \ARG__4_i_1_n_0\,
C(2) => \ARG__4_i_1_n_0\,
C(1) => \ARG__4_i_1_n_0\,
C(0) => \ARG__4_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__4_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__4_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__4_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__4_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__4_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE20(15 downto 0),
P(13) => \ARG__4_n_92\,
P(12) => \ARG__4_n_93\,
P(11) => \ARG__4_n_94\,
P(10) => \ARG__4_n_95\,
P(9) => \ARG__4_n_96\,
P(8) => \ARG__4_n_97\,
P(7) => \ARG__4_n_98\,
P(6) => \ARG__4_n_99\,
P(5) => \ARG__4_n_100\,
P(4) => \ARG__4_n_101\,
P(3) => \ARG__4_n_102\,
P(2) => \ARG__4_n_103\,
P(1) => \ARG__4_n_104\,
P(0) => \ARG__4_n_105\,
PATTERNBDETECT => \NLW_ARG__4_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__4_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__4_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__4_UNDERFLOW_UNCONNECTED\
);
\ARG__4_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_3\(14),
O => \ARG__4_i_1_n_0\
);
\ARG__5\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__5_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__5_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_21\(14),
C(12) => \ARG__5_i_1_n_0\,
C(11) => \ARG__5_i_1_n_0\,
C(10) => \ARG__5_i_1_n_0\,
C(9) => \ARG__5_i_1_n_0\,
C(8) => \ARG__5_i_1_n_0\,
C(7) => \ARG__5_i_1_n_0\,
C(6) => \ARG__5_i_1_n_0\,
C(5) => \ARG__5_i_1_n_0\,
C(4) => \ARG__5_i_1_n_0\,
C(3) => \ARG__5_i_1_n_0\,
C(2) => \ARG__5_i_1_n_0\,
C(1) => \ARG__5_i_1_n_0\,
C(0) => \ARG__5_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__5_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__5_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__5_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__5_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__5_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__5_n_76\,
P(28) => \ARG__5_n_77\,
P(27) => \ARG__5_n_78\,
P(26) => \ARG__5_n_79\,
P(25) => \ARG__5_n_80\,
P(24) => \ARG__5_n_81\,
P(23) => \ARG__5_n_82\,
P(22) => \ARG__5_n_83\,
P(21) => \ARG__5_n_84\,
P(20) => \ARG__5_n_85\,
P(19) => \ARG__5_n_86\,
P(18) => \ARG__5_n_87\,
P(17) => \ARG__5_n_88\,
P(16) => \ARG__5_n_89\,
P(15) => \ARG__5_n_90\,
P(14) => \ARG__5_n_91\,
P(13) => \ARG__5_n_92\,
P(12) => \ARG__5_n_93\,
P(11) => \ARG__5_n_94\,
P(10) => \ARG__5_n_95\,
P(9) => \ARG__5_n_96\,
P(8) => \ARG__5_n_97\,
P(7) => \ARG__5_n_98\,
P(6) => \ARG__5_n_99\,
P(5) => \ARG__5_n_100\,
P(4) => \ARG__5_n_101\,
P(3) => \ARG__5_n_102\,
P(2) => \ARG__5_n_103\,
P(1) => \ARG__5_n_104\,
P(0) => \ARG__5_n_105\,
PATTERNBDETECT => \NLW_ARG__5_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__5_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__5_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__5_UNDERFLOW_UNCONNECTED\
);
\ARG__5_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_21\(14),
O => \ARG__5_i_1_n_0\
);
\ARG__6\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__6_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[4]_3\(15),
B(16) => \weight_reg[4]_3\(15),
B(15 downto 0) => \weight_reg[4]_3\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__6_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_4\(14),
C(12) => \ARG__6_i_1_n_0\,
C(11) => \ARG__6_i_1_n_0\,
C(10) => \ARG__6_i_1_n_0\,
C(9) => \ARG__6_i_1_n_0\,
C(8) => \ARG__6_i_1_n_0\,
C(7) => \ARG__6_i_1_n_0\,
C(6) => \ARG__6_i_1_n_0\,
C(5) => \ARG__6_i_1_n_0\,
C(4) => \ARG__6_i_1_n_0\,
C(3) => \ARG__6_i_1_n_0\,
C(2) => \ARG__6_i_1_n_0\,
C(1) => \ARG__6_i_1_n_0\,
C(0) => \ARG__6_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__6_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__6_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__6_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__6_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__6_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE22(15 downto 0),
P(13) => \ARG__6_n_92\,
P(12) => \ARG__6_n_93\,
P(11) => \ARG__6_n_94\,
P(10) => \ARG__6_n_95\,
P(9) => \ARG__6_n_96\,
P(8) => \ARG__6_n_97\,
P(7) => \ARG__6_n_98\,
P(6) => \ARG__6_n_99\,
P(5) => \ARG__6_n_100\,
P(4) => \ARG__6_n_101\,
P(3) => \ARG__6_n_102\,
P(2) => \ARG__6_n_103\,
P(1) => \ARG__6_n_104\,
P(0) => \ARG__6_n_105\,
PATTERNBDETECT => \NLW_ARG__6_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__6_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__6_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__6_UNDERFLOW_UNCONNECTED\
);
\ARG__6_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_4\(14),
O => \ARG__6_i_1_n_0\
);
\ARG__7\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__7_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__7_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_22\(14),
C(12) => \ARG__7_i_1_n_0\,
C(11) => \ARG__7_i_1_n_0\,
C(10) => \ARG__7_i_1_n_0\,
C(9) => \ARG__7_i_1_n_0\,
C(8) => \ARG__7_i_1_n_0\,
C(7) => \ARG__7_i_1_n_0\,
C(6) => \ARG__7_i_1_n_0\,
C(5) => \ARG__7_i_1_n_0\,
C(4) => \ARG__7_i_1_n_0\,
C(3) => \ARG__7_i_1_n_0\,
C(2) => \ARG__7_i_1_n_0\,
C(1) => \ARG__7_i_1_n_0\,
C(0) => \ARG__7_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__7_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__7_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__7_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__7_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__7_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__7_n_76\,
P(28) => \ARG__7_n_77\,
P(27) => \ARG__7_n_78\,
P(26) => \ARG__7_n_79\,
P(25) => \ARG__7_n_80\,
P(24) => \ARG__7_n_81\,
P(23) => \ARG__7_n_82\,
P(22) => \ARG__7_n_83\,
P(21) => \ARG__7_n_84\,
P(20) => \ARG__7_n_85\,
P(19) => \ARG__7_n_86\,
P(18) => \ARG__7_n_87\,
P(17) => \ARG__7_n_88\,
P(16) => \ARG__7_n_89\,
P(15) => \ARG__7_n_90\,
P(14) => \ARG__7_n_91\,
P(13) => \ARG__7_n_92\,
P(12) => \ARG__7_n_93\,
P(11) => \ARG__7_n_94\,
P(10) => \ARG__7_n_95\,
P(9) => \ARG__7_n_96\,
P(8) => \ARG__7_n_97\,
P(7) => \ARG__7_n_98\,
P(6) => \ARG__7_n_99\,
P(5) => \ARG__7_n_100\,
P(4) => \ARG__7_n_101\,
P(3) => \ARG__7_n_102\,
P(2) => \ARG__7_n_103\,
P(1) => \ARG__7_n_104\,
P(0) => \ARG__7_n_105\,
PATTERNBDETECT => \NLW_ARG__7_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__7_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__7_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__7_UNDERFLOW_UNCONNECTED\
);
\ARG__7_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_22\(14),
O => \ARG__7_i_1_n_0\
);
\ARG__8\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__8_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[5]_4\(15),
B(16) => \weight_reg[5]_4\(15),
B(15 downto 0) => \weight_reg[5]_4\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__8_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_5\(14),
C(12) => \ARG__8_i_1_n_0\,
C(11) => \ARG__8_i_1_n_0\,
C(10) => \ARG__8_i_1_n_0\,
C(9) => \ARG__8_i_1_n_0\,
C(8) => \ARG__8_i_1_n_0\,
C(7) => \ARG__8_i_1_n_0\,
C(6) => \ARG__8_i_1_n_0\,
C(5) => \ARG__8_i_1_n_0\,
C(4) => \ARG__8_i_1_n_0\,
C(3) => \ARG__8_i_1_n_0\,
C(2) => \ARG__8_i_1_n_0\,
C(1) => \ARG__8_i_1_n_0\,
C(0) => \ARG__8_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__8_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__8_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__8_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__8_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__8_P_UNCONNECTED\(47 downto 30),
P(29 downto 14) => RESIZE24(15 downto 0),
P(13) => \ARG__8_n_92\,
P(12) => \ARG__8_n_93\,
P(11) => \ARG__8_n_94\,
P(10) => \ARG__8_n_95\,
P(9) => \ARG__8_n_96\,
P(8) => \ARG__8_n_97\,
P(7) => \ARG__8_n_98\,
P(6) => \ARG__8_n_99\,
P(5) => \ARG__8_n_100\,
P(4) => \ARG__8_n_101\,
P(3) => \ARG__8_n_102\,
P(2) => \ARG__8_n_103\,
P(1) => \ARG__8_n_104\,
P(0) => \ARG__8_n_105\,
PATTERNBDETECT => \NLW_ARG__8_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__8_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__8_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__8_UNDERFLOW_UNCONNECTED\
);
\ARG__8_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_5\(14),
O => \ARG__8_i_1_n_0\
);
\ARG__9\: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 0,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => \NLW_ARG__9_ACOUT_UNCONNECTED\(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => \NLW_ARG__9_BCOUT_UNCONNECTED\(17 downto 0),
C(47 downto 14) => B"0000000000000000000000000000000000",
C(13) => \^mul_temp_23\(14),
C(12) => \ARG__9_i_1_n_0\,
C(11) => \ARG__9_i_1_n_0\,
C(10) => \ARG__9_i_1_n_0\,
C(9) => \ARG__9_i_1_n_0\,
C(8) => \ARG__9_i_1_n_0\,
C(7) => \ARG__9_i_1_n_0\,
C(6) => \ARG__9_i_1_n_0\,
C(5) => \ARG__9_i_1_n_0\,
C(4) => \ARG__9_i_1_n_0\,
C(3) => \ARG__9_i_1_n_0\,
C(2) => \ARG__9_i_1_n_0\,
C(1) => \ARG__9_i_1_n_0\,
C(0) => \ARG__9_i_1_n_0\,
CARRYCASCIN => '0',
CARRYCASCOUT => \NLW_ARG__9_CARRYCASCOUT_UNCONNECTED\,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => \NLW_ARG__9_CARRYOUT_UNCONNECTED\(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => \NLW_ARG__9_MULTSIGNOUT_UNCONNECTED\,
OPMODE(6 downto 0) => B"0110101",
OVERFLOW => \NLW_ARG__9_OVERFLOW_UNCONNECTED\,
P(47 downto 30) => \NLW_ARG__9_P_UNCONNECTED\(47 downto 30),
P(29) => \ARG__9_n_76\,
P(28) => \ARG__9_n_77\,
P(27) => \ARG__9_n_78\,
P(26) => \ARG__9_n_79\,
P(25) => \ARG__9_n_80\,
P(24) => \ARG__9_n_81\,
P(23) => \ARG__9_n_82\,
P(22) => \ARG__9_n_83\,
P(21) => \ARG__9_n_84\,
P(20) => \ARG__9_n_85\,
P(19) => \ARG__9_n_86\,
P(18) => \ARG__9_n_87\,
P(17) => \ARG__9_n_88\,
P(16) => \ARG__9_n_89\,
P(15) => \ARG__9_n_90\,
P(14) => \ARG__9_n_91\,
P(13) => \ARG__9_n_92\,
P(12) => \ARG__9_n_93\,
P(11) => \ARG__9_n_94\,
P(10) => \ARG__9_n_95\,
P(9) => \ARG__9_n_96\,
P(8) => \ARG__9_n_97\,
P(7) => \ARG__9_n_98\,
P(6) => \ARG__9_n_99\,
P(5) => \ARG__9_n_100\,
P(4) => \ARG__9_n_101\,
P(3) => \ARG__9_n_102\,
P(2) => \ARG__9_n_103\,
P(1) => \ARG__9_n_104\,
P(0) => \ARG__9_n_105\,
PATTERNBDETECT => \NLW_ARG__9_PATTERNBDETECT_UNCONNECTED\,
PATTERNDETECT => \NLW_ARG__9_PATTERNDETECT_UNCONNECTED\,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => \NLW_ARG__9_PCOUT_UNCONNECTED\(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => \NLW_ARG__9_UNDERFLOW_UNCONNECTED\
);
\ARG__9_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_23\(14),
O => \ARG__9_i_1_n_0\
);
ARG_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => ARG_carry_n_0,
CO(2) => ARG_carry_n_1,
CO(1) => ARG_carry_n_2,
CO(0) => ARG_carry_n_3,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 1) => \^mul_temp_16\(1 downto 0),
DI(0) => '1',
O(3 downto 0) => NLW_ARG_carry_O_UNCONNECTED(3 downto 0),
S(3) => \^mul_temp_16\(2),
S(2 downto 0) => \write_reg_d_k_reg[3]\(2 downto 0)
);
\ARG_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => ARG_carry_n_0,
CO(3) => \ARG_carry__0_n_0\,
CO(2) => \ARG_carry__0_n_1\,
CO(1) => \ARG_carry__0_n_2\,
CO(0) => \ARG_carry__0_n_3\,
CYINIT => '0',
DI(3) => \^mul_temp_16\(5),
DI(2) => \^mul_temp_16\(3),
DI(1) => \^mul_temp_16\(4),
DI(0) => DI(0),
O(3 downto 0) => \ARG__31\(20 downto 17),
S(3) => \ARG_carry__0_i_2_n_0\,
S(2) => \ARG_carry__0_i_3_n_0\,
S(1) => \ARG_carry__0_i_4_n_0\,
S(0) => \^mul_temp_16\(3)
);
\ARG_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(5),
I1 => \^mul_temp_16\(6),
O => \ARG_carry__0_i_2_n_0\
);
\ARG_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(3),
I1 => \^mul_temp_16\(5),
O => \ARG_carry__0_i_3_n_0\
);
\ARG_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(3),
I1 => \^mul_temp_16\(4),
O => \ARG_carry__0_i_4_n_0\
);
\ARG_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__0_n_0\,
CO(3) => \ARG_carry__1_n_0\,
CO(2) => \ARG_carry__1_n_1\,
CO(1) => \ARG_carry__1_n_2\,
CO(0) => \ARG_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^mul_temp_16\(9 downto 6),
O(3 downto 0) => \ARG__31\(24 downto 21),
S(3) => \ARG_carry__1_i_1_n_0\,
S(2) => \ARG_carry__1_i_2_n_0\,
S(1) => \ARG_carry__1_i_3_n_0\,
S(0) => \ARG_carry__1_i_4_n_0\
);
\ARG_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(9),
I1 => \^mul_temp_16\(10),
O => \ARG_carry__1_i_1_n_0\
);
\ARG_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(8),
I1 => \^mul_temp_16\(9),
O => \ARG_carry__1_i_2_n_0\
);
\ARG_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(7),
I1 => \^mul_temp_16\(8),
O => \ARG_carry__1_i_3_n_0\
);
\ARG_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(6),
I1 => \^mul_temp_16\(7),
O => \ARG_carry__1_i_4_n_0\
);
\ARG_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__1_n_0\,
CO(3) => \ARG_carry__2_n_0\,
CO(2) => \ARG_carry__2_n_1\,
CO(1) => \ARG_carry__2_n_2\,
CO(0) => \ARG_carry__2_n_3\,
CYINIT => '0',
DI(3 downto 0) => \^mul_temp_16\(13 downto 10),
O(3 downto 0) => \ARG__31\(28 downto 25),
S(3) => \ARG_carry__2_i_1_n_0\,
S(2) => \ARG_carry__2_i_2_n_0\,
S(1) => \ARG_carry__2_i_3_n_0\,
S(0) => \ARG_carry__2_i_4_n_0\
);
\ARG_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(13),
I1 => \^mul_temp_16\(14),
O => \ARG_carry__2_i_1_n_0\
);
\ARG_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(12),
I1 => \^mul_temp_16\(13),
O => \ARG_carry__2_i_2_n_0\
);
\ARG_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(11),
I1 => \^mul_temp_16\(12),
O => \ARG_carry__2_i_3_n_0\
);
\ARG_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(10),
I1 => \^mul_temp_16\(11),
O => \ARG_carry__2_i_4_n_0\
);
\ARG_carry__3\: unisim.vcomponents.CARRY4
port map (
CI => \ARG_carry__2_n_0\,
CO(3 downto 1) => \NLW_ARG_carry__3_CO_UNCONNECTED\(3 downto 1),
CO(0) => \ARG_carry__3_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \^mul_temp_16\(14),
O(3 downto 2) => \NLW_ARG_carry__3_O_UNCONNECTED\(3 downto 2),
O(1) => \ARG__31\(32),
O(0) => \ARG__31\(29),
S(3 downto 1) => B"001",
S(0) => \ARG_carry__3_i_1_n_0\
);
\ARG_carry__3_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^mul_temp_16\(14),
I1 => \^mul_temp_16\(15),
O => \ARG_carry__3_i_1_n_0\
);
ARG_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^mul_temp_18\(14),
O => ARG_i_1_n_0
);
\add_temp_14__0_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__0_carry_n_0\,
CO(2) => \add_temp_14__0_carry_n_1\,
CO(1) => \add_temp_14__0_carry_n_2\,
CO(0) => \add_temp_14__0_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry_i_1_n_0\,
DI(2) => \add_temp_14__0_carry_i_2_n_0\,
DI(1) => \add_temp_14__0_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__0_carry_n_4\,
O(2) => \add_temp_14__0_carry_n_5\,
O(1) => \add_temp_14__0_carry_n_6\,
O(0) => \add_temp_14__0_carry_n_7\,
S(3) => \add_temp_14__0_carry_i_4_n_0\,
S(2) => \add_temp_14__0_carry_i_5_n_0\,
S(1) => \add_temp_14__0_carry_i_6_n_0\,
S(0) => \add_temp_14__0_carry_i_7_n_0\
);
\add_temp_14__0_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry_n_0\,
CO(3) => \add_temp_14__0_carry__0_n_0\,
CO(2) => \add_temp_14__0_carry__0_n_1\,
CO(1) => \add_temp_14__0_carry__0_n_2\,
CO(0) => \add_temp_14__0_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__0_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__0_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__0_carry__0_i_4_n_0\,
O(3) => \add_temp_14__0_carry__0_n_4\,
O(2) => \add_temp_14__0_carry__0_n_5\,
O(1) => \add_temp_14__0_carry__0_n_6\,
O(0) => \add_temp_14__0_carry__0_n_7\,
S(3) => \add_temp_14__0_carry__0_i_5_n_0\,
S(2) => \add_temp_14__0_carry__0_i_6_n_0\,
S(1) => \add_temp_14__0_carry__0_i_7_n_0\,
S(0) => \add_temp_14__0_carry__0_i_8_n_0\
);
\add_temp_14__0_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(6),
I1 => RESIZE15(6),
I2 => RESIZE42(6),
O => \add_temp_14__0_carry__0_i_1_n_0\
);
\add_temp_14__0_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(5),
I1 => RESIZE15(5),
I2 => RESIZE42(5),
O => \add_temp_14__0_carry__0_i_2_n_0\
);
\add_temp_14__0_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(4),
I1 => RESIZE15(4),
I2 => RESIZE42(4),
O => \add_temp_14__0_carry__0_i_3_n_0\
);
\add_temp_14__0_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(3),
I1 => RESIZE15(3),
I2 => RESIZE42(3),
O => \add_temp_14__0_carry__0_i_4_n_0\
);
\add_temp_14__0_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(7),
I1 => RESIZE15(7),
I2 => RESIZE42(7),
I3 => \add_temp_14__0_carry__0_i_1_n_0\,
O => \add_temp_14__0_carry__0_i_5_n_0\
);
\add_temp_14__0_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(6),
I1 => RESIZE15(6),
I2 => RESIZE42(6),
I3 => \add_temp_14__0_carry__0_i_2_n_0\,
O => \add_temp_14__0_carry__0_i_6_n_0\
);
\add_temp_14__0_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(5),
I1 => RESIZE15(5),
I2 => RESIZE42(5),
I3 => \add_temp_14__0_carry__0_i_3_n_0\,
O => \add_temp_14__0_carry__0_i_7_n_0\
);
\add_temp_14__0_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(4),
I1 => RESIZE15(4),
I2 => RESIZE42(4),
I3 => \add_temp_14__0_carry__0_i_4_n_0\,
O => \add_temp_14__0_carry__0_i_8_n_0\
);
\add_temp_14__0_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry__0_n_0\,
CO(3) => \add_temp_14__0_carry__1_n_0\,
CO(2) => \add_temp_14__0_carry__1_n_1\,
CO(1) => \add_temp_14__0_carry__1_n_2\,
CO(0) => \add_temp_14__0_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__0_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__0_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__0_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__0_carry__1_i_4_n_0\,
O(3) => \add_temp_14__0_carry__1_n_4\,
O(2) => \add_temp_14__0_carry__1_n_5\,
O(1) => \add_temp_14__0_carry__1_n_6\,
O(0) => \add_temp_14__0_carry__1_n_7\,
S(3) => \add_temp_14__0_carry__1_i_5_n_0\,
S(2) => \add_temp_14__0_carry__1_i_6_n_0\,
S(1) => \add_temp_14__0_carry__1_i_7_n_0\,
S(0) => \add_temp_14__0_carry__1_i_8_n_0\
);
\add_temp_14__0_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(10),
I1 => RESIZE42(10),
I2 => RESIZE15(10),
O => \add_temp_14__0_carry__1_i_1_n_0\
);
\add_temp_14__0_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(9),
I1 => RESIZE42(9),
I2 => RESIZE15(9),
O => \add_temp_14__0_carry__1_i_2_n_0\
);
\add_temp_14__0_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(8),
I1 => RESIZE15(8),
I2 => RESIZE42(8),
O => \add_temp_14__0_carry__1_i_3_n_0\
);
\add_temp_14__0_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(7),
I1 => RESIZE15(7),
I2 => RESIZE42(7),
O => \add_temp_14__0_carry__1_i_4_n_0\
);
\add_temp_14__0_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(11),
I1 => RESIZE15(11),
I2 => RESIZE42(11),
I3 => \add_temp_14__0_carry__1_i_1_n_0\,
O => \add_temp_14__0_carry__1_i_5_n_0\
);
\add_temp_14__0_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(10),
I1 => RESIZE42(10),
I2 => RESIZE15(10),
I3 => \add_temp_14__0_carry__1_i_2_n_0\,
O => \add_temp_14__0_carry__1_i_6_n_0\
);
\add_temp_14__0_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(9),
I1 => RESIZE42(9),
I2 => RESIZE15(9),
I3 => \add_temp_14__0_carry__1_i_3_n_0\,
O => \add_temp_14__0_carry__1_i_7_n_0\
);
\add_temp_14__0_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(8),
I1 => RESIZE15(8),
I2 => RESIZE42(8),
I3 => \add_temp_14__0_carry__1_i_4_n_0\,
O => \add_temp_14__0_carry__1_i_8_n_0\
);
\add_temp_14__0_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__0_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__0_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__0_carry__2_n_1\,
CO(1) => \add_temp_14__0_carry__2_n_2\,
CO(0) => \add_temp_14__0_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__0_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__0_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__0_carry__2_i_3_n_0\,
O(3) => \add_temp_14__0_carry__2_n_4\,
O(2) => \add_temp_14__0_carry__2_n_5\,
O(1) => \add_temp_14__0_carry__2_n_6\,
O(0) => \add_temp_14__0_carry__2_n_7\,
S(3) => \add_temp_14__0_carry__2_i_4_n_0\,
S(2) => \add_temp_14__0_carry__2_i_5_n_0\,
S(1) => \add_temp_14__0_carry__2_i_6_n_0\,
S(0) => \add_temp_14__0_carry__2_i_7_n_0\
);
\add_temp_14__0_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE15(13),
I1 => RESIZE42(13),
I2 => RESIZE44(13),
O => \add_temp_14__0_carry__2_i_1_n_0\
);
\add_temp_14__0_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(12),
I1 => RESIZE15(12),
I2 => RESIZE42(12),
O => \add_temp_14__0_carry__2_i_2_n_0\
);
\add_temp_14__0_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(11),
I1 => RESIZE15(11),
I2 => RESIZE42(11),
O => \add_temp_14__0_carry__2_i_3_n_0\
);
\add_temp_14__0_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE15(14),
I1 => RESIZE44(14),
I2 => RESIZE42(14),
I3 => RESIZE44(15),
I4 => RESIZE42(15),
I5 => RESIZE15(15),
O => \add_temp_14__0_carry__2_i_4_n_0\
);
\add_temp_14__0_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__2_i_1_n_0\,
I1 => RESIZE44(14),
I2 => RESIZE42(14),
I3 => RESIZE15(14),
O => \add_temp_14__0_carry__2_i_5_n_0\
);
\add_temp_14__0_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE15(13),
I1 => RESIZE42(13),
I2 => RESIZE44(13),
I3 => \add_temp_14__0_carry__2_i_2_n_0\,
O => \add_temp_14__0_carry__2_i_6_n_0\
);
\add_temp_14__0_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(12),
I1 => RESIZE15(12),
I2 => RESIZE42(12),
I3 => \add_temp_14__0_carry__2_i_3_n_0\,
O => \add_temp_14__0_carry__2_i_7_n_0\
);
\add_temp_14__0_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(2),
I1 => RESIZE15(2),
I2 => RESIZE42(2),
O => \add_temp_14__0_carry_i_1_n_0\
);
\add_temp_14__0_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(1),
I1 => RESIZE15(1),
I2 => RESIZE42(1),
O => \add_temp_14__0_carry_i_2_n_0\
);
\add_temp_14__0_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE44(0),
I1 => RESIZE15(0),
I2 => RESIZE42(0),
O => \add_temp_14__0_carry_i_3_n_0\
);
\add_temp_14__0_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(3),
I1 => RESIZE15(3),
I2 => RESIZE42(3),
I3 => \add_temp_14__0_carry_i_1_n_0\,
O => \add_temp_14__0_carry_i_4_n_0\
);
\add_temp_14__0_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(2),
I1 => RESIZE15(2),
I2 => RESIZE42(2),
I3 => \add_temp_14__0_carry_i_2_n_0\,
O => \add_temp_14__0_carry_i_5_n_0\
);
\add_temp_14__0_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE44(1),
I1 => RESIZE15(1),
I2 => RESIZE42(1),
I3 => \add_temp_14__0_carry_i_3_n_0\,
O => \add_temp_14__0_carry_i_6_n_0\
);
\add_temp_14__0_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE44(0),
I1 => RESIZE15(0),
I2 => RESIZE42(0),
O => \add_temp_14__0_carry_i_7_n_0\
);
\add_temp_14__138_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__138_carry_n_0\,
CO(2) => \add_temp_14__138_carry_n_1\,
CO(1) => \add_temp_14__138_carry_n_2\,
CO(0) => \add_temp_14__138_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry_i_1_n_0\,
DI(2) => \add_temp_14__138_carry_i_2_n_0\,
DI(1) => \add_temp_14__138_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__138_carry_n_4\,
O(2) => \add_temp_14__138_carry_n_5\,
O(1) => \add_temp_14__138_carry_n_6\,
O(0) => \add_temp_14__138_carry_n_7\,
S(3) => \add_temp_14__138_carry_i_4_n_0\,
S(2) => \add_temp_14__138_carry_i_5_n_0\,
S(1) => \add_temp_14__138_carry_i_6_n_0\,
S(0) => \add_temp_14__138_carry_i_7_n_0\
);
\add_temp_14__138_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry_n_0\,
CO(3) => \add_temp_14__138_carry__0_n_0\,
CO(2) => \add_temp_14__138_carry__0_n_1\,
CO(1) => \add_temp_14__138_carry__0_n_2\,
CO(0) => \add_temp_14__138_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__138_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__138_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__138_carry__0_i_4_n_0\,
O(3) => \add_temp_14__138_carry__0_n_4\,
O(2) => \add_temp_14__138_carry__0_n_5\,
O(1) => \add_temp_14__138_carry__0_n_6\,
O(0) => \add_temp_14__138_carry__0_n_7\,
S(3) => \add_temp_14__138_carry__0_i_5_n_0\,
S(2) => \add_temp_14__138_carry__0_i_6_n_0\,
S(1) => \add_temp_14__138_carry__0_i_7_n_0\,
S(0) => \add_temp_14__138_carry__0_i_8_n_0\
);
\add_temp_14__138_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(6),
I1 => RESIZE26(6),
I2 => RESIZE28(6),
O => \add_temp_14__138_carry__0_i_1_n_0\
);
\add_temp_14__138_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE28(5),
I1 => RESIZE24(5),
I2 => RESIZE26(5),
O => \add_temp_14__138_carry__0_i_2_n_0\
);
\add_temp_14__138_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(4),
I1 => RESIZE24(4),
I2 => RESIZE28(4),
O => \add_temp_14__138_carry__0_i_3_n_0\
);
\add_temp_14__138_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(3),
I1 => RESIZE28(3),
I2 => RESIZE24(3),
O => \add_temp_14__138_carry__0_i_4_n_0\
);
\add_temp_14__138_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(7),
I1 => RESIZE26(7),
I2 => RESIZE28(7),
I3 => \add_temp_14__138_carry__0_i_1_n_0\,
O => \add_temp_14__138_carry__0_i_5_n_0\
);
\add_temp_14__138_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(6),
I1 => RESIZE26(6),
I2 => RESIZE28(6),
I3 => \add_temp_14__138_carry__0_i_2_n_0\,
O => \add_temp_14__138_carry__0_i_6_n_0\
);
\add_temp_14__138_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE28(5),
I1 => RESIZE24(5),
I2 => RESIZE26(5),
I3 => \add_temp_14__138_carry__0_i_3_n_0\,
O => \add_temp_14__138_carry__0_i_7_n_0\
);
\add_temp_14__138_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(4),
I1 => RESIZE24(4),
I2 => RESIZE28(4),
I3 => \add_temp_14__138_carry__0_i_4_n_0\,
O => \add_temp_14__138_carry__0_i_8_n_0\
);
\add_temp_14__138_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry__0_n_0\,
CO(3) => \add_temp_14__138_carry__1_n_0\,
CO(2) => \add_temp_14__138_carry__1_n_1\,
CO(1) => \add_temp_14__138_carry__1_n_2\,
CO(0) => \add_temp_14__138_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__138_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__138_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__138_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__138_carry__1_i_4_n_0\,
O(3) => \add_temp_14__138_carry__1_n_4\,
O(2) => \add_temp_14__138_carry__1_n_5\,
O(1) => \add_temp_14__138_carry__1_n_6\,
O(0) => \add_temp_14__138_carry__1_n_7\,
S(3) => \add_temp_14__138_carry__1_i_5_n_0\,
S(2) => \add_temp_14__138_carry__1_i_6_n_0\,
S(1) => \add_temp_14__138_carry__1_i_7_n_0\,
S(0) => \add_temp_14__138_carry__1_i_8_n_0\
);
\add_temp_14__138_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(10),
I1 => RESIZE26(10),
I2 => RESIZE28(10),
O => \add_temp_14__138_carry__1_i_1_n_0\
);
\add_temp_14__138_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(9),
I1 => RESIZE26(9),
I2 => RESIZE28(9),
O => \add_temp_14__138_carry__1_i_2_n_0\
);
\add_temp_14__138_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(8),
I1 => RESIZE26(8),
I2 => RESIZE28(8),
O => \add_temp_14__138_carry__1_i_3_n_0\
);
\add_temp_14__138_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(7),
I1 => RESIZE26(7),
I2 => RESIZE28(7),
O => \add_temp_14__138_carry__1_i_4_n_0\
);
\add_temp_14__138_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(11),
I1 => RESIZE26(11),
I2 => RESIZE28(11),
I3 => \add_temp_14__138_carry__1_i_1_n_0\,
O => \add_temp_14__138_carry__1_i_5_n_0\
);
\add_temp_14__138_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(10),
I1 => RESIZE26(10),
I2 => RESIZE28(10),
I3 => \add_temp_14__138_carry__1_i_2_n_0\,
O => \add_temp_14__138_carry__1_i_6_n_0\
);
\add_temp_14__138_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(9),
I1 => RESIZE26(9),
I2 => RESIZE28(9),
I3 => \add_temp_14__138_carry__1_i_3_n_0\,
O => \add_temp_14__138_carry__1_i_7_n_0\
);
\add_temp_14__138_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(8),
I1 => RESIZE26(8),
I2 => RESIZE28(8),
I3 => \add_temp_14__138_carry__1_i_4_n_0\,
O => \add_temp_14__138_carry__1_i_8_n_0\
);
\add_temp_14__138_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__138_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__138_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__138_carry__2_n_1\,
CO(1) => \add_temp_14__138_carry__2_n_2\,
CO(0) => \add_temp_14__138_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__138_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__138_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__138_carry__2_i_3_n_0\,
O(3) => \add_temp_14__138_carry__2_n_4\,
O(2) => \add_temp_14__138_carry__2_n_5\,
O(1) => \add_temp_14__138_carry__2_n_6\,
O(0) => \add_temp_14__138_carry__2_n_7\,
S(3) => \add_temp_14__138_carry__2_i_4_n_0\,
S(2) => \add_temp_14__138_carry__2_i_5_n_0\,
S(1) => \add_temp_14__138_carry__2_i_6_n_0\,
S(0) => \add_temp_14__138_carry__2_i_7_n_0\
);
\add_temp_14__138_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(13),
I1 => RESIZE26(13),
I2 => RESIZE28(13),
O => \add_temp_14__138_carry__2_i_1_n_0\
);
\add_temp_14__138_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(12),
I1 => RESIZE26(12),
I2 => RESIZE28(12),
O => \add_temp_14__138_carry__2_i_2_n_0\
);
\add_temp_14__138_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE24(11),
I1 => RESIZE26(11),
I2 => RESIZE28(11),
O => \add_temp_14__138_carry__2_i_3_n_0\
);
\add_temp_14__138_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE28(14),
I1 => RESIZE26(14),
I2 => RESIZE24(14),
I3 => RESIZE26(15),
I4 => RESIZE24(15),
I5 => RESIZE28(15),
O => \add_temp_14__138_carry__2_i_4_n_0\
);
\add_temp_14__138_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__138_carry__2_i_1_n_0\,
I1 => RESIZE26(14),
I2 => RESIZE24(14),
I3 => RESIZE28(14),
O => \add_temp_14__138_carry__2_i_5_n_0\
);
\add_temp_14__138_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(13),
I1 => RESIZE26(13),
I2 => RESIZE28(13),
I3 => \add_temp_14__138_carry__2_i_2_n_0\,
O => \add_temp_14__138_carry__2_i_6_n_0\
);
\add_temp_14__138_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE24(12),
I1 => RESIZE26(12),
I2 => RESIZE28(12),
I3 => \add_temp_14__138_carry__2_i_3_n_0\,
O => \add_temp_14__138_carry__2_i_7_n_0\
);
\add_temp_14__138_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(2),
I1 => RESIZE28(2),
I2 => RESIZE24(2),
O => \add_temp_14__138_carry_i_1_n_0\
);
\add_temp_14__138_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(1),
I1 => RESIZE28(1),
I2 => RESIZE24(1),
O => \add_temp_14__138_carry_i_2_n_0\
);
\add_temp_14__138_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE26(0),
I1 => RESIZE28(0),
I2 => RESIZE24(0),
O => \add_temp_14__138_carry_i_3_n_0\
);
\add_temp_14__138_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(3),
I1 => RESIZE28(3),
I2 => RESIZE24(3),
I3 => \add_temp_14__138_carry_i_1_n_0\,
O => \add_temp_14__138_carry_i_4_n_0\
);
\add_temp_14__138_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(2),
I1 => RESIZE28(2),
I2 => RESIZE24(2),
I3 => \add_temp_14__138_carry_i_2_n_0\,
O => \add_temp_14__138_carry_i_5_n_0\
);
\add_temp_14__138_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE26(1),
I1 => RESIZE28(1),
I2 => RESIZE24(1),
I3 => \add_temp_14__138_carry_i_3_n_0\,
O => \add_temp_14__138_carry_i_6_n_0\
);
\add_temp_14__138_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE26(0),
I1 => RESIZE28(0),
I2 => RESIZE24(0),
O => \add_temp_14__138_carry_i_7_n_0\
);
\add_temp_14__184_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__184_carry_n_0\,
CO(2) => \add_temp_14__184_carry_n_1\,
CO(1) => \add_temp_14__184_carry_n_2\,
CO(0) => \add_temp_14__184_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry_i_1_n_0\,
DI(2) => \add_temp_14__184_carry_i_2_n_0\,
DI(1) => \add_temp_14__184_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__184_carry_n_4\,
O(2) => \add_temp_14__184_carry_n_5\,
O(1) => \add_temp_14__184_carry_n_6\,
O(0) => \add_temp_14__184_carry_n_7\,
S(3) => \add_temp_14__184_carry_i_4_n_0\,
S(2) => \add_temp_14__184_carry_i_5_n_0\,
S(1) => \add_temp_14__184_carry_i_6_n_0\,
S(0) => \add_temp_14__184_carry_i_7_n_0\
);
\add_temp_14__184_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry_n_0\,
CO(3) => \add_temp_14__184_carry__0_n_0\,
CO(2) => \add_temp_14__184_carry__0_n_1\,
CO(1) => \add_temp_14__184_carry__0_n_2\,
CO(0) => \add_temp_14__184_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__184_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__184_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__184_carry__0_i_4_n_0\,
O(3) => \add_temp_14__184_carry__0_n_4\,
O(2) => \add_temp_14__184_carry__0_n_5\,
O(1) => \add_temp_14__184_carry__0_n_6\,
O(0) => \add_temp_14__184_carry__0_n_7\,
S(3) => \add_temp_14__184_carry__0_i_5_n_0\,
S(2) => \add_temp_14__184_carry__0_i_6_n_0\,
S(1) => \add_temp_14__184_carry__0_i_7_n_0\,
S(0) => \add_temp_14__184_carry__0_i_8_n_0\
);
\add_temp_14__184_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(6),
I1 => RESIZE18(6),
I2 => RESIZE22(6),
O => \add_temp_14__184_carry__0_i_1_n_0\
);
\add_temp_14__184_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(5),
I1 => RESIZE18(5),
I2 => RESIZE22(5),
O => \add_temp_14__184_carry__0_i_2_n_0\
);
\add_temp_14__184_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(4),
I1 => RESIZE18(4),
I2 => RESIZE22(4),
O => \add_temp_14__184_carry__0_i_3_n_0\
);
\add_temp_14__184_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(3),
I1 => RESIZE22(3),
I2 => RESIZE20(3),
O => \add_temp_14__184_carry__0_i_4_n_0\
);
\add_temp_14__184_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(7),
I1 => RESIZE18(7),
I2 => RESIZE22(7),
I3 => \add_temp_14__184_carry__0_i_1_n_0\,
O => \add_temp_14__184_carry__0_i_5_n_0\
);
\add_temp_14__184_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(6),
I1 => RESIZE18(6),
I2 => RESIZE22(6),
I3 => \add_temp_14__184_carry__0_i_2_n_0\,
O => \add_temp_14__184_carry__0_i_6_n_0\
);
\add_temp_14__184_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(5),
I1 => RESIZE18(5),
I2 => RESIZE22(5),
I3 => \add_temp_14__184_carry__0_i_3_n_0\,
O => \add_temp_14__184_carry__0_i_7_n_0\
);
\add_temp_14__184_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(4),
I1 => RESIZE18(4),
I2 => RESIZE22(4),
I3 => \add_temp_14__184_carry__0_i_4_n_0\,
O => \add_temp_14__184_carry__0_i_8_n_0\
);
\add_temp_14__184_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry__0_n_0\,
CO(3) => \add_temp_14__184_carry__1_n_0\,
CO(2) => \add_temp_14__184_carry__1_n_1\,
CO(1) => \add_temp_14__184_carry__1_n_2\,
CO(0) => \add_temp_14__184_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__184_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__184_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__184_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__184_carry__1_i_4_n_0\,
O(3) => \add_temp_14__184_carry__1_n_4\,
O(2) => \add_temp_14__184_carry__1_n_5\,
O(1) => \add_temp_14__184_carry__1_n_6\,
O(0) => \add_temp_14__184_carry__1_n_7\,
S(3) => \add_temp_14__184_carry__1_i_5_n_0\,
S(2) => \add_temp_14__184_carry__1_i_6_n_0\,
S(1) => \add_temp_14__184_carry__1_i_7_n_0\,
S(0) => \add_temp_14__184_carry__1_i_8_n_0\
);
\add_temp_14__184_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(10),
I1 => RESIZE22(10),
I2 => RESIZE20(10),
O => \add_temp_14__184_carry__1_i_1_n_0\
);
\add_temp_14__184_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(9),
I1 => RESIZE22(9),
I2 => RESIZE20(9),
O => \add_temp_14__184_carry__1_i_2_n_0\
);
\add_temp_14__184_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(8),
I1 => RESIZE22(8),
I2 => RESIZE20(8),
O => \add_temp_14__184_carry__1_i_3_n_0\
);
\add_temp_14__184_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(7),
I1 => RESIZE18(7),
I2 => RESIZE22(7),
O => \add_temp_14__184_carry__1_i_4_n_0\
);
\add_temp_14__184_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(11),
I1 => RESIZE22(11),
I2 => RESIZE20(11),
I3 => \add_temp_14__184_carry__1_i_1_n_0\,
O => \add_temp_14__184_carry__1_i_5_n_0\
);
\add_temp_14__184_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(10),
I1 => RESIZE22(10),
I2 => RESIZE20(10),
I3 => \add_temp_14__184_carry__1_i_2_n_0\,
O => \add_temp_14__184_carry__1_i_6_n_0\
);
\add_temp_14__184_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(9),
I1 => RESIZE22(9),
I2 => RESIZE20(9),
I3 => \add_temp_14__184_carry__1_i_3_n_0\,
O => \add_temp_14__184_carry__1_i_7_n_0\
);
\add_temp_14__184_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(8),
I1 => RESIZE22(8),
I2 => RESIZE20(8),
I3 => \add_temp_14__184_carry__1_i_4_n_0\,
O => \add_temp_14__184_carry__1_i_8_n_0\
);
\add_temp_14__184_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__184_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__184_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__184_carry__2_n_1\,
CO(1) => \add_temp_14__184_carry__2_n_2\,
CO(0) => \add_temp_14__184_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__184_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__184_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__184_carry__2_i_3_n_0\,
O(3) => \add_temp_14__184_carry__2_n_4\,
O(2) => \add_temp_14__184_carry__2_n_5\,
O(1) => \add_temp_14__184_carry__2_n_6\,
O(0) => \add_temp_14__184_carry__2_n_7\,
S(3) => \add_temp_14__184_carry__2_i_4_n_0\,
S(2) => \add_temp_14__184_carry__2_i_5_n_0\,
S(1) => \add_temp_14__184_carry__2_i_6_n_0\,
S(0) => \add_temp_14__184_carry__2_i_7_n_0\
);
\add_temp_14__184_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(13),
I1 => RESIZE22(13),
I2 => RESIZE20(13),
O => \add_temp_14__184_carry__2_i_1_n_0\
);
\add_temp_14__184_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(12),
I1 => RESIZE22(12),
I2 => RESIZE20(12),
O => \add_temp_14__184_carry__2_i_2_n_0\
);
\add_temp_14__184_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(11),
I1 => RESIZE22(11),
I2 => RESIZE20(11),
O => \add_temp_14__184_carry__2_i_3_n_0\
);
\add_temp_14__184_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE20(14),
I1 => RESIZE22(14),
I2 => RESIZE18(14),
I3 => RESIZE20(15),
I4 => RESIZE18(15),
I5 => RESIZE22(15),
O => \add_temp_14__184_carry__2_i_4_n_0\
);
\add_temp_14__184_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry__2_i_1_n_0\,
I1 => RESIZE20(14),
I2 => RESIZE18(14),
I3 => RESIZE22(14),
O => \add_temp_14__184_carry__2_i_5_n_0\
);
\add_temp_14__184_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(13),
I1 => RESIZE22(13),
I2 => RESIZE20(13),
I3 => \add_temp_14__184_carry__2_i_2_n_0\,
O => \add_temp_14__184_carry__2_i_6_n_0\
);
\add_temp_14__184_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(12),
I1 => RESIZE22(12),
I2 => RESIZE20(12),
I3 => \add_temp_14__184_carry__2_i_3_n_0\,
O => \add_temp_14__184_carry__2_i_7_n_0\
);
\add_temp_14__184_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE22(2),
I1 => RESIZE18(2),
I2 => RESIZE20(2),
O => \add_temp_14__184_carry_i_1_n_0\
);
\add_temp_14__184_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE20(1),
I1 => RESIZE18(1),
I2 => RESIZE22(1),
O => \add_temp_14__184_carry_i_2_n_0\
);
\add_temp_14__184_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE18(0),
I1 => RESIZE22(0),
I2 => RESIZE20(0),
O => \add_temp_14__184_carry_i_3_n_0\
);
\add_temp_14__184_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE18(3),
I1 => RESIZE22(3),
I2 => RESIZE20(3),
I3 => \add_temp_14__184_carry_i_1_n_0\,
O => \add_temp_14__184_carry_i_4_n_0\
);
\add_temp_14__184_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE22(2),
I1 => RESIZE18(2),
I2 => RESIZE20(2),
I3 => \add_temp_14__184_carry_i_2_n_0\,
O => \add_temp_14__184_carry_i_5_n_0\
);
\add_temp_14__184_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE20(1),
I1 => RESIZE18(1),
I2 => RESIZE22(1),
I3 => \add_temp_14__184_carry_i_3_n_0\,
O => \add_temp_14__184_carry_i_6_n_0\
);
\add_temp_14__184_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE18(0),
I1 => RESIZE22(0),
I2 => RESIZE20(0),
O => \add_temp_14__184_carry_i_7_n_0\
);
\add_temp_14__230_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__230_carry_n_0\,
CO(2) => \add_temp_14__230_carry_n_1\,
CO(1) => \add_temp_14__230_carry_n_2\,
CO(0) => \add_temp_14__230_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry_i_1_n_0\,
DI(2) => \add_temp_14__230_carry_i_2_n_0\,
DI(1) => \add_temp_14__230_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__230_carry_n_4\,
O(2) => \add_temp_14__230_carry_n_5\,
O(1) => \add_temp_14__230_carry_n_6\,
O(0) => \add_temp_14__230_carry_n_7\,
S(3) => \add_temp_14__230_carry_i_4_n_0\,
S(2) => \add_temp_14__230_carry_i_5_n_0\,
S(1) => \add_temp_14__230_carry_i_6_n_0\,
S(0) => \add_temp_14__230_carry_i_7_n_0\
);
\add_temp_14__230_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry_n_0\,
CO(3) => \add_temp_14__230_carry__0_n_0\,
CO(2) => \add_temp_14__230_carry__0_n_1\,
CO(1) => \add_temp_14__230_carry__0_n_2\,
CO(0) => \add_temp_14__230_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__230_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__230_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__230_carry__0_i_4_n_0\,
O(3) => \add_temp_14__230_carry__0_n_4\,
O(2) => \add_temp_14__230_carry__0_n_5\,
O(1) => \add_temp_14__230_carry__0_n_6\,
O(0) => \add_temp_14__230_carry__0_n_7\,
S(3) => \add_temp_14__230_carry__0_i_5_n_0\,
S(2) => \add_temp_14__230_carry__0_i_6_n_0\,
S(1) => \add_temp_14__230_carry__0_i_7_n_0\,
S(0) => \add_temp_14__230_carry__0_i_8_n_0\
);
\add_temp_14__230_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(6),
I1 => \add_temp_14__0_carry__0_n_5\,
I2 => \add_temp_14__46_carry__0_n_5\,
O => \add_temp_14__230_carry__0_i_1_n_0\
);
\add_temp_14__230_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(5),
I1 => \add_temp_14__46_carry__0_n_6\,
I2 => \add_temp_14__0_carry__0_n_6\,
O => \add_temp_14__230_carry__0_i_2_n_0\
);
\add_temp_14__230_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__0_n_7\,
I1 => \add_temp_14__46_carry__0_n_7\,
I2 => RESIZE16(4),
O => \add_temp_14__230_carry__0_i_3_n_0\
);
\add_temp_14__230_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry_n_4\,
I1 => \add_temp_14__46_carry_n_4\,
I2 => RESIZE16(3),
O => \add_temp_14__230_carry__0_i_4_n_0\
);
\add_temp_14__230_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__0_n_4\,
I1 => \add_temp_14__46_carry__0_n_4\,
I2 => RESIZE16(7),
I3 => \add_temp_14__230_carry__0_i_1_n_0\,
O => \add_temp_14__230_carry__0_i_5_n_0\
);
\add_temp_14__230_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(6),
I1 => \add_temp_14__0_carry__0_n_5\,
I2 => \add_temp_14__46_carry__0_n_5\,
I3 => \add_temp_14__230_carry__0_i_2_n_0\,
O => \add_temp_14__230_carry__0_i_6_n_0\
);
\add_temp_14__230_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(5),
I1 => \add_temp_14__46_carry__0_n_6\,
I2 => \add_temp_14__0_carry__0_n_6\,
I3 => \add_temp_14__230_carry__0_i_3_n_0\,
O => \add_temp_14__230_carry__0_i_7_n_0\
);
\add_temp_14__230_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__0_n_7\,
I1 => \add_temp_14__46_carry__0_n_7\,
I2 => RESIZE16(4),
I3 => \add_temp_14__230_carry__0_i_4_n_0\,
O => \add_temp_14__230_carry__0_i_8_n_0\
);
\add_temp_14__230_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry__0_n_0\,
CO(3) => \add_temp_14__230_carry__1_n_0\,
CO(2) => \add_temp_14__230_carry__1_n_1\,
CO(1) => \add_temp_14__230_carry__1_n_2\,
CO(0) => \add_temp_14__230_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__230_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__230_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__230_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__230_carry__1_i_4_n_0\,
O(3) => \add_temp_14__230_carry__1_n_4\,
O(2) => \add_temp_14__230_carry__1_n_5\,
O(1) => \add_temp_14__230_carry__1_n_6\,
O(0) => \add_temp_14__230_carry__1_n_7\,
S(3) => \add_temp_14__230_carry__1_i_5_n_0\,
S(2) => \add_temp_14__230_carry__1_i_6_n_0\,
S(1) => \add_temp_14__230_carry__1_i_7_n_0\,
S(0) => \add_temp_14__230_carry__1_i_8_n_0\
);
\add_temp_14__230_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(10),
I1 => \add_temp_14__0_carry__1_n_5\,
I2 => \add_temp_14__46_carry__1_n_5\,
O => \add_temp_14__230_carry__1_i_1_n_0\
);
\add_temp_14__230_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__1_n_6\,
I1 => \add_temp_14__46_carry__1_n_6\,
I2 => RESIZE16(9),
O => \add_temp_14__230_carry__1_i_2_n_0\
);
\add_temp_14__230_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__1_n_7\,
I1 => RESIZE16(8),
I2 => \add_temp_14__46_carry__1_n_7\,
O => \add_temp_14__230_carry__1_i_3_n_0\
);
\add_temp_14__230_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry__0_n_4\,
I1 => \add_temp_14__46_carry__0_n_4\,
I2 => RESIZE16(7),
O => \add_temp_14__230_carry__1_i_4_n_0\
);
\add_temp_14__230_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(11),
I1 => \add_temp_14__0_carry__1_n_4\,
I2 => \add_temp_14__46_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_i_1_n_0\,
O => \add_temp_14__230_carry__1_i_5_n_0\
);
\add_temp_14__230_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(10),
I1 => \add_temp_14__0_carry__1_n_5\,
I2 => \add_temp_14__46_carry__1_n_5\,
I3 => \add_temp_14__230_carry__1_i_2_n_0\,
O => \add_temp_14__230_carry__1_i_6_n_0\
);
\add_temp_14__230_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__1_n_6\,
I1 => \add_temp_14__46_carry__1_n_6\,
I2 => RESIZE16(9),
I3 => \add_temp_14__230_carry__1_i_3_n_0\,
O => \add_temp_14__230_carry__1_i_7_n_0\
);
\add_temp_14__230_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry__1_n_7\,
I1 => RESIZE16(8),
I2 => \add_temp_14__46_carry__1_n_7\,
I3 => \add_temp_14__230_carry__1_i_4_n_0\,
O => \add_temp_14__230_carry__1_i_8_n_0\
);
\add_temp_14__230_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__230_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__230_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__230_carry__2_n_1\,
CO(1) => \add_temp_14__230_carry__2_n_2\,
CO(0) => \add_temp_14__230_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__230_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__230_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__230_carry__2_i_3_n_0\,
O(3) => \add_temp_14__230_carry__2_n_4\,
O(2) => \add_temp_14__230_carry__2_n_5\,
O(1) => \add_temp_14__230_carry__2_n_6\,
O(0) => \add_temp_14__230_carry__2_n_7\,
S(3) => \add_temp_14__230_carry__2_i_4_n_0\,
S(2) => \add_temp_14__230_carry__2_i_5_n_0\,
S(1) => \add_temp_14__230_carry__2_i_6_n_0\,
S(0) => \add_temp_14__230_carry__2_i_7_n_0\
);
\add_temp_14__230_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(13),
I1 => \add_temp_14__0_carry__2_n_6\,
I2 => \add_temp_14__46_carry__2_n_6\,
O => \add_temp_14__230_carry__2_i_1_n_0\
);
\add_temp_14__230_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(12),
I1 => \add_temp_14__0_carry__2_n_7\,
I2 => \add_temp_14__46_carry__2_n_7\,
O => \add_temp_14__230_carry__2_i_2_n_0\
);
\add_temp_14__230_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE16(11),
I1 => \add_temp_14__0_carry__1_n_4\,
I2 => \add_temp_14__46_carry__1_n_4\,
O => \add_temp_14__230_carry__2_i_3_n_0\
);
\add_temp_14__230_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => \add_temp_14__46_carry__2_n_5\,
I1 => \add_temp_14__0_carry__2_n_5\,
I2 => RESIZE16(14),
I3 => \add_temp_14__0_carry__2_n_4\,
I4 => \add_temp_14__46_carry__2_n_4\,
I5 => RESIZE16(15),
O => \add_temp_14__230_carry__2_i_4_n_0\
);
\add_temp_14__230_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__230_carry__2_i_1_n_0\,
I1 => \add_temp_14__0_carry__2_n_5\,
I2 => \add_temp_14__46_carry__2_n_5\,
I3 => RESIZE16(14),
O => \add_temp_14__230_carry__2_i_5_n_0\
);
\add_temp_14__230_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(13),
I1 => \add_temp_14__0_carry__2_n_6\,
I2 => \add_temp_14__46_carry__2_n_6\,
I3 => \add_temp_14__230_carry__2_i_2_n_0\,
O => \add_temp_14__230_carry__2_i_6_n_0\
);
\add_temp_14__230_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE16(12),
I1 => \add_temp_14__0_carry__2_n_7\,
I2 => \add_temp_14__46_carry__2_n_7\,
I3 => \add_temp_14__230_carry__2_i_3_n_0\,
O => \add_temp_14__230_carry__2_i_7_n_0\
);
\add_temp_14__230_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__46_carry_n_5\,
I1 => \add_temp_14__0_carry_n_5\,
I2 => RESIZE16(2),
O => \add_temp_14__230_carry_i_1_n_0\
);
\add_temp_14__230_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__0_carry_n_6\,
I1 => RESIZE16(1),
I2 => \add_temp_14__46_carry_n_6\,
O => \add_temp_14__230_carry_i_2_n_0\
);
\add_temp_14__230_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__46_carry_n_7\,
I1 => \add_temp_14__0_carry_n_7\,
I2 => RESIZE16(0),
O => \add_temp_14__230_carry_i_3_n_0\
);
\add_temp_14__230_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry_n_4\,
I1 => \add_temp_14__46_carry_n_4\,
I2 => RESIZE16(3),
I3 => \add_temp_14__230_carry_i_1_n_0\,
O => \add_temp_14__230_carry_i_4_n_0\
);
\add_temp_14__230_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__46_carry_n_5\,
I1 => \add_temp_14__0_carry_n_5\,
I2 => RESIZE16(2),
I3 => \add_temp_14__230_carry_i_2_n_0\,
O => \add_temp_14__230_carry_i_5_n_0\
);
\add_temp_14__230_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__0_carry_n_6\,
I1 => RESIZE16(1),
I2 => \add_temp_14__46_carry_n_6\,
I3 => \add_temp_14__230_carry_i_3_n_0\,
O => \add_temp_14__230_carry_i_6_n_0\
);
\add_temp_14__230_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__46_carry_n_7\,
I1 => \add_temp_14__0_carry_n_7\,
I2 => RESIZE16(0),
O => \add_temp_14__230_carry_i_7_n_0\
);
\add_temp_14__278_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__278_carry_n_0\,
CO(2) => \add_temp_14__278_carry_n_1\,
CO(1) => \add_temp_14__278_carry_n_2\,
CO(0) => \add_temp_14__278_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry_i_1_n_0\,
DI(2) => \add_temp_14__278_carry_i_2_n_0\,
DI(1) => \add_temp_14__278_carry_i_3_n_0\,
DI(0) => \add_temp_14__92_carry_n_7\,
O(3 downto 0) => filter_sum(3 downto 0),
S(3) => \add_temp_14__278_carry_i_4_n_0\,
S(2) => \add_temp_14__278_carry_i_5_n_0\,
S(1) => \add_temp_14__278_carry_i_6_n_0\,
S(0) => \add_temp_14__278_carry_i_7_n_0\
);
\add_temp_14__278_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry_n_0\,
CO(3) => \add_temp_14__278_carry__0_n_0\,
CO(2) => \add_temp_14__278_carry__0_n_1\,
CO(1) => \add_temp_14__278_carry__0_n_2\,
CO(0) => \add_temp_14__278_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__278_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__278_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__278_carry__0_i_4_n_0\,
O(3 downto 0) => filter_sum(7 downto 4),
S(3) => \add_temp_14__278_carry__0_i_5_n_0\,
S(2) => \add_temp_14__278_carry__0_i_6_n_0\,
S(1) => \add_temp_14__278_carry__0_i_7_n_0\,
S(0) => \add_temp_14__278_carry__0_i_8_n_0\
);
\add_temp_14__278_carry__0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_5\,
I1 => \add_temp_14__230_carry__0_n_5\,
I2 => \add_temp_14__184_carry__0_n_5\,
I3 => \add_temp_14__278_carry__0_i_9_n_0\,
I4 => \add_temp_14__92_carry__0_n_5\,
O => \add_temp_14__278_carry__0_i_1_n_0\
);
\add_temp_14__278_carry__0_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__230_carry__0_n_7\,
I1 => \add_temp_14__184_carry__0_n_7\,
I2 => \add_temp_14__138_carry__0_n_7\,
O => \add_temp_14__278_carry__0_i_10_n_0\
);
\add_temp_14__278_carry__0_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__230_carry_n_4\,
I1 => \add_temp_14__184_carry_n_4\,
I2 => \add_temp_14__138_carry_n_4\,
O => \add_temp_14__278_carry__0_i_11_n_0\
);
\add_temp_14__278_carry__0_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__0_n_4\,
I1 => \add_temp_14__230_carry__0_n_4\,
I2 => \add_temp_14__184_carry__0_n_4\,
O => \add_temp_14__278_carry__0_i_12_n_0\
);
\add_temp_14__278_carry__0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_6\,
I1 => \add_temp_14__230_carry__0_n_6\,
I2 => \add_temp_14__184_carry__0_n_6\,
I3 => \add_temp_14__278_carry__0_i_10_n_0\,
I4 => \add_temp_14__92_carry__0_n_6\,
O => \add_temp_14__278_carry__0_i_2_n_0\
);
\add_temp_14__278_carry__0_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__0_n_7\,
I1 => \add_temp_14__230_carry__0_n_7\,
I2 => \add_temp_14__184_carry__0_n_7\,
I3 => \add_temp_14__278_carry__0_i_11_n_0\,
I4 => \add_temp_14__92_carry__0_n_7\,
O => \add_temp_14__278_carry__0_i_3_n_0\
);
\add_temp_14__278_carry__0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry_n_4\,
I1 => \add_temp_14__230_carry_n_4\,
I2 => \add_temp_14__184_carry_n_4\,
I3 => \add_temp_14__278_carry_i_9_n_0\,
I4 => \add_temp_14__92_carry_n_4\,
O => \add_temp_14__278_carry__0_i_4_n_0\
);
\add_temp_14__278_carry__0_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__0_i_1_n_0\,
I1 => \add_temp_14__278_carry__0_i_12_n_0\,
I2 => \add_temp_14__92_carry__0_n_4\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__184_carry__0_n_5\,
I5 => \add_temp_14__230_carry__0_n_5\,
O => \add_temp_14__278_carry__0_i_5_n_0\
);
\add_temp_14__278_carry__0_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_2_n_0\,
I1 => \add_temp_14__184_carry__0_n_5\,
I2 => \add_temp_14__230_carry__0_n_5\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__92_carry__0_n_5\,
I5 => \add_temp_14__278_carry__0_i_9_n_0\,
O => \add_temp_14__278_carry__0_i_6_n_0\
);
\add_temp_14__278_carry__0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_3_n_0\,
I1 => \add_temp_14__184_carry__0_n_6\,
I2 => \add_temp_14__230_carry__0_n_6\,
I3 => \add_temp_14__138_carry__0_n_6\,
I4 => \add_temp_14__92_carry__0_n_6\,
I5 => \add_temp_14__278_carry__0_i_10_n_0\,
O => \add_temp_14__278_carry__0_i_7_n_0\
);
\add_temp_14__278_carry__0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__0_i_4_n_0\,
I1 => \add_temp_14__184_carry__0_n_7\,
I2 => \add_temp_14__230_carry__0_n_7\,
I3 => \add_temp_14__138_carry__0_n_7\,
I4 => \add_temp_14__92_carry__0_n_7\,
I5 => \add_temp_14__278_carry__0_i_11_n_0\,
O => \add_temp_14__278_carry__0_i_8_n_0\
);
\add_temp_14__278_carry__0_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__138_carry__0_n_6\,
I1 => \add_temp_14__184_carry__0_n_6\,
I2 => \add_temp_14__230_carry__0_n_6\,
O => \add_temp_14__278_carry__0_i_9_n_0\
);
\add_temp_14__278_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry__0_n_0\,
CO(3) => \add_temp_14__278_carry__1_n_0\,
CO(2) => \add_temp_14__278_carry__1_n_1\,
CO(1) => \add_temp_14__278_carry__1_n_2\,
CO(0) => \add_temp_14__278_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__278_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__278_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__278_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__278_carry__1_i_4_n_0\,
O(3 downto 0) => filter_sum(11 downto 8),
S(3) => \add_temp_14__278_carry__1_i_5_n_0\,
S(2) => \add_temp_14__278_carry__1_i_6_n_0\,
S(1) => \add_temp_14__278_carry__1_i_7_n_0\,
S(0) => \add_temp_14__278_carry__1_i_8_n_0\
);
\add_temp_14__278_carry__1_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__1_n_5\,
I1 => \add_temp_14__230_carry__1_n_5\,
I2 => \add_temp_14__184_carry__1_n_5\,
I3 => \add_temp_14__278_carry__1_i_9_n_0\,
I4 => \add_temp_14__92_carry__1_n_5\,
O => \add_temp_14__278_carry__1_i_1_n_0\
);
\add_temp_14__278_carry__1_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__1_n_7\,
I1 => \add_temp_14__138_carry__1_n_7\,
I2 => \add_temp_14__230_carry__1_n_7\,
O => \add_temp_14__278_carry__1_i_10_n_0\
);
\add_temp_14__278_carry__1_i_11\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__1_n_7\,
I1 => \add_temp_14__230_carry__1_n_7\,
I2 => \add_temp_14__184_carry__1_n_7\,
O => \add_temp_14__278_carry__1_i_11_n_0\
);
\add_temp_14__278_carry__1_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__1_n_4\,
I1 => \add_temp_14__230_carry__1_n_4\,
I2 => \add_temp_14__184_carry__1_n_4\,
O => \add_temp_14__278_carry__1_i_12_n_0\
);
\add_temp_14__278_carry__1_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__1_n_6\,
I1 => \add_temp_14__230_carry__1_n_6\,
I2 => \add_temp_14__184_carry__1_n_6\,
I3 => \add_temp_14__278_carry__1_i_10_n_0\,
I4 => \add_temp_14__92_carry__1_n_6\,
O => \add_temp_14__278_carry__1_i_2_n_0\
);
\add_temp_14__278_carry__1_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__1_n_7\,
I1 => \add_temp_14__138_carry__0_n_4\,
I2 => \add_temp_14__184_carry__0_n_4\,
I3 => \add_temp_14__230_carry__0_n_4\,
I4 => \add_temp_14__278_carry__1_i_11_n_0\,
O => \add_temp_14__278_carry__1_i_3_n_0\
);
\add_temp_14__278_carry__1_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__0_n_4\,
I1 => \add_temp_14__230_carry__0_n_5\,
I2 => \add_temp_14__184_carry__0_n_5\,
I3 => \add_temp_14__138_carry__0_n_5\,
I4 => \add_temp_14__278_carry__0_i_12_n_0\,
O => \add_temp_14__278_carry__1_i_4_n_0\
);
\add_temp_14__278_carry__1_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__1_i_1_n_0\,
I1 => \add_temp_14__278_carry__1_i_12_n_0\,
I2 => \add_temp_14__92_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_n_5\,
I4 => \add_temp_14__184_carry__1_n_5\,
I5 => \add_temp_14__138_carry__1_n_5\,
O => \add_temp_14__278_carry__1_i_5_n_0\
);
\add_temp_14__278_carry__1_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__1_i_2_n_0\,
I1 => \add_temp_14__184_carry__1_n_5\,
I2 => \add_temp_14__230_carry__1_n_5\,
I3 => \add_temp_14__138_carry__1_n_5\,
I4 => \add_temp_14__92_carry__1_n_5\,
I5 => \add_temp_14__278_carry__1_i_9_n_0\,
O => \add_temp_14__278_carry__1_i_6_n_0\
);
\add_temp_14__278_carry__1_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__1_i_3_n_0\,
I1 => \add_temp_14__184_carry__1_n_6\,
I2 => \add_temp_14__230_carry__1_n_6\,
I3 => \add_temp_14__138_carry__1_n_6\,
I4 => \add_temp_14__92_carry__1_n_6\,
I5 => \add_temp_14__278_carry__1_i_10_n_0\,
O => \add_temp_14__278_carry__1_i_7_n_0\
);
\add_temp_14__278_carry__1_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__1_i_4_n_0\,
I1 => \add_temp_14__278_carry__1_i_11_n_0\,
I2 => \add_temp_14__92_carry__1_n_7\,
I3 => \add_temp_14__230_carry__0_n_4\,
I4 => \add_temp_14__184_carry__0_n_4\,
I5 => \add_temp_14__138_carry__0_n_4\,
O => \add_temp_14__278_carry__1_i_8_n_0\
);
\add_temp_14__278_carry__1_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__1_n_6\,
I1 => \add_temp_14__230_carry__1_n_6\,
I2 => \add_temp_14__138_carry__1_n_6\,
O => \add_temp_14__278_carry__1_i_9_n_0\
);
\add_temp_14__278_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__278_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__278_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__278_carry__2_n_1\,
CO(1) => \add_temp_14__278_carry__2_n_2\,
CO(0) => \add_temp_14__278_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__278_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__278_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__278_carry__2_i_3_n_0\,
O(3 downto 0) => filter_sum(15 downto 12),
S(3) => \add_temp_14__278_carry__2_i_4_n_0\,
S(2) => \add_temp_14__278_carry__2_i_5_n_0\,
S(1) => \add_temp_14__278_carry__2_i_6_n_0\,
S(0) => \add_temp_14__278_carry__2_i_7_n_0\
);
\add_temp_14__278_carry__2_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry__2_n_6\,
I1 => \add_temp_14__230_carry__2_n_6\,
I2 => \add_temp_14__184_carry__2_n_6\,
I3 => \add_temp_14__278_carry__2_i_8_n_0\,
I4 => \add_temp_14__92_carry__2_n_6\,
O => \add_temp_14__278_carry__2_i_1_n_0\
);
\add_temp_14__278_carry__2_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__2_n_6\,
I1 => \add_temp_14__230_carry__2_n_6\,
I2 => \add_temp_14__138_carry__2_n_6\,
O => \add_temp_14__278_carry__2_i_10_n_0\
);
\add_temp_14__278_carry__2_i_11\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry__2_n_4\,
I1 => \add_temp_14__230_carry__2_n_4\,
I2 => \add_temp_14__138_carry__2_n_4\,
I3 => \add_temp_14__92_carry__2_n_4\,
O => \add_temp_14__278_carry__2_i_11_n_0\
);
\add_temp_14__278_carry__2_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__2_n_7\,
I1 => \add_temp_14__138_carry__1_n_4\,
I2 => \add_temp_14__184_carry__1_n_4\,
I3 => \add_temp_14__230_carry__1_n_4\,
I4 => \add_temp_14__278_carry__2_i_9_n_0\,
O => \add_temp_14__278_carry__2_i_2_n_0\
);
\add_temp_14__278_carry__2_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FEEAA880"
)
port map (
I0 => \add_temp_14__92_carry__1_n_4\,
I1 => \add_temp_14__138_carry__1_n_5\,
I2 => \add_temp_14__184_carry__1_n_5\,
I3 => \add_temp_14__230_carry__1_n_5\,
I4 => \add_temp_14__278_carry__1_i_12_n_0\,
O => \add_temp_14__278_carry__2_i_3_n_0\
);
\add_temp_14__278_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"E187871E871E1E78"
)
port map (
I0 => \add_temp_14__92_carry__2_n_5\,
I1 => \add_temp_14__278_carry__2_i_10_n_0\,
I2 => \add_temp_14__278_carry__2_i_11_n_0\,
I3 => \add_temp_14__138_carry__2_n_5\,
I4 => \add_temp_14__184_carry__2_n_5\,
I5 => \add_temp_14__230_carry__2_n_5\,
O => \add_temp_14__278_carry__2_i_4_n_0\
);
\add_temp_14__278_carry__2_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__2_i_1_n_0\,
I1 => \add_temp_14__184_carry__2_n_5\,
I2 => \add_temp_14__230_carry__2_n_5\,
I3 => \add_temp_14__138_carry__2_n_5\,
I4 => \add_temp_14__92_carry__2_n_5\,
I5 => \add_temp_14__278_carry__2_i_10_n_0\,
O => \add_temp_14__278_carry__2_i_5_n_0\
);
\add_temp_14__278_carry__2_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry__2_i_2_n_0\,
I1 => \add_temp_14__184_carry__2_n_6\,
I2 => \add_temp_14__230_carry__2_n_6\,
I3 => \add_temp_14__138_carry__2_n_6\,
I4 => \add_temp_14__92_carry__2_n_6\,
I5 => \add_temp_14__278_carry__2_i_8_n_0\,
O => \add_temp_14__278_carry__2_i_6_n_0\
);
\add_temp_14__278_carry__2_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"6969699669969696"
)
port map (
I0 => \add_temp_14__278_carry__2_i_3_n_0\,
I1 => \add_temp_14__278_carry__2_i_9_n_0\,
I2 => \add_temp_14__92_carry__2_n_7\,
I3 => \add_temp_14__230_carry__1_n_4\,
I4 => \add_temp_14__184_carry__1_n_4\,
I5 => \add_temp_14__138_carry__1_n_4\,
O => \add_temp_14__278_carry__2_i_7_n_0\
);
\add_temp_14__278_carry__2_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry__2_n_7\,
I1 => \add_temp_14__138_carry__2_n_7\,
I2 => \add_temp_14__230_carry__2_n_7\,
O => \add_temp_14__278_carry__2_i_8_n_0\
);
\add_temp_14__278_carry__2_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry__2_n_7\,
I1 => \add_temp_14__230_carry__2_n_7\,
I2 => \add_temp_14__184_carry__2_n_7\,
O => \add_temp_14__278_carry__2_i_9_n_0\
);
\add_temp_14__278_carry_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF969600"
)
port map (
I0 => \add_temp_14__138_carry_n_5\,
I1 => \add_temp_14__230_carry_n_5\,
I2 => \add_temp_14__184_carry_n_5\,
I3 => \add_temp_14__278_carry_i_8_n_0\,
I4 => \add_temp_14__92_carry_n_5\,
O => \add_temp_14__278_carry_i_1_n_0\
);
\add_temp_14__278_carry_i_10\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \add_temp_14__138_carry_n_5\,
I1 => \add_temp_14__230_carry_n_5\,
I2 => \add_temp_14__184_carry_n_5\,
O => \add_temp_14__278_carry_i_10_n_0\
);
\add_temp_14__278_carry_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"96696996"
)
port map (
I0 => \add_temp_14__278_carry_i_8_n_0\,
I1 => \add_temp_14__92_carry_n_5\,
I2 => \add_temp_14__138_carry_n_5\,
I3 => \add_temp_14__230_carry_n_5\,
I4 => \add_temp_14__184_carry_n_5\,
O => \add_temp_14__278_carry_i_2_n_0\
);
\add_temp_14__278_carry_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry_n_6\,
I1 => \add_temp_14__230_carry_n_6\,
I2 => \add_temp_14__138_carry_n_6\,
I3 => \add_temp_14__92_carry_n_6\,
O => \add_temp_14__278_carry_i_3_n_0\
);
\add_temp_14__278_carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6996966996696996"
)
port map (
I0 => \add_temp_14__278_carry_i_1_n_0\,
I1 => \add_temp_14__184_carry_n_4\,
I2 => \add_temp_14__230_carry_n_4\,
I3 => \add_temp_14__138_carry_n_4\,
I4 => \add_temp_14__92_carry_n_4\,
I5 => \add_temp_14__278_carry_i_9_n_0\,
O => \add_temp_14__278_carry_i_4_n_0\
);
\add_temp_14__278_carry_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"6999999699969666"
)
port map (
I0 => \add_temp_14__278_carry_i_10_n_0\,
I1 => \add_temp_14__92_carry_n_5\,
I2 => \add_temp_14__138_carry_n_6\,
I3 => \add_temp_14__230_carry_n_6\,
I4 => \add_temp_14__184_carry_n_6\,
I5 => \add_temp_14__92_carry_n_6\,
O => \add_temp_14__278_carry_i_5_n_0\
);
\add_temp_14__278_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"566A"
)
port map (
I0 => \add_temp_14__278_carry_i_3_n_0\,
I1 => \add_temp_14__230_carry_n_7\,
I2 => \add_temp_14__184_carry_n_7\,
I3 => \add_temp_14__138_carry_n_7\,
O => \add_temp_14__278_carry_i_6_n_0\
);
\add_temp_14__278_carry_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__184_carry_n_7\,
I1 => \add_temp_14__230_carry_n_7\,
I2 => \add_temp_14__138_carry_n_7\,
I3 => \add_temp_14__92_carry_n_7\,
O => \add_temp_14__278_carry_i_7_n_0\
);
\add_temp_14__278_carry_i_8\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__138_carry_n_6\,
I1 => \add_temp_14__230_carry_n_6\,
I2 => \add_temp_14__184_carry_n_6\,
O => \add_temp_14__278_carry_i_8_n_0\
);
\add_temp_14__278_carry_i_9\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => \add_temp_14__184_carry_n_5\,
I1 => \add_temp_14__138_carry_n_5\,
I2 => \add_temp_14__230_carry_n_5\,
O => \add_temp_14__278_carry_i_9_n_0\
);
\add_temp_14__46_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__46_carry_n_0\,
CO(2) => \add_temp_14__46_carry_n_1\,
CO(1) => \add_temp_14__46_carry_n_2\,
CO(0) => \add_temp_14__46_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry_i_1_n_0\,
DI(2) => \add_temp_14__46_carry_i_2_n_0\,
DI(1) => \add_temp_14__46_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__46_carry_n_4\,
O(2) => \add_temp_14__46_carry_n_5\,
O(1) => \add_temp_14__46_carry_n_6\,
O(0) => \add_temp_14__46_carry_n_7\,
S(3) => \add_temp_14__46_carry_i_4_n_0\,
S(2) => \add_temp_14__46_carry_i_5_n_0\,
S(1) => \add_temp_14__46_carry_i_6_n_0\,
S(0) => \add_temp_14__46_carry_i_7_n_0\
);
\add_temp_14__46_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry_n_0\,
CO(3) => \add_temp_14__46_carry__0_n_0\,
CO(2) => \add_temp_14__46_carry__0_n_1\,
CO(1) => \add_temp_14__46_carry__0_n_2\,
CO(0) => \add_temp_14__46_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__46_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__46_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__46_carry__0_i_4_n_0\,
O(3) => \add_temp_14__46_carry__0_n_4\,
O(2) => \add_temp_14__46_carry__0_n_5\,
O(1) => \add_temp_14__46_carry__0_n_6\,
O(0) => \add_temp_14__46_carry__0_n_7\,
S(3) => \add_temp_14__46_carry__0_i_5_n_0\,
S(2) => \add_temp_14__46_carry__0_i_6_n_0\,
S(1) => \add_temp_14__46_carry__0_i_7_n_0\,
S(0) => \add_temp_14__46_carry__0_i_8_n_0\
);
\add_temp_14__46_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(6),
I1 => RESIZE40(6),
I2 => RESIZE36(6),
O => \add_temp_14__46_carry__0_i_1_n_0\
);
\add_temp_14__46_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(5),
I1 => RESIZE40(5),
I2 => RESIZE36(5),
O => \add_temp_14__46_carry__0_i_2_n_0\
);
\add_temp_14__46_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(4),
I1 => RESIZE40(4),
I2 => RESIZE36(4),
O => \add_temp_14__46_carry__0_i_3_n_0\
);
\add_temp_14__46_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(3),
I1 => RESIZE40(3),
I2 => RESIZE36(3),
O => \add_temp_14__46_carry__0_i_4_n_0\
);
\add_temp_14__46_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(7),
I1 => RESIZE40(7),
I2 => RESIZE36(7),
I3 => \add_temp_14__46_carry__0_i_1_n_0\,
O => \add_temp_14__46_carry__0_i_5_n_0\
);
\add_temp_14__46_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(6),
I1 => RESIZE40(6),
I2 => RESIZE36(6),
I3 => \add_temp_14__46_carry__0_i_2_n_0\,
O => \add_temp_14__46_carry__0_i_6_n_0\
);
\add_temp_14__46_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(5),
I1 => RESIZE40(5),
I2 => RESIZE36(5),
I3 => \add_temp_14__46_carry__0_i_3_n_0\,
O => \add_temp_14__46_carry__0_i_7_n_0\
);
\add_temp_14__46_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(4),
I1 => RESIZE40(4),
I2 => RESIZE36(4),
I3 => \add_temp_14__46_carry__0_i_4_n_0\,
O => \add_temp_14__46_carry__0_i_8_n_0\
);
\add_temp_14__46_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry__0_n_0\,
CO(3) => \add_temp_14__46_carry__1_n_0\,
CO(2) => \add_temp_14__46_carry__1_n_1\,
CO(1) => \add_temp_14__46_carry__1_n_2\,
CO(0) => \add_temp_14__46_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__46_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__46_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__46_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__46_carry__1_i_4_n_0\,
O(3) => \add_temp_14__46_carry__1_n_4\,
O(2) => \add_temp_14__46_carry__1_n_5\,
O(1) => \add_temp_14__46_carry__1_n_6\,
O(0) => \add_temp_14__46_carry__1_n_7\,
S(3) => \add_temp_14__46_carry__1_i_5_n_0\,
S(2) => \add_temp_14__46_carry__1_i_6_n_0\,
S(1) => \add_temp_14__46_carry__1_i_7_n_0\,
S(0) => \add_temp_14__46_carry__1_i_8_n_0\
);
\add_temp_14__46_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE40(10),
I1 => RESIZE36(10),
I2 => RESIZE38(10),
O => \add_temp_14__46_carry__1_i_1_n_0\
);
\add_temp_14__46_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(9),
I1 => RESIZE40(9),
I2 => RESIZE36(9),
O => \add_temp_14__46_carry__1_i_2_n_0\
);
\add_temp_14__46_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(8),
I1 => RESIZE40(8),
I2 => RESIZE36(8),
O => \add_temp_14__46_carry__1_i_3_n_0\
);
\add_temp_14__46_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(7),
I1 => RESIZE40(7),
I2 => RESIZE36(7),
O => \add_temp_14__46_carry__1_i_4_n_0\
);
\add_temp_14__46_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(11),
I1 => RESIZE38(11),
I2 => RESIZE40(11),
I3 => \add_temp_14__46_carry__1_i_1_n_0\,
O => \add_temp_14__46_carry__1_i_5_n_0\
);
\add_temp_14__46_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE40(10),
I1 => RESIZE36(10),
I2 => RESIZE38(10),
I3 => \add_temp_14__46_carry__1_i_2_n_0\,
O => \add_temp_14__46_carry__1_i_6_n_0\
);
\add_temp_14__46_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(9),
I1 => RESIZE40(9),
I2 => RESIZE36(9),
I3 => \add_temp_14__46_carry__1_i_3_n_0\,
O => \add_temp_14__46_carry__1_i_7_n_0\
);
\add_temp_14__46_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(8),
I1 => RESIZE40(8),
I2 => RESIZE36(8),
I3 => \add_temp_14__46_carry__1_i_4_n_0\,
O => \add_temp_14__46_carry__1_i_8_n_0\
);
\add_temp_14__46_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__46_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__46_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__46_carry__2_n_1\,
CO(1) => \add_temp_14__46_carry__2_n_2\,
CO(0) => \add_temp_14__46_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__46_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__46_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__46_carry__2_i_3_n_0\,
O(3) => \add_temp_14__46_carry__2_n_4\,
O(2) => \add_temp_14__46_carry__2_n_5\,
O(1) => \add_temp_14__46_carry__2_n_6\,
O(0) => \add_temp_14__46_carry__2_n_7\,
S(3) => \add_temp_14__46_carry__2_i_4_n_0\,
S(2) => \add_temp_14__46_carry__2_i_5_n_0\,
S(1) => \add_temp_14__46_carry__2_i_6_n_0\,
S(0) => \add_temp_14__46_carry__2_i_7_n_0\
);
\add_temp_14__46_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(13),
I1 => RESIZE38(13),
I2 => RESIZE40(13),
O => \add_temp_14__46_carry__2_i_1_n_0\
);
\add_temp_14__46_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(12),
I1 => RESIZE38(12),
I2 => RESIZE40(12),
O => \add_temp_14__46_carry__2_i_2_n_0\
);
\add_temp_14__46_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE36(11),
I1 => RESIZE38(11),
I2 => RESIZE40(11),
O => \add_temp_14__46_carry__2_i_3_n_0\
);
\add_temp_14__46_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE40(14),
I1 => RESIZE38(14),
I2 => RESIZE36(14),
I3 => RESIZE38(15),
I4 => RESIZE36(15),
I5 => RESIZE40(15),
O => \add_temp_14__46_carry__2_i_4_n_0\
);
\add_temp_14__46_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__46_carry__2_i_1_n_0\,
I1 => RESIZE38(14),
I2 => RESIZE36(14),
I3 => RESIZE40(14),
O => \add_temp_14__46_carry__2_i_5_n_0\
);
\add_temp_14__46_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(13),
I1 => RESIZE38(13),
I2 => RESIZE40(13),
I3 => \add_temp_14__46_carry__2_i_2_n_0\,
O => \add_temp_14__46_carry__2_i_6_n_0\
);
\add_temp_14__46_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE36(12),
I1 => RESIZE38(12),
I2 => RESIZE40(12),
I3 => \add_temp_14__46_carry__2_i_3_n_0\,
O => \add_temp_14__46_carry__2_i_7_n_0\
);
\add_temp_14__46_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(2),
I1 => RESIZE40(2),
I2 => RESIZE36(2),
O => \add_temp_14__46_carry_i_1_n_0\
);
\add_temp_14__46_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(1),
I1 => RESIZE40(1),
I2 => RESIZE36(1),
O => \add_temp_14__46_carry_i_2_n_0\
);
\add_temp_14__46_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE38(0),
I1 => RESIZE40(0),
I2 => RESIZE36(0),
O => \add_temp_14__46_carry_i_3_n_0\
);
\add_temp_14__46_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(3),
I1 => RESIZE40(3),
I2 => RESIZE36(3),
I3 => \add_temp_14__46_carry_i_1_n_0\,
O => \add_temp_14__46_carry_i_4_n_0\
);
\add_temp_14__46_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(2),
I1 => RESIZE40(2),
I2 => RESIZE36(2),
I3 => \add_temp_14__46_carry_i_2_n_0\,
O => \add_temp_14__46_carry_i_5_n_0\
);
\add_temp_14__46_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE38(1),
I1 => RESIZE40(1),
I2 => RESIZE36(1),
I3 => \add_temp_14__46_carry_i_3_n_0\,
O => \add_temp_14__46_carry_i_6_n_0\
);
\add_temp_14__46_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE38(0),
I1 => RESIZE40(0),
I2 => RESIZE36(0),
O => \add_temp_14__46_carry_i_7_n_0\
);
\add_temp_14__92_carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \add_temp_14__92_carry_n_0\,
CO(2) => \add_temp_14__92_carry_n_1\,
CO(1) => \add_temp_14__92_carry_n_2\,
CO(0) => \add_temp_14__92_carry_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry_i_1_n_0\,
DI(2) => \add_temp_14__92_carry_i_2_n_0\,
DI(1) => \add_temp_14__92_carry_i_3_n_0\,
DI(0) => '0',
O(3) => \add_temp_14__92_carry_n_4\,
O(2) => \add_temp_14__92_carry_n_5\,
O(1) => \add_temp_14__92_carry_n_6\,
O(0) => \add_temp_14__92_carry_n_7\,
S(3) => \add_temp_14__92_carry_i_4_n_0\,
S(2) => \add_temp_14__92_carry_i_5_n_0\,
S(1) => \add_temp_14__92_carry_i_6_n_0\,
S(0) => \add_temp_14__92_carry_i_7_n_0\
);
\add_temp_14__92_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry_n_0\,
CO(3) => \add_temp_14__92_carry__0_n_0\,
CO(2) => \add_temp_14__92_carry__0_n_1\,
CO(1) => \add_temp_14__92_carry__0_n_2\,
CO(0) => \add_temp_14__92_carry__0_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry__0_i_1_n_0\,
DI(2) => \add_temp_14__92_carry__0_i_2_n_0\,
DI(1) => \add_temp_14__92_carry__0_i_3_n_0\,
DI(0) => \add_temp_14__92_carry__0_i_4_n_0\,
O(3) => \add_temp_14__92_carry__0_n_4\,
O(2) => \add_temp_14__92_carry__0_n_5\,
O(1) => \add_temp_14__92_carry__0_n_6\,
O(0) => \add_temp_14__92_carry__0_n_7\,
S(3) => \add_temp_14__92_carry__0_i_5_n_0\,
S(2) => \add_temp_14__92_carry__0_i_6_n_0\,
S(1) => \add_temp_14__92_carry__0_i_7_n_0\,
S(0) => \add_temp_14__92_carry__0_i_8_n_0\
);
\add_temp_14__92_carry__0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(6),
I1 => RESIZE34(6),
I2 => RESIZE30(6),
O => \add_temp_14__92_carry__0_i_1_n_0\
);
\add_temp_14__92_carry__0_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(5),
I1 => RESIZE34(5),
I2 => RESIZE30(5),
O => \add_temp_14__92_carry__0_i_2_n_0\
);
\add_temp_14__92_carry__0_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(4),
I1 => RESIZE34(4),
I2 => RESIZE30(4),
O => \add_temp_14__92_carry__0_i_3_n_0\
);
\add_temp_14__92_carry__0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(3),
I1 => RESIZE34(3),
I2 => RESIZE30(3),
O => \add_temp_14__92_carry__0_i_4_n_0\
);
\add_temp_14__92_carry__0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE34(7),
I1 => RESIZE30(7),
I2 => RESIZE32(7),
I3 => \add_temp_14__92_carry__0_i_1_n_0\,
O => \add_temp_14__92_carry__0_i_5_n_0\
);
\add_temp_14__92_carry__0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(6),
I1 => RESIZE34(6),
I2 => RESIZE30(6),
I3 => \add_temp_14__92_carry__0_i_2_n_0\,
O => \add_temp_14__92_carry__0_i_6_n_0\
);
\add_temp_14__92_carry__0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(5),
I1 => RESIZE34(5),
I2 => RESIZE30(5),
I3 => \add_temp_14__92_carry__0_i_3_n_0\,
O => \add_temp_14__92_carry__0_i_7_n_0\
);
\add_temp_14__92_carry__0_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(4),
I1 => RESIZE34(4),
I2 => RESIZE30(4),
I3 => \add_temp_14__92_carry__0_i_4_n_0\,
O => \add_temp_14__92_carry__0_i_8_n_0\
);
\add_temp_14__92_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry__0_n_0\,
CO(3) => \add_temp_14__92_carry__1_n_0\,
CO(2) => \add_temp_14__92_carry__1_n_1\,
CO(1) => \add_temp_14__92_carry__1_n_2\,
CO(0) => \add_temp_14__92_carry__1_n_3\,
CYINIT => '0',
DI(3) => \add_temp_14__92_carry__1_i_1_n_0\,
DI(2) => \add_temp_14__92_carry__1_i_2_n_0\,
DI(1) => \add_temp_14__92_carry__1_i_3_n_0\,
DI(0) => \add_temp_14__92_carry__1_i_4_n_0\,
O(3) => \add_temp_14__92_carry__1_n_4\,
O(2) => \add_temp_14__92_carry__1_n_5\,
O(1) => \add_temp_14__92_carry__1_n_6\,
O(0) => \add_temp_14__92_carry__1_n_7\,
S(3) => \add_temp_14__92_carry__1_i_5_n_0\,
S(2) => \add_temp_14__92_carry__1_i_6_n_0\,
S(1) => \add_temp_14__92_carry__1_i_7_n_0\,
S(0) => \add_temp_14__92_carry__1_i_8_n_0\
);
\add_temp_14__92_carry__1_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(10),
I1 => RESIZE32(10),
I2 => RESIZE34(10),
O => \add_temp_14__92_carry__1_i_1_n_0\
);
\add_temp_14__92_carry__1_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(9),
I1 => RESIZE32(9),
I2 => RESIZE34(9),
O => \add_temp_14__92_carry__1_i_2_n_0\
);
\add_temp_14__92_carry__1_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(8),
I1 => RESIZE32(8),
I2 => RESIZE34(8),
O => \add_temp_14__92_carry__1_i_3_n_0\
);
\add_temp_14__92_carry__1_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE34(7),
I1 => RESIZE30(7),
I2 => RESIZE32(7),
O => \add_temp_14__92_carry__1_i_4_n_0\
);
\add_temp_14__92_carry__1_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(11),
I1 => RESIZE32(11),
I2 => RESIZE34(11),
I3 => \add_temp_14__92_carry__1_i_1_n_0\,
O => \add_temp_14__92_carry__1_i_5_n_0\
);
\add_temp_14__92_carry__1_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(10),
I1 => RESIZE32(10),
I2 => RESIZE34(10),
I3 => \add_temp_14__92_carry__1_i_2_n_0\,
O => \add_temp_14__92_carry__1_i_6_n_0\
);
\add_temp_14__92_carry__1_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(9),
I1 => RESIZE32(9),
I2 => RESIZE34(9),
I3 => \add_temp_14__92_carry__1_i_3_n_0\,
O => \add_temp_14__92_carry__1_i_7_n_0\
);
\add_temp_14__92_carry__1_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(8),
I1 => RESIZE32(8),
I2 => RESIZE34(8),
I3 => \add_temp_14__92_carry__1_i_4_n_0\,
O => \add_temp_14__92_carry__1_i_8_n_0\
);
\add_temp_14__92_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \add_temp_14__92_carry__1_n_0\,
CO(3) => \NLW_add_temp_14__92_carry__2_CO_UNCONNECTED\(3),
CO(2) => \add_temp_14__92_carry__2_n_1\,
CO(1) => \add_temp_14__92_carry__2_n_2\,
CO(0) => \add_temp_14__92_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \add_temp_14__92_carry__2_i_1_n_0\,
DI(1) => \add_temp_14__92_carry__2_i_2_n_0\,
DI(0) => \add_temp_14__92_carry__2_i_3_n_0\,
O(3) => \add_temp_14__92_carry__2_n_4\,
O(2) => \add_temp_14__92_carry__2_n_5\,
O(1) => \add_temp_14__92_carry__2_n_6\,
O(0) => \add_temp_14__92_carry__2_n_7\,
S(3) => \add_temp_14__92_carry__2_i_4_n_0\,
S(2) => \add_temp_14__92_carry__2_i_5_n_0\,
S(1) => \add_temp_14__92_carry__2_i_6_n_0\,
S(0) => \add_temp_14__92_carry__2_i_7_n_0\
);
\add_temp_14__92_carry__2_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(13),
I1 => RESIZE32(13),
I2 => RESIZE34(13),
O => \add_temp_14__92_carry__2_i_1_n_0\
);
\add_temp_14__92_carry__2_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(12),
I1 => RESIZE32(12),
I2 => RESIZE34(12),
O => \add_temp_14__92_carry__2_i_2_n_0\
);
\add_temp_14__92_carry__2_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE30(11),
I1 => RESIZE32(11),
I2 => RESIZE34(11),
O => \add_temp_14__92_carry__2_i_3_n_0\
);
\add_temp_14__92_carry__2_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"17E8E817E81717E8"
)
port map (
I0 => RESIZE34(14),
I1 => RESIZE32(14),
I2 => RESIZE30(14),
I3 => RESIZE32(15),
I4 => RESIZE30(15),
I5 => RESIZE34(15),
O => \add_temp_14__92_carry__2_i_4_n_0\
);
\add_temp_14__92_carry__2_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \add_temp_14__92_carry__2_i_1_n_0\,
I1 => RESIZE32(14),
I2 => RESIZE30(14),
I3 => RESIZE34(14),
O => \add_temp_14__92_carry__2_i_5_n_0\
);
\add_temp_14__92_carry__2_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(13),
I1 => RESIZE32(13),
I2 => RESIZE34(13),
I3 => \add_temp_14__92_carry__2_i_2_n_0\,
O => \add_temp_14__92_carry__2_i_6_n_0\
);
\add_temp_14__92_carry__2_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE30(12),
I1 => RESIZE32(12),
I2 => RESIZE34(12),
I3 => \add_temp_14__92_carry__2_i_3_n_0\,
O => \add_temp_14__92_carry__2_i_7_n_0\
);
\add_temp_14__92_carry_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(2),
I1 => RESIZE34(2),
I2 => RESIZE30(2),
O => \add_temp_14__92_carry_i_1_n_0\
);
\add_temp_14__92_carry_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(1),
I1 => RESIZE34(1),
I2 => RESIZE30(1),
O => \add_temp_14__92_carry_i_2_n_0\
);
\add_temp_14__92_carry_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"E8"
)
port map (
I0 => RESIZE32(0),
I1 => RESIZE34(0),
I2 => RESIZE30(0),
O => \add_temp_14__92_carry_i_3_n_0\
);
\add_temp_14__92_carry_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(3),
I1 => RESIZE34(3),
I2 => RESIZE30(3),
I3 => \add_temp_14__92_carry_i_1_n_0\,
O => \add_temp_14__92_carry_i_4_n_0\
);
\add_temp_14__92_carry_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(2),
I1 => RESIZE34(2),
I2 => RESIZE30(2),
I3 => \add_temp_14__92_carry_i_2_n_0\,
O => \add_temp_14__92_carry_i_5_n_0\
);
\add_temp_14__92_carry_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => RESIZE32(1),
I1 => RESIZE34(1),
I2 => RESIZE30(1),
I3 => \add_temp_14__92_carry_i_3_n_0\,
O => \add_temp_14__92_carry_i_6_n_0\
);
\add_temp_14__92_carry_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => RESIZE32(0),
I1 => RESIZE34(0),
I2 => RESIZE30(0),
O => \add_temp_14__92_carry_i_7_n_0\
);
\data_pipeline_tmp_reg[0][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(0),
Q => \data_pipeline_tmp_reg[0]\(0)
);
\data_pipeline_tmp_reg[0][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(10),
Q => \data_pipeline_tmp_reg[0]\(10)
);
\data_pipeline_tmp_reg[0][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(11),
Q => \data_pipeline_tmp_reg[0]\(11)
);
\data_pipeline_tmp_reg[0][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(12),
Q => \data_pipeline_tmp_reg[0]\(12)
);
\data_pipeline_tmp_reg[0][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(13),
Q => \data_pipeline_tmp_reg[0]\(13)
);
\data_pipeline_tmp_reg[0][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(14),
Q => \data_pipeline_tmp_reg[0]\(14)
);
\data_pipeline_tmp_reg[0][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(15),
Q => \data_pipeline_tmp_reg[0]\(15)
);
\data_pipeline_tmp_reg[0][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(1),
Q => \data_pipeline_tmp_reg[0]\(1)
);
\data_pipeline_tmp_reg[0][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(2),
Q => \data_pipeline_tmp_reg[0]\(2)
);
\data_pipeline_tmp_reg[0][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(3),
Q => \data_pipeline_tmp_reg[0]\(3)
);
\data_pipeline_tmp_reg[0][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(4),
Q => \data_pipeline_tmp_reg[0]\(4)
);
\data_pipeline_tmp_reg[0][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(5),
Q => \data_pipeline_tmp_reg[0]\(5)
);
\data_pipeline_tmp_reg[0][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(6),
Q => \data_pipeline_tmp_reg[0]\(6)
);
\data_pipeline_tmp_reg[0][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(7),
Q => \data_pipeline_tmp_reg[0]\(7)
);
\data_pipeline_tmp_reg[0][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(8),
Q => \data_pipeline_tmp_reg[0]\(8)
);
\data_pipeline_tmp_reg[0][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[1]\(9),
Q => \data_pipeline_tmp_reg[0]\(9)
);
\data_pipeline_tmp_reg[10][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(0),
Q => \data_pipeline_tmp_reg[10]\(0)
);
\data_pipeline_tmp_reg[10][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(10),
Q => \data_pipeline_tmp_reg[10]\(10)
);
\data_pipeline_tmp_reg[10][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(11),
Q => \data_pipeline_tmp_reg[10]\(11)
);
\data_pipeline_tmp_reg[10][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(12),
Q => \data_pipeline_tmp_reg[10]\(12)
);
\data_pipeline_tmp_reg[10][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(13),
Q => \data_pipeline_tmp_reg[10]\(13)
);
\data_pipeline_tmp_reg[10][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(14),
Q => \data_pipeline_tmp_reg[10]\(14)
);
\data_pipeline_tmp_reg[10][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(15),
Q => \data_pipeline_tmp_reg[10]\(15)
);
\data_pipeline_tmp_reg[10][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(1),
Q => \data_pipeline_tmp_reg[10]\(1)
);
\data_pipeline_tmp_reg[10][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(2),
Q => \data_pipeline_tmp_reg[10]\(2)
);
\data_pipeline_tmp_reg[10][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(3),
Q => \data_pipeline_tmp_reg[10]\(3)
);
\data_pipeline_tmp_reg[10][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(4),
Q => \data_pipeline_tmp_reg[10]\(4)
);
\data_pipeline_tmp_reg[10][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(5),
Q => \data_pipeline_tmp_reg[10]\(5)
);
\data_pipeline_tmp_reg[10][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(6),
Q => \data_pipeline_tmp_reg[10]\(6)
);
\data_pipeline_tmp_reg[10][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(7),
Q => \data_pipeline_tmp_reg[10]\(7)
);
\data_pipeline_tmp_reg[10][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(8),
Q => \data_pipeline_tmp_reg[10]\(8)
);
\data_pipeline_tmp_reg[10][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[11]\(9),
Q => \data_pipeline_tmp_reg[10]\(9)
);
\data_pipeline_tmp_reg[11][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(0),
Q => \data_pipeline_tmp_reg[11]\(0)
);
\data_pipeline_tmp_reg[11][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(10),
Q => \data_pipeline_tmp_reg[11]\(10)
);
\data_pipeline_tmp_reg[11][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(11),
Q => \data_pipeline_tmp_reg[11]\(11)
);
\data_pipeline_tmp_reg[11][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(12),
Q => \data_pipeline_tmp_reg[11]\(12)
);
\data_pipeline_tmp_reg[11][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(13),
Q => \data_pipeline_tmp_reg[11]\(13)
);
\data_pipeline_tmp_reg[11][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(14),
Q => \data_pipeline_tmp_reg[11]\(14)
);
\data_pipeline_tmp_reg[11][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(15),
Q => \data_pipeline_tmp_reg[11]\(15)
);
\data_pipeline_tmp_reg[11][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(1),
Q => \data_pipeline_tmp_reg[11]\(1)
);
\data_pipeline_tmp_reg[11][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(2),
Q => \data_pipeline_tmp_reg[11]\(2)
);
\data_pipeline_tmp_reg[11][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(3),
Q => \data_pipeline_tmp_reg[11]\(3)
);
\data_pipeline_tmp_reg[11][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(4),
Q => \data_pipeline_tmp_reg[11]\(4)
);
\data_pipeline_tmp_reg[11][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(5),
Q => \data_pipeline_tmp_reg[11]\(5)
);
\data_pipeline_tmp_reg[11][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(6),
Q => \data_pipeline_tmp_reg[11]\(6)
);
\data_pipeline_tmp_reg[11][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(7),
Q => \data_pipeline_tmp_reg[11]\(7)
);
\data_pipeline_tmp_reg[11][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(8),
Q => \data_pipeline_tmp_reg[11]\(8)
);
\data_pipeline_tmp_reg[11][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[12]\(9),
Q => \data_pipeline_tmp_reg[11]\(9)
);
\data_pipeline_tmp_reg[12][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(0),
Q => \data_pipeline_tmp_reg[12]\(0)
);
\data_pipeline_tmp_reg[12][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(10),
Q => \data_pipeline_tmp_reg[12]\(10)
);
\data_pipeline_tmp_reg[12][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(11),
Q => \data_pipeline_tmp_reg[12]\(11)
);
\data_pipeline_tmp_reg[12][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(12),
Q => \data_pipeline_tmp_reg[12]\(12)
);
\data_pipeline_tmp_reg[12][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(13),
Q => \data_pipeline_tmp_reg[12]\(13)
);
\data_pipeline_tmp_reg[12][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(14),
Q => \data_pipeline_tmp_reg[12]\(14)
);
\data_pipeline_tmp_reg[12][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(15),
Q => \data_pipeline_tmp_reg[12]\(15)
);
\data_pipeline_tmp_reg[12][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(1),
Q => \data_pipeline_tmp_reg[12]\(1)
);
\data_pipeline_tmp_reg[12][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(2),
Q => \data_pipeline_tmp_reg[12]\(2)
);
\data_pipeline_tmp_reg[12][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(3),
Q => \data_pipeline_tmp_reg[12]\(3)
);
\data_pipeline_tmp_reg[12][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(4),
Q => \data_pipeline_tmp_reg[12]\(4)
);
\data_pipeline_tmp_reg[12][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(5),
Q => \data_pipeline_tmp_reg[12]\(5)
);
\data_pipeline_tmp_reg[12][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(6),
Q => \data_pipeline_tmp_reg[12]\(6)
);
\data_pipeline_tmp_reg[12][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(7),
Q => \data_pipeline_tmp_reg[12]\(7)
);
\data_pipeline_tmp_reg[12][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(8),
Q => \data_pipeline_tmp_reg[12]\(8)
);
\data_pipeline_tmp_reg[12][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[13]\(9),
Q => \data_pipeline_tmp_reg[12]\(9)
);
\data_pipeline_tmp_reg[13][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(0),
Q => \data_pipeline_tmp_reg[13]\(0)
);
\data_pipeline_tmp_reg[13][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(10),
Q => \data_pipeline_tmp_reg[13]\(10)
);
\data_pipeline_tmp_reg[13][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(11),
Q => \data_pipeline_tmp_reg[13]\(11)
);
\data_pipeline_tmp_reg[13][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(12),
Q => \data_pipeline_tmp_reg[13]\(12)
);
\data_pipeline_tmp_reg[13][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(13),
Q => \data_pipeline_tmp_reg[13]\(13)
);
\data_pipeline_tmp_reg[13][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(14),
Q => \data_pipeline_tmp_reg[13]\(14)
);
\data_pipeline_tmp_reg[13][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(15),
Q => \data_pipeline_tmp_reg[13]\(15)
);
\data_pipeline_tmp_reg[13][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(1),
Q => \data_pipeline_tmp_reg[13]\(1)
);
\data_pipeline_tmp_reg[13][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(2),
Q => \data_pipeline_tmp_reg[13]\(2)
);
\data_pipeline_tmp_reg[13][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(3),
Q => \data_pipeline_tmp_reg[13]\(3)
);
\data_pipeline_tmp_reg[13][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(4),
Q => \data_pipeline_tmp_reg[13]\(4)
);
\data_pipeline_tmp_reg[13][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(5),
Q => \data_pipeline_tmp_reg[13]\(5)
);
\data_pipeline_tmp_reg[13][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(6),
Q => \data_pipeline_tmp_reg[13]\(6)
);
\data_pipeline_tmp_reg[13][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(7),
Q => \data_pipeline_tmp_reg[13]\(7)
);
\data_pipeline_tmp_reg[13][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(8),
Q => \data_pipeline_tmp_reg[13]\(8)
);
\data_pipeline_tmp_reg[13][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[14]\(9),
Q => \data_pipeline_tmp_reg[13]\(9)
);
\data_pipeline_tmp_reg[14][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(0),
Q => \data_pipeline_tmp_reg[14]\(0)
);
\data_pipeline_tmp_reg[14][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(10),
Q => \data_pipeline_tmp_reg[14]\(10)
);
\data_pipeline_tmp_reg[14][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(11),
Q => \data_pipeline_tmp_reg[14]\(11)
);
\data_pipeline_tmp_reg[14][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(12),
Q => \data_pipeline_tmp_reg[14]\(12)
);
\data_pipeline_tmp_reg[14][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(13),
Q => \data_pipeline_tmp_reg[14]\(13)
);
\data_pipeline_tmp_reg[14][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(14),
Q => \data_pipeline_tmp_reg[14]\(14)
);
\data_pipeline_tmp_reg[14][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(15),
Q => \data_pipeline_tmp_reg[14]\(15)
);
\data_pipeline_tmp_reg[14][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(1),
Q => \data_pipeline_tmp_reg[14]\(1)
);
\data_pipeline_tmp_reg[14][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(2),
Q => \data_pipeline_tmp_reg[14]\(2)
);
\data_pipeline_tmp_reg[14][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(3),
Q => \data_pipeline_tmp_reg[14]\(3)
);
\data_pipeline_tmp_reg[14][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(4),
Q => \data_pipeline_tmp_reg[14]\(4)
);
\data_pipeline_tmp_reg[14][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(5),
Q => \data_pipeline_tmp_reg[14]\(5)
);
\data_pipeline_tmp_reg[14][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(6),
Q => \data_pipeline_tmp_reg[14]\(6)
);
\data_pipeline_tmp_reg[14][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(7),
Q => \data_pipeline_tmp_reg[14]\(7)
);
\data_pipeline_tmp_reg[14][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(8),
Q => \data_pipeline_tmp_reg[14]\(8)
);
\data_pipeline_tmp_reg[14][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \write_reg_x_k_reg[15]\(9),
Q => \data_pipeline_tmp_reg[14]\(9)
);
\data_pipeline_tmp_reg[1][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(0),
Q => \data_pipeline_tmp_reg[1]\(0)
);
\data_pipeline_tmp_reg[1][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(10),
Q => \data_pipeline_tmp_reg[1]\(10)
);
\data_pipeline_tmp_reg[1][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(11),
Q => \data_pipeline_tmp_reg[1]\(11)
);
\data_pipeline_tmp_reg[1][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(12),
Q => \data_pipeline_tmp_reg[1]\(12)
);
\data_pipeline_tmp_reg[1][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(13),
Q => \data_pipeline_tmp_reg[1]\(13)
);
\data_pipeline_tmp_reg[1][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(14),
Q => \data_pipeline_tmp_reg[1]\(14)
);
\data_pipeline_tmp_reg[1][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(15),
Q => \data_pipeline_tmp_reg[1]\(15)
);
\data_pipeline_tmp_reg[1][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(1),
Q => \data_pipeline_tmp_reg[1]\(1)
);
\data_pipeline_tmp_reg[1][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(2),
Q => \data_pipeline_tmp_reg[1]\(2)
);
\data_pipeline_tmp_reg[1][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(3),
Q => \data_pipeline_tmp_reg[1]\(3)
);
\data_pipeline_tmp_reg[1][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(4),
Q => \data_pipeline_tmp_reg[1]\(4)
);
\data_pipeline_tmp_reg[1][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(5),
Q => \data_pipeline_tmp_reg[1]\(5)
);
\data_pipeline_tmp_reg[1][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(6),
Q => \data_pipeline_tmp_reg[1]\(6)
);
\data_pipeline_tmp_reg[1][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(7),
Q => \data_pipeline_tmp_reg[1]\(7)
);
\data_pipeline_tmp_reg[1][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(8),
Q => \data_pipeline_tmp_reg[1]\(8)
);
\data_pipeline_tmp_reg[1][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[2]\(9),
Q => \data_pipeline_tmp_reg[1]\(9)
);
\data_pipeline_tmp_reg[2][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(0),
Q => \data_pipeline_tmp_reg[2]\(0)
);
\data_pipeline_tmp_reg[2][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(10),
Q => \data_pipeline_tmp_reg[2]\(10)
);
\data_pipeline_tmp_reg[2][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(11),
Q => \data_pipeline_tmp_reg[2]\(11)
);
\data_pipeline_tmp_reg[2][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(12),
Q => \data_pipeline_tmp_reg[2]\(12)
);
\data_pipeline_tmp_reg[2][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(13),
Q => \data_pipeline_tmp_reg[2]\(13)
);
\data_pipeline_tmp_reg[2][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(14),
Q => \data_pipeline_tmp_reg[2]\(14)
);
\data_pipeline_tmp_reg[2][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(15),
Q => \data_pipeline_tmp_reg[2]\(15)
);
\data_pipeline_tmp_reg[2][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(1),
Q => \data_pipeline_tmp_reg[2]\(1)
);
\data_pipeline_tmp_reg[2][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(2),
Q => \data_pipeline_tmp_reg[2]\(2)
);
\data_pipeline_tmp_reg[2][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(3),
Q => \data_pipeline_tmp_reg[2]\(3)
);
\data_pipeline_tmp_reg[2][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(4),
Q => \data_pipeline_tmp_reg[2]\(4)
);
\data_pipeline_tmp_reg[2][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(5),
Q => \data_pipeline_tmp_reg[2]\(5)
);
\data_pipeline_tmp_reg[2][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(6),
Q => \data_pipeline_tmp_reg[2]\(6)
);
\data_pipeline_tmp_reg[2][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(7),
Q => \data_pipeline_tmp_reg[2]\(7)
);
\data_pipeline_tmp_reg[2][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(8),
Q => \data_pipeline_tmp_reg[2]\(8)
);
\data_pipeline_tmp_reg[2][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[3]\(9),
Q => \data_pipeline_tmp_reg[2]\(9)
);
\data_pipeline_tmp_reg[3][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(0),
Q => \data_pipeline_tmp_reg[3]\(0)
);
\data_pipeline_tmp_reg[3][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(10),
Q => \data_pipeline_tmp_reg[3]\(10)
);
\data_pipeline_tmp_reg[3][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(11),
Q => \data_pipeline_tmp_reg[3]\(11)
);
\data_pipeline_tmp_reg[3][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(12),
Q => \data_pipeline_tmp_reg[3]\(12)
);
\data_pipeline_tmp_reg[3][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(13),
Q => \data_pipeline_tmp_reg[3]\(13)
);
\data_pipeline_tmp_reg[3][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(14),
Q => \data_pipeline_tmp_reg[3]\(14)
);
\data_pipeline_tmp_reg[3][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(15),
Q => \data_pipeline_tmp_reg[3]\(15)
);
\data_pipeline_tmp_reg[3][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(1),
Q => \data_pipeline_tmp_reg[3]\(1)
);
\data_pipeline_tmp_reg[3][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(2),
Q => \data_pipeline_tmp_reg[3]\(2)
);
\data_pipeline_tmp_reg[3][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(3),
Q => \data_pipeline_tmp_reg[3]\(3)
);
\data_pipeline_tmp_reg[3][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(4),
Q => \data_pipeline_tmp_reg[3]\(4)
);
\data_pipeline_tmp_reg[3][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(5),
Q => \data_pipeline_tmp_reg[3]\(5)
);
\data_pipeline_tmp_reg[3][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(6),
Q => \data_pipeline_tmp_reg[3]\(6)
);
\data_pipeline_tmp_reg[3][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(7),
Q => \data_pipeline_tmp_reg[3]\(7)
);
\data_pipeline_tmp_reg[3][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(8),
Q => \data_pipeline_tmp_reg[3]\(8)
);
\data_pipeline_tmp_reg[3][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[4]\(9),
Q => \data_pipeline_tmp_reg[3]\(9)
);
\data_pipeline_tmp_reg[4][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(0),
Q => \data_pipeline_tmp_reg[4]\(0)
);
\data_pipeline_tmp_reg[4][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(10),
Q => \data_pipeline_tmp_reg[4]\(10)
);
\data_pipeline_tmp_reg[4][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(11),
Q => \data_pipeline_tmp_reg[4]\(11)
);
\data_pipeline_tmp_reg[4][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(12),
Q => \data_pipeline_tmp_reg[4]\(12)
);
\data_pipeline_tmp_reg[4][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(13),
Q => \data_pipeline_tmp_reg[4]\(13)
);
\data_pipeline_tmp_reg[4][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(14),
Q => \data_pipeline_tmp_reg[4]\(14)
);
\data_pipeline_tmp_reg[4][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(15),
Q => \data_pipeline_tmp_reg[4]\(15)
);
\data_pipeline_tmp_reg[4][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(1),
Q => \data_pipeline_tmp_reg[4]\(1)
);
\data_pipeline_tmp_reg[4][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(2),
Q => \data_pipeline_tmp_reg[4]\(2)
);
\data_pipeline_tmp_reg[4][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(3),
Q => \data_pipeline_tmp_reg[4]\(3)
);
\data_pipeline_tmp_reg[4][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(4),
Q => \data_pipeline_tmp_reg[4]\(4)
);
\data_pipeline_tmp_reg[4][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(5),
Q => \data_pipeline_tmp_reg[4]\(5)
);
\data_pipeline_tmp_reg[4][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(6),
Q => \data_pipeline_tmp_reg[4]\(6)
);
\data_pipeline_tmp_reg[4][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(7),
Q => \data_pipeline_tmp_reg[4]\(7)
);
\data_pipeline_tmp_reg[4][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(8),
Q => \data_pipeline_tmp_reg[4]\(8)
);
\data_pipeline_tmp_reg[4][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[5]\(9),
Q => \data_pipeline_tmp_reg[4]\(9)
);
\data_pipeline_tmp_reg[5][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(0),
Q => \data_pipeline_tmp_reg[5]\(0)
);
\data_pipeline_tmp_reg[5][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(10),
Q => \data_pipeline_tmp_reg[5]\(10)
);
\data_pipeline_tmp_reg[5][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(11),
Q => \data_pipeline_tmp_reg[5]\(11)
);
\data_pipeline_tmp_reg[5][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(12),
Q => \data_pipeline_tmp_reg[5]\(12)
);
\data_pipeline_tmp_reg[5][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(13),
Q => \data_pipeline_tmp_reg[5]\(13)
);
\data_pipeline_tmp_reg[5][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(14),
Q => \data_pipeline_tmp_reg[5]\(14)
);
\data_pipeline_tmp_reg[5][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(15),
Q => \data_pipeline_tmp_reg[5]\(15)
);
\data_pipeline_tmp_reg[5][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(1),
Q => \data_pipeline_tmp_reg[5]\(1)
);
\data_pipeline_tmp_reg[5][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(2),
Q => \data_pipeline_tmp_reg[5]\(2)
);
\data_pipeline_tmp_reg[5][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(3),
Q => \data_pipeline_tmp_reg[5]\(3)
);
\data_pipeline_tmp_reg[5][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(4),
Q => \data_pipeline_tmp_reg[5]\(4)
);
\data_pipeline_tmp_reg[5][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(5),
Q => \data_pipeline_tmp_reg[5]\(5)
);
\data_pipeline_tmp_reg[5][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(6),
Q => \data_pipeline_tmp_reg[5]\(6)
);
\data_pipeline_tmp_reg[5][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(7),
Q => \data_pipeline_tmp_reg[5]\(7)
);
\data_pipeline_tmp_reg[5][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(8),
Q => \data_pipeline_tmp_reg[5]\(8)
);
\data_pipeline_tmp_reg[5][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[6]\(9),
Q => \data_pipeline_tmp_reg[5]\(9)
);
\data_pipeline_tmp_reg[6][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(0),
Q => \data_pipeline_tmp_reg[6]\(0)
);
\data_pipeline_tmp_reg[6][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(10),
Q => \data_pipeline_tmp_reg[6]\(10)
);
\data_pipeline_tmp_reg[6][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(11),
Q => \data_pipeline_tmp_reg[6]\(11)
);
\data_pipeline_tmp_reg[6][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(12),
Q => \data_pipeline_tmp_reg[6]\(12)
);
\data_pipeline_tmp_reg[6][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(13),
Q => \data_pipeline_tmp_reg[6]\(13)
);
\data_pipeline_tmp_reg[6][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(14),
Q => \data_pipeline_tmp_reg[6]\(14)
);
\data_pipeline_tmp_reg[6][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(15),
Q => \data_pipeline_tmp_reg[6]\(15)
);
\data_pipeline_tmp_reg[6][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(1),
Q => \data_pipeline_tmp_reg[6]\(1)
);
\data_pipeline_tmp_reg[6][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(2),
Q => \data_pipeline_tmp_reg[6]\(2)
);
\data_pipeline_tmp_reg[6][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(3),
Q => \data_pipeline_tmp_reg[6]\(3)
);
\data_pipeline_tmp_reg[6][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(4),
Q => \data_pipeline_tmp_reg[6]\(4)
);
\data_pipeline_tmp_reg[6][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(5),
Q => \data_pipeline_tmp_reg[6]\(5)
);
\data_pipeline_tmp_reg[6][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(6),
Q => \data_pipeline_tmp_reg[6]\(6)
);
\data_pipeline_tmp_reg[6][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(7),
Q => \data_pipeline_tmp_reg[6]\(7)
);
\data_pipeline_tmp_reg[6][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(8),
Q => \data_pipeline_tmp_reg[6]\(8)
);
\data_pipeline_tmp_reg[6][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[7]\(9),
Q => \data_pipeline_tmp_reg[6]\(9)
);
\data_pipeline_tmp_reg[7][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(0),
Q => \data_pipeline_tmp_reg[7]\(0)
);
\data_pipeline_tmp_reg[7][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(10),
Q => \data_pipeline_tmp_reg[7]\(10)
);
\data_pipeline_tmp_reg[7][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(11),
Q => \data_pipeline_tmp_reg[7]\(11)
);
\data_pipeline_tmp_reg[7][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(12),
Q => \data_pipeline_tmp_reg[7]\(12)
);
\data_pipeline_tmp_reg[7][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(13),
Q => \data_pipeline_tmp_reg[7]\(13)
);
\data_pipeline_tmp_reg[7][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(14),
Q => \data_pipeline_tmp_reg[7]\(14)
);
\data_pipeline_tmp_reg[7][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(15),
Q => \data_pipeline_tmp_reg[7]\(15)
);
\data_pipeline_tmp_reg[7][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(1),
Q => \data_pipeline_tmp_reg[7]\(1)
);
\data_pipeline_tmp_reg[7][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(2),
Q => \data_pipeline_tmp_reg[7]\(2)
);
\data_pipeline_tmp_reg[7][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(3),
Q => \data_pipeline_tmp_reg[7]\(3)
);
\data_pipeline_tmp_reg[7][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(4),
Q => \data_pipeline_tmp_reg[7]\(4)
);
\data_pipeline_tmp_reg[7][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(5),
Q => \data_pipeline_tmp_reg[7]\(5)
);
\data_pipeline_tmp_reg[7][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(6),
Q => \data_pipeline_tmp_reg[7]\(6)
);
\data_pipeline_tmp_reg[7][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(7),
Q => \data_pipeline_tmp_reg[7]\(7)
);
\data_pipeline_tmp_reg[7][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(8),
Q => \data_pipeline_tmp_reg[7]\(8)
);
\data_pipeline_tmp_reg[7][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[8]\(9),
Q => \data_pipeline_tmp_reg[7]\(9)
);
\data_pipeline_tmp_reg[8][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(0),
Q => \data_pipeline_tmp_reg[8]\(0)
);
\data_pipeline_tmp_reg[8][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(10),
Q => \data_pipeline_tmp_reg[8]\(10)
);
\data_pipeline_tmp_reg[8][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(11),
Q => \data_pipeline_tmp_reg[8]\(11)
);
\data_pipeline_tmp_reg[8][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(12),
Q => \data_pipeline_tmp_reg[8]\(12)
);
\data_pipeline_tmp_reg[8][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(13),
Q => \data_pipeline_tmp_reg[8]\(13)
);
\data_pipeline_tmp_reg[8][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(14),
Q => \data_pipeline_tmp_reg[8]\(14)
);
\data_pipeline_tmp_reg[8][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(15),
Q => \data_pipeline_tmp_reg[8]\(15)
);
\data_pipeline_tmp_reg[8][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(1),
Q => \data_pipeline_tmp_reg[8]\(1)
);
\data_pipeline_tmp_reg[8][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(2),
Q => \data_pipeline_tmp_reg[8]\(2)
);
\data_pipeline_tmp_reg[8][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(3),
Q => \data_pipeline_tmp_reg[8]\(3)
);
\data_pipeline_tmp_reg[8][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(4),
Q => \data_pipeline_tmp_reg[8]\(4)
);
\data_pipeline_tmp_reg[8][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(5),
Q => \data_pipeline_tmp_reg[8]\(5)
);
\data_pipeline_tmp_reg[8][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(6),
Q => \data_pipeline_tmp_reg[8]\(6)
);
\data_pipeline_tmp_reg[8][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(7),
Q => \data_pipeline_tmp_reg[8]\(7)
);
\data_pipeline_tmp_reg[8][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(8),
Q => \data_pipeline_tmp_reg[8]\(8)
);
\data_pipeline_tmp_reg[8][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[9]\(9),
Q => \data_pipeline_tmp_reg[8]\(9)
);
\data_pipeline_tmp_reg[9][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(0),
Q => \data_pipeline_tmp_reg[9]\(0)
);
\data_pipeline_tmp_reg[9][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(10),
Q => \data_pipeline_tmp_reg[9]\(10)
);
\data_pipeline_tmp_reg[9][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(11),
Q => \data_pipeline_tmp_reg[9]\(11)
);
\data_pipeline_tmp_reg[9][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(12),
Q => \data_pipeline_tmp_reg[9]\(12)
);
\data_pipeline_tmp_reg[9][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(13),
Q => \data_pipeline_tmp_reg[9]\(13)
);
\data_pipeline_tmp_reg[9][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(14),
Q => \data_pipeline_tmp_reg[9]\(14)
);
\data_pipeline_tmp_reg[9][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(15),
Q => \data_pipeline_tmp_reg[9]\(15)
);
\data_pipeline_tmp_reg[9][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(1),
Q => \data_pipeline_tmp_reg[9]\(1)
);
\data_pipeline_tmp_reg[9][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(2),
Q => \data_pipeline_tmp_reg[9]\(2)
);
\data_pipeline_tmp_reg[9][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(3),
Q => \data_pipeline_tmp_reg[9]\(3)
);
\data_pipeline_tmp_reg[9][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(4),
Q => \data_pipeline_tmp_reg[9]\(4)
);
\data_pipeline_tmp_reg[9][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(5),
Q => \data_pipeline_tmp_reg[9]\(5)
);
\data_pipeline_tmp_reg[9][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(6),
Q => \data_pipeline_tmp_reg[9]\(6)
);
\data_pipeline_tmp_reg[9][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(7),
Q => \data_pipeline_tmp_reg[9]\(7)
);
\data_pipeline_tmp_reg[9][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(8),
Q => \data_pipeline_tmp_reg[9]\(8)
);
\data_pipeline_tmp_reg[9][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \data_pipeline_tmp_reg[10]\(9),
Q => \data_pipeline_tmp_reg[9]\(9)
);
mul_temp: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[0]_15\(15),
B(16) => \weight_reg[0]_15\(15),
B(15 downto 0) => \weight_reg[0]_15\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_n_74,
P(30) => mul_temp_n_75,
P(29) => mul_temp_n_76,
P(28) => mul_temp_n_77,
P(27) => mul_temp_n_78,
P(26) => mul_temp_n_79,
P(25) => mul_temp_n_80,
P(24) => mul_temp_n_81,
P(23) => mul_temp_n_82,
P(22) => mul_temp_n_83,
P(21) => mul_temp_n_84,
P(20) => mul_temp_n_85,
P(19) => mul_temp_n_86,
P(18) => mul_temp_n_87,
P(17) => mul_temp_n_88,
P(16) => mul_temp_n_89,
P(15) => mul_temp_n_90,
P(14) => \^mul_temp\(14),
P(13) => mul_temp_n_92,
P(12) => mul_temp_n_93,
P(11) => mul_temp_n_94,
P(10) => mul_temp_n_95,
P(9) => mul_temp_n_96,
P(8) => mul_temp_n_97,
P(7) => mul_temp_n_98,
P(6) => mul_temp_n_99,
P(5) => mul_temp_n_100,
P(4) => mul_temp_n_101,
P(3) => mul_temp_n_102,
P(2) => mul_temp_n_103,
P(1) => mul_temp_n_104,
P(0) => mul_temp_n_105,
PATTERNBDETECT => NLW_mul_temp_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_UNDERFLOW_UNCONNECTED
);
mul_temp_1: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_1_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[1]_0\(15),
B(16) => \weight_reg[1]_0\(15),
B(15 downto 0) => \weight_reg[1]_0\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_1_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_1_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_1_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_1_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_1_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_1_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_1_n_74,
P(30) => mul_temp_1_n_75,
P(29) => mul_temp_1_n_76,
P(28) => mul_temp_1_n_77,
P(27) => mul_temp_1_n_78,
P(26) => mul_temp_1_n_79,
P(25) => mul_temp_1_n_80,
P(24) => mul_temp_1_n_81,
P(23) => mul_temp_1_n_82,
P(22) => mul_temp_1_n_83,
P(21) => mul_temp_1_n_84,
P(20) => mul_temp_1_n_85,
P(19) => mul_temp_1_n_86,
P(18) => mul_temp_1_n_87,
P(17) => mul_temp_1_n_88,
P(16) => mul_temp_1_n_89,
P(15) => mul_temp_1_n_90,
P(14) => \^mul_temp_1\(14),
P(13) => mul_temp_1_n_92,
P(12) => mul_temp_1_n_93,
P(11) => mul_temp_1_n_94,
P(10) => mul_temp_1_n_95,
P(9) => mul_temp_1_n_96,
P(8) => mul_temp_1_n_97,
P(7) => mul_temp_1_n_98,
P(6) => mul_temp_1_n_99,
P(5) => mul_temp_1_n_100,
P(4) => mul_temp_1_n_101,
P(3) => mul_temp_1_n_102,
P(2) => mul_temp_1_n_103,
P(1) => mul_temp_1_n_104,
P(0) => mul_temp_1_n_105,
PATTERNBDETECT => NLW_mul_temp_1_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_1_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_1_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_1_UNDERFLOW_UNCONNECTED
);
mul_temp_10: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_10_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[10]_9\(15),
B(16) => \weight_reg[10]_9\(15),
B(15 downto 0) => \weight_reg[10]_9\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_10_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_10_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_10_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_10_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_10_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_10_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_10_n_74,
P(30) => mul_temp_10_n_75,
P(29) => mul_temp_10_n_76,
P(28) => mul_temp_10_n_77,
P(27) => mul_temp_10_n_78,
P(26) => mul_temp_10_n_79,
P(25) => mul_temp_10_n_80,
P(24) => mul_temp_10_n_81,
P(23) => mul_temp_10_n_82,
P(22) => mul_temp_10_n_83,
P(21) => mul_temp_10_n_84,
P(20) => mul_temp_10_n_85,
P(19) => mul_temp_10_n_86,
P(18) => mul_temp_10_n_87,
P(17) => mul_temp_10_n_88,
P(16) => mul_temp_10_n_89,
P(15) => mul_temp_10_n_90,
P(14) => \^mul_temp_10\(14),
P(13) => mul_temp_10_n_92,
P(12) => mul_temp_10_n_93,
P(11) => mul_temp_10_n_94,
P(10) => mul_temp_10_n_95,
P(9) => mul_temp_10_n_96,
P(8) => mul_temp_10_n_97,
P(7) => mul_temp_10_n_98,
P(6) => mul_temp_10_n_99,
P(5) => mul_temp_10_n_100,
P(4) => mul_temp_10_n_101,
P(3) => mul_temp_10_n_102,
P(2) => mul_temp_10_n_103,
P(1) => mul_temp_10_n_104,
P(0) => mul_temp_10_n_105,
PATTERNBDETECT => NLW_mul_temp_10_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_10_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_10_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_10_UNDERFLOW_UNCONNECTED
);
mul_temp_11: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_11_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[11]_10\(15),
B(16) => \weight_reg[11]_10\(15),
B(15 downto 0) => \weight_reg[11]_10\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_11_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_11_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_11_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_11_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_11_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_11_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_11_n_74,
P(30) => mul_temp_11_n_75,
P(29) => mul_temp_11_n_76,
P(28) => mul_temp_11_n_77,
P(27) => mul_temp_11_n_78,
P(26) => mul_temp_11_n_79,
P(25) => mul_temp_11_n_80,
P(24) => mul_temp_11_n_81,
P(23) => mul_temp_11_n_82,
P(22) => mul_temp_11_n_83,
P(21) => mul_temp_11_n_84,
P(20) => mul_temp_11_n_85,
P(19) => mul_temp_11_n_86,
P(18) => mul_temp_11_n_87,
P(17) => mul_temp_11_n_88,
P(16) => mul_temp_11_n_89,
P(15) => mul_temp_11_n_90,
P(14) => \^mul_temp_11\(14),
P(13) => mul_temp_11_n_92,
P(12) => mul_temp_11_n_93,
P(11) => mul_temp_11_n_94,
P(10) => mul_temp_11_n_95,
P(9) => mul_temp_11_n_96,
P(8) => mul_temp_11_n_97,
P(7) => mul_temp_11_n_98,
P(6) => mul_temp_11_n_99,
P(5) => mul_temp_11_n_100,
P(4) => mul_temp_11_n_101,
P(3) => mul_temp_11_n_102,
P(2) => mul_temp_11_n_103,
P(1) => mul_temp_11_n_104,
P(0) => mul_temp_11_n_105,
PATTERNBDETECT => NLW_mul_temp_11_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_11_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_11_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_11_UNDERFLOW_UNCONNECTED
);
mul_temp_12: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_12_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[12]_11\(15),
B(16) => \weight_reg[12]_11\(15),
B(15 downto 0) => \weight_reg[12]_11\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_12_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_12_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_12_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_12_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_12_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_12_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_12_n_74,
P(30) => mul_temp_12_n_75,
P(29) => mul_temp_12_n_76,
P(28) => mul_temp_12_n_77,
P(27) => mul_temp_12_n_78,
P(26) => mul_temp_12_n_79,
P(25) => mul_temp_12_n_80,
P(24) => mul_temp_12_n_81,
P(23) => mul_temp_12_n_82,
P(22) => mul_temp_12_n_83,
P(21) => mul_temp_12_n_84,
P(20) => mul_temp_12_n_85,
P(19) => mul_temp_12_n_86,
P(18) => mul_temp_12_n_87,
P(17) => mul_temp_12_n_88,
P(16) => mul_temp_12_n_89,
P(15) => mul_temp_12_n_90,
P(14) => \^mul_temp_12\(14),
P(13) => mul_temp_12_n_92,
P(12) => mul_temp_12_n_93,
P(11) => mul_temp_12_n_94,
P(10) => mul_temp_12_n_95,
P(9) => mul_temp_12_n_96,
P(8) => mul_temp_12_n_97,
P(7) => mul_temp_12_n_98,
P(6) => mul_temp_12_n_99,
P(5) => mul_temp_12_n_100,
P(4) => mul_temp_12_n_101,
P(3) => mul_temp_12_n_102,
P(2) => mul_temp_12_n_103,
P(1) => mul_temp_12_n_104,
P(0) => mul_temp_12_n_105,
PATTERNBDETECT => NLW_mul_temp_12_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_12_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_12_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_12_UNDERFLOW_UNCONNECTED
);
mul_temp_13: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_13_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[13]_12\(15),
B(16) => \weight_reg[13]_12\(15),
B(15 downto 0) => \weight_reg[13]_12\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_13_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_13_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_13_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_13_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_13_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_13_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_13_n_74,
P(30) => mul_temp_13_n_75,
P(29) => mul_temp_13_n_76,
P(28) => mul_temp_13_n_77,
P(27) => mul_temp_13_n_78,
P(26) => mul_temp_13_n_79,
P(25) => mul_temp_13_n_80,
P(24) => mul_temp_13_n_81,
P(23) => mul_temp_13_n_82,
P(22) => mul_temp_13_n_83,
P(21) => mul_temp_13_n_84,
P(20) => mul_temp_13_n_85,
P(19) => mul_temp_13_n_86,
P(18) => mul_temp_13_n_87,
P(17) => mul_temp_13_n_88,
P(16) => mul_temp_13_n_89,
P(15) => mul_temp_13_n_90,
P(14) => \^mul_temp_13\(14),
P(13) => mul_temp_13_n_92,
P(12) => mul_temp_13_n_93,
P(11) => mul_temp_13_n_94,
P(10) => mul_temp_13_n_95,
P(9) => mul_temp_13_n_96,
P(8) => mul_temp_13_n_97,
P(7) => mul_temp_13_n_98,
P(6) => mul_temp_13_n_99,
P(5) => mul_temp_13_n_100,
P(4) => mul_temp_13_n_101,
P(3) => mul_temp_13_n_102,
P(2) => mul_temp_13_n_103,
P(1) => mul_temp_13_n_104,
P(0) => mul_temp_13_n_105,
PATTERNBDETECT => NLW_mul_temp_13_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_13_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_13_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_13_UNDERFLOW_UNCONNECTED
);
mul_temp_14: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_14_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[14]_13\(15),
B(16) => \weight_reg[14]_13\(15),
B(15 downto 0) => \weight_reg[14]_13\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_14_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_14_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_14_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_14_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_14_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_14_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_14_n_74,
P(30) => mul_temp_14_n_75,
P(29) => mul_temp_14_n_76,
P(28) => mul_temp_14_n_77,
P(27) => mul_temp_14_n_78,
P(26) => mul_temp_14_n_79,
P(25) => mul_temp_14_n_80,
P(24) => mul_temp_14_n_81,
P(23) => mul_temp_14_n_82,
P(22) => mul_temp_14_n_83,
P(21) => mul_temp_14_n_84,
P(20) => mul_temp_14_n_85,
P(19) => mul_temp_14_n_86,
P(18) => mul_temp_14_n_87,
P(17) => mul_temp_14_n_88,
P(16) => mul_temp_14_n_89,
P(15) => mul_temp_14_n_90,
P(14) => \^mul_temp_14\(14),
P(13) => mul_temp_14_n_92,
P(12) => mul_temp_14_n_93,
P(11) => mul_temp_14_n_94,
P(10) => mul_temp_14_n_95,
P(9) => mul_temp_14_n_96,
P(8) => mul_temp_14_n_97,
P(7) => mul_temp_14_n_98,
P(6) => mul_temp_14_n_99,
P(5) => mul_temp_14_n_100,
P(4) => mul_temp_14_n_101,
P(3) => mul_temp_14_n_102,
P(2) => mul_temp_14_n_103,
P(1) => mul_temp_14_n_104,
P(0) => mul_temp_14_n_105,
PATTERNBDETECT => NLW_mul_temp_14_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_14_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_14_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_14_UNDERFLOW_UNCONNECTED
);
mul_temp_15: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_15_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[15]_14\(15),
B(16) => \weight_reg[15]_14\(15),
B(15 downto 0) => \weight_reg[15]_14\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_15_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_15_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_15_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_15_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_15_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_15_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_15_n_74,
P(30) => mul_temp_15_n_75,
P(29) => mul_temp_15_n_76,
P(28) => mul_temp_15_n_77,
P(27) => mul_temp_15_n_78,
P(26) => mul_temp_15_n_79,
P(25) => mul_temp_15_n_80,
P(24) => mul_temp_15_n_81,
P(23) => mul_temp_15_n_82,
P(22) => mul_temp_15_n_83,
P(21) => mul_temp_15_n_84,
P(20) => mul_temp_15_n_85,
P(19) => mul_temp_15_n_86,
P(18) => mul_temp_15_n_87,
P(17) => mul_temp_15_n_88,
P(16) => mul_temp_15_n_89,
P(15) => mul_temp_15_n_90,
P(14) => \^mul_temp_15\(14),
P(13) => mul_temp_15_n_92,
P(12) => mul_temp_15_n_93,
P(11) => mul_temp_15_n_94,
P(10) => mul_temp_15_n_95,
P(9) => mul_temp_15_n_96,
P(8) => mul_temp_15_n_97,
P(7) => mul_temp_15_n_98,
P(6) => mul_temp_15_n_99,
P(5) => mul_temp_15_n_100,
P(4) => mul_temp_15_n_101,
P(3) => mul_temp_15_n_102,
P(2) => mul_temp_15_n_103,
P(1) => mul_temp_15_n_104,
P(0) => mul_temp_15_n_105,
PATTERNBDETECT => NLW_mul_temp_15_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_15_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_15_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_15_UNDERFLOW_UNCONNECTED
);
mul_temp_17: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[0]\(15),
A(28) => \data_pipeline_tmp_reg[0]\(15),
A(27) => \data_pipeline_tmp_reg[0]\(15),
A(26) => \data_pipeline_tmp_reg[0]\(15),
A(25) => \data_pipeline_tmp_reg[0]\(15),
A(24) => \data_pipeline_tmp_reg[0]\(15),
A(23) => \data_pipeline_tmp_reg[0]\(15),
A(22) => \data_pipeline_tmp_reg[0]\(15),
A(21) => \data_pipeline_tmp_reg[0]\(15),
A(20) => \data_pipeline_tmp_reg[0]\(15),
A(19) => \data_pipeline_tmp_reg[0]\(15),
A(18) => \data_pipeline_tmp_reg[0]\(15),
A(17) => \data_pipeline_tmp_reg[0]\(15),
A(16) => \data_pipeline_tmp_reg[0]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[0]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_17_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_17_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_17_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_17_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_17_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_17_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_17_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_17_n_74,
P(30) => mul_temp_17_n_75,
P(29) => mul_temp_17_n_76,
P(28) => mul_temp_17_n_77,
P(27) => mul_temp_17_n_78,
P(26) => mul_temp_17_n_79,
P(25) => mul_temp_17_n_80,
P(24) => mul_temp_17_n_81,
P(23) => mul_temp_17_n_82,
P(22) => mul_temp_17_n_83,
P(21) => mul_temp_17_n_84,
P(20) => mul_temp_17_n_85,
P(19) => mul_temp_17_n_86,
P(18) => mul_temp_17_n_87,
P(17) => mul_temp_17_n_88,
P(16) => mul_temp_17_n_89,
P(15) => mul_temp_17_n_90,
P(14) => \^mul_temp_17\(14),
P(13) => mul_temp_17_n_92,
P(12) => mul_temp_17_n_93,
P(11) => mul_temp_17_n_94,
P(10) => mul_temp_17_n_95,
P(9) => mul_temp_17_n_96,
P(8) => mul_temp_17_n_97,
P(7) => mul_temp_17_n_98,
P(6) => mul_temp_17_n_99,
P(5) => mul_temp_17_n_100,
P(4) => mul_temp_17_n_101,
P(3) => mul_temp_17_n_102,
P(2) => mul_temp_17_n_103,
P(1) => mul_temp_17_n_104,
P(0) => mul_temp_17_n_105,
PATTERNBDETECT => NLW_mul_temp_17_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_17_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_17_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_17_UNDERFLOW_UNCONNECTED
);
mul_temp_18: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[1]\(15),
A(28) => \data_pipeline_tmp_reg[1]\(15),
A(27) => \data_pipeline_tmp_reg[1]\(15),
A(26) => \data_pipeline_tmp_reg[1]\(15),
A(25) => \data_pipeline_tmp_reg[1]\(15),
A(24) => \data_pipeline_tmp_reg[1]\(15),
A(23) => \data_pipeline_tmp_reg[1]\(15),
A(22) => \data_pipeline_tmp_reg[1]\(15),
A(21) => \data_pipeline_tmp_reg[1]\(15),
A(20) => \data_pipeline_tmp_reg[1]\(15),
A(19) => \data_pipeline_tmp_reg[1]\(15),
A(18) => \data_pipeline_tmp_reg[1]\(15),
A(17) => \data_pipeline_tmp_reg[1]\(15),
A(16) => \data_pipeline_tmp_reg[1]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[1]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_18_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_18_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_18_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_18_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_18_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_18_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_18_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_18_n_74,
P(30) => mul_temp_18_n_75,
P(29) => mul_temp_18_n_76,
P(28) => mul_temp_18_n_77,
P(27) => mul_temp_18_n_78,
P(26) => mul_temp_18_n_79,
P(25) => mul_temp_18_n_80,
P(24) => mul_temp_18_n_81,
P(23) => mul_temp_18_n_82,
P(22) => mul_temp_18_n_83,
P(21) => mul_temp_18_n_84,
P(20) => mul_temp_18_n_85,
P(19) => mul_temp_18_n_86,
P(18) => mul_temp_18_n_87,
P(17) => mul_temp_18_n_88,
P(16) => mul_temp_18_n_89,
P(15) => mul_temp_18_n_90,
P(14) => \^mul_temp_18\(14),
P(13) => mul_temp_18_n_92,
P(12) => mul_temp_18_n_93,
P(11) => mul_temp_18_n_94,
P(10) => mul_temp_18_n_95,
P(9) => mul_temp_18_n_96,
P(8) => mul_temp_18_n_97,
P(7) => mul_temp_18_n_98,
P(6) => mul_temp_18_n_99,
P(5) => mul_temp_18_n_100,
P(4) => mul_temp_18_n_101,
P(3) => mul_temp_18_n_102,
P(2) => mul_temp_18_n_103,
P(1) => mul_temp_18_n_104,
P(0) => mul_temp_18_n_105,
PATTERNBDETECT => NLW_mul_temp_18_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_18_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_18_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_18_UNDERFLOW_UNCONNECTED
);
mul_temp_19: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_19_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_19_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_19_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_19_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_19_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_19_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_19_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_19_n_74,
P(30) => mul_temp_19_n_75,
P(29) => mul_temp_19_n_76,
P(28) => mul_temp_19_n_77,
P(27) => mul_temp_19_n_78,
P(26) => mul_temp_19_n_79,
P(25) => mul_temp_19_n_80,
P(24) => mul_temp_19_n_81,
P(23) => mul_temp_19_n_82,
P(22) => mul_temp_19_n_83,
P(21) => mul_temp_19_n_84,
P(20) => mul_temp_19_n_85,
P(19) => mul_temp_19_n_86,
P(18) => mul_temp_19_n_87,
P(17) => mul_temp_19_n_88,
P(16) => mul_temp_19_n_89,
P(15) => mul_temp_19_n_90,
P(14) => \^mul_temp_19\(14),
P(13) => mul_temp_19_n_92,
P(12) => mul_temp_19_n_93,
P(11) => mul_temp_19_n_94,
P(10) => mul_temp_19_n_95,
P(9) => mul_temp_19_n_96,
P(8) => mul_temp_19_n_97,
P(7) => mul_temp_19_n_98,
P(6) => mul_temp_19_n_99,
P(5) => mul_temp_19_n_100,
P(4) => mul_temp_19_n_101,
P(3) => mul_temp_19_n_102,
P(2) => mul_temp_19_n_103,
P(1) => mul_temp_19_n_104,
P(0) => mul_temp_19_n_105,
PATTERNBDETECT => NLW_mul_temp_19_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_19_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_19_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_19_UNDERFLOW_UNCONNECTED
);
mul_temp_2: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[2]\(15),
A(28) => \data_pipeline_tmp_reg[2]\(15),
A(27) => \data_pipeline_tmp_reg[2]\(15),
A(26) => \data_pipeline_tmp_reg[2]\(15),
A(25) => \data_pipeline_tmp_reg[2]\(15),
A(24) => \data_pipeline_tmp_reg[2]\(15),
A(23) => \data_pipeline_tmp_reg[2]\(15),
A(22) => \data_pipeline_tmp_reg[2]\(15),
A(21) => \data_pipeline_tmp_reg[2]\(15),
A(20) => \data_pipeline_tmp_reg[2]\(15),
A(19) => \data_pipeline_tmp_reg[2]\(15),
A(18) => \data_pipeline_tmp_reg[2]\(15),
A(17) => \data_pipeline_tmp_reg[2]\(15),
A(16) => \data_pipeline_tmp_reg[2]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[2]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_2_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[2]_1\(15),
B(16) => \weight_reg[2]_1\(15),
B(15 downto 0) => \weight_reg[2]_1\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_2_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_2_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_2_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_2_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_2_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_2_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_2_n_74,
P(30) => mul_temp_2_n_75,
P(29) => mul_temp_2_n_76,
P(28) => mul_temp_2_n_77,
P(27) => mul_temp_2_n_78,
P(26) => mul_temp_2_n_79,
P(25) => mul_temp_2_n_80,
P(24) => mul_temp_2_n_81,
P(23) => mul_temp_2_n_82,
P(22) => mul_temp_2_n_83,
P(21) => mul_temp_2_n_84,
P(20) => mul_temp_2_n_85,
P(19) => mul_temp_2_n_86,
P(18) => mul_temp_2_n_87,
P(17) => mul_temp_2_n_88,
P(16) => mul_temp_2_n_89,
P(15) => mul_temp_2_n_90,
P(14) => \^mul_temp_2\(14),
P(13) => mul_temp_2_n_92,
P(12) => mul_temp_2_n_93,
P(11) => mul_temp_2_n_94,
P(10) => mul_temp_2_n_95,
P(9) => mul_temp_2_n_96,
P(8) => mul_temp_2_n_97,
P(7) => mul_temp_2_n_98,
P(6) => mul_temp_2_n_99,
P(5) => mul_temp_2_n_100,
P(4) => mul_temp_2_n_101,
P(3) => mul_temp_2_n_102,
P(2) => mul_temp_2_n_103,
P(1) => mul_temp_2_n_104,
P(0) => mul_temp_2_n_105,
PATTERNBDETECT => NLW_mul_temp_2_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_2_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_2_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_2_UNDERFLOW_UNCONNECTED
);
mul_temp_20: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_20_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_20_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_20_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_20_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_20_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_20_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_20_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_20_n_74,
P(30) => mul_temp_20_n_75,
P(29) => mul_temp_20_n_76,
P(28) => mul_temp_20_n_77,
P(27) => mul_temp_20_n_78,
P(26) => mul_temp_20_n_79,
P(25) => mul_temp_20_n_80,
P(24) => mul_temp_20_n_81,
P(23) => mul_temp_20_n_82,
P(22) => mul_temp_20_n_83,
P(21) => mul_temp_20_n_84,
P(20) => mul_temp_20_n_85,
P(19) => mul_temp_20_n_86,
P(18) => mul_temp_20_n_87,
P(17) => mul_temp_20_n_88,
P(16) => mul_temp_20_n_89,
P(15) => mul_temp_20_n_90,
P(14) => \^mul_temp_20\(14),
P(13) => mul_temp_20_n_92,
P(12) => mul_temp_20_n_93,
P(11) => mul_temp_20_n_94,
P(10) => mul_temp_20_n_95,
P(9) => mul_temp_20_n_96,
P(8) => mul_temp_20_n_97,
P(7) => mul_temp_20_n_98,
P(6) => mul_temp_20_n_99,
P(5) => mul_temp_20_n_100,
P(4) => mul_temp_20_n_101,
P(3) => mul_temp_20_n_102,
P(2) => mul_temp_20_n_103,
P(1) => mul_temp_20_n_104,
P(0) => mul_temp_20_n_105,
PATTERNBDETECT => NLW_mul_temp_20_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_20_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_20_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_20_UNDERFLOW_UNCONNECTED
);
mul_temp_21: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_21_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_21_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_21_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_21_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_21_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_21_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_21_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_21_n_74,
P(30) => mul_temp_21_n_75,
P(29) => mul_temp_21_n_76,
P(28) => mul_temp_21_n_77,
P(27) => mul_temp_21_n_78,
P(26) => mul_temp_21_n_79,
P(25) => mul_temp_21_n_80,
P(24) => mul_temp_21_n_81,
P(23) => mul_temp_21_n_82,
P(22) => mul_temp_21_n_83,
P(21) => mul_temp_21_n_84,
P(20) => mul_temp_21_n_85,
P(19) => mul_temp_21_n_86,
P(18) => mul_temp_21_n_87,
P(17) => mul_temp_21_n_88,
P(16) => mul_temp_21_n_89,
P(15) => mul_temp_21_n_90,
P(14) => \^mul_temp_21\(14),
P(13) => mul_temp_21_n_92,
P(12) => mul_temp_21_n_93,
P(11) => mul_temp_21_n_94,
P(10) => mul_temp_21_n_95,
P(9) => mul_temp_21_n_96,
P(8) => mul_temp_21_n_97,
P(7) => mul_temp_21_n_98,
P(6) => mul_temp_21_n_99,
P(5) => mul_temp_21_n_100,
P(4) => mul_temp_21_n_101,
P(3) => mul_temp_21_n_102,
P(2) => mul_temp_21_n_103,
P(1) => mul_temp_21_n_104,
P(0) => mul_temp_21_n_105,
PATTERNBDETECT => NLW_mul_temp_21_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_21_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_21_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_21_UNDERFLOW_UNCONNECTED
);
mul_temp_22: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_22_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_22_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_22_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_22_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_22_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_22_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_22_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_22_n_74,
P(30) => mul_temp_22_n_75,
P(29) => mul_temp_22_n_76,
P(28) => mul_temp_22_n_77,
P(27) => mul_temp_22_n_78,
P(26) => mul_temp_22_n_79,
P(25) => mul_temp_22_n_80,
P(24) => mul_temp_22_n_81,
P(23) => mul_temp_22_n_82,
P(22) => mul_temp_22_n_83,
P(21) => mul_temp_22_n_84,
P(20) => mul_temp_22_n_85,
P(19) => mul_temp_22_n_86,
P(18) => mul_temp_22_n_87,
P(17) => mul_temp_22_n_88,
P(16) => mul_temp_22_n_89,
P(15) => mul_temp_22_n_90,
P(14) => \^mul_temp_22\(14),
P(13) => mul_temp_22_n_92,
P(12) => mul_temp_22_n_93,
P(11) => mul_temp_22_n_94,
P(10) => mul_temp_22_n_95,
P(9) => mul_temp_22_n_96,
P(8) => mul_temp_22_n_97,
P(7) => mul_temp_22_n_98,
P(6) => mul_temp_22_n_99,
P(5) => mul_temp_22_n_100,
P(4) => mul_temp_22_n_101,
P(3) => mul_temp_22_n_102,
P(2) => mul_temp_22_n_103,
P(1) => mul_temp_22_n_104,
P(0) => mul_temp_22_n_105,
PATTERNBDETECT => NLW_mul_temp_22_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_22_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_22_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_22_UNDERFLOW_UNCONNECTED
);
mul_temp_23: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_23_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_23_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_23_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_23_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_23_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_23_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_23_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_23_n_74,
P(30) => mul_temp_23_n_75,
P(29) => mul_temp_23_n_76,
P(28) => mul_temp_23_n_77,
P(27) => mul_temp_23_n_78,
P(26) => mul_temp_23_n_79,
P(25) => mul_temp_23_n_80,
P(24) => mul_temp_23_n_81,
P(23) => mul_temp_23_n_82,
P(22) => mul_temp_23_n_83,
P(21) => mul_temp_23_n_84,
P(20) => mul_temp_23_n_85,
P(19) => mul_temp_23_n_86,
P(18) => mul_temp_23_n_87,
P(17) => mul_temp_23_n_88,
P(16) => mul_temp_23_n_89,
P(15) => mul_temp_23_n_90,
P(14) => \^mul_temp_23\(14),
P(13) => mul_temp_23_n_92,
P(12) => mul_temp_23_n_93,
P(11) => mul_temp_23_n_94,
P(10) => mul_temp_23_n_95,
P(9) => mul_temp_23_n_96,
P(8) => mul_temp_23_n_97,
P(7) => mul_temp_23_n_98,
P(6) => mul_temp_23_n_99,
P(5) => mul_temp_23_n_100,
P(4) => mul_temp_23_n_101,
P(3) => mul_temp_23_n_102,
P(2) => mul_temp_23_n_103,
P(1) => mul_temp_23_n_104,
P(0) => mul_temp_23_n_105,
PATTERNBDETECT => NLW_mul_temp_23_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_23_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_23_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_23_UNDERFLOW_UNCONNECTED
);
mul_temp_24: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_24_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_24_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_24_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_24_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_24_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_24_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_24_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_24_n_74,
P(30) => mul_temp_24_n_75,
P(29) => mul_temp_24_n_76,
P(28) => mul_temp_24_n_77,
P(27) => mul_temp_24_n_78,
P(26) => mul_temp_24_n_79,
P(25) => mul_temp_24_n_80,
P(24) => mul_temp_24_n_81,
P(23) => mul_temp_24_n_82,
P(22) => mul_temp_24_n_83,
P(21) => mul_temp_24_n_84,
P(20) => mul_temp_24_n_85,
P(19) => mul_temp_24_n_86,
P(18) => mul_temp_24_n_87,
P(17) => mul_temp_24_n_88,
P(16) => mul_temp_24_n_89,
P(15) => mul_temp_24_n_90,
P(14) => \^mul_temp_24\(14),
P(13) => mul_temp_24_n_92,
P(12) => mul_temp_24_n_93,
P(11) => mul_temp_24_n_94,
P(10) => mul_temp_24_n_95,
P(9) => mul_temp_24_n_96,
P(8) => mul_temp_24_n_97,
P(7) => mul_temp_24_n_98,
P(6) => mul_temp_24_n_99,
P(5) => mul_temp_24_n_100,
P(4) => mul_temp_24_n_101,
P(3) => mul_temp_24_n_102,
P(2) => mul_temp_24_n_103,
P(1) => mul_temp_24_n_104,
P(0) => mul_temp_24_n_105,
PATTERNBDETECT => NLW_mul_temp_24_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_24_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_24_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_24_UNDERFLOW_UNCONNECTED
);
mul_temp_25: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_25_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_25_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_25_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_25_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_25_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_25_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_25_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_25_n_74,
P(30) => mul_temp_25_n_75,
P(29) => mul_temp_25_n_76,
P(28) => mul_temp_25_n_77,
P(27) => mul_temp_25_n_78,
P(26) => mul_temp_25_n_79,
P(25) => mul_temp_25_n_80,
P(24) => mul_temp_25_n_81,
P(23) => mul_temp_25_n_82,
P(22) => mul_temp_25_n_83,
P(21) => mul_temp_25_n_84,
P(20) => mul_temp_25_n_85,
P(19) => mul_temp_25_n_86,
P(18) => mul_temp_25_n_87,
P(17) => mul_temp_25_n_88,
P(16) => mul_temp_25_n_89,
P(15) => mul_temp_25_n_90,
P(14) => \^mul_temp_25\(14),
P(13) => mul_temp_25_n_92,
P(12) => mul_temp_25_n_93,
P(11) => mul_temp_25_n_94,
P(10) => mul_temp_25_n_95,
P(9) => mul_temp_25_n_96,
P(8) => mul_temp_25_n_97,
P(7) => mul_temp_25_n_98,
P(6) => mul_temp_25_n_99,
P(5) => mul_temp_25_n_100,
P(4) => mul_temp_25_n_101,
P(3) => mul_temp_25_n_102,
P(2) => mul_temp_25_n_103,
P(1) => mul_temp_25_n_104,
P(0) => mul_temp_25_n_105,
PATTERNBDETECT => NLW_mul_temp_25_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_25_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_25_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_25_UNDERFLOW_UNCONNECTED
);
mul_temp_26: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_26_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_26_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_26_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_26_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_26_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_26_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_26_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_26_n_74,
P(30) => mul_temp_26_n_75,
P(29) => mul_temp_26_n_76,
P(28) => mul_temp_26_n_77,
P(27) => mul_temp_26_n_78,
P(26) => mul_temp_26_n_79,
P(25) => mul_temp_26_n_80,
P(24) => mul_temp_26_n_81,
P(23) => mul_temp_26_n_82,
P(22) => mul_temp_26_n_83,
P(21) => mul_temp_26_n_84,
P(20) => mul_temp_26_n_85,
P(19) => mul_temp_26_n_86,
P(18) => mul_temp_26_n_87,
P(17) => mul_temp_26_n_88,
P(16) => mul_temp_26_n_89,
P(15) => mul_temp_26_n_90,
P(14) => \^mul_temp_26\(14),
P(13) => mul_temp_26_n_92,
P(12) => mul_temp_26_n_93,
P(11) => mul_temp_26_n_94,
P(10) => mul_temp_26_n_95,
P(9) => mul_temp_26_n_96,
P(8) => mul_temp_26_n_97,
P(7) => mul_temp_26_n_98,
P(6) => mul_temp_26_n_99,
P(5) => mul_temp_26_n_100,
P(4) => mul_temp_26_n_101,
P(3) => mul_temp_26_n_102,
P(2) => mul_temp_26_n_103,
P(1) => mul_temp_26_n_104,
P(0) => mul_temp_26_n_105,
PATTERNBDETECT => NLW_mul_temp_26_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_26_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_26_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_26_UNDERFLOW_UNCONNECTED
);
mul_temp_27: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[10]\(15),
A(28) => \data_pipeline_tmp_reg[10]\(15),
A(27) => \data_pipeline_tmp_reg[10]\(15),
A(26) => \data_pipeline_tmp_reg[10]\(15),
A(25) => \data_pipeline_tmp_reg[10]\(15),
A(24) => \data_pipeline_tmp_reg[10]\(15),
A(23) => \data_pipeline_tmp_reg[10]\(15),
A(22) => \data_pipeline_tmp_reg[10]\(15),
A(21) => \data_pipeline_tmp_reg[10]\(15),
A(20) => \data_pipeline_tmp_reg[10]\(15),
A(19) => \data_pipeline_tmp_reg[10]\(15),
A(18) => \data_pipeline_tmp_reg[10]\(15),
A(17) => \data_pipeline_tmp_reg[10]\(15),
A(16) => \data_pipeline_tmp_reg[10]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[10]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_27_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_27_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_27_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_27_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_27_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_27_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_27_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_27_n_74,
P(30) => mul_temp_27_n_75,
P(29) => mul_temp_27_n_76,
P(28) => mul_temp_27_n_77,
P(27) => mul_temp_27_n_78,
P(26) => mul_temp_27_n_79,
P(25) => mul_temp_27_n_80,
P(24) => mul_temp_27_n_81,
P(23) => mul_temp_27_n_82,
P(22) => mul_temp_27_n_83,
P(21) => mul_temp_27_n_84,
P(20) => mul_temp_27_n_85,
P(19) => mul_temp_27_n_86,
P(18) => mul_temp_27_n_87,
P(17) => mul_temp_27_n_88,
P(16) => mul_temp_27_n_89,
P(15) => mul_temp_27_n_90,
P(14) => \^mul_temp_27\(14),
P(13) => mul_temp_27_n_92,
P(12) => mul_temp_27_n_93,
P(11) => mul_temp_27_n_94,
P(10) => mul_temp_27_n_95,
P(9) => mul_temp_27_n_96,
P(8) => mul_temp_27_n_97,
P(7) => mul_temp_27_n_98,
P(6) => mul_temp_27_n_99,
P(5) => mul_temp_27_n_100,
P(4) => mul_temp_27_n_101,
P(3) => mul_temp_27_n_102,
P(2) => mul_temp_27_n_103,
P(1) => mul_temp_27_n_104,
P(0) => mul_temp_27_n_105,
PATTERNBDETECT => NLW_mul_temp_27_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_27_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_27_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_27_UNDERFLOW_UNCONNECTED
);
mul_temp_28: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[11]\(15),
A(28) => \data_pipeline_tmp_reg[11]\(15),
A(27) => \data_pipeline_tmp_reg[11]\(15),
A(26) => \data_pipeline_tmp_reg[11]\(15),
A(25) => \data_pipeline_tmp_reg[11]\(15),
A(24) => \data_pipeline_tmp_reg[11]\(15),
A(23) => \data_pipeline_tmp_reg[11]\(15),
A(22) => \data_pipeline_tmp_reg[11]\(15),
A(21) => \data_pipeline_tmp_reg[11]\(15),
A(20) => \data_pipeline_tmp_reg[11]\(15),
A(19) => \data_pipeline_tmp_reg[11]\(15),
A(18) => \data_pipeline_tmp_reg[11]\(15),
A(17) => \data_pipeline_tmp_reg[11]\(15),
A(16) => \data_pipeline_tmp_reg[11]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[11]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_28_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_28_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_28_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_28_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_28_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_28_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_28_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_28_n_74,
P(30) => mul_temp_28_n_75,
P(29) => mul_temp_28_n_76,
P(28) => mul_temp_28_n_77,
P(27) => mul_temp_28_n_78,
P(26) => mul_temp_28_n_79,
P(25) => mul_temp_28_n_80,
P(24) => mul_temp_28_n_81,
P(23) => mul_temp_28_n_82,
P(22) => mul_temp_28_n_83,
P(21) => mul_temp_28_n_84,
P(20) => mul_temp_28_n_85,
P(19) => mul_temp_28_n_86,
P(18) => mul_temp_28_n_87,
P(17) => mul_temp_28_n_88,
P(16) => mul_temp_28_n_89,
P(15) => mul_temp_28_n_90,
P(14) => \^mul_temp_28\(14),
P(13) => mul_temp_28_n_92,
P(12) => mul_temp_28_n_93,
P(11) => mul_temp_28_n_94,
P(10) => mul_temp_28_n_95,
P(9) => mul_temp_28_n_96,
P(8) => mul_temp_28_n_97,
P(7) => mul_temp_28_n_98,
P(6) => mul_temp_28_n_99,
P(5) => mul_temp_28_n_100,
P(4) => mul_temp_28_n_101,
P(3) => mul_temp_28_n_102,
P(2) => mul_temp_28_n_103,
P(1) => mul_temp_28_n_104,
P(0) => mul_temp_28_n_105,
PATTERNBDETECT => NLW_mul_temp_28_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_28_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_28_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_28_UNDERFLOW_UNCONNECTED
);
mul_temp_29: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[12]\(15),
A(28) => \data_pipeline_tmp_reg[12]\(15),
A(27) => \data_pipeline_tmp_reg[12]\(15),
A(26) => \data_pipeline_tmp_reg[12]\(15),
A(25) => \data_pipeline_tmp_reg[12]\(15),
A(24) => \data_pipeline_tmp_reg[12]\(15),
A(23) => \data_pipeline_tmp_reg[12]\(15),
A(22) => \data_pipeline_tmp_reg[12]\(15),
A(21) => \data_pipeline_tmp_reg[12]\(15),
A(20) => \data_pipeline_tmp_reg[12]\(15),
A(19) => \data_pipeline_tmp_reg[12]\(15),
A(18) => \data_pipeline_tmp_reg[12]\(15),
A(17) => \data_pipeline_tmp_reg[12]\(15),
A(16) => \data_pipeline_tmp_reg[12]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[12]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_29_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_29_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_29_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_29_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_29_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_29_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_29_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_29_n_74,
P(30) => mul_temp_29_n_75,
P(29) => mul_temp_29_n_76,
P(28) => mul_temp_29_n_77,
P(27) => mul_temp_29_n_78,
P(26) => mul_temp_29_n_79,
P(25) => mul_temp_29_n_80,
P(24) => mul_temp_29_n_81,
P(23) => mul_temp_29_n_82,
P(22) => mul_temp_29_n_83,
P(21) => mul_temp_29_n_84,
P(20) => mul_temp_29_n_85,
P(19) => mul_temp_29_n_86,
P(18) => mul_temp_29_n_87,
P(17) => mul_temp_29_n_88,
P(16) => mul_temp_29_n_89,
P(15) => mul_temp_29_n_90,
P(14) => \^mul_temp_29\(14),
P(13) => mul_temp_29_n_92,
P(12) => mul_temp_29_n_93,
P(11) => mul_temp_29_n_94,
P(10) => mul_temp_29_n_95,
P(9) => mul_temp_29_n_96,
P(8) => mul_temp_29_n_97,
P(7) => mul_temp_29_n_98,
P(6) => mul_temp_29_n_99,
P(5) => mul_temp_29_n_100,
P(4) => mul_temp_29_n_101,
P(3) => mul_temp_29_n_102,
P(2) => mul_temp_29_n_103,
P(1) => mul_temp_29_n_104,
P(0) => mul_temp_29_n_105,
PATTERNBDETECT => NLW_mul_temp_29_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_29_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_29_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_29_UNDERFLOW_UNCONNECTED
);
mul_temp_3: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[3]\(15),
A(28) => \data_pipeline_tmp_reg[3]\(15),
A(27) => \data_pipeline_tmp_reg[3]\(15),
A(26) => \data_pipeline_tmp_reg[3]\(15),
A(25) => \data_pipeline_tmp_reg[3]\(15),
A(24) => \data_pipeline_tmp_reg[3]\(15),
A(23) => \data_pipeline_tmp_reg[3]\(15),
A(22) => \data_pipeline_tmp_reg[3]\(15),
A(21) => \data_pipeline_tmp_reg[3]\(15),
A(20) => \data_pipeline_tmp_reg[3]\(15),
A(19) => \data_pipeline_tmp_reg[3]\(15),
A(18) => \data_pipeline_tmp_reg[3]\(15),
A(17) => \data_pipeline_tmp_reg[3]\(15),
A(16) => \data_pipeline_tmp_reg[3]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[3]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_3_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[3]_2\(15),
B(16) => \weight_reg[3]_2\(15),
B(15 downto 0) => \weight_reg[3]_2\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_3_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_3_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_3_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_3_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_3_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_3_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_3_n_74,
P(30) => mul_temp_3_n_75,
P(29) => mul_temp_3_n_76,
P(28) => mul_temp_3_n_77,
P(27) => mul_temp_3_n_78,
P(26) => mul_temp_3_n_79,
P(25) => mul_temp_3_n_80,
P(24) => mul_temp_3_n_81,
P(23) => mul_temp_3_n_82,
P(22) => mul_temp_3_n_83,
P(21) => mul_temp_3_n_84,
P(20) => mul_temp_3_n_85,
P(19) => mul_temp_3_n_86,
P(18) => mul_temp_3_n_87,
P(17) => mul_temp_3_n_88,
P(16) => mul_temp_3_n_89,
P(15) => mul_temp_3_n_90,
P(14) => \^mul_temp_3\(14),
P(13) => mul_temp_3_n_92,
P(12) => mul_temp_3_n_93,
P(11) => mul_temp_3_n_94,
P(10) => mul_temp_3_n_95,
P(9) => mul_temp_3_n_96,
P(8) => mul_temp_3_n_97,
P(7) => mul_temp_3_n_98,
P(6) => mul_temp_3_n_99,
P(5) => mul_temp_3_n_100,
P(4) => mul_temp_3_n_101,
P(3) => mul_temp_3_n_102,
P(2) => mul_temp_3_n_103,
P(1) => mul_temp_3_n_104,
P(0) => mul_temp_3_n_105,
PATTERNBDETECT => NLW_mul_temp_3_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_3_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_3_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_3_UNDERFLOW_UNCONNECTED
);
mul_temp_30: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[13]\(15),
A(28) => \data_pipeline_tmp_reg[13]\(15),
A(27) => \data_pipeline_tmp_reg[13]\(15),
A(26) => \data_pipeline_tmp_reg[13]\(15),
A(25) => \data_pipeline_tmp_reg[13]\(15),
A(24) => \data_pipeline_tmp_reg[13]\(15),
A(23) => \data_pipeline_tmp_reg[13]\(15),
A(22) => \data_pipeline_tmp_reg[13]\(15),
A(21) => \data_pipeline_tmp_reg[13]\(15),
A(20) => \data_pipeline_tmp_reg[13]\(15),
A(19) => \data_pipeline_tmp_reg[13]\(15),
A(18) => \data_pipeline_tmp_reg[13]\(15),
A(17) => \data_pipeline_tmp_reg[13]\(15),
A(16) => \data_pipeline_tmp_reg[13]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[13]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_30_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_30_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_30_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_30_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_30_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_30_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_30_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_30_n_74,
P(30) => mul_temp_30_n_75,
P(29) => mul_temp_30_n_76,
P(28) => mul_temp_30_n_77,
P(27) => mul_temp_30_n_78,
P(26) => mul_temp_30_n_79,
P(25) => mul_temp_30_n_80,
P(24) => mul_temp_30_n_81,
P(23) => mul_temp_30_n_82,
P(22) => mul_temp_30_n_83,
P(21) => mul_temp_30_n_84,
P(20) => mul_temp_30_n_85,
P(19) => mul_temp_30_n_86,
P(18) => mul_temp_30_n_87,
P(17) => mul_temp_30_n_88,
P(16) => mul_temp_30_n_89,
P(15) => mul_temp_30_n_90,
P(14) => \^mul_temp_30\(14),
P(13) => mul_temp_30_n_92,
P(12) => mul_temp_30_n_93,
P(11) => mul_temp_30_n_94,
P(10) => mul_temp_30_n_95,
P(9) => mul_temp_30_n_96,
P(8) => mul_temp_30_n_97,
P(7) => mul_temp_30_n_98,
P(6) => mul_temp_30_n_99,
P(5) => mul_temp_30_n_100,
P(4) => mul_temp_30_n_101,
P(3) => mul_temp_30_n_102,
P(2) => mul_temp_30_n_103,
P(1) => mul_temp_30_n_104,
P(0) => mul_temp_30_n_105,
PATTERNBDETECT => NLW_mul_temp_30_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_30_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_30_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_30_UNDERFLOW_UNCONNECTED
);
mul_temp_31: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[14]\(15),
A(28) => \data_pipeline_tmp_reg[14]\(15),
A(27) => \data_pipeline_tmp_reg[14]\(15),
A(26) => \data_pipeline_tmp_reg[14]\(15),
A(25) => \data_pipeline_tmp_reg[14]\(15),
A(24) => \data_pipeline_tmp_reg[14]\(15),
A(23) => \data_pipeline_tmp_reg[14]\(15),
A(22) => \data_pipeline_tmp_reg[14]\(15),
A(21) => \data_pipeline_tmp_reg[14]\(15),
A(20) => \data_pipeline_tmp_reg[14]\(15),
A(19) => \data_pipeline_tmp_reg[14]\(15),
A(18) => \data_pipeline_tmp_reg[14]\(15),
A(17) => \data_pipeline_tmp_reg[14]\(15),
A(16) => \data_pipeline_tmp_reg[14]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[14]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_31_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_31_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_31_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_31_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_31_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_31_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_31_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_31_n_74,
P(30) => mul_temp_31_n_75,
P(29) => mul_temp_31_n_76,
P(28) => mul_temp_31_n_77,
P(27) => mul_temp_31_n_78,
P(26) => mul_temp_31_n_79,
P(25) => mul_temp_31_n_80,
P(24) => mul_temp_31_n_81,
P(23) => mul_temp_31_n_82,
P(22) => mul_temp_31_n_83,
P(21) => mul_temp_31_n_84,
P(20) => mul_temp_31_n_85,
P(19) => mul_temp_31_n_86,
P(18) => mul_temp_31_n_87,
P(17) => mul_temp_31_n_88,
P(16) => mul_temp_31_n_89,
P(15) => mul_temp_31_n_90,
P(14) => \^mul_temp_31\(14),
P(13) => mul_temp_31_n_92,
P(12) => mul_temp_31_n_93,
P(11) => mul_temp_31_n_94,
P(10) => mul_temp_31_n_95,
P(9) => mul_temp_31_n_96,
P(8) => mul_temp_31_n_97,
P(7) => mul_temp_31_n_98,
P(6) => mul_temp_31_n_99,
P(5) => mul_temp_31_n_100,
P(4) => mul_temp_31_n_101,
P(3) => mul_temp_31_n_102,
P(2) => mul_temp_31_n_103,
P(1) => mul_temp_31_n_104,
P(0) => mul_temp_31_n_105,
PATTERNBDETECT => NLW_mul_temp_31_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_31_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_31_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_31_UNDERFLOW_UNCONNECTED
);
mul_temp_32: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \write_reg_x_k_reg[15]\(15),
A(28) => \write_reg_x_k_reg[15]\(15),
A(27) => \write_reg_x_k_reg[15]\(15),
A(26) => \write_reg_x_k_reg[15]\(15),
A(25) => \write_reg_x_k_reg[15]\(15),
A(24) => \write_reg_x_k_reg[15]\(15),
A(23) => \write_reg_x_k_reg[15]\(15),
A(22) => \write_reg_x_k_reg[15]\(15),
A(21) => \write_reg_x_k_reg[15]\(15),
A(20) => \write_reg_x_k_reg[15]\(15),
A(19) => \write_reg_x_k_reg[15]\(15),
A(18) => \write_reg_x_k_reg[15]\(15),
A(17) => \write_reg_x_k_reg[15]\(15),
A(16) => \write_reg_x_k_reg[15]\(15),
A(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_32_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \ARG__31\(32),
B(16) => \ARG__31\(32),
B(15) => \ARG__31\(32),
B(14) => \ARG__31\(32),
B(13) => \ARG__31\(32),
B(12 downto 0) => \ARG__31\(29 downto 17),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_32_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_32_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_32_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_32_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_32_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_32_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_32_n_74,
P(30) => mul_temp_32_n_75,
P(29) => mul_temp_32_n_76,
P(28) => mul_temp_32_n_77,
P(27) => mul_temp_32_n_78,
P(26) => mul_temp_32_n_79,
P(25) => mul_temp_32_n_80,
P(24) => mul_temp_32_n_81,
P(23) => mul_temp_32_n_82,
P(22) => mul_temp_32_n_83,
P(21) => mul_temp_32_n_84,
P(20) => mul_temp_32_n_85,
P(19) => mul_temp_32_n_86,
P(18) => mul_temp_32_n_87,
P(17) => mul_temp_32_n_88,
P(16) => mul_temp_32_n_89,
P(15) => mul_temp_32_n_90,
P(14) => \^mul_temp_32\(14),
P(13) => mul_temp_32_n_92,
P(12) => mul_temp_32_n_93,
P(11) => mul_temp_32_n_94,
P(10) => mul_temp_32_n_95,
P(9) => mul_temp_32_n_96,
P(8) => mul_temp_32_n_97,
P(7) => mul_temp_32_n_98,
P(6) => mul_temp_32_n_99,
P(5) => mul_temp_32_n_100,
P(4) => mul_temp_32_n_101,
P(3) => mul_temp_32_n_102,
P(2) => mul_temp_32_n_103,
P(1) => mul_temp_32_n_104,
P(0) => mul_temp_32_n_105,
PATTERNBDETECT => NLW_mul_temp_32_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_32_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_32_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_32_UNDERFLOW_UNCONNECTED
);
mul_temp_4: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[4]\(15),
A(28) => \data_pipeline_tmp_reg[4]\(15),
A(27) => \data_pipeline_tmp_reg[4]\(15),
A(26) => \data_pipeline_tmp_reg[4]\(15),
A(25) => \data_pipeline_tmp_reg[4]\(15),
A(24) => \data_pipeline_tmp_reg[4]\(15),
A(23) => \data_pipeline_tmp_reg[4]\(15),
A(22) => \data_pipeline_tmp_reg[4]\(15),
A(21) => \data_pipeline_tmp_reg[4]\(15),
A(20) => \data_pipeline_tmp_reg[4]\(15),
A(19) => \data_pipeline_tmp_reg[4]\(15),
A(18) => \data_pipeline_tmp_reg[4]\(15),
A(17) => \data_pipeline_tmp_reg[4]\(15),
A(16) => \data_pipeline_tmp_reg[4]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[4]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_4_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[4]_3\(15),
B(16) => \weight_reg[4]_3\(15),
B(15 downto 0) => \weight_reg[4]_3\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_4_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_4_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_4_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_4_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_4_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_4_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_4_n_74,
P(30) => mul_temp_4_n_75,
P(29) => mul_temp_4_n_76,
P(28) => mul_temp_4_n_77,
P(27) => mul_temp_4_n_78,
P(26) => mul_temp_4_n_79,
P(25) => mul_temp_4_n_80,
P(24) => mul_temp_4_n_81,
P(23) => mul_temp_4_n_82,
P(22) => mul_temp_4_n_83,
P(21) => mul_temp_4_n_84,
P(20) => mul_temp_4_n_85,
P(19) => mul_temp_4_n_86,
P(18) => mul_temp_4_n_87,
P(17) => mul_temp_4_n_88,
P(16) => mul_temp_4_n_89,
P(15) => mul_temp_4_n_90,
P(14) => \^mul_temp_4\(14),
P(13) => mul_temp_4_n_92,
P(12) => mul_temp_4_n_93,
P(11) => mul_temp_4_n_94,
P(10) => mul_temp_4_n_95,
P(9) => mul_temp_4_n_96,
P(8) => mul_temp_4_n_97,
P(7) => mul_temp_4_n_98,
P(6) => mul_temp_4_n_99,
P(5) => mul_temp_4_n_100,
P(4) => mul_temp_4_n_101,
P(3) => mul_temp_4_n_102,
P(2) => mul_temp_4_n_103,
P(1) => mul_temp_4_n_104,
P(0) => mul_temp_4_n_105,
PATTERNBDETECT => NLW_mul_temp_4_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_4_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_4_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_4_UNDERFLOW_UNCONNECTED
);
mul_temp_5: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[5]\(15),
A(28) => \data_pipeline_tmp_reg[5]\(15),
A(27) => \data_pipeline_tmp_reg[5]\(15),
A(26) => \data_pipeline_tmp_reg[5]\(15),
A(25) => \data_pipeline_tmp_reg[5]\(15),
A(24) => \data_pipeline_tmp_reg[5]\(15),
A(23) => \data_pipeline_tmp_reg[5]\(15),
A(22) => \data_pipeline_tmp_reg[5]\(15),
A(21) => \data_pipeline_tmp_reg[5]\(15),
A(20) => \data_pipeline_tmp_reg[5]\(15),
A(19) => \data_pipeline_tmp_reg[5]\(15),
A(18) => \data_pipeline_tmp_reg[5]\(15),
A(17) => \data_pipeline_tmp_reg[5]\(15),
A(16) => \data_pipeline_tmp_reg[5]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[5]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_5_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[5]_4\(15),
B(16) => \weight_reg[5]_4\(15),
B(15 downto 0) => \weight_reg[5]_4\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_5_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_5_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_5_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_5_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_5_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_5_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_5_n_74,
P(30) => mul_temp_5_n_75,
P(29) => mul_temp_5_n_76,
P(28) => mul_temp_5_n_77,
P(27) => mul_temp_5_n_78,
P(26) => mul_temp_5_n_79,
P(25) => mul_temp_5_n_80,
P(24) => mul_temp_5_n_81,
P(23) => mul_temp_5_n_82,
P(22) => mul_temp_5_n_83,
P(21) => mul_temp_5_n_84,
P(20) => mul_temp_5_n_85,
P(19) => mul_temp_5_n_86,
P(18) => mul_temp_5_n_87,
P(17) => mul_temp_5_n_88,
P(16) => mul_temp_5_n_89,
P(15) => mul_temp_5_n_90,
P(14) => \^mul_temp_5\(14),
P(13) => mul_temp_5_n_92,
P(12) => mul_temp_5_n_93,
P(11) => mul_temp_5_n_94,
P(10) => mul_temp_5_n_95,
P(9) => mul_temp_5_n_96,
P(8) => mul_temp_5_n_97,
P(7) => mul_temp_5_n_98,
P(6) => mul_temp_5_n_99,
P(5) => mul_temp_5_n_100,
P(4) => mul_temp_5_n_101,
P(3) => mul_temp_5_n_102,
P(2) => mul_temp_5_n_103,
P(1) => mul_temp_5_n_104,
P(0) => mul_temp_5_n_105,
PATTERNBDETECT => NLW_mul_temp_5_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_5_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_5_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_5_UNDERFLOW_UNCONNECTED
);
mul_temp_6: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[6]\(15),
A(28) => \data_pipeline_tmp_reg[6]\(15),
A(27) => \data_pipeline_tmp_reg[6]\(15),
A(26) => \data_pipeline_tmp_reg[6]\(15),
A(25) => \data_pipeline_tmp_reg[6]\(15),
A(24) => \data_pipeline_tmp_reg[6]\(15),
A(23) => \data_pipeline_tmp_reg[6]\(15),
A(22) => \data_pipeline_tmp_reg[6]\(15),
A(21) => \data_pipeline_tmp_reg[6]\(15),
A(20) => \data_pipeline_tmp_reg[6]\(15),
A(19) => \data_pipeline_tmp_reg[6]\(15),
A(18) => \data_pipeline_tmp_reg[6]\(15),
A(17) => \data_pipeline_tmp_reg[6]\(15),
A(16) => \data_pipeline_tmp_reg[6]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[6]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_6_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[6]_5\(15),
B(16) => \weight_reg[6]_5\(15),
B(15 downto 0) => \weight_reg[6]_5\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_6_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_6_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_6_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_6_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_6_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_6_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_6_n_74,
P(30) => mul_temp_6_n_75,
P(29) => mul_temp_6_n_76,
P(28) => mul_temp_6_n_77,
P(27) => mul_temp_6_n_78,
P(26) => mul_temp_6_n_79,
P(25) => mul_temp_6_n_80,
P(24) => mul_temp_6_n_81,
P(23) => mul_temp_6_n_82,
P(22) => mul_temp_6_n_83,
P(21) => mul_temp_6_n_84,
P(20) => mul_temp_6_n_85,
P(19) => mul_temp_6_n_86,
P(18) => mul_temp_6_n_87,
P(17) => mul_temp_6_n_88,
P(16) => mul_temp_6_n_89,
P(15) => mul_temp_6_n_90,
P(14) => \^mul_temp_6\(14),
P(13) => mul_temp_6_n_92,
P(12) => mul_temp_6_n_93,
P(11) => mul_temp_6_n_94,
P(10) => mul_temp_6_n_95,
P(9) => mul_temp_6_n_96,
P(8) => mul_temp_6_n_97,
P(7) => mul_temp_6_n_98,
P(6) => mul_temp_6_n_99,
P(5) => mul_temp_6_n_100,
P(4) => mul_temp_6_n_101,
P(3) => mul_temp_6_n_102,
P(2) => mul_temp_6_n_103,
P(1) => mul_temp_6_n_104,
P(0) => mul_temp_6_n_105,
PATTERNBDETECT => NLW_mul_temp_6_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_6_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_6_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_6_UNDERFLOW_UNCONNECTED
);
mul_temp_7: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[7]\(15),
A(28) => \data_pipeline_tmp_reg[7]\(15),
A(27) => \data_pipeline_tmp_reg[7]\(15),
A(26) => \data_pipeline_tmp_reg[7]\(15),
A(25) => \data_pipeline_tmp_reg[7]\(15),
A(24) => \data_pipeline_tmp_reg[7]\(15),
A(23) => \data_pipeline_tmp_reg[7]\(15),
A(22) => \data_pipeline_tmp_reg[7]\(15),
A(21) => \data_pipeline_tmp_reg[7]\(15),
A(20) => \data_pipeline_tmp_reg[7]\(15),
A(19) => \data_pipeline_tmp_reg[7]\(15),
A(18) => \data_pipeline_tmp_reg[7]\(15),
A(17) => \data_pipeline_tmp_reg[7]\(15),
A(16) => \data_pipeline_tmp_reg[7]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[7]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_7_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[7]_6\(15),
B(16) => \weight_reg[7]_6\(15),
B(15 downto 0) => \weight_reg[7]_6\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_7_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_7_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_7_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_7_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_7_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_7_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_7_n_74,
P(30) => mul_temp_7_n_75,
P(29) => mul_temp_7_n_76,
P(28) => mul_temp_7_n_77,
P(27) => mul_temp_7_n_78,
P(26) => mul_temp_7_n_79,
P(25) => mul_temp_7_n_80,
P(24) => mul_temp_7_n_81,
P(23) => mul_temp_7_n_82,
P(22) => mul_temp_7_n_83,
P(21) => mul_temp_7_n_84,
P(20) => mul_temp_7_n_85,
P(19) => mul_temp_7_n_86,
P(18) => mul_temp_7_n_87,
P(17) => mul_temp_7_n_88,
P(16) => mul_temp_7_n_89,
P(15) => mul_temp_7_n_90,
P(14) => \^mul_temp_7\(14),
P(13) => mul_temp_7_n_92,
P(12) => mul_temp_7_n_93,
P(11) => mul_temp_7_n_94,
P(10) => mul_temp_7_n_95,
P(9) => mul_temp_7_n_96,
P(8) => mul_temp_7_n_97,
P(7) => mul_temp_7_n_98,
P(6) => mul_temp_7_n_99,
P(5) => mul_temp_7_n_100,
P(4) => mul_temp_7_n_101,
P(3) => mul_temp_7_n_102,
P(2) => mul_temp_7_n_103,
P(1) => mul_temp_7_n_104,
P(0) => mul_temp_7_n_105,
PATTERNBDETECT => NLW_mul_temp_7_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_7_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_7_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_7_UNDERFLOW_UNCONNECTED
);
mul_temp_8: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[8]\(15),
A(28) => \data_pipeline_tmp_reg[8]\(15),
A(27) => \data_pipeline_tmp_reg[8]\(15),
A(26) => \data_pipeline_tmp_reg[8]\(15),
A(25) => \data_pipeline_tmp_reg[8]\(15),
A(24) => \data_pipeline_tmp_reg[8]\(15),
A(23) => \data_pipeline_tmp_reg[8]\(15),
A(22) => \data_pipeline_tmp_reg[8]\(15),
A(21) => \data_pipeline_tmp_reg[8]\(15),
A(20) => \data_pipeline_tmp_reg[8]\(15),
A(19) => \data_pipeline_tmp_reg[8]\(15),
A(18) => \data_pipeline_tmp_reg[8]\(15),
A(17) => \data_pipeline_tmp_reg[8]\(15),
A(16) => \data_pipeline_tmp_reg[8]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[8]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_8_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[8]_7\(15),
B(16) => \weight_reg[8]_7\(15),
B(15 downto 0) => \weight_reg[8]_7\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_8_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_8_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_8_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_8_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_8_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_8_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_8_n_74,
P(30) => mul_temp_8_n_75,
P(29) => mul_temp_8_n_76,
P(28) => mul_temp_8_n_77,
P(27) => mul_temp_8_n_78,
P(26) => mul_temp_8_n_79,
P(25) => mul_temp_8_n_80,
P(24) => mul_temp_8_n_81,
P(23) => mul_temp_8_n_82,
P(22) => mul_temp_8_n_83,
P(21) => mul_temp_8_n_84,
P(20) => mul_temp_8_n_85,
P(19) => mul_temp_8_n_86,
P(18) => mul_temp_8_n_87,
P(17) => mul_temp_8_n_88,
P(16) => mul_temp_8_n_89,
P(15) => mul_temp_8_n_90,
P(14) => \^mul_temp_8\(14),
P(13) => mul_temp_8_n_92,
P(12) => mul_temp_8_n_93,
P(11) => mul_temp_8_n_94,
P(10) => mul_temp_8_n_95,
P(9) => mul_temp_8_n_96,
P(8) => mul_temp_8_n_97,
P(7) => mul_temp_8_n_98,
P(6) => mul_temp_8_n_99,
P(5) => mul_temp_8_n_100,
P(4) => mul_temp_8_n_101,
P(3) => mul_temp_8_n_102,
P(2) => mul_temp_8_n_103,
P(1) => mul_temp_8_n_104,
P(0) => mul_temp_8_n_105,
PATTERNBDETECT => NLW_mul_temp_8_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_8_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_8_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_8_UNDERFLOW_UNCONNECTED
);
mul_temp_9: unisim.vcomponents.DSP48E1
generic map(
ACASCREG => 0,
ADREG => 1,
ALUMODEREG => 0,
AREG => 0,
AUTORESET_PATDET => "NO_RESET",
A_INPUT => "DIRECT",
BCASCREG => 0,
BREG => 0,
B_INPUT => "DIRECT",
CARRYINREG => 0,
CARRYINSELREG => 0,
CREG => 1,
DREG => 1,
INMODEREG => 0,
MASK => X"3FFFFFFFFFFF",
MREG => 0,
OPMODEREG => 0,
PATTERN => X"000000000000",
PREG => 0,
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_DPORT => false,
USE_MULT => "MULTIPLY",
USE_PATTERN_DETECT => "NO_PATDET",
USE_SIMD => "ONE48"
)
port map (
A(29) => \data_pipeline_tmp_reg[9]\(15),
A(28) => \data_pipeline_tmp_reg[9]\(15),
A(27) => \data_pipeline_tmp_reg[9]\(15),
A(26) => \data_pipeline_tmp_reg[9]\(15),
A(25) => \data_pipeline_tmp_reg[9]\(15),
A(24) => \data_pipeline_tmp_reg[9]\(15),
A(23) => \data_pipeline_tmp_reg[9]\(15),
A(22) => \data_pipeline_tmp_reg[9]\(15),
A(21) => \data_pipeline_tmp_reg[9]\(15),
A(20) => \data_pipeline_tmp_reg[9]\(15),
A(19) => \data_pipeline_tmp_reg[9]\(15),
A(18) => \data_pipeline_tmp_reg[9]\(15),
A(17) => \data_pipeline_tmp_reg[9]\(15),
A(16) => \data_pipeline_tmp_reg[9]\(15),
A(15 downto 0) => \data_pipeline_tmp_reg[9]\(15 downto 0),
ACIN(29 downto 0) => B"000000000000000000000000000000",
ACOUT(29 downto 0) => NLW_mul_temp_9_ACOUT_UNCONNECTED(29 downto 0),
ALUMODE(3 downto 0) => B"0000",
B(17) => \weight_reg[9]_8\(15),
B(16) => \weight_reg[9]_8\(15),
B(15 downto 0) => \weight_reg[9]_8\(15 downto 0),
BCIN(17 downto 0) => B"000000000000000000",
BCOUT(17 downto 0) => NLW_mul_temp_9_BCOUT_UNCONNECTED(17 downto 0),
C(47 downto 0) => B"111111111111111111111111111111111111111111111111",
CARRYCASCIN => '0',
CARRYCASCOUT => NLW_mul_temp_9_CARRYCASCOUT_UNCONNECTED,
CARRYIN => '0',
CARRYINSEL(2 downto 0) => B"000",
CARRYOUT(3 downto 0) => NLW_mul_temp_9_CARRYOUT_UNCONNECTED(3 downto 0),
CEA1 => '0',
CEA2 => '0',
CEAD => '0',
CEALUMODE => '0',
CEB1 => '0',
CEB2 => '0',
CEC => '0',
CECARRYIN => '0',
CECTRL => '0',
CED => '0',
CEINMODE => '0',
CEM => '0',
CEP => '0',
CLK => '0',
D(24 downto 0) => B"0000000000000000000000000",
INMODE(4 downto 0) => B"00000",
MULTSIGNIN => '0',
MULTSIGNOUT => NLW_mul_temp_9_MULTSIGNOUT_UNCONNECTED,
OPMODE(6 downto 0) => B"0000101",
OVERFLOW => NLW_mul_temp_9_OVERFLOW_UNCONNECTED,
P(47 downto 32) => NLW_mul_temp_9_P_UNCONNECTED(47 downto 32),
P(31) => mul_temp_9_n_74,
P(30) => mul_temp_9_n_75,
P(29) => mul_temp_9_n_76,
P(28) => mul_temp_9_n_77,
P(27) => mul_temp_9_n_78,
P(26) => mul_temp_9_n_79,
P(25) => mul_temp_9_n_80,
P(24) => mul_temp_9_n_81,
P(23) => mul_temp_9_n_82,
P(22) => mul_temp_9_n_83,
P(21) => mul_temp_9_n_84,
P(20) => mul_temp_9_n_85,
P(19) => mul_temp_9_n_86,
P(18) => mul_temp_9_n_87,
P(17) => mul_temp_9_n_88,
P(16) => mul_temp_9_n_89,
P(15) => mul_temp_9_n_90,
P(14) => \^mul_temp_9\(14),
P(13) => mul_temp_9_n_92,
P(12) => mul_temp_9_n_93,
P(11) => mul_temp_9_n_94,
P(10) => mul_temp_9_n_95,
P(9) => mul_temp_9_n_96,
P(8) => mul_temp_9_n_97,
P(7) => mul_temp_9_n_98,
P(6) => mul_temp_9_n_99,
P(5) => mul_temp_9_n_100,
P(4) => mul_temp_9_n_101,
P(3) => mul_temp_9_n_102,
P(2) => mul_temp_9_n_103,
P(1) => mul_temp_9_n_104,
P(0) => mul_temp_9_n_105,
PATTERNBDETECT => NLW_mul_temp_9_PATTERNBDETECT_UNCONNECTED,
PATTERNDETECT => NLW_mul_temp_9_PATTERNDETECT_UNCONNECTED,
PCIN(47 downto 0) => B"000000000000000000000000000000000000000000000000",
PCOUT(47 downto 0) => NLW_mul_temp_9_PCOUT_UNCONNECTED(47 downto 0),
RSTA => '0',
RSTALLCARRYIN => '0',
RSTALUMODE => '0',
RSTB => '0',
RSTC => '0',
RSTCTRL => '0',
RSTD => '0',
RSTINMODE => '0',
RSTM => '0',
RSTP => '0',
UNDERFLOW => NLW_mul_temp_9_UNDERFLOW_UNCONNECTED
);
sub_temp_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => sub_temp_carry_n_0,
CO(2) => sub_temp_carry_n_1,
CO(1) => sub_temp_carry_n_2,
CO(0) => sub_temp_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => Q(3 downto 0),
O(3 downto 0) => \^mul_temp_16\(3 downto 0),
S(3 downto 0) => \write_reg_d_k_reg[3]_0\(3 downto 0)
);
\sub_temp_carry__0\: unisim.vcomponents.CARRY4
port map (
CI => sub_temp_carry_n_0,
CO(3) => \sub_temp_carry__0_n_0\,
CO(2) => \sub_temp_carry__0_n_1\,
CO(1) => \sub_temp_carry__0_n_2\,
CO(0) => \sub_temp_carry__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(7 downto 4),
O(3 downto 0) => \^mul_temp_16\(7 downto 4),
S(3 downto 0) => \write_reg_d_k_reg[7]\(3 downto 0)
);
\sub_temp_carry__1\: unisim.vcomponents.CARRY4
port map (
CI => \sub_temp_carry__0_n_0\,
CO(3) => \sub_temp_carry__1_n_0\,
CO(2) => \sub_temp_carry__1_n_1\,
CO(1) => \sub_temp_carry__1_n_2\,
CO(0) => \sub_temp_carry__1_n_3\,
CYINIT => '0',
DI(3 downto 0) => Q(11 downto 8),
O(3 downto 0) => \^mul_temp_16\(11 downto 8),
S(3 downto 0) => \write_reg_d_k_reg[11]\(3 downto 0)
);
\sub_temp_carry__2\: unisim.vcomponents.CARRY4
port map (
CI => \sub_temp_carry__1_n_0\,
CO(3) => \NLW_sub_temp_carry__2_CO_UNCONNECTED\(3),
CO(2) => \sub_temp_carry__2_n_1\,
CO(1) => \sub_temp_carry__2_n_2\,
CO(0) => \sub_temp_carry__2_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => Q(14 downto 12),
O(3 downto 0) => \^mul_temp_16\(15 downto 12),
S(3 downto 0) => S(3 downto 0)
);
\weight[0][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_88\,
I1 => \weight_reg[0]_15\(3),
O => \weight[0][0]_i_2_n_0\
);
\weight[0][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_89\,
I1 => \weight_reg[0]_15\(2),
O => \weight[0][0]_i_3_n_0\
);
\weight[0][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_90\,
I1 => \weight_reg[0]_15\(1),
O => \weight[0][0]_i_4_n_0\
);
\weight[0][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_91\,
I1 => \weight_reg[0]_15\(0),
O => \weight[0][0]_i_5_n_0\
);
\weight[0][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_76\,
I1 => \weight_reg[0]_15\(15),
O => \weight[0][12]_i_2_n_0\
);
\weight[0][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_77\,
I1 => \weight_reg[0]_15\(14),
O => \weight[0][12]_i_3_n_0\
);
\weight[0][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_78\,
I1 => \weight_reg[0]_15\(13),
O => \weight[0][12]_i_4_n_0\
);
\weight[0][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_79\,
I1 => \weight_reg[0]_15\(12),
O => \weight[0][12]_i_5_n_0\
);
\weight[0][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_84\,
I1 => \weight_reg[0]_15\(7),
O => \weight[0][4]_i_2_n_0\
);
\weight[0][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_85\,
I1 => \weight_reg[0]_15\(6),
O => \weight[0][4]_i_3_n_0\
);
\weight[0][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_86\,
I1 => \weight_reg[0]_15\(5),
O => \weight[0][4]_i_4_n_0\
);
\weight[0][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_87\,
I1 => \weight_reg[0]_15\(4),
O => \weight[0][4]_i_5_n_0\
);
\weight[0][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_80\,
I1 => \weight_reg[0]_15\(11),
O => \weight[0][8]_i_2_n_0\
);
\weight[0][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_81\,
I1 => \weight_reg[0]_15\(10),
O => \weight[0][8]_i_3_n_0\
);
\weight[0][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_82\,
I1 => \weight_reg[0]_15\(9),
O => \weight[0][8]_i_4_n_0\
);
\weight[0][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__29_n_83\,
I1 => \weight_reg[0]_15\(8),
O => \weight[0][8]_i_5_n_0\
);
\weight[10][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_88\,
I1 => \weight_reg[10]_9\(3),
O => \weight[10][0]_i_2_n_0\
);
\weight[10][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_89\,
I1 => \weight_reg[10]_9\(2),
O => \weight[10][0]_i_3_n_0\
);
\weight[10][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_90\,
I1 => \weight_reg[10]_9\(1),
O => \weight[10][0]_i_4_n_0\
);
\weight[10][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_91\,
I1 => \weight_reg[10]_9\(0),
O => \weight[10][0]_i_5_n_0\
);
\weight[10][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_76\,
I1 => \weight_reg[10]_9\(15),
O => \weight[10][12]_i_2_n_0\
);
\weight[10][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_77\,
I1 => \weight_reg[10]_9\(14),
O => \weight[10][12]_i_3_n_0\
);
\weight[10][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_78\,
I1 => \weight_reg[10]_9\(13),
O => \weight[10][12]_i_4_n_0\
);
\weight[10][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_79\,
I1 => \weight_reg[10]_9\(12),
O => \weight[10][12]_i_5_n_0\
);
\weight[10][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_84\,
I1 => \weight_reg[10]_9\(7),
O => \weight[10][4]_i_2_n_0\
);
\weight[10][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_85\,
I1 => \weight_reg[10]_9\(6),
O => \weight[10][4]_i_3_n_0\
);
\weight[10][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_86\,
I1 => \weight_reg[10]_9\(5),
O => \weight[10][4]_i_4_n_0\
);
\weight[10][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_87\,
I1 => \weight_reg[10]_9\(4),
O => \weight[10][4]_i_5_n_0\
);
\weight[10][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_80\,
I1 => \weight_reg[10]_9\(11),
O => \weight[10][8]_i_2_n_0\
);
\weight[10][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_81\,
I1 => \weight_reg[10]_9\(10),
O => \weight[10][8]_i_3_n_0\
);
\weight[10][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_82\,
I1 => \weight_reg[10]_9\(9),
O => \weight[10][8]_i_4_n_0\
);
\weight[10][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__17_n_83\,
I1 => \weight_reg[10]_9\(8),
O => \weight[10][8]_i_5_n_0\
);
\weight[11][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_88\,
I1 => \weight_reg[11]_10\(3),
O => \weight[11][0]_i_2_n_0\
);
\weight[11][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_89\,
I1 => \weight_reg[11]_10\(2),
O => \weight[11][0]_i_3_n_0\
);
\weight[11][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_90\,
I1 => \weight_reg[11]_10\(1),
O => \weight[11][0]_i_4_n_0\
);
\weight[11][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_91\,
I1 => \weight_reg[11]_10\(0),
O => \weight[11][0]_i_5_n_0\
);
\weight[11][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_76\,
I1 => \weight_reg[11]_10\(15),
O => \weight[11][12]_i_2_n_0\
);
\weight[11][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_77\,
I1 => \weight_reg[11]_10\(14),
O => \weight[11][12]_i_3_n_0\
);
\weight[11][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_78\,
I1 => \weight_reg[11]_10\(13),
O => \weight[11][12]_i_4_n_0\
);
\weight[11][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_79\,
I1 => \weight_reg[11]_10\(12),
O => \weight[11][12]_i_5_n_0\
);
\weight[11][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_84\,
I1 => \weight_reg[11]_10\(7),
O => \weight[11][4]_i_2_n_0\
);
\weight[11][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_85\,
I1 => \weight_reg[11]_10\(6),
O => \weight[11][4]_i_3_n_0\
);
\weight[11][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_86\,
I1 => \weight_reg[11]_10\(5),
O => \weight[11][4]_i_4_n_0\
);
\weight[11][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_87\,
I1 => \weight_reg[11]_10\(4),
O => \weight[11][4]_i_5_n_0\
);
\weight[11][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_80\,
I1 => \weight_reg[11]_10\(11),
O => \weight[11][8]_i_2_n_0\
);
\weight[11][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_81\,
I1 => \weight_reg[11]_10\(10),
O => \weight[11][8]_i_3_n_0\
);
\weight[11][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_82\,
I1 => \weight_reg[11]_10\(9),
O => \weight[11][8]_i_4_n_0\
);
\weight[11][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__19_n_83\,
I1 => \weight_reg[11]_10\(8),
O => \weight[11][8]_i_5_n_0\
);
\weight[12][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_88\,
I1 => \weight_reg[12]_11\(3),
O => \weight[12][0]_i_2_n_0\
);
\weight[12][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_89\,
I1 => \weight_reg[12]_11\(2),
O => \weight[12][0]_i_3_n_0\
);
\weight[12][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_90\,
I1 => \weight_reg[12]_11\(1),
O => \weight[12][0]_i_4_n_0\
);
\weight[12][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_91\,
I1 => \weight_reg[12]_11\(0),
O => \weight[12][0]_i_5_n_0\
);
\weight[12][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_76\,
I1 => \weight_reg[12]_11\(15),
O => \weight[12][12]_i_2_n_0\
);
\weight[12][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_77\,
I1 => \weight_reg[12]_11\(14),
O => \weight[12][12]_i_3_n_0\
);
\weight[12][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_78\,
I1 => \weight_reg[12]_11\(13),
O => \weight[12][12]_i_4_n_0\
);
\weight[12][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_79\,
I1 => \weight_reg[12]_11\(12),
O => \weight[12][12]_i_5_n_0\
);
\weight[12][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_84\,
I1 => \weight_reg[12]_11\(7),
O => \weight[12][4]_i_2_n_0\
);
\weight[12][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_85\,
I1 => \weight_reg[12]_11\(6),
O => \weight[12][4]_i_3_n_0\
);
\weight[12][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_86\,
I1 => \weight_reg[12]_11\(5),
O => \weight[12][4]_i_4_n_0\
);
\weight[12][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_87\,
I1 => \weight_reg[12]_11\(4),
O => \weight[12][4]_i_5_n_0\
);
\weight[12][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_80\,
I1 => \weight_reg[12]_11\(11),
O => \weight[12][8]_i_2_n_0\
);
\weight[12][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_81\,
I1 => \weight_reg[12]_11\(10),
O => \weight[12][8]_i_3_n_0\
);
\weight[12][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_82\,
I1 => \weight_reg[12]_11\(9),
O => \weight[12][8]_i_4_n_0\
);
\weight[12][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__21_n_83\,
I1 => \weight_reg[12]_11\(8),
O => \weight[12][8]_i_5_n_0\
);
\weight[13][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_88\,
I1 => \weight_reg[13]_12\(3),
O => \weight[13][0]_i_2_n_0\
);
\weight[13][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_89\,
I1 => \weight_reg[13]_12\(2),
O => \weight[13][0]_i_3_n_0\
);
\weight[13][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_90\,
I1 => \weight_reg[13]_12\(1),
O => \weight[13][0]_i_4_n_0\
);
\weight[13][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_91\,
I1 => \weight_reg[13]_12\(0),
O => \weight[13][0]_i_5_n_0\
);
\weight[13][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_76\,
I1 => \weight_reg[13]_12\(15),
O => \weight[13][12]_i_2_n_0\
);
\weight[13][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_77\,
I1 => \weight_reg[13]_12\(14),
O => \weight[13][12]_i_3_n_0\
);
\weight[13][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_78\,
I1 => \weight_reg[13]_12\(13),
O => \weight[13][12]_i_4_n_0\
);
\weight[13][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_79\,
I1 => \weight_reg[13]_12\(12),
O => \weight[13][12]_i_5_n_0\
);
\weight[13][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_84\,
I1 => \weight_reg[13]_12\(7),
O => \weight[13][4]_i_2_n_0\
);
\weight[13][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_85\,
I1 => \weight_reg[13]_12\(6),
O => \weight[13][4]_i_3_n_0\
);
\weight[13][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_86\,
I1 => \weight_reg[13]_12\(5),
O => \weight[13][4]_i_4_n_0\
);
\weight[13][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_87\,
I1 => \weight_reg[13]_12\(4),
O => \weight[13][4]_i_5_n_0\
);
\weight[13][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_80\,
I1 => \weight_reg[13]_12\(11),
O => \weight[13][8]_i_2_n_0\
);
\weight[13][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_81\,
I1 => \weight_reg[13]_12\(10),
O => \weight[13][8]_i_3_n_0\
);
\weight[13][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_82\,
I1 => \weight_reg[13]_12\(9),
O => \weight[13][8]_i_4_n_0\
);
\weight[13][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__23_n_83\,
I1 => \weight_reg[13]_12\(8),
O => \weight[13][8]_i_5_n_0\
);
\weight[14][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_88\,
I1 => \weight_reg[14]_13\(3),
O => \weight[14][0]_i_2_n_0\
);
\weight[14][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_89\,
I1 => \weight_reg[14]_13\(2),
O => \weight[14][0]_i_3_n_0\
);
\weight[14][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_90\,
I1 => \weight_reg[14]_13\(1),
O => \weight[14][0]_i_4_n_0\
);
\weight[14][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_91\,
I1 => \weight_reg[14]_13\(0),
O => \weight[14][0]_i_5_n_0\
);
\weight[14][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_76\,
I1 => \weight_reg[14]_13\(15),
O => \weight[14][12]_i_2_n_0\
);
\weight[14][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_77\,
I1 => \weight_reg[14]_13\(14),
O => \weight[14][12]_i_3_n_0\
);
\weight[14][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_78\,
I1 => \weight_reg[14]_13\(13),
O => \weight[14][12]_i_4_n_0\
);
\weight[14][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_79\,
I1 => \weight_reg[14]_13\(12),
O => \weight[14][12]_i_5_n_0\
);
\weight[14][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_84\,
I1 => \weight_reg[14]_13\(7),
O => \weight[14][4]_i_2_n_0\
);
\weight[14][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_85\,
I1 => \weight_reg[14]_13\(6),
O => \weight[14][4]_i_3_n_0\
);
\weight[14][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_86\,
I1 => \weight_reg[14]_13\(5),
O => \weight[14][4]_i_4_n_0\
);
\weight[14][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_87\,
I1 => \weight_reg[14]_13\(4),
O => \weight[14][4]_i_5_n_0\
);
\weight[14][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_80\,
I1 => \weight_reg[14]_13\(11),
O => \weight[14][8]_i_2_n_0\
);
\weight[14][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_81\,
I1 => \weight_reg[14]_13\(10),
O => \weight[14][8]_i_3_n_0\
);
\weight[14][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_82\,
I1 => \weight_reg[14]_13\(9),
O => \weight[14][8]_i_4_n_0\
);
\weight[14][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__25_n_83\,
I1 => \weight_reg[14]_13\(8),
O => \weight[14][8]_i_5_n_0\
);
\weight[15][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_88\,
I1 => \weight_reg[15]_14\(3),
O => \weight[15][0]_i_2_n_0\
);
\weight[15][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_89\,
I1 => \weight_reg[15]_14\(2),
O => \weight[15][0]_i_3_n_0\
);
\weight[15][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_90\,
I1 => \weight_reg[15]_14\(1),
O => \weight[15][0]_i_4_n_0\
);
\weight[15][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_91\,
I1 => \weight_reg[15]_14\(0),
O => \weight[15][0]_i_5_n_0\
);
\weight[15][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_76\,
I1 => \weight_reg[15]_14\(15),
O => \weight[15][12]_i_2_n_0\
);
\weight[15][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_77\,
I1 => \weight_reg[15]_14\(14),
O => \weight[15][12]_i_3_n_0\
);
\weight[15][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_78\,
I1 => \weight_reg[15]_14\(13),
O => \weight[15][12]_i_4_n_0\
);
\weight[15][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_79\,
I1 => \weight_reg[15]_14\(12),
O => \weight[15][12]_i_5_n_0\
);
\weight[15][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_84\,
I1 => \weight_reg[15]_14\(7),
O => \weight[15][4]_i_2_n_0\
);
\weight[15][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_85\,
I1 => \weight_reg[15]_14\(6),
O => \weight[15][4]_i_3_n_0\
);
\weight[15][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_86\,
I1 => \weight_reg[15]_14\(5),
O => \weight[15][4]_i_4_n_0\
);
\weight[15][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_87\,
I1 => \weight_reg[15]_14\(4),
O => \weight[15][4]_i_5_n_0\
);
\weight[15][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_80\,
I1 => \weight_reg[15]_14\(11),
O => \weight[15][8]_i_2_n_0\
);
\weight[15][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_81\,
I1 => \weight_reg[15]_14\(10),
O => \weight[15][8]_i_3_n_0\
);
\weight[15][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_82\,
I1 => \weight_reg[15]_14\(9),
O => \weight[15][8]_i_4_n_0\
);
\weight[15][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__27_n_83\,
I1 => \weight_reg[15]_14\(8),
O => \weight[15][8]_i_5_n_0\
);
\weight[1][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(3),
I1 => \weight_reg[1]_0\(3),
O => \weight[1][0]_i_2_n_0\
);
\weight[1][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(2),
I1 => \weight_reg[1]_0\(2),
O => \weight[1][0]_i_3_n_0\
);
\weight[1][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(1),
I1 => \weight_reg[1]_0\(1),
O => \weight[1][0]_i_4_n_0\
);
\weight[1][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(0),
I1 => \weight_reg[1]_0\(0),
O => \weight[1][0]_i_5_n_0\
);
\weight[1][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(15),
I1 => \weight_reg[1]_0\(15),
O => \weight[1][12]_i_2_n_0\
);
\weight[1][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(14),
I1 => \weight_reg[1]_0\(14),
O => \weight[1][12]_i_3_n_0\
);
\weight[1][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(13),
I1 => \weight_reg[1]_0\(13),
O => \weight[1][12]_i_4_n_0\
);
\weight[1][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(12),
I1 => \weight_reg[1]_0\(12),
O => \weight[1][12]_i_5_n_0\
);
\weight[1][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(7),
I1 => \weight_reg[1]_0\(7),
O => \weight[1][4]_i_2_n_0\
);
\weight[1][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(6),
I1 => \weight_reg[1]_0\(6),
O => \weight[1][4]_i_3_n_0\
);
\weight[1][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(5),
I1 => \weight_reg[1]_0\(5),
O => \weight[1][4]_i_4_n_0\
);
\weight[1][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(4),
I1 => \weight_reg[1]_0\(4),
O => \weight[1][4]_i_5_n_0\
);
\weight[1][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(11),
I1 => \weight_reg[1]_0\(11),
O => \weight[1][8]_i_2_n_0\
);
\weight[1][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(10),
I1 => \weight_reg[1]_0\(10),
O => \weight[1][8]_i_3_n_0\
);
\weight[1][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(9),
I1 => \weight_reg[1]_0\(9),
O => \weight[1][8]_i_4_n_0\
);
\weight[1][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \in\(8),
I1 => \weight_reg[1]_0\(8),
O => \weight[1][8]_i_5_n_0\
);
\weight[2][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_88\,
I1 => \weight_reg[2]_1\(3),
O => \weight[2][0]_i_2_n_0\
);
\weight[2][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_89\,
I1 => \weight_reg[2]_1\(2),
O => \weight[2][0]_i_3_n_0\
);
\weight[2][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_90\,
I1 => \weight_reg[2]_1\(1),
O => \weight[2][0]_i_4_n_0\
);
\weight[2][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_91\,
I1 => \weight_reg[2]_1\(0),
O => \weight[2][0]_i_5_n_0\
);
\weight[2][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_76\,
I1 => \weight_reg[2]_1\(15),
O => \weight[2][12]_i_2_n_0\
);
\weight[2][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_77\,
I1 => \weight_reg[2]_1\(14),
O => \weight[2][12]_i_3_n_0\
);
\weight[2][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_78\,
I1 => \weight_reg[2]_1\(13),
O => \weight[2][12]_i_4_n_0\
);
\weight[2][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_79\,
I1 => \weight_reg[2]_1\(12),
O => \weight[2][12]_i_5_n_0\
);
\weight[2][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_84\,
I1 => \weight_reg[2]_1\(7),
O => \weight[2][4]_i_2_n_0\
);
\weight[2][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_85\,
I1 => \weight_reg[2]_1\(6),
O => \weight[2][4]_i_3_n_0\
);
\weight[2][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_86\,
I1 => \weight_reg[2]_1\(5),
O => \weight[2][4]_i_4_n_0\
);
\weight[2][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_87\,
I1 => \weight_reg[2]_1\(4),
O => \weight[2][4]_i_5_n_0\
);
\weight[2][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_80\,
I1 => \weight_reg[2]_1\(11),
O => \weight[2][8]_i_2_n_0\
);
\weight[2][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_81\,
I1 => \weight_reg[2]_1\(10),
O => \weight[2][8]_i_3_n_0\
);
\weight[2][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_82\,
I1 => \weight_reg[2]_1\(9),
O => \weight[2][8]_i_4_n_0\
);
\weight[2][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__1_n_83\,
I1 => \weight_reg[2]_1\(8),
O => \weight[2][8]_i_5_n_0\
);
\weight[3][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_88\,
I1 => \weight_reg[3]_2\(3),
O => \weight[3][0]_i_2_n_0\
);
\weight[3][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_89\,
I1 => \weight_reg[3]_2\(2),
O => \weight[3][0]_i_3_n_0\
);
\weight[3][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_90\,
I1 => \weight_reg[3]_2\(1),
O => \weight[3][0]_i_4_n_0\
);
\weight[3][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_91\,
I1 => \weight_reg[3]_2\(0),
O => \weight[3][0]_i_5_n_0\
);
\weight[3][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_76\,
I1 => \weight_reg[3]_2\(15),
O => \weight[3][12]_i_2_n_0\
);
\weight[3][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_77\,
I1 => \weight_reg[3]_2\(14),
O => \weight[3][12]_i_3_n_0\
);
\weight[3][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_78\,
I1 => \weight_reg[3]_2\(13),
O => \weight[3][12]_i_4_n_0\
);
\weight[3][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_79\,
I1 => \weight_reg[3]_2\(12),
O => \weight[3][12]_i_5_n_0\
);
\weight[3][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_84\,
I1 => \weight_reg[3]_2\(7),
O => \weight[3][4]_i_2_n_0\
);
\weight[3][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_85\,
I1 => \weight_reg[3]_2\(6),
O => \weight[3][4]_i_3_n_0\
);
\weight[3][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_86\,
I1 => \weight_reg[3]_2\(5),
O => \weight[3][4]_i_4_n_0\
);
\weight[3][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_87\,
I1 => \weight_reg[3]_2\(4),
O => \weight[3][4]_i_5_n_0\
);
\weight[3][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_80\,
I1 => \weight_reg[3]_2\(11),
O => \weight[3][8]_i_2_n_0\
);
\weight[3][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_81\,
I1 => \weight_reg[3]_2\(10),
O => \weight[3][8]_i_3_n_0\
);
\weight[3][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_82\,
I1 => \weight_reg[3]_2\(9),
O => \weight[3][8]_i_4_n_0\
);
\weight[3][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__3_n_83\,
I1 => \weight_reg[3]_2\(8),
O => \weight[3][8]_i_5_n_0\
);
\weight[4][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_88\,
I1 => \weight_reg[4]_3\(3),
O => \weight[4][0]_i_2_n_0\
);
\weight[4][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_89\,
I1 => \weight_reg[4]_3\(2),
O => \weight[4][0]_i_3_n_0\
);
\weight[4][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_90\,
I1 => \weight_reg[4]_3\(1),
O => \weight[4][0]_i_4_n_0\
);
\weight[4][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_91\,
I1 => \weight_reg[4]_3\(0),
O => \weight[4][0]_i_5_n_0\
);
\weight[4][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_76\,
I1 => \weight_reg[4]_3\(15),
O => \weight[4][12]_i_2_n_0\
);
\weight[4][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_77\,
I1 => \weight_reg[4]_3\(14),
O => \weight[4][12]_i_3_n_0\
);
\weight[4][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_78\,
I1 => \weight_reg[4]_3\(13),
O => \weight[4][12]_i_4_n_0\
);
\weight[4][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_79\,
I1 => \weight_reg[4]_3\(12),
O => \weight[4][12]_i_5_n_0\
);
\weight[4][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_84\,
I1 => \weight_reg[4]_3\(7),
O => \weight[4][4]_i_2_n_0\
);
\weight[4][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_85\,
I1 => \weight_reg[4]_3\(6),
O => \weight[4][4]_i_3_n_0\
);
\weight[4][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_86\,
I1 => \weight_reg[4]_3\(5),
O => \weight[4][4]_i_4_n_0\
);
\weight[4][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_87\,
I1 => \weight_reg[4]_3\(4),
O => \weight[4][4]_i_5_n_0\
);
\weight[4][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_80\,
I1 => \weight_reg[4]_3\(11),
O => \weight[4][8]_i_2_n_0\
);
\weight[4][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_81\,
I1 => \weight_reg[4]_3\(10),
O => \weight[4][8]_i_3_n_0\
);
\weight[4][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_82\,
I1 => \weight_reg[4]_3\(9),
O => \weight[4][8]_i_4_n_0\
);
\weight[4][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__5_n_83\,
I1 => \weight_reg[4]_3\(8),
O => \weight[4][8]_i_5_n_0\
);
\weight[5][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_88\,
I1 => \weight_reg[5]_4\(3),
O => \weight[5][0]_i_2_n_0\
);
\weight[5][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_89\,
I1 => \weight_reg[5]_4\(2),
O => \weight[5][0]_i_3_n_0\
);
\weight[5][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_90\,
I1 => \weight_reg[5]_4\(1),
O => \weight[5][0]_i_4_n_0\
);
\weight[5][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_91\,
I1 => \weight_reg[5]_4\(0),
O => \weight[5][0]_i_5_n_0\
);
\weight[5][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_76\,
I1 => \weight_reg[5]_4\(15),
O => \weight[5][12]_i_2_n_0\
);
\weight[5][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_77\,
I1 => \weight_reg[5]_4\(14),
O => \weight[5][12]_i_3_n_0\
);
\weight[5][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_78\,
I1 => \weight_reg[5]_4\(13),
O => \weight[5][12]_i_4_n_0\
);
\weight[5][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_79\,
I1 => \weight_reg[5]_4\(12),
O => \weight[5][12]_i_5_n_0\
);
\weight[5][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_84\,
I1 => \weight_reg[5]_4\(7),
O => \weight[5][4]_i_2_n_0\
);
\weight[5][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_85\,
I1 => \weight_reg[5]_4\(6),
O => \weight[5][4]_i_3_n_0\
);
\weight[5][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_86\,
I1 => \weight_reg[5]_4\(5),
O => \weight[5][4]_i_4_n_0\
);
\weight[5][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_87\,
I1 => \weight_reg[5]_4\(4),
O => \weight[5][4]_i_5_n_0\
);
\weight[5][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_80\,
I1 => \weight_reg[5]_4\(11),
O => \weight[5][8]_i_2_n_0\
);
\weight[5][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_81\,
I1 => \weight_reg[5]_4\(10),
O => \weight[5][8]_i_3_n_0\
);
\weight[5][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_82\,
I1 => \weight_reg[5]_4\(9),
O => \weight[5][8]_i_4_n_0\
);
\weight[5][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__7_n_83\,
I1 => \weight_reg[5]_4\(8),
O => \weight[5][8]_i_5_n_0\
);
\weight[6][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_88\,
I1 => \weight_reg[6]_5\(3),
O => \weight[6][0]_i_2_n_0\
);
\weight[6][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_89\,
I1 => \weight_reg[6]_5\(2),
O => \weight[6][0]_i_3_n_0\
);
\weight[6][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_90\,
I1 => \weight_reg[6]_5\(1),
O => \weight[6][0]_i_4_n_0\
);
\weight[6][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_91\,
I1 => \weight_reg[6]_5\(0),
O => \weight[6][0]_i_5_n_0\
);
\weight[6][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_76\,
I1 => \weight_reg[6]_5\(15),
O => \weight[6][12]_i_2_n_0\
);
\weight[6][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_77\,
I1 => \weight_reg[6]_5\(14),
O => \weight[6][12]_i_3_n_0\
);
\weight[6][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_78\,
I1 => \weight_reg[6]_5\(13),
O => \weight[6][12]_i_4_n_0\
);
\weight[6][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_79\,
I1 => \weight_reg[6]_5\(12),
O => \weight[6][12]_i_5_n_0\
);
\weight[6][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_84\,
I1 => \weight_reg[6]_5\(7),
O => \weight[6][4]_i_2_n_0\
);
\weight[6][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_85\,
I1 => \weight_reg[6]_5\(6),
O => \weight[6][4]_i_3_n_0\
);
\weight[6][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_86\,
I1 => \weight_reg[6]_5\(5),
O => \weight[6][4]_i_4_n_0\
);
\weight[6][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_87\,
I1 => \weight_reg[6]_5\(4),
O => \weight[6][4]_i_5_n_0\
);
\weight[6][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_80\,
I1 => \weight_reg[6]_5\(11),
O => \weight[6][8]_i_2_n_0\
);
\weight[6][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_81\,
I1 => \weight_reg[6]_5\(10),
O => \weight[6][8]_i_3_n_0\
);
\weight[6][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_82\,
I1 => \weight_reg[6]_5\(9),
O => \weight[6][8]_i_4_n_0\
);
\weight[6][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__9_n_83\,
I1 => \weight_reg[6]_5\(8),
O => \weight[6][8]_i_5_n_0\
);
\weight[7][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_88\,
I1 => \weight_reg[7]_6\(3),
O => \weight[7][0]_i_2_n_0\
);
\weight[7][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_89\,
I1 => \weight_reg[7]_6\(2),
O => \weight[7][0]_i_3_n_0\
);
\weight[7][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_90\,
I1 => \weight_reg[7]_6\(1),
O => \weight[7][0]_i_4_n_0\
);
\weight[7][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_91\,
I1 => \weight_reg[7]_6\(0),
O => \weight[7][0]_i_5_n_0\
);
\weight[7][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_76\,
I1 => \weight_reg[7]_6\(15),
O => \weight[7][12]_i_2_n_0\
);
\weight[7][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_77\,
I1 => \weight_reg[7]_6\(14),
O => \weight[7][12]_i_3_n_0\
);
\weight[7][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_78\,
I1 => \weight_reg[7]_6\(13),
O => \weight[7][12]_i_4_n_0\
);
\weight[7][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_79\,
I1 => \weight_reg[7]_6\(12),
O => \weight[7][12]_i_5_n_0\
);
\weight[7][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_84\,
I1 => \weight_reg[7]_6\(7),
O => \weight[7][4]_i_2_n_0\
);
\weight[7][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_85\,
I1 => \weight_reg[7]_6\(6),
O => \weight[7][4]_i_3_n_0\
);
\weight[7][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_86\,
I1 => \weight_reg[7]_6\(5),
O => \weight[7][4]_i_4_n_0\
);
\weight[7][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_87\,
I1 => \weight_reg[7]_6\(4),
O => \weight[7][4]_i_5_n_0\
);
\weight[7][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_80\,
I1 => \weight_reg[7]_6\(11),
O => \weight[7][8]_i_2_n_0\
);
\weight[7][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_81\,
I1 => \weight_reg[7]_6\(10),
O => \weight[7][8]_i_3_n_0\
);
\weight[7][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_82\,
I1 => \weight_reg[7]_6\(9),
O => \weight[7][8]_i_4_n_0\
);
\weight[7][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__11_n_83\,
I1 => \weight_reg[7]_6\(8),
O => \weight[7][8]_i_5_n_0\
);
\weight[8][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_88\,
I1 => \weight_reg[8]_7\(3),
O => \weight[8][0]_i_2_n_0\
);
\weight[8][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_89\,
I1 => \weight_reg[8]_7\(2),
O => \weight[8][0]_i_3_n_0\
);
\weight[8][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_90\,
I1 => \weight_reg[8]_7\(1),
O => \weight[8][0]_i_4_n_0\
);
\weight[8][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_91\,
I1 => \weight_reg[8]_7\(0),
O => \weight[8][0]_i_5_n_0\
);
\weight[8][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_76\,
I1 => \weight_reg[8]_7\(15),
O => \weight[8][12]_i_2_n_0\
);
\weight[8][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_77\,
I1 => \weight_reg[8]_7\(14),
O => \weight[8][12]_i_3_n_0\
);
\weight[8][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_78\,
I1 => \weight_reg[8]_7\(13),
O => \weight[8][12]_i_4_n_0\
);
\weight[8][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_79\,
I1 => \weight_reg[8]_7\(12),
O => \weight[8][12]_i_5_n_0\
);
\weight[8][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_84\,
I1 => \weight_reg[8]_7\(7),
O => \weight[8][4]_i_2_n_0\
);
\weight[8][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_85\,
I1 => \weight_reg[8]_7\(6),
O => \weight[8][4]_i_3_n_0\
);
\weight[8][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_86\,
I1 => \weight_reg[8]_7\(5),
O => \weight[8][4]_i_4_n_0\
);
\weight[8][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_87\,
I1 => \weight_reg[8]_7\(4),
O => \weight[8][4]_i_5_n_0\
);
\weight[8][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_80\,
I1 => \weight_reg[8]_7\(11),
O => \weight[8][8]_i_2_n_0\
);
\weight[8][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_81\,
I1 => \weight_reg[8]_7\(10),
O => \weight[8][8]_i_3_n_0\
);
\weight[8][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_82\,
I1 => \weight_reg[8]_7\(9),
O => \weight[8][8]_i_4_n_0\
);
\weight[8][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__13_n_83\,
I1 => \weight_reg[8]_7\(8),
O => \weight[8][8]_i_5_n_0\
);
\weight[9][0]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_88\,
I1 => \weight_reg[9]_8\(3),
O => \weight[9][0]_i_2_n_0\
);
\weight[9][0]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_89\,
I1 => \weight_reg[9]_8\(2),
O => \weight[9][0]_i_3_n_0\
);
\weight[9][0]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_90\,
I1 => \weight_reg[9]_8\(1),
O => \weight[9][0]_i_4_n_0\
);
\weight[9][0]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_91\,
I1 => \weight_reg[9]_8\(0),
O => \weight[9][0]_i_5_n_0\
);
\weight[9][12]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_76\,
I1 => \weight_reg[9]_8\(15),
O => \weight[9][12]_i_2_n_0\
);
\weight[9][12]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_77\,
I1 => \weight_reg[9]_8\(14),
O => \weight[9][12]_i_3_n_0\
);
\weight[9][12]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_78\,
I1 => \weight_reg[9]_8\(13),
O => \weight[9][12]_i_4_n_0\
);
\weight[9][12]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_79\,
I1 => \weight_reg[9]_8\(12),
O => \weight[9][12]_i_5_n_0\
);
\weight[9][4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_84\,
I1 => \weight_reg[9]_8\(7),
O => \weight[9][4]_i_2_n_0\
);
\weight[9][4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_85\,
I1 => \weight_reg[9]_8\(6),
O => \weight[9][4]_i_3_n_0\
);
\weight[9][4]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_86\,
I1 => \weight_reg[9]_8\(5),
O => \weight[9][4]_i_4_n_0\
);
\weight[9][4]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_87\,
I1 => \weight_reg[9]_8\(4),
O => \weight[9][4]_i_5_n_0\
);
\weight[9][8]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_80\,
I1 => \weight_reg[9]_8\(11),
O => \weight[9][8]_i_2_n_0\
);
\weight[9][8]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_81\,
I1 => \weight_reg[9]_8\(10),
O => \weight[9][8]_i_3_n_0\
);
\weight[9][8]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_82\,
I1 => \weight_reg[9]_8\(9),
O => \weight[9][8]_i_4_n_0\
);
\weight[9][8]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \ARG__15_n_83\,
I1 => \weight_reg[9]_8\(8),
O => \weight[9][8]_i_5_n_0\
);
\weight_reg[0][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_7\,
Q => \weight_reg[0]_15\(0)
);
\weight_reg[0][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[0][0]_i_1_n_0\,
CO(2) => \weight_reg[0][0]_i_1_n_1\,
CO(1) => \weight_reg[0][0]_i_1_n_2\,
CO(0) => \weight_reg[0][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_88\,
DI(2) => \ARG__29_n_89\,
DI(1) => \ARG__29_n_90\,
DI(0) => \ARG__29_n_91\,
O(3) => \weight_reg[0][0]_i_1_n_4\,
O(2) => \weight_reg[0][0]_i_1_n_5\,
O(1) => \weight_reg[0][0]_i_1_n_6\,
O(0) => \weight_reg[0][0]_i_1_n_7\,
S(3) => \weight[0][0]_i_2_n_0\,
S(2) => \weight[0][0]_i_3_n_0\,
S(1) => \weight[0][0]_i_4_n_0\,
S(0) => \weight[0][0]_i_5_n_0\
);
\weight_reg[0][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_5\,
Q => \weight_reg[0]_15\(10)
);
\weight_reg[0][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_4\,
Q => \weight_reg[0]_15\(11)
);
\weight_reg[0][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_7\,
Q => \weight_reg[0]_15\(12)
);
\weight_reg[0][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[0][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[0][12]_i_1_n_1\,
CO(1) => \weight_reg[0][12]_i_1_n_2\,
CO(0) => \weight_reg[0][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__29_n_77\,
DI(1) => \ARG__29_n_78\,
DI(0) => \ARG__29_n_79\,
O(3) => \weight_reg[0][12]_i_1_n_4\,
O(2) => \weight_reg[0][12]_i_1_n_5\,
O(1) => \weight_reg[0][12]_i_1_n_6\,
O(0) => \weight_reg[0][12]_i_1_n_7\,
S(3) => \weight[0][12]_i_2_n_0\,
S(2) => \weight[0][12]_i_3_n_0\,
S(1) => \weight[0][12]_i_4_n_0\,
S(0) => \weight[0][12]_i_5_n_0\
);
\weight_reg[0][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_6\,
Q => \weight_reg[0]_15\(13)
);
\weight_reg[0][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_5\,
Q => \weight_reg[0]_15\(14)
);
\weight_reg[0][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][12]_i_1_n_4\,
Q => \weight_reg[0]_15\(15)
);
\weight_reg[0][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_6\,
Q => \weight_reg[0]_15\(1)
);
\weight_reg[0][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_5\,
Q => \weight_reg[0]_15\(2)
);
\weight_reg[0][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][0]_i_1_n_4\,
Q => \weight_reg[0]_15\(3)
);
\weight_reg[0][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_7\,
Q => \weight_reg[0]_15\(4)
);
\weight_reg[0][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][0]_i_1_n_0\,
CO(3) => \weight_reg[0][4]_i_1_n_0\,
CO(2) => \weight_reg[0][4]_i_1_n_1\,
CO(1) => \weight_reg[0][4]_i_1_n_2\,
CO(0) => \weight_reg[0][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_84\,
DI(2) => \ARG__29_n_85\,
DI(1) => \ARG__29_n_86\,
DI(0) => \ARG__29_n_87\,
O(3) => \weight_reg[0][4]_i_1_n_4\,
O(2) => \weight_reg[0][4]_i_1_n_5\,
O(1) => \weight_reg[0][4]_i_1_n_6\,
O(0) => \weight_reg[0][4]_i_1_n_7\,
S(3) => \weight[0][4]_i_2_n_0\,
S(2) => \weight[0][4]_i_3_n_0\,
S(1) => \weight[0][4]_i_4_n_0\,
S(0) => \weight[0][4]_i_5_n_0\
);
\weight_reg[0][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_6\,
Q => \weight_reg[0]_15\(5)
);
\weight_reg[0][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_5\,
Q => \weight_reg[0]_15\(6)
);
\weight_reg[0][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][4]_i_1_n_4\,
Q => \weight_reg[0]_15\(7)
);
\weight_reg[0][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_7\,
Q => \weight_reg[0]_15\(8)
);
\weight_reg[0][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[0][4]_i_1_n_0\,
CO(3) => \weight_reg[0][8]_i_1_n_0\,
CO(2) => \weight_reg[0][8]_i_1_n_1\,
CO(1) => \weight_reg[0][8]_i_1_n_2\,
CO(0) => \weight_reg[0][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__29_n_80\,
DI(2) => \ARG__29_n_81\,
DI(1) => \ARG__29_n_82\,
DI(0) => \ARG__29_n_83\,
O(3) => \weight_reg[0][8]_i_1_n_4\,
O(2) => \weight_reg[0][8]_i_1_n_5\,
O(1) => \weight_reg[0][8]_i_1_n_6\,
O(0) => \weight_reg[0][8]_i_1_n_7\,
S(3) => \weight[0][8]_i_2_n_0\,
S(2) => \weight[0][8]_i_3_n_0\,
S(1) => \weight[0][8]_i_4_n_0\,
S(0) => \weight[0][8]_i_5_n_0\
);
\weight_reg[0][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[0][8]_i_1_n_6\,
Q => \weight_reg[0]_15\(9)
);
\weight_reg[10][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_7\,
Q => \weight_reg[10]_9\(0)
);
\weight_reg[10][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[10][0]_i_1_n_0\,
CO(2) => \weight_reg[10][0]_i_1_n_1\,
CO(1) => \weight_reg[10][0]_i_1_n_2\,
CO(0) => \weight_reg[10][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_88\,
DI(2) => \ARG__17_n_89\,
DI(1) => \ARG__17_n_90\,
DI(0) => \ARG__17_n_91\,
O(3) => \weight_reg[10][0]_i_1_n_4\,
O(2) => \weight_reg[10][0]_i_1_n_5\,
O(1) => \weight_reg[10][0]_i_1_n_6\,
O(0) => \weight_reg[10][0]_i_1_n_7\,
S(3) => \weight[10][0]_i_2_n_0\,
S(2) => \weight[10][0]_i_3_n_0\,
S(1) => \weight[10][0]_i_4_n_0\,
S(0) => \weight[10][0]_i_5_n_0\
);
\weight_reg[10][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_5\,
Q => \weight_reg[10]_9\(10)
);
\weight_reg[10][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_4\,
Q => \weight_reg[10]_9\(11)
);
\weight_reg[10][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_7\,
Q => \weight_reg[10]_9\(12)
);
\weight_reg[10][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[10][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[10][12]_i_1_n_1\,
CO(1) => \weight_reg[10][12]_i_1_n_2\,
CO(0) => \weight_reg[10][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__17_n_77\,
DI(1) => \ARG__17_n_78\,
DI(0) => \ARG__17_n_79\,
O(3) => \weight_reg[10][12]_i_1_n_4\,
O(2) => \weight_reg[10][12]_i_1_n_5\,
O(1) => \weight_reg[10][12]_i_1_n_6\,
O(0) => \weight_reg[10][12]_i_1_n_7\,
S(3) => \weight[10][12]_i_2_n_0\,
S(2) => \weight[10][12]_i_3_n_0\,
S(1) => \weight[10][12]_i_4_n_0\,
S(0) => \weight[10][12]_i_5_n_0\
);
\weight_reg[10][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_6\,
Q => \weight_reg[10]_9\(13)
);
\weight_reg[10][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_5\,
Q => \weight_reg[10]_9\(14)
);
\weight_reg[10][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][12]_i_1_n_4\,
Q => \weight_reg[10]_9\(15)
);
\weight_reg[10][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_6\,
Q => \weight_reg[10]_9\(1)
);
\weight_reg[10][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_5\,
Q => \weight_reg[10]_9\(2)
);
\weight_reg[10][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][0]_i_1_n_4\,
Q => \weight_reg[10]_9\(3)
);
\weight_reg[10][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_7\,
Q => \weight_reg[10]_9\(4)
);
\weight_reg[10][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][0]_i_1_n_0\,
CO(3) => \weight_reg[10][4]_i_1_n_0\,
CO(2) => \weight_reg[10][4]_i_1_n_1\,
CO(1) => \weight_reg[10][4]_i_1_n_2\,
CO(0) => \weight_reg[10][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_84\,
DI(2) => \ARG__17_n_85\,
DI(1) => \ARG__17_n_86\,
DI(0) => \ARG__17_n_87\,
O(3) => \weight_reg[10][4]_i_1_n_4\,
O(2) => \weight_reg[10][4]_i_1_n_5\,
O(1) => \weight_reg[10][4]_i_1_n_6\,
O(0) => \weight_reg[10][4]_i_1_n_7\,
S(3) => \weight[10][4]_i_2_n_0\,
S(2) => \weight[10][4]_i_3_n_0\,
S(1) => \weight[10][4]_i_4_n_0\,
S(0) => \weight[10][4]_i_5_n_0\
);
\weight_reg[10][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_6\,
Q => \weight_reg[10]_9\(5)
);
\weight_reg[10][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_5\,
Q => \weight_reg[10]_9\(6)
);
\weight_reg[10][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][4]_i_1_n_4\,
Q => \weight_reg[10]_9\(7)
);
\weight_reg[10][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_7\,
Q => \weight_reg[10]_9\(8)
);
\weight_reg[10][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[10][4]_i_1_n_0\,
CO(3) => \weight_reg[10][8]_i_1_n_0\,
CO(2) => \weight_reg[10][8]_i_1_n_1\,
CO(1) => \weight_reg[10][8]_i_1_n_2\,
CO(0) => \weight_reg[10][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__17_n_80\,
DI(2) => \ARG__17_n_81\,
DI(1) => \ARG__17_n_82\,
DI(0) => \ARG__17_n_83\,
O(3) => \weight_reg[10][8]_i_1_n_4\,
O(2) => \weight_reg[10][8]_i_1_n_5\,
O(1) => \weight_reg[10][8]_i_1_n_6\,
O(0) => \weight_reg[10][8]_i_1_n_7\,
S(3) => \weight[10][8]_i_2_n_0\,
S(2) => \weight[10][8]_i_3_n_0\,
S(1) => \weight[10][8]_i_4_n_0\,
S(0) => \weight[10][8]_i_5_n_0\
);
\weight_reg[10][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[10][8]_i_1_n_6\,
Q => \weight_reg[10]_9\(9)
);
\weight_reg[11][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_7\,
Q => \weight_reg[11]_10\(0)
);
\weight_reg[11][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[11][0]_i_1_n_0\,
CO(2) => \weight_reg[11][0]_i_1_n_1\,
CO(1) => \weight_reg[11][0]_i_1_n_2\,
CO(0) => \weight_reg[11][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_88\,
DI(2) => \ARG__19_n_89\,
DI(1) => \ARG__19_n_90\,
DI(0) => \ARG__19_n_91\,
O(3) => \weight_reg[11][0]_i_1_n_4\,
O(2) => \weight_reg[11][0]_i_1_n_5\,
O(1) => \weight_reg[11][0]_i_1_n_6\,
O(0) => \weight_reg[11][0]_i_1_n_7\,
S(3) => \weight[11][0]_i_2_n_0\,
S(2) => \weight[11][0]_i_3_n_0\,
S(1) => \weight[11][0]_i_4_n_0\,
S(0) => \weight[11][0]_i_5_n_0\
);
\weight_reg[11][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_5\,
Q => \weight_reg[11]_10\(10)
);
\weight_reg[11][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_4\,
Q => \weight_reg[11]_10\(11)
);
\weight_reg[11][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_7\,
Q => \weight_reg[11]_10\(12)
);
\weight_reg[11][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[11][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[11][12]_i_1_n_1\,
CO(1) => \weight_reg[11][12]_i_1_n_2\,
CO(0) => \weight_reg[11][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__19_n_77\,
DI(1) => \ARG__19_n_78\,
DI(0) => \ARG__19_n_79\,
O(3) => \weight_reg[11][12]_i_1_n_4\,
O(2) => \weight_reg[11][12]_i_1_n_5\,
O(1) => \weight_reg[11][12]_i_1_n_6\,
O(0) => \weight_reg[11][12]_i_1_n_7\,
S(3) => \weight[11][12]_i_2_n_0\,
S(2) => \weight[11][12]_i_3_n_0\,
S(1) => \weight[11][12]_i_4_n_0\,
S(0) => \weight[11][12]_i_5_n_0\
);
\weight_reg[11][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_6\,
Q => \weight_reg[11]_10\(13)
);
\weight_reg[11][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_5\,
Q => \weight_reg[11]_10\(14)
);
\weight_reg[11][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][12]_i_1_n_4\,
Q => \weight_reg[11]_10\(15)
);
\weight_reg[11][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_6\,
Q => \weight_reg[11]_10\(1)
);
\weight_reg[11][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_5\,
Q => \weight_reg[11]_10\(2)
);
\weight_reg[11][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][0]_i_1_n_4\,
Q => \weight_reg[11]_10\(3)
);
\weight_reg[11][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_7\,
Q => \weight_reg[11]_10\(4)
);
\weight_reg[11][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][0]_i_1_n_0\,
CO(3) => \weight_reg[11][4]_i_1_n_0\,
CO(2) => \weight_reg[11][4]_i_1_n_1\,
CO(1) => \weight_reg[11][4]_i_1_n_2\,
CO(0) => \weight_reg[11][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_84\,
DI(2) => \ARG__19_n_85\,
DI(1) => \ARG__19_n_86\,
DI(0) => \ARG__19_n_87\,
O(3) => \weight_reg[11][4]_i_1_n_4\,
O(2) => \weight_reg[11][4]_i_1_n_5\,
O(1) => \weight_reg[11][4]_i_1_n_6\,
O(0) => \weight_reg[11][4]_i_1_n_7\,
S(3) => \weight[11][4]_i_2_n_0\,
S(2) => \weight[11][4]_i_3_n_0\,
S(1) => \weight[11][4]_i_4_n_0\,
S(0) => \weight[11][4]_i_5_n_0\
);
\weight_reg[11][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_6\,
Q => \weight_reg[11]_10\(5)
);
\weight_reg[11][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_5\,
Q => \weight_reg[11]_10\(6)
);
\weight_reg[11][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][4]_i_1_n_4\,
Q => \weight_reg[11]_10\(7)
);
\weight_reg[11][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_7\,
Q => \weight_reg[11]_10\(8)
);
\weight_reg[11][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[11][4]_i_1_n_0\,
CO(3) => \weight_reg[11][8]_i_1_n_0\,
CO(2) => \weight_reg[11][8]_i_1_n_1\,
CO(1) => \weight_reg[11][8]_i_1_n_2\,
CO(0) => \weight_reg[11][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__19_n_80\,
DI(2) => \ARG__19_n_81\,
DI(1) => \ARG__19_n_82\,
DI(0) => \ARG__19_n_83\,
O(3) => \weight_reg[11][8]_i_1_n_4\,
O(2) => \weight_reg[11][8]_i_1_n_5\,
O(1) => \weight_reg[11][8]_i_1_n_6\,
O(0) => \weight_reg[11][8]_i_1_n_7\,
S(3) => \weight[11][8]_i_2_n_0\,
S(2) => \weight[11][8]_i_3_n_0\,
S(1) => \weight[11][8]_i_4_n_0\,
S(0) => \weight[11][8]_i_5_n_0\
);
\weight_reg[11][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[11][8]_i_1_n_6\,
Q => \weight_reg[11]_10\(9)
);
\weight_reg[12][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_7\,
Q => \weight_reg[12]_11\(0)
);
\weight_reg[12][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[12][0]_i_1_n_0\,
CO(2) => \weight_reg[12][0]_i_1_n_1\,
CO(1) => \weight_reg[12][0]_i_1_n_2\,
CO(0) => \weight_reg[12][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_88\,
DI(2) => \ARG__21_n_89\,
DI(1) => \ARG__21_n_90\,
DI(0) => \ARG__21_n_91\,
O(3) => \weight_reg[12][0]_i_1_n_4\,
O(2) => \weight_reg[12][0]_i_1_n_5\,
O(1) => \weight_reg[12][0]_i_1_n_6\,
O(0) => \weight_reg[12][0]_i_1_n_7\,
S(3) => \weight[12][0]_i_2_n_0\,
S(2) => \weight[12][0]_i_3_n_0\,
S(1) => \weight[12][0]_i_4_n_0\,
S(0) => \weight[12][0]_i_5_n_0\
);
\weight_reg[12][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_5\,
Q => \weight_reg[12]_11\(10)
);
\weight_reg[12][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_4\,
Q => \weight_reg[12]_11\(11)
);
\weight_reg[12][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_7\,
Q => \weight_reg[12]_11\(12)
);
\weight_reg[12][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[12][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[12][12]_i_1_n_1\,
CO(1) => \weight_reg[12][12]_i_1_n_2\,
CO(0) => \weight_reg[12][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__21_n_77\,
DI(1) => \ARG__21_n_78\,
DI(0) => \ARG__21_n_79\,
O(3) => \weight_reg[12][12]_i_1_n_4\,
O(2) => \weight_reg[12][12]_i_1_n_5\,
O(1) => \weight_reg[12][12]_i_1_n_6\,
O(0) => \weight_reg[12][12]_i_1_n_7\,
S(3) => \weight[12][12]_i_2_n_0\,
S(2) => \weight[12][12]_i_3_n_0\,
S(1) => \weight[12][12]_i_4_n_0\,
S(0) => \weight[12][12]_i_5_n_0\
);
\weight_reg[12][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_6\,
Q => \weight_reg[12]_11\(13)
);
\weight_reg[12][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_5\,
Q => \weight_reg[12]_11\(14)
);
\weight_reg[12][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][12]_i_1_n_4\,
Q => \weight_reg[12]_11\(15)
);
\weight_reg[12][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_6\,
Q => \weight_reg[12]_11\(1)
);
\weight_reg[12][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_5\,
Q => \weight_reg[12]_11\(2)
);
\weight_reg[12][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][0]_i_1_n_4\,
Q => \weight_reg[12]_11\(3)
);
\weight_reg[12][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_7\,
Q => \weight_reg[12]_11\(4)
);
\weight_reg[12][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][0]_i_1_n_0\,
CO(3) => \weight_reg[12][4]_i_1_n_0\,
CO(2) => \weight_reg[12][4]_i_1_n_1\,
CO(1) => \weight_reg[12][4]_i_1_n_2\,
CO(0) => \weight_reg[12][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_84\,
DI(2) => \ARG__21_n_85\,
DI(1) => \ARG__21_n_86\,
DI(0) => \ARG__21_n_87\,
O(3) => \weight_reg[12][4]_i_1_n_4\,
O(2) => \weight_reg[12][4]_i_1_n_5\,
O(1) => \weight_reg[12][4]_i_1_n_6\,
O(0) => \weight_reg[12][4]_i_1_n_7\,
S(3) => \weight[12][4]_i_2_n_0\,
S(2) => \weight[12][4]_i_3_n_0\,
S(1) => \weight[12][4]_i_4_n_0\,
S(0) => \weight[12][4]_i_5_n_0\
);
\weight_reg[12][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_6\,
Q => \weight_reg[12]_11\(5)
);
\weight_reg[12][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_5\,
Q => \weight_reg[12]_11\(6)
);
\weight_reg[12][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][4]_i_1_n_4\,
Q => \weight_reg[12]_11\(7)
);
\weight_reg[12][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_7\,
Q => \weight_reg[12]_11\(8)
);
\weight_reg[12][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[12][4]_i_1_n_0\,
CO(3) => \weight_reg[12][8]_i_1_n_0\,
CO(2) => \weight_reg[12][8]_i_1_n_1\,
CO(1) => \weight_reg[12][8]_i_1_n_2\,
CO(0) => \weight_reg[12][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__21_n_80\,
DI(2) => \ARG__21_n_81\,
DI(1) => \ARG__21_n_82\,
DI(0) => \ARG__21_n_83\,
O(3) => \weight_reg[12][8]_i_1_n_4\,
O(2) => \weight_reg[12][8]_i_1_n_5\,
O(1) => \weight_reg[12][8]_i_1_n_6\,
O(0) => \weight_reg[12][8]_i_1_n_7\,
S(3) => \weight[12][8]_i_2_n_0\,
S(2) => \weight[12][8]_i_3_n_0\,
S(1) => \weight[12][8]_i_4_n_0\,
S(0) => \weight[12][8]_i_5_n_0\
);
\weight_reg[12][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[12][8]_i_1_n_6\,
Q => \weight_reg[12]_11\(9)
);
\weight_reg[13][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_7\,
Q => \weight_reg[13]_12\(0)
);
\weight_reg[13][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[13][0]_i_1_n_0\,
CO(2) => \weight_reg[13][0]_i_1_n_1\,
CO(1) => \weight_reg[13][0]_i_1_n_2\,
CO(0) => \weight_reg[13][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_88\,
DI(2) => \ARG__23_n_89\,
DI(1) => \ARG__23_n_90\,
DI(0) => \ARG__23_n_91\,
O(3) => \weight_reg[13][0]_i_1_n_4\,
O(2) => \weight_reg[13][0]_i_1_n_5\,
O(1) => \weight_reg[13][0]_i_1_n_6\,
O(0) => \weight_reg[13][0]_i_1_n_7\,
S(3) => \weight[13][0]_i_2_n_0\,
S(2) => \weight[13][0]_i_3_n_0\,
S(1) => \weight[13][0]_i_4_n_0\,
S(0) => \weight[13][0]_i_5_n_0\
);
\weight_reg[13][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_5\,
Q => \weight_reg[13]_12\(10)
);
\weight_reg[13][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_4\,
Q => \weight_reg[13]_12\(11)
);
\weight_reg[13][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_7\,
Q => \weight_reg[13]_12\(12)
);
\weight_reg[13][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[13][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[13][12]_i_1_n_1\,
CO(1) => \weight_reg[13][12]_i_1_n_2\,
CO(0) => \weight_reg[13][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__23_n_77\,
DI(1) => \ARG__23_n_78\,
DI(0) => \ARG__23_n_79\,
O(3) => \weight_reg[13][12]_i_1_n_4\,
O(2) => \weight_reg[13][12]_i_1_n_5\,
O(1) => \weight_reg[13][12]_i_1_n_6\,
O(0) => \weight_reg[13][12]_i_1_n_7\,
S(3) => \weight[13][12]_i_2_n_0\,
S(2) => \weight[13][12]_i_3_n_0\,
S(1) => \weight[13][12]_i_4_n_0\,
S(0) => \weight[13][12]_i_5_n_0\
);
\weight_reg[13][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_6\,
Q => \weight_reg[13]_12\(13)
);
\weight_reg[13][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_5\,
Q => \weight_reg[13]_12\(14)
);
\weight_reg[13][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][12]_i_1_n_4\,
Q => \weight_reg[13]_12\(15)
);
\weight_reg[13][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_6\,
Q => \weight_reg[13]_12\(1)
);
\weight_reg[13][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_5\,
Q => \weight_reg[13]_12\(2)
);
\weight_reg[13][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][0]_i_1_n_4\,
Q => \weight_reg[13]_12\(3)
);
\weight_reg[13][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_7\,
Q => \weight_reg[13]_12\(4)
);
\weight_reg[13][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][0]_i_1_n_0\,
CO(3) => \weight_reg[13][4]_i_1_n_0\,
CO(2) => \weight_reg[13][4]_i_1_n_1\,
CO(1) => \weight_reg[13][4]_i_1_n_2\,
CO(0) => \weight_reg[13][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_84\,
DI(2) => \ARG__23_n_85\,
DI(1) => \ARG__23_n_86\,
DI(0) => \ARG__23_n_87\,
O(3) => \weight_reg[13][4]_i_1_n_4\,
O(2) => \weight_reg[13][4]_i_1_n_5\,
O(1) => \weight_reg[13][4]_i_1_n_6\,
O(0) => \weight_reg[13][4]_i_1_n_7\,
S(3) => \weight[13][4]_i_2_n_0\,
S(2) => \weight[13][4]_i_3_n_0\,
S(1) => \weight[13][4]_i_4_n_0\,
S(0) => \weight[13][4]_i_5_n_0\
);
\weight_reg[13][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_6\,
Q => \weight_reg[13]_12\(5)
);
\weight_reg[13][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_5\,
Q => \weight_reg[13]_12\(6)
);
\weight_reg[13][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][4]_i_1_n_4\,
Q => \weight_reg[13]_12\(7)
);
\weight_reg[13][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_7\,
Q => \weight_reg[13]_12\(8)
);
\weight_reg[13][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[13][4]_i_1_n_0\,
CO(3) => \weight_reg[13][8]_i_1_n_0\,
CO(2) => \weight_reg[13][8]_i_1_n_1\,
CO(1) => \weight_reg[13][8]_i_1_n_2\,
CO(0) => \weight_reg[13][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__23_n_80\,
DI(2) => \ARG__23_n_81\,
DI(1) => \ARG__23_n_82\,
DI(0) => \ARG__23_n_83\,
O(3) => \weight_reg[13][8]_i_1_n_4\,
O(2) => \weight_reg[13][8]_i_1_n_5\,
O(1) => \weight_reg[13][8]_i_1_n_6\,
O(0) => \weight_reg[13][8]_i_1_n_7\,
S(3) => \weight[13][8]_i_2_n_0\,
S(2) => \weight[13][8]_i_3_n_0\,
S(1) => \weight[13][8]_i_4_n_0\,
S(0) => \weight[13][8]_i_5_n_0\
);
\weight_reg[13][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[13][8]_i_1_n_6\,
Q => \weight_reg[13]_12\(9)
);
\weight_reg[14][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_7\,
Q => \weight_reg[14]_13\(0)
);
\weight_reg[14][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[14][0]_i_1_n_0\,
CO(2) => \weight_reg[14][0]_i_1_n_1\,
CO(1) => \weight_reg[14][0]_i_1_n_2\,
CO(0) => \weight_reg[14][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_88\,
DI(2) => \ARG__25_n_89\,
DI(1) => \ARG__25_n_90\,
DI(0) => \ARG__25_n_91\,
O(3) => \weight_reg[14][0]_i_1_n_4\,
O(2) => \weight_reg[14][0]_i_1_n_5\,
O(1) => \weight_reg[14][0]_i_1_n_6\,
O(0) => \weight_reg[14][0]_i_1_n_7\,
S(3) => \weight[14][0]_i_2_n_0\,
S(2) => \weight[14][0]_i_3_n_0\,
S(1) => \weight[14][0]_i_4_n_0\,
S(0) => \weight[14][0]_i_5_n_0\
);
\weight_reg[14][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_5\,
Q => \weight_reg[14]_13\(10)
);
\weight_reg[14][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_4\,
Q => \weight_reg[14]_13\(11)
);
\weight_reg[14][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_7\,
Q => \weight_reg[14]_13\(12)
);
\weight_reg[14][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[14][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[14][12]_i_1_n_1\,
CO(1) => \weight_reg[14][12]_i_1_n_2\,
CO(0) => \weight_reg[14][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__25_n_77\,
DI(1) => \ARG__25_n_78\,
DI(0) => \ARG__25_n_79\,
O(3) => \weight_reg[14][12]_i_1_n_4\,
O(2) => \weight_reg[14][12]_i_1_n_5\,
O(1) => \weight_reg[14][12]_i_1_n_6\,
O(0) => \weight_reg[14][12]_i_1_n_7\,
S(3) => \weight[14][12]_i_2_n_0\,
S(2) => \weight[14][12]_i_3_n_0\,
S(1) => \weight[14][12]_i_4_n_0\,
S(0) => \weight[14][12]_i_5_n_0\
);
\weight_reg[14][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_6\,
Q => \weight_reg[14]_13\(13)
);
\weight_reg[14][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_5\,
Q => \weight_reg[14]_13\(14)
);
\weight_reg[14][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][12]_i_1_n_4\,
Q => \weight_reg[14]_13\(15)
);
\weight_reg[14][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_6\,
Q => \weight_reg[14]_13\(1)
);
\weight_reg[14][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_5\,
Q => \weight_reg[14]_13\(2)
);
\weight_reg[14][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][0]_i_1_n_4\,
Q => \weight_reg[14]_13\(3)
);
\weight_reg[14][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_7\,
Q => \weight_reg[14]_13\(4)
);
\weight_reg[14][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][0]_i_1_n_0\,
CO(3) => \weight_reg[14][4]_i_1_n_0\,
CO(2) => \weight_reg[14][4]_i_1_n_1\,
CO(1) => \weight_reg[14][4]_i_1_n_2\,
CO(0) => \weight_reg[14][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_84\,
DI(2) => \ARG__25_n_85\,
DI(1) => \ARG__25_n_86\,
DI(0) => \ARG__25_n_87\,
O(3) => \weight_reg[14][4]_i_1_n_4\,
O(2) => \weight_reg[14][4]_i_1_n_5\,
O(1) => \weight_reg[14][4]_i_1_n_6\,
O(0) => \weight_reg[14][4]_i_1_n_7\,
S(3) => \weight[14][4]_i_2_n_0\,
S(2) => \weight[14][4]_i_3_n_0\,
S(1) => \weight[14][4]_i_4_n_0\,
S(0) => \weight[14][4]_i_5_n_0\
);
\weight_reg[14][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_6\,
Q => \weight_reg[14]_13\(5)
);
\weight_reg[14][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_5\,
Q => \weight_reg[14]_13\(6)
);
\weight_reg[14][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][4]_i_1_n_4\,
Q => \weight_reg[14]_13\(7)
);
\weight_reg[14][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_7\,
Q => \weight_reg[14]_13\(8)
);
\weight_reg[14][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[14][4]_i_1_n_0\,
CO(3) => \weight_reg[14][8]_i_1_n_0\,
CO(2) => \weight_reg[14][8]_i_1_n_1\,
CO(1) => \weight_reg[14][8]_i_1_n_2\,
CO(0) => \weight_reg[14][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__25_n_80\,
DI(2) => \ARG__25_n_81\,
DI(1) => \ARG__25_n_82\,
DI(0) => \ARG__25_n_83\,
O(3) => \weight_reg[14][8]_i_1_n_4\,
O(2) => \weight_reg[14][8]_i_1_n_5\,
O(1) => \weight_reg[14][8]_i_1_n_6\,
O(0) => \weight_reg[14][8]_i_1_n_7\,
S(3) => \weight[14][8]_i_2_n_0\,
S(2) => \weight[14][8]_i_3_n_0\,
S(1) => \weight[14][8]_i_4_n_0\,
S(0) => \weight[14][8]_i_5_n_0\
);
\weight_reg[14][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[14][8]_i_1_n_6\,
Q => \weight_reg[14]_13\(9)
);
\weight_reg[15][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_7\,
Q => \weight_reg[15]_14\(0)
);
\weight_reg[15][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[15][0]_i_1_n_0\,
CO(2) => \weight_reg[15][0]_i_1_n_1\,
CO(1) => \weight_reg[15][0]_i_1_n_2\,
CO(0) => \weight_reg[15][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_88\,
DI(2) => \ARG__27_n_89\,
DI(1) => \ARG__27_n_90\,
DI(0) => \ARG__27_n_91\,
O(3) => \weight_reg[15][0]_i_1_n_4\,
O(2) => \weight_reg[15][0]_i_1_n_5\,
O(1) => \weight_reg[15][0]_i_1_n_6\,
O(0) => \weight_reg[15][0]_i_1_n_7\,
S(3) => \weight[15][0]_i_2_n_0\,
S(2) => \weight[15][0]_i_3_n_0\,
S(1) => \weight[15][0]_i_4_n_0\,
S(0) => \weight[15][0]_i_5_n_0\
);
\weight_reg[15][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_5\,
Q => \weight_reg[15]_14\(10)
);
\weight_reg[15][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_4\,
Q => \weight_reg[15]_14\(11)
);
\weight_reg[15][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_7\,
Q => \weight_reg[15]_14\(12)
);
\weight_reg[15][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[15][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[15][12]_i_1_n_1\,
CO(1) => \weight_reg[15][12]_i_1_n_2\,
CO(0) => \weight_reg[15][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__27_n_77\,
DI(1) => \ARG__27_n_78\,
DI(0) => \ARG__27_n_79\,
O(3) => \weight_reg[15][12]_i_1_n_4\,
O(2) => \weight_reg[15][12]_i_1_n_5\,
O(1) => \weight_reg[15][12]_i_1_n_6\,
O(0) => \weight_reg[15][12]_i_1_n_7\,
S(3) => \weight[15][12]_i_2_n_0\,
S(2) => \weight[15][12]_i_3_n_0\,
S(1) => \weight[15][12]_i_4_n_0\,
S(0) => \weight[15][12]_i_5_n_0\
);
\weight_reg[15][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_6\,
Q => \weight_reg[15]_14\(13)
);
\weight_reg[15][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_5\,
Q => \weight_reg[15]_14\(14)
);
\weight_reg[15][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][12]_i_1_n_4\,
Q => \weight_reg[15]_14\(15)
);
\weight_reg[15][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_6\,
Q => \weight_reg[15]_14\(1)
);
\weight_reg[15][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_5\,
Q => \weight_reg[15]_14\(2)
);
\weight_reg[15][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][0]_i_1_n_4\,
Q => \weight_reg[15]_14\(3)
);
\weight_reg[15][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_7\,
Q => \weight_reg[15]_14\(4)
);
\weight_reg[15][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][0]_i_1_n_0\,
CO(3) => \weight_reg[15][4]_i_1_n_0\,
CO(2) => \weight_reg[15][4]_i_1_n_1\,
CO(1) => \weight_reg[15][4]_i_1_n_2\,
CO(0) => \weight_reg[15][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_84\,
DI(2) => \ARG__27_n_85\,
DI(1) => \ARG__27_n_86\,
DI(0) => \ARG__27_n_87\,
O(3) => \weight_reg[15][4]_i_1_n_4\,
O(2) => \weight_reg[15][4]_i_1_n_5\,
O(1) => \weight_reg[15][4]_i_1_n_6\,
O(0) => \weight_reg[15][4]_i_1_n_7\,
S(3) => \weight[15][4]_i_2_n_0\,
S(2) => \weight[15][4]_i_3_n_0\,
S(1) => \weight[15][4]_i_4_n_0\,
S(0) => \weight[15][4]_i_5_n_0\
);
\weight_reg[15][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_6\,
Q => \weight_reg[15]_14\(5)
);
\weight_reg[15][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_5\,
Q => \weight_reg[15]_14\(6)
);
\weight_reg[15][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][4]_i_1_n_4\,
Q => \weight_reg[15]_14\(7)
);
\weight_reg[15][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_7\,
Q => \weight_reg[15]_14\(8)
);
\weight_reg[15][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[15][4]_i_1_n_0\,
CO(3) => \weight_reg[15][8]_i_1_n_0\,
CO(2) => \weight_reg[15][8]_i_1_n_1\,
CO(1) => \weight_reg[15][8]_i_1_n_2\,
CO(0) => \weight_reg[15][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__27_n_80\,
DI(2) => \ARG__27_n_81\,
DI(1) => \ARG__27_n_82\,
DI(0) => \ARG__27_n_83\,
O(3) => \weight_reg[15][8]_i_1_n_4\,
O(2) => \weight_reg[15][8]_i_1_n_5\,
O(1) => \weight_reg[15][8]_i_1_n_6\,
O(0) => \weight_reg[15][8]_i_1_n_7\,
S(3) => \weight[15][8]_i_2_n_0\,
S(2) => \weight[15][8]_i_3_n_0\,
S(1) => \weight[15][8]_i_4_n_0\,
S(0) => \weight[15][8]_i_5_n_0\
);
\weight_reg[15][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[15][8]_i_1_n_6\,
Q => \weight_reg[15]_14\(9)
);
\weight_reg[1][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_7\,
Q => \weight_reg[1]_0\(0)
);
\weight_reg[1][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[1][0]_i_1_n_0\,
CO(2) => \weight_reg[1][0]_i_1_n_1\,
CO(1) => \weight_reg[1][0]_i_1_n_2\,
CO(0) => \weight_reg[1][0]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(3 downto 0),
O(3) => \weight_reg[1][0]_i_1_n_4\,
O(2) => \weight_reg[1][0]_i_1_n_5\,
O(1) => \weight_reg[1][0]_i_1_n_6\,
O(0) => \weight_reg[1][0]_i_1_n_7\,
S(3) => \weight[1][0]_i_2_n_0\,
S(2) => \weight[1][0]_i_3_n_0\,
S(1) => \weight[1][0]_i_4_n_0\,
S(0) => \weight[1][0]_i_5_n_0\
);
\weight_reg[1][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_5\,
Q => \weight_reg[1]_0\(10)
);
\weight_reg[1][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_4\,
Q => \weight_reg[1]_0\(11)
);
\weight_reg[1][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_7\,
Q => \weight_reg[1]_0\(12)
);
\weight_reg[1][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[1][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[1][12]_i_1_n_1\,
CO(1) => \weight_reg[1][12]_i_1_n_2\,
CO(0) => \weight_reg[1][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2 downto 0) => \in\(14 downto 12),
O(3) => \weight_reg[1][12]_i_1_n_4\,
O(2) => \weight_reg[1][12]_i_1_n_5\,
O(1) => \weight_reg[1][12]_i_1_n_6\,
O(0) => \weight_reg[1][12]_i_1_n_7\,
S(3) => \weight[1][12]_i_2_n_0\,
S(2) => \weight[1][12]_i_3_n_0\,
S(1) => \weight[1][12]_i_4_n_0\,
S(0) => \weight[1][12]_i_5_n_0\
);
\weight_reg[1][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_6\,
Q => \weight_reg[1]_0\(13)
);
\weight_reg[1][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_5\,
Q => \weight_reg[1]_0\(14)
);
\weight_reg[1][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][12]_i_1_n_4\,
Q => \weight_reg[1]_0\(15)
);
\weight_reg[1][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_6\,
Q => \weight_reg[1]_0\(1)
);
\weight_reg[1][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_5\,
Q => \weight_reg[1]_0\(2)
);
\weight_reg[1][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][0]_i_1_n_4\,
Q => \weight_reg[1]_0\(3)
);
\weight_reg[1][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_7\,
Q => \weight_reg[1]_0\(4)
);
\weight_reg[1][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][0]_i_1_n_0\,
CO(3) => \weight_reg[1][4]_i_1_n_0\,
CO(2) => \weight_reg[1][4]_i_1_n_1\,
CO(1) => \weight_reg[1][4]_i_1_n_2\,
CO(0) => \weight_reg[1][4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(7 downto 4),
O(3) => \weight_reg[1][4]_i_1_n_4\,
O(2) => \weight_reg[1][4]_i_1_n_5\,
O(1) => \weight_reg[1][4]_i_1_n_6\,
O(0) => \weight_reg[1][4]_i_1_n_7\,
S(3) => \weight[1][4]_i_2_n_0\,
S(2) => \weight[1][4]_i_3_n_0\,
S(1) => \weight[1][4]_i_4_n_0\,
S(0) => \weight[1][4]_i_5_n_0\
);
\weight_reg[1][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_6\,
Q => \weight_reg[1]_0\(5)
);
\weight_reg[1][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_5\,
Q => \weight_reg[1]_0\(6)
);
\weight_reg[1][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][4]_i_1_n_4\,
Q => \weight_reg[1]_0\(7)
);
\weight_reg[1][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_7\,
Q => \weight_reg[1]_0\(8)
);
\weight_reg[1][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[1][4]_i_1_n_0\,
CO(3) => \weight_reg[1][8]_i_1_n_0\,
CO(2) => \weight_reg[1][8]_i_1_n_1\,
CO(1) => \weight_reg[1][8]_i_1_n_2\,
CO(0) => \weight_reg[1][8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => \in\(11 downto 8),
O(3) => \weight_reg[1][8]_i_1_n_4\,
O(2) => \weight_reg[1][8]_i_1_n_5\,
O(1) => \weight_reg[1][8]_i_1_n_6\,
O(0) => \weight_reg[1][8]_i_1_n_7\,
S(3) => \weight[1][8]_i_2_n_0\,
S(2) => \weight[1][8]_i_3_n_0\,
S(1) => \weight[1][8]_i_4_n_0\,
S(0) => \weight[1][8]_i_5_n_0\
);
\weight_reg[1][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[1][8]_i_1_n_6\,
Q => \weight_reg[1]_0\(9)
);
\weight_reg[2][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_7\,
Q => \weight_reg[2]_1\(0)
);
\weight_reg[2][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[2][0]_i_1_n_0\,
CO(2) => \weight_reg[2][0]_i_1_n_1\,
CO(1) => \weight_reg[2][0]_i_1_n_2\,
CO(0) => \weight_reg[2][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_88\,
DI(2) => \ARG__1_n_89\,
DI(1) => \ARG__1_n_90\,
DI(0) => \ARG__1_n_91\,
O(3) => \weight_reg[2][0]_i_1_n_4\,
O(2) => \weight_reg[2][0]_i_1_n_5\,
O(1) => \weight_reg[2][0]_i_1_n_6\,
O(0) => \weight_reg[2][0]_i_1_n_7\,
S(3) => \weight[2][0]_i_2_n_0\,
S(2) => \weight[2][0]_i_3_n_0\,
S(1) => \weight[2][0]_i_4_n_0\,
S(0) => \weight[2][0]_i_5_n_0\
);
\weight_reg[2][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_5\,
Q => \weight_reg[2]_1\(10)
);
\weight_reg[2][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_4\,
Q => \weight_reg[2]_1\(11)
);
\weight_reg[2][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_7\,
Q => \weight_reg[2]_1\(12)
);
\weight_reg[2][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[2][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[2][12]_i_1_n_1\,
CO(1) => \weight_reg[2][12]_i_1_n_2\,
CO(0) => \weight_reg[2][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__1_n_77\,
DI(1) => \ARG__1_n_78\,
DI(0) => \ARG__1_n_79\,
O(3) => \weight_reg[2][12]_i_1_n_4\,
O(2) => \weight_reg[2][12]_i_1_n_5\,
O(1) => \weight_reg[2][12]_i_1_n_6\,
O(0) => \weight_reg[2][12]_i_1_n_7\,
S(3) => \weight[2][12]_i_2_n_0\,
S(2) => \weight[2][12]_i_3_n_0\,
S(1) => \weight[2][12]_i_4_n_0\,
S(0) => \weight[2][12]_i_5_n_0\
);
\weight_reg[2][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_6\,
Q => \weight_reg[2]_1\(13)
);
\weight_reg[2][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_5\,
Q => \weight_reg[2]_1\(14)
);
\weight_reg[2][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][12]_i_1_n_4\,
Q => \weight_reg[2]_1\(15)
);
\weight_reg[2][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_6\,
Q => \weight_reg[2]_1\(1)
);
\weight_reg[2][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_5\,
Q => \weight_reg[2]_1\(2)
);
\weight_reg[2][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][0]_i_1_n_4\,
Q => \weight_reg[2]_1\(3)
);
\weight_reg[2][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_7\,
Q => \weight_reg[2]_1\(4)
);
\weight_reg[2][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][0]_i_1_n_0\,
CO(3) => \weight_reg[2][4]_i_1_n_0\,
CO(2) => \weight_reg[2][4]_i_1_n_1\,
CO(1) => \weight_reg[2][4]_i_1_n_2\,
CO(0) => \weight_reg[2][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_84\,
DI(2) => \ARG__1_n_85\,
DI(1) => \ARG__1_n_86\,
DI(0) => \ARG__1_n_87\,
O(3) => \weight_reg[2][4]_i_1_n_4\,
O(2) => \weight_reg[2][4]_i_1_n_5\,
O(1) => \weight_reg[2][4]_i_1_n_6\,
O(0) => \weight_reg[2][4]_i_1_n_7\,
S(3) => \weight[2][4]_i_2_n_0\,
S(2) => \weight[2][4]_i_3_n_0\,
S(1) => \weight[2][4]_i_4_n_0\,
S(0) => \weight[2][4]_i_5_n_0\
);
\weight_reg[2][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_6\,
Q => \weight_reg[2]_1\(5)
);
\weight_reg[2][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_5\,
Q => \weight_reg[2]_1\(6)
);
\weight_reg[2][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][4]_i_1_n_4\,
Q => \weight_reg[2]_1\(7)
);
\weight_reg[2][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_7\,
Q => \weight_reg[2]_1\(8)
);
\weight_reg[2][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[2][4]_i_1_n_0\,
CO(3) => \weight_reg[2][8]_i_1_n_0\,
CO(2) => \weight_reg[2][8]_i_1_n_1\,
CO(1) => \weight_reg[2][8]_i_1_n_2\,
CO(0) => \weight_reg[2][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__1_n_80\,
DI(2) => \ARG__1_n_81\,
DI(1) => \ARG__1_n_82\,
DI(0) => \ARG__1_n_83\,
O(3) => \weight_reg[2][8]_i_1_n_4\,
O(2) => \weight_reg[2][8]_i_1_n_5\,
O(1) => \weight_reg[2][8]_i_1_n_6\,
O(0) => \weight_reg[2][8]_i_1_n_7\,
S(3) => \weight[2][8]_i_2_n_0\,
S(2) => \weight[2][8]_i_3_n_0\,
S(1) => \weight[2][8]_i_4_n_0\,
S(0) => \weight[2][8]_i_5_n_0\
);
\weight_reg[2][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[2][8]_i_1_n_6\,
Q => \weight_reg[2]_1\(9)
);
\weight_reg[3][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_7\,
Q => \weight_reg[3]_2\(0)
);
\weight_reg[3][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[3][0]_i_1_n_0\,
CO(2) => \weight_reg[3][0]_i_1_n_1\,
CO(1) => \weight_reg[3][0]_i_1_n_2\,
CO(0) => \weight_reg[3][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_88\,
DI(2) => \ARG__3_n_89\,
DI(1) => \ARG__3_n_90\,
DI(0) => \ARG__3_n_91\,
O(3) => \weight_reg[3][0]_i_1_n_4\,
O(2) => \weight_reg[3][0]_i_1_n_5\,
O(1) => \weight_reg[3][0]_i_1_n_6\,
O(0) => \weight_reg[3][0]_i_1_n_7\,
S(3) => \weight[3][0]_i_2_n_0\,
S(2) => \weight[3][0]_i_3_n_0\,
S(1) => \weight[3][0]_i_4_n_0\,
S(0) => \weight[3][0]_i_5_n_0\
);
\weight_reg[3][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_5\,
Q => \weight_reg[3]_2\(10)
);
\weight_reg[3][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_4\,
Q => \weight_reg[3]_2\(11)
);
\weight_reg[3][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_7\,
Q => \weight_reg[3]_2\(12)
);
\weight_reg[3][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[3][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[3][12]_i_1_n_1\,
CO(1) => \weight_reg[3][12]_i_1_n_2\,
CO(0) => \weight_reg[3][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__3_n_77\,
DI(1) => \ARG__3_n_78\,
DI(0) => \ARG__3_n_79\,
O(3) => \weight_reg[3][12]_i_1_n_4\,
O(2) => \weight_reg[3][12]_i_1_n_5\,
O(1) => \weight_reg[3][12]_i_1_n_6\,
O(0) => \weight_reg[3][12]_i_1_n_7\,
S(3) => \weight[3][12]_i_2_n_0\,
S(2) => \weight[3][12]_i_3_n_0\,
S(1) => \weight[3][12]_i_4_n_0\,
S(0) => \weight[3][12]_i_5_n_0\
);
\weight_reg[3][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_6\,
Q => \weight_reg[3]_2\(13)
);
\weight_reg[3][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_5\,
Q => \weight_reg[3]_2\(14)
);
\weight_reg[3][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][12]_i_1_n_4\,
Q => \weight_reg[3]_2\(15)
);
\weight_reg[3][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_6\,
Q => \weight_reg[3]_2\(1)
);
\weight_reg[3][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_5\,
Q => \weight_reg[3]_2\(2)
);
\weight_reg[3][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][0]_i_1_n_4\,
Q => \weight_reg[3]_2\(3)
);
\weight_reg[3][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_7\,
Q => \weight_reg[3]_2\(4)
);
\weight_reg[3][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][0]_i_1_n_0\,
CO(3) => \weight_reg[3][4]_i_1_n_0\,
CO(2) => \weight_reg[3][4]_i_1_n_1\,
CO(1) => \weight_reg[3][4]_i_1_n_2\,
CO(0) => \weight_reg[3][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_84\,
DI(2) => \ARG__3_n_85\,
DI(1) => \ARG__3_n_86\,
DI(0) => \ARG__3_n_87\,
O(3) => \weight_reg[3][4]_i_1_n_4\,
O(2) => \weight_reg[3][4]_i_1_n_5\,
O(1) => \weight_reg[3][4]_i_1_n_6\,
O(0) => \weight_reg[3][4]_i_1_n_7\,
S(3) => \weight[3][4]_i_2_n_0\,
S(2) => \weight[3][4]_i_3_n_0\,
S(1) => \weight[3][4]_i_4_n_0\,
S(0) => \weight[3][4]_i_5_n_0\
);
\weight_reg[3][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_6\,
Q => \weight_reg[3]_2\(5)
);
\weight_reg[3][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_5\,
Q => \weight_reg[3]_2\(6)
);
\weight_reg[3][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][4]_i_1_n_4\,
Q => \weight_reg[3]_2\(7)
);
\weight_reg[3][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_7\,
Q => \weight_reg[3]_2\(8)
);
\weight_reg[3][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[3][4]_i_1_n_0\,
CO(3) => \weight_reg[3][8]_i_1_n_0\,
CO(2) => \weight_reg[3][8]_i_1_n_1\,
CO(1) => \weight_reg[3][8]_i_1_n_2\,
CO(0) => \weight_reg[3][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__3_n_80\,
DI(2) => \ARG__3_n_81\,
DI(1) => \ARG__3_n_82\,
DI(0) => \ARG__3_n_83\,
O(3) => \weight_reg[3][8]_i_1_n_4\,
O(2) => \weight_reg[3][8]_i_1_n_5\,
O(1) => \weight_reg[3][8]_i_1_n_6\,
O(0) => \weight_reg[3][8]_i_1_n_7\,
S(3) => \weight[3][8]_i_2_n_0\,
S(2) => \weight[3][8]_i_3_n_0\,
S(1) => \weight[3][8]_i_4_n_0\,
S(0) => \weight[3][8]_i_5_n_0\
);
\weight_reg[3][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[3][8]_i_1_n_6\,
Q => \weight_reg[3]_2\(9)
);
\weight_reg[4][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_7\,
Q => \weight_reg[4]_3\(0)
);
\weight_reg[4][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[4][0]_i_1_n_0\,
CO(2) => \weight_reg[4][0]_i_1_n_1\,
CO(1) => \weight_reg[4][0]_i_1_n_2\,
CO(0) => \weight_reg[4][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_88\,
DI(2) => \ARG__5_n_89\,
DI(1) => \ARG__5_n_90\,
DI(0) => \ARG__5_n_91\,
O(3) => \weight_reg[4][0]_i_1_n_4\,
O(2) => \weight_reg[4][0]_i_1_n_5\,
O(1) => \weight_reg[4][0]_i_1_n_6\,
O(0) => \weight_reg[4][0]_i_1_n_7\,
S(3) => \weight[4][0]_i_2_n_0\,
S(2) => \weight[4][0]_i_3_n_0\,
S(1) => \weight[4][0]_i_4_n_0\,
S(0) => \weight[4][0]_i_5_n_0\
);
\weight_reg[4][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_5\,
Q => \weight_reg[4]_3\(10)
);
\weight_reg[4][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_4\,
Q => \weight_reg[4]_3\(11)
);
\weight_reg[4][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_7\,
Q => \weight_reg[4]_3\(12)
);
\weight_reg[4][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[4][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[4][12]_i_1_n_1\,
CO(1) => \weight_reg[4][12]_i_1_n_2\,
CO(0) => \weight_reg[4][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__5_n_77\,
DI(1) => \ARG__5_n_78\,
DI(0) => \ARG__5_n_79\,
O(3) => \weight_reg[4][12]_i_1_n_4\,
O(2) => \weight_reg[4][12]_i_1_n_5\,
O(1) => \weight_reg[4][12]_i_1_n_6\,
O(0) => \weight_reg[4][12]_i_1_n_7\,
S(3) => \weight[4][12]_i_2_n_0\,
S(2) => \weight[4][12]_i_3_n_0\,
S(1) => \weight[4][12]_i_4_n_0\,
S(0) => \weight[4][12]_i_5_n_0\
);
\weight_reg[4][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_6\,
Q => \weight_reg[4]_3\(13)
);
\weight_reg[4][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_5\,
Q => \weight_reg[4]_3\(14)
);
\weight_reg[4][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][12]_i_1_n_4\,
Q => \weight_reg[4]_3\(15)
);
\weight_reg[4][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_6\,
Q => \weight_reg[4]_3\(1)
);
\weight_reg[4][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_5\,
Q => \weight_reg[4]_3\(2)
);
\weight_reg[4][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][0]_i_1_n_4\,
Q => \weight_reg[4]_3\(3)
);
\weight_reg[4][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_7\,
Q => \weight_reg[4]_3\(4)
);
\weight_reg[4][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][0]_i_1_n_0\,
CO(3) => \weight_reg[4][4]_i_1_n_0\,
CO(2) => \weight_reg[4][4]_i_1_n_1\,
CO(1) => \weight_reg[4][4]_i_1_n_2\,
CO(0) => \weight_reg[4][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_84\,
DI(2) => \ARG__5_n_85\,
DI(1) => \ARG__5_n_86\,
DI(0) => \ARG__5_n_87\,
O(3) => \weight_reg[4][4]_i_1_n_4\,
O(2) => \weight_reg[4][4]_i_1_n_5\,
O(1) => \weight_reg[4][4]_i_1_n_6\,
O(0) => \weight_reg[4][4]_i_1_n_7\,
S(3) => \weight[4][4]_i_2_n_0\,
S(2) => \weight[4][4]_i_3_n_0\,
S(1) => \weight[4][4]_i_4_n_0\,
S(0) => \weight[4][4]_i_5_n_0\
);
\weight_reg[4][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_6\,
Q => \weight_reg[4]_3\(5)
);
\weight_reg[4][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_5\,
Q => \weight_reg[4]_3\(6)
);
\weight_reg[4][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][4]_i_1_n_4\,
Q => \weight_reg[4]_3\(7)
);
\weight_reg[4][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_7\,
Q => \weight_reg[4]_3\(8)
);
\weight_reg[4][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[4][4]_i_1_n_0\,
CO(3) => \weight_reg[4][8]_i_1_n_0\,
CO(2) => \weight_reg[4][8]_i_1_n_1\,
CO(1) => \weight_reg[4][8]_i_1_n_2\,
CO(0) => \weight_reg[4][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__5_n_80\,
DI(2) => \ARG__5_n_81\,
DI(1) => \ARG__5_n_82\,
DI(0) => \ARG__5_n_83\,
O(3) => \weight_reg[4][8]_i_1_n_4\,
O(2) => \weight_reg[4][8]_i_1_n_5\,
O(1) => \weight_reg[4][8]_i_1_n_6\,
O(0) => \weight_reg[4][8]_i_1_n_7\,
S(3) => \weight[4][8]_i_2_n_0\,
S(2) => \weight[4][8]_i_3_n_0\,
S(1) => \weight[4][8]_i_4_n_0\,
S(0) => \weight[4][8]_i_5_n_0\
);
\weight_reg[4][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[4][8]_i_1_n_6\,
Q => \weight_reg[4]_3\(9)
);
\weight_reg[5][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_7\,
Q => \weight_reg[5]_4\(0)
);
\weight_reg[5][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[5][0]_i_1_n_0\,
CO(2) => \weight_reg[5][0]_i_1_n_1\,
CO(1) => \weight_reg[5][0]_i_1_n_2\,
CO(0) => \weight_reg[5][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_88\,
DI(2) => \ARG__7_n_89\,
DI(1) => \ARG__7_n_90\,
DI(0) => \ARG__7_n_91\,
O(3) => \weight_reg[5][0]_i_1_n_4\,
O(2) => \weight_reg[5][0]_i_1_n_5\,
O(1) => \weight_reg[5][0]_i_1_n_6\,
O(0) => \weight_reg[5][0]_i_1_n_7\,
S(3) => \weight[5][0]_i_2_n_0\,
S(2) => \weight[5][0]_i_3_n_0\,
S(1) => \weight[5][0]_i_4_n_0\,
S(0) => \weight[5][0]_i_5_n_0\
);
\weight_reg[5][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_5\,
Q => \weight_reg[5]_4\(10)
);
\weight_reg[5][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_4\,
Q => \weight_reg[5]_4\(11)
);
\weight_reg[5][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_7\,
Q => \weight_reg[5]_4\(12)
);
\weight_reg[5][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[5][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[5][12]_i_1_n_1\,
CO(1) => \weight_reg[5][12]_i_1_n_2\,
CO(0) => \weight_reg[5][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__7_n_77\,
DI(1) => \ARG__7_n_78\,
DI(0) => \ARG__7_n_79\,
O(3) => \weight_reg[5][12]_i_1_n_4\,
O(2) => \weight_reg[5][12]_i_1_n_5\,
O(1) => \weight_reg[5][12]_i_1_n_6\,
O(0) => \weight_reg[5][12]_i_1_n_7\,
S(3) => \weight[5][12]_i_2_n_0\,
S(2) => \weight[5][12]_i_3_n_0\,
S(1) => \weight[5][12]_i_4_n_0\,
S(0) => \weight[5][12]_i_5_n_0\
);
\weight_reg[5][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_6\,
Q => \weight_reg[5]_4\(13)
);
\weight_reg[5][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_5\,
Q => \weight_reg[5]_4\(14)
);
\weight_reg[5][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][12]_i_1_n_4\,
Q => \weight_reg[5]_4\(15)
);
\weight_reg[5][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_6\,
Q => \weight_reg[5]_4\(1)
);
\weight_reg[5][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_5\,
Q => \weight_reg[5]_4\(2)
);
\weight_reg[5][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][0]_i_1_n_4\,
Q => \weight_reg[5]_4\(3)
);
\weight_reg[5][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_7\,
Q => \weight_reg[5]_4\(4)
);
\weight_reg[5][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][0]_i_1_n_0\,
CO(3) => \weight_reg[5][4]_i_1_n_0\,
CO(2) => \weight_reg[5][4]_i_1_n_1\,
CO(1) => \weight_reg[5][4]_i_1_n_2\,
CO(0) => \weight_reg[5][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_84\,
DI(2) => \ARG__7_n_85\,
DI(1) => \ARG__7_n_86\,
DI(0) => \ARG__7_n_87\,
O(3) => \weight_reg[5][4]_i_1_n_4\,
O(2) => \weight_reg[5][4]_i_1_n_5\,
O(1) => \weight_reg[5][4]_i_1_n_6\,
O(0) => \weight_reg[5][4]_i_1_n_7\,
S(3) => \weight[5][4]_i_2_n_0\,
S(2) => \weight[5][4]_i_3_n_0\,
S(1) => \weight[5][4]_i_4_n_0\,
S(0) => \weight[5][4]_i_5_n_0\
);
\weight_reg[5][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_6\,
Q => \weight_reg[5]_4\(5)
);
\weight_reg[5][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_5\,
Q => \weight_reg[5]_4\(6)
);
\weight_reg[5][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][4]_i_1_n_4\,
Q => \weight_reg[5]_4\(7)
);
\weight_reg[5][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_7\,
Q => \weight_reg[5]_4\(8)
);
\weight_reg[5][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[5][4]_i_1_n_0\,
CO(3) => \weight_reg[5][8]_i_1_n_0\,
CO(2) => \weight_reg[5][8]_i_1_n_1\,
CO(1) => \weight_reg[5][8]_i_1_n_2\,
CO(0) => \weight_reg[5][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__7_n_80\,
DI(2) => \ARG__7_n_81\,
DI(1) => \ARG__7_n_82\,
DI(0) => \ARG__7_n_83\,
O(3) => \weight_reg[5][8]_i_1_n_4\,
O(2) => \weight_reg[5][8]_i_1_n_5\,
O(1) => \weight_reg[5][8]_i_1_n_6\,
O(0) => \weight_reg[5][8]_i_1_n_7\,
S(3) => \weight[5][8]_i_2_n_0\,
S(2) => \weight[5][8]_i_3_n_0\,
S(1) => \weight[5][8]_i_4_n_0\,
S(0) => \weight[5][8]_i_5_n_0\
);
\weight_reg[5][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[5][8]_i_1_n_6\,
Q => \weight_reg[5]_4\(9)
);
\weight_reg[6][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_7\,
Q => \weight_reg[6]_5\(0)
);
\weight_reg[6][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[6][0]_i_1_n_0\,
CO(2) => \weight_reg[6][0]_i_1_n_1\,
CO(1) => \weight_reg[6][0]_i_1_n_2\,
CO(0) => \weight_reg[6][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_88\,
DI(2) => \ARG__9_n_89\,
DI(1) => \ARG__9_n_90\,
DI(0) => \ARG__9_n_91\,
O(3) => \weight_reg[6][0]_i_1_n_4\,
O(2) => \weight_reg[6][0]_i_1_n_5\,
O(1) => \weight_reg[6][0]_i_1_n_6\,
O(0) => \weight_reg[6][0]_i_1_n_7\,
S(3) => \weight[6][0]_i_2_n_0\,
S(2) => \weight[6][0]_i_3_n_0\,
S(1) => \weight[6][0]_i_4_n_0\,
S(0) => \weight[6][0]_i_5_n_0\
);
\weight_reg[6][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_5\,
Q => \weight_reg[6]_5\(10)
);
\weight_reg[6][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_4\,
Q => \weight_reg[6]_5\(11)
);
\weight_reg[6][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_7\,
Q => \weight_reg[6]_5\(12)
);
\weight_reg[6][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[6][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[6][12]_i_1_n_1\,
CO(1) => \weight_reg[6][12]_i_1_n_2\,
CO(0) => \weight_reg[6][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__9_n_77\,
DI(1) => \ARG__9_n_78\,
DI(0) => \ARG__9_n_79\,
O(3) => \weight_reg[6][12]_i_1_n_4\,
O(2) => \weight_reg[6][12]_i_1_n_5\,
O(1) => \weight_reg[6][12]_i_1_n_6\,
O(0) => \weight_reg[6][12]_i_1_n_7\,
S(3) => \weight[6][12]_i_2_n_0\,
S(2) => \weight[6][12]_i_3_n_0\,
S(1) => \weight[6][12]_i_4_n_0\,
S(0) => \weight[6][12]_i_5_n_0\
);
\weight_reg[6][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_6\,
Q => \weight_reg[6]_5\(13)
);
\weight_reg[6][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_5\,
Q => \weight_reg[6]_5\(14)
);
\weight_reg[6][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][12]_i_1_n_4\,
Q => \weight_reg[6]_5\(15)
);
\weight_reg[6][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_6\,
Q => \weight_reg[6]_5\(1)
);
\weight_reg[6][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_5\,
Q => \weight_reg[6]_5\(2)
);
\weight_reg[6][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][0]_i_1_n_4\,
Q => \weight_reg[6]_5\(3)
);
\weight_reg[6][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_7\,
Q => \weight_reg[6]_5\(4)
);
\weight_reg[6][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][0]_i_1_n_0\,
CO(3) => \weight_reg[6][4]_i_1_n_0\,
CO(2) => \weight_reg[6][4]_i_1_n_1\,
CO(1) => \weight_reg[6][4]_i_1_n_2\,
CO(0) => \weight_reg[6][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_84\,
DI(2) => \ARG__9_n_85\,
DI(1) => \ARG__9_n_86\,
DI(0) => \ARG__9_n_87\,
O(3) => \weight_reg[6][4]_i_1_n_4\,
O(2) => \weight_reg[6][4]_i_1_n_5\,
O(1) => \weight_reg[6][4]_i_1_n_6\,
O(0) => \weight_reg[6][4]_i_1_n_7\,
S(3) => \weight[6][4]_i_2_n_0\,
S(2) => \weight[6][4]_i_3_n_0\,
S(1) => \weight[6][4]_i_4_n_0\,
S(0) => \weight[6][4]_i_5_n_0\
);
\weight_reg[6][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_6\,
Q => \weight_reg[6]_5\(5)
);
\weight_reg[6][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_5\,
Q => \weight_reg[6]_5\(6)
);
\weight_reg[6][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][4]_i_1_n_4\,
Q => \weight_reg[6]_5\(7)
);
\weight_reg[6][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_7\,
Q => \weight_reg[6]_5\(8)
);
\weight_reg[6][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[6][4]_i_1_n_0\,
CO(3) => \weight_reg[6][8]_i_1_n_0\,
CO(2) => \weight_reg[6][8]_i_1_n_1\,
CO(1) => \weight_reg[6][8]_i_1_n_2\,
CO(0) => \weight_reg[6][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__9_n_80\,
DI(2) => \ARG__9_n_81\,
DI(1) => \ARG__9_n_82\,
DI(0) => \ARG__9_n_83\,
O(3) => \weight_reg[6][8]_i_1_n_4\,
O(2) => \weight_reg[6][8]_i_1_n_5\,
O(1) => \weight_reg[6][8]_i_1_n_6\,
O(0) => \weight_reg[6][8]_i_1_n_7\,
S(3) => \weight[6][8]_i_2_n_0\,
S(2) => \weight[6][8]_i_3_n_0\,
S(1) => \weight[6][8]_i_4_n_0\,
S(0) => \weight[6][8]_i_5_n_0\
);
\weight_reg[6][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[6][8]_i_1_n_6\,
Q => \weight_reg[6]_5\(9)
);
\weight_reg[7][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_7\,
Q => \weight_reg[7]_6\(0)
);
\weight_reg[7][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[7][0]_i_1_n_0\,
CO(2) => \weight_reg[7][0]_i_1_n_1\,
CO(1) => \weight_reg[7][0]_i_1_n_2\,
CO(0) => \weight_reg[7][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_88\,
DI(2) => \ARG__11_n_89\,
DI(1) => \ARG__11_n_90\,
DI(0) => \ARG__11_n_91\,
O(3) => \weight_reg[7][0]_i_1_n_4\,
O(2) => \weight_reg[7][0]_i_1_n_5\,
O(1) => \weight_reg[7][0]_i_1_n_6\,
O(0) => \weight_reg[7][0]_i_1_n_7\,
S(3) => \weight[7][0]_i_2_n_0\,
S(2) => \weight[7][0]_i_3_n_0\,
S(1) => \weight[7][0]_i_4_n_0\,
S(0) => \weight[7][0]_i_5_n_0\
);
\weight_reg[7][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_5\,
Q => \weight_reg[7]_6\(10)
);
\weight_reg[7][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_4\,
Q => \weight_reg[7]_6\(11)
);
\weight_reg[7][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_7\,
Q => \weight_reg[7]_6\(12)
);
\weight_reg[7][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[7][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[7][12]_i_1_n_1\,
CO(1) => \weight_reg[7][12]_i_1_n_2\,
CO(0) => \weight_reg[7][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__11_n_77\,
DI(1) => \ARG__11_n_78\,
DI(0) => \ARG__11_n_79\,
O(3) => \weight_reg[7][12]_i_1_n_4\,
O(2) => \weight_reg[7][12]_i_1_n_5\,
O(1) => \weight_reg[7][12]_i_1_n_6\,
O(0) => \weight_reg[7][12]_i_1_n_7\,
S(3) => \weight[7][12]_i_2_n_0\,
S(2) => \weight[7][12]_i_3_n_0\,
S(1) => \weight[7][12]_i_4_n_0\,
S(0) => \weight[7][12]_i_5_n_0\
);
\weight_reg[7][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_6\,
Q => \weight_reg[7]_6\(13)
);
\weight_reg[7][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_5\,
Q => \weight_reg[7]_6\(14)
);
\weight_reg[7][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][12]_i_1_n_4\,
Q => \weight_reg[7]_6\(15)
);
\weight_reg[7][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_6\,
Q => \weight_reg[7]_6\(1)
);
\weight_reg[7][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_5\,
Q => \weight_reg[7]_6\(2)
);
\weight_reg[7][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][0]_i_1_n_4\,
Q => \weight_reg[7]_6\(3)
);
\weight_reg[7][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_7\,
Q => \weight_reg[7]_6\(4)
);
\weight_reg[7][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][0]_i_1_n_0\,
CO(3) => \weight_reg[7][4]_i_1_n_0\,
CO(2) => \weight_reg[7][4]_i_1_n_1\,
CO(1) => \weight_reg[7][4]_i_1_n_2\,
CO(0) => \weight_reg[7][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_84\,
DI(2) => \ARG__11_n_85\,
DI(1) => \ARG__11_n_86\,
DI(0) => \ARG__11_n_87\,
O(3) => \weight_reg[7][4]_i_1_n_4\,
O(2) => \weight_reg[7][4]_i_1_n_5\,
O(1) => \weight_reg[7][4]_i_1_n_6\,
O(0) => \weight_reg[7][4]_i_1_n_7\,
S(3) => \weight[7][4]_i_2_n_0\,
S(2) => \weight[7][4]_i_3_n_0\,
S(1) => \weight[7][4]_i_4_n_0\,
S(0) => \weight[7][4]_i_5_n_0\
);
\weight_reg[7][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_6\,
Q => \weight_reg[7]_6\(5)
);
\weight_reg[7][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_5\,
Q => \weight_reg[7]_6\(6)
);
\weight_reg[7][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][4]_i_1_n_4\,
Q => \weight_reg[7]_6\(7)
);
\weight_reg[7][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_7\,
Q => \weight_reg[7]_6\(8)
);
\weight_reg[7][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[7][4]_i_1_n_0\,
CO(3) => \weight_reg[7][8]_i_1_n_0\,
CO(2) => \weight_reg[7][8]_i_1_n_1\,
CO(1) => \weight_reg[7][8]_i_1_n_2\,
CO(0) => \weight_reg[7][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__11_n_80\,
DI(2) => \ARG__11_n_81\,
DI(1) => \ARG__11_n_82\,
DI(0) => \ARG__11_n_83\,
O(3) => \weight_reg[7][8]_i_1_n_4\,
O(2) => \weight_reg[7][8]_i_1_n_5\,
O(1) => \weight_reg[7][8]_i_1_n_6\,
O(0) => \weight_reg[7][8]_i_1_n_7\,
S(3) => \weight[7][8]_i_2_n_0\,
S(2) => \weight[7][8]_i_3_n_0\,
S(1) => \weight[7][8]_i_4_n_0\,
S(0) => \weight[7][8]_i_5_n_0\
);
\weight_reg[7][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[7][8]_i_1_n_6\,
Q => \weight_reg[7]_6\(9)
);
\weight_reg[8][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_7\,
Q => \weight_reg[8]_7\(0)
);
\weight_reg[8][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[8][0]_i_1_n_0\,
CO(2) => \weight_reg[8][0]_i_1_n_1\,
CO(1) => \weight_reg[8][0]_i_1_n_2\,
CO(0) => \weight_reg[8][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_88\,
DI(2) => \ARG__13_n_89\,
DI(1) => \ARG__13_n_90\,
DI(0) => \ARG__13_n_91\,
O(3) => \weight_reg[8][0]_i_1_n_4\,
O(2) => \weight_reg[8][0]_i_1_n_5\,
O(1) => \weight_reg[8][0]_i_1_n_6\,
O(0) => \weight_reg[8][0]_i_1_n_7\,
S(3) => \weight[8][0]_i_2_n_0\,
S(2) => \weight[8][0]_i_3_n_0\,
S(1) => \weight[8][0]_i_4_n_0\,
S(0) => \weight[8][0]_i_5_n_0\
);
\weight_reg[8][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_5\,
Q => \weight_reg[8]_7\(10)
);
\weight_reg[8][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_4\,
Q => \weight_reg[8]_7\(11)
);
\weight_reg[8][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_7\,
Q => \weight_reg[8]_7\(12)
);
\weight_reg[8][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[8][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[8][12]_i_1_n_1\,
CO(1) => \weight_reg[8][12]_i_1_n_2\,
CO(0) => \weight_reg[8][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__13_n_77\,
DI(1) => \ARG__13_n_78\,
DI(0) => \ARG__13_n_79\,
O(3) => \weight_reg[8][12]_i_1_n_4\,
O(2) => \weight_reg[8][12]_i_1_n_5\,
O(1) => \weight_reg[8][12]_i_1_n_6\,
O(0) => \weight_reg[8][12]_i_1_n_7\,
S(3) => \weight[8][12]_i_2_n_0\,
S(2) => \weight[8][12]_i_3_n_0\,
S(1) => \weight[8][12]_i_4_n_0\,
S(0) => \weight[8][12]_i_5_n_0\
);
\weight_reg[8][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_6\,
Q => \weight_reg[8]_7\(13)
);
\weight_reg[8][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_5\,
Q => \weight_reg[8]_7\(14)
);
\weight_reg[8][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][12]_i_1_n_4\,
Q => \weight_reg[8]_7\(15)
);
\weight_reg[8][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_6\,
Q => \weight_reg[8]_7\(1)
);
\weight_reg[8][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_5\,
Q => \weight_reg[8]_7\(2)
);
\weight_reg[8][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][0]_i_1_n_4\,
Q => \weight_reg[8]_7\(3)
);
\weight_reg[8][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_7\,
Q => \weight_reg[8]_7\(4)
);
\weight_reg[8][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][0]_i_1_n_0\,
CO(3) => \weight_reg[8][4]_i_1_n_0\,
CO(2) => \weight_reg[8][4]_i_1_n_1\,
CO(1) => \weight_reg[8][4]_i_1_n_2\,
CO(0) => \weight_reg[8][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_84\,
DI(2) => \ARG__13_n_85\,
DI(1) => \ARG__13_n_86\,
DI(0) => \ARG__13_n_87\,
O(3) => \weight_reg[8][4]_i_1_n_4\,
O(2) => \weight_reg[8][4]_i_1_n_5\,
O(1) => \weight_reg[8][4]_i_1_n_6\,
O(0) => \weight_reg[8][4]_i_1_n_7\,
S(3) => \weight[8][4]_i_2_n_0\,
S(2) => \weight[8][4]_i_3_n_0\,
S(1) => \weight[8][4]_i_4_n_0\,
S(0) => \weight[8][4]_i_5_n_0\
);
\weight_reg[8][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_6\,
Q => \weight_reg[8]_7\(5)
);
\weight_reg[8][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_5\,
Q => \weight_reg[8]_7\(6)
);
\weight_reg[8][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][4]_i_1_n_4\,
Q => \weight_reg[8]_7\(7)
);
\weight_reg[8][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_7\,
Q => \weight_reg[8]_7\(8)
);
\weight_reg[8][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[8][4]_i_1_n_0\,
CO(3) => \weight_reg[8][8]_i_1_n_0\,
CO(2) => \weight_reg[8][8]_i_1_n_1\,
CO(1) => \weight_reg[8][8]_i_1_n_2\,
CO(0) => \weight_reg[8][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__13_n_80\,
DI(2) => \ARG__13_n_81\,
DI(1) => \ARG__13_n_82\,
DI(0) => \ARG__13_n_83\,
O(3) => \weight_reg[8][8]_i_1_n_4\,
O(2) => \weight_reg[8][8]_i_1_n_5\,
O(1) => \weight_reg[8][8]_i_1_n_6\,
O(0) => \weight_reg[8][8]_i_1_n_7\,
S(3) => \weight[8][8]_i_2_n_0\,
S(2) => \weight[8][8]_i_3_n_0\,
S(1) => \weight[8][8]_i_4_n_0\,
S(0) => \weight[8][8]_i_5_n_0\
);
\weight_reg[8][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[8][8]_i_1_n_6\,
Q => \weight_reg[8]_7\(9)
);
\weight_reg[9][0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_7\,
Q => \weight_reg[9]_8\(0)
);
\weight_reg[9][0]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \weight_reg[9][0]_i_1_n_0\,
CO(2) => \weight_reg[9][0]_i_1_n_1\,
CO(1) => \weight_reg[9][0]_i_1_n_2\,
CO(0) => \weight_reg[9][0]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_88\,
DI(2) => \ARG__15_n_89\,
DI(1) => \ARG__15_n_90\,
DI(0) => \ARG__15_n_91\,
O(3) => \weight_reg[9][0]_i_1_n_4\,
O(2) => \weight_reg[9][0]_i_1_n_5\,
O(1) => \weight_reg[9][0]_i_1_n_6\,
O(0) => \weight_reg[9][0]_i_1_n_7\,
S(3) => \weight[9][0]_i_2_n_0\,
S(2) => \weight[9][0]_i_3_n_0\,
S(1) => \weight[9][0]_i_4_n_0\,
S(0) => \weight[9][0]_i_5_n_0\
);
\weight_reg[9][10]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_5\,
Q => \weight_reg[9]_8\(10)
);
\weight_reg[9][11]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_4\,
Q => \weight_reg[9]_8\(11)
);
\weight_reg[9][12]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_7\,
Q => \weight_reg[9]_8\(12)
);
\weight_reg[9][12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][8]_i_1_n_0\,
CO(3) => \NLW_weight_reg[9][12]_i_1_CO_UNCONNECTED\(3),
CO(2) => \weight_reg[9][12]_i_1_n_1\,
CO(1) => \weight_reg[9][12]_i_1_n_2\,
CO(0) => \weight_reg[9][12]_i_1_n_3\,
CYINIT => '0',
DI(3) => '0',
DI(2) => \ARG__15_n_77\,
DI(1) => \ARG__15_n_78\,
DI(0) => \ARG__15_n_79\,
O(3) => \weight_reg[9][12]_i_1_n_4\,
O(2) => \weight_reg[9][12]_i_1_n_5\,
O(1) => \weight_reg[9][12]_i_1_n_6\,
O(0) => \weight_reg[9][12]_i_1_n_7\,
S(3) => \weight[9][12]_i_2_n_0\,
S(2) => \weight[9][12]_i_3_n_0\,
S(1) => \weight[9][12]_i_4_n_0\,
S(0) => \weight[9][12]_i_5_n_0\
);
\weight_reg[9][13]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_6\,
Q => \weight_reg[9]_8\(13)
);
\weight_reg[9][14]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_5\,
Q => \weight_reg[9]_8\(14)
);
\weight_reg[9][15]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][12]_i_1_n_4\,
Q => \weight_reg[9]_8\(15)
);
\weight_reg[9][1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_6\,
Q => \weight_reg[9]_8\(1)
);
\weight_reg[9][2]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_5\,
Q => \weight_reg[9]_8\(2)
);
\weight_reg[9][3]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][0]_i_1_n_4\,
Q => \weight_reg[9]_8\(3)
);
\weight_reg[9][4]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_7\,
Q => \weight_reg[9]_8\(4)
);
\weight_reg[9][4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][0]_i_1_n_0\,
CO(3) => \weight_reg[9][4]_i_1_n_0\,
CO(2) => \weight_reg[9][4]_i_1_n_1\,
CO(1) => \weight_reg[9][4]_i_1_n_2\,
CO(0) => \weight_reg[9][4]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_84\,
DI(2) => \ARG__15_n_85\,
DI(1) => \ARG__15_n_86\,
DI(0) => \ARG__15_n_87\,
O(3) => \weight_reg[9][4]_i_1_n_4\,
O(2) => \weight_reg[9][4]_i_1_n_5\,
O(1) => \weight_reg[9][4]_i_1_n_6\,
O(0) => \weight_reg[9][4]_i_1_n_7\,
S(3) => \weight[9][4]_i_2_n_0\,
S(2) => \weight[9][4]_i_3_n_0\,
S(1) => \weight[9][4]_i_4_n_0\,
S(0) => \weight[9][4]_i_5_n_0\
);
\weight_reg[9][5]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_6\,
Q => \weight_reg[9]_8\(5)
);
\weight_reg[9][6]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_5\,
Q => \weight_reg[9]_8\(6)
);
\weight_reg[9][7]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][4]_i_1_n_4\,
Q => \weight_reg[9]_8\(7)
);
\weight_reg[9][8]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_7\,
Q => \weight_reg[9]_8\(8)
);
\weight_reg[9][8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \weight_reg[9][4]_i_1_n_0\,
CO(3) => \weight_reg[9][8]_i_1_n_0\,
CO(2) => \weight_reg[9][8]_i_1_n_1\,
CO(1) => \weight_reg[9][8]_i_1_n_2\,
CO(0) => \weight_reg[9][8]_i_1_n_3\,
CYINIT => '0',
DI(3) => \ARG__15_n_80\,
DI(2) => \ARG__15_n_81\,
DI(1) => \ARG__15_n_82\,
DI(0) => \ARG__15_n_83\,
O(3) => \weight_reg[9][8]_i_1_n_4\,
O(2) => \weight_reg[9][8]_i_1_n_5\,
O(1) => \weight_reg[9][8]_i_1_n_6\,
O(0) => \weight_reg[9][8]_i_1_n_7\,
S(3) => \weight[9][8]_i_2_n_0\,
S(2) => \weight[9][8]_i_3_n_0\,
S(1) => \weight[9][8]_i_4_n_0\,
S(0) => \weight[9][8]_i_5_n_0\
);
\weight_reg[9][9]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => cop_dut_enable,
CLR => AR(0),
D => \weight_reg[9][8]_i_1_n_6\,
Q => \weight_reg[9]_8\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder is
port (
read_reg_cop_out_ready : out STD_LOGIC;
write_reg_axi_enable : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\sync_reg_e_k_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[7]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\ARG__29\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cp_controller_cpstate_reg[0]\ : out STD_LOGIC;
\ARG__28\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
\AXI4_Lite_RDATA_tmp_reg[31]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
strobe_sw_cop_in_strobe : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
cop_out_ready : in STD_LOGIC;
\wdata_reg[0]\ : in STD_LOGIC;
filter_sum : in STD_LOGIC_VECTOR ( 15 downto 0 );
mul_temp_16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
cp_controller_cpstate : in STD_LOGIC_VECTOR ( 1 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\wdata_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
wr_enb_1_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder is
signal \^q\ : STD_LOGIC_VECTOR ( 14 downto 0 );
signal in_strobe : STD_LOGIC;
signal \^write_reg_axi_enable\ : STD_LOGIC;
signal write_reg_d_k : STD_LOGIC_VECTOR ( 15 to 15 );
begin
Q(14 downto 0) <= \^q\(14 downto 0);
write_reg_axi_enable <= \^write_reg_axi_enable\;
\ARG_carry__0_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(3),
O => DI(0)
);
ARG_carry_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(1),
O => \ARG__29\(2)
);
ARG_carry_i_2: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(0),
O => \ARG__29\(1)
);
ARG_carry_i_3: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => mul_temp_16(3),
O => \ARG__29\(0)
);
\cp_controller_cpstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0F20"
)
port map (
I0 => in_strobe,
I1 => cp_controller_cpstate(1),
I2 => \^write_reg_axi_enable\,
I3 => cp_controller_cpstate(0),
O => \cp_controller_cpstate_reg[0]\
);
read_reg_cop_out_ready_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => AR(0),
D => cop_out_ready,
Q => read_reg_cop_out_ready
);
strobe_reg_cop_in_strobe_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => AR(0),
D => strobe_sw_cop_in_strobe,
Q => in_strobe
);
\sub_temp_carry__0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(7),
I1 => filter_sum(7),
O => \sync_reg_e_k_reg[7]_0\(3)
);
\sub_temp_carry__0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(6),
I1 => filter_sum(6),
O => \sync_reg_e_k_reg[7]_0\(2)
);
\sub_temp_carry__0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(5),
I1 => filter_sum(5),
O => \sync_reg_e_k_reg[7]_0\(1)
);
\sub_temp_carry__0_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(4),
I1 => filter_sum(4),
O => \sync_reg_e_k_reg[7]_0\(0)
);
\sub_temp_carry__1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(11),
I1 => filter_sum(11),
O => \sync_reg_e_k_reg[11]_0\(3)
);
\sub_temp_carry__1_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(10),
I1 => filter_sum(10),
O => \sync_reg_e_k_reg[11]_0\(2)
);
\sub_temp_carry__1_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(9),
I1 => filter_sum(9),
O => \sync_reg_e_k_reg[11]_0\(1)
);
\sub_temp_carry__1_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(8),
I1 => filter_sum(8),
O => \sync_reg_e_k_reg[11]_0\(0)
);
\sub_temp_carry__2_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => write_reg_d_k(15),
I1 => filter_sum(15),
O => S(3)
);
\sub_temp_carry__2_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(14),
I1 => filter_sum(14),
O => S(2)
);
\sub_temp_carry__2_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(13),
I1 => filter_sum(13),
O => S(1)
);
\sub_temp_carry__2_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(12),
I1 => filter_sum(12),
O => S(0)
);
sub_temp_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(3),
I1 => filter_sum(3),
O => \sync_reg_e_k_reg[3]_0\(3)
);
sub_temp_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(2),
I1 => filter_sum(2),
O => \sync_reg_e_k_reg[3]_0\(2)
);
sub_temp_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(1),
I1 => filter_sum(1),
O => \sync_reg_e_k_reg[3]_0\(1)
);
sub_temp_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^q\(0),
I1 => filter_sum(0),
O => \sync_reg_e_k_reg[3]_0\(0)
);
\sync_reg_e_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(0),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(0)
);
\sync_reg_e_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(10),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(10)
);
\sync_reg_e_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(11),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(11)
);
\sync_reg_e_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(12),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(12)
);
\sync_reg_e_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(13),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(13)
);
\sync_reg_e_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(14),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(14)
);
\sync_reg_e_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(15),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(15)
);
\sync_reg_e_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(1),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(1)
);
\sync_reg_e_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(2),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(2)
);
\sync_reg_e_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(3),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(3)
);
\sync_reg_e_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(4),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(4)
);
\sync_reg_e_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(5),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(5)
);
\sync_reg_e_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(6),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(6)
);
\sync_reg_e_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(7),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(7)
);
\sync_reg_e_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(8),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(8)
);
\sync_reg_e_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => in_strobe,
CLR => AR(0),
D => mul_temp_16(9),
Q => \AXI4_Lite_RDATA_tmp_reg[31]\(9)
);
write_reg_axi_enable_reg: unisim.vcomponents.FDPE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
D => \wdata_reg[0]\,
PRE => AR(0),
Q => \^write_reg_axi_enable\
);
\write_reg_d_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(0),
Q => \^q\(0)
);
\write_reg_d_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(10),
Q => \^q\(10)
);
\write_reg_d_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(11),
Q => \^q\(11)
);
\write_reg_d_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(12),
Q => \^q\(12)
);
\write_reg_d_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(13),
Q => \^q\(13)
);
\write_reg_d_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(14),
Q => \^q\(14)
);
\write_reg_d_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(15),
Q => write_reg_d_k(15)
);
\write_reg_d_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(1),
Q => \^q\(1)
);
\write_reg_d_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(2),
Q => \^q\(2)
);
\write_reg_d_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(3),
Q => \^q\(3)
);
\write_reg_d_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(4),
Q => \^q\(4)
);
\write_reg_d_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(5),
Q => \^q\(5)
);
\write_reg_d_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(6),
Q => \^q\(6)
);
\write_reg_d_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(7),
Q => \^q\(7)
);
\write_reg_d_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(8),
Q => \^q\(8)
);
\write_reg_d_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => wr_enb_1_reg(0),
CLR => AR(0),
D => \wdata_reg[15]\(9),
Q => \^q\(9)
);
\write_reg_x_k_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(0),
Q => \ARG__28\(0)
);
\write_reg_x_k_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(10),
Q => \ARG__28\(10)
);
\write_reg_x_k_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(11),
Q => \ARG__28\(11)
);
\write_reg_x_k_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(12),
Q => \ARG__28\(12)
);
\write_reg_x_k_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(13),
Q => \ARG__28\(13)
);
\write_reg_x_k_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(14),
Q => \ARG__28\(14)
);
\write_reg_x_k_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(15),
Q => \ARG__28\(15)
);
\write_reg_x_k_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(1),
Q => \ARG__28\(1)
);
\write_reg_x_k_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(2),
Q => \ARG__28\(2)
);
\write_reg_x_k_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(3),
Q => \ARG__28\(3)
);
\write_reg_x_k_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(4),
Q => \ARG__28\(4)
);
\write_reg_x_k_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(5),
Q => \ARG__28\(5)
);
\write_reg_x_k_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(6),
Q => \ARG__28\(6)
);
\write_reg_x_k_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(7),
Q => \ARG__28\(7)
);
\write_reg_x_k_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(8),
Q => \ARG__28\(8)
);
\write_reg_x_k_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => E(0),
CLR => AR(0),
D => \wdata_reg[15]\(9),
Q => \ARG__28\(9)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module is
port (
AXI4_Lite_RVALID : out STD_LOGIC;
write_reg_axi_enable_reg : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
write_reg_axi_enable_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWREADY : out STD_LOGIC;
strobe_sw_cop_in_strobe : out STD_LOGIC;
\write_reg_d_k_reg[15]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
write_reg_axi_enable : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_BREADY : in STD_LOGIC;
\sync_reg_e_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
read_reg_cop_out_ready : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module is
signal \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\ : STD_LOGIC;
signal \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\ : STD_LOGIC;
signal \^axi4_lite_rvalid\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal aw_transfer : STD_LOGIC;
signal \axi_lite_rstate[0]_i_1_n_0\ : STD_LOGIC;
signal axi_lite_wstate : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axi_lite_wstate[0]_i_1_n_0\ : STD_LOGIC;
signal \axi_lite_wstate_next_inferred__1/i__n_0\ : STD_LOGIC;
signal data_read : STD_LOGIC_VECTOR ( 31 downto 0 );
signal reset : STD_LOGIC;
signal sel0 : STD_LOGIC_VECTOR ( 13 downto 0 );
signal soft_reset : STD_LOGIC;
signal soft_reset_i_2_n_0 : STD_LOGIC;
signal soft_reset_i_3_n_0 : STD_LOGIC;
signal soft_reset_i_4_n_0 : STD_LOGIC;
signal strobe_reg_cop_in_strobe_i_3_n_0 : STD_LOGIC;
signal strobe_sw : STD_LOGIC;
signal top_rd_enb : STD_LOGIC;
signal top_wr_enb : STD_LOGIC;
signal w_transfer : STD_LOGIC;
signal write_reg_axi_enable_i_2_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of AXI4_Lite_BVALID_INST_0 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_5\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \AXI4_Lite_RDATA_tmp[31]_i_7\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of AXI4_Lite_WREADY_INST_0 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axi_lite_rstate[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axi_lite_wstate[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \axi_lite_wstate_next_inferred__1/i_\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of strobe_reg_cop_in_strobe_i_3 : label is "soft_lutpair1";
begin
AXI4_Lite_RVALID <= \^axi4_lite_rvalid\;
Q(15 downto 0) <= \^q\(15 downto 0);
AXI4_Lite_ARREADY_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^axi4_lite_rvalid\,
O => AXI4_Lite_ARREADY
);
AXI4_Lite_AWREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => axi_lite_wstate(0),
I1 => axi_lite_wstate(1),
O => AXI4_Lite_AWREADY
);
AXI4_Lite_BVALID_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_lite_wstate(1),
I1 => axi_lite_wstate(0),
O => AXI4_Lite_BVALID
);
\AXI4_Lite_RDATA_tmp[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00008CCC00008000"
)
port map (
I0 => \sync_reg_e_k_reg[15]\(0),
I1 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I5 => \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\,
O => data_read(0)
);
\AXI4_Lite_RDATA_tmp[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => sel0(6),
I1 => AXI4_Lite_ARADDR(6),
I2 => sel0(0),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(0),
O => \AXI4_Lite_RDATA_tmp[0]_i_2_n_0\
);
\AXI4_Lite_RDATA_tmp[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000B80000000000"
)
port map (
I0 => AXI4_Lite_ARADDR(0),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(0),
I3 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I5 => read_reg_cop_out_ready,
O => \AXI4_Lite_RDATA_tmp[0]_i_3_n_0\
);
\AXI4_Lite_RDATA_tmp[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(10),
O => data_read(10)
);
\AXI4_Lite_RDATA_tmp[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(11),
O => data_read(11)
);
\AXI4_Lite_RDATA_tmp[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(12),
O => data_read(12)
);
\AXI4_Lite_RDATA_tmp[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(13),
O => data_read(13)
);
\AXI4_Lite_RDATA_tmp[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(14),
O => data_read(14)
);
\AXI4_Lite_RDATA_tmp[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(1),
O => data_read(1)
);
\AXI4_Lite_RDATA_tmp[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(2),
O => data_read(2)
);
\AXI4_Lite_RDATA_tmp[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => AXI4_Lite_ARVALID,
I1 => \^axi4_lite_rvalid\,
O => top_rd_enb
);
\AXI4_Lite_RDATA_tmp[31]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(5),
I1 => sel0(4),
I2 => AXI4_Lite_ARADDR(5),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(4),
O => \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_11\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(3),
I1 => sel0(2),
I2 => AXI4_Lite_ARADDR(3),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(2),
O => \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_12\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEEF0EE"
)
port map (
I0 => sel0(9),
I1 => sel0(8),
I2 => AXI4_Lite_ARADDR(9),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(8),
O => \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(15),
O => data_read(31)
);
\AXI4_Lite_RDATA_tmp[31]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => AXI4_Lite_ARESETN,
O => reset
);
\AXI4_Lite_RDATA_tmp[31]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFEFEFFFFAEFEA"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\,
I1 => AXI4_Lite_ARADDR(10),
I2 => AXI4_Lite_ARVALID,
I3 => sel0(10),
I4 => AXI4_Lite_ARADDR(11),
I5 => sel0(11),
O => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(1),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(1),
O => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(6),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(6),
O => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => AXI4_Lite_ARADDR(0),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(0),
O => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"00011101"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_10_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_11_n_0\,
I2 => sel0(7),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(7),
O => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\
);
\AXI4_Lite_RDATA_tmp[31]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFBBFCB8"
)
port map (
I0 => AXI4_Lite_ARADDR(13),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(13),
I3 => AXI4_Lite_ARADDR(12),
I4 => sel0(12),
I5 => \AXI4_Lite_RDATA_tmp[31]_i_12_n_0\,
O => \AXI4_Lite_RDATA_tmp[31]_i_9_n_0\
);
\AXI4_Lite_RDATA_tmp[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(3),
O => data_read(3)
);
\AXI4_Lite_RDATA_tmp[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(4),
O => data_read(4)
);
\AXI4_Lite_RDATA_tmp[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(5),
O => data_read(5)
);
\AXI4_Lite_RDATA_tmp[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(6),
O => data_read(6)
);
\AXI4_Lite_RDATA_tmp[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(7),
O => data_read(7)
);
\AXI4_Lite_RDATA_tmp[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(8),
O => data_read(8)
);
\AXI4_Lite_RDATA_tmp[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040000000000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I5 => \sync_reg_e_k_reg[15]\(9),
O => data_read(9)
);
\AXI4_Lite_RDATA_tmp_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(0),
Q => AXI4_Lite_RDATA(0)
);
\AXI4_Lite_RDATA_tmp_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(10),
Q => AXI4_Lite_RDATA(10)
);
\AXI4_Lite_RDATA_tmp_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(11),
Q => AXI4_Lite_RDATA(11)
);
\AXI4_Lite_RDATA_tmp_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(12),
Q => AXI4_Lite_RDATA(12)
);
\AXI4_Lite_RDATA_tmp_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(13),
Q => AXI4_Lite_RDATA(13)
);
\AXI4_Lite_RDATA_tmp_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(14),
Q => AXI4_Lite_RDATA(14)
);
\AXI4_Lite_RDATA_tmp_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(1),
Q => AXI4_Lite_RDATA(1)
);
\AXI4_Lite_RDATA_tmp_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(2),
Q => AXI4_Lite_RDATA(2)
);
\AXI4_Lite_RDATA_tmp_reg[31]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(31),
Q => AXI4_Lite_RDATA(15)
);
\AXI4_Lite_RDATA_tmp_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(3),
Q => AXI4_Lite_RDATA(3)
);
\AXI4_Lite_RDATA_tmp_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(4),
Q => AXI4_Lite_RDATA(4)
);
\AXI4_Lite_RDATA_tmp_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(5),
Q => AXI4_Lite_RDATA(5)
);
\AXI4_Lite_RDATA_tmp_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(6),
Q => AXI4_Lite_RDATA(6)
);
\AXI4_Lite_RDATA_tmp_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(7),
Q => AXI4_Lite_RDATA(7)
);
\AXI4_Lite_RDATA_tmp_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(8),
Q => AXI4_Lite_RDATA(8)
);
\AXI4_Lite_RDATA_tmp_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => top_rd_enb,
CLR => reset,
D => data_read(9),
Q => AXI4_Lite_RDATA(9)
);
AXI4_Lite_WREADY_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => axi_lite_wstate(0),
I1 => axi_lite_wstate(1),
O => AXI4_Lite_WREADY
);
\axi_lite_rstate[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => AXI4_Lite_RREADY,
I1 => \^axi4_lite_rvalid\,
I2 => AXI4_Lite_ARVALID,
O => \axi_lite_rstate[0]_i_1_n_0\
);
\axi_lite_rstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_rstate[0]_i_1_n_0\,
Q => \^axi4_lite_rvalid\
);
\axi_lite_wstate[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"002E"
)
port map (
I0 => AXI4_Lite_AWVALID,
I1 => axi_lite_wstate(0),
I2 => AXI4_Lite_WVALID,
I3 => axi_lite_wstate(1),
O => \axi_lite_wstate[0]_i_1_n_0\
);
\axi_lite_wstate_next_inferred__1/i_\: unisim.vcomponents.LUT4
generic map(
INIT => X"0838"
)
port map (
I0 => AXI4_Lite_WVALID,
I1 => axi_lite_wstate(0),
I2 => axi_lite_wstate(1),
I3 => AXI4_Lite_BREADY,
O => \axi_lite_wstate_next_inferred__1/i__n_0\
);
\axi_lite_wstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_wstate[0]_i_1_n_0\,
Q => axi_lite_wstate(0)
);
\axi_lite_wstate_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => \axi_lite_wstate_next_inferred__1/i__n_0\,
Q => axi_lite_wstate(1)
);
soft_reset_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => soft_reset_i_2_n_0,
I1 => sel0(1),
I2 => sel0(0),
I3 => sel0(7),
I4 => sel0(6),
I5 => soft_reset_i_3_n_0,
O => strobe_sw
);
soft_reset_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => sel0(13),
I1 => sel0(12),
I2 => sel0(11),
I3 => sel0(10),
O => soft_reset_i_2_n_0
);
soft_reset_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => sel0(2),
I1 => sel0(3),
I2 => sel0(8),
I3 => sel0(9),
I4 => soft_reset_i_4_n_0,
O => soft_reset_i_3_n_0
);
soft_reset_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"0008"
)
port map (
I0 => top_wr_enb,
I1 => \^q\(0),
I2 => sel0(5),
I3 => sel0(4),
O => soft_reset_i_4_n_0
);
soft_reset_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => strobe_sw,
Q => soft_reset
);
strobe_reg_cop_in_strobe_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000020000000"
)
port map (
I0 => \^q\(0),
I1 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I2 => strobe_reg_cop_in_strobe_i_3_n_0,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => strobe_sw_cop_in_strobe
);
strobe_reg_cop_in_strobe_i_2: unisim.vcomponents.LUT3
generic map(
INIT => X"DF"
)
port map (
I0 => AXI4_Lite_ARESETN,
I1 => soft_reset,
I2 => IPCORE_RESETN,
O => write_reg_axi_enable_reg
);
strobe_reg_cop_in_strobe_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"000ACC0A"
)
port map (
I0 => sel0(1),
I1 => AXI4_Lite_ARADDR(1),
I2 => sel0(0),
I3 => AXI4_Lite_ARVALID,
I4 => AXI4_Lite_ARADDR(0),
O => strobe_reg_cop_in_strobe_i_3_n_0
);
\waddr[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => AXI4_Lite_AWVALID,
I1 => axi_lite_wstate(1),
I2 => axi_lite_wstate(0),
O => aw_transfer
);
\waddr_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(8),
Q => sel0(8)
);
\waddr_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(9),
Q => sel0(9)
);
\waddr_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(10),
Q => sel0(10)
);
\waddr_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(11),
Q => sel0(11)
);
\waddr_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(12),
Q => sel0(12)
);
\waddr_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(13),
Q => sel0(13)
);
\waddr_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(0),
Q => sel0(0)
);
\waddr_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(1),
Q => sel0(1)
);
\waddr_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(2),
Q => sel0(2)
);
\waddr_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(3),
Q => sel0(3)
);
\waddr_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(4),
Q => sel0(4)
);
\waddr_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(5),
Q => sel0(5)
);
\waddr_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(6),
Q => sel0(6)
);
\waddr_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => aw_transfer,
CLR => reset,
D => AXI4_Lite_AWADDR(7),
Q => sel0(7)
);
\wdata[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"20"
)
port map (
I0 => AXI4_Lite_WVALID,
I1 => axi_lite_wstate(1),
I2 => axi_lite_wstate(0),
O => w_transfer
);
\wdata_reg[0]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(0),
Q => \^q\(0)
);
\wdata_reg[10]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(10),
Q => \^q\(10)
);
\wdata_reg[11]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(11),
Q => \^q\(11)
);
\wdata_reg[12]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(12),
Q => \^q\(12)
);
\wdata_reg[13]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(13),
Q => \^q\(13)
);
\wdata_reg[14]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(14),
Q => \^q\(14)
);
\wdata_reg[15]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(15),
Q => \^q\(15)
);
\wdata_reg[1]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(1),
Q => \^q\(1)
);
\wdata_reg[2]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(2),
Q => \^q\(2)
);
\wdata_reg[3]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(3),
Q => \^q\(3)
);
\wdata_reg[4]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(4),
Q => \^q\(4)
);
\wdata_reg[5]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(5),
Q => \^q\(5)
);
\wdata_reg[6]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(6),
Q => \^q\(6)
);
\wdata_reg[7]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(7),
Q => \^q\(7)
);
\wdata_reg[8]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(8),
Q => \^q\(8)
);
\wdata_reg[9]\: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => w_transfer,
CLR => reset,
D => AXI4_Lite_WDATA(9),
Q => \^q\(9)
);
wr_enb_1_reg: unisim.vcomponents.FDCE
port map (
C => AXI4_Lite_ACLK,
CE => '1',
CLR => reset,
D => w_transfer,
Q => top_wr_enb
);
write_reg_axi_enable_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFBFFF00008000"
)
port map (
I0 => \^q\(0),
I1 => write_reg_axi_enable_i_2_n_0,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I3 => top_wr_enb,
I4 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
I5 => write_reg_axi_enable,
O => write_reg_axi_enable_reg_0
);
write_reg_axi_enable_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000047034400"
)
port map (
I0 => AXI4_Lite_ARADDR(6),
I1 => AXI4_Lite_ARVALID,
I2 => sel0(6),
I3 => AXI4_Lite_ARADDR(0),
I4 => sel0(0),
I5 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
O => write_reg_axi_enable_i_2_n_0
);
\write_reg_d_k[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000040000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => \write_reg_d_k_reg[15]\(0)
);
\write_reg_x_k[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000004000000"
)
port map (
I0 => \AXI4_Lite_RDATA_tmp[31]_i_5_n_0\,
I1 => \AXI4_Lite_RDATA_tmp[31]_i_6_n_0\,
I2 => \AXI4_Lite_RDATA_tmp[31]_i_7_n_0\,
I3 => \AXI4_Lite_RDATA_tmp[31]_i_8_n_0\,
I4 => top_wr_enb,
I5 => \AXI4_Lite_RDATA_tmp[31]_i_4_n_0\,
O => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop is
port (
cp_controller_cpstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
cop_out_ready : out STD_LOGIC;
cop_dut_enable : out STD_LOGIC;
strobe_reg_cop_in_strobe_reg : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
write_reg_axi_enable : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop is
signal \^cp_controller_cpstate\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cp_controller_cpstate[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cp_controller_cpstate[1]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of read_reg_cop_out_ready_i_1 : label is "soft_lutpair5";
begin
cp_controller_cpstate(1 downto 0) <= \^cp_controller_cpstate\(1 downto 0);
\cp_controller_cpstate[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"38"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => write_reg_axi_enable,
I2 => \^cp_controller_cpstate\(1),
O => \cp_controller_cpstate[1]_i_1_n_0\
);
\cp_controller_cpstate_reg[0]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => '1',
CLR => AR(0),
D => strobe_reg_cop_in_strobe_reg,
Q => \^cp_controller_cpstate\(0)
);
\cp_controller_cpstate_reg[1]\: unisim.vcomponents.FDCE
port map (
C => IPCORE_CLK,
CE => '1',
CLR => AR(0),
D => \cp_controller_cpstate[1]_i_1_n_0\,
Q => \^cp_controller_cpstate\(1)
);
\data_pipeline_tmp[14][15]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => \^cp_controller_cpstate\(1),
O => cop_dut_enable
);
read_reg_cop_out_ready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \^cp_controller_cpstate\(0),
I1 => \^cp_controller_cpstate\(1),
O => cop_out_ready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite is
port (
write_reg_axi_enable_reg : out STD_LOGIC;
AXI4_Lite_RVALID : out STD_LOGIC;
write_reg_axi_enable : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 14 downto 0 );
\sync_reg_e_k_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\sync_reg_e_k_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
DI : out STD_LOGIC_VECTOR ( 0 to 0 );
\ARG__29\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\cp_controller_cpstate_reg[0]\ : out STD_LOGIC;
\ARG__28\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
cop_out_ready : in STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
filter_sum : in STD_LOGIC_VECTOR ( 15 downto 0 );
mul_temp_16 : in STD_LOGIC_VECTOR ( 15 downto 0 );
cp_controller_cpstate : in STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_RREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite is
signal read_reg_cop_out_ready : STD_LOGIC;
signal reg_enb_d_k : STD_LOGIC;
signal reg_enb_x_k : STD_LOGIC;
signal strobe_sw_cop_in_strobe : STD_LOGIC;
signal sync_reg_e_k : STD_LOGIC_VECTOR ( 15 downto 0 );
signal top_data_write : STD_LOGIC_VECTOR ( 0 to 0 );
signal u_lms_pcore_axi_lite_module_inst_n_10 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_11 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_12 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_13 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_14 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_15 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_16 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_17 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_18 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_19 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_4 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_5 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_6 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_7 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_8 : STD_LOGIC;
signal u_lms_pcore_axi_lite_module_inst_n_9 : STD_LOGIC;
signal \^write_reg_axi_enable\ : STD_LOGIC;
signal \^write_reg_axi_enable_reg\ : STD_LOGIC;
begin
write_reg_axi_enable <= \^write_reg_axi_enable\;
write_reg_axi_enable_reg <= \^write_reg_axi_enable_reg\;
u_lms_pcore_addr_decoder_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_addr_decoder
port map (
AR(0) => \^write_reg_axi_enable_reg\,
\ARG__28\(15 downto 0) => \ARG__28\(15 downto 0),
\ARG__29\(2 downto 0) => \ARG__29\(2 downto 0),
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
\AXI4_Lite_RDATA_tmp_reg[31]\(15 downto 0) => sync_reg_e_k(15 downto 0),
DI(0) => DI(0),
E(0) => reg_enb_x_k,
Q(14 downto 0) => Q(14 downto 0),
S(3 downto 0) => S(3 downto 0),
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
\cp_controller_cpstate_reg[0]\ => \cp_controller_cpstate_reg[0]\,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => mul_temp_16(15 downto 0),
read_reg_cop_out_ready => read_reg_cop_out_ready,
strobe_sw_cop_in_strobe => strobe_sw_cop_in_strobe,
\sync_reg_e_k_reg[11]_0\(3 downto 0) => \sync_reg_e_k_reg[11]\(3 downto 0),
\sync_reg_e_k_reg[3]_0\(3 downto 0) => \sync_reg_e_k_reg[3]\(3 downto 0),
\sync_reg_e_k_reg[7]_0\(3 downto 0) => \sync_reg_e_k_reg[7]\(3 downto 0),
\wdata_reg[0]\ => u_lms_pcore_axi_lite_module_inst_n_4,
\wdata_reg[15]\(15) => u_lms_pcore_axi_lite_module_inst_n_5,
\wdata_reg[15]\(14) => u_lms_pcore_axi_lite_module_inst_n_6,
\wdata_reg[15]\(13) => u_lms_pcore_axi_lite_module_inst_n_7,
\wdata_reg[15]\(12) => u_lms_pcore_axi_lite_module_inst_n_8,
\wdata_reg[15]\(11) => u_lms_pcore_axi_lite_module_inst_n_9,
\wdata_reg[15]\(10) => u_lms_pcore_axi_lite_module_inst_n_10,
\wdata_reg[15]\(9) => u_lms_pcore_axi_lite_module_inst_n_11,
\wdata_reg[15]\(8) => u_lms_pcore_axi_lite_module_inst_n_12,
\wdata_reg[15]\(7) => u_lms_pcore_axi_lite_module_inst_n_13,
\wdata_reg[15]\(6) => u_lms_pcore_axi_lite_module_inst_n_14,
\wdata_reg[15]\(5) => u_lms_pcore_axi_lite_module_inst_n_15,
\wdata_reg[15]\(4) => u_lms_pcore_axi_lite_module_inst_n_16,
\wdata_reg[15]\(3) => u_lms_pcore_axi_lite_module_inst_n_17,
\wdata_reg[15]\(2) => u_lms_pcore_axi_lite_module_inst_n_18,
\wdata_reg[15]\(1) => u_lms_pcore_axi_lite_module_inst_n_19,
\wdata_reg[15]\(0) => top_data_write(0),
wr_enb_1_reg(0) => reg_enb_d_k,
write_reg_axi_enable => \^write_reg_axi_enable\
);
u_lms_pcore_axi_lite_module_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite_module
port map (
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(13 downto 0),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(13 downto 0),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15 downto 0) => AXI4_Lite_RDATA(15 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
E(0) => reg_enb_x_k,
IPCORE_RESETN => IPCORE_RESETN,
Q(15) => u_lms_pcore_axi_lite_module_inst_n_5,
Q(14) => u_lms_pcore_axi_lite_module_inst_n_6,
Q(13) => u_lms_pcore_axi_lite_module_inst_n_7,
Q(12) => u_lms_pcore_axi_lite_module_inst_n_8,
Q(11) => u_lms_pcore_axi_lite_module_inst_n_9,
Q(10) => u_lms_pcore_axi_lite_module_inst_n_10,
Q(9) => u_lms_pcore_axi_lite_module_inst_n_11,
Q(8) => u_lms_pcore_axi_lite_module_inst_n_12,
Q(7) => u_lms_pcore_axi_lite_module_inst_n_13,
Q(6) => u_lms_pcore_axi_lite_module_inst_n_14,
Q(5) => u_lms_pcore_axi_lite_module_inst_n_15,
Q(4) => u_lms_pcore_axi_lite_module_inst_n_16,
Q(3) => u_lms_pcore_axi_lite_module_inst_n_17,
Q(2) => u_lms_pcore_axi_lite_module_inst_n_18,
Q(1) => u_lms_pcore_axi_lite_module_inst_n_19,
Q(0) => top_data_write(0),
read_reg_cop_out_ready => read_reg_cop_out_ready,
strobe_sw_cop_in_strobe => strobe_sw_cop_in_strobe,
\sync_reg_e_k_reg[15]\(15 downto 0) => sync_reg_e_k(15 downto 0),
write_reg_axi_enable => \^write_reg_axi_enable\,
write_reg_axi_enable_reg => \^write_reg_axi_enable_reg\,
write_reg_axi_enable_reg_0 => u_lms_pcore_axi_lite_module_inst_n_4,
\write_reg_d_k_reg[15]\(0) => reg_enb_d_k
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut is
port (
mul_temp_16 : out STD_LOGIC_VECTOR ( 15 downto 0 );
filter_sum : out STD_LOGIC_VECTOR ( 15 downto 0 );
\write_reg_x_k_reg[15]\ : in STD_LOGIC_VECTOR ( 15 downto 0 );
cop_dut_enable : in STD_LOGIC;
IPCORE_CLK : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
\write_reg_d_k_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
DI : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 14 downto 0 );
\write_reg_d_k_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[7]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\write_reg_d_k_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
S : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut is
begin
u_LMS: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_LMS
port map (
AR(0) => AR(0),
DI(0) => DI(0),
IPCORE_CLK => IPCORE_CLK,
Q(14 downto 0) => Q(14 downto 0),
S(3 downto 0) => S(3 downto 0),
cop_dut_enable => cop_dut_enable,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => mul_temp_16(15 downto 0),
\write_reg_d_k_reg[11]\(3 downto 0) => \write_reg_d_k_reg[11]\(3 downto 0),
\write_reg_d_k_reg[3]\(2 downto 0) => \write_reg_d_k_reg[3]\(2 downto 0),
\write_reg_d_k_reg[3]_0\(3 downto 0) => \write_reg_d_k_reg[3]_0\(3 downto 0),
\write_reg_d_k_reg[7]\(3 downto 0) => \write_reg_d_k_reg[7]\(3 downto 0),
\write_reg_x_k_reg[15]\(15 downto 0) => \write_reg_x_k_reg[15]\(15 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore is
port (
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_RVALID : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
IPCORE_CLK : in STD_LOGIC;
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 13 downto 0 );
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore is
signal cop_dut_enable : STD_LOGIC;
signal cop_out_ready : STD_LOGIC;
signal cp_controller_cpstate : STD_LOGIC_VECTOR ( 1 downto 0 );
signal filter_sum : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \u_LMS/mul_temp_16\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal u_lms_pcore_axi_lite_inst_n_0 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_24 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_25 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_26 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_27 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_28 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_29 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_30 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_31 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_32 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_33 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_34 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_35 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_36 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_37 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_38 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_39 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_40 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_5 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_6 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_7 : STD_LOGIC;
signal u_lms_pcore_axi_lite_inst_n_8 : STD_LOGIC;
signal write_reg_axi_enable : STD_LOGIC;
signal write_reg_d_k : STD_LOGIC_VECTOR ( 14 downto 0 );
signal write_reg_x_k : STD_LOGIC_VECTOR ( 15 downto 0 );
begin
u_lms_pcore_axi_lite_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_axi_lite
port map (
\ARG__28\(15 downto 0) => write_reg_x_k(15 downto 0),
\ARG__29\(2) => u_lms_pcore_axi_lite_inst_n_37,
\ARG__29\(1) => u_lms_pcore_axi_lite_inst_n_38,
\ARG__29\(0) => u_lms_pcore_axi_lite_inst_n_39,
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(13 downto 0),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(13 downto 0),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15 downto 0) => AXI4_Lite_RDATA(15 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
DI(0) => u_lms_pcore_axi_lite_inst_n_36,
IPCORE_RESETN => IPCORE_RESETN,
Q(14 downto 0) => write_reg_d_k(14 downto 0),
S(3) => u_lms_pcore_axi_lite_inst_n_5,
S(2) => u_lms_pcore_axi_lite_inst_n_6,
S(1) => u_lms_pcore_axi_lite_inst_n_7,
S(0) => u_lms_pcore_axi_lite_inst_n_8,
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
\cp_controller_cpstate_reg[0]\ => u_lms_pcore_axi_lite_inst_n_40,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => \u_LMS/mul_temp_16\(15 downto 0),
\sync_reg_e_k_reg[11]\(3) => u_lms_pcore_axi_lite_inst_n_24,
\sync_reg_e_k_reg[11]\(2) => u_lms_pcore_axi_lite_inst_n_25,
\sync_reg_e_k_reg[11]\(1) => u_lms_pcore_axi_lite_inst_n_26,
\sync_reg_e_k_reg[11]\(0) => u_lms_pcore_axi_lite_inst_n_27,
\sync_reg_e_k_reg[3]\(3) => u_lms_pcore_axi_lite_inst_n_32,
\sync_reg_e_k_reg[3]\(2) => u_lms_pcore_axi_lite_inst_n_33,
\sync_reg_e_k_reg[3]\(1) => u_lms_pcore_axi_lite_inst_n_34,
\sync_reg_e_k_reg[3]\(0) => u_lms_pcore_axi_lite_inst_n_35,
\sync_reg_e_k_reg[7]\(3) => u_lms_pcore_axi_lite_inst_n_28,
\sync_reg_e_k_reg[7]\(2) => u_lms_pcore_axi_lite_inst_n_29,
\sync_reg_e_k_reg[7]\(1) => u_lms_pcore_axi_lite_inst_n_30,
\sync_reg_e_k_reg[7]\(0) => u_lms_pcore_axi_lite_inst_n_31,
write_reg_axi_enable => write_reg_axi_enable,
write_reg_axi_enable_reg => u_lms_pcore_axi_lite_inst_n_0
);
u_lms_pcore_cop_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_cop
port map (
AR(0) => u_lms_pcore_axi_lite_inst_n_0,
IPCORE_CLK => IPCORE_CLK,
cop_dut_enable => cop_dut_enable,
cop_out_ready => cop_out_ready,
cp_controller_cpstate(1 downto 0) => cp_controller_cpstate(1 downto 0),
strobe_reg_cop_in_strobe_reg => u_lms_pcore_axi_lite_inst_n_40,
write_reg_axi_enable => write_reg_axi_enable
);
u_lms_pcore_dut_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore_dut
port map (
AR(0) => u_lms_pcore_axi_lite_inst_n_0,
DI(0) => u_lms_pcore_axi_lite_inst_n_36,
IPCORE_CLK => IPCORE_CLK,
Q(14 downto 0) => write_reg_d_k(14 downto 0),
S(3) => u_lms_pcore_axi_lite_inst_n_5,
S(2) => u_lms_pcore_axi_lite_inst_n_6,
S(1) => u_lms_pcore_axi_lite_inst_n_7,
S(0) => u_lms_pcore_axi_lite_inst_n_8,
cop_dut_enable => cop_dut_enable,
filter_sum(15 downto 0) => filter_sum(15 downto 0),
mul_temp_16(15 downto 0) => \u_LMS/mul_temp_16\(15 downto 0),
\write_reg_d_k_reg[11]\(3) => u_lms_pcore_axi_lite_inst_n_24,
\write_reg_d_k_reg[11]\(2) => u_lms_pcore_axi_lite_inst_n_25,
\write_reg_d_k_reg[11]\(1) => u_lms_pcore_axi_lite_inst_n_26,
\write_reg_d_k_reg[11]\(0) => u_lms_pcore_axi_lite_inst_n_27,
\write_reg_d_k_reg[3]\(2) => u_lms_pcore_axi_lite_inst_n_37,
\write_reg_d_k_reg[3]\(1) => u_lms_pcore_axi_lite_inst_n_38,
\write_reg_d_k_reg[3]\(0) => u_lms_pcore_axi_lite_inst_n_39,
\write_reg_d_k_reg[3]_0\(3) => u_lms_pcore_axi_lite_inst_n_32,
\write_reg_d_k_reg[3]_0\(2) => u_lms_pcore_axi_lite_inst_n_33,
\write_reg_d_k_reg[3]_0\(1) => u_lms_pcore_axi_lite_inst_n_34,
\write_reg_d_k_reg[3]_0\(0) => u_lms_pcore_axi_lite_inst_n_35,
\write_reg_d_k_reg[7]\(3) => u_lms_pcore_axi_lite_inst_n_28,
\write_reg_d_k_reg[7]\(2) => u_lms_pcore_axi_lite_inst_n_29,
\write_reg_d_k_reg[7]\(1) => u_lms_pcore_axi_lite_inst_n_30,
\write_reg_d_k_reg[7]\(0) => u_lms_pcore_axi_lite_inst_n_31,
\write_reg_x_k_reg[15]\(15 downto 0) => write_reg_x_k(15 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
IPCORE_CLK : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_RVALID : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_lms_pcore_0_0,lms_pcore,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "lms_pcore,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
signal \^axi4_lite_rdata\ : STD_LOGIC_VECTOR ( 30 downto 0 );
attribute x_interface_info : string;
attribute x_interface_info of AXI4_Lite_ACLK : signal is "xilinx.com:signal:clock:1.0 AXI4_Lite_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of AXI4_Lite_ACLK : signal is "XIL_INTERFACENAME AXI4_Lite_ACLK, ASSOCIATED_RESET AXI4_Lite_ARESETN, ASSOCIATED_BUSIF AXI4_Lite, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of AXI4_Lite_ARESETN : signal is "xilinx.com:signal:reset:1.0 AXI4_Lite_ARESETN RST";
attribute x_interface_parameter of AXI4_Lite_ARESETN : signal is "XIL_INTERFACENAME AXI4_Lite_ARESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of AXI4_Lite_ARREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARREADY";
attribute x_interface_info of AXI4_Lite_ARVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARVALID";
attribute x_interface_info of AXI4_Lite_AWREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWREADY";
attribute x_interface_info of AXI4_Lite_AWVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWVALID";
attribute x_interface_info of AXI4_Lite_BREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BREADY";
attribute x_interface_info of AXI4_Lite_BVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BVALID";
attribute x_interface_info of AXI4_Lite_RREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RREADY";
attribute x_interface_info of AXI4_Lite_RVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RVALID";
attribute x_interface_info of AXI4_Lite_WREADY : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WREADY";
attribute x_interface_info of AXI4_Lite_WVALID : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WVALID";
attribute x_interface_info of IPCORE_CLK : signal is "xilinx.com:signal:clock:1.0 IPCORE_CLK CLK";
attribute x_interface_parameter of IPCORE_CLK : signal is "XIL_INTERFACENAME IPCORE_CLK, ASSOCIATED_RESET IPCORE_RESETN, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of IPCORE_RESETN : signal is "xilinx.com:signal:reset:1.0 IPCORE_RESETN RST";
attribute x_interface_parameter of IPCORE_RESETN : signal is "XIL_INTERFACENAME IPCORE_RESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of AXI4_Lite_ARADDR : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite ARADDR";
attribute x_interface_info of AXI4_Lite_AWADDR : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite AWADDR";
attribute x_interface_parameter of AXI4_Lite_AWADDR : signal is "XIL_INTERFACENAME AXI4_Lite, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 16, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 1, NUM_WRITE_OUTSTANDING 1, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of AXI4_Lite_BRESP : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite BRESP";
attribute x_interface_info of AXI4_Lite_RDATA : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RDATA";
attribute x_interface_info of AXI4_Lite_RRESP : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite RRESP";
attribute x_interface_info of AXI4_Lite_WDATA : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WDATA";
attribute x_interface_info of AXI4_Lite_WSTRB : signal is "xilinx.com:interface:aximm:1.0 AXI4_Lite WSTRB";
begin
AXI4_Lite_BRESP(1) <= \<const0>\;
AXI4_Lite_BRESP(0) <= \<const0>\;
AXI4_Lite_RDATA(31) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(30) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(29) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(28) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(27) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(26) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(25) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(24) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(23) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(22) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(21) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(20) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(19) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(18) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(17) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(16) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(15) <= \^axi4_lite_rdata\(30);
AXI4_Lite_RDATA(14 downto 0) <= \^axi4_lite_rdata\(14 downto 0);
AXI4_Lite_RRESP(1) <= \<const0>\;
AXI4_Lite_RRESP(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lms_pcore
port map (
AXI4_Lite_ACLK => AXI4_Lite_ACLK,
AXI4_Lite_ARADDR(13 downto 0) => AXI4_Lite_ARADDR(15 downto 2),
AXI4_Lite_ARESETN => AXI4_Lite_ARESETN,
AXI4_Lite_ARREADY => AXI4_Lite_ARREADY,
AXI4_Lite_ARVALID => AXI4_Lite_ARVALID,
AXI4_Lite_AWADDR(13 downto 0) => AXI4_Lite_AWADDR(15 downto 2),
AXI4_Lite_AWREADY => AXI4_Lite_AWREADY,
AXI4_Lite_AWVALID => AXI4_Lite_AWVALID,
AXI4_Lite_BREADY => AXI4_Lite_BREADY,
AXI4_Lite_BVALID => AXI4_Lite_BVALID,
AXI4_Lite_RDATA(15) => \^axi4_lite_rdata\(30),
AXI4_Lite_RDATA(14 downto 0) => \^axi4_lite_rdata\(14 downto 0),
AXI4_Lite_RREADY => AXI4_Lite_RREADY,
AXI4_Lite_RVALID => AXI4_Lite_RVALID,
AXI4_Lite_WDATA(15 downto 0) => AXI4_Lite_WDATA(15 downto 0),
AXI4_Lite_WREADY => AXI4_Lite_WREADY,
AXI4_Lite_WVALID => AXI4_Lite_WVALID,
IPCORE_CLK => IPCORE_CLK,
IPCORE_RESETN => IPCORE_RESETN
);
end STRUCTURE;
| mit | cbef84fca5dcc3939be4e5f29fa5ffb8 | 0.528968 | 2.58885 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/lab3_project.xpr/project_1/project_1.srcs/sources_1/bd/design_1/ip/design_1_axi_cdma_0_0/synth/design_1_axi_cdma_0_0.vhd | 1 | 20,628 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_cdma:4.1
-- IP Revision: 14
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_cdma_v4_1_14;
USE axi_cdma_v4_1_14.axi_cdma;
ENTITY design_1_axi_cdma_0_0 IS
PORT (
m_axi_aclk : IN STD_LOGIC;
s_axi_lite_aclk : IN STD_LOGIC;
s_axi_lite_aresetn : IN STD_LOGIC;
cdma_introut : OUT STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arready : IN STD_LOGIC;
m_axi_arvalid : OUT STD_LOGIC;
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_rready : OUT STD_LOGIC;
m_axi_rvalid : IN STD_LOGIC;
m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wready : IN STD_LOGIC;
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
m_axi_bvalid : IN STD_LOGIC;
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
cdma_tvect_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_axi_cdma_0_0;
ARCHITECTURE design_1_axi_cdma_0_0_arch OF design_1_axi_cdma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_cdma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_cdma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_AXI_LITE_IS_ASYNC : INTEGER;
C_M_AXI_ADDR_WIDTH : INTEGER;
C_M_AXI_DATA_WIDTH : INTEGER;
C_M_AXI_MAX_BURST_LEN : INTEGER;
C_INCLUDE_DRE : INTEGER;
C_USE_DATAMOVER_LITE : INTEGER;
C_READ_ADDR_PIPE_DEPTH : INTEGER;
C_WRITE_ADDR_PIPE_DEPTH : INTEGER;
C_INCLUDE_SF : INTEGER;
C_INCLUDE_SG : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_FAMILY : STRING
);
PORT (
m_axi_aclk : IN STD_LOGIC;
s_axi_lite_aclk : IN STD_LOGIC;
s_axi_lite_aresetn : IN STD_LOGIC;
cdma_introut : OUT STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arready : IN STD_LOGIC;
m_axi_arvalid : OUT STD_LOGIC;
m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_rready : OUT STD_LOGIC;
m_axi_rvalid : IN STD_LOGIC;
m_axi_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_rlast : IN STD_LOGIC;
m_axi_awready : IN STD_LOGIC;
m_axi_awvalid : OUT STD_LOGIC;
m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wready : IN STD_LOGIC;
m_axi_wvalid : OUT STD_LOGIC;
m_axi_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_wlast : OUT STD_LOGIC;
m_axi_bready : OUT STD_LOGIC;
m_axi_bvalid : IN STD_LOGIC;
m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
cdma_tvect_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_cdma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_axi_cdma_0_0_arch: ARCHITECTURE IS "axi_cdma,Vivado 2017.3";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_axi_cdma_0_0_arch : ARCHITECTURE IS "design_1_axi_cdma_0_0,axi_cdma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_axi_cdma_0_0_arch: ARCHITECTURE IS "design_1_axi_cdma_0_0,axi_cdma,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_cdma,x_ipVersion=4.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=6,C_S_AXI_LITE_DATA_WIDTH=32,C_AXI_LITE_IS_ASYNC=0,C_M_AXI_ADDR_WIDTH=32,C_M_AXI_DATA_WIDTH=32,C_M_AXI_MAX_BURST_LEN=256,C_INCLUDE_DRE=0,C_USE_DATAMOVER_LITE=0,C_READ_ADDR_PIPE_DEPTH=4,C_WRITE_ADDR_PIPE_DEPTH=4,C_INCLUDE_SF=0,C_INCLUDE_SG=0,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WI" &
"DTH=32,C_DLYTMR_RESOLUTION=256,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_arready: SIGNAL IS "XIL_INTERFACENAME M_AXI, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_awready: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 6, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 0, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_PARAMETER OF cdma_introut: SIGNAL IS "XIL_INTERFACENAME CDMA_INTERRUPT, SENSITIVITY LEVEL_HIGH, PortWidth 1";
ATTRIBUTE X_INTERFACE_INFO OF cdma_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 CDMA_INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aresetn: SIGNAL IS "XIL_INTERFACENAME AXI_RESETN, POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_PARAMETER OF s_axi_lite_aclk: SIGNAL IS "XIL_INTERFACENAME S_AXI_LITE_ACLK, ASSOCIATED_BUSIF S_AXI_LITE, ASSOCIATED_RESET s_axi_lite_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_PARAMETER OF m_axi_aclk: SIGNAL IS "XIL_INTERFACENAME M_AXI_ACLK, ASSOCIATED_BUSIF M_AXI:M_AXI_SG, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_ACLK CLK";
BEGIN
U0 : axi_cdma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 6,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_AXI_LITE_IS_ASYNC => 0,
C_M_AXI_ADDR_WIDTH => 32,
C_M_AXI_DATA_WIDTH => 32,
C_M_AXI_MAX_BURST_LEN => 256,
C_INCLUDE_DRE => 0,
C_USE_DATAMOVER_LITE => 0,
C_READ_ADDR_PIPE_DEPTH => 4,
C_WRITE_ADDR_PIPE_DEPTH => 4,
C_INCLUDE_SF => 0,
C_INCLUDE_SG => 0,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 256,
C_FAMILY => "zynq"
)
PORT MAP (
m_axi_aclk => m_axi_aclk,
s_axi_lite_aclk => s_axi_lite_aclk,
s_axi_lite_aresetn => s_axi_lite_aresetn,
cdma_introut => cdma_introut,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arprot => m_axi_arprot,
m_axi_arcache => m_axi_arcache,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_axi_rdata => m_axi_rdata,
m_axi_rresp => m_axi_rresp,
m_axi_rlast => m_axi_rlast,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awprot => m_axi_awprot,
m_axi_awcache => m_axi_awcache,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
m_axi_bresp => m_axi_bresp,
m_axi_sg_awready => '0',
m_axi_sg_wready => '0',
m_axi_sg_bvalid => '0',
m_axi_sg_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_arready => '0',
m_axi_sg_rvalid => '0',
m_axi_sg_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
m_axi_sg_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_sg_rlast => '0',
cdma_tvect_out => cdma_tvect_out
);
END design_1_axi_cdma_0_0_arch;
| mit | 7712e828835edbae80f29519b26db9c7 | 0.687124 | 3.041581 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-asic/pads.vhd | 1 | 26,638 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.config.all;
library techmap;
use techmap.gencomp.all;
entity pads is
generic (
padtech : integer := 0;
padlevel : integer := 0;
padvoltage : integer := 0;
padfilter : integer := 0;
padstrength : integer := 0;
padslew : integer := 0;
padclkarch : integer := 0;
padhf : integer := 0;
spw_input_type : integer := 0;
jtag_padfilter : integer := 0;
testen_padfilter : integer := 0;
resetn_padfilter : integer := 0;
clk_padfilter : integer := 0;
spw_padstrength : integer := 0;
jtag_padstrength : integer := 0;
uart_padstrength : integer := 0;
dsu_padstrength : integer := 0;
oepol : integer := 0
);
port (
----------------------------------------------------------------------------
--to chip boundary
----------------------------------------------------------------------------
resetn : in std_ulogic;
clksel : in std_logic_vector (1 downto 0);
clk : in std_ulogic;
lock : out std_ulogic;
errorn : inout std_ulogic;
address : out std_logic_vector(27 downto 0);
data : inout std_logic_vector(31 downto 0);
cb : inout std_logic_vector(7 downto 0);
sdclk : out std_ulogic;
sdcsn : out std_logic_vector (1 downto 0);
sdwen : out std_ulogic;
sdrasn : out std_ulogic;
sdcasn : out std_ulogic;
sddqm : out std_logic_vector (3 downto 0);
dsutx : out std_ulogic;
dsurx : in std_ulogic;
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic;
rxd1 : in std_ulogic;
txd2 : out std_ulogic;
rxd2 : in std_ulogic;
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
wdogn : inout std_ulogic;
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
i2c_scl : inout std_ulogic;
i2c_sda : inout std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector (1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdio : inout std_logic;
emdc : out std_ulogic;
testen : in std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
---------------------------------------------------------------------------
--to core
---------------------------------------------------------------------------
lresetn : out std_ulogic;
lclksel : out std_logic_vector (1 downto 0);
lclk : out std_ulogic;
llock : in std_ulogic;
lerrorn : in std_ulogic;
laddress : in std_logic_vector(27 downto 0);
ldatain : out std_logic_vector(31 downto 0);
ldataout : in std_logic_vector(31 downto 0);
ldataen : in std_logic_vector(31 downto 0);
lcbin : out std_logic_vector(7 downto 0);
lcbout : in std_logic_vector(7 downto 0);
lcben : in std_logic_vector(7 downto 0);
lsdclk : in std_ulogic;
lsdcsn : in std_logic_vector (1 downto 0);
lsdwen : in std_ulogic;
lsdrasn : in std_ulogic;
lsdcasn : in std_ulogic;
lsddqm : in std_logic_vector (3 downto 0);
ldsutx : in std_ulogic;
ldsurx : out std_ulogic;
ldsuen : out std_ulogic;
ldsubre : out std_ulogic;
ldsuact : in std_ulogic;
ltxd1 : in std_ulogic;
lrxd1 : out std_ulogic;
ltxd2 : in std_ulogic;
lrxd2 : out std_ulogic;
lramsn : in std_logic_vector (4 downto 0);
lramoen : in std_logic_vector (4 downto 0);
lrwen : in std_logic_vector (3 downto 0);
loen : in std_ulogic;
lwriten : in std_ulogic;
lread : in std_ulogic;
liosn : in std_ulogic;
lromsn : in std_logic_vector (1 downto 0);
lbrdyn : out std_ulogic;
lbexcn : out std_ulogic;
lwdogn : in std_ulogic;
lgpioin : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
lgpioout : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
lgpioen : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
li2c_sclout : in std_ulogic;
li2c_sclen : in std_ulogic;
li2c_sclin : out std_ulogic;
li2c_sdaout : in std_ulogic;
li2c_sdaen : in std_ulogic;
li2c_sdain : out std_ulogic;
lspi_miso : out std_ulogic;
lspi_mosi : in std_ulogic;
lspi_sck : in std_ulogic;
lspi_slvsel : in std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
lprom32 : out std_ulogic;
lspw_clksel : out std_logic_vector (1 downto 0);
lspw_clk : out std_ulogic;
lspw_rxd : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_rxs : out std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txd : in std_logic_vector(0 to CFG_SPW_NUM-1);
lspw_txs : in std_logic_vector(0 to CFG_SPW_NUM-1);
lgtx_clk : out std_ulogic;
lerx_clk : out std_ulogic;
lerxd : out std_logic_vector(7 downto 0);
lerx_dv : out std_ulogic;
letx_clk : out std_ulogic;
letxd : in std_logic_vector(7 downto 0);
letx_en : in std_ulogic;
letx_er : in std_ulogic;
lerx_er : out std_ulogic;
lerx_col : out std_ulogic;
lerx_crs : out std_ulogic;
lemdint : out std_ulogic;
lemdioin : out std_logic;
lemdioout : in std_logic;
lemdioen : in std_logic;
lemdc : in std_ulogic;
ltesten : out std_ulogic;
ltrst : out std_ulogic;
ltck : out std_ulogic;
ltms : out std_ulogic;
ltdi : out std_ulogic;
ltdo : in std_ulogic;
ltdoen : in std_ulogic
);
end;
architecture rtl of pads is
signal vcc,gnd : std_logic;
begin
vcc <= '1';
gnd <= '0';
------------------------------------------------------------------------------
-- Clocking and clock pads
------------------------------------------------------------------------------
reset_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => resetn_padfilter,
strength => padstrength)
port map (
pad => resetn,
o => lresetn);
clk_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => clk,
o => lclk);
clksel_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 2)
port map(
pad => clksel,
o => lclksel);
spwclk_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => spw_clk,
o => lspw_clk);
spwclksel_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 2)
port map(
pad => spw_clksel,
o => lspw_clksel);
------------------------------------------------------------------------------
-- Test / Misc pads
------------------------------------------------------------------------------
wdogn_pad : toutpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength,
oepol => oepol)
port map(
pad => wdogn,
en => lwdogn,
i => gnd);
testen_pad : inpad
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => testen_padfilter,
strength => padstrength)
port map(
pad => testen,
o => ltesten);
lockpad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (
pad => lock,
i => llock);
errorn_pad : toutpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength,
oepol => oepol)
port map(
pad => errorn,
en => lerrorn,
i => gnd);
------------------------------------------------------------------------------
-- JTAG pads
------------------------------------------------------------------------------
trst_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => trst,
o => ltrst);
tck_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tck,
o => ltck);
tms_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tms,
o => ltms);
tdi_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => jtag_padfilter)
port map (
pad => tdi,
o => ltdi);
tdo_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => jtag_padstrength)
port map (
pad => tdo,
i => ltdo);
------------------------------------------------------------------------------
-- DSU pads
------------------------------------------------------------------------------
dsuen_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsuen,
o => ldsuen);
dsubre_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsubre,
o => ldsubre);
dsuact_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => dsu_padstrength)
port map (
pad => dsuact,
i => ldsuact);
dsurx_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter)
port map (
pad => dsurx,
o => ldsurx);
dsutx_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => dsu_padstrength)
port map (
pad => dsutx,
i => ldsutx);
------------------------------------------------------------------------------
-- UART pads
------------------------------------------------------------------------------
rxd1_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (
pad => rxd1,
o => lrxd1);
txd1_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => uart_padstrength)
port map (
pad => txd1,
i => ltxd1);
rxd2_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (
pad => rxd2,
o => lrxd2);
txd2_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => uart_padstrength)
port map (
pad => txd2,
i => ltxd2);
------------------------------------------------------------------------------
-- SPI pads
------------------------------------------------------------------------------
miso_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map(
pad => spi_miso,
o => lspi_miso);
mosi_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map(
pad => spi_mosi,
i => lspi_mosi);
sck_pad : outpad
generic map (
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map(
pad => spi_sck,
i => lspi_sck);
slvsel_pad : outpadv
generic map (
width => CFG_SPICTRL_SLVS,
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (
pad => spi_slvsel,
i => lspi_slvsel);
------------------------------------------------------------------------------
-- I2C pads
------------------------------------------------------------------------------
scl_pad : iopad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => i2c_scl,
i => li2c_sclout,
en => li2c_sclen,
o => li2c_sclin);
sda_pad : iopad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => i2c_sda,
i => li2c_sdaout,
en => li2c_sdaen,
o => li2c_sdain);
------------------------------------------------------------------------------
-- Memory Interface pads
------------------------------------------------------------------------------
addr_pad : outpadv generic map (width => 28, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (address, laddress);
data_pad : iopadvv generic map (width => 32, tech => padtech, level => padlevel, voltage => padvoltage, oepol => oepol, strength => padstrength) port map (pad => data, i => ldataout, en => ldataen, o => ldatain);
rams_pad : outpadv generic map (width => 5, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (ramsn, lramsn);
roms_pad : outpadv generic map (width => 2, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (romsn, lromsn);
ramoen_pad : outpadv generic map (width => 5, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (ramoen, lramoen);
rwen_pad : outpadv generic map (width => 4, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (rwen, lrwen);
oen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (oen, loen);
wri_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (writen, lwriten);
read_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (read, lread);
iosn_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (iosn, liosn);
cb_pad : iopadvv generic map (width => 8, tech => padtech, level => padlevel, voltage => padvoltage, oepol => oepol, strength => padstrength) port map (pad => cb, i => lcbout, en => lcben, o => lcbin);
sdpads : if CFG_MCTRL_SDEN = 1 generate
sdclk_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdclk, lsdclk);
sdwen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdwen, lsdwen);
sdras_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdrasn, lsdrasn);
sdcas_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdcasn, lsdcasn);
sddqm_pad : outpadv generic map (width => 4, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sddqm, lsddqm);
sdcsn_pad : outpadv generic map (width => 2, tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength) port map (sdcsn, lsdcsn);
end generate;
brdyn_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => brdyn,
o => lbrdyn);
bexcn_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => bexcn,
o => lbexcn);
prom32_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => pullup)
port map (
pad => prom32,
o => lprom32);
------------------------------------------------------------------------------
-- GPIO pads
------------------------------------------------------------------------------
gpio_pads : iopadvv
generic map (
width => CFG_GRGPIO_WIDTH,
tech => padtech,
level => padlevel,
voltage => padvoltage,
oepol => oepol,
strength => padstrength)
port map (
pad => gpio,
i => lgpioout,
en => lgpioen,
o => lgpioin);
------------------------------------------------------------------------------
-- SpW pads
------------------------------------------------------------------------------
spwpads0 : if CFG_SPW_EN > 0 generate
spwlvttl_pads : entity work.spw_lvttl_pads
generic map(
padtech => padtech,
strength => spw_padstrength,
input_type => spw_input_type,
voltage => padvoltage,
level => padlevel)
port map(
spw_rxd => spw_rxd,
spw_rxs => spw_rxs,
spw_txd => spw_txd,
spw_txs => spw_txs,
lspw_rxd => lspw_rxd,
lspw_rxs => lspw_rxs,
lspw_txd => lspw_txd,
lspw_txs => lspw_txs);
end generate;
nospwpads0 : if CFG_SPW_EN = 0 generate
spw_txd <= (others => '0');
spw_txs <= (others => '0');
lspw_rxd <= (others => '0');
lspw_rxs <= (others => '0');
end generate;
------------------------------------------------------------------------------
-- ETHERNET
------------------------------------------------------------------------------
greth1g: if CFG_GRETH1G = 1 generate
gtx_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (
pad => gtx_clk,
o => lgtx_clk);
end generate;
nogreth1g: if CFG_GRETH1G = 0 generate
lgtx_clk <= '0';
end generate;
ethpads : if (CFG_GRETH = 1) generate
etxc_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (etx_clk, letx_clk);
erxc_pad : clkpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
arch => padclkarch,
hf => padhf,
filter => clk_padfilter)
port map (erx_clk, lerx_clk);
erxd_pad : inpadv
generic map(
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength,
width => 8)
port map (erxd, lerxd);
erxdv_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_dv, lerx_dv);
erxer_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_er, lerx_er);
erxco_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_col, lerx_col);
erxcr_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (erx_crs, lerx_crs);
etxd_pad : outpadv
generic map(
width => 8,
tech => padtech,
level => padlevel,
slew => padslew,
voltage => padvoltage,
strength => padstrength)
port map (etxd, letxd);
etxen_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (etx_en, letx_en);
etxer_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (etx_er, letx_er);
emdc_pad : outpad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (emdc, lemdc);
emdio_pad : iopad generic map (tech => padtech, level => padlevel, slew => padslew, voltage => padvoltage, strength => padstrength)
port map (emdio, lemdioout, lemdioen, lemdioin);
emdint_pad : inpad
generic map (
tech => padtech,
level => padlevel,
voltage => padvoltage,
filter => padfilter,
strength => padstrength)
port map (emdint, lemdint);
end generate;
end;
| gpl-2.0 | 03c55339b34f94e68b6abf16e429db93 | 0.479878 | 4.206886 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/skew_outpad.vhd | 1 | 2,082 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: skew_outpad
-- File: skew_outpad.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity skew_outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end;
architecture rtl of skew_outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else i;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_skew_outpad generic map (level, slew, voltage, strength, skew) port map (pad, i, rst, o);
end generate;
end;
| gpl-2.0 | 419b5c0904b64a957d650232f97fd33e | 0.617675 | 3.973282 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.cache/ip/2017.2/75df72de079a856e/zqynq_lab_1_design_xbar_0_sim_netlist.vhdl | 1 | 845,215 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:10:34 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_xbar_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_xbar_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter is
port (
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
aa_mi_arvalid : out STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rlast_i0 : out STD_LOGIC;
\m_axi_arqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
ADDRESS_HIT_0 : out STD_LOGIC;
match : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ : out STD_LOGIC;
sel_4 : out STD_LOGIC;
sel_2 : out STD_LOGIC;
ADDRESS_HIT_3 : out STD_LOGIC;
ADDRESS_HIT_1 : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[3].r_issuing_cnt_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_1\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : out STD_LOGIC;
p_39_in : out STD_LOGIC;
p_57_in : out STD_LOGIC;
p_75_in : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]_0\ : out STD_LOGIC;
\gen_master_slots[4].r_issuing_cnt_reg[32]\ : out STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_arready_4 : in STD_LOGIC;
p_23_in : in STD_LOGIC;
\read_cs__0\ : in STD_LOGIC;
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
r_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
\r_cmd_pop_0__1\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
\r_cmd_pop_1__1\ : in STD_LOGIC;
\r_cmd_pop_3__1\ : in STD_LOGIC;
\r_cmd_pop_2__1\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
\s_axi_araddr[18]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter is
signal \^address_hit_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^aa_mi_arvalid\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[1]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_3_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \^m_axi_arqos[15]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^match\ : STD_LOGIC;
signal s_ready_i2 : STD_LOGIC;
signal \^sel_2\ : STD_LOGIC;
signal \^sel_4\ : STD_LOGIC;
signal st_aa_artarget_hot : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_rid_i[11]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_4\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[10]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gen_master_slots[1].r_issuing_cnt[11]_i_4\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[19]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gen_master_slots[2].r_issuing_cnt[19]_i_4\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[26]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_2\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_4\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[1]_i_2__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[2]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[3]_i_1__0\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[3]_i_4__0\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_valid_i_i_1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_26__0\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \m_axi_arvalid[0]_INST_0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \m_axi_arvalid[1]_INST_0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \m_axi_arvalid[2]_INST_0\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \m_axi_arvalid[3]_INST_0\ : label is "soft_lutpair3";
begin
ADDRESS_HIT_0 <= \^address_hit_0\;
Q(0) <= \^q\(0);
S_AXI_ARREADY(0) <= \^s_axi_arready\(0);
aa_mi_arvalid <= \^aa_mi_arvalid\;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ <= \^gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\;
\m_axi_arqos[15]\(68 downto 0) <= \^m_axi_arqos[15]\(68 downto 0);
match <= \^match\;
sel_2 <= \^sel_2\;
sel_4 <= \^sel_4\;
\gen_axi.s_axi_rid_i[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
I2 => mi_arready_4,
I3 => p_23_in,
O => \gen_axi.s_axi_rid_i_reg[11]\(0)
);
\gen_axi.s_axi_rlast_i_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"55035500"
)
port map (
I0 => \read_cs__0\,
I1 => \^m_axi_arqos[15]\(45),
I2 => \^m_axi_arqos[15]\(44),
I3 => p_23_in,
I4 => \gen_axi.s_axi_rlast_i_i_5_n_0\,
O => s_axi_rlast_i0
);
\gen_axi.s_axi_rlast_i_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \^m_axi_arqos[15]\(46),
I1 => \^m_axi_arqos[15]\(47),
I2 => \^m_axi_arqos[15]\(48),
I3 => \^m_axi_arqos[15]\(49),
I4 => \^m_axi_arqos[15]\(51),
I5 => \^m_axi_arqos[15]\(50),
O => \gen_axi.s_axi_rlast_i_i_5_n_0\
);
\gen_master_slots[0].r_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \r_cmd_pop_0__1\,
I2 => m_axi_arready(0),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(0),
I5 => r_issuing_cnt(1),
O => D(0)
);
\gen_master_slots[0].r_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I1 => r_issuing_cnt(1),
I2 => r_issuing_cnt(2),
O => D(1)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(1),
I1 => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\,
I2 => r_issuing_cnt(3),
I3 => r_issuing_cnt(2),
O => D(2)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(0),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(0),
O => p_93_in
);
\gen_master_slots[0].r_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(0),
I1 => \r_cmd_pop_0__1\,
I2 => m_axi_arready(0),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(0),
I5 => r_issuing_cnt(1),
O => \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I1 => r_issuing_cnt(5),
I2 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(5),
I1 => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\,
I2 => r_issuing_cnt(7),
I3 => r_issuing_cnt(6),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(1),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(1),
O => p_75_in
);
\gen_master_slots[1].r_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \r_cmd_pop_1__1\,
I2 => m_axi_arready(1),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(1),
I5 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].r_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(4),
I1 => \r_cmd_pop_1__1\,
I2 => m_axi_arready(1),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(1),
I5 => r_issuing_cnt(5),
O => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0)
);
\gen_master_slots[2].r_issuing_cnt[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(8),
I1 => \r_cmd_pop_2__1\,
I2 => m_axi_arready(2),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(2),
I5 => r_issuing_cnt(9),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0)
);
\gen_master_slots[2].r_issuing_cnt[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\,
I1 => r_issuing_cnt(9),
I2 => r_issuing_cnt(10),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(9),
I1 => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\,
I2 => r_issuing_cnt(11),
I3 => r_issuing_cnt(10),
O => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(2),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(2),
O => p_57_in
);
\gen_master_slots[2].r_issuing_cnt[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(8),
I1 => \r_cmd_pop_2__1\,
I2 => m_axi_arready(2),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(2),
I5 => r_issuing_cnt(9),
O => \gen_master_slots[2].r_issuing_cnt[19]_i_5_n_0\
);
\gen_master_slots[3].r_issuing_cnt[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9AAAAAAA65555555"
)
port map (
I0 => r_issuing_cnt(12),
I1 => \r_cmd_pop_3__1\,
I2 => m_axi_arready(3),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(3),
I5 => r_issuing_cnt(13),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(0)
);
\gen_master_slots[3].r_issuing_cnt[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\,
I1 => r_issuing_cnt(13),
I2 => r_issuing_cnt(14),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(1)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => r_issuing_cnt(13),
I1 => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\,
I2 => r_issuing_cnt(15),
I3 => r_issuing_cnt(14),
O => \gen_master_slots[3].r_issuing_cnt_reg[27]\(2)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => m_axi_arready(3),
I1 => \^aa_mi_arvalid\,
I2 => aa_mi_artarget_hot(3),
O => p_39_in
);
\gen_master_slots[3].r_issuing_cnt[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"20000000BAAAAAAA"
)
port map (
I0 => r_issuing_cnt(12),
I1 => \r_cmd_pop_3__1\,
I2 => m_axi_arready(3),
I3 => \^aa_mi_arvalid\,
I4 => aa_mi_artarget_hot(3),
I5 => r_issuing_cnt(13),
O => \gen_master_slots[3].r_issuing_cnt[27]_i_5_n_0\
);
\gen_master_slots[4].r_issuing_cnt[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"807F0080"
)
port map (
I0 => \^q\(0),
I1 => \^aa_mi_arvalid\,
I2 => mi_arready_4,
I3 => \r_cmd_pop_4__1\,
I4 => r_issuing_cnt(16),
O => \gen_master_slots[4].r_issuing_cnt_reg[32]\
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0808080"
)
port map (
I0 => \^sel_2\,
I1 => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\,
I2 => \^sel_4\,
I3 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I4 => \gen_no_arbiter.m_target_hot_i[1]_i_2__0_n_0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A080"
)
port map (
I0 => \^sel_2\,
I1 => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\,
I2 => \^sel_4\,
I3 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\,
O => \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]_0\
);
\gen_no_arbiter.m_mesg_i[11]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_mi_arvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(0),
Q => \^m_axi_arqos[15]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(10),
Q => \^m_axi_arqos[15]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(11),
Q => \^m_axi_arqos[15]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(12),
Q => \^m_axi_arqos[15]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(13),
Q => \^m_axi_arqos[15]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(14),
Q => \^m_axi_arqos[15]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(15),
Q => \^m_axi_arqos[15]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(16),
Q => \^m_axi_arqos[15]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(17),
Q => \^m_axi_arqos[15]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(18),
Q => \^m_axi_arqos[15]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(19),
Q => \^m_axi_arqos[15]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(1),
Q => \^m_axi_arqos[15]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(20),
Q => \^m_axi_arqos[15]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(21),
Q => \^m_axi_arqos[15]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(22),
Q => \^m_axi_arqos[15]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(23),
Q => \^m_axi_arqos[15]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(24),
Q => \^m_axi_arqos[15]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(25),
Q => \^m_axi_arqos[15]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(26),
Q => \^m_axi_arqos[15]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(27),
Q => \^m_axi_arqos[15]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(28),
Q => \^m_axi_arqos[15]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(29),
Q => \^m_axi_arqos[15]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(2),
Q => \^m_axi_arqos[15]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(30),
Q => \^m_axi_arqos[15]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(31),
Q => \^m_axi_arqos[15]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(32),
Q => \^m_axi_arqos[15]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(33),
Q => \^m_axi_arqos[15]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(34),
Q => \^m_axi_arqos[15]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(35),
Q => \^m_axi_arqos[15]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(36),
Q => \^m_axi_arqos[15]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(37),
Q => \^m_axi_arqos[15]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(38),
Q => \^m_axi_arqos[15]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(39),
Q => \^m_axi_arqos[15]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(3),
Q => \^m_axi_arqos[15]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(40),
Q => \^m_axi_arqos[15]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(41),
Q => \^m_axi_arqos[15]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(42),
Q => \^m_axi_arqos[15]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(43),
Q => \^m_axi_arqos[15]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(44),
Q => \^m_axi_arqos[15]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(45),
Q => \^m_axi_arqos[15]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(46),
Q => \^m_axi_arqos[15]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(47),
Q => \^m_axi_arqos[15]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(48),
Q => \^m_axi_arqos[15]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(49),
Q => \^m_axi_arqos[15]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(4),
Q => \^m_axi_arqos[15]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(50),
Q => \^m_axi_arqos[15]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(51),
Q => \^m_axi_arqos[15]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(52),
Q => \^m_axi_arqos[15]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(53),
Q => \^m_axi_arqos[15]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(54),
Q => \^m_axi_arqos[15]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(55),
Q => \^m_axi_arqos[15]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(56),
Q => \^m_axi_arqos[15]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(57),
Q => \^m_axi_arqos[15]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(58),
Q => \^m_axi_arqos[15]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(5),
Q => \^m_axi_arqos[15]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(59),
Q => \^m_axi_arqos[15]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(60),
Q => \^m_axi_arqos[15]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(61),
Q => \^m_axi_arqos[15]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(62),
Q => \^m_axi_arqos[15]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(63),
Q => \^m_axi_arqos[15]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(64),
Q => \^m_axi_arqos[15]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(6),
Q => \^m_axi_arqos[15]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(65),
Q => \^m_axi_arqos[15]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(66),
Q => \^m_axi_arqos[15]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(67),
Q => \^m_axi_arqos[15]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(68),
Q => \^m_axi_arqos[15]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(7),
Q => \^m_axi_arqos[15]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(8),
Q => \^m_axi_arqos[15]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => \s_axi_arqos[3]\(9),
Q => \^m_axi_arqos[15]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^address_hit_0\,
I1 => \^match\,
O => st_aa_artarget_hot(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
I4 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I5 => \^sel_4\,
O => \^address_hit_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^sel_4\,
I1 => \gen_no_arbiter.m_target_hot_i[1]_i_2__0_n_0\,
I2 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
O => st_aa_artarget_hot(1)
);
\gen_no_arbiter.m_target_hot_i[1]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
O => \gen_no_arbiter.m_target_hot_i[1]_i_2__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => \s_axi_arqos[3]\(34),
I1 => \s_axi_arqos[3]\(35),
I2 => \s_axi_arqos[3]\(33),
I3 => \s_axi_arqos[3]\(32),
I4 => \s_axi_arqos[3]\(37),
I5 => \s_axi_arqos[3]\(36),
O => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
\gen_no_arbiter.m_target_hot_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^sel_4\,
I1 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\,
I2 => \^sel_2\,
O => st_aa_artarget_hot(2)
);
\gen_no_arbiter.m_target_hot_i[2]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => \s_axi_arqos[3]\(35),
I1 => \s_axi_arqos[3]\(34),
I2 => \s_axi_arqos[3]\(32),
I3 => \s_axi_arqos[3]\(33),
I4 => \s_axi_arqos[3]\(36),
I5 => \s_axi_arqos[3]\(37),
O => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\
);
\gen_no_arbiter.m_target_hot_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^sel_4\,
I1 => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\,
I2 => \^sel_2\,
O => st_aa_artarget_hot(3)
);
\gen_no_arbiter.m_target_hot_i[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => \s_axi_arqos[3]\(40),
I1 => \s_axi_arqos[3]\(41),
I2 => \s_axi_arqos[3]\(38),
I3 => \s_axi_arqos[3]\(39),
I4 => \s_axi_arqos[3]\(43),
I5 => \s_axi_arqos[3]\(42),
O => \^sel_4\
);
\gen_no_arbiter.m_target_hot_i[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \s_axi_arqos[3]\(34),
I1 => \s_axi_arqos[3]\(35),
I2 => \s_axi_arqos[3]\(32),
I3 => \s_axi_arqos[3]\(33),
I4 => \s_axi_arqos[3]\(37),
I5 => \s_axi_arqos[3]\(36),
O => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
O => \^sel_2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFE0000F0000000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\,
I1 => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\,
I2 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I3 => \gen_no_arbiter.m_target_hot_i[1]_i_2__0_n_0\,
I4 => \^sel_4\,
I5 => \^sel_2\,
O => \^match\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_artarget_hot(0),
Q => aa_mi_artarget_hot(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_artarget_hot(1),
Q => aa_mi_artarget_hot(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_artarget_hot(2),
Q => aa_mi_artarget_hot(2),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_artarget_hot(3),
Q => aa_mi_artarget_hot(3),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \s_axi_araddr[18]\(0),
Q => \^q\(0),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"DC"
)
port map (
I0 => \gen_no_arbiter.m_valid_i_i_2_n_0\,
I1 => m_valid_i,
I2 => \^aa_mi_arvalid\,
O => \gen_no_arbiter.m_valid_i_i_1_n_0\
);
\gen_no_arbiter.m_valid_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF88800000000"
)
port map (
I0 => m_axi_arready(2),
I1 => aa_mi_artarget_hot(2),
I2 => m_axi_arready(1),
I3 => aa_mi_artarget_hot(1),
I4 => \gen_no_arbiter.m_valid_i_i_3_n_0\,
I5 => \^aa_mi_arvalid\,
O => \gen_no_arbiter.m_valid_i_i_2_n_0\
);
\gen_no_arbiter.m_valid_i_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => m_axi_arready(0),
I2 => \^q\(0),
I3 => mi_arready_4,
I4 => m_axi_arready(3),
I5 => aa_mi_artarget_hot(3),
O => \gen_no_arbiter.m_valid_i_i_3_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1_n_0\,
Q => \^aa_mi_arvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_15__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_arvalid(0),
I1 => \^s_axi_arready\(0),
O => \gen_no_arbiter.s_ready_i_reg[0]_1\
);
\gen_no_arbiter.s_ready_i[0]_i_21__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \gen_slave_slots[0].gen_si_read.si_transactor_ar/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I1 => \s_axi_arqos[3]\(29),
I2 => \s_axi_arqos[3]\(28),
I3 => \s_axi_arqos[3]\(31),
I4 => \s_axi_arqos[3]\(30),
I5 => \^sel_4\,
O => ADDRESS_HIT_1
);
\gen_no_arbiter.s_ready_i[0]_i_23__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \s_axi_arqos[3]\(29),
I1 => \s_axi_arqos[3]\(28),
I2 => \s_axi_arqos[3]\(31),
I3 => \s_axi_arqos[3]\(30),
I4 => \gen_no_arbiter.m_target_hot_i[3]_i_3__0_n_0\,
I5 => \^sel_4\,
O => ADDRESS_HIT_3
);
\gen_no_arbiter.s_ready_i[0]_i_26__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => r_issuing_cnt(10),
I1 => r_issuing_cnt(9),
I2 => r_issuing_cnt(11),
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => E(0),
Q => \^s_axi_arready\(0),
R => '0'
);
\m_axi_arvalid[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(0),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(0)
);
\m_axi_arvalid[1]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(1),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(1)
);
\m_axi_arvalid[2]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(2),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(2)
);
\m_axi_arvalid[3]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => aa_mi_artarget_hot(3),
I1 => \^aa_mi_arvalid\,
O => m_axi_arvalid(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 is
port (
ss_aa_awready : out STD_LOGIC;
aa_sa_awvalid : out STD_LOGIC;
\mi_awready_mux__3\ : out STD_LOGIC;
\s_ready_i0__1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
p_84_in : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
p_66_in : out STD_LOGIC;
p_48_in : out STD_LOGIC;
p_101_in : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
write_cs01_out : out STD_LOGIC;
ADDRESS_HIT_0 : out STD_LOGIC;
match : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ : out STD_LOGIC;
sel_4 : out STD_LOGIC;
sel_2 : out STD_LOGIC;
ADDRESS_HIT_3 : out STD_LOGIC;
ADDRESS_HIT_1 : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_1\ : out STD_LOGIC;
\sa_wm_awready_mux__3\ : out STD_LOGIC;
st_aa_awtarget_enc : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gen_master_slots[4].w_issuing_cnt_reg[32]\ : out STD_LOGIC;
\m_axi_awqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_valid_i : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
mi_awready_4 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 68 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_ready_d_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_awaddr[18]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 : entity is "axi_crossbar_v2_1_14_addr_arbiter";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 is
signal \^address_hit_0\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \^aa_sa_awvalid\ : STD_LOGIC;
signal \^gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[1]_i_2_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\ : STD_LOGIC;
signal \m_ready_d[1]_i_4_n_0\ : STD_LOGIC;
signal \^match\ : STD_LOGIC;
signal \^mi_awready_mux__3\ : STD_LOGIC;
signal \^s_ready_i0__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal s_ready_i2 : STD_LOGIC;
signal \^sel_2\ : STD_LOGIC;
signal \^sel_4\ : STD_LOGIC;
signal \^ss_aa_awready\ : STD_LOGIC;
signal st_aa_awtarget_hot : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^write_cs01_out\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_wready_i_i_2\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_4\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_4\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_4\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[1]_i_2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[2]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[3]_i_1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gen_no_arbiter.m_target_hot_i[3]_i_4\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_axi_awvalid[0]_INST_0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_axi_awvalid[1]_INST_0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_axi_awvalid[2]_INST_0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \m_axi_awvalid[3]_INST_0\ : label is "soft_lutpair15";
begin
ADDRESS_HIT_0 <= \^address_hit_0\;
Q(4 downto 0) <= \^q\(4 downto 0);
aa_sa_awvalid <= \^aa_sa_awvalid\;
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ <= \^gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\;
match <= \^match\;
\mi_awready_mux__3\ <= \^mi_awready_mux__3\;
\s_ready_i0__1\(0) <= \^s_ready_i0__1\(0);
sel_2 <= \^sel_2\;
sel_4 <= \^sel_4\;
ss_aa_awready <= \^ss_aa_awready\;
write_cs01_out <= \^write_cs01_out\;
\gen_axi.s_axi_wready_i_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => mi_awready_4,
I1 => \^q\(4),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => \^write_cs01_out\
);
\gen_master_slots[0].w_issuing_cnt[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(0),
I1 => \^q\(0),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_101_in
);
\gen_master_slots[1].w_issuing_cnt[11]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(1),
I1 => \^q\(1),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_84_in
);
\gen_master_slots[2].w_issuing_cnt[19]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(2),
I1 => \^q\(2),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_66_in
);
\gen_master_slots[3].w_issuing_cnt[27]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => m_axi_awready(3),
I1 => \^q\(3),
I2 => \^aa_sa_awvalid\,
I3 => m_ready_d(1),
O => p_48_in
);
\gen_master_slots[4].w_issuing_cnt[32]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"95552AAA"
)
port map (
I0 => \^write_cs01_out\,
I1 => s_axi_bready(0),
I2 => p_46_out,
I3 => \chosen_reg[4]\(0),
I4 => w_issuing_cnt(3),
O => \gen_master_slots[4].w_issuing_cnt_reg[32]\
);
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0808080"
)
port map (
I0 => \^sel_2\,
I1 => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\,
I2 => \^sel_4\,
I3 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I4 => \gen_no_arbiter.m_target_hot_i[1]_i_2_n_0\,
O => st_aa_awtarget_enc(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A080"
)
port map (
I0 => \^sel_2\,
I1 => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\,
I2 => \^sel_4\,
I3 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\,
O => st_aa_awtarget_enc(1)
);
\gen_no_arbiter.m_mesg_i[11]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^aa_sa_awvalid\,
O => s_ready_i2
);
\gen_no_arbiter.m_mesg_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(0),
Q => \m_axi_awqos[15]\(0),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(10),
Q => \m_axi_awqos[15]\(10),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(11),
Q => \m_axi_awqos[15]\(11),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(12),
Q => \m_axi_awqos[15]\(12),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(13),
Q => \m_axi_awqos[15]\(13),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(14),
Q => \m_axi_awqos[15]\(14),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(15),
Q => \m_axi_awqos[15]\(15),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(16),
Q => \m_axi_awqos[15]\(16),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(17),
Q => \m_axi_awqos[15]\(17),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(18),
Q => \m_axi_awqos[15]\(18),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(19),
Q => \m_axi_awqos[15]\(19),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(1),
Q => \m_axi_awqos[15]\(1),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(20),
Q => \m_axi_awqos[15]\(20),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(21),
Q => \m_axi_awqos[15]\(21),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(22),
Q => \m_axi_awqos[15]\(22),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(23),
Q => \m_axi_awqos[15]\(23),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(24),
Q => \m_axi_awqos[15]\(24),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(25),
Q => \m_axi_awqos[15]\(25),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(26),
Q => \m_axi_awqos[15]\(26),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(27),
Q => \m_axi_awqos[15]\(27),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(28),
Q => \m_axi_awqos[15]\(28),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(29),
Q => \m_axi_awqos[15]\(29),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(2),
Q => \m_axi_awqos[15]\(2),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(30),
Q => \m_axi_awqos[15]\(30),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(31),
Q => \m_axi_awqos[15]\(31),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(32),
Q => \m_axi_awqos[15]\(32),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(33),
Q => \m_axi_awqos[15]\(33),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(34),
Q => \m_axi_awqos[15]\(34),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(35),
Q => \m_axi_awqos[15]\(35),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(36),
Q => \m_axi_awqos[15]\(36),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(37),
Q => \m_axi_awqos[15]\(37),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(38),
Q => \m_axi_awqos[15]\(38),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(39),
Q => \m_axi_awqos[15]\(39),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(3),
Q => \m_axi_awqos[15]\(3),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(40),
Q => \m_axi_awqos[15]\(40),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(41),
Q => \m_axi_awqos[15]\(41),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(42),
Q => \m_axi_awqos[15]\(42),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(43),
Q => \m_axi_awqos[15]\(43),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(44),
Q => \m_axi_awqos[15]\(44),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(45),
Q => \m_axi_awqos[15]\(45),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(46),
Q => \m_axi_awqos[15]\(46),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(47),
Q => \m_axi_awqos[15]\(47),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(48),
Q => \m_axi_awqos[15]\(48),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(49),
Q => \m_axi_awqos[15]\(49),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(4),
Q => \m_axi_awqos[15]\(4),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(50),
Q => \m_axi_awqos[15]\(50),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(51),
Q => \m_axi_awqos[15]\(51),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(52),
Q => \m_axi_awqos[15]\(52),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(53),
Q => \m_axi_awqos[15]\(53),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(54),
Q => \m_axi_awqos[15]\(54),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(55),
Q => \m_axi_awqos[15]\(55),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(56),
Q => \m_axi_awqos[15]\(56),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(57),
Q => \m_axi_awqos[15]\(57),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(58),
Q => \m_axi_awqos[15]\(58),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(5),
Q => \m_axi_awqos[15]\(5),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(59),
Q => \m_axi_awqos[15]\(59),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(60),
Q => \m_axi_awqos[15]\(60),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(61),
Q => \m_axi_awqos[15]\(61),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(62),
Q => \m_axi_awqos[15]\(62),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(63),
Q => \m_axi_awqos[15]\(63),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(64),
Q => \m_axi_awqos[15]\(64),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(6),
Q => \m_axi_awqos[15]\(6),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(65),
Q => \m_axi_awqos[15]\(65),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(66),
Q => \m_axi_awqos[15]\(66),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(67),
Q => \m_axi_awqos[15]\(67),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(68),
Q => \m_axi_awqos[15]\(68),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(7),
Q => \m_axi_awqos[15]\(7),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(8),
Q => \m_axi_awqos[15]\(8),
R => SR(0)
);
\gen_no_arbiter.m_mesg_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => s_ready_i2,
D => D(9),
Q => \m_axi_awqos[15]\(9),
R => SR(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^address_hit_0\,
I1 => \^match\,
O => st_aa_awtarget_hot(0)
);
\gen_no_arbiter.m_target_hot_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => D(29),
I1 => D(28),
I2 => D(31),
I3 => D(30),
I4 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I5 => \^sel_4\,
O => \^address_hit_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^sel_4\,
I1 => \gen_no_arbiter.m_target_hot_i[1]_i_2_n_0\,
I2 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
O => st_aa_awtarget_hot(1)
);
\gen_no_arbiter.m_target_hot_i[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0004"
)
port map (
I0 => D(29),
I1 => D(28),
I2 => D(31),
I3 => D(30),
O => \gen_no_arbiter.m_target_hot_i[1]_i_2_n_0\
);
\gen_no_arbiter.m_target_hot_i[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000001000000000"
)
port map (
I0 => D(34),
I1 => D(35),
I2 => D(33),
I3 => D(32),
I4 => D(37),
I5 => D(36),
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\
);
\gen_no_arbiter.m_target_hot_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^sel_4\,
I1 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\,
I2 => \^sel_2\,
O => st_aa_awtarget_hot(2)
);
\gen_no_arbiter.m_target_hot_i[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000200000000"
)
port map (
I0 => D(35),
I1 => D(34),
I2 => D(32),
I3 => D(33),
I4 => D(36),
I5 => D(37),
O => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\
);
\gen_no_arbiter.m_target_hot_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^sel_4\,
I1 => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\,
I2 => \^sel_2\,
O => st_aa_awtarget_hot(3)
);
\gen_no_arbiter.m_target_hot_i[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => D(40),
I1 => D(41),
I2 => D(38),
I3 => D(39),
I4 => D(43),
I5 => D(42),
O => \^sel_4\
);
\gen_no_arbiter.m_target_hot_i[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => D(34),
I1 => D(35),
I2 => D(32),
I3 => D(33),
I4 => D(37),
I5 => D(36),
O => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\
);
\gen_no_arbiter.m_target_hot_i[3]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => D(29),
I1 => D(28),
I2 => D(31),
I3 => D(30),
O => \^sel_2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FEFE0000F0000000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\,
I1 => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\,
I2 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I3 => \gen_no_arbiter.m_target_hot_i[1]_i_2_n_0\,
I4 => \^sel_4\,
I5 => \^sel_2\,
O => \^match\
);
\gen_no_arbiter.m_target_hot_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_awtarget_hot(0),
Q => \^q\(0),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_awtarget_hot(1),
Q => \^q\(1),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_awtarget_hot(2),
Q => \^q\(2),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => st_aa_awtarget_hot(3),
Q => \^q\(3),
R => '0'
);
\gen_no_arbiter.m_target_hot_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \s_axi_awaddr[18]\(0),
Q => \^q\(4),
R => '0'
);
\gen_no_arbiter.m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFF1F00"
)
port map (
I0 => m_ready_d(1),
I1 => \^mi_awready_mux__3\,
I2 => \^s_ready_i0__1\(0),
I3 => \^aa_sa_awvalid\,
I4 => m_valid_i,
O => \gen_no_arbiter.m_valid_i_i_1__0_n_0\
);
\gen_no_arbiter.m_valid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_no_arbiter.m_valid_i_i_1__0_n_0\,
Q => \^aa_sa_awvalid\,
R => SR(0)
);
\gen_no_arbiter.s_ready_i[0]_i_15\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^ss_aa_awready\,
I1 => s_axi_awvalid(0),
I2 => m_ready_d_0(0),
O => \gen_no_arbiter.s_ready_i_reg[0]_1\
);
\gen_no_arbiter.s_ready_i[0]_i_21\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000002000000000"
)
port map (
I0 => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_addr_decoder.addr_decoder_inst/gen_target[1].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_3\,
I1 => D(29),
I2 => D(28),
I3 => D(31),
I4 => D(30),
I5 => \^sel_4\,
O => ADDRESS_HIT_1
);
\gen_no_arbiter.s_ready_i[0]_i_23\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => D(29),
I1 => D(28),
I2 => D(31),
I3 => D(30),
I4 => \gen_no_arbiter.m_target_hot_i[3]_i_3_n_0\,
I5 => \^sel_4\,
O => ADDRESS_HIT_3
);
\gen_no_arbiter.s_ready_i[0]_i_27\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => w_issuing_cnt(1),
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(2),
O => \gen_no_arbiter.s_ready_i_reg[0]_0\
);
\gen_no_arbiter.s_ready_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => E(0),
Q => \^ss_aa_awready\,
R => '0'
);
\m_axi_awvalid[0]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(0),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(0)
);
\m_axi_awvalid[1]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(1)
);
\m_axi_awvalid[2]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(2),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(2)
);
\m_axi_awvalid[3]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(3),
I1 => \^aa_sa_awvalid\,
I2 => m_ready_d(1),
O => m_axi_awvalid(3)
);
\m_ready_d[0]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(4),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(2),
I4 => \^q\(3),
O => \sa_wm_awready_mux__3\
);
\m_ready_d[1]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFEAEAEA"
)
port map (
I0 => \m_ready_d[1]_i_4_n_0\,
I1 => \^q\(1),
I2 => m_axi_awready(1),
I3 => \^q\(2),
I4 => m_axi_awready(2),
O => \^mi_awready_mux__3\
);
\m_ready_d[1]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => m_ready_d(0),
I1 => \^q\(3),
I2 => \^q\(2),
I3 => \^q\(1),
I4 => \^q\(0),
I5 => \^q\(4),
O => \^s_ready_i0__1\(0)
);
\m_ready_d[1]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF888F888F888"
)
port map (
I0 => \^q\(0),
I1 => m_axi_awready(0),
I2 => \^q\(4),
I3 => mi_awready_4,
I4 => m_axi_awready(3),
I5 => \^q\(3),
O => \m_ready_d[1]_i_4_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp is
port (
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].w_issuing_cnt_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
resp_select : out STD_LOGIC_VECTOR ( 0 to 0 );
s_ready_i_reg : out STD_LOGIC_VECTOR ( 4 downto 0 );
f_mux4_return : out STD_LOGIC_VECTOR ( 13 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
p_84_in : in STD_LOGIC;
p_66_in : in STD_LOGIC;
p_48_in : in STD_LOGIC;
p_101_in : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\ : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\any_pop__1\ : in STD_LOGIC;
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
ADDRESS_HIT_3 : in STD_LOGIC;
match : in STD_LOGIC;
ADDRESS_HIT_1 : in STD_LOGIC;
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[18]\ : in STD_LOGIC;
sel_4 : in STD_LOGIC;
\s_axi_awaddr[25]\ : in STD_LOGIC;
sel_2 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
st_mr_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
st_mr_bmesg : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_68_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp is
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_16_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_17_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_20_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_22_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_24_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_25_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6_n_0\ : STD_LOGIC;
signal last_rr_hot : STD_LOGIC;
signal \last_rr_hot[0]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_2__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_3__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_4__0_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_5__0_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_5_in6_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in9_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal \^resp_select\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \resp_select__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_bvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_ready_i_reg\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \w_cmd_pop_0__0\ : STD_LOGIC;
signal \w_cmd_pop_1__0\ : STD_LOGIC;
signal \w_cmd_pop_2__0\ : STD_LOGIC;
signal \w_cmd_pop_3__0\ : STD_LOGIC;
signal \w_cmd_pop_4__0\ : STD_LOGIC;
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[3]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_3\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_3\ : label is "soft_lutpair153";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_3\ : label is "soft_lutpair152";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_26\ : label is "soft_lutpair157";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_2__0\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_3__0\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \last_rr_hot[1]_i_2__0\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_3__0\ : label is "soft_lutpair155";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_2__0\ : label is "soft_lutpair156";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_3__0\ : label is "soft_lutpair154";
attribute SOFT_HLUTNM of \s_axi_bvalid[0]_INST_0_i_1\ : label is "soft_lutpair153";
begin
SR(0) <= \^sr\(0);
m_valid_i <= \^m_valid_i\;
resp_select(0) <= \^resp_select\(0);
s_axi_bvalid(0) <= \^s_axi_bvalid\(0);
s_ready_i_reg(4 downto 0) <= \^s_ready_i_reg\(4 downto 0);
\chosen[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBB8"
)
port map (
I0 => s_axi_bready(0),
I1 => \^s_axi_bvalid\(0),
I2 => p_46_out,
I3 => p_128_out,
I4 => p_108_out,
I5 => m_valid_i_reg,
O => need_arbitration
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(0),
Q => \^s_ready_i_reg\(0),
R => \^sr\(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(1),
Q => \^s_ready_i_reg\(1),
R => \^sr\(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(2),
Q => \^s_ready_i_reg\(2),
R => \^sr\(0)
);
\chosen_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(3),
Q => \^s_ready_i_reg\(3),
R => \^sr\(0)
);
\chosen_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(4),
Q => \^s_ready_i_reg\(4),
R => \^sr\(0)
);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(36),
I1 => st_mr_bid(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(24),
I5 => st_mr_bid(12),
O => f_mux4_return(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(46),
I1 => st_mr_bid(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(34),
I5 => st_mr_bid(22),
O => f_mux4_return(10)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^s_ready_i_reg\(4),
I1 => p_46_out,
O => \^resp_select\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(47),
I1 => st_mr_bid(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(35),
I5 => st_mr_bid(23),
O => f_mux4_return(11)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_68_out,
I1 => \^s_ready_i_reg\(3),
I2 => p_108_out,
I3 => \^s_ready_i_reg\(1),
O => \resp_select__0\(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bmesg(6),
I1 => st_mr_bmesg(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bmesg(4),
I5 => st_mr_bmesg(2),
O => f_mux4_return(12)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bmesg(7),
I1 => st_mr_bmesg(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bmesg(5),
I5 => st_mr_bmesg(3),
O => f_mux4_return(13)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(37),
I1 => st_mr_bid(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(25),
I5 => st_mr_bid(13),
O => f_mux4_return(1)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(38),
I1 => st_mr_bid(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(26),
I5 => st_mr_bid(14),
O => f_mux4_return(2)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(39),
I1 => st_mr_bid(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(27),
I5 => st_mr_bid(15),
O => f_mux4_return(3)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(40),
I1 => st_mr_bid(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(28),
I5 => st_mr_bid(16),
O => f_mux4_return(4)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(41),
I1 => st_mr_bid(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(29),
I5 => st_mr_bid(17),
O => f_mux4_return(5)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(42),
I1 => st_mr_bid(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(30),
I5 => st_mr_bid(18),
O => f_mux4_return(6)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(43),
I1 => st_mr_bid(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(31),
I5 => st_mr_bid(19),
O => f_mux4_return(7)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(44),
I1 => st_mr_bid(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(32),
I5 => st_mr_bid(20),
O => f_mux4_return(8)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_bid(45),
I1 => st_mr_bid(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_bid(33),
I5 => st_mr_bid(21),
O => f_mux4_return(9)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(1),
I1 => w_issuing_cnt(2),
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(3),
I4 => \w_cmd_pop_0__0\,
I5 => p_101_in,
O => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(0),
I1 => p_128_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_0__0\
);
\gen_master_slots[1].w_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(5),
I1 => w_issuing_cnt(6),
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(7),
I4 => \w_cmd_pop_1__0\,
I5 => p_84_in,
O => E(0)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(1),
I1 => p_108_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_1__0\
);
\gen_master_slots[2].w_issuing_cnt[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(9),
I1 => w_issuing_cnt(10),
I2 => w_issuing_cnt(8),
I3 => w_issuing_cnt(11),
I4 => \w_cmd_pop_2__0\,
I5 => p_66_in,
O => \gen_master_slots[2].w_issuing_cnt_reg[16]\(0)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(2),
I1 => p_88_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_2__0\
);
\gen_master_slots[3].w_issuing_cnt[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => w_issuing_cnt(13),
I1 => w_issuing_cnt(14),
I2 => w_issuing_cnt(12),
I3 => w_issuing_cnt(15),
I4 => \w_cmd_pop_3__0\,
I5 => p_48_in,
O => \gen_master_slots[3].w_issuing_cnt_reg[24]\(0)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(3),
I1 => p_68_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_3__0\
);
\gen_no_arbiter.m_mesg_i[11]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn_d,
O => \^sr\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => \gen_no_arbiter.s_ready_i_reg[0]\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_16\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0808080"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\,
I1 => ADDRESS_HIT_1,
I2 => match,
I3 => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\,
I4 => ADDRESS_HIT_0,
O => \gen_no_arbiter.s_ready_i[0]_i_16_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8FF00F8F8FFFF"
)
port map (
I0 => ADDRESS_HIT_3,
I1 => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\,
I2 => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\,
I3 => \w_cmd_pop_4__0\,
I4 => match,
I5 => w_issuing_cnt(16),
O => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\,
I5 => aa_sa_awvalid,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_20\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_1__0\,
I1 => w_issuing_cnt(4),
I2 => w_issuing_cnt(7),
I3 => w_issuing_cnt(5),
I4 => w_issuing_cnt(6),
O => \gen_no_arbiter.s_ready_i[0]_i_20_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_22\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_0__0\,
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(3),
I3 => w_issuing_cnt(1),
I4 => w_issuing_cnt(2),
O => \gen_no_arbiter.s_ready_i[0]_i_22_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_24\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \w_cmd_pop_3__0\,
I1 => w_issuing_cnt(12),
I2 => w_issuing_cnt(15),
I3 => w_issuing_cnt(13),
I4 => w_issuing_cnt(14),
O => \gen_no_arbiter.s_ready_i[0]_i_24_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_25\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE00000000000000"
)
port map (
I0 => \gen_master_slots[2].w_issuing_cnt_reg[18]\,
I1 => w_issuing_cnt(8),
I2 => \w_cmd_pop_2__0\,
I3 => sel_4,
I4 => \s_axi_awaddr[25]\,
I5 => sel_2,
O => \gen_no_arbiter.s_ready_i[0]_i_25_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_26\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \^s_ready_i_reg\(4),
I1 => p_46_out,
I2 => s_axi_bready(0),
O => \w_cmd_pop_4__0\
);
\gen_no_arbiter.s_ready_i[0]_i_6\: unisim.vcomponents.LUT6
generic map(
INIT => X"FD00FD00FD000000"
)
port map (
I0 => Q(0),
I1 => \any_pop__1\,
I2 => \gen_multi_thread.accept_cnt_reg[0]\,
I3 => \gen_no_arbiter.s_ready_i_reg[0]_0\,
I4 => \gen_no_arbiter.s_ready_i[0]_i_16_n_0\,
I5 => \gen_no_arbiter.s_ready_i[0]_i_17_n_0\,
O => \gen_no_arbiter.s_ready_i[0]_i_6_n_0\
);
\last_rr_hot[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_128_out,
I1 => p_68_out,
I2 => p_46_out,
I3 => \last_rr_hot[0]_i_2__0_n_0\,
I4 => \last_rr_hot[0]_i_3__0_n_0\,
I5 => p_6_in,
O => next_rr_hot(0)
);
\last_rr_hot[0]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_5_in6_in,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_108_out,
I3 => p_88_out,
O => \last_rr_hot[0]_i_2__0_n_0\
);
\last_rr_hot[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_46_out,
I1 => p_7_in9_in,
I2 => p_8_in,
O => \last_rr_hot[0]_i_3__0_n_0\
);
\last_rr_hot[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_108_out,
I1 => p_128_out,
I2 => p_46_out,
I3 => \last_rr_hot[1]_i_2__0_n_0\,
I4 => \last_rr_hot[4]_i_4__0_n_0\,
I5 => p_7_in9_in,
O => next_rr_hot(1)
);
\last_rr_hot[1]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_6_in,
I1 => p_5_in6_in,
I2 => p_88_out,
I3 => p_68_out,
O => \last_rr_hot[1]_i_2__0_n_0\
);
\last_rr_hot[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_88_out,
I1 => m_valid_i_reg_0,
I2 => \last_rr_hot[4]_i_5__0_n_0\,
I3 => p_46_out,
I4 => \last_rr_hot[2]_i_3__0_n_0\,
I5 => p_8_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_108_out,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_5_in6_in,
O => \last_rr_hot[2]_i_3__0_n_0\
);
\last_rr_hot[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_68_out,
I1 => p_108_out,
I2 => p_88_out,
I3 => \last_rr_hot[3]_i_2__0_n_0\,
I4 => \last_rr_hot[3]_i_3__0_n_0\,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(3)
);
\last_rr_hot[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_8_in,
I1 => p_7_in9_in,
I2 => p_46_out,
I3 => p_128_out,
O => \last_rr_hot[3]_i_2__0_n_0\
);
\last_rr_hot[3]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_88_out,
I1 => p_5_in6_in,
I2 => p_6_in,
O => \last_rr_hot[3]_i_3__0_n_0\
);
\last_rr_hot[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(3),
I2 => next_rr_hot(2),
I3 => next_rr_hot(1),
I4 => next_rr_hot(0),
I5 => next_rr_hot(4),
O => last_rr_hot
);
\last_rr_hot[4]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_46_out,
I1 => m_valid_i_reg,
I2 => \last_rr_hot[4]_i_4__0_n_0\,
I3 => p_108_out,
I4 => \last_rr_hot[4]_i_5__0_n_0\,
I5 => p_5_in6_in,
O => next_rr_hot(4)
);
\last_rr_hot[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_128_out,
I1 => p_8_in,
I2 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[4]_i_4__0_n_0\
);
\last_rr_hot[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_68_out,
I1 => p_6_in,
I2 => p_7_in9_in,
O => \last_rr_hot[4]_i_5__0_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(0),
Q => \last_rr_hot_reg_n_0_[0]\,
R => \^sr\(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(1),
Q => p_5_in6_in,
R => \^sr\(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(2),
Q => p_6_in,
R => \^sr\(0)
);
\last_rr_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(3),
Q => p_7_in9_in,
R => \^sr\(0)
);
\last_rr_hot_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(4),
Q => p_8_in,
S => \^sr\(0)
);
\s_axi_bvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFEAEAEA"
)
port map (
I0 => \^resp_select\(0),
I1 => p_128_out,
I2 => \^s_ready_i_reg\(0),
I3 => p_108_out,
I4 => \^s_ready_i_reg\(1),
I5 => \resp_select__0\(1),
O => \^s_axi_bvalid\(0)
);
\s_axi_bvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_68_out,
I1 => \^s_ready_i_reg\(3),
I2 => p_88_out,
I3 => \^s_ready_i_reg\(2),
O => \resp_select__0\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8 is
port (
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
f_mux4_return : out STD_LOGIC_VECTOR ( 46 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
resp_select : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : in STD_LOGIC;
st_mr_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
st_mr_rmesg : in STD_LOGIC_VECTOR ( 135 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_62_out : in STD_LOGIC;
p_102_out : in STD_LOGIC;
p_40_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8 : entity is "axi_crossbar_v2_1_14_arbiter_resp";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8 is
signal \^q\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal last_rr_hot : STD_LOGIC;
signal \last_rr_hot[0]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[0]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[1]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[2]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_2_n_0\ : STD_LOGIC;
signal \last_rr_hot[3]_i_3_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_4_n_0\ : STD_LOGIC;
signal \last_rr_hot[4]_i_5_n_0\ : STD_LOGIC;
signal \last_rr_hot_reg_n_0_[0]\ : STD_LOGIC;
signal need_arbitration : STD_LOGIC;
signal next_rr_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal p_0_in1_in : STD_LOGIC_VECTOR ( 3 downto 1 );
signal p_5_in6_in : STD_LOGIC;
signal p_6_in : STD_LOGIC;
signal p_7_in9_in : STD_LOGIC;
signal p_8_in : STD_LOGIC;
signal \^resp_select\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \resp_select__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_rvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute use_clock_enable : string;
attribute use_clock_enable of \chosen_reg[0]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[1]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[2]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[3]\ : label is "yes";
attribute use_clock_enable of \chosen_reg[4]\ : label is "yes";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_2\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \last_rr_hot[0]_i_3\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \last_rr_hot[1]_i_2\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_3\ : label is "soft_lutpair126";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_2\ : label is "soft_lutpair124";
attribute SOFT_HLUTNM of \last_rr_hot[3]_i_3\ : label is "soft_lutpair125";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_4\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_5\ : label is "soft_lutpair127";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1\ : label is "soft_lutpair128";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__2\ : label is "soft_lutpair130";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__3\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_1\ : label is "soft_lutpair131";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_2\ : label is "soft_lutpair129";
attribute SOFT_HLUTNM of \s_axi_rvalid[0]_INST_0_i_3\ : label is "soft_lutpair127";
begin
Q(4 downto 0) <= \^q\(4 downto 0);
resp_select(0) <= \^resp_select\(0);
s_axi_rvalid(0) <= \^s_axi_rvalid\(0);
\chosen[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBBBBBBBBBBB8"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rvalid\(0),
I2 => p_40_out,
I3 => p_122_out,
I4 => p_102_out,
I5 => m_valid_i_reg,
O => need_arbitration
);
\chosen_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(0),
Q => \^q\(0),
R => SR(0)
);
\chosen_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(1),
Q => \^q\(1),
R => SR(0)
);
\chosen_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(2),
Q => \^q\(2),
R => SR(0)
);
\chosen_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(3),
Q => \^q\(3),
R => SR(0)
);
\chosen_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => need_arbitration,
D => next_rr_hot(4),
Q => \^q\(4),
R => SR(0)
);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(36),
I1 => st_mr_rid(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(24),
I5 => st_mr_rid(12),
O => f_mux4_return(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(46),
I1 => st_mr_rid(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(34),
I5 => st_mr_rid(22),
O => f_mux4_return(10)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(4),
I1 => p_40_out,
O => \^resp_select\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(47),
I1 => st_mr_rid(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(35),
I5 => st_mr_rid(23),
O => f_mux4_return(11)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_62_out,
I1 => \^q\(3),
I2 => p_102_out,
I3 => \^q\(1),
O => \resp_select__0\(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => p_62_out,
I1 => \^q\(3),
I2 => p_82_out,
I3 => \^q\(2),
O => \resp_select__0\(1)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(102),
I1 => st_mr_rmesg(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(68),
I5 => st_mr_rmesg(34),
O => f_mux4_return(12)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(103),
I1 => st_mr_rmesg(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(69),
I5 => st_mr_rmesg(35),
O => f_mux4_return(13)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(104),
I1 => st_mr_rmesg(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(70),
I5 => st_mr_rmesg(36),
O => f_mux4_return(14)
);
\gen_fpga.gen_mux_5_8[16].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(105),
I1 => st_mr_rmesg(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(71),
I5 => st_mr_rmesg(37),
O => f_mux4_return(15)
);
\gen_fpga.gen_mux_5_8[17].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(106),
I1 => st_mr_rmesg(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(72),
I5 => st_mr_rmesg(38),
O => f_mux4_return(16)
);
\gen_fpga.gen_mux_5_8[18].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(107),
I1 => st_mr_rmesg(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(73),
I5 => st_mr_rmesg(39),
O => f_mux4_return(17)
);
\gen_fpga.gen_mux_5_8[19].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(108),
I1 => st_mr_rmesg(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(74),
I5 => st_mr_rmesg(40),
O => f_mux4_return(18)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(37),
I1 => st_mr_rid(1),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(25),
I5 => st_mr_rid(13),
O => f_mux4_return(1)
);
\gen_fpga.gen_mux_5_8[20].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(109),
I1 => st_mr_rmesg(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(75),
I5 => st_mr_rmesg(41),
O => f_mux4_return(19)
);
\gen_fpga.gen_mux_5_8[21].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(110),
I1 => st_mr_rmesg(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(76),
I5 => st_mr_rmesg(42),
O => f_mux4_return(20)
);
\gen_fpga.gen_mux_5_8[22].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(111),
I1 => st_mr_rmesg(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(77),
I5 => st_mr_rmesg(43),
O => f_mux4_return(21)
);
\gen_fpga.gen_mux_5_8[23].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(112),
I1 => st_mr_rmesg(10),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(78),
I5 => st_mr_rmesg(44),
O => f_mux4_return(22)
);
\gen_fpga.gen_mux_5_8[24].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(113),
I1 => st_mr_rmesg(11),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(79),
I5 => st_mr_rmesg(45),
O => f_mux4_return(23)
);
\gen_fpga.gen_mux_5_8[25].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(114),
I1 => st_mr_rmesg(12),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(80),
I5 => st_mr_rmesg(46),
O => f_mux4_return(24)
);
\gen_fpga.gen_mux_5_8[26].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(115),
I1 => st_mr_rmesg(13),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(81),
I5 => st_mr_rmesg(47),
O => f_mux4_return(25)
);
\gen_fpga.gen_mux_5_8[27].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(116),
I1 => st_mr_rmesg(14),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(82),
I5 => st_mr_rmesg(48),
O => f_mux4_return(26)
);
\gen_fpga.gen_mux_5_8[28].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(117),
I1 => st_mr_rmesg(15),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(83),
I5 => st_mr_rmesg(49),
O => f_mux4_return(27)
);
\gen_fpga.gen_mux_5_8[29].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(118),
I1 => st_mr_rmesg(16),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(84),
I5 => st_mr_rmesg(50),
O => f_mux4_return(28)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(38),
I1 => st_mr_rid(2),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(26),
I5 => st_mr_rid(14),
O => f_mux4_return(2)
);
\gen_fpga.gen_mux_5_8[30].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(119),
I1 => st_mr_rmesg(17),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(85),
I5 => st_mr_rmesg(51),
O => f_mux4_return(29)
);
\gen_fpga.gen_mux_5_8[31].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(120),
I1 => st_mr_rmesg(18),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(86),
I5 => st_mr_rmesg(52),
O => f_mux4_return(30)
);
\gen_fpga.gen_mux_5_8[32].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(121),
I1 => st_mr_rmesg(19),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(87),
I5 => st_mr_rmesg(53),
O => f_mux4_return(31)
);
\gen_fpga.gen_mux_5_8[33].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(122),
I1 => st_mr_rmesg(20),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(88),
I5 => st_mr_rmesg(54),
O => f_mux4_return(32)
);
\gen_fpga.gen_mux_5_8[34].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(123),
I1 => st_mr_rmesg(21),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(89),
I5 => st_mr_rmesg(55),
O => f_mux4_return(33)
);
\gen_fpga.gen_mux_5_8[35].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(124),
I1 => st_mr_rmesg(22),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(90),
I5 => st_mr_rmesg(56),
O => f_mux4_return(34)
);
\gen_fpga.gen_mux_5_8[36].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(125),
I1 => st_mr_rmesg(23),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(91),
I5 => st_mr_rmesg(57),
O => f_mux4_return(35)
);
\gen_fpga.gen_mux_5_8[37].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(126),
I1 => st_mr_rmesg(24),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(92),
I5 => st_mr_rmesg(58),
O => f_mux4_return(36)
);
\gen_fpga.gen_mux_5_8[38].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(127),
I1 => st_mr_rmesg(25),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(93),
I5 => st_mr_rmesg(59),
O => f_mux4_return(37)
);
\gen_fpga.gen_mux_5_8[39].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(128),
I1 => st_mr_rmesg(26),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(94),
I5 => st_mr_rmesg(60),
O => f_mux4_return(38)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(39),
I1 => st_mr_rid(3),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(27),
I5 => st_mr_rid(15),
O => f_mux4_return(3)
);
\gen_fpga.gen_mux_5_8[40].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(129),
I1 => st_mr_rmesg(27),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(95),
I5 => st_mr_rmesg(61),
O => f_mux4_return(39)
);
\gen_fpga.gen_mux_5_8[41].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(130),
I1 => st_mr_rmesg(28),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(96),
I5 => st_mr_rmesg(62),
O => f_mux4_return(40)
);
\gen_fpga.gen_mux_5_8[42].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(131),
I1 => st_mr_rmesg(29),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(97),
I5 => st_mr_rmesg(63),
O => f_mux4_return(41)
);
\gen_fpga.gen_mux_5_8[43].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(132),
I1 => st_mr_rmesg(30),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(98),
I5 => st_mr_rmesg(64),
O => f_mux4_return(42)
);
\gen_fpga.gen_mux_5_8[44].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(133),
I1 => st_mr_rmesg(31),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(99),
I5 => st_mr_rmesg(65),
O => f_mux4_return(43)
);
\gen_fpga.gen_mux_5_8[45].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(134),
I1 => st_mr_rmesg(32),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(100),
I5 => st_mr_rmesg(66),
O => f_mux4_return(44)
);
\gen_fpga.gen_mux_5_8[46].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rmesg(135),
I1 => st_mr_rmesg(33),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rmesg(101),
I5 => st_mr_rmesg(67),
O => f_mux4_return(45)
);
\gen_fpga.gen_mux_5_8[47].mux_s2_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => \m_payload_i_reg[34]_0\(0),
I1 => \m_payload_i_reg[34]_1\(0),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => \m_payload_i_reg[34]_2\(0),
I5 => \m_payload_i_reg[34]_3\(0),
O => f_mux4_return(46)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(40),
I1 => st_mr_rid(4),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(28),
I5 => st_mr_rid(16),
O => f_mux4_return(4)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(41),
I1 => st_mr_rid(5),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(29),
I5 => st_mr_rid(17),
O => f_mux4_return(5)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(42),
I1 => st_mr_rid(6),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(30),
I5 => st_mr_rid(18),
O => f_mux4_return(6)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(43),
I1 => st_mr_rid(7),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(31),
I5 => st_mr_rid(19),
O => f_mux4_return(7)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(44),
I1 => st_mr_rid(8),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(32),
I5 => st_mr_rid(20),
O => f_mux4_return(8)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFFCA0FCAF0CA00C"
)
port map (
I0 => st_mr_rid(45),
I1 => st_mr_rid(9),
I2 => \resp_select__0\(0),
I3 => \resp_select__0\(1),
I4 => st_mr_rid(33),
I5 => st_mr_rid(21),
O => f_mux4_return(9)
);
\last_rr_hot[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_122_out,
I1 => p_62_out,
I2 => p_40_out,
I3 => \last_rr_hot[0]_i_2_n_0\,
I4 => \last_rr_hot[0]_i_3_n_0\,
I5 => p_6_in,
O => next_rr_hot(0)
);
\last_rr_hot[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_5_in6_in,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_102_out,
I3 => p_82_out,
O => \last_rr_hot[0]_i_2_n_0\
);
\last_rr_hot[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_40_out,
I1 => p_7_in9_in,
I2 => p_8_in,
O => \last_rr_hot[0]_i_3_n_0\
);
\last_rr_hot[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_102_out,
I1 => p_40_out,
I2 => p_122_out,
I3 => \last_rr_hot[1]_i_2_n_0\,
I4 => \last_rr_hot[4]_i_4_n_0\,
I5 => p_7_in9_in,
O => next_rr_hot(1)
);
\last_rr_hot[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_6_in,
I1 => p_5_in6_in,
I2 => p_82_out,
I3 => p_62_out,
O => \last_rr_hot[1]_i_2_n_0\
);
\last_rr_hot[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_82_out,
I1 => m_valid_i_reg_0,
I2 => \last_rr_hot[4]_i_5_n_0\,
I3 => p_40_out,
I4 => \last_rr_hot[2]_i_3_n_0\,
I5 => p_8_in,
O => next_rr_hot(2)
);
\last_rr_hot[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_102_out,
I1 => \last_rr_hot_reg_n_0_[0]\,
I2 => p_5_in6_in,
O => \last_rr_hot[2]_i_3_n_0\
);
\last_rr_hot[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA0202AAAA0200"
)
port map (
I0 => p_62_out,
I1 => p_102_out,
I2 => p_82_out,
I3 => \last_rr_hot[3]_i_2_n_0\,
I4 => \last_rr_hot[3]_i_3_n_0\,
I5 => \last_rr_hot_reg_n_0_[0]\,
O => next_rr_hot(3)
);
\last_rr_hot[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00AE"
)
port map (
I0 => p_8_in,
I1 => p_7_in9_in,
I2 => p_40_out,
I3 => p_122_out,
O => \last_rr_hot[3]_i_2_n_0\
);
\last_rr_hot[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_82_out,
I1 => p_5_in6_in,
I2 => p_6_in,
O => \last_rr_hot[3]_i_3_n_0\
);
\last_rr_hot[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => need_arbitration,
I1 => next_rr_hot(3),
I2 => next_rr_hot(2),
I3 => next_rr_hot(1),
I4 => next_rr_hot(0),
I5 => next_rr_hot(4),
O => last_rr_hot
);
\last_rr_hot[4]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA2222AAAA0020"
)
port map (
I0 => p_40_out,
I1 => m_valid_i_reg,
I2 => \last_rr_hot[4]_i_4_n_0\,
I3 => p_102_out,
I4 => \last_rr_hot[4]_i_5_n_0\,
I5 => p_5_in6_in,
O => next_rr_hot(4)
);
\last_rr_hot[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_122_out,
I1 => p_8_in,
I2 => \last_rr_hot_reg_n_0_[0]\,
O => \last_rr_hot[4]_i_4_n_0\
);
\last_rr_hot[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"F4"
)
port map (
I0 => p_62_out,
I1 => p_6_in,
I2 => p_7_in9_in,
O => \last_rr_hot[4]_i_5_n_0\
);
\last_rr_hot_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(0),
Q => \last_rr_hot_reg_n_0_[0]\,
R => SR(0)
);
\last_rr_hot_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(1),
Q => p_5_in6_in,
R => SR(0)
);
\last_rr_hot_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(2),
Q => p_6_in,
R => SR(0)
);
\last_rr_hot_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(3),
Q => p_7_in9_in,
R => SR(0)
);
\last_rr_hot_reg[4]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => last_rr_hot,
D => next_rr_hot(4),
Q => p_8_in,
S => SR(0)
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(0),
I1 => s_axi_rready(0),
I2 => p_122_out,
O => \m_payload_i_reg[0]\(0)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(1),
I1 => s_axi_rready(0),
I2 => p_102_out,
O => \m_payload_i_reg[0]_0\(0)
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(4),
I1 => s_axi_rready(0),
I2 => p_40_out,
O => \m_payload_i_reg[34]\(0)
);
\m_payload_i[46]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(3),
I1 => s_axi_rready(0),
I2 => p_62_out,
O => \m_payload_i_reg[0]_1\(0)
);
\m_payload_i[46]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"8F"
)
port map (
I0 => \^q\(2),
I1 => s_axi_rready(0),
I2 => p_82_out,
O => \m_payload_i_reg[0]_2\(0)
);
\s_axi_rvalid[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFF8"
)
port map (
I0 => \^q\(0),
I1 => p_122_out,
I2 => p_0_in1_in(2),
I3 => p_0_in1_in(1),
I4 => p_0_in1_in(3),
I5 => \^resp_select\(0),
O => \^s_axi_rvalid\(0)
);
\s_axi_rvalid[0]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(2),
I1 => p_82_out,
O => p_0_in1_in(2)
);
\s_axi_rvalid[0]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(1),
I1 => p_102_out,
O => p_0_in1_in(1)
);
\s_axi_rvalid[0]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^q\(3),
I1 => p_62_out,
O => p_0_in1_in(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave is
port (
mi_awready_4 : out STD_LOGIC;
p_22_in : out STD_LOGIC;
p_29_in : out STD_LOGIC;
p_23_in : out STD_LOGIC;
p_25_in : out STD_LOGIC;
\read_cs__0\ : out STD_LOGIC;
mi_arready_4 : out STD_LOGIC;
\m_payload_i_reg[13]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
aa_sa_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
mi_rready_4 : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\gen_no_arbiter.m_target_hot_i_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[51]\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
mi_bready_4 : in STD_LOGIC;
\write_cs0__0\ : in STD_LOGIC;
write_cs01_out : in STD_LOGIC;
s_axi_rlast_i0 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.m_mesg_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aresetn_d : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave is
signal \gen_axi.read_cnt[4]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.read_cnt_reg\ : STD_LOGIC_VECTOR ( 7 downto 1 );
signal \gen_axi.read_cnt_reg__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gen_axi.read_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_arready_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_awready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bid_i[11]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_bvalid_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_3_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_rlast_i_i_4_n_0\ : STD_LOGIC;
signal \gen_axi.s_axi_wready_i_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_axi.write_cs[1]_i_1_n_0\ : STD_LOGIC;
signal \^mi_arready_4\ : STD_LOGIC;
signal \^mi_awready_4\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^p_22_in\ : STD_LOGIC;
signal \^p_23_in\ : STD_LOGIC;
signal \^p_25_in\ : STD_LOGIC;
signal \^p_29_in\ : STD_LOGIC;
signal \^read_cs__0\ : STD_LOGIC;
signal write_cs : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.read_cnt[0]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[1]_i_1\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[2]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[4]_i_2\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_1\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gen_axi.read_cnt[5]_i_2\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \gen_axi.s_axi_arready_i_i_3\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gen_axi.s_axi_rlast_i_i_3\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \gen_axi.write_cs[0]_i_1\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \gen_axi.write_cs[1]_i_1\ : label is "soft_lutpair20";
begin
mi_arready_4 <= \^mi_arready_4\;
mi_awready_4 <= \^mi_awready_4\;
p_22_in <= \^p_22_in\;
p_23_in <= \^p_23_in\;
p_25_in <= \^p_25_in\;
p_29_in <= \^p_29_in\;
\read_cs__0\ <= \^read_cs__0\;
\gen_axi.read_cnt[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"74"
)
port map (
I0 => \gen_axi.read_cnt_reg__0\(0),
I1 => \^p_23_in\,
I2 => \gen_no_arbiter.m_mesg_i_reg[51]\(12),
O => p_0_in(0)
);
\gen_axi.read_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E22E"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(13),
I1 => \^p_23_in\,
I2 => \gen_axi.read_cnt_reg__0\(0),
I3 => \gen_axi.read_cnt_reg\(1),
O => p_0_in(1)
);
\gen_axi.read_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(14),
I1 => \gen_axi.read_cnt_reg\(1),
I2 => \gen_axi.read_cnt_reg__0\(0),
I3 => \^p_23_in\,
I4 => \gen_axi.read_cnt_reg\(2),
O => p_0_in(2)
);
\gen_axi.read_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCAAAA0003AAAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(15),
I1 => \gen_axi.read_cnt_reg__0\(0),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg\(2),
I4 => \^p_23_in\,
I5 => \gen_axi.read_cnt_reg\(3),
O => p_0_in(3)
);
\gen_axi.read_cnt[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFCAAAA0003AAAA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(16),
I1 => \gen_axi.read_cnt_reg\(2),
I2 => \gen_axi.read_cnt[4]_i_2_n_0\,
I3 => \gen_axi.read_cnt_reg\(3),
I4 => \^p_23_in\,
I5 => \gen_axi.read_cnt_reg\(4),
O => p_0_in(4)
);
\gen_axi.read_cnt[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \gen_axi.read_cnt_reg\(1),
I1 => \gen_axi.read_cnt_reg__0\(0),
O => \gen_axi.read_cnt[4]_i_2_n_0\
);
\gen_axi.read_cnt[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CA3A"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(17),
I1 => \gen_axi.read_cnt[5]_i_2_n_0\,
I2 => \^p_23_in\,
I3 => \gen_axi.read_cnt_reg\(5),
O => p_0_in(5)
);
\gen_axi.read_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg\(3),
I1 => \gen_axi.read_cnt_reg__0\(0),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg\(2),
I4 => \gen_axi.read_cnt_reg\(4),
O => \gen_axi.read_cnt[5]_i_2_n_0\
);
\gen_axi.read_cnt[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CA3A"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(18),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \^p_23_in\,
I3 => \gen_axi.read_cnt_reg\(6),
O => p_0_in(6)
);
\gen_axi.read_cnt[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4F40404040404040"
)
port map (
I0 => \^read_cs__0\,
I1 => mi_rready_4,
I2 => \^p_23_in\,
I3 => \^mi_arready_4\,
I4 => aa_mi_arvalid,
I5 => \gen_no_arbiter.m_target_hot_i_reg[4]\(0),
O => \gen_axi.read_cnt[7]_i_1_n_0\
);
\gen_axi.read_cnt[7]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FCAA03AA"
)
port map (
I0 => \gen_no_arbiter.m_mesg_i_reg[51]\(19),
I1 => \gen_axi.read_cnt[7]_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg\(6),
I3 => \^p_23_in\,
I4 => \gen_axi.read_cnt_reg\(7),
O => p_0_in(7)
);
\gen_axi.read_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(2),
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.read_cnt_reg__0\(0),
I4 => \gen_axi.read_cnt_reg\(3),
I5 => \gen_axi.read_cnt_reg\(5),
O => \gen_axi.read_cnt[7]_i_3_n_0\
);
\gen_axi.read_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(0),
Q => \gen_axi.read_cnt_reg__0\(0),
R => SR(0)
);
\gen_axi.read_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(1),
Q => \gen_axi.read_cnt_reg\(1),
R => SR(0)
);
\gen_axi.read_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(2),
Q => \gen_axi.read_cnt_reg\(2),
R => SR(0)
);
\gen_axi.read_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(3),
Q => \gen_axi.read_cnt_reg\(3),
R => SR(0)
);
\gen_axi.read_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(4),
Q => \gen_axi.read_cnt_reg\(4),
R => SR(0)
);
\gen_axi.read_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(5),
Q => \gen_axi.read_cnt_reg\(5),
R => SR(0)
);
\gen_axi.read_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(6),
Q => \gen_axi.read_cnt_reg\(6),
R => SR(0)
);
\gen_axi.read_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.read_cnt[7]_i_1_n_0\,
D => p_0_in(7),
Q => \gen_axi.read_cnt_reg\(7),
R => SR(0)
);
\gen_axi.read_cs[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"7F70707070707070"
)
port map (
I0 => \^read_cs__0\,
I1 => mi_rready_4,
I2 => \^p_23_in\,
I3 => \^mi_arready_4\,
I4 => aa_mi_arvalid,
I5 => \gen_no_arbiter.m_target_hot_i_reg[4]\(0),
O => \gen_axi.read_cs[0]_i_1_n_0\
);
\gen_axi.read_cs_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.read_cs[0]_i_1_n_0\,
Q => \^p_23_in\,
R => SR(0)
);
\gen_axi.s_axi_arready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000FBBB0000"
)
port map (
I0 => \^mi_arready_4\,
I1 => \^p_23_in\,
I2 => \^read_cs__0\,
I3 => mi_rready_4,
I4 => aresetn_d,
I5 => E(0),
O => \gen_axi.s_axi_arready_i_i_1_n_0\
);
\gen_axi.s_axi_arready_i_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_axi.read_cnt[4]_i_2_n_0\,
I1 => \gen_axi.read_cnt_reg\(6),
I2 => \gen_axi.read_cnt_reg\(7),
I3 => \gen_axi.s_axi_arready_i_i_3_n_0\,
I4 => \gen_axi.read_cnt_reg\(2),
I5 => \gen_axi.read_cnt_reg\(3),
O => \^read_cs__0\
);
\gen_axi.s_axi_arready_i_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(5),
O => \gen_axi.s_axi_arready_i_i_3_n_0\
);
\gen_axi.s_axi_arready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_arready_i_i_1_n_0\,
Q => \^mi_arready_4\,
R => '0'
);
\gen_axi.s_axi_awready_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFBB0000F0FF"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => Q(0),
I2 => mi_bready_4,
I3 => write_cs(1),
I4 => write_cs(0),
I5 => \^mi_awready_4\,
O => \gen_axi.s_axi_awready_i_i_1_n_0\
);
\gen_axi.s_axi_awready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_awready_i_i_1_n_0\,
Q => \^mi_awready_4\,
R => SR(0)
);
\gen_axi.s_axi_bid_i[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0100000000000000"
)
port map (
I0 => write_cs(1),
I1 => write_cs(0),
I2 => m_ready_d(0),
I3 => aa_sa_awvalid,
I4 => Q(0),
I5 => \^mi_awready_4\,
O => \gen_axi.s_axi_bid_i[11]_i_1_n_0\
);
\gen_axi.s_axi_bid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(0),
Q => \m_payload_i_reg[13]\(0),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(10),
Q => \m_payload_i_reg[13]\(10),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(11),
Q => \m_payload_i_reg[13]\(11),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(1),
Q => \m_payload_i_reg[13]\(1),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(2),
Q => \m_payload_i_reg[13]\(2),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(3),
Q => \m_payload_i_reg[13]\(3),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(4),
Q => \m_payload_i_reg[13]\(4),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(5),
Q => \m_payload_i_reg[13]\(5),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(6),
Q => \m_payload_i_reg[13]\(6),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(7),
Q => \m_payload_i_reg[13]\(7),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(8),
Q => \m_payload_i_reg[13]\(8),
R => SR(0)
);
\gen_axi.s_axi_bid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
D => \gen_no_arbiter.m_mesg_i_reg[11]\(9),
Q => \m_payload_i_reg[13]\(9),
R => SR(0)
);
\gen_axi.s_axi_bvalid_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFF00C0"
)
port map (
I0 => mi_bready_4,
I1 => write_cs(0),
I2 => \write_cs0__0\,
I3 => write_cs(1),
I4 => \^p_29_in\,
O => \gen_axi.s_axi_bvalid_i_i_1_n_0\
);
\gen_axi.s_axi_bvalid_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_bvalid_i_i_1_n_0\,
Q => \^p_29_in\,
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(0),
Q => \skid_buffer_reg[46]\(0),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(10),
Q => \skid_buffer_reg[46]\(10),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(11),
Q => \skid_buffer_reg[46]\(11),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(1),
Q => \skid_buffer_reg[46]\(1),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(2),
Q => \skid_buffer_reg[46]\(2),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(3),
Q => \skid_buffer_reg[46]\(3),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(4),
Q => \skid_buffer_reg[46]\(4),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(5),
Q => \skid_buffer_reg[46]\(5),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(6),
Q => \skid_buffer_reg[46]\(6),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(7),
Q => \skid_buffer_reg[46]\(7),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(8),
Q => \skid_buffer_reg[46]\(8),
R => SR(0)
);
\gen_axi.s_axi_rid_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \gen_no_arbiter.m_mesg_i_reg[51]\(9),
Q => \skid_buffer_reg[46]\(9),
R => SR(0)
);
\gen_axi.s_axi_rlast_i_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFBFFAAAA0800"
)
port map (
I0 => s_axi_rlast_i0,
I1 => \gen_axi.s_axi_rlast_i_i_3_n_0\,
I2 => \gen_axi.read_cnt_reg\(1),
I3 => \gen_axi.s_axi_rlast_i_i_4_n_0\,
I4 => E(0),
I5 => \^p_25_in\,
O => \gen_axi.s_axi_rlast_i_i_1_n_0\
);
\gen_axi.s_axi_rlast_i_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \gen_axi.read_cnt_reg\(2),
I1 => \gen_axi.read_cnt_reg\(3),
O => \gen_axi.s_axi_rlast_i_i_3_n_0\
);
\gen_axi.s_axi_rlast_i_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => \gen_axi.read_cnt_reg\(4),
I1 => \gen_axi.read_cnt_reg\(5),
I2 => \gen_axi.read_cnt_reg\(6),
I3 => \gen_axi.read_cnt_reg\(7),
I4 => mi_rready_4,
I5 => \^p_23_in\,
O => \gen_axi.s_axi_rlast_i_i_4_n_0\
);
\gen_axi.s_axi_rlast_i_reg\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_rlast_i_i_1_n_0\,
Q => \^p_25_in\,
R => SR(0)
);
\gen_axi.s_axi_wready_i_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF5F000C"
)
port map (
I0 => \write_cs0__0\,
I1 => write_cs01_out,
I2 => write_cs(0),
I3 => write_cs(1),
I4 => \^p_22_in\,
O => \gen_axi.s_axi_wready_i_i_1_n_0\
);
\gen_axi.s_axi_wready_i_reg\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \gen_axi.s_axi_wready_i_i_1_n_0\,
Q => \^p_22_in\,
R => SR(0)
);
\gen_axi.write_cs[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4522"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => write_cs(1),
I2 => \write_cs0__0\,
I3 => write_cs(0),
O => \gen_axi.write_cs[0]_i_1_n_0\
);
\gen_axi.write_cs[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FE00FE44"
)
port map (
I0 => \gen_axi.s_axi_bid_i[11]_i_1_n_0\,
I1 => write_cs(1),
I2 => \write_cs0__0\,
I3 => write_cs(0),
I4 => mi_bready_4,
O => \gen_axi.write_cs[1]_i_1_n_0\
);
\gen_axi.write_cs_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[0]_i_1_n_0\,
Q => write_cs(0),
R => SR(0)
);
\gen_axi.write_cs_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_axi.write_cs[1]_i_1_n_0\,
Q => write_cs(1),
R => SR(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter is
port (
\s_axi_awready[0]\ : out STD_LOGIC;
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
ss_wr_awvalid : out STD_LOGIC;
ss_wr_awready : in STD_LOGIC;
ss_aa_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter is
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_valid_i_i_2__0\ : label is "soft_lutpair178";
attribute SOFT_HLUTNM of \s_axi_awready[0]_INST_0\ : label is "soft_lutpair178";
begin
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready,
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000C8C0"
)
port map (
I0 => s_axi_awvalid(0),
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => ss_wr_awready,
I4 => \^m_ready_d\(0),
I5 => ss_aa_awready,
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
\m_valid_i_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid(0),
I1 => \^m_ready_d\(1),
O => ss_wr_awvalid
);
\s_axi_awready[0]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEE0"
)
port map (
I0 => \^m_ready_d\(1),
I1 => ss_wr_awready,
I2 => \^m_ready_d\(0),
I3 => ss_aa_awready,
O => \s_axi_awready[0]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5 is
port (
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_axi.s_axi_awready_i_reg\ : out STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[19]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[3].w_issuing_cnt_reg[27]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gen_master_slots[0].w_issuing_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_ready_d : out STD_LOGIC_VECTOR ( 1 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 15 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_108_out : in STD_LOGIC;
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_88_out : in STD_LOGIC;
p_68_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
\mi_awready_mux__3\ : in STD_LOGIC;
\s_ready_i0__1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\sa_wm_awready_mux__3\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5 : entity is "axi_crossbar_v2_1_14_splitter";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5 is
signal \^gen_axi.s_axi_awready_i_reg\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\ : STD_LOGIC;
signal \^m_ready_d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \m_ready_d[0]_i_1_n_0\ : STD_LOGIC;
signal \m_ready_d[1]_i_1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_axi.s_axi_awready_i_i_2\ : label is "soft_lutpair182";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[2]_i_1\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \gen_master_slots[0].w_issuing_cnt[3]_i_2\ : label is "soft_lutpair185";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[10]_i_1\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \gen_master_slots[1].w_issuing_cnt[11]_i_2\ : label is "soft_lutpair181";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[18]_i_1\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \gen_master_slots[2].w_issuing_cnt[19]_i_2\ : label is "soft_lutpair183";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[26]_i_1\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \gen_master_slots[3].w_issuing_cnt[27]_i_2\ : label is "soft_lutpair184";
attribute SOFT_HLUTNM of \m_ready_d[1]_i_1\ : label is "soft_lutpair182";
begin
\gen_axi.s_axi_awready_i_reg\ <= \^gen_axi.s_axi_awready_i_reg\;
m_ready_d(1 downto 0) <= \^m_ready_d\(1 downto 0);
\gen_axi.s_axi_awready_i_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_ready_d\(1),
I1 => aa_sa_awvalid,
O => \^gen_axi.s_axi_awready_i_reg\
);
\gen_master_slots[0].w_issuing_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(0),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(1),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(0)
);
\gen_master_slots[0].w_issuing_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I1 => w_issuing_cnt(0),
I2 => w_issuing_cnt(1),
I3 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(1)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(1),
I1 => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\,
I2 => w_issuing_cnt(0),
I3 => w_issuing_cnt(3),
I4 => w_issuing_cnt(2),
O => \gen_master_slots[0].w_issuing_cnt_reg[3]\(2)
);
\gen_master_slots[0].w_issuing_cnt[3]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(0),
I2 => m_axi_awready(0),
I3 => s_axi_bready(0),
I4 => p_128_out,
I5 => \chosen_reg[3]\(0),
O => \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I1 => w_issuing_cnt(4),
I2 => w_issuing_cnt(5),
I3 => w_issuing_cnt(6),
O => D(1)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(5),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(4),
I3 => w_issuing_cnt(7),
I4 => w_issuing_cnt(6),
O => D(2)
);
\gen_master_slots[1].w_issuing_cnt[11]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(1),
I2 => m_axi_awready(1),
I3 => s_axi_bready(0),
I4 => p_108_out,
I5 => \chosen_reg[3]\(1),
O => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\
);
\gen_master_slots[1].w_issuing_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(4),
I1 => \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0\,
I2 => w_issuing_cnt(5),
O => D(0)
);
\gen_master_slots[2].w_issuing_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(8),
I1 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I2 => w_issuing_cnt(9),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(0)
);
\gen_master_slots[2].w_issuing_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I1 => w_issuing_cnt(8),
I2 => w_issuing_cnt(9),
I3 => w_issuing_cnt(10),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(1)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(9),
I1 => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\,
I2 => w_issuing_cnt(8),
I3 => w_issuing_cnt(11),
I4 => w_issuing_cnt(10),
O => \gen_master_slots[2].w_issuing_cnt_reg[19]\(2)
);
\gen_master_slots[2].w_issuing_cnt[19]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(2),
I2 => m_axi_awready(2),
I3 => s_axi_bready(0),
I4 => p_88_out,
I5 => \chosen_reg[3]\(2),
O => \gen_master_slots[2].w_issuing_cnt[19]_i_5_n_0\
);
\gen_master_slots[3].w_issuing_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => w_issuing_cnt(12),
I1 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I2 => w_issuing_cnt(13),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(0)
);
\gen_master_slots[3].w_issuing_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7E81"
)
port map (
I0 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I1 => w_issuing_cnt(12),
I2 => w_issuing_cnt(13),
I3 => w_issuing_cnt(14),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(1)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => w_issuing_cnt(13),
I1 => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\,
I2 => w_issuing_cnt(12),
I3 => w_issuing_cnt(15),
I4 => w_issuing_cnt(14),
O => \gen_master_slots[3].w_issuing_cnt_reg[27]\(2)
);
\gen_master_slots[3].w_issuing_cnt[27]_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"0040404040404040"
)
port map (
I0 => \^gen_axi.s_axi_awready_i_reg\,
I1 => Q(3),
I2 => m_axi_awready(3),
I3 => s_axi_bready(0),
I4 => p_68_out,
I5 => \chosen_reg[3]\(3),
O => \gen_master_slots[3].w_issuing_cnt[27]_i_5_n_0\
);
\m_ready_d[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000C0008000C0000"
)
port map (
I0 => aa_sa_awvalid,
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => \mi_awready_mux__3\,
I4 => \^m_ready_d\(0),
I5 => \sa_wm_awready_mux__3\,
O => \m_ready_d[0]_i_1_n_0\
);
\m_ready_d[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0000C8C0"
)
port map (
I0 => aa_sa_awvalid,
I1 => aresetn_d,
I2 => \^m_ready_d\(1),
I3 => \mi_awready_mux__3\,
I4 => \s_ready_i0__1\(0),
O => \m_ready_d[1]_i_1_n_0\
);
\m_ready_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[0]_i_1_n_0\,
Q => \^m_ready_d\(0),
R => '0'
);
\m_ready_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_ready_d[1]_i_1_n_0\,
Q => \^m_ready_d\(1),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
port (
\storage_data1_reg[0]\ : out STD_LOGIC;
push : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\ is
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => st_aa_awtarget_enc(0),
Q => \storage_data1_reg[0]\,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ is
port (
p_2_out : out STD_LOGIC;
push : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\ is
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => push,
CLK => aclk,
D => st_aa_awtarget_enc(0),
Q => p_2_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ is
port (
push : out STD_LOGIC;
\storage_data1_reg[2]\ : out STD_LOGIC;
\m_aready__1\ : out STD_LOGIC;
\m_aready0__3\ : out STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
fifoaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
aclk : in STD_LOGIC;
match : in STD_LOGIC;
out0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
load_s1 : in STD_LOGIC;
m_select_enc : in STD_LOGIC_VECTOR ( 2 downto 0 );
ss_wr_awready : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_avalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ : entity is "axi_data_fifo_v2_1_12_ndeep_srl";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\ is
signal \^m_aready0__3\ : STD_LOGIC;
signal \^m_aready__1\ : STD_LOGIC;
signal p_3_out : STD_LOGIC;
signal \^push\ : STD_LOGIC;
signal \s_axi_wready[0]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "PRIMITIVE";
attribute srl_bus_name : string;
attribute srl_bus_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls ";
attribute srl_name : string;
attribute srl_name of \gen_primitive_shifter.gen_srls[0].srl_inst\ : label is "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[2].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst ";
begin
\m_aready0__3\ <= \^m_aready0__3\;
\m_aready__1\ <= \^m_aready__1\;
push <= \^push\;
\gen_primitive_shifter.gen_srls[0].srl_inst\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000",
IS_CLK_INVERTED => '0'
)
port map (
A(4 downto 3) => B"00",
A(2 downto 0) => fifoaddr(2 downto 0),
CE => \^push\,
CLK => aclk,
D => D(0),
Q => p_3_out,
Q31 => \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED\
);
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0088000000F80000"
)
port map (
I0 => ss_wr_awready,
I1 => out0(0),
I2 => out0(1),
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => \^m_aready__1\,
O => \^push\
);
\m_valid_i_i_1__8\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => s_axi_wlast(0),
I1 => m_avalid,
I2 => s_axi_wvalid(0),
I3 => \^m_aready0__3\,
O => \^m_aready__1\
);
\s_axi_wready[0]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAFEAAAAAAAEA"
)
port map (
I0 => \s_axi_wready[0]_INST_0_i_2_n_0\,
I1 => m_axi_wready(1),
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
I5 => m_axi_wready(2),
O => \^m_aready0__3\
);
\s_axi_wready[0]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0000CA000000CA"
)
port map (
I0 => m_axi_wready(0),
I1 => p_22_in,
I2 => m_select_enc(2),
I3 => m_select_enc(1),
I4 => m_select_enc(0),
I5 => m_axi_wready(3),
O => \s_axi_wready[0]_INST_0_i_2_n_0\
);
\storage_data1[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"C5FFC500"
)
port map (
I0 => match,
I1 => p_3_out,
I2 => out0(0),
I3 => load_s1,
I4 => m_select_enc(2),
O => \storage_data1_reg[2]\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
\m_payload_i_reg[2]_0\ : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
mi_bready_4 : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_29_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\ : STD_LOGIC;
signal \^m_payload_i_reg[2]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__0_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^mi_bready_4\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
begin
\m_payload_i_reg[2]_0\ <= \^m_payload_i_reg[2]_0\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
mi_bready_4 <= \^mi_bready_4\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\aresetn_d_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]\,
Q => \^s_ready_i_reg_0\,
R => '0'
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => p_29_in,
I1 => \^mi_bready_4\,
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[2]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__0_n_0\
);
\m_valid_i_i_1__9\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^s_ready_i_reg_0\,
O => \^m_valid_i_reg_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__0_n_0\,
Q => \^m_payload_i_reg[2]_0\,
R => \^m_valid_i_reg_0\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[2]_0\,
I1 => p_29_in,
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \^s_ready_i_reg_0\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^mi_bready_4\,
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__2_n_0\ : STD_LOGIC;
signal \s_ready_i_i_1__3_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen60_in\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__2_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__2_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__3_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__3_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_1_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__1_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen53_in\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => m_valid_i_i_1_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_1_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__1_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__1_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
p_108_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal m_valid_i_i_2_n_0 : STD_LOGIC;
signal \s_ready_i_i_1__0_n_0\ : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
\last_rr_hot[2]_i_2__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_108_out,
O => \chosen_reg[2]\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen411_in\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
m_valid_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => m_valid_i_i_2_n_0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i_i_2_n_0,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_0\,
O => \s_ready_i_i_1__0_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__0_n_0\,
Q => \^m_axi_bready\(0),
R => p_1_in
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ is
port (
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
\chosen_reg[4]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
p_88_out : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 13 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\ is
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\ : STD_LOGIC;
signal \^m_axi_bready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^p_1_in\ : STD_LOGIC;
signal s_ready_i_i_2_n_0 : STD_LOGIC;
begin
m_axi_bready(0) <= \^m_axi_bready\(0);
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
p_1_in <= \^p_1_in\;
\aresetn_d[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => p_0_in(1),
I1 => aresetn,
O => \aresetn_d_reg[1]\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => p_0_in(1),
R => '0'
);
\last_rr_hot[4]_i_3__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => p_88_out,
O => \chosen_reg[4]\
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
O => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(12),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(13),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen6\,
D => D(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBBBBBB"
)
port map (
I0 => m_axi_bvalid(0),
I1 => \^m_axi_bready\(0),
I2 => s_axi_bready(0),
I3 => \^m_payload_i_reg[0]_0\,
I4 => Q(0),
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^m_payload_i_reg[0]_0\,
R => \aresetn_d_reg[1]_0\
);
s_ready_i_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => p_0_in(1),
O => \^p_1_in\
);
s_ready_i_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"B111FFFF"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => m_axi_bvalid(0),
I2 => s_axi_bready(0),
I3 => Q(0),
I4 => \aresetn_d_reg[1]_1\,
O => s_ready_i_i_2_n_0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i_i_2_n_0,
Q => \^m_axi_bready\(0),
R => \^p_1_in\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\skid_buffer_reg[34]_0\ : out STD_LOGIC;
\r_cmd_pop_4__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_23_in : in STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_25_in : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 12 downto 0 );
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \s_ready_i_i_1__6_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 34 );
signal \^skid_buffer_reg[34]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__3\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__3\ : label is "soft_lutpair123";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__3\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__3\ : label is "soft_lutpair122";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__3\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__3\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__3\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__3\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__3\ : label is "soft_lutpair118";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__3\ : label is "soft_lutpair118";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0);
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\skid_buffer_reg[34]_0\ <= \^skid_buffer_reg[34]_0\;
\gen_master_slots[4].r_issuing_cnt[32]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
I1 => \chosen_reg[4]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \r_cmd_pop_4__1\
);
\m_payload_i[34]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => p_25_in,
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(0),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(1),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(2),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(3),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(4),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[40]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(5),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(6),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(7),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(8),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(9),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(10),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \gen_axi.s_axi_rid_i_reg[11]\(11),
I1 => \^skid_buffer_reg[34]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_valid_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^skid_buffer_reg[34]_0\,
I1 => p_23_in,
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[4]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[4]\(0),
I3 => \^skid_buffer_reg[34]_0\,
I4 => p_23_in,
O => \s_ready_i_i_1__6_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__6_n_0\,
Q => \^skid_buffer_reg[34]_0\,
R => p_1_in
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => p_25_in,
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[34]_0\,
D => \gen_axi.s_axi_rid_i_reg[11]\(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[3]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_3__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[4]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_3 : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
match : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_39_in : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\ : STD_LOGIC;
signal \^m_axi_rready[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_3__1\ : STD_LOGIC;
signal \s_ready_i_i_1__7_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[3].r_issuing_cnt[27]_i_3\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \last_rr_hot[4]_i_3\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__7\ : label is "soft_lutpair112";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__2\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__2\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__2\ : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__2\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__2\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__2\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__2\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__2\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__2\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__2\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__2\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair114";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[3]\ <= \^m_axi_rready[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_3__1\ <= \^r_cmd_pop_3__1\;
\gen_master_slots[3].r_issuing_cnt[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => r_issuing_cnt(1),
I1 => r_issuing_cnt(2),
I2 => r_issuing_cnt(0),
I3 => r_issuing_cnt(3),
I4 => \^r_cmd_pop_3__1\,
I5 => p_39_in,
O => E(0)
);
\gen_master_slots[3].r_issuing_cnt[27]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[3]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_3__1\
);
\gen_no_arbiter.s_ready_i[0]_i_17__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8FF00F8F8FFFF"
)
port map (
I0 => ADDRESS_HIT_3,
I1 => \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\,
I2 => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
I3 => \r_cmd_pop_4__1\,
I4 => match,
I5 => r_issuing_cnt(4),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_24__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_3__1\,
I1 => r_issuing_cnt(0),
I2 => r_issuing_cnt(3),
I3 => r_issuing_cnt(1),
I4 => r_issuing_cnt(2),
O => \gen_no_arbiter.s_ready_i[0]_i_24__0_n_0\
);
\last_rr_hot[4]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => p_82_out,
O => \chosen_reg[4]\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__7\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[3]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[3]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__6\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[3]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[3]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[3]\(0),
I3 => \^m_axi_rready[3]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__7_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__7_n_0\,
Q => \^m_axi_rready[3]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[3]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[2]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\r_cmd_pop_2__1\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].r_issuing_cnt_reg[18]\ : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_4 : in STD_LOGIC;
\s_axi_araddr[25]\ : in STD_LOGIC;
sel_2 : in STD_LOGIC;
p_57_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[2]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_2__1\ : STD_LOGIC;
signal \s_ready_i_i_1__8_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__6\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair89";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[2]\ <= \^m_axi_rready[2]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_2__1\ <= \^r_cmd_pop_2__1\;
\gen_master_slots[2].r_issuing_cnt[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(1),
I1 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(2),
I2 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0),
I3 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3),
I4 => \^r_cmd_pop_2__1\,
I5 => p_57_in,
O => E(0)
);
\gen_master_slots[2].r_issuing_cnt[19]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[2]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_2__1\
);
\gen_no_arbiter.s_ready_i[0]_i_25__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FE00000000000000"
)
port map (
I0 => \gen_master_slots[2].r_issuing_cnt_reg[18]\,
I1 => \gen_master_slots[2].r_issuing_cnt_reg[19]\(0),
I2 => \^r_cmd_pop_2__1\,
I3 => sel_4,
I4 => \s_axi_araddr[25]\,
I5 => sel_2,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__6\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[2]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[2]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__7\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[2]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[2]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__8\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[2]\(0),
I3 => \^m_axi_rready[2]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__8_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__8_n_0\,
Q => \^m_axi_rready[2]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[2]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_1__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_1 : in STD_LOGIC;
match : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_75_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\ : STD_LOGIC;
signal \^m_axi_rready[1]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_1__1\ : STD_LOGIC;
signal \s_ready_i_i_1__5_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__5\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1__0\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1__0\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2__0\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair66";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[1]\ <= \^m_axi_rready[1]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_1__1\ <= \^r_cmd_pop_1__1\;
\gen_master_slots[1].r_issuing_cnt[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1),
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3),
I4 => \^r_cmd_pop_1__1\,
I5 => p_75_in,
O => E(0)
);
\gen_master_slots[1].r_issuing_cnt[11]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[1]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_1__1\
);
\gen_no_arbiter.s_ready_i[0]_i_16__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0808080"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\,
I1 => ADDRESS_HIT_1,
I2 => match,
I3 => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
I4 => ADDRESS_HIT_0,
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\gen_no_arbiter.s_ready_i[0]_i_20__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_1__1\,
I1 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(0),
I2 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3),
I3 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(1),
I4 => \gen_master_slots[1].r_issuing_cnt_reg[11]\(2),
O => \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[1]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[1]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[1]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[1]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__5\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[1]\(0),
I3 => \^m_axi_rready[1]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__5_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__5_n_0\,
Q => \^m_axi_rready[1]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[1]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ is
port (
m_valid_i_reg_0 : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_0__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : in STD_LOGIC;
p_102_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
\chosen_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\ is
signal \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \^m_axi_rready[0]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^r_cmd_pop_0__1\ : STD_LOGIC;
signal \s_ready_i_i_1__4_n_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 46 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_master_slots[0].r_issuing_cnt[3]_i_3\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \last_rr_hot[2]_i_2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__4\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair44";
begin
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) <= \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0);
\m_axi_rready[0]\ <= \^m_axi_rready[0]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
\r_cmd_pop_0__1\ <= \^r_cmd_pop_0__1\;
\gen_master_slots[0].r_issuing_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I4 => \^r_cmd_pop_0__1\,
I5 => p_93_in,
O => E(0)
);
\gen_master_slots[0].r_issuing_cnt[3]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
I1 => \chosen_reg[0]\(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
O => \^r_cmd_pop_0__1\
);
\gen_no_arbiter.s_ready_i[0]_i_22__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFEF"
)
port map (
I0 => \^r_cmd_pop_0__1\,
I1 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(0),
I2 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3),
I3 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(1),
I4 => \gen_master_slots[0].r_issuing_cnt_reg[3]\(2),
O => \gen_no_arbiter.s_ready_i_reg[0]\
);
\last_rr_hot[2]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => p_102_out,
O => \chosen_reg[2]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(12),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(13),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(14),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(15),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(16),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(17),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(18),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(19),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(20),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(21),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(22),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(23),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(24),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(25),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(26),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(27),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(28),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(29),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(30),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(31),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rresp(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rlast(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(0),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(1),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(2),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => skid_buffer(37)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(3),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => skid_buffer(40)
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => skid_buffer(41)
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => skid_buffer(42)
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => skid_buffer(43)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(10),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rid(11),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(4),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(5),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(6),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(7),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(8),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => m_axi_rdata(9),
I1 => \^m_axi_rready[0]\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(0),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(10),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(11),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(12),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(13),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(14),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(15),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(16),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(17),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(18),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(19),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(1),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(20),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(21),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(22),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(23),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(24),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(25),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(26),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(27),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(28),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(29),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(2),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(30),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(31),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(32),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(33),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(34),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(35),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(36),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(37),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(38),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(39),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(3),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(40),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(41),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(42),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(43),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(44),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(45),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(46),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(4),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(5),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(6),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(7),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(8),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \chosen_reg[0]_0\(0),
D => skid_buffer(9),
Q => \^gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(9),
R => '0'
);
\m_valid_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"DDFDFDFD"
)
port map (
I0 => \^m_axi_rready[0]\,
I1 => m_axi_rvalid(0),
I2 => \^m_valid_i_reg_0\,
I3 => s_axi_rready(0),
I4 => \chosen_reg[0]\(0),
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]\
);
\s_ready_i_i_1__4\: unisim.vcomponents.LUT5
generic map(
INIT => X"D5D5FFD5"
)
port map (
I0 => \^m_valid_i_reg_0\,
I1 => s_axi_rready(0),
I2 => \chosen_reg[0]\(0),
I3 => \^m_axi_rready[0]\,
I4 => m_axi_rvalid(0),
O => \s_ready_i_i_1__4_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__4_n_0\,
Q => \^m_axi_rready[0]\,
R => p_1_in
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rresp(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rlast(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(2),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(3),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(4),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(5),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(6),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(7),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(8),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(9),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(10),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rid(11),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^m_axi_rready[0]\,
D => m_axi_rdata(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc is
port (
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
resp_select : in STD_LOGIC_VECTOR ( 0 to 0 );
f_mux4_return : in STD_LOGIC_VECTOR ( 46 downto 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
\m_payload_i_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\ : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.accept_cnt_reg[0]\ : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_master_slots[4].r_issuing_cnt_reg[32]\ : in STD_LOGIC;
cmd_push_0 : in STD_LOGIC;
\thread_valid_0__2\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\thread_valid_3__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_4 : in STD_LOGIC;
\thread_valid_4__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_7 : in STD_LOGIC;
\thread_valid_7__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_6 : in STD_LOGIC;
\thread_valid_6__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_5 : in STD_LOGIC;
\thread_valid_5__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_2 : in STD_LOGIC;
\thread_valid_2__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_1 : in STD_LOGIC;
\thread_valid_1__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc is
signal \any_pop__1\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\ : STD_LOGIC;
signal \^m_valid_i\ : STD_LOGIC;
signal \^s_axi_rid[0]\ : STD_LOGIC;
signal \^s_axi_rid[10]\ : STD_LOGIC;
signal \^s_axi_rid[11]\ : STD_LOGIC;
signal \^s_axi_rid[1]\ : STD_LOGIC;
signal \^s_axi_rid[2]\ : STD_LOGIC;
signal \^s_axi_rid[3]\ : STD_LOGIC;
signal \^s_axi_rid[4]\ : STD_LOGIC;
signal \^s_axi_rid[5]\ : STD_LOGIC;
signal \^s_axi_rid[6]\ : STD_LOGIC;
signal \^s_axi_rid[7]\ : STD_LOGIC;
signal \^s_axi_rid[8]\ : STD_LOGIC;
signal \^s_axi_rid[9]\ : STD_LOGIC;
signal \^s_axi_rlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[0].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[10].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[11].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[12].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[13].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[15].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[16].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[17].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[18].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[19].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[1].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[20].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[21].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[22].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[23].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[24].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[25].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[26].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[27].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[28].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[29].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[2].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[30].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[31].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[32].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[33].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[34].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[35].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[36].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[37].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[38].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[39].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[3].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[40].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[41].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[42].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[43].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[44].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[45].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[46].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[47].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[4].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[5].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[6].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[7].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[8].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[9].mux_s2_inst\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1__0\ : label is "soft_lutpair132";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1__0\ : label is "soft_lutpair132";
begin
m_valid_i <= \^m_valid_i\;
\s_axi_rid[0]\ <= \^s_axi_rid[0]\;
\s_axi_rid[10]\ <= \^s_axi_rid[10]\;
\s_axi_rid[11]\ <= \^s_axi_rid[11]\;
\s_axi_rid[1]\ <= \^s_axi_rid[1]\;
\s_axi_rid[2]\ <= \^s_axi_rid[2]\;
\s_axi_rid[3]\ <= \^s_axi_rid[3]\;
\s_axi_rid[4]\ <= \^s_axi_rid[4]\;
\s_axi_rid[5]\ <= \^s_axi_rid[5]\;
\s_axi_rid[6]\ <= \^s_axi_rid[6]\;
\s_axi_rid[7]\ <= \^s_axi_rid[7]\;
\s_axi_rid[8]\ <= \^s_axi_rid[8]\;
\s_axi_rid[9]\ <= \^s_axi_rid[9]\;
s_axi_rlast(0) <= \^s_axi_rlast\(0);
\gen_fpga.gen_mux_5_8[0].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(0),
I1 => st_mr_rid(0),
O => \^s_axi_rid[0]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(10),
I1 => st_mr_rid(10),
O => \^s_axi_rid[10]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(11),
I1 => st_mr_rid(11),
O => \^s_axi_rid[11]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(12),
I1 => '1',
O => s_axi_rresp(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(13),
I1 => '1',
O => s_axi_rresp(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(14),
I1 => '0',
O => s_axi_rdata(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[16].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(15),
I1 => '0',
O => s_axi_rdata(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[17].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(16),
I1 => '0',
O => s_axi_rdata(2),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[18].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(17),
I1 => '0',
O => s_axi_rdata(3),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[19].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(18),
I1 => '0',
O => s_axi_rdata(4),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(1),
I1 => st_mr_rid(1),
O => \^s_axi_rid[1]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[20].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(19),
I1 => '0',
O => s_axi_rdata(5),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[21].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(20),
I1 => '0',
O => s_axi_rdata(6),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[22].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(21),
I1 => '0',
O => s_axi_rdata(7),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[23].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(22),
I1 => '0',
O => s_axi_rdata(8),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[24].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(23),
I1 => '0',
O => s_axi_rdata(9),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[25].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(24),
I1 => '0',
O => s_axi_rdata(10),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[26].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(25),
I1 => '0',
O => s_axi_rdata(11),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[27].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(26),
I1 => '0',
O => s_axi_rdata(12),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[28].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(27),
I1 => '0',
O => s_axi_rdata(13),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[29].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(28),
I1 => '0',
O => s_axi_rdata(14),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(2),
I1 => st_mr_rid(2),
O => \^s_axi_rid[2]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[30].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(29),
I1 => '0',
O => s_axi_rdata(15),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[31].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(30),
I1 => '0',
O => s_axi_rdata(16),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[32].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(31),
I1 => '0',
O => s_axi_rdata(17),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[33].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(32),
I1 => '0',
O => s_axi_rdata(18),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[34].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(33),
I1 => '0',
O => s_axi_rdata(19),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[35].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(34),
I1 => '0',
O => s_axi_rdata(20),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[36].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(35),
I1 => '0',
O => s_axi_rdata(21),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[37].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(36),
I1 => '0',
O => s_axi_rdata(22),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[38].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(37),
I1 => '0',
O => s_axi_rdata(23),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[39].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(38),
I1 => '0',
O => s_axi_rdata(24),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(3),
I1 => st_mr_rid(3),
O => \^s_axi_rid[3]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[40].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(39),
I1 => '0',
O => s_axi_rdata(25),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[41].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(40),
I1 => '0',
O => s_axi_rdata(26),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[42].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(41),
I1 => '0',
O => s_axi_rdata(27),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[43].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(42),
I1 => '0',
O => s_axi_rdata(28),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[44].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(43),
I1 => '0',
O => s_axi_rdata(29),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[45].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(44),
I1 => '0',
O => s_axi_rdata(30),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[46].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(45),
I1 => '0',
O => s_axi_rdata(31),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[47].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(46),
I1 => \m_payload_i_reg[34]\(0),
O => \^s_axi_rlast\(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(4),
I1 => st_mr_rid(4),
O => \^s_axi_rid[4]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(5),
I1 => st_mr_rid(5),
O => \^s_axi_rid[5]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(6),
I1 => st_mr_rid(6),
O => \^s_axi_rid[6]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(7),
I1 => st_mr_rid(7),
O => \^s_axi_rid[7]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(8),
I1 => st_mr_rid(8),
O => \^s_axi_rid[8]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(9),
I1 => st_mr_rid(9),
O => \^s_axi_rid[9]\,
S => resp_select(0)
);
\gen_multi_thread.accept_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A65"
)
port map (
I0 => Q(0),
I1 => \any_pop__1\,
I2 => S_AXI_ARREADY(0),
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFF2200D"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => \any_pop__1\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => \any_pop__1\,
I5 => S_AXI_ARREADY(0),
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800FFAE0051"
)
port map (
I0 => Q(1),
I1 => S_AXI_ARREADY(0),
I2 => \any_pop__1\,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_0,
I1 => \any_pop__1\,
I2 => \thread_valid_0__2\,
I3 => CO(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_1,
I1 => \any_pop__1\,
I2 => \thread_valid_1__2\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_2,
I1 => \any_pop__1\,
I2 => \thread_valid_2__2\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_3,
I1 => \any_pop__1\,
I2 => \thread_valid_3__2\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_4,
I1 => \any_pop__1\,
I2 => \thread_valid_4__2\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_5,
I1 => \any_pop__1\,
I2 => \thread_valid_5__2\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_6,
I1 => \any_pop__1\,
I2 => \thread_valid_6__2\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_7,
I1 => \any_pop__1\,
I2 => \thread_valid_7__2\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_rready(0),
I1 => \^s_axi_rlast\(0),
I2 => s_axi_rvalid(0),
O => \any_pop__1\
);
\gen_no_arbiter.s_ready_i[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^m_valid_i\,
I1 => aresetn_d,
O => E(0)
);
\gen_no_arbiter.s_ready_i[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000100"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\,
I2 => \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\,
I3 => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\,
I4 => \gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\,
I5 => aa_mi_arvalid,
O => \^m_valid_i\
);
\gen_no_arbiter.s_ready_i[0]_i_6__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FD00FD00FD000000"
)
port map (
I0 => Q(3),
I1 => \any_pop__1\,
I2 => \gen_multi_thread.accept_cnt_reg[0]\,
I3 => \gen_no_arbiter.s_ready_i_reg[0]\,
I4 => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
I5 => \gen_master_slots[4].r_issuing_cnt_reg[32]\,
O => \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0\
);
\i__carry_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \^s_axi_rid[11]\,
O => S(3)
);
\i__carry_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \^s_axi_rid[8]\,
O => S(2)
);
\i__carry_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \^s_axi_rid[5]\,
O => S(1)
);
\i__carry_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \^s_axi_rid[2]\,
O => S(0)
);
p_10_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
p_10_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
p_10_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
p_10_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
p_12_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
p_12_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
p_12_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
p_12_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
p_14_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(3)
);
p_14_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(2)
);
p_14_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(1)
);
p_14_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(0)
);
p_2_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
p_2_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
p_2_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
p_2_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
p_4_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
p_4_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
p_4_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
p_4_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
p_6_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
p_6_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
p_6_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
p_6_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
p_8_out_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \^s_axi_rid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \^s_axi_rid[11]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3)
);
p_8_out_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \^s_axi_rid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \^s_axi_rid[8]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2)
);
p_8_out_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \^s_axi_rid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \^s_axi_rid[5]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1)
);
p_8_out_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_rid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \^s_axi_rid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \^s_axi_rid[2]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ is
port (
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\any_pop__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.accept_cnt_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
resp_select : in STD_LOGIC_VECTOR ( 0 to 0 );
f_mux4_return : in STD_LOGIC_VECTOR ( 13 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
cmd_push_0 : in STD_LOGIC;
\thread_valid_0__2\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_3 : in STD_LOGIC;
\thread_valid_3__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_4 : in STD_LOGIC;
\thread_valid_4__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_7 : in STD_LOGIC;
\thread_valid_7__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_6 : in STD_LOGIC;
\thread_valid_6__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_5 : in STD_LOGIC;
\thread_valid_5__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_2 : in STD_LOGIC;
\thread_valid_2__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
cmd_push_1 : in STD_LOGIC;
\thread_valid_1__2\ : in STD_LOGIC;
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_ready_d_reg[1]\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ : entity is "generic_baseblocks_v2_1_0_mux_enc";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\ is
signal \^any_pop__1\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \^s_axi_bid[0]\ : STD_LOGIC;
signal \^s_axi_bid[10]\ : STD_LOGIC;
signal \^s_axi_bid[11]\ : STD_LOGIC;
signal \^s_axi_bid[1]\ : STD_LOGIC;
signal \^s_axi_bid[2]\ : STD_LOGIC;
signal \^s_axi_bid[3]\ : STD_LOGIC;
signal \^s_axi_bid[4]\ : STD_LOGIC;
signal \^s_axi_bid[5]\ : STD_LOGIC;
signal \^s_axi_bid[6]\ : STD_LOGIC;
signal \^s_axi_bid[7]\ : STD_LOGIC;
signal \^s_axi_bid[8]\ : STD_LOGIC;
signal \^s_axi_bid[9]\ : STD_LOGIC;
attribute BOX_TYPE : string;
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[0].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[10].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[11].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[12].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[13].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[15].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[1].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[2].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[3].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[4].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[5].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[6].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[7].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[8].mux_s2_inst\ : label is "PRIMITIVE";
attribute BOX_TYPE of \gen_fpga.gen_mux_5_8[9].mux_s2_inst\ : label is "PRIMITIVE";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[1]_i_1\ : label is "soft_lutpair158";
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[2]_i_1\ : label is "soft_lutpair158";
begin
\any_pop__1\ <= \^any_pop__1\;
\s_axi_bid[0]\ <= \^s_axi_bid[0]\;
\s_axi_bid[10]\ <= \^s_axi_bid[10]\;
\s_axi_bid[11]\ <= \^s_axi_bid[11]\;
\s_axi_bid[1]\ <= \^s_axi_bid[1]\;
\s_axi_bid[2]\ <= \^s_axi_bid[2]\;
\s_axi_bid[3]\ <= \^s_axi_bid[3]\;
\s_axi_bid[4]\ <= \^s_axi_bid[4]\;
\s_axi_bid[5]\ <= \^s_axi_bid[5]\;
\s_axi_bid[6]\ <= \^s_axi_bid[6]\;
\s_axi_bid[7]\ <= \^s_axi_bid[7]\;
\s_axi_bid[8]\ <= \^s_axi_bid[8]\;
\s_axi_bid[9]\ <= \^s_axi_bid[9]\;
\gen_fpga.gen_mux_5_8[0].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(0),
I1 => st_mr_bid(0),
O => \^s_axi_bid[0]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[10].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(10),
I1 => st_mr_bid(10),
O => \^s_axi_bid[10]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[11].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(11),
I1 => st_mr_bid(11),
O => \^s_axi_bid[11]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[12].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(12),
I1 => '1',
O => s_axi_bresp(0),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[13].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(13),
I1 => '1',
O => s_axi_bresp(1),
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[15].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => '1',
I1 => '1',
O => p_0_out,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[1].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(1),
I1 => st_mr_bid(1),
O => \^s_axi_bid[1]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[2].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(2),
I1 => st_mr_bid(2),
O => \^s_axi_bid[2]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[3].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(3),
I1 => st_mr_bid(3),
O => \^s_axi_bid[3]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[4].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(4),
I1 => st_mr_bid(4),
O => \^s_axi_bid[4]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[5].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(5),
I1 => st_mr_bid(5),
O => \^s_axi_bid[5]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[6].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(6),
I1 => st_mr_bid(6),
O => \^s_axi_bid[6]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[7].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(7),
I1 => st_mr_bid(7),
O => \^s_axi_bid[7]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[8].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(8),
I1 => st_mr_bid(8),
O => \^s_axi_bid[8]\,
S => resp_select(0)
);
\gen_fpga.gen_mux_5_8[9].mux_s2_inst\: unisim.vcomponents.MUXF7
port map (
I0 => f_mux4_return(9),
I1 => st_mr_bid(9),
O => \^s_axi_bid[9]\,
S => resp_select(0)
);
\gen_multi_thread.accept_cnt[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9A65"
)
port map (
I0 => Q(0),
I1 => \^any_pop__1\,
I2 => \m_ready_d_reg[1]\,
I3 => Q(1),
O => D(0)
);
\gen_multi_thread.accept_cnt[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"DFF2200D"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \^any_pop__1\,
I2 => Q(0),
I3 => Q(1),
I4 => Q(2),
O => D(1)
);
\gen_multi_thread.accept_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFFFFFE0000"
)
port map (
I0 => Q(1),
I1 => Q(2),
I2 => Q(0),
I3 => Q(3),
I4 => \^any_pop__1\,
I5 => \m_ready_d_reg[1]\,
O => \gen_multi_thread.accept_cnt_reg[3]\(0)
);
\gen_multi_thread.accept_cnt[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FF0800FFAE0051"
)
port map (
I0 => Q(1),
I1 => \m_ready_d_reg[1]\,
I2 => \^any_pop__1\,
I3 => Q(0),
I4 => Q(3),
I5 => Q(2),
O => D(2)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_0,
I1 => \^any_pop__1\,
I2 => \thread_valid_0__2\,
I3 => CO(0),
O => E(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_1,
I1 => \^any_pop__1\,
I2 => \thread_valid_1__2\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_2,
I1 => \^any_pop__1\,
I2 => \thread_valid_2__2\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_3,
I1 => \^any_pop__1\,
I2 => \thread_valid_3__2\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_4,
I1 => \^any_pop__1\,
I2 => \thread_valid_4__2\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_5,
I1 => \^any_pop__1\,
I2 => \thread_valid_5__2\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_6,
I1 => \^any_pop__1\,
I2 => \thread_valid_6__2\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => cmd_push_7,
I1 => \^any_pop__1\,
I2 => \thread_valid_7__2\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => s_axi_bready(0),
I1 => p_0_out,
I2 => s_axi_bvalid(0),
O => \^any_pop__1\
);
\i__carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(9),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11),
I5 => \^s_axi_bid[11]\,
O => S(3)
);
\i__carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(6),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(8),
I5 => \^s_axi_bid[8]\,
O => S(2)
);
\i__carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(3),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(5),
I5 => \^s_axi_bid[5]\,
O => S(1)
);
\i__carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(0),
I4 => \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(2),
I5 => \^s_axi_bid[2]\,
O => S(0)
);
\p_10_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(9),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3)
);
\p_10_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(6),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2)
);
\p_10_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(3),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1)
);
\p_10_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(0),
I4 => \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0)
);
\p_12_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3)
);
\p_12_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2)
);
\p_12_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1)
);
\p_12_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0)
);
\p_14_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(9),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3)
);
\p_14_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(6),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2)
);
\p_14_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(3),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1)
);
\p_14_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(0),
I4 => \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0)
);
\p_2_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(9),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3)
);
\p_2_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(6),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2)
);
\p_2_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(3),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1)
);
\p_2_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(0),
I4 => \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0)
);
\p_4_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(9),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3)
);
\p_4_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(6),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2)
);
\p_4_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(3),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1)
);
\p_4_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(0),
I4 => \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0)
);
\p_6_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(9),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3)
);
\p_6_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(6),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2)
);
\p_6_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(3),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1)
);
\p_6_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(0),
I4 => \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0)
);
\p_8_out_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[10]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(10),
I2 => \^s_axi_bid[9]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(9),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11),
I5 => \^s_axi_bid[11]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3)
);
\p_8_out_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[7]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(7),
I2 => \^s_axi_bid[6]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(6),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(8),
I5 => \^s_axi_bid[8]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2)
);
\p_8_out_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[4]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(4),
I2 => \^s_axi_bid[3]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(3),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(5),
I5 => \^s_axi_bid[5]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1)
);
\p_8_out_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^s_axi_bid[1]\,
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(1),
I2 => \^s_axi_bid[0]\,
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(0),
I4 => \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(2),
I5 => \^s_axi_bid[2]\,
O => \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor is
port (
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[0]_2\ : out STD_LOGIC_VECTOR ( 0 to 0 );
st_mr_rid : in STD_LOGIC_VECTOR ( 59 downto 0 );
\m_payload_i_reg[34]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
aresetn_d : in STD_LOGIC;
aa_mi_arvalid : in STD_LOGIC;
\s_axi_araddr[18]\ : in STD_LOGIC;
\s_axi_araddr[25]\ : in STD_LOGIC;
match : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[8]\ : in STD_LOGIC;
\gen_master_slots[4].r_issuing_cnt_reg[32]\ : in STD_LOGIC;
S_AXI_ARREADY : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : in STD_LOGIC;
st_mr_rmesg : in STD_LOGIC_VECTOR ( 135 downto 0 );
\m_payload_i_reg[34]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_2\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[34]_4\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_62_out : in STD_LOGIC;
p_102_out : in STD_LOGIC;
p_40_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
p_82_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_arid[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \accum_push_5__0\ : STD_LOGIC;
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 58 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal aid_match_00_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_00_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal aid_match_10_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_10_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal aid_match_20_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_20_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal aid_match_30_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_30_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal aid_match_40_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_40_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal aid_match_50_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_50_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal aid_match_60_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_60_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal \aid_match_6__0\ : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal aid_match_70_carry_i_1_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_2_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_3_n_0 : STD_LOGIC;
signal aid_match_70_carry_i_4_n_0 : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal \aid_match_7__0\ : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal f_mux4_return : STD_LOGIC_VECTOR ( 47 downto 0 );
signal \gen_multi_thread.accept_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_49\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_50\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_51\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_52\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_53\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_54\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_55\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_56\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_57\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_58\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_59\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_60\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_61\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_62\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_63\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_64\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_65\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_66\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_67\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_68\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_69\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_70\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_71\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_72\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_73\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_74\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_75\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_76\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_77\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_78\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_79\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_80\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_81\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_82\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_83\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_84\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_85\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_86\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_87\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_88\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_89\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_90\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_91\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_92\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal resp_select : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^s_axi_rvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \thread_valid_0__2\ : STD_LOGIC;
signal \thread_valid_1__2\ : STD_LOGIC;
signal \thread_valid_2__2\ : STD_LOGIC;
signal \thread_valid_3__2\ : STD_LOGIC;
signal \thread_valid_4__2\ : STD_LOGIC;
signal \thread_valid_5__2\ : STD_LOGIC;
signal \thread_valid_6__2\ : STD_LOGIC;
signal \thread_valid_7__2\ : STD_LOGIC;
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1\ : label is "soft_lutpair151";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\ : label is "soft_lutpair143";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\ : label is "soft_lutpair140";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\ : label is "soft_lutpair141";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0\ : label is "soft_lutpair142";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0\ : label is "soft_lutpair144";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0\ : label is "soft_lutpair145";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\ : label is "soft_lutpair133";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\ : label is "soft_lutpair135";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0\ : label is "soft_lutpair146";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0\ : label is "soft_lutpair147";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\ : label is "soft_lutpair139";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\ : label is "soft_lutpair149";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\ : label is "soft_lutpair136";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0\ : label is "soft_lutpair148";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\ : label is "soft_lutpair150";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\ : label is "soft_lutpair134";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0\ : label is "soft_lutpair138";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0\ : label is "soft_lutpair137";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_14__0\ : label is "soft_lutpair151";
begin
D(0) <= \^d\(0);
s_axi_rvalid(0) <= \^s_axi_rvalid\(0);
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_00_carry_i_1_n_0,
S(2) => aid_match_00_carry_i_2_n_0,
S(1) => aid_match_00_carry_i_3_n_0,
S(0) => aid_match_00_carry_i_4_n_0
);
aid_match_00_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
O => aid_match_00_carry_i_1_n_0
);
aid_match_00_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
O => aid_match_00_carry_i_2_n_0
);
aid_match_00_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
O => aid_match_00_carry_i_3_n_0
);
aid_match_00_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
O => aid_match_00_carry_i_4_n_0
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_10_carry_i_1_n_0,
S(2) => aid_match_10_carry_i_2_n_0,
S(1) => aid_match_10_carry_i_3_n_0,
S(0) => aid_match_10_carry_i_4_n_0
);
aid_match_10_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
I5 => \s_axi_arid[11]\(11),
O => aid_match_10_carry_i_1_n_0
);
aid_match_10_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
I5 => \s_axi_arid[11]\(8),
O => aid_match_10_carry_i_2_n_0
);
aid_match_10_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
I5 => \s_axi_arid[11]\(5),
O => aid_match_10_carry_i_3_n_0
);
aid_match_10_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
I5 => \s_axi_arid[11]\(2),
O => aid_match_10_carry_i_4_n_0
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_20_carry_i_1_n_0,
S(2) => aid_match_20_carry_i_2_n_0,
S(1) => aid_match_20_carry_i_3_n_0,
S(0) => aid_match_20_carry_i_4_n_0
);
aid_match_20_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
O => aid_match_20_carry_i_1_n_0
);
aid_match_20_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
O => aid_match_20_carry_i_2_n_0
);
aid_match_20_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
O => aid_match_20_carry_i_3_n_0
);
aid_match_20_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
O => aid_match_20_carry_i_4_n_0
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_30_carry_i_1_n_0,
S(2) => aid_match_30_carry_i_2_n_0,
S(1) => aid_match_30_carry_i_3_n_0,
S(0) => aid_match_30_carry_i_4_n_0
);
aid_match_30_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
O => aid_match_30_carry_i_1_n_0
);
aid_match_30_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
O => aid_match_30_carry_i_2_n_0
);
aid_match_30_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
O => aid_match_30_carry_i_3_n_0
);
aid_match_30_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
O => aid_match_30_carry_i_4_n_0
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_40_carry_i_1_n_0,
S(2) => aid_match_40_carry_i_2_n_0,
S(1) => aid_match_40_carry_i_3_n_0,
S(0) => aid_match_40_carry_i_4_n_0
);
aid_match_40_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
O => aid_match_40_carry_i_1_n_0
);
aid_match_40_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
O => aid_match_40_carry_i_2_n_0
);
aid_match_40_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
O => aid_match_40_carry_i_3_n_0
);
aid_match_40_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
O => aid_match_40_carry_i_4_n_0
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_50_carry_i_1_n_0,
S(2) => aid_match_50_carry_i_2_n_0,
S(1) => aid_match_50_carry_i_3_n_0,
S(0) => aid_match_50_carry_i_4_n_0
);
aid_match_50_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
O => aid_match_50_carry_i_1_n_0
);
aid_match_50_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
O => aid_match_50_carry_i_2_n_0
);
aid_match_50_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
O => aid_match_50_carry_i_3_n_0
);
aid_match_50_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
O => aid_match_50_carry_i_4_n_0
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_60_carry_i_1_n_0,
S(2) => aid_match_60_carry_i_2_n_0,
S(1) => aid_match_60_carry_i_3_n_0,
S(0) => aid_match_60_carry_i_4_n_0
);
aid_match_60_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
O => aid_match_60_carry_i_1_n_0
);
aid_match_60_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
O => aid_match_60_carry_i_2_n_0
);
aid_match_60_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
O => aid_match_60_carry_i_3_n_0
);
aid_match_60_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
O => aid_match_60_carry_i_4_n_0
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => aid_match_70_carry_i_1_n_0,
S(2) => aid_match_70_carry_i_2_n_0,
S(1) => aid_match_70_carry_i_3_n_0,
S(0) => aid_match_70_carry_i_4_n_0
);
aid_match_70_carry_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
I2 => \s_axi_arid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
I4 => \s_axi_arid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
O => aid_match_70_carry_i_1_n_0
);
aid_match_70_carry_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
I2 => \s_axi_arid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
I4 => \s_axi_arid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
O => aid_match_70_carry_i_2_n_0
);
aid_match_70_carry_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
I2 => \s_axi_arid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
I4 => \s_axi_arid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
O => aid_match_70_carry_i_3_n_0
);
aid_match_70_carry_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_arid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
I2 => \s_axi_arid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
I4 => \s_axi_arid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
O => aid_match_70_carry_i_4_n_0
);
\gen_multi_thread.accept_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_57\,
D => \gen_multi_thread.accept_cnt[0]_i_1_n_0\,
Q => \gen_multi_thread.accept_cnt_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_57\,
D => \gen_multi_thread.mux_resp_multi_thread_n_60\,
Q => \gen_multi_thread.accept_cnt_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_57\,
D => \gen_multi_thread.mux_resp_multi_thread_n_59\,
Q => \gen_multi_thread.accept_cnt_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_57\,
D => \gen_multi_thread.mux_resp_multi_thread_n_58\,
Q => \gen_multi_thread.accept_cnt_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_8
port map (
Q(4 downto 0) => Q(4 downto 0),
SR(0) => SR(0),
aclk => aclk,
f_mux4_return(46 downto 14) => f_mux4_return(47 downto 15),
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\m_payload_i_reg[0]\(0) => \m_payload_i_reg[0]\(0),
\m_payload_i_reg[0]_0\(0) => \m_payload_i_reg[0]_0\(0),
\m_payload_i_reg[0]_1\(0) => \m_payload_i_reg[0]_1\(0),
\m_payload_i_reg[0]_2\(0) => \m_payload_i_reg[0]_2\(0),
\m_payload_i_reg[34]\(0) => \m_payload_i_reg[34]\(0),
\m_payload_i_reg[34]_0\(0) => \m_payload_i_reg[34]_1\(0),
\m_payload_i_reg[34]_1\(0) => \m_payload_i_reg[34]_2\(0),
\m_payload_i_reg[34]_2\(0) => \m_payload_i_reg[34]_3\(0),
\m_payload_i_reg[34]_3\(0) => \m_payload_i_reg[34]_4\(0),
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
p_102_out => p_102_out,
p_122_out => p_122_out,
p_40_out => p_40_out,
p_62_out => p_62_out,
p_82_out => p_82_out,
resp_select(0) => resp_select(2),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rvalid(0) => \^s_axi_rvalid\(0),
st_mr_rid(47 downto 0) => st_mr_rid(47 downto 0),
st_mr_rmesg(135 downto 0) => st_mr_rmesg(135 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(0),
I1 => cmd_push_0,
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(2),
I3 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(1),
I1 => cmd_push_0,
I2 => active_cnt(0),
I3 => active_cnt(3),
I4 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0\,
Q => active_cnt(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0\,
Q => active_cnt(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0\,
Q => active_cnt(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_49\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0\,
Q => active_cnt(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"E222"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => aid_match_00,
I3 => S_AXI_ARREADY(0),
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[18]\,
Q => active_target(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_araddr[25]\,
Q => active_target(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_1,
I1 => active_cnt(8),
I2 => active_cnt(10),
I3 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(9),
I1 => cmd_push_1,
I2 => active_cnt(8),
I3 => active_cnt(11),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(8),
I1 => cmd_push_1,
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_56\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0\,
Q => active_cnt(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_56\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0\,
Q => active_cnt(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_56\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0\,
Q => active_cnt(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_56\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0\,
Q => active_cnt(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => aid_match_10,
I4 => S_AXI_ARREADY(0),
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[18]\,
Q => active_target(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_araddr[25]\,
Q => active_target(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(16),
I1 => cmd_push_2,
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_2,
I1 => active_cnt(16),
I2 => active_cnt(18),
I3 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(17),
I1 => cmd_push_2,
I2 => active_cnt(16),
I3 => active_cnt(19),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0\,
Q => active_cnt(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0\,
Q => active_cnt(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0\,
Q => active_cnt(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_55\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0\,
Q => active_cnt(19),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80008000800080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => \thread_valid_2__2\,
I4 => aid_match_20,
I5 => S_AXI_ARREADY(0),
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
O => \thread_valid_0__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
O => \thread_valid_1__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
O => \thread_valid_2__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[18]\,
Q => active_target(16),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_araddr[25]\,
Q => active_target(17),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(18),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(24),
I1 => cmd_push_3,
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(26),
I3 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(25),
I1 => cmd_push_3,
I2 => active_cnt(24),
I3 => active_cnt(27),
I4 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0\,
Q => active_cnt(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0\,
Q => active_cnt(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0\,
Q => active_cnt(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_50\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0\,
Q => active_cnt(27),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I2 => \thread_valid_3__2\,
I3 => aid_match_30,
I4 => S_AXI_ARREADY(0),
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[18]\,
Q => active_target(24),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_araddr[25]\,
Q => active_target(25),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(26),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(32),
I1 => cmd_push_4,
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_4,
I1 => active_cnt(32),
I2 => active_cnt(34),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(33),
I1 => cmd_push_4,
I2 => active_cnt(32),
I3 => active_cnt(35),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0\,
Q => active_cnt(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0\,
Q => active_cnt(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0\,
Q => active_cnt(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_51\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0\,
Q => active_cnt(35),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
I1 => \thread_valid_3__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \thread_valid_4__2\,
I4 => aid_match_40,
I5 => S_AXI_ARREADY(0),
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555557FFFFFFFF"
)
port map (
I0 => \thread_valid_0__2\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
I5 => \thread_valid_2__2\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
O => \thread_valid_3__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
O => \thread_valid_4__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[18]\,
Q => active_target(32),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_araddr[25]\,
Q => active_target(33),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(34),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(40),
I1 => cmd_push_5,
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_5,
I1 => active_cnt(40),
I2 => active_cnt(42),
I3 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(41),
I1 => cmd_push_5,
I2 => active_cnt(40),
I3 => active_cnt(43),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0\,
Q => active_cnt(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0\,
Q => active_cnt(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0\,
Q => active_cnt(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_54\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0\,
Q => active_cnt(43),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I2 => \thread_valid_5__2\,
I3 => aid_match_50,
I4 => S_AXI_ARREADY(0),
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[18]\,
Q => active_target(40),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_araddr[25]\,
Q => active_target(41),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(42),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(48),
I1 => cmd_push_6,
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_6,
I1 => active_cnt(48),
I2 => active_cnt(50),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(49),
I1 => cmd_push_6,
I2 => active_cnt(48),
I3 => active_cnt(51),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0\,
Q => active_cnt(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0\,
Q => active_cnt(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0\,
Q => active_cnt(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_53\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0\,
Q => active_cnt(51),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \thread_valid_5__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \thread_valid_6__2\,
I4 => aid_match_60,
I5 => S_AXI_ARREADY(0),
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
O => \thread_valid_5__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(51),
I2 => active_cnt(49),
I3 => active_cnt(48),
O => \thread_valid_6__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[18]\,
Q => active_target(48),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_araddr[25]\,
Q => active_target(49),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(50),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(56),
I1 => cmd_push_7,
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_7,
I1 => active_cnt(56),
I2 => active_cnt(58),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(57),
I1 => cmd_push_7,
I2 => active_cnt(56),
I3 => active_cnt(59),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
O => \thread_valid_7__2\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0\,
Q => active_cnt(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0\,
Q => active_cnt(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0\,
Q => active_cnt(58),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_52\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0\,
Q => active_cnt(59),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(0),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(1),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(2),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(3),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(4),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(5),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(6),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(7),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(8),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(9),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(10),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_arid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\,
I3 => \aid_match_7__0\,
I4 => S_AXI_ARREADY(0),
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55555557"
)
port map (
I0 => \thread_valid_3__2\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2__0_n_0\,
O => \accum_push_5__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => \thread_valid_6__2\,
I5 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => S_AXI_ARREADY(0),
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\,
I4 => \aid_match_6__0\,
I5 => \aid_match_7__0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
O => \aid_match_7__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_00,
I1 => \thread_valid_0__2\,
I2 => aid_match_10,
I3 => \thread_valid_1__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_20,
I1 => \thread_valid_2__2\,
I2 => aid_match_30,
I3 => \thread_valid_3__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_40,
I1 => \thread_valid_4__2\,
I2 => aid_match_50,
I3 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(48),
I1 => active_cnt(49),
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => aid_match_60,
O => \aid_match_6__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[18]\,
Q => active_target(56),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_araddr[25]\,
Q => active_target(57),
R => SR(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(58),
R => SR(0)
);
\gen_multi_thread.mux_resp_multi_thread\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc
port map (
CO(0) => p_14_out,
D(2) => \gen_multi_thread.mux_resp_multi_thread_n_58\,
D(1) => \gen_multi_thread.mux_resp_multi_thread_n_59\,
D(0) => \gen_multi_thread.mux_resp_multi_thread_n_60\,
E(0) => E(0),
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg__0\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_61\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_62\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_63\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_64\,
S_AXI_ARREADY(0) => S_AXI_ARREADY(0),
aa_mi_arvalid => aa_mi_arvalid,
aresetn_d => aresetn_d,
cmd_push_0 => cmd_push_0,
cmd_push_1 => cmd_push_1,
cmd_push_2 => cmd_push_2,
cmd_push_3 => cmd_push_3,
cmd_push_4 => cmd_push_4,
cmd_push_5 => cmd_push_5,
cmd_push_6 => cmd_push_6,
cmd_push_7 => cmd_push_7,
f_mux4_return(46 downto 14) => f_mux4_return(47 downto 15),
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].r_issuing_cnt_reg[8]\,
\gen_master_slots[4].r_issuing_cnt_reg[32]\ => \gen_master_slots[4].r_issuing_cnt_reg[32]\,
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\,
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_89\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_90\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_91\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_92\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_85\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_86\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_87\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_88\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\ => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_81\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_82\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_83\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_84\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_77\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_78\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_79\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_80\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\ => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_73\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_74\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_75\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_76\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_69\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_70\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_71\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_72\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\ => \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_65\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_66\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_67\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_68\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg__0\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg__0\(11 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
\m_payload_i_reg[34]\(0) => \m_payload_i_reg[34]_0\(0),
m_valid_i => m_valid_i,
resp_select(0) => resp_select(2),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => \s_axi_rid[0]\,
\s_axi_rid[10]\ => \s_axi_rid[10]\,
\s_axi_rid[11]\ => \s_axi_rid[11]\,
\s_axi_rid[1]\ => \s_axi_rid[1]\,
\s_axi_rid[2]\ => \s_axi_rid[2]\,
\s_axi_rid[3]\ => \s_axi_rid[3]\,
\s_axi_rid[4]\ => \s_axi_rid[4]\,
\s_axi_rid[5]\ => \s_axi_rid[5]\,
\s_axi_rid[6]\ => \s_axi_rid[6]\,
\s_axi_rid[7]\ => \s_axi_rid[7]\,
\s_axi_rid[8]\ => \s_axi_rid[8]\,
\s_axi_rid[9]\ => \s_axi_rid[9]\,
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid(0) => \^s_axi_rvalid\(0),
st_mr_rid(11 downto 0) => st_mr_rid(59 downto 48),
\thread_valid_0__2\ => \thread_valid_0__2\,
\thread_valid_1__2\ => \thread_valid_1__2\,
\thread_valid_2__2\ => \thread_valid_2__2\,
\thread_valid_3__2\ => \thread_valid_3__2\,
\thread_valid_4__2\ => \thread_valid_4__2\,
\thread_valid_5__2\ => \thread_valid_5__2\,
\thread_valid_6__2\ => \thread_valid_6__2\,
\thread_valid_7__2\ => \thread_valid_7__2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => match,
O => \^d\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_10__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(8),
I1 => \s_axi_araddr[18]\,
I2 => active_target(9),
I3 => \s_axi_araddr[25]\,
I4 => match,
I5 => active_target(10),
O => \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_11__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(0),
I1 => \s_axi_araddr[18]\,
I2 => active_target(1),
I3 => \s_axi_araddr[25]\,
I4 => match,
I5 => active_target(2),
O => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(48),
I1 => \s_axi_araddr[18]\,
I2 => active_target(49),
I3 => \s_axi_araddr[25]\,
I4 => match,
I5 => active_target(50),
O => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(56),
I1 => \s_axi_araddr[18]\,
I2 => active_target(57),
I3 => \s_axi_araddr[25]\,
I4 => match,
I5 => active_target(58),
O => \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg__0\(0),
I1 => \gen_multi_thread.accept_cnt_reg__0\(2),
I2 => \gen_multi_thread.accept_cnt_reg__0\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(40),
I1 => \s_axi_araddr[18]\,
I2 => active_target(41),
I3 => \s_axi_araddr[25]\,
I4 => match,
I5 => active_target(42),
O => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(32),
I1 => \s_axi_araddr[18]\,
I2 => active_target(33),
I3 => \s_axi_araddr[25]\,
I4 => match,
I5 => active_target(34),
O => \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\,
I1 => \thread_valid_3__2\,
I2 => aid_match_30,
I3 => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\,
I4 => \thread_valid_2__2\,
I5 => aid_match_20,
O => \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0\,
I1 => \thread_valid_1__2\,
I2 => aid_match_10,
I3 => \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0\,
I4 => \thread_valid_0__2\,
I5 => aid_match_00,
O => \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF808080"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0\,
I1 => \thread_valid_6__2\,
I2 => aid_match_60,
I3 => \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0\,
I4 => \aid_match_7__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0\,
I1 => \thread_valid_5__2\,
I2 => aid_match_50,
I3 => \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0\,
I4 => \thread_valid_4__2\,
I5 => aid_match_40,
O => \gen_no_arbiter.s_ready_i[0]_i_7__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(24),
I1 => \s_axi_araddr[18]\,
I2 => active_target(25),
I3 => \s_axi_araddr[25]\,
I4 => match,
I5 => active_target(26),
O => \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(16),
I1 => \s_axi_araddr[18]\,
I2 => active_target(17),
I3 => \s_axi_araddr[25]\,
I4 => match,
I5 => active_target(18),
O => \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_61\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_62\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_63\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_64\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_81\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_82\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_83\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_84\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_85\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_86\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_87\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_88\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_89\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_90\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_91\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_92\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_65\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_66\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_67\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_68\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_69\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_70\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_71\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_72\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_73\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_74\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_75\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_76\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_77\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_78\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_79\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_80\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
port (
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].w_issuing_cnt_reg[16]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[3].w_issuing_cnt_reg[24]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].w_issuing_cnt_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
st_mr_bid : in STD_LOGIC_VECTOR ( 59 downto 0 );
w_issuing_cnt : in STD_LOGIC_VECTOR ( 16 downto 0 );
p_84_in : in STD_LOGIC;
p_66_in : in STD_LOGIC;
p_48_in : in STD_LOGIC;
p_101_in : in STD_LOGIC;
aresetn_d : in STD_LOGIC;
aa_sa_awvalid : in STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 1 downto 0 );
match : in STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]_0\ : in STD_LOGIC;
ADDRESS_HIT_3 : in STD_LOGIC;
ADDRESS_HIT_1 : in STD_LOGIC;
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[2].w_issuing_cnt_reg[18]\ : in STD_LOGIC;
sel_4 : in STD_LOGIC;
\s_axi_awaddr[25]\ : in STD_LOGIC;
sel_2 : in STD_LOGIC;
\m_ready_d_reg[1]\ : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
p_46_out : in STD_LOGIC;
p_128_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC;
st_mr_bmesg : in STD_LOGIC_VECTOR ( 7 downto 0 );
p_68_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_valid_i_reg_0 : in STD_LOGIC;
\s_axi_awid[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ : entity is "axi_crossbar_v2_1_14_si_transactor";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\ is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sr\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \accum_push_5__0\ : STD_LOGIC;
signal active_cnt : STD_LOGIC_VECTOR ( 59 downto 0 );
signal active_target : STD_LOGIC_VECTOR ( 58 downto 0 );
signal aid_match_00 : STD_LOGIC;
signal \aid_match_00_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_00_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_00_carry_n_1 : STD_LOGIC;
signal aid_match_00_carry_n_2 : STD_LOGIC;
signal aid_match_00_carry_n_3 : STD_LOGIC;
signal aid_match_10 : STD_LOGIC;
signal \aid_match_10_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_10_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_10_carry_n_1 : STD_LOGIC;
signal aid_match_10_carry_n_2 : STD_LOGIC;
signal aid_match_10_carry_n_3 : STD_LOGIC;
signal aid_match_20 : STD_LOGIC;
signal \aid_match_20_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_20_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_20_carry_n_1 : STD_LOGIC;
signal aid_match_20_carry_n_2 : STD_LOGIC;
signal aid_match_20_carry_n_3 : STD_LOGIC;
signal aid_match_30 : STD_LOGIC;
signal \aid_match_30_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_30_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_30_carry_n_1 : STD_LOGIC;
signal aid_match_30_carry_n_2 : STD_LOGIC;
signal aid_match_30_carry_n_3 : STD_LOGIC;
signal aid_match_40 : STD_LOGIC;
signal \aid_match_40_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_40_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_40_carry_n_1 : STD_LOGIC;
signal aid_match_40_carry_n_2 : STD_LOGIC;
signal aid_match_40_carry_n_3 : STD_LOGIC;
signal aid_match_50 : STD_LOGIC;
signal \aid_match_50_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_50_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_50_carry_n_1 : STD_LOGIC;
signal aid_match_50_carry_n_2 : STD_LOGIC;
signal aid_match_50_carry_n_3 : STD_LOGIC;
signal aid_match_60 : STD_LOGIC;
signal \aid_match_60_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_60_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_60_carry_n_1 : STD_LOGIC;
signal aid_match_60_carry_n_2 : STD_LOGIC;
signal aid_match_60_carry_n_3 : STD_LOGIC;
signal \aid_match_6__0\ : STD_LOGIC;
signal aid_match_70 : STD_LOGIC;
signal \aid_match_70_carry_i_1__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_2__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_3__0_n_0\ : STD_LOGIC;
signal \aid_match_70_carry_i_4__0_n_0\ : STD_LOGIC;
signal aid_match_70_carry_n_1 : STD_LOGIC;
signal aid_match_70_carry_n_2 : STD_LOGIC;
signal aid_match_70_carry_n_3 : STD_LOGIC;
signal \aid_match_7__0\ : STD_LOGIC;
signal \any_pop__1\ : STD_LOGIC;
signal cmd_push_0 : STD_LOGIC;
signal cmd_push_1 : STD_LOGIC;
signal cmd_push_2 : STD_LOGIC;
signal cmd_push_3 : STD_LOGIC;
signal cmd_push_4 : STD_LOGIC;
signal cmd_push_5 : STD_LOGIC;
signal cmd_push_6 : STD_LOGIC;
signal cmd_push_7 : STD_LOGIC;
signal f_mux4_return : STD_LOGIC_VECTOR ( 13 downto 0 );
signal \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.accept_cnt_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[0].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[1].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[2].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[3].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[4].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[5].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[6].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_id_reg\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\ : STD_LOGIC;
signal \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_14\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_16\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_17\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_18\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_19\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_20\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_21\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_22\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_23\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_24\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_25\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_26\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_27\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_28\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_29\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_30\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_31\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_32\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_33\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_34\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_35\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_36\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_37\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_38\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_39\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_40\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_41\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_42\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_43\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_44\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_45\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_46\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_47\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_48\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_49\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_50\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_51\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_52\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_53\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_54\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_55\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_56\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_57\ : STD_LOGIC;
signal \gen_multi_thread.mux_resp_multi_thread_n_58\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_10_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_11_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_12_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_13_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_14_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_18_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_19_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_3_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_4_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_5_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_7_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_8_n_0\ : STD_LOGIC;
signal \gen_no_arbiter.s_ready_i[0]_i_9_n_0\ : STD_LOGIC;
signal p_0_out : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_1\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_2\ : STD_LOGIC;
signal \p_0_out_inferred__9/i__carry_n_3\ : STD_LOGIC;
signal p_10_out : STD_LOGIC;
signal p_10_out_carry_n_1 : STD_LOGIC;
signal p_10_out_carry_n_2 : STD_LOGIC;
signal p_10_out_carry_n_3 : STD_LOGIC;
signal p_12_out : STD_LOGIC;
signal p_12_out_carry_n_1 : STD_LOGIC;
signal p_12_out_carry_n_2 : STD_LOGIC;
signal p_12_out_carry_n_3 : STD_LOGIC;
signal p_14_out : STD_LOGIC;
signal p_14_out_carry_n_1 : STD_LOGIC;
signal p_14_out_carry_n_2 : STD_LOGIC;
signal p_14_out_carry_n_3 : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal p_2_out_carry_n_1 : STD_LOGIC;
signal p_2_out_carry_n_2 : STD_LOGIC;
signal p_2_out_carry_n_3 : STD_LOGIC;
signal p_4_out : STD_LOGIC;
signal p_4_out_carry_n_1 : STD_LOGIC;
signal p_4_out_carry_n_2 : STD_LOGIC;
signal p_4_out_carry_n_3 : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_6_out_carry_n_1 : STD_LOGIC;
signal p_6_out_carry_n_2 : STD_LOGIC;
signal p_6_out_carry_n_3 : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal p_8_out_carry_n_1 : STD_LOGIC;
signal p_8_out_carry_n_2 : STD_LOGIC;
signal p_8_out_carry_n_3 : STD_LOGIC;
signal resp_select : STD_LOGIC_VECTOR ( 2 to 2 );
signal \^s_axi_bvalid\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \thread_valid_0__2\ : STD_LOGIC;
signal \thread_valid_1__2\ : STD_LOGIC;
signal \thread_valid_2__2\ : STD_LOGIC;
signal \thread_valid_3__2\ : STD_LOGIC;
signal \thread_valid_4__2\ : STD_LOGIC;
signal \thread_valid_5__2\ : STD_LOGIC;
signal \thread_valid_6__2\ : STD_LOGIC;
signal \thread_valid_7__2\ : STD_LOGIC;
signal NLW_aid_match_00_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_10_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_20_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_30_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_40_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_50_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_60_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_aid_match_70_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_10_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_12_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_14_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_2_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_4_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_6_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_p_8_out_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gen_multi_thread.accept_cnt[0]_i_1__0\ : label is "soft_lutpair177";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\ : label is "soft_lutpair169";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\ : label is "soft_lutpair166";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\ : label is "soft_lutpair167";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2\ : label is "soft_lutpair168";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3\ : label is "soft_lutpair170";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4\ : label is "soft_lutpair171";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\ : label is "soft_lutpair159";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\ : label is "soft_lutpair161";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3\ : label is "soft_lutpair172";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4\ : label is "soft_lutpair173";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\ : label is "soft_lutpair165";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\ : label is "soft_lutpair175";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\ : label is "soft_lutpair162";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2\ : label is "soft_lutpair174";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\ : label is "soft_lutpair176";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\ : label is "soft_lutpair160";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5\ : label is "soft_lutpair164";
attribute SOFT_HLUTNM of \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9\ : label is "soft_lutpair163";
attribute SOFT_HLUTNM of \gen_no_arbiter.s_ready_i[0]_i_14\ : label is "soft_lutpair177";
begin
D(0) <= \^d\(0);
SR(0) <= \^sr\(0);
s_axi_bvalid(0) <= \^s_axi_bvalid\(0);
aid_match_00_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_00,
CO(2) => aid_match_00_carry_n_1,
CO(1) => aid_match_00_carry_n_2,
CO(0) => aid_match_00_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_00_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_00_carry_i_1__0_n_0\,
S(2) => \aid_match_00_carry_i_2__0_n_0\,
S(1) => \aid_match_00_carry_i_3__0_n_0\,
S(0) => \aid_match_00_carry_i_4__0_n_0\
);
\aid_match_00_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
O => \aid_match_00_carry_i_1__0_n_0\
);
\aid_match_00_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8),
O => \aid_match_00_carry_i_2__0_n_0\
);
\aid_match_00_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
O => \aid_match_00_carry_i_3__0_n_0\
);
\aid_match_00_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
O => \aid_match_00_carry_i_4__0_n_0\
);
aid_match_10_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_10,
CO(2) => aid_match_10_carry_n_1,
CO(1) => aid_match_10_carry_n_2,
CO(0) => aid_match_10_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_10_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_10_carry_i_1__0_n_0\,
S(2) => \aid_match_10_carry_i_2__0_n_0\,
S(1) => \aid_match_10_carry_i_3__0_n_0\,
S(0) => \aid_match_10_carry_i_4__0_n_0\
);
\aid_match_10_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
I5 => \s_axi_awid[11]\(11),
O => \aid_match_10_carry_i_1__0_n_0\
);
\aid_match_10_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(6),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8),
I5 => \s_axi_awid[11]\(8),
O => \aid_match_10_carry_i_2__0_n_0\
);
\aid_match_10_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
I5 => \s_axi_awid[11]\(5),
O => \aid_match_10_carry_i_3__0_n_0\
);
\aid_match_10_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
I4 => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
I5 => \s_axi_awid[11]\(2),
O => \aid_match_10_carry_i_4__0_n_0\
);
aid_match_20_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_20,
CO(2) => aid_match_20_carry_n_1,
CO(1) => aid_match_20_carry_n_2,
CO(0) => aid_match_20_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_20_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_20_carry_i_1__0_n_0\,
S(2) => \aid_match_20_carry_i_2__0_n_0\,
S(1) => \aid_match_20_carry_i_3__0_n_0\,
S(0) => \aid_match_20_carry_i_4__0_n_0\
);
\aid_match_20_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
O => \aid_match_20_carry_i_1__0_n_0\
);
\aid_match_20_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8),
O => \aid_match_20_carry_i_2__0_n_0\
);
\aid_match_20_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
O => \aid_match_20_carry_i_3__0_n_0\
);
\aid_match_20_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
O => \aid_match_20_carry_i_4__0_n_0\
);
aid_match_30_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_30,
CO(2) => aid_match_30_carry_n_1,
CO(1) => aid_match_30_carry_n_2,
CO(0) => aid_match_30_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_30_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_30_carry_i_1__0_n_0\,
S(2) => \aid_match_30_carry_i_2__0_n_0\,
S(1) => \aid_match_30_carry_i_3__0_n_0\,
S(0) => \aid_match_30_carry_i_4__0_n_0\
);
\aid_match_30_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
O => \aid_match_30_carry_i_1__0_n_0\
);
\aid_match_30_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8),
O => \aid_match_30_carry_i_2__0_n_0\
);
\aid_match_30_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
O => \aid_match_30_carry_i_3__0_n_0\
);
\aid_match_30_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
O => \aid_match_30_carry_i_4__0_n_0\
);
aid_match_40_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_40,
CO(2) => aid_match_40_carry_n_1,
CO(1) => aid_match_40_carry_n_2,
CO(0) => aid_match_40_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_40_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_40_carry_i_1__0_n_0\,
S(2) => \aid_match_40_carry_i_2__0_n_0\,
S(1) => \aid_match_40_carry_i_3__0_n_0\,
S(0) => \aid_match_40_carry_i_4__0_n_0\
);
\aid_match_40_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
O => \aid_match_40_carry_i_1__0_n_0\
);
\aid_match_40_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8),
O => \aid_match_40_carry_i_2__0_n_0\
);
\aid_match_40_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
O => \aid_match_40_carry_i_3__0_n_0\
);
\aid_match_40_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
O => \aid_match_40_carry_i_4__0_n_0\
);
aid_match_50_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_50,
CO(2) => aid_match_50_carry_n_1,
CO(1) => aid_match_50_carry_n_2,
CO(0) => aid_match_50_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_50_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_50_carry_i_1__0_n_0\,
S(2) => \aid_match_50_carry_i_2__0_n_0\,
S(1) => \aid_match_50_carry_i_3__0_n_0\,
S(0) => \aid_match_50_carry_i_4__0_n_0\
);
\aid_match_50_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
O => \aid_match_50_carry_i_1__0_n_0\
);
\aid_match_50_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8),
O => \aid_match_50_carry_i_2__0_n_0\
);
\aid_match_50_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
O => \aid_match_50_carry_i_3__0_n_0\
);
\aid_match_50_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
O => \aid_match_50_carry_i_4__0_n_0\
);
aid_match_60_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_60,
CO(2) => aid_match_60_carry_n_1,
CO(1) => aid_match_60_carry_n_2,
CO(0) => aid_match_60_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_60_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_60_carry_i_1__0_n_0\,
S(2) => \aid_match_60_carry_i_2__0_n_0\,
S(1) => \aid_match_60_carry_i_3__0_n_0\,
S(0) => \aid_match_60_carry_i_4__0_n_0\
);
\aid_match_60_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
O => \aid_match_60_carry_i_1__0_n_0\
);
\aid_match_60_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8),
O => \aid_match_60_carry_i_2__0_n_0\
);
\aid_match_60_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
O => \aid_match_60_carry_i_3__0_n_0\
);
\aid_match_60_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
O => \aid_match_60_carry_i_4__0_n_0\
);
aid_match_70_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => aid_match_70,
CO(2) => aid_match_70_carry_n_1,
CO(1) => aid_match_70_carry_n_2,
CO(0) => aid_match_70_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_aid_match_70_carry_O_UNCONNECTED(3 downto 0),
S(3) => \aid_match_70_carry_i_1__0_n_0\,
S(2) => \aid_match_70_carry_i_2__0_n_0\,
S(1) => \aid_match_70_carry_i_3__0_n_0\,
S(0) => \aid_match_70_carry_i_4__0_n_0\
);
\aid_match_70_carry_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(10),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
I2 => \s_axi_awid[11]\(9),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
I4 => \s_axi_awid[11]\(11),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
O => \aid_match_70_carry_i_1__0_n_0\
);
\aid_match_70_carry_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(7),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(7),
I2 => \s_axi_awid[11]\(6),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(6),
I4 => \s_axi_awid[11]\(8),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8),
O => \aid_match_70_carry_i_2__0_n_0\
);
\aid_match_70_carry_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(4),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
I2 => \s_axi_awid[11]\(3),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
I4 => \s_axi_awid[11]\(5),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
O => \aid_match_70_carry_i_3__0_n_0\
);
\aid_match_70_carry_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \s_axi_awid[11]\(1),
I1 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
I2 => \s_axi_awid[11]\(0),
I3 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
I4 => \s_axi_awid[11]\(2),
I5 => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
O => \aid_match_70_carry_i_4__0_n_0\
);
\gen_multi_thread.accept_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
O => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.accept_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.accept_cnt[0]_i_1__0_n_0\,
Q => \gen_multi_thread.accept_cnt_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_26\,
Q => \gen_multi_thread.accept_cnt_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_25\,
Q => \gen_multi_thread.accept_cnt_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.accept_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_23\,
D => \gen_multi_thread.mux_resp_multi_thread_n_24\,
Q => \gen_multi_thread.accept_cnt_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.arbiter_resp_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp
port map (
ADDRESS_HIT_0 => ADDRESS_HIT_0,
ADDRESS_HIT_1 => ADDRESS_HIT_1,
ADDRESS_HIT_3 => ADDRESS_HIT_3,
E(0) => E(0),
Q(0) => \gen_multi_thread.accept_cnt_reg\(3),
SR(0) => \^sr\(0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
\any_pop__1\ => \any_pop__1\,
aresetn_d => aresetn_d,
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => \gen_master_slots[0].w_issuing_cnt_reg[0]\(0),
\gen_master_slots[2].w_issuing_cnt_reg[16]\(0) => \gen_master_slots[2].w_issuing_cnt_reg[16]\(0),
\gen_master_slots[2].w_issuing_cnt_reg[18]\ => \gen_master_slots[2].w_issuing_cnt_reg[18]\,
\gen_master_slots[3].w_issuing_cnt_reg[24]\(0) => \gen_master_slots[3].w_issuing_cnt_reg[24]\(0),
\gen_multi_thread.accept_cnt_reg[0]\ => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\,
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\ => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\,
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\ => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\,
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\ => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\ => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\,
\gen_no_arbiter.s_ready_i_reg[0]\(0) => \gen_no_arbiter.s_ready_i_reg[0]\(0),
\gen_no_arbiter.s_ready_i_reg[0]_0\ => \gen_no_arbiter.s_ready_i_reg[0]_0\,
m_valid_i => m_valid_i,
m_valid_i_reg => m_valid_i_reg,
m_valid_i_reg_0 => m_valid_i_reg_0,
match => match,
p_101_in => p_101_in,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_68_out => p_68_out,
p_84_in => p_84_in,
p_88_out => p_88_out,
resp_select(0) => resp_select(2),
\s_axi_awaddr[25]\ => \s_axi_awaddr[25]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bvalid(0) => \^s_axi_bvalid\(0),
s_ready_i_reg(4 downto 0) => Q(4 downto 0),
sel_2 => sel_2,
sel_4 => sel_4,
st_mr_bid(47 downto 0) => st_mr_bid(47 downto 0),
st_mr_bmesg(7 downto 0) => st_mr_bmesg(7 downto 0),
w_issuing_cnt(16 downto 0) => w_issuing_cnt(16 downto 0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(0),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(0),
I1 => cmd_push_0,
I2 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_0,
I1 => active_cnt(0),
I2 => active_cnt(2),
I3 => active_cnt(1),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(1),
I1 => cmd_push_0,
I2 => active_cnt(0),
I3 => active_cnt(3),
I4 => active_cnt(2),
O => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_14\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0\,
Q => active_cnt(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_14\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0\,
Q => active_cnt(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_14\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0\,
Q => active_cnt(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_14\,
D => \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0\,
Q => active_cnt(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_id_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E222"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => aid_match_00,
I3 => \m_ready_d_reg[1]\,
O => cmd_push_0
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => st_aa_awtarget_enc(0),
Q => active_target(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => st_aa_awtarget_enc(1),
Q => active_target(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[0].active_target_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_0,
D => \^d\(0),
Q => active_target(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_1,
I1 => active_cnt(8),
I2 => active_cnt(10),
I3 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(9),
I1 => cmd_push_1,
I2 => active_cnt(8),
I3 => active_cnt(11),
I4 => active_cnt(10),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(8),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(8),
I1 => cmd_push_1,
I2 => active_cnt(9),
O => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0\,
Q => active_cnt(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0\,
Q => active_cnt(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0\,
Q => active_cnt(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_22\,
D => \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0\,
Q => active_cnt(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F8080808"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => aid_match_10,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_1
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => \^d\(0),
Q => active_target(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => st_aa_awtarget_enc(0),
Q => active_target(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[1].active_target_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_1,
D => st_aa_awtarget_enc(1),
Q => active_target(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(16),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(16),
I1 => cmd_push_2,
I2 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_2,
I1 => active_cnt(16),
I2 => active_cnt(18),
I3 => active_cnt(17),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(17),
I1 => cmd_push_2,
I2 => active_cnt(16),
I3 => active_cnt(19),
I4 => active_cnt(18),
O => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0\,
Q => active_cnt(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0\,
Q => active_cnt(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0\,
Q => active_cnt(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_21\,
D => \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0\,
Q => active_cnt(19),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80008000800080"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I1 => \thread_valid_0__2\,
I2 => \thread_valid_1__2\,
I3 => \thread_valid_2__2\,
I4 => aid_match_20,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_2
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(2),
I1 => active_cnt(3),
I2 => active_cnt(1),
I3 => active_cnt(0),
O => \thread_valid_0__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(10),
I1 => active_cnt(11),
I2 => active_cnt(9),
I3 => active_cnt(8),
O => \thread_valid_1__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target[18]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(18),
I1 => active_cnt(19),
I2 => active_cnt(17),
I3 => active_cnt(16),
O => \thread_valid_2__2\
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => st_aa_awtarget_enc(0),
Q => active_target(16),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => st_aa_awtarget_enc(1),
Q => active_target(17),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[2].active_target_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_2,
D => \^d\(0),
Q => active_target(18),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(24),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(24),
I1 => cmd_push_3,
I2 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_3,
I1 => active_cnt(24),
I2 => active_cnt(26),
I3 => active_cnt(25),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(25),
I1 => cmd_push_3,
I2 => active_cnt(24),
I3 => active_cnt(27),
I4 => active_cnt(26),
O => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0\,
Q => active_cnt(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0\,
Q => active_cnt(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0\,
Q => active_cnt(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_16\,
D => \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0\,
Q => active_cnt(27),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I2 => \thread_valid_3__2\,
I3 => aid_match_30,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_3
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => st_aa_awtarget_enc(0),
Q => active_target(24),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => st_aa_awtarget_enc(1),
Q => active_target(25),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[3].active_target_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_3,
D => \^d\(0),
Q => active_target(26),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(32),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(32),
I1 => cmd_push_4,
I2 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_4,
I1 => active_cnt(32),
I2 => active_cnt(34),
I3 => active_cnt(33),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(33),
I1 => cmd_push_4,
I2 => active_cnt(32),
I3 => active_cnt(35),
I4 => active_cnt(34),
O => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0\,
Q => active_cnt(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0\,
Q => active_cnt(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0\,
Q => active_cnt(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_17\,
D => \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0\,
Q => active_cnt(35),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[52]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
I1 => \thread_valid_3__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \thread_valid_4__2\,
I4 => aid_match_40,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_4
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"55555557FFFFFFFF"
)
port map (
I0 => \thread_valid_0__2\,
I1 => active_cnt(10),
I2 => active_cnt(11),
I3 => active_cnt(9),
I4 => active_cnt(8),
I5 => \thread_valid_2__2\,
O => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(26),
I1 => active_cnt(27),
I2 => active_cnt(25),
I3 => active_cnt(24),
O => \thread_valid_3__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target[34]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(34),
I1 => active_cnt(35),
I2 => active_cnt(33),
I3 => active_cnt(32),
O => \thread_valid_4__2\
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => st_aa_awtarget_enc(0),
Q => active_target(32),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => st_aa_awtarget_enc(1),
Q => active_target(33),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[4].active_target_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_4,
D => \^d\(0),
Q => active_target(34),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(40),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(40),
I1 => cmd_push_5,
I2 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_5,
I1 => active_cnt(40),
I2 => active_cnt(42),
I3 => active_cnt(41),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(41),
I1 => cmd_push_5,
I2 => active_cnt(40),
I3 => active_cnt(43),
I4 => active_cnt(42),
O => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0\,
Q => active_cnt(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0\,
Q => active_cnt(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0\,
Q => active_cnt(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_20\,
D => \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0\,
Q => active_cnt(43),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[65]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[66]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[69]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target[42]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F4040404"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I2 => \thread_valid_5__2\,
I3 => aid_match_50,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_5
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => st_aa_awtarget_enc(0),
Q => active_target(40),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => st_aa_awtarget_enc(1),
Q => active_target(41),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[5].active_target_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_5,
D => \^d\(0),
Q => active_target(42),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(48),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(48),
I1 => cmd_push_6,
I2 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_6,
I1 => active_cnt(48),
I2 => active_cnt(50),
I3 => active_cnt(49),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(49),
I1 => cmd_push_6,
I2 => active_cnt(48),
I3 => active_cnt(51),
I4 => active_cnt(50),
O => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0\,
Q => active_cnt(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0\,
Q => active_cnt(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0\,
Q => active_cnt(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_19\,
D => \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0\,
Q => active_cnt(51),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[72]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[73]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[74]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[75]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[76]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[77]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[78]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[81]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF40004000400040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \thread_valid_5__2\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \thread_valid_6__2\,
I4 => aid_match_60,
I5 => \m_ready_d_reg[1]\,
O => cmd_push_6
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(42),
I1 => active_cnt(43),
I2 => active_cnt(41),
I3 => active_cnt(40),
O => \thread_valid_5__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target[50]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(50),
I1 => active_cnt(51),
I2 => active_cnt(49),
I3 => active_cnt(48),
O => \thread_valid_6__2\
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => st_aa_awtarget_enc(0),
Q => active_target(48),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => st_aa_awtarget_enc(1),
Q => active_target(49),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[6].active_target_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_6,
D => \^d\(0),
Q => active_target(50),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => active_cnt(56),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => active_cnt(56),
I1 => cmd_push_7,
I2 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"78E1"
)
port map (
I0 => cmd_push_7,
I1 => active_cnt(56),
I2 => active_cnt(58),
I3 => active_cnt(57),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"7F80FE01"
)
port map (
I0 => active_cnt(57),
I1 => cmd_push_7,
I2 => active_cnt(56),
I3 => active_cnt(59),
I4 => active_cnt(58),
O => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
O => \thread_valid_7__2\
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0\,
Q => active_cnt(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0\,
Q => active_cnt(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0\,
Q => active_cnt(58),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \gen_multi_thread.mux_resp_multi_thread_n_18\,
D => \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0\,
Q => active_cnt(59),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[84]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(0),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(0),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[85]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(1),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(1),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[86]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(2),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(2),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[87]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(3),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(3),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[88]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(4),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(4),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[89]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(5),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(5),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[90]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(6),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(6),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(7),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(7),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(8),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(8),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[93]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(9),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(9),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(10),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(10),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \s_axi_awid[11]\(11),
Q => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF404040"
)
port map (
I0 => \accum_push_5__0\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\,
I3 => \aid_match_7__0\,
I4 => \m_ready_d_reg[1]\,
O => cmd_push_7
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF55555557"
)
port map (
I0 => \thread_valid_3__2\,
I1 => active_cnt(34),
I2 => active_cnt(35),
I3 => active_cnt(33),
I4 => active_cnt(32),
I5 => \gen_multi_thread.gen_thread_loop[4].active_target[34]_i_2_n_0\,
O => \accum_push_5__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0001000000000000"
)
port map (
I0 => active_cnt(58),
I1 => active_cnt(59),
I2 => active_cnt(57),
I3 => active_cnt(56),
I4 => \thread_valid_6__2\,
I5 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_3_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000002"
)
port map (
I0 => \m_ready_d_reg[1]\,
I1 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\,
I2 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\,
I3 => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\,
I4 => \aid_match_6__0\,
I5 => \aid_match_7__0\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_4_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(56),
I1 => active_cnt(57),
I2 => active_cnt(59),
I3 => active_cnt(58),
I4 => aid_match_70,
O => \aid_match_7__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_00,
I1 => \thread_valid_0__2\,
I2 => aid_match_10,
I3 => \thread_valid_1__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_6_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_20,
I1 => \thread_valid_2__2\,
I2 => aid_match_30,
I3 => \thread_valid_3__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_7_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => aid_match_40,
I1 => \thread_valid_4__2\,
I2 => aid_match_50,
I3 => \thread_valid_5__2\,
O => \gen_multi_thread.gen_thread_loop[7].active_target[58]_i_8_n_0\
);
\gen_multi_thread.gen_thread_loop[7].active_target[58]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFE0000"
)
port map (
I0 => active_cnt(48),
I1 => active_cnt(49),
I2 => active_cnt(51),
I3 => active_cnt(50),
I4 => aid_match_60,
O => \aid_match_6__0\
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => st_aa_awtarget_enc(0),
Q => active_target(56),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => st_aa_awtarget_enc(1),
Q => active_target(57),
R => \^sr\(0)
);
\gen_multi_thread.gen_thread_loop[7].active_target_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => cmd_push_7,
D => \^d\(0),
Q => active_target(58),
R => \^sr\(0)
);
\gen_multi_thread.mux_resp_multi_thread\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_generic_baseblocks_v2_1_0_mux_enc__parameterized0\
port map (
CO(0) => p_14_out,
D(2) => \gen_multi_thread.mux_resp_multi_thread_n_24\,
D(1) => \gen_multi_thread.mux_resp_multi_thread_n_25\,
D(0) => \gen_multi_thread.mux_resp_multi_thread_n_26\,
E(0) => \gen_multi_thread.mux_resp_multi_thread_n_14\,
Q(3 downto 0) => \gen_multi_thread.accept_cnt_reg\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_27\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_28\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_29\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_30\,
\any_pop__1\ => \any_pop__1\,
cmd_push_0 => cmd_push_0,
cmd_push_1 => cmd_push_1,
cmd_push_2 => cmd_push_2,
cmd_push_3 => cmd_push_3,
cmd_push_4 => cmd_push_4,
cmd_push_5 => cmd_push_5,
cmd_push_6 => cmd_push_6,
cmd_push_7 => cmd_push_7,
f_mux4_return(13 downto 0) => f_mux4_return(13 downto 0),
\gen_multi_thread.accept_cnt_reg[3]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_23\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(3) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[0].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_22\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22]\(0) => p_12_out,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[1].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_21\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34]\(0) => p_10_out,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[2].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_16\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_43\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_44\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_45\,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_46\,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46]\(0) => p_8_out,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[3].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_17\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_39\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_40\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_41\,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_42\,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58]\(0) => p_6_out,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[4].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_20\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_35\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_36\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_37\,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_38\,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70]\(0) => p_4_out,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[5].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_19\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(3) => \gen_multi_thread.mux_resp_multi_thread_n_31\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(2) => \gen_multi_thread.mux_resp_multi_thread_n_32\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(1) => \gen_multi_thread.mux_resp_multi_thread_n_33\,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0\(0) => \gen_multi_thread.mux_resp_multi_thread_n_34\,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82]\(0) => p_2_out,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[6].active_id_reg\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => \gen_multi_thread.mux_resp_multi_thread_n_18\,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94]\(0) => p_0_out,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_id_reg\(11 downto 0),
\m_ready_d_reg[1]\ => \m_ready_d_reg[1]\,
resp_select(0) => resp_select(2),
\s_axi_bid[0]\ => \s_axi_bid[0]\,
\s_axi_bid[10]\ => \s_axi_bid[10]\,
\s_axi_bid[11]\ => \s_axi_bid[11]\,
\s_axi_bid[1]\ => \s_axi_bid[1]\,
\s_axi_bid[2]\ => \s_axi_bid[2]\,
\s_axi_bid[3]\ => \s_axi_bid[3]\,
\s_axi_bid[4]\ => \s_axi_bid[4]\,
\s_axi_bid[5]\ => \s_axi_bid[5]\,
\s_axi_bid[6]\ => \s_axi_bid[6]\,
\s_axi_bid[7]\ => \s_axi_bid[7]\,
\s_axi_bid[8]\ => \s_axi_bid[8]\,
\s_axi_bid[9]\ => \s_axi_bid[9]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => \^s_axi_bvalid\(0),
st_mr_bid(11 downto 0) => st_mr_bid(59 downto 48),
\thread_valid_0__2\ => \thread_valid_0__2\,
\thread_valid_1__2\ => \thread_valid_1__2\,
\thread_valid_2__2\ => \thread_valid_2__2\,
\thread_valid_3__2\ => \thread_valid_3__2\,
\thread_valid_4__2\ => \thread_valid_4__2\,
\thread_valid_5__2\ => \thread_valid_5__2\,
\thread_valid_6__2\ => \thread_valid_6__2\,
\thread_valid_7__2\ => \thread_valid_7__2\
);
\gen_no_arbiter.m_target_hot_i[4]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => match,
O => \^d\(0)
);
\gen_no_arbiter.s_ready_i[0]_i_10\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(8),
I1 => st_aa_awtarget_enc(0),
I2 => active_target(9),
I3 => st_aa_awtarget_enc(1),
I4 => match,
I5 => active_target(10),
O => \gen_no_arbiter.s_ready_i[0]_i_10_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_11\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(0),
I1 => st_aa_awtarget_enc(0),
I2 => active_target(1),
I3 => st_aa_awtarget_enc(1),
I4 => match,
I5 => active_target(2),
O => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_12\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(48),
I1 => st_aa_awtarget_enc(0),
I2 => active_target(49),
I3 => st_aa_awtarget_enc(1),
I4 => match,
I5 => active_target(50),
O => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_13\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(56),
I1 => st_aa_awtarget_enc(0),
I2 => active_target(57),
I3 => st_aa_awtarget_enc(1),
I4 => match,
I5 => active_target(58),
O => \gen_no_arbiter.s_ready_i[0]_i_13_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => \gen_multi_thread.accept_cnt_reg\(0),
I1 => \gen_multi_thread.accept_cnt_reg\(2),
I2 => \gen_multi_thread.accept_cnt_reg\(1),
O => \gen_no_arbiter.s_ready_i[0]_i_14_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(40),
I1 => st_aa_awtarget_enc(0),
I2 => active_target(41),
I3 => st_aa_awtarget_enc(1),
I4 => match,
I5 => active_target(42),
O => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_19\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(32),
I1 => st_aa_awtarget_enc(0),
I2 => active_target(33),
I3 => st_aa_awtarget_enc(1),
I4 => match,
I5 => active_target(34),
O => \gen_no_arbiter.s_ready_i[0]_i_19_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\,
I1 => \thread_valid_3__2\,
I2 => aid_match_30,
I3 => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\,
I4 => \thread_valid_2__2\,
I5 => aid_match_20,
O => \gen_no_arbiter.s_ready_i[0]_i_3_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_10_n_0\,
I1 => \thread_valid_1__2\,
I2 => aid_match_10,
I3 => \gen_no_arbiter.s_ready_i[0]_i_11_n_0\,
I4 => \thread_valid_0__2\,
I5 => aid_match_00,
O => \gen_no_arbiter.s_ready_i[0]_i_4_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF808080"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_12_n_0\,
I1 => \thread_valid_6__2\,
I2 => aid_match_60,
I3 => \gen_no_arbiter.s_ready_i[0]_i_13_n_0\,
I4 => \aid_match_7__0\,
O => \gen_no_arbiter.s_ready_i[0]_i_5_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \gen_no_arbiter.s_ready_i[0]_i_18_n_0\,
I1 => \thread_valid_5__2\,
I2 => aid_match_50,
I3 => \gen_no_arbiter.s_ready_i[0]_i_19_n_0\,
I4 => \thread_valid_4__2\,
I5 => aid_match_40,
O => \gen_no_arbiter.s_ready_i[0]_i_7_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(24),
I1 => st_aa_awtarget_enc(0),
I2 => active_target(25),
I3 => st_aa_awtarget_enc(1),
I4 => match,
I5 => active_target(26),
O => \gen_no_arbiter.s_ready_i[0]_i_8_n_0\
);
\gen_no_arbiter.s_ready_i[0]_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF6FF66FF6FFFF"
)
port map (
I0 => active_target(16),
I1 => st_aa_awtarget_enc(0),
I2 => active_target(17),
I3 => st_aa_awtarget_enc(1),
I4 => match,
I5 => active_target(18),
O => \gen_no_arbiter.s_ready_i[0]_i_9_n_0\
);
\p_0_out_inferred__9/i__carry\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_0_out,
CO(2) => \p_0_out_inferred__9/i__carry_n_1\,
CO(1) => \p_0_out_inferred__9/i__carry_n_2\,
CO(0) => \p_0_out_inferred__9/i__carry_n_3\,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED\(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_27\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_28\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_29\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_30\
);
p_10_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_10_out,
CO(2) => p_10_out_carry_n_1,
CO(1) => p_10_out_carry_n_2,
CO(0) => p_10_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_10_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_47\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_48\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_49\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_50\
);
p_12_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_12_out,
CO(2) => p_12_out_carry_n_1,
CO(1) => p_12_out_carry_n_2,
CO(0) => p_12_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_12_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_51\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_52\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_53\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_54\
);
p_14_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_14_out,
CO(2) => p_14_out_carry_n_1,
CO(1) => p_14_out_carry_n_2,
CO(0) => p_14_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_14_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_55\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_56\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_57\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_58\
);
p_2_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_2_out,
CO(2) => p_2_out_carry_n_1,
CO(1) => p_2_out_carry_n_2,
CO(0) => p_2_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_2_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_31\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_32\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_33\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_34\
);
p_4_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_4_out,
CO(2) => p_4_out_carry_n_1,
CO(1) => p_4_out_carry_n_2,
CO(0) => p_4_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_4_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_35\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_36\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_37\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_38\
);
p_6_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_6_out,
CO(2) => p_6_out_carry_n_1,
CO(1) => p_6_out_carry_n_2,
CO(0) => p_6_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_6_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_39\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_40\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_41\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_42\
);
p_8_out_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => p_8_out,
CO(2) => p_8_out_carry_n_1,
CO(1) => p_8_out_carry_n_2,
CO(0) => p_8_out_carry_n_3,
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => NLW_p_8_out_carry_O_UNCONNECTED(3 downto 0),
S(3) => \gen_multi_thread.mux_resp_multi_thread_n_43\,
S(2) => \gen_multi_thread.mux_resp_multi_thread_n_44\,
S(1) => \gen_multi_thread.mux_resp_multi_thread_n_45\,
S(0) => \gen_multi_thread.mux_resp_multi_thread_n_46\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\write_cs0__0\ : out STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
match : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo is
signal \/FSM_onehot_state[1]_i_1_n_0\ : STD_LOGIC;
signal \/FSM_onehot_state[2]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[0]_i_1_n_0\ : STD_LOGIC;
signal \FSM_onehot_state[3]_i_2_n_0\ : STD_LOGIC;
signal \FSM_onehot_state_reg_n_0_[2]\ : STD_LOGIC;
attribute RTL_KEEP : string;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[2]\ : signal is "yes";
signal \FSM_onehot_state_reg_n_0_[3]\ : STD_LOGIC;
attribute RTL_KEEP of \FSM_onehot_state_reg_n_0_[3]\ : signal is "yes";
signal areset_d1 : STD_LOGIC;
signal fifoaddr : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gen_rep[0].fifoaddr[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[1]_i_1_n_0\ : STD_LOGIC;
signal \gen_rep[0].fifoaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[0].srl_nx1_n_0\ : STD_LOGIC;
signal \gen_srls[0].gen_rep[2].srl_nx1_n_1\ : STD_LOGIC;
signal load_s1 : STD_LOGIC;
signal \m_aready0__3\ : STD_LOGIC;
signal \m_aready__1\ : STD_LOGIC;
signal m_avalid : STD_LOGIC;
signal m_select_enc : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \m_valid_i__0\ : STD_LOGIC;
signal m_valid_i_n_0 : STD_LOGIC;
signal p_0_in5_out : STD_LOGIC;
signal p_0_in8_in : STD_LOGIC;
attribute RTL_KEEP of p_0_in8_in : signal is "yes";
signal p_2_out : STD_LOGIC;
signal p_9_in : STD_LOGIC;
attribute RTL_KEEP of p_9_in : signal is "yes";
signal push : STD_LOGIC;
signal \s_ready_i1__4\ : STD_LOGIC;
signal \s_ready_i_i_1__9_n_0\ : STD_LOGIC;
signal \^ss_wr_awready\ : STD_LOGIC;
signal \storage_data1[0]_i_1_n_0\ : STD_LOGIC;
signal \storage_data1[1]_i_1_n_0\ : STD_LOGIC;
attribute KEEP : string;
attribute KEEP of \FSM_onehot_state_reg[0]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[1]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[2]\ : label is "yes";
attribute KEEP of \FSM_onehot_state_reg[3]\ : label is "yes";
attribute syn_keep : string;
attribute syn_keep of \gen_rep[0].fifoaddr_reg[0]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[1]\ : label is "1";
attribute syn_keep of \gen_rep[0].fifoaddr_reg[2]\ : label is "1";
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_axi_wvalid[0]_INST_0\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \m_axi_wvalid[1]_INST_0\ : label is "soft_lutpair179";
attribute SOFT_HLUTNM of \m_axi_wvalid[2]_INST_0\ : label is "soft_lutpair180";
attribute SOFT_HLUTNM of \m_axi_wvalid[3]_INST_0\ : label is "soft_lutpair180";
begin
ss_wr_awready <= \^ss_wr_awready\;
\/FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"20202F20"
)
port map (
I0 => s_axi_awvalid(0),
I1 => m_ready_d(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[1]_i_1_n_0\
);
\/FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0B0B0BF"
)
port map (
I0 => m_ready_d(0),
I1 => s_axi_awvalid(0),
I2 => p_9_in,
I3 => p_0_in5_out,
I4 => p_0_in8_in,
O => \/FSM_onehot_state[2]_i_1_n_0\
);
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"008A0000"
)
port map (
I0 => \m_aready__1\,
I1 => m_ready_d(0),
I2 => s_axi_awvalid(0),
I3 => p_9_in,
I4 => p_0_in8_in,
O => \FSM_onehot_state[0]_i_1_n_0\
);
\FSM_onehot_state[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF488F488F488"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => \m_valid_i__0\
);
\FSM_onehot_state[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"00007500"
)
port map (
I0 => \m_aready__1\,
I1 => m_ready_d(0),
I2 => s_axi_awvalid(0),
I3 => p_0_in8_in,
I4 => p_9_in,
O => \FSM_onehot_state[3]_i_2_n_0\
);
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[0]_i_1_n_0\,
Q => p_9_in,
S => areset_d1
);
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \/FSM_onehot_state[1]_i_1_n_0\,
Q => p_0_in8_in,
R => areset_d1
);
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \/FSM_onehot_state[2]_i_1_n_0\,
Q => \FSM_onehot_state_reg_n_0_[2]\,
R => areset_d1
);
\FSM_onehot_state_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => \FSM_onehot_state[3]_i_2_n_0\,
Q => \FSM_onehot_state_reg_n_0_[3]\,
R => areset_d1
);
areset_d1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => SR(0),
Q => areset_d1,
R => '0'
);
\gen_axi.write_cs[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000800000"
)
port map (
I0 => s_axi_wlast(0),
I1 => m_avalid,
I2 => s_axi_wvalid(0),
I3 => m_select_enc(0),
I4 => m_select_enc(2),
I5 => m_select_enc(1),
O => \write_cs0__0\
);
\gen_rep[0].fifoaddr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8778"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => push,
I3 => fifoaddr(0),
O => \gen_rep[0].fifoaddr[0]_i_1_n_0\
);
\gen_rep[0].fifoaddr[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8FF77008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(0),
I3 => push,
I4 => fifoaddr(1),
O => \gen_rep[0].fifoaddr[1]_i_1_n_0\
);
\gen_rep[0].fifoaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"8FFFFFF770000008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(0),
I3 => fifoaddr(1),
I4 => push,
I5 => fifoaddr(2),
O => \gen_rep[0].fifoaddr[2]_i_1_n_0\
);
\gen_rep[0].fifoaddr_reg[0]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[0]_i_1_n_0\,
Q => fifoaddr(0),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[1]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[1]_i_1_n_0\,
Q => fifoaddr(1),
S => SR(0)
);
\gen_rep[0].fifoaddr_reg[2]\: unisim.vcomponents.FDSE
port map (
C => aclk,
CE => '1',
D => \gen_rep[0].fifoaddr[2]_i_1_n_0\,
Q => fifoaddr(2),
S => SR(0)
);
\gen_srls[0].gen_rep[0].srl_nx1\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0\
port map (
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
push => push,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(0),
\storage_data1_reg[0]\ => \gen_srls[0].gen_rep[0].srl_nx1_n_0\
);
\gen_srls[0].gen_rep[1].srl_nx1\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_6\
port map (
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
p_2_out => p_2_out,
push => push,
st_aa_awtarget_enc(0) => st_aa_awtarget_enc(1)
);
\gen_srls[0].gen_rep[2].srl_nx1\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_7\
port map (
D(0) => D(0),
aclk => aclk,
fifoaddr(2 downto 0) => fifoaddr(2 downto 0),
load_s1 => load_s1,
\m_aready0__3\ => \m_aready0__3\,
\m_aready__1\ => \m_aready__1\,
m_avalid => m_avalid,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_ready_d(0) => m_ready_d(0),
m_select_enc(2 downto 0) => m_select_enc(2 downto 0),
match => match,
out0(1) => p_0_in8_in,
out0(0) => \FSM_onehot_state_reg_n_0_[3]\,
p_22_in => p_22_in,
push => push,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => \^ss_wr_awready\,
\storage_data1_reg[2]\ => \gen_srls[0].gen_rep[2].srl_nx1_n_1\
);
\m_axi_wvalid[0]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000008"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(0)
);
\m_axi_wvalid[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000080"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(1)
);
\m_axi_wvalid[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000800"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(2)
);
\m_axi_wvalid[3]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"00008000"
)
port map (
I0 => s_axi_wvalid(0),
I1 => m_avalid,
I2 => m_select_enc(0),
I3 => m_select_enc(1),
I4 => m_select_enc(2),
O => m_axi_wvalid(3)
);
m_valid_i: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFF400F400F400"
)
port map (
I0 => \m_aready__1\,
I1 => p_0_in8_in,
I2 => p_9_in,
I3 => ss_wr_awvalid,
I4 => \FSM_onehot_state_reg_n_0_[3]\,
I5 => p_0_in5_out,
O => m_valid_i_n_0
);
m_valid_i_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000008"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(1),
I3 => fifoaddr(0),
I4 => fifoaddr(2),
I5 => push,
O => p_0_in5_out
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => \m_valid_i__0\,
D => m_valid_i_n_0,
Q => m_avalid,
R => areset_d1
);
\s_axi_wready[0]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => m_avalid,
I1 => \m_aready0__3\,
O => s_axi_wready(0)
);
\s_ready_i_i_1__9\: unisim.vcomponents.LUT5
generic map(
INIT => X"F0FFF0F8"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => areset_d1,
I3 => \s_ready_i1__4\,
I4 => \^ss_wr_awready\,
O => \s_ready_i_i_1__9_n_0\
);
\s_ready_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000700000000000"
)
port map (
I0 => \m_aready__1\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => fifoaddr(2),
I3 => fifoaddr(1),
I4 => fifoaddr(0),
I5 => push,
O => \s_ready_i1__4\
);
s_ready_i_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__9_n_0\,
Q => \^ss_wr_awready\,
R => SR(0)
);
\storage_data1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \gen_srls[0].gen_rep[0].srl_nx1_n_0\,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => st_aa_awtarget_enc(0),
I3 => load_s1,
I4 => m_select_enc(0),
O => \storage_data1[0]_i_1_n_0\
);
\storage_data1[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => p_2_out,
I1 => \FSM_onehot_state_reg_n_0_[3]\,
I2 => st_aa_awtarget_enc(1),
I3 => load_s1,
I4 => m_select_enc(1),
O => \storage_data1[1]_i_1_n_0\
);
\storage_data1[2]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0FCA0A0A0ECA0A0"
)
port map (
I0 => \FSM_onehot_state_reg_n_0_[3]\,
I1 => p_9_in,
I2 => \m_aready__1\,
I3 => m_ready_d(0),
I4 => s_axi_awvalid(0),
I5 => p_0_in8_in,
O => load_s1
);
\storage_data1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \storage_data1[0]_i_1_n_0\,
Q => m_select_enc(0),
R => '0'
);
\storage_data1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \storage_data1[1]_i_1_n_0\,
Q => m_select_enc(1),
R => '0'
);
\storage_data1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \gen_srls[0].gen_rep[2].srl_nx1_n_1\,
Q => m_select_enc(2),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
port (
p_128_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_122_out : out STD_LOGIC;
\m_axi_rready[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_0__1\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[2]\ : out STD_LOGIC;
\chosen_reg[2]_0\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[0].r_issuing_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_93_in : in STD_LOGIC;
p_102_out : in STD_LOGIC;
p_108_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[0]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
begin
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_15\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\chosen_reg[2]\ => \chosen_reg[2]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_128_out,
p_108_out => p_108_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_16\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[0]\(0) => \chosen_reg[0]\(0),
\chosen_reg[0]_0\(0) => \chosen_reg[0]_0\(0),
\chosen_reg[2]\ => \chosen_reg[2]\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => \gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => \m_axi_rready[0]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_122_out,
p_102_out => p_102_out,
p_1_in => p_1_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 is
port (
p_108_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_102_out : out STD_LOGIC;
\m_axi_rready[1]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_1__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_1 : in STD_LOGIC;
match : in STD_LOGIC;
\gen_master_slots[0].r_issuing_cnt_reg[0]\ : in STD_LOGIC;
ADDRESS_HIT_0 : in STD_LOGIC;
\gen_master_slots[1].r_issuing_cnt_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_75_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 is
begin
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_13\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_108_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_14\
port map (
ADDRESS_HIT_0 => ADDRESS_HIT_0,
ADDRESS_HIT_1 => ADDRESS_HIT_1,
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[1]\(0) => \chosen_reg[1]\(0),
\chosen_reg[1]_0\(0) => \chosen_reg[1]_0\(0),
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].r_issuing_cnt_reg[0]\,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0) => \gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[1]\ => \m_axi_rready[1]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_102_out,
match => match,
p_1_in => p_1_in,
p_75_in => p_75_in,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 is
port (
p_88_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_82_out : out STD_LOGIC;
\m_axi_rready[2]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
\r_cmd_pop_2__1\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
\gen_master_slots[2].r_issuing_cnt_reg[18]\ : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[19]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_4 : in STD_LOGIC;
\s_axi_araddr[25]\ : in STD_LOGIC;
sel_2 : in STD_LOGIC;
p_57_in : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[2]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 is
begin
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_11\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_88_out,
p_1_in => p_1_in,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_12\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\chosen_reg[2]\(0) => \chosen_reg[2]\(0),
\chosen_reg[2]_0\(0) => \chosen_reg[2]_0\(0),
\gen_master_slots[2].r_issuing_cnt_reg[18]\ => \gen_master_slots[2].r_issuing_cnt_reg[18]\,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0) => \gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[2]\ => \m_axi_rready[2]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_82_out,
p_1_in => p_1_in,
p_57_in => p_57_in,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
\s_axi_araddr[25]\ => \s_axi_araddr[25]\,
s_axi_rready(0) => s_axi_rready(0),
sel_2 => sel_2,
sel_4 => sel_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3 is
port (
p_68_out : out STD_LOGIC;
m_axi_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
p_1_in : out STD_LOGIC;
p_62_out : out STD_LOGIC;
\m_axi_rready[3]\ : out STD_LOGIC;
\gen_no_arbiter.s_ready_i_reg[0]\ : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\r_cmd_pop_3__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\chosen_reg[4]\ : out STD_LOGIC;
\chosen_reg[4]_0\ : out STD_LOGIC;
\aresetn_d_reg[1]\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\aresetn_d_reg[1]_1\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
ADDRESS_HIT_3 : in STD_LOGIC;
\gen_master_slots[2].r_issuing_cnt_reg[16]\ : in STD_LOGIC;
\r_cmd_pop_4__1\ : in STD_LOGIC;
match : in STD_LOGIC;
r_issuing_cnt : in STD_LOGIC_VECTOR ( 4 downto 0 );
p_39_in : in STD_LOGIC;
p_82_out : in STD_LOGIC;
p_88_out : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
D : in STD_LOGIC_VECTOR ( 13 downto 0 );
\chosen_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3 is
signal \^p_1_in\ : STD_LOGIC;
begin
p_1_in <= \^p_1_in\;
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_9\
port map (
D(13 downto 0) => D(13 downto 0),
Q(0) => Q(0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]\,
\aresetn_d_reg[1]_0\ => \aresetn_d_reg[1]_0\,
\aresetn_d_reg[1]_1\ => \aresetn_d_reg[1]_1\,
\chosen_reg[4]\ => \chosen_reg[4]_0\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(13 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 0),
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
\m_payload_i_reg[0]_0\ => p_68_out,
p_1_in => \^p_1_in\,
p_88_out => p_88_out,
s_axi_bready(0) => s_axi_bready(0)
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_10\
port map (
ADDRESS_HIT_3 => ADDRESS_HIT_3,
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \aresetn_d_reg[1]_0\,
\chosen_reg[3]\(0) => \chosen_reg[3]\(0),
\chosen_reg[3]_0\(0) => \chosen_reg[3]_0\(0),
\chosen_reg[4]\ => \chosen_reg[4]\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].r_issuing_cnt_reg[16]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_no_arbiter.s_ready_i_reg[0]\,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[3]\ => \m_axi_rready[3]\,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
m_valid_i_reg_0 => p_62_out,
match => match,
p_1_in => \^p_1_in\,
p_39_in => p_39_in,
p_82_out => p_82_out,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(4 downto 0) => r_issuing_cnt(4 downto 0),
s_axi_rready(0) => s_axi_rready(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4 is
port (
p_46_out : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
mi_bready_4 : out STD_LOGIC;
p_40_out : out STD_LOGIC;
mi_rready_4 : out STD_LOGIC;
s_ready_i_reg : out STD_LOGIC;
\r_cmd_pop_4__1\ : out STD_LOGIC;
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
aclk : in STD_LOGIC;
p_1_in : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
p_29_in : in STD_LOGIC;
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
\chosen_reg[4]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
p_23_in : in STD_LOGIC;
\gen_axi.s_axi_rid_i_reg[11]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
p_25_in : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4 : entity is "axi_register_slice_v2_1_13_axi_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4 is
signal \^m_valid_i_reg\ : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
D(11 downto 0) => D(11 downto 0),
Q(0) => Q(0),
aclk => aclk,
\aresetn_d_reg[0]\ => \aresetn_d_reg[0]\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(11 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(11 downto 0),
\m_payload_i_reg[2]_0\ => p_46_out,
m_valid_i_reg_0 => \^m_valid_i_reg\,
mi_bready_4 => mi_bready_4,
p_1_in => p_1_in,
p_29_in => p_29_in,
s_axi_bready(0) => s_axi_bready(0),
s_ready_i_reg_0 => s_ready_i_reg
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
E(0) => E(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \^m_valid_i_reg\,
\chosen_reg[4]\(0) => \chosen_reg[4]\(0),
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => \gen_axi.s_axi_rid_i_reg[11]\(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0) => \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 0),
m_valid_i_reg_0 => p_40_out,
p_1_in => p_1_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
s_axi_rready(0) => s_axi_rready(0),
\skid_buffer_reg[34]_0\ => mi_rready_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router is
port (
ss_wr_awready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
\write_cs0__0\ : out STD_LOGIC;
st_aa_awtarget_enc : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 );
SR : in STD_LOGIC_VECTOR ( 0 to 0 );
match : in STD_LOGIC;
m_ready_d : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
p_22_in : in STD_LOGIC;
ss_wr_awvalid : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router is
begin
wrouter_aw_fifo: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
port map (
D(0) => D(0),
SR(0) => SR(0),
aclk => aclk,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(0) => m_ready_d(0),
match => match,
p_22_in => p_22_in,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
st_aa_awtarget_enc(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
\write_cs0__0\ => \write_cs0__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar is
port (
M_AXI_RREADY : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : out STD_LOGIC_VECTOR ( 68 downto 0 );
\m_axi_arqos[15]\ : out STD_LOGIC_VECTOR ( 68 downto 0 );
S_AXI_ARREADY : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_rid[0]\ : out STD_LOGIC;
\s_axi_rid[1]\ : out STD_LOGIC;
\s_axi_rid[2]\ : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC;
\s_axi_rid[4]\ : out STD_LOGIC;
\s_axi_rid[5]\ : out STD_LOGIC;
\s_axi_rid[6]\ : out STD_LOGIC;
\s_axi_rid[7]\ : out STD_LOGIC;
\s_axi_rid[8]\ : out STD_LOGIC;
\s_axi_rid[9]\ : out STD_LOGIC;
\s_axi_rid[10]\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC;
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
\s_axi_bid[0]\ : out STD_LOGIC;
\s_axi_bid[1]\ : out STD_LOGIC;
\s_axi_bid[2]\ : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC;
\s_axi_bid[4]\ : out STD_LOGIC;
\s_axi_bid[5]\ : out STD_LOGIC;
\s_axi_bid[6]\ : out STD_LOGIC;
\s_axi_bid[7]\ : out STD_LOGIC;
\s_axi_bid[8]\ : out STD_LOGIC;
\s_axi_bid[9]\ : out STD_LOGIC;
\s_axi_bid[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
\s_axi_awready[0]\ : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
aclk : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 68 downto 0 );
\s_axi_arqos[3]\ : in STD_LOGIC_VECTOR ( 68 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
aresetn : in STD_LOGIC;
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar is
signal \^q\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal aa_mi_artarget_hot : STD_LOGIC_VECTOR ( 4 to 4 );
signal aa_mi_arvalid : STD_LOGIC;
signal aa_mi_awtarget_hot : STD_LOGIC_VECTOR ( 4 downto 0 );
signal aa_sa_awvalid : STD_LOGIC;
signal addr_arbiter_ar_n_103 : STD_LOGIC;
signal addr_arbiter_ar_n_104 : STD_LOGIC;
signal addr_arbiter_ar_n_105 : STD_LOGIC;
signal addr_arbiter_ar_n_76 : STD_LOGIC;
signal addr_arbiter_ar_n_81 : STD_LOGIC;
signal addr_arbiter_ar_n_82 : STD_LOGIC;
signal addr_arbiter_ar_n_83 : STD_LOGIC;
signal addr_arbiter_ar_n_84 : STD_LOGIC;
signal addr_arbiter_ar_n_85 : STD_LOGIC;
signal addr_arbiter_ar_n_86 : STD_LOGIC;
signal addr_arbiter_ar_n_87 : STD_LOGIC;
signal addr_arbiter_ar_n_88 : STD_LOGIC;
signal addr_arbiter_ar_n_89 : STD_LOGIC;
signal addr_arbiter_ar_n_90 : STD_LOGIC;
signal addr_arbiter_ar_n_91 : STD_LOGIC;
signal addr_arbiter_ar_n_92 : STD_LOGIC;
signal addr_arbiter_ar_n_93 : STD_LOGIC;
signal addr_arbiter_ar_n_94 : STD_LOGIC;
signal addr_arbiter_aw_n_20 : STD_LOGIC;
signal addr_arbiter_aw_n_25 : STD_LOGIC;
signal addr_arbiter_aw_n_26 : STD_LOGIC;
signal addr_arbiter_aw_n_30 : STD_LOGIC;
signal aresetn_d : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_5\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_1\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2_2\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\ : STD_LOGIC;
signal \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_3\ : STD_LOGIC;
signal \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_54\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_55\ : STD_LOGIC;
signal \gen_master_slots[0].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[1].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_4\ : STD_LOGIC;
signal \gen_master_slots[2].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_55\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_56\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_57\ : STD_LOGIC;
signal \gen_master_slots[3].reg_slice_mi_n_6\ : STD_LOGIC;
signal \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\ : STD_LOGIC;
signal \gen_master_slots[4].reg_slice_mi_n_1\ : STD_LOGIC;
signal \gen_master_slots[4].reg_slice_mi_n_5\ : STD_LOGIC;
signal \gen_multi_thread.arbiter_resp_inst/chosen\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_multi_thread.arbiter_resp_inst/chosen_10\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\ : STD_LOGIC;
signal \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\ : STD_LOGIC;
signal \^m_axi_arqos[15]\ : STD_LOGIC_VECTOR ( 68 downto 0 );
signal m_ready_d : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_ready_d_13 : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m_valid_i : STD_LOGIC;
signal m_valid_i_11 : STD_LOGIC;
signal match : STD_LOGIC;
signal match_4 : STD_LOGIC;
signal mi_arready_4 : STD_LOGIC;
signal mi_awready_4 : STD_LOGIC;
signal \mi_awready_mux__3\ : STD_LOGIC;
signal mi_bready_4 : STD_LOGIC;
signal mi_rready_4 : STD_LOGIC;
signal p_101_in : STD_LOGIC;
signal p_102_out : STD_LOGIC;
signal p_104_out : STD_LOGIC;
signal p_108_out : STD_LOGIC;
signal p_122_out : STD_LOGIC;
signal p_124_out : STD_LOGIC;
signal p_128_out : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_22_in : STD_LOGIC;
signal p_23_in : STD_LOGIC;
signal p_25_in : STD_LOGIC;
signal p_28_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_29_in : STD_LOGIC;
signal p_32_in : STD_LOGIC_VECTOR ( 11 downto 0 );
signal p_39_in : STD_LOGIC;
signal p_40_out : STD_LOGIC;
signal p_42_out : STD_LOGIC;
signal p_46_out : STD_LOGIC;
signal p_48_in : STD_LOGIC;
signal p_57_in : STD_LOGIC;
signal p_62_out : STD_LOGIC;
signal p_64_out : STD_LOGIC;
signal p_66_in : STD_LOGIC;
signal p_68_out : STD_LOGIC;
signal p_75_in : STD_LOGIC;
signal p_82_out : STD_LOGIC;
signal p_84_in : STD_LOGIC;
signal p_84_out : STD_LOGIC;
signal p_88_out : STD_LOGIC;
signal p_93_in : STD_LOGIC;
signal \r_cmd_pop_0__1\ : STD_LOGIC;
signal \r_cmd_pop_1__1\ : STD_LOGIC;
signal \r_cmd_pop_2__1\ : STD_LOGIC;
signal \r_cmd_pop_3__1\ : STD_LOGIC;
signal \r_cmd_pop_4__1\ : STD_LOGIC;
signal r_issuing_cnt : STD_LOGIC_VECTOR ( 32 downto 0 );
signal \r_pipe/p_1_in\ : STD_LOGIC;
signal \r_pipe/p_1_in_6\ : STD_LOGIC;
signal \r_pipe/p_1_in_7\ : STD_LOGIC;
signal \r_pipe/p_1_in_8\ : STD_LOGIC;
signal \r_pipe/p_1_in_9\ : STD_LOGIC;
signal \read_cs__0\ : STD_LOGIC;
signal reset : STD_LOGIC;
signal \^s_axi_awready[0]\ : STD_LOGIC;
signal s_axi_rlast_i0 : STD_LOGIC;
signal s_axi_rvalid_i : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal s_ready_i0_12 : STD_LOGIC;
signal \s_ready_i0__1\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \sa_wm_awready_mux__3\ : STD_LOGIC;
signal splitter_aw_mi_n_0 : STD_LOGIC;
signal splitter_aw_mi_n_1 : STD_LOGIC;
signal splitter_aw_mi_n_10 : STD_LOGIC;
signal splitter_aw_mi_n_11 : STD_LOGIC;
signal splitter_aw_mi_n_12 : STD_LOGIC;
signal splitter_aw_mi_n_2 : STD_LOGIC;
signal splitter_aw_mi_n_3 : STD_LOGIC;
signal splitter_aw_mi_n_4 : STD_LOGIC;
signal splitter_aw_mi_n_5 : STD_LOGIC;
signal splitter_aw_mi_n_6 : STD_LOGIC;
signal splitter_aw_mi_n_7 : STD_LOGIC;
signal splitter_aw_mi_n_8 : STD_LOGIC;
signal splitter_aw_mi_n_9 : STD_LOGIC;
signal ss_aa_awready : STD_LOGIC;
signal ss_wr_awready : STD_LOGIC;
signal ss_wr_awvalid : STD_LOGIC;
signal st_aa_awtarget_enc : STD_LOGIC_VECTOR ( 1 downto 0 );
signal st_mr_bid : STD_LOGIC_VECTOR ( 59 downto 0 );
signal st_mr_bmesg : STD_LOGIC_VECTOR ( 10 downto 0 );
signal st_mr_rid : STD_LOGIC_VECTOR ( 59 downto 0 );
signal st_mr_rmesg : STD_LOGIC_VECTOR ( 139 downto 0 );
signal w_issuing_cnt : STD_LOGIC_VECTOR ( 32 downto 0 );
signal write_cs01_out : STD_LOGIC;
signal \write_cs0__0\ : STD_LOGIC;
begin
Q(68 downto 0) <= \^q\(68 downto 0);
S_AXI_ARREADY(0) <= \^s_axi_arready\(0);
\m_axi_arqos[15]\(68 downto 0) <= \^m_axi_arqos[15]\(68 downto 0);
\s_axi_awready[0]\ <= \^s_axi_awready[0]\;
addr_arbiter_ar: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
ADDRESS_HIT_1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
ADDRESS_HIT_3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
D(2) => addr_arbiter_ar_n_81,
D(1) => addr_arbiter_ar_n_82,
D(0) => addr_arbiter_ar_n_83,
E(0) => s_ready_i0,
Q(0) => aa_mi_artarget_hot(4),
SR(0) => reset,
S_AXI_ARREADY(0) => \^s_axi_arready\(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
\gen_axi.s_axi_rid_i_reg[11]\(0) => s_axi_rvalid_i,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(2) => addr_arbiter_ar_n_84,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(1) => addr_arbiter_ar_n_85,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(0) => addr_arbiter_ar_n_86,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(2) => addr_arbiter_ar_n_90,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(1) => addr_arbiter_ar_n_91,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(0) => addr_arbiter_ar_n_92,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(2) => addr_arbiter_ar_n_87,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(1) => addr_arbiter_ar_n_88,
\gen_master_slots[3].r_issuing_cnt_reg[27]\(0) => addr_arbiter_ar_n_89,
\gen_master_slots[4].r_issuing_cnt_reg[32]\ => addr_arbiter_ar_n_105,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]\ => addr_arbiter_ar_n_103,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ => addr_arbiter_ar_n_76,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]_0\ => addr_arbiter_ar_n_104,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_ar_n_93,
\gen_no_arbiter.s_ready_i_reg[0]_1\ => addr_arbiter_ar_n_94,
\m_axi_arqos[15]\(68 downto 0) => \^m_axi_arqos[15]\(68 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_valid_i => m_valid_i,
match => match,
mi_arready_4 => mi_arready_4,
p_23_in => p_23_in,
p_39_in => p_39_in,
p_57_in => p_57_in,
p_75_in => p_75_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(16) => r_issuing_cnt(32),
r_issuing_cnt(15 downto 12) => r_issuing_cnt(27 downto 24),
r_issuing_cnt(11 downto 8) => r_issuing_cnt(19 downto 16),
r_issuing_cnt(7 downto 4) => r_issuing_cnt(11 downto 8),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(3 downto 0),
\read_cs__0\ => \read_cs__0\,
\s_axi_araddr[18]\(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\,
\s_axi_arqos[3]\(68 downto 0) => \s_axi_arqos[3]\(68 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_rlast_i0 => s_axi_rlast_i0,
sel_2 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2\,
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
addr_arbiter_aw: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_5\,
ADDRESS_HIT_1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
ADDRESS_HIT_3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_1\,
D(68 downto 0) => D(68 downto 0),
E(0) => s_ready_i0_12,
Q(4 downto 0) => aa_mi_awtarget_hot(4 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
\chosen_reg[4]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen_10\(4),
\gen_master_slots[4].w_issuing_cnt_reg[32]\ => addr_arbiter_aw_n_30,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57]\ => addr_arbiter_aw_n_20,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_25,
\gen_no_arbiter.s_ready_i_reg[0]_1\ => addr_arbiter_aw_n_26,
\m_axi_awqos[15]\(68 downto 0) => \^q\(68 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d_13(1 downto 0),
m_ready_d_0(0) => m_ready_d(0),
m_valid_i => m_valid_i_11,
match => match_4,
mi_awready_4 => mi_awready_4,
\mi_awready_mux__3\ => \mi_awready_mux__3\,
p_101_in => p_101_in,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_84_in => p_84_in,
\s_axi_awaddr[18]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bready(0) => s_axi_bready(0),
\s_ready_i0__1\(0) => \s_ready_i0__1\(0),
\sa_wm_awready_mux__3\ => \sa_wm_awready_mux__3\,
sel_2 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2_2\,
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_3\,
ss_aa_awready => ss_aa_awready,
st_aa_awtarget_enc(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
w_issuing_cnt(3) => w_issuing_cnt(32),
w_issuing_cnt(2 downto 0) => w_issuing_cnt(19 downto 17),
write_cs01_out => write_cs01_out
);
aresetn_d_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => aresetn_d,
R => '0'
);
\gen_decerr_slave.decerr_slave_inst\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave
port map (
E(0) => s_axi_rvalid_i,
Q(0) => aa_mi_awtarget_hot(4),
SR(0) => reset,
aa_mi_arvalid => aa_mi_arvalid,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_no_arbiter.m_mesg_i_reg[11]\(11 downto 0) => \^q\(11 downto 0),
\gen_no_arbiter.m_mesg_i_reg[51]\(19 downto 12) => \^m_axi_arqos[15]\(51 downto 44),
\gen_no_arbiter.m_mesg_i_reg[51]\(11 downto 0) => \^m_axi_arqos[15]\(11 downto 0),
\gen_no_arbiter.m_target_hot_i_reg[4]\(0) => aa_mi_artarget_hot(4),
\m_payload_i_reg[13]\(11 downto 0) => p_32_in(11 downto 0),
m_ready_d(0) => m_ready_d_13(1),
\m_ready_d_reg[1]\ => splitter_aw_mi_n_3,
mi_arready_4 => mi_arready_4,
mi_awready_4 => mi_awready_4,
mi_bready_4 => mi_bready_4,
mi_rready_4 => mi_rready_4,
p_22_in => p_22_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
p_29_in => p_29_in,
\read_cs__0\ => \read_cs__0\,
s_axi_rlast_i0 => s_axi_rlast_i0,
\skid_buffer_reg[46]\(11 downto 0) => p_28_in(11 downto 0),
write_cs01_out => write_cs01_out,
\write_cs0__0\ => \write_cs0__0\
);
\gen_master_slots[0].r_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(0),
O => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].r_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0\,
Q => r_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_83,
Q => r_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_82,
Q => r_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].r_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[0].reg_slice_mi_n_4\,
D => addr_arbiter_ar_n_81,
Q => r_issuing_cnt(3),
R => reset
);
\gen_master_slots[0].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
port map (
D(13 downto 2) => m_axi_bid(11 downto 0),
D(1 downto 0) => m_axi_bresp(1 downto 0),
E(0) => \gen_master_slots[0].reg_slice_mi_n_4\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_10\(0),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[0]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(0),
\chosen_reg[0]_0\(0) => \r_pipe/p_1_in_9\,
\chosen_reg[2]\ => \gen_master_slots[0].reg_slice_mi_n_54\,
\chosen_reg[2]_0\ => \gen_master_slots[0].reg_slice_mi_n_55\,
\gen_master_slots[0].r_issuing_cnt_reg[3]\(3 downto 0) => r_issuing_cnt(3 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_124_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(1 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(34 downto 3),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(1 downto 0),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_6\,
m_axi_bready(0) => m_axi_bready(0),
m_axi_bvalid(0) => m_axi_bvalid(0),
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast(0) => m_axi_rlast(0),
\m_axi_rready[0]\ => M_AXI_RREADY(0),
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_rvalid(0) => m_axi_rvalid(0),
p_102_out => p_102_out,
p_108_out => p_108_out,
p_122_out => p_122_out,
p_128_out => p_128_out,
p_1_in => p_1_in,
p_93_in => p_93_in,
\r_cmd_pop_0__1\ => \r_cmd_pop_0__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[0].w_issuing_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(0),
O => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\
);
\gen_master_slots[0].w_issuing_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0\,
Q => w_issuing_cnt(0),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_12,
Q => w_issuing_cnt(1),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_11,
Q => w_issuing_cnt(2),
R => reset
);
\gen_master_slots[0].w_issuing_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
D => splitter_aw_mi_n_10,
Q => w_issuing_cnt(3),
R => reset
);
\gen_master_slots[1].r_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(8),
O => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].r_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_85,
Q => r_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_84,
Q => r_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_5\,
D => \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0\,
Q => r_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].r_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[1].reg_slice_mi_n_5\,
D => addr_arbiter_ar_n_86,
Q => r_issuing_cnt(9),
R => reset
);
\gen_master_slots[1].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0\,
ADDRESS_HIT_1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1\,
D(13 downto 2) => m_axi_bid(23 downto 12),
D(1 downto 0) => m_axi_bresp(3 downto 2),
E(0) => \gen_master_slots[1].reg_slice_mi_n_5\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_10\(1),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[1]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(1),
\chosen_reg[1]_0\(0) => \r_pipe/p_1_in_8\,
\gen_master_slots[0].r_issuing_cnt_reg[0]\ => \gen_master_slots[0].reg_slice_mi_n_6\,
\gen_master_slots[1].r_issuing_cnt_reg[11]\(3 downto 0) => r_issuing_cnt(11 downto 8),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_104_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(36 downto 35),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(69 downto 38),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(23 downto 12),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(4 downto 3),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[1].reg_slice_mi_n_4\,
m_axi_bready(0) => m_axi_bready(1),
m_axi_bvalid(0) => m_axi_bvalid(1),
m_axi_rdata(31 downto 0) => m_axi_rdata(63 downto 32),
m_axi_rid(11 downto 0) => m_axi_rid(23 downto 12),
m_axi_rlast(0) => m_axi_rlast(1),
\m_axi_rready[1]\ => M_AXI_RREADY(1),
m_axi_rresp(1 downto 0) => m_axi_rresp(3 downto 2),
m_axi_rvalid(0) => m_axi_rvalid(1),
match => match,
p_102_out => p_102_out,
p_108_out => p_108_out,
p_1_in => p_1_in,
p_75_in => p_75_in,
\r_cmd_pop_1__1\ => \r_cmd_pop_1__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[1].w_issuing_cnt[8]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(8),
O => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\
);
\gen_master_slots[1].w_issuing_cnt_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_1,
Q => w_issuing_cnt(10),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_0,
Q => w_issuing_cnt(11),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0\,
Q => w_issuing_cnt(8),
R => reset
);
\gen_master_slots[1].w_issuing_cnt_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
D => splitter_aw_mi_n_2,
Q => w_issuing_cnt(9),
R => reset
);
\gen_master_slots[2].r_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(16),
O => \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\
);
\gen_master_slots[2].r_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_6\,
D => \gen_master_slots[2].r_issuing_cnt[16]_i_1_n_0\,
Q => r_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_6\,
D => addr_arbiter_ar_n_92,
Q => r_issuing_cnt(17),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_6\,
D => addr_arbiter_ar_n_91,
Q => r_issuing_cnt(18),
R => reset
);
\gen_master_slots[2].r_issuing_cnt_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[2].reg_slice_mi_n_6\,
D => addr_arbiter_ar_n_90,
Q => r_issuing_cnt(19),
R => reset
);
\gen_master_slots[2].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2
port map (
D(13 downto 2) => m_axi_bid(35 downto 24),
D(1 downto 0) => m_axi_bresp(5 downto 4),
E(0) => \gen_master_slots[2].reg_slice_mi_n_6\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_10\(2),
aclk => aclk,
\aresetn_d_reg[1]\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[2]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(2),
\chosen_reg[2]_0\(0) => \r_pipe/p_1_in\,
\gen_master_slots[2].r_issuing_cnt_reg[18]\ => addr_arbiter_ar_n_93,
\gen_master_slots[2].r_issuing_cnt_reg[19]\(3 downto 0) => r_issuing_cnt(19 downto 16),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_84_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(71 downto 70),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(104 downto 73),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(35 downto 24),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(7 downto 6),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[2].reg_slice_mi_n_4\,
m_axi_bready(0) => m_axi_bready(2),
m_axi_bvalid(0) => m_axi_bvalid(2),
m_axi_rdata(31 downto 0) => m_axi_rdata(95 downto 64),
m_axi_rid(11 downto 0) => m_axi_rid(35 downto 24),
m_axi_rlast(0) => m_axi_rlast(2),
\m_axi_rready[2]\ => M_AXI_RREADY(2),
m_axi_rresp(1 downto 0) => m_axi_rresp(5 downto 4),
m_axi_rvalid(0) => m_axi_rvalid(2),
p_1_in => p_1_in,
p_57_in => p_57_in,
p_82_out => p_82_out,
p_88_out => p_88_out,
\r_cmd_pop_2__1\ => \r_cmd_pop_2__1\,
\s_axi_araddr[25]\ => addr_arbiter_ar_n_76,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0),
sel_2 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2\,
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4\
);
\gen_master_slots[2].w_issuing_cnt[16]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(16),
O => \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\
);
\gen_master_slots[2].w_issuing_cnt_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => \gen_master_slots[2].w_issuing_cnt[16]_i_1_n_0\,
Q => w_issuing_cnt(16),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_6,
Q => w_issuing_cnt(17),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_5,
Q => w_issuing_cnt(18),
R => reset
);
\gen_master_slots[2].w_issuing_cnt_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
D => splitter_aw_mi_n_4,
Q => w_issuing_cnt(19),
R => reset
);
\gen_master_slots[3].r_issuing_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => r_issuing_cnt(24),
O => \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\
);
\gen_master_slots[3].r_issuing_cnt_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_6\,
D => \gen_master_slots[3].r_issuing_cnt[24]_i_1_n_0\,
Q => r_issuing_cnt(24),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_6\,
D => addr_arbiter_ar_n_89,
Q => r_issuing_cnt(25),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_6\,
D => addr_arbiter_ar_n_88,
Q => r_issuing_cnt(26),
R => reset
);
\gen_master_slots[3].r_issuing_cnt_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_master_slots[3].reg_slice_mi_n_6\,
D => addr_arbiter_ar_n_87,
Q => r_issuing_cnt(27),
R => reset
);
\gen_master_slots[3].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_3
port map (
ADDRESS_HIT_3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3\,
D(13 downto 2) => m_axi_bid(47 downto 36),
D(1 downto 0) => m_axi_bresp(7 downto 6),
E(0) => \gen_master_slots[3].reg_slice_mi_n_6\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_10\(3),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]\ => \gen_master_slots[3].reg_slice_mi_n_57\,
\aresetn_d_reg[1]_0\ => \gen_master_slots[4].reg_slice_mi_n_1\,
\aresetn_d_reg[1]_1\ => \gen_master_slots[4].reg_slice_mi_n_5\,
\chosen_reg[3]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(3),
\chosen_reg[3]_0\(0) => \r_pipe/p_1_in_6\,
\chosen_reg[4]\ => \gen_master_slots[3].reg_slice_mi_n_55\,
\chosen_reg[4]_0\ => \gen_master_slots[3].reg_slice_mi_n_56\,
\gen_master_slots[2].r_issuing_cnt_reg[16]\ => \gen_master_slots[2].reg_slice_mi_n_4\,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(46 downto 35) => st_mr_rid(47 downto 36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(34) => p_64_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(33 downto 32) => st_mr_rmesg(106 downto 105),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(31 downto 0) => st_mr_rmesg(139 downto 108),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(13 downto 2) => st_mr_bid(47 downto 36),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(1 downto 0) => st_mr_bmesg(10 downto 9),
\gen_no_arbiter.s_ready_i_reg[0]\ => \gen_master_slots[3].reg_slice_mi_n_5\,
m_axi_bready(0) => m_axi_bready(3),
m_axi_bvalid(0) => m_axi_bvalid(3),
m_axi_rdata(31 downto 0) => m_axi_rdata(127 downto 96),
m_axi_rid(11 downto 0) => m_axi_rid(47 downto 36),
m_axi_rlast(0) => m_axi_rlast(3),
\m_axi_rready[3]\ => M_AXI_RREADY(3),
m_axi_rresp(1 downto 0) => m_axi_rresp(7 downto 6),
m_axi_rvalid(0) => m_axi_rvalid(3),
match => match,
p_1_in => p_1_in,
p_39_in => p_39_in,
p_62_out => p_62_out,
p_68_out => p_68_out,
p_82_out => p_82_out,
p_88_out => p_88_out,
\r_cmd_pop_3__1\ => \r_cmd_pop_3__1\,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
r_issuing_cnt(4) => r_issuing_cnt(32),
r_issuing_cnt(3 downto 0) => r_issuing_cnt(27 downto 24),
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0)
);
\gen_master_slots[3].w_issuing_cnt[24]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => w_issuing_cnt(24),
O => \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\
);
\gen_master_slots[3].w_issuing_cnt_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => \gen_master_slots[3].w_issuing_cnt[24]_i_1_n_0\,
Q => w_issuing_cnt(24),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_9,
Q => w_issuing_cnt(25),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_8,
Q => w_issuing_cnt(26),
R => reset
);
\gen_master_slots[3].w_issuing_cnt_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
D => splitter_aw_mi_n_7,
Q => w_issuing_cnt(27),
R => reset
);
\gen_master_slots[4].r_issuing_cnt_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_ar_n_105,
Q => r_issuing_cnt(32),
R => reset
);
\gen_master_slots[4].reg_slice_mi\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_4
port map (
D(11 downto 0) => p_32_in(11 downto 0),
E(0) => \r_pipe/p_1_in_7\,
Q(0) => \gen_multi_thread.arbiter_resp_inst/chosen_10\(4),
aclk => aclk,
\aresetn_d_reg[0]\ => \gen_master_slots[3].reg_slice_mi_n_57\,
\chosen_reg[4]\(0) => \gen_multi_thread.arbiter_resp_inst/chosen\(4),
\gen_axi.s_axi_rid_i_reg[11]\(11 downto 0) => p_28_in(11 downto 0),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(12 downto 1) => st_mr_rid(59 downto 48),
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]\(0) => p_42_out,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0\(11 downto 0) => st_mr_bid(59 downto 48),
m_valid_i_reg => \gen_master_slots[4].reg_slice_mi_n_1\,
mi_bready_4 => mi_bready_4,
mi_rready_4 => mi_rready_4,
p_1_in => p_1_in,
p_23_in => p_23_in,
p_25_in => p_25_in,
p_29_in => p_29_in,
p_40_out => p_40_out,
p_46_out => p_46_out,
\r_cmd_pop_4__1\ => \r_cmd_pop_4__1\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_rready(0) => s_axi_rready(0),
s_ready_i_reg => \gen_master_slots[4].reg_slice_mi_n_5\
);
\gen_master_slots[4].w_issuing_cnt_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => addr_arbiter_aw_n_30,
Q => w_issuing_cnt(32),
R => reset
);
\gen_slave_slots[0].gen_si_read.si_transactor_ar\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor
port map (
D(0) => \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_49\,
E(0) => s_ready_i0,
Q(4 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen\(4 downto 0),
SR(0) => reset,
S_AXI_ARREADY(0) => \^s_axi_arready\(0),
aa_mi_arvalid => aa_mi_arvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_master_slots[1].r_issuing_cnt_reg[8]\ => \gen_master_slots[1].reg_slice_mi_n_4\,
\gen_master_slots[4].r_issuing_cnt_reg[32]\ => \gen_master_slots[3].reg_slice_mi_n_5\,
\gen_no_arbiter.s_ready_i_reg[0]\ => addr_arbiter_ar_n_94,
\m_payload_i_reg[0]\(0) => \r_pipe/p_1_in_9\,
\m_payload_i_reg[0]_0\(0) => \r_pipe/p_1_in_8\,
\m_payload_i_reg[0]_1\(0) => \r_pipe/p_1_in_6\,
\m_payload_i_reg[0]_2\(0) => \r_pipe/p_1_in\,
\m_payload_i_reg[34]\(0) => \r_pipe/p_1_in_7\,
\m_payload_i_reg[34]_0\(0) => p_42_out,
\m_payload_i_reg[34]_1\(0) => p_64_out,
\m_payload_i_reg[34]_2\(0) => p_124_out,
\m_payload_i_reg[34]_3\(0) => p_84_out,
\m_payload_i_reg[34]_4\(0) => p_104_out,
m_valid_i => m_valid_i,
m_valid_i_reg => \gen_master_slots[3].reg_slice_mi_n_55\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_54\,
match => match,
p_102_out => p_102_out,
p_122_out => p_122_out,
p_40_out => p_40_out,
p_62_out => p_62_out,
p_82_out => p_82_out,
\s_axi_araddr[18]\ => addr_arbiter_ar_n_103,
\s_axi_araddr[25]\ => addr_arbiter_ar_n_104,
\s_axi_arid[11]\(11 downto 0) => \s_axi_arqos[3]\(11 downto 0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => \s_axi_rid[0]\,
\s_axi_rid[10]\ => \s_axi_rid[10]\,
\s_axi_rid[11]\ => \s_axi_rid[11]\,
\s_axi_rid[1]\ => \s_axi_rid[1]\,
\s_axi_rid[2]\ => \s_axi_rid[2]\,
\s_axi_rid[3]\ => \s_axi_rid[3]\,
\s_axi_rid[4]\ => \s_axi_rid[4]\,
\s_axi_rid[5]\ => \s_axi_rid[5]\,
\s_axi_rid[6]\ => \s_axi_rid[6]\,
\s_axi_rid[7]\ => \s_axi_rid[7]\,
\s_axi_rid[8]\ => \s_axi_rid[8]\,
\s_axi_rid[9]\ => \s_axi_rid[9]\,
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid(0) => s_axi_rvalid(0),
st_mr_rid(59 downto 0) => st_mr_rid(59 downto 0),
st_mr_rmesg(135 downto 104) => st_mr_rmesg(139 downto 108),
st_mr_rmesg(103 downto 70) => st_mr_rmesg(106 downto 73),
st_mr_rmesg(69 downto 36) => st_mr_rmesg(71 downto 38),
st_mr_rmesg(35 downto 2) => st_mr_rmesg(36 downto 3),
st_mr_rmesg(1 downto 0) => st_mr_rmesg(1 downto 0)
);
\gen_slave_slots[0].gen_si_write.si_transactor_aw\: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0\
port map (
ADDRESS_HIT_0 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_0_5\,
ADDRESS_HIT_1 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_1_0\,
ADDRESS_HIT_3 => \gen_addr_decoder.addr_decoder_inst/ADDRESS_HIT_3_1\,
D(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
E(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_14\,
Q(4 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_10\(4 downto 0),
SR(0) => reset,
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\gen_master_slots[0].w_issuing_cnt_reg[0]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_17\,
\gen_master_slots[2].w_issuing_cnt_reg[16]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_15\,
\gen_master_slots[2].w_issuing_cnt_reg[18]\ => addr_arbiter_aw_n_25,
\gen_master_slots[3].w_issuing_cnt_reg[24]\(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_16\,
\gen_no_arbiter.s_ready_i_reg[0]\(0) => s_ready_i0_12,
\gen_no_arbiter.s_ready_i_reg[0]_0\ => addr_arbiter_aw_n_26,
\m_ready_d_reg[1]\ => \^s_axi_awready[0]\,
m_valid_i => m_valid_i_11,
m_valid_i_reg => \gen_master_slots[3].reg_slice_mi_n_56\,
m_valid_i_reg_0 => \gen_master_slots[0].reg_slice_mi_n_55\,
match => match_4,
p_101_in => p_101_in,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_46_out => p_46_out,
p_48_in => p_48_in,
p_66_in => p_66_in,
p_68_out => p_68_out,
p_84_in => p_84_in,
p_88_out => p_88_out,
\s_axi_awaddr[25]\ => addr_arbiter_aw_n_20,
\s_axi_awid[11]\(11 downto 0) => D(11 downto 0),
\s_axi_bid[0]\ => \s_axi_bid[0]\,
\s_axi_bid[10]\ => \s_axi_bid[10]\,
\s_axi_bid[11]\ => \s_axi_bid[11]\,
\s_axi_bid[1]\ => \s_axi_bid[1]\,
\s_axi_bid[2]\ => \s_axi_bid[2]\,
\s_axi_bid[3]\ => \s_axi_bid[3]\,
\s_axi_bid[4]\ => \s_axi_bid[4]\,
\s_axi_bid[5]\ => \s_axi_bid[5]\,
\s_axi_bid[6]\ => \s_axi_bid[6]\,
\s_axi_bid[7]\ => \s_axi_bid[7]\,
\s_axi_bid[8]\ => \s_axi_bid[8]\,
\s_axi_bid[9]\ => \s_axi_bid[9]\,
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
sel_2 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_2_2\,
sel_4 => \gen_addr_decoder.addr_decoder_inst/gen_target[3].gen_region[0].gen_comparator_static.gen_addr_range.addr_decode_comparator/sel_4_3\,
st_aa_awtarget_enc(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
st_mr_bid(59 downto 0) => st_mr_bid(59 downto 0),
st_mr_bmesg(7 downto 6) => st_mr_bmesg(10 downto 9),
st_mr_bmesg(5 downto 4) => st_mr_bmesg(7 downto 6),
st_mr_bmesg(3 downto 2) => st_mr_bmesg(4 downto 3),
st_mr_bmesg(1 downto 0) => st_mr_bmesg(1 downto 0),
w_issuing_cnt(16) => w_issuing_cnt(32),
w_issuing_cnt(15 downto 12) => w_issuing_cnt(27 downto 24),
w_issuing_cnt(11 downto 8) => w_issuing_cnt(19 downto 16),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
\gen_slave_slots[0].gen_si_write.splitter_aw_si\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter
port map (
aclk => aclk,
aresetn_d => aresetn_d,
m_ready_d(1 downto 0) => m_ready_d(1 downto 0),
\s_axi_awready[0]\ => \^s_axi_awready[0]\,
s_axi_awvalid(0) => s_axi_awvalid(0),
ss_aa_awready => ss_aa_awready,
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid
);
\gen_slave_slots[0].gen_si_write.wdata_router_w\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router
port map (
D(0) => \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_21\,
SR(0) => reset,
aclk => aclk,
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
m_ready_d(0) => m_ready_d(1),
match => match_4,
p_22_in => p_22_in,
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0),
ss_wr_awready => ss_wr_awready,
ss_wr_awvalid => ss_wr_awvalid,
st_aa_awtarget_enc(1 downto 0) => st_aa_awtarget_enc(1 downto 0),
\write_cs0__0\ => \write_cs0__0\
);
splitter_aw_mi: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_5
port map (
D(2) => splitter_aw_mi_n_0,
D(1) => splitter_aw_mi_n_1,
D(0) => splitter_aw_mi_n_2,
Q(3 downto 0) => aa_mi_awtarget_hot(3 downto 0),
aa_sa_awvalid => aa_sa_awvalid,
aclk => aclk,
aresetn_d => aresetn_d,
\chosen_reg[3]\(3 downto 0) => \gen_multi_thread.arbiter_resp_inst/chosen_10\(3 downto 0),
\gen_axi.s_axi_awready_i_reg\ => splitter_aw_mi_n_3,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(2) => splitter_aw_mi_n_10,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(1) => splitter_aw_mi_n_11,
\gen_master_slots[0].w_issuing_cnt_reg[3]\(0) => splitter_aw_mi_n_12,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(2) => splitter_aw_mi_n_4,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(1) => splitter_aw_mi_n_5,
\gen_master_slots[2].w_issuing_cnt_reg[19]\(0) => splitter_aw_mi_n_6,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(2) => splitter_aw_mi_n_7,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(1) => splitter_aw_mi_n_8,
\gen_master_slots[3].w_issuing_cnt_reg[27]\(0) => splitter_aw_mi_n_9,
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_ready_d(1 downto 0) => m_ready_d_13(1 downto 0),
\mi_awready_mux__3\ => \mi_awready_mux__3\,
p_108_out => p_108_out,
p_128_out => p_128_out,
p_68_out => p_68_out,
p_88_out => p_88_out,
s_axi_bready(0) => s_axi_bready(0),
\s_ready_i0__1\(0) => \s_ready_i0__1\(0),
\sa_wm_awready_mux__3\ => \sa_wm_awready_mux__3\,
w_issuing_cnt(15 downto 12) => w_issuing_cnt(27 downto 24),
w_issuing_cnt(11 downto 8) => w_issuing_cnt(19 downto 16),
w_issuing_cnt(7 downto 4) => w_issuing_cnt(11 downto 8),
w_issuing_cnt(3 downto 0) => w_issuing_cnt(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_ruser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "zynq";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 8;
attribute P_LOCK : integer;
attribute P_LOCK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar : entity is "1'b1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_araddr\ : STD_LOGIC_VECTOR ( 127 downto 96 );
signal \^m_axi_arburst\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \^m_axi_arcache\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_arlen\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^m_axi_arlock\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^m_axi_arprot\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_arqos\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_arsize\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_awaddr\ : STD_LOGIC_VECTOR ( 127 downto 96 );
signal \^m_axi_awburst\ : STD_LOGIC_VECTOR ( 7 downto 6 );
signal \^m_axi_awcache\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_awlen\ : STD_LOGIC_VECTOR ( 31 downto 24 );
signal \^m_axi_awlock\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^m_axi_awprot\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^m_axi_awqos\ : STD_LOGIC_VECTOR ( 15 downto 12 );
signal \^m_axi_awsize\ : STD_LOGIC_VECTOR ( 11 downto 9 );
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\(0) <= s_axi_wlast(0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
m_axi_araddr(127 downto 96) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(95 downto 64) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(63 downto 32) <= \^m_axi_araddr\(127 downto 96);
m_axi_araddr(31 downto 0) <= \^m_axi_araddr\(127 downto 96);
m_axi_arburst(7 downto 6) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(5 downto 4) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(3 downto 2) <= \^m_axi_arburst\(7 downto 6);
m_axi_arburst(1 downto 0) <= \^m_axi_arburst\(7 downto 6);
m_axi_arcache(15 downto 12) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(11 downto 8) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(7 downto 4) <= \^m_axi_arcache\(15 downto 12);
m_axi_arcache(3 downto 0) <= \^m_axi_arcache\(15 downto 12);
m_axi_arid(47 downto 36) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(35 downto 24) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(23 downto 12) <= \^m_axi_arid\(11 downto 0);
m_axi_arid(11 downto 0) <= \^m_axi_arid\(11 downto 0);
m_axi_arlen(31 downto 24) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(23 downto 16) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(15 downto 8) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlen(7 downto 0) <= \^m_axi_arlen\(7 downto 0);
m_axi_arlock(3) <= \^m_axi_arlock\(3);
m_axi_arlock(2) <= \^m_axi_arlock\(3);
m_axi_arlock(1) <= \^m_axi_arlock\(3);
m_axi_arlock(0) <= \^m_axi_arlock\(3);
m_axi_arprot(11 downto 9) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(8 downto 6) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(5 downto 3) <= \^m_axi_arprot\(11 downto 9);
m_axi_arprot(2 downto 0) <= \^m_axi_arprot\(11 downto 9);
m_axi_arqos(15 downto 12) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(11 downto 8) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(7 downto 4) <= \^m_axi_arqos\(15 downto 12);
m_axi_arqos(3 downto 0) <= \^m_axi_arqos\(15 downto 12);
m_axi_arregion(15) <= \<const0>\;
m_axi_arregion(14) <= \<const0>\;
m_axi_arregion(13) <= \<const0>\;
m_axi_arregion(12) <= \<const0>\;
m_axi_arregion(11) <= \<const0>\;
m_axi_arregion(10) <= \<const0>\;
m_axi_arregion(9) <= \<const0>\;
m_axi_arregion(8) <= \<const0>\;
m_axi_arregion(7) <= \<const0>\;
m_axi_arregion(6) <= \<const0>\;
m_axi_arregion(5) <= \<const0>\;
m_axi_arregion(4) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(11 downto 9) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(8 downto 6) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(5 downto 3) <= \^m_axi_arsize\(11 downto 9);
m_axi_arsize(2 downto 0) <= \^m_axi_arsize\(11 downto 9);
m_axi_aruser(3) <= \<const0>\;
m_axi_aruser(2) <= \<const0>\;
m_axi_aruser(1) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awaddr(127 downto 96) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(95 downto 64) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(63 downto 32) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awaddr(31 downto 0) <= \^m_axi_awaddr\(127 downto 96);
m_axi_awburst(7 downto 6) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(5 downto 4) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(3 downto 2) <= \^m_axi_awburst\(7 downto 6);
m_axi_awburst(1 downto 0) <= \^m_axi_awburst\(7 downto 6);
m_axi_awcache(15 downto 12) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(11 downto 8) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(7 downto 4) <= \^m_axi_awcache\(15 downto 12);
m_axi_awcache(3 downto 0) <= \^m_axi_awcache\(15 downto 12);
m_axi_awid(47 downto 36) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(35 downto 24) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(23 downto 12) <= \^m_axi_awid\(11 downto 0);
m_axi_awid(11 downto 0) <= \^m_axi_awid\(11 downto 0);
m_axi_awlen(31 downto 24) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(23 downto 16) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(15 downto 8) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlen(7 downto 0) <= \^m_axi_awlen\(31 downto 24);
m_axi_awlock(3) <= \^m_axi_awlock\(3);
m_axi_awlock(2) <= \^m_axi_awlock\(3);
m_axi_awlock(1) <= \^m_axi_awlock\(3);
m_axi_awlock(0) <= \^m_axi_awlock\(3);
m_axi_awprot(11 downto 9) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(8 downto 6) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(5 downto 3) <= \^m_axi_awprot\(11 downto 9);
m_axi_awprot(2 downto 0) <= \^m_axi_awprot\(11 downto 9);
m_axi_awqos(15 downto 12) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(11 downto 8) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(7 downto 4) <= \^m_axi_awqos\(15 downto 12);
m_axi_awqos(3 downto 0) <= \^m_axi_awqos\(15 downto 12);
m_axi_awregion(15) <= \<const0>\;
m_axi_awregion(14) <= \<const0>\;
m_axi_awregion(13) <= \<const0>\;
m_axi_awregion(12) <= \<const0>\;
m_axi_awregion(11) <= \<const0>\;
m_axi_awregion(10) <= \<const0>\;
m_axi_awregion(9) <= \<const0>\;
m_axi_awregion(8) <= \<const0>\;
m_axi_awregion(7) <= \<const0>\;
m_axi_awregion(6) <= \<const0>\;
m_axi_awregion(5) <= \<const0>\;
m_axi_awregion(4) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(11 downto 9) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(8 downto 6) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(5 downto 3) <= \^m_axi_awsize\(11 downto 9);
m_axi_awsize(2 downto 0) <= \^m_axi_awsize\(11 downto 9);
m_axi_awuser(3) <= \<const0>\;
m_axi_awuser(2) <= \<const0>\;
m_axi_awuser(1) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(127 downto 96) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(95 downto 64) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(63 downto 32) <= \^s_axi_wdata\(31 downto 0);
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(47) <= \<const0>\;
m_axi_wid(46) <= \<const0>\;
m_axi_wid(45) <= \<const0>\;
m_axi_wid(44) <= \<const0>\;
m_axi_wid(43) <= \<const0>\;
m_axi_wid(42) <= \<const0>\;
m_axi_wid(41) <= \<const0>\;
m_axi_wid(40) <= \<const0>\;
m_axi_wid(39) <= \<const0>\;
m_axi_wid(38) <= \<const0>\;
m_axi_wid(37) <= \<const0>\;
m_axi_wid(36) <= \<const0>\;
m_axi_wid(35) <= \<const0>\;
m_axi_wid(34) <= \<const0>\;
m_axi_wid(33) <= \<const0>\;
m_axi_wid(32) <= \<const0>\;
m_axi_wid(31) <= \<const0>\;
m_axi_wid(30) <= \<const0>\;
m_axi_wid(29) <= \<const0>\;
m_axi_wid(28) <= \<const0>\;
m_axi_wid(27) <= \<const0>\;
m_axi_wid(26) <= \<const0>\;
m_axi_wid(25) <= \<const0>\;
m_axi_wid(24) <= \<const0>\;
m_axi_wid(23) <= \<const0>\;
m_axi_wid(22) <= \<const0>\;
m_axi_wid(21) <= \<const0>\;
m_axi_wid(20) <= \<const0>\;
m_axi_wid(19) <= \<const0>\;
m_axi_wid(18) <= \<const0>\;
m_axi_wid(17) <= \<const0>\;
m_axi_wid(16) <= \<const0>\;
m_axi_wid(15) <= \<const0>\;
m_axi_wid(14) <= \<const0>\;
m_axi_wid(13) <= \<const0>\;
m_axi_wid(12) <= \<const0>\;
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast(3) <= \^s_axi_wlast\(0);
m_axi_wlast(2) <= \^s_axi_wlast\(0);
m_axi_wlast(1) <= \^s_axi_wlast\(0);
m_axi_wlast(0) <= \^s_axi_wlast\(0);
m_axi_wstrb(15 downto 12) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(11 downto 8) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(7 downto 4) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(3) <= \<const0>\;
m_axi_wuser(2) <= \<const0>\;
m_axi_wuser(1) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_samd.crossbar_samd\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar
port map (
D(68 downto 65) => s_axi_awqos(3 downto 0),
D(64 downto 61) => s_axi_awcache(3 downto 0),
D(60 downto 59) => s_axi_awburst(1 downto 0),
D(58 downto 56) => s_axi_awprot(2 downto 0),
D(55) => s_axi_awlock(0),
D(54 downto 52) => s_axi_awsize(2 downto 0),
D(51 downto 44) => s_axi_awlen(7 downto 0),
D(43 downto 12) => s_axi_awaddr(31 downto 0),
D(11 downto 0) => s_axi_awid(11 downto 0),
M_AXI_RREADY(3 downto 0) => m_axi_rready(3 downto 0),
Q(68 downto 65) => \^m_axi_awqos\(15 downto 12),
Q(64 downto 61) => \^m_axi_awcache\(15 downto 12),
Q(60 downto 59) => \^m_axi_awburst\(7 downto 6),
Q(58 downto 56) => \^m_axi_awprot\(11 downto 9),
Q(55) => \^m_axi_awlock\(3),
Q(54 downto 52) => \^m_axi_awsize\(11 downto 9),
Q(51 downto 44) => \^m_axi_awlen\(31 downto 24),
Q(43 downto 12) => \^m_axi_awaddr\(127 downto 96),
Q(11 downto 0) => \^m_axi_awid\(11 downto 0),
S_AXI_ARREADY(0) => s_axi_arready(0),
aclk => aclk,
aresetn => aresetn,
\m_axi_arqos[15]\(68 downto 65) => \^m_axi_arqos\(15 downto 12),
\m_axi_arqos[15]\(64 downto 61) => \^m_axi_arcache\(15 downto 12),
\m_axi_arqos[15]\(60 downto 59) => \^m_axi_arburst\(7 downto 6),
\m_axi_arqos[15]\(58 downto 56) => \^m_axi_arprot\(11 downto 9),
\m_axi_arqos[15]\(55) => \^m_axi_arlock\(3),
\m_axi_arqos[15]\(54 downto 52) => \^m_axi_arsize\(11 downto 9),
\m_axi_arqos[15]\(51 downto 44) => \^m_axi_arlen\(7 downto 0),
\m_axi_arqos[15]\(43 downto 12) => \^m_axi_araddr\(127 downto 96),
\m_axi_arqos[15]\(11 downto 0) => \^m_axi_arid\(11 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => m_axi_bid(47 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => m_axi_rid(47 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
\s_axi_arqos[3]\(68 downto 65) => s_axi_arqos(3 downto 0),
\s_axi_arqos[3]\(64 downto 61) => s_axi_arcache(3 downto 0),
\s_axi_arqos[3]\(60 downto 59) => s_axi_arburst(1 downto 0),
\s_axi_arqos[3]\(58 downto 56) => s_axi_arprot(2 downto 0),
\s_axi_arqos[3]\(55) => s_axi_arlock(0),
\s_axi_arqos[3]\(54 downto 52) => s_axi_arsize(2 downto 0),
\s_axi_arqos[3]\(51 downto 44) => s_axi_arlen(7 downto 0),
\s_axi_arqos[3]\(43 downto 12) => s_axi_araddr(31 downto 0),
\s_axi_arqos[3]\(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arvalid(0) => s_axi_arvalid(0),
\s_axi_awready[0]\ => s_axi_awready(0),
s_axi_awvalid(0) => s_axi_awvalid(0),
\s_axi_bid[0]\ => s_axi_bid(0),
\s_axi_bid[10]\ => s_axi_bid(10),
\s_axi_bid[11]\ => s_axi_bid(11),
\s_axi_bid[1]\ => s_axi_bid(1),
\s_axi_bid[2]\ => s_axi_bid(2),
\s_axi_bid[3]\ => s_axi_bid(3),
\s_axi_bid[4]\ => s_axi_bid(4),
\s_axi_bid[5]\ => s_axi_bid(5),
\s_axi_bid[6]\ => s_axi_bid(6),
\s_axi_bid[7]\ => s_axi_bid(7),
\s_axi_bid[8]\ => s_axi_bid(8),
\s_axi_bid[9]\ => s_axi_bid(9),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
\s_axi_rid[0]\ => s_axi_rid(0),
\s_axi_rid[10]\ => s_axi_rid(10),
\s_axi_rid[11]\ => s_axi_rid(11),
\s_axi_rid[1]\ => s_axi_rid(1),
\s_axi_rid[2]\ => s_axi_rid(2),
\s_axi_rid[3]\ => s_axi_rid(3),
\s_axi_rid[4]\ => s_axi_rid(4),
\s_axi_rid[5]\ => s_axi_rid(5),
\s_axi_rid[6]\ => s_axi_rid(6),
\s_axi_rid[7]\ => s_axi_rid(7),
\s_axi_rid[8]\ => s_axi_rid(8),
\s_axi_rid[9]\ => s_axi_rid(9),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wlast(0) => \^s_axi_wlast\(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_wlast : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arid : out STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rid : in STD_LOGIC_VECTOR ( 47 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 127 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_rlast : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 47 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_CONNECTIVITY_MODE : integer;
attribute C_CONNECTIVITY_MODE of inst : label is 1;
attribute C_DEBUG : integer;
attribute C_DEBUG of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_M_AXI_ADDR_WIDTH : string;
attribute C_M_AXI_ADDR_WIDTH of inst : label is "128'b00000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000";
attribute C_M_AXI_BASE_ADDR : string;
attribute C_M_AXI_BASE_ADDR of inst : label is "256'b0000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000100001010000000000000000000000000000000000000000000000000000000010000010010000100000000000000000000000000000000000000000000000001000001001000000000000000000000";
attribute C_M_AXI_READ_CONNECTIVITY : string;
attribute C_M_AXI_READ_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_READ_ISSUING : string;
attribute C_M_AXI_READ_ISSUING of inst : label is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_M_AXI_SECURE : string;
attribute C_M_AXI_SECURE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute C_M_AXI_WRITE_CONNECTIVITY : string;
attribute C_M_AXI_WRITE_CONNECTIVITY of inst : label is "128'b00000000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001";
attribute C_M_AXI_WRITE_ISSUING : string;
attribute C_M_AXI_WRITE_ISSUING of inst : label is "128'b00000000000000000000000000001000000000000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000";
attribute C_NUM_ADDR_RANGES : integer;
attribute C_NUM_ADDR_RANGES of inst : label is 1;
attribute C_NUM_MASTER_SLOTS : integer;
attribute C_NUM_MASTER_SLOTS of inst : label is 4;
attribute C_NUM_SLAVE_SLOTS : integer;
attribute C_NUM_SLAVE_SLOTS of inst : label is 1;
attribute C_R_REGISTER : integer;
attribute C_R_REGISTER of inst : label is 0;
attribute C_S_AXI_ARB_PRIORITY : integer;
attribute C_S_AXI_ARB_PRIORITY of inst : label is 0;
attribute C_S_AXI_BASE_ID : integer;
attribute C_S_AXI_BASE_ID of inst : label is 0;
attribute C_S_AXI_READ_ACCEPTANCE : integer;
attribute C_S_AXI_READ_ACCEPTANCE of inst : label is 8;
attribute C_S_AXI_SINGLE_THREAD : integer;
attribute C_S_AXI_SINGLE_THREAD of inst : label is 0;
attribute C_S_AXI_THREAD_ID_WIDTH : integer;
attribute C_S_AXI_THREAD_ID_WIDTH of inst : label is 12;
attribute C_S_AXI_WRITE_ACCEPTANCE : integer;
attribute C_S_AXI_WRITE_ACCEPTANCE of inst : label is 8;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_ADDR_DECODE : integer;
attribute P_ADDR_DECODE of inst : label is 1;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_FAMILY : string;
attribute P_FAMILY of inst : label is "zynq";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_LEN : integer;
attribute P_LEN of inst : label is 8;
attribute P_LOCK : integer;
attribute P_LOCK of inst : label is 1;
attribute P_M_AXI_ERR_MODE : string;
attribute P_M_AXI_ERR_MODE of inst : label is "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
attribute P_M_AXI_SUPPORTS_READ : string;
attribute P_M_AXI_SUPPORTS_READ of inst : label is "4'b1111";
attribute P_M_AXI_SUPPORTS_WRITE : string;
attribute P_M_AXI_SUPPORTS_WRITE of inst : label is "4'b1111";
attribute P_ONES : string;
attribute P_ONES of inst : label is "65'b11111111111111111111111111111111111111111111111111111111111111111";
attribute P_RANGE_CHECK : integer;
attribute P_RANGE_CHECK of inst : label is 1;
attribute P_S_AXI_BASE_ID : string;
attribute P_S_AXI_BASE_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000000000000000";
attribute P_S_AXI_HIGH_ID : string;
attribute P_S_AXI_HIGH_ID of inst : label is "64'b0000000000000000000000000000000000000000000000000000111111111111";
attribute P_S_AXI_SUPPORTS_READ : string;
attribute P_S_AXI_SUPPORTS_READ of inst : label is "1'b1";
attribute P_S_AXI_SUPPORTS_WRITE : string;
attribute P_S_AXI_SUPPORTS_WRITE of inst : label is "1'b1";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(127 downto 0) => m_axi_araddr(127 downto 0),
m_axi_arburst(7 downto 0) => m_axi_arburst(7 downto 0),
m_axi_arcache(15 downto 0) => m_axi_arcache(15 downto 0),
m_axi_arid(47 downto 0) => m_axi_arid(47 downto 0),
m_axi_arlen(31 downto 0) => m_axi_arlen(31 downto 0),
m_axi_arlock(3 downto 0) => m_axi_arlock(3 downto 0),
m_axi_arprot(11 downto 0) => m_axi_arprot(11 downto 0),
m_axi_arqos(15 downto 0) => m_axi_arqos(15 downto 0),
m_axi_arready(3 downto 0) => m_axi_arready(3 downto 0),
m_axi_arregion(15 downto 0) => m_axi_arregion(15 downto 0),
m_axi_arsize(11 downto 0) => m_axi_arsize(11 downto 0),
m_axi_aruser(3 downto 0) => NLW_inst_m_axi_aruser_UNCONNECTED(3 downto 0),
m_axi_arvalid(3 downto 0) => m_axi_arvalid(3 downto 0),
m_axi_awaddr(127 downto 0) => m_axi_awaddr(127 downto 0),
m_axi_awburst(7 downto 0) => m_axi_awburst(7 downto 0),
m_axi_awcache(15 downto 0) => m_axi_awcache(15 downto 0),
m_axi_awid(47 downto 0) => m_axi_awid(47 downto 0),
m_axi_awlen(31 downto 0) => m_axi_awlen(31 downto 0),
m_axi_awlock(3 downto 0) => m_axi_awlock(3 downto 0),
m_axi_awprot(11 downto 0) => m_axi_awprot(11 downto 0),
m_axi_awqos(15 downto 0) => m_axi_awqos(15 downto 0),
m_axi_awready(3 downto 0) => m_axi_awready(3 downto 0),
m_axi_awregion(15 downto 0) => m_axi_awregion(15 downto 0),
m_axi_awsize(11 downto 0) => m_axi_awsize(11 downto 0),
m_axi_awuser(3 downto 0) => NLW_inst_m_axi_awuser_UNCONNECTED(3 downto 0),
m_axi_awvalid(3 downto 0) => m_axi_awvalid(3 downto 0),
m_axi_bid(47 downto 0) => m_axi_bid(47 downto 0),
m_axi_bready(3 downto 0) => m_axi_bready(3 downto 0),
m_axi_bresp(7 downto 0) => m_axi_bresp(7 downto 0),
m_axi_buser(3 downto 0) => B"0000",
m_axi_bvalid(3 downto 0) => m_axi_bvalid(3 downto 0),
m_axi_rdata(127 downto 0) => m_axi_rdata(127 downto 0),
m_axi_rid(47 downto 0) => m_axi_rid(47 downto 0),
m_axi_rlast(3 downto 0) => m_axi_rlast(3 downto 0),
m_axi_rready(3 downto 0) => m_axi_rready(3 downto 0),
m_axi_rresp(7 downto 0) => m_axi_rresp(7 downto 0),
m_axi_ruser(3 downto 0) => B"0000",
m_axi_rvalid(3 downto 0) => m_axi_rvalid(3 downto 0),
m_axi_wdata(127 downto 0) => m_axi_wdata(127 downto 0),
m_axi_wid(47 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(47 downto 0),
m_axi_wlast(3 downto 0) => m_axi_wlast(3 downto 0),
m_axi_wready(3 downto 0) => m_axi_wready(3 downto 0),
m_axi_wstrb(15 downto 0) => m_axi_wstrb(15 downto 0),
m_axi_wuser(3 downto 0) => NLW_inst_m_axi_wuser_UNCONNECTED(3 downto 0),
m_axi_wvalid(3 downto 0) => m_axi_wvalid(3 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready(0) => s_axi_arready(0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid(0) => s_axi_arvalid(0),
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready(0) => s_axi_awready(0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid(0) => s_axi_awvalid(0),
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready(0) => s_axi_bready(0),
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid(0) => s_axi_bvalid(0),
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast(0) => s_axi_rlast(0),
s_axi_rready(0) => s_axi_rready(0),
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid(0) => s_axi_rvalid(0),
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast(0) => s_axi_wlast(0),
s_axi_wready(0) => s_axi_wready(0),
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid(0) => s_axi_wvalid(0)
);
end STRUCTURE;
| mit | 74fe2f02c4639d3d6b078e21f271aa29 | 0.554649 | 2.63306 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/synth/ip_design.vhd | 1 | 177,183 | --Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
--Date : Wed Oct 18 15:14:15 2017
--Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
--Command : generate_target ip_design.bd
--Design : ip_design
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_XB6WOP is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_XB6WOP;
architecture STRUCTURE of m00_couplers_imp_XB6WOP is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= m00_couplers_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= m00_couplers_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_couplers_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_couplers_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1CTDBQ9 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m01_couplers_imp_1CTDBQ9;
architecture STRUCTURE of m01_couplers_imp_1CTDBQ9 is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m01_couplers_to_m01_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m01_couplers_to_m01_couplers_AWVALID(0);
M_AXI_bready(0) <= m01_couplers_to_m01_couplers_BREADY(0);
M_AXI_rready(0) <= m01_couplers_to_m01_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m01_couplers_to_m01_couplers_WVALID(0);
S_AXI_arready(0) <= m01_couplers_to_m01_couplers_ARREADY(0);
S_AXI_awready(0) <= m01_couplers_to_m01_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m01_couplers_to_m01_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m01_couplers_to_m01_couplers_RVALID(0);
S_AXI_wready(0) <= m01_couplers_to_m01_couplers_WREADY(0);
m01_couplers_to_m01_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_couplers_ARREADY(0) <= M_AXI_arready(0);
m01_couplers_to_m01_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m01_couplers_to_m01_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_couplers_AWREADY(0) <= M_AXI_awready(0);
m01_couplers_to_m01_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m01_couplers_to_m01_couplers_BREADY(0) <= S_AXI_bready(0);
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID(0) <= M_AXI_bvalid(0);
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY(0) <= S_AXI_rready(0);
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID(0) <= M_AXI_rvalid(0);
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY(0) <= M_AXI_wready(0);
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_3J4E14 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m02_couplers_imp_3J4E14;
architecture STRUCTURE of m02_couplers_imp_3J4E14 is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(31 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(31 downto 0);
M_AXI_arvalid(0) <= m02_couplers_to_m02_couplers_ARVALID(0);
M_AXI_awaddr(31 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(31 downto 0);
M_AXI_awvalid(0) <= m02_couplers_to_m02_couplers_AWVALID(0);
M_AXI_bready(0) <= m02_couplers_to_m02_couplers_BREADY(0);
M_AXI_rready(0) <= m02_couplers_to_m02_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m02_couplers_to_m02_couplers_WVALID(0);
S_AXI_arready(0) <= m02_couplers_to_m02_couplers_ARREADY(0);
S_AXI_awready(0) <= m02_couplers_to_m02_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m02_couplers_to_m02_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m02_couplers_to_m02_couplers_RVALID(0);
S_AXI_wready(0) <= m02_couplers_to_m02_couplers_WREADY(0);
m02_couplers_to_m02_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m02_couplers_to_m02_couplers_ARREADY(0) <= M_AXI_arready(0);
m02_couplers_to_m02_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m02_couplers_to_m02_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m02_couplers_to_m02_couplers_AWREADY(0) <= M_AXI_awready(0);
m02_couplers_to_m02_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m02_couplers_to_m02_couplers_BREADY(0) <= S_AXI_bready(0);
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID(0) <= M_AXI_bvalid(0);
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY(0) <= S_AXI_rready(0);
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID(0) <= M_AXI_rvalid(0);
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY(0) <= M_AXI_wready(0);
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m03_couplers_imp_1OV3LN4 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m03_couplers_imp_1OV3LN4;
architecture STRUCTURE of m03_couplers_imp_1OV3LN4 is
signal m03_couplers_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_ARREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_ARVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_AWREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_AWVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_BVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_RREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_m03_couplers_RVALID : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_m03_couplers_WREADY : STD_LOGIC;
signal m03_couplers_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_m03_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m03_couplers_to_m03_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m03_couplers_to_m03_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m03_couplers_to_m03_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m03_couplers_to_m03_couplers_AWVALID;
M_AXI_bready <= m03_couplers_to_m03_couplers_BREADY;
M_AXI_rready <= m03_couplers_to_m03_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m03_couplers_to_m03_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m03_couplers_to_m03_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m03_couplers_to_m03_couplers_WVALID;
S_AXI_arready <= m03_couplers_to_m03_couplers_ARREADY;
S_AXI_awready <= m03_couplers_to_m03_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m03_couplers_to_m03_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m03_couplers_to_m03_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m03_couplers_to_m03_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m03_couplers_to_m03_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m03_couplers_to_m03_couplers_RVALID;
S_AXI_wready <= m03_couplers_to_m03_couplers_WREADY;
m03_couplers_to_m03_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m03_couplers_to_m03_couplers_ARREADY <= M_AXI_arready;
m03_couplers_to_m03_couplers_ARVALID <= S_AXI_arvalid;
m03_couplers_to_m03_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m03_couplers_to_m03_couplers_AWREADY <= M_AXI_awready;
m03_couplers_to_m03_couplers_AWVALID <= S_AXI_awvalid;
m03_couplers_to_m03_couplers_BREADY <= S_AXI_bready;
m03_couplers_to_m03_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m03_couplers_to_m03_couplers_BVALID <= M_AXI_bvalid;
m03_couplers_to_m03_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m03_couplers_to_m03_couplers_RREADY <= S_AXI_rready;
m03_couplers_to_m03_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m03_couplers_to_m03_couplers_RVALID <= M_AXI_rvalid;
m03_couplers_to_m03_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m03_couplers_to_m03_couplers_WREADY <= M_AXI_wready;
m03_couplers_to_m03_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m03_couplers_to_m03_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m04_couplers_imp_14CCC2J is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m04_couplers_imp_14CCC2J;
architecture STRUCTURE of m04_couplers_imp_14CCC2J is
signal m04_couplers_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_ARREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_ARVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_AWREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_AWVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_BVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_RREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_m04_couplers_RVALID : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_m04_couplers_WREADY : STD_LOGIC;
signal m04_couplers_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_m04_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m04_couplers_to_m04_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m04_couplers_to_m04_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m04_couplers_to_m04_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m04_couplers_to_m04_couplers_AWVALID;
M_AXI_bready <= m04_couplers_to_m04_couplers_BREADY;
M_AXI_rready <= m04_couplers_to_m04_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m04_couplers_to_m04_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m04_couplers_to_m04_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m04_couplers_to_m04_couplers_WVALID;
S_AXI_arready <= m04_couplers_to_m04_couplers_ARREADY;
S_AXI_awready <= m04_couplers_to_m04_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m04_couplers_to_m04_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m04_couplers_to_m04_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m04_couplers_to_m04_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m04_couplers_to_m04_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m04_couplers_to_m04_couplers_RVALID;
S_AXI_wready <= m04_couplers_to_m04_couplers_WREADY;
m04_couplers_to_m04_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m04_couplers_to_m04_couplers_ARREADY <= M_AXI_arready;
m04_couplers_to_m04_couplers_ARVALID <= S_AXI_arvalid;
m04_couplers_to_m04_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m04_couplers_to_m04_couplers_AWREADY <= M_AXI_awready;
m04_couplers_to_m04_couplers_AWVALID <= S_AXI_awvalid;
m04_couplers_to_m04_couplers_BREADY <= S_AXI_bready;
m04_couplers_to_m04_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m04_couplers_to_m04_couplers_BVALID <= M_AXI_bvalid;
m04_couplers_to_m04_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m04_couplers_to_m04_couplers_RREADY <= S_AXI_rready;
m04_couplers_to_m04_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m04_couplers_to_m04_couplers_RVALID <= M_AXI_rvalid;
m04_couplers_to_m04_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m04_couplers_to_m04_couplers_WREADY <= M_AXI_wready;
m04_couplers_to_m04_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m04_couplers_to_m04_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m05_couplers_imp_JKHUF7 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m05_couplers_imp_JKHUF7;
architecture STRUCTURE of m05_couplers_imp_JKHUF7 is
signal m05_couplers_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_ARREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_ARVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_AWREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_AWVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_BVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_RREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_m05_couplers_RVALID : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_m05_couplers_WREADY : STD_LOGIC;
signal m05_couplers_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_m05_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= m05_couplers_to_m05_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= m05_couplers_to_m05_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= m05_couplers_to_m05_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= m05_couplers_to_m05_couplers_AWVALID;
M_AXI_bready <= m05_couplers_to_m05_couplers_BREADY;
M_AXI_rready <= m05_couplers_to_m05_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m05_couplers_to_m05_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m05_couplers_to_m05_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m05_couplers_to_m05_couplers_WVALID;
S_AXI_arready <= m05_couplers_to_m05_couplers_ARREADY;
S_AXI_awready <= m05_couplers_to_m05_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m05_couplers_to_m05_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m05_couplers_to_m05_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m05_couplers_to_m05_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m05_couplers_to_m05_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m05_couplers_to_m05_couplers_RVALID;
S_AXI_wready <= m05_couplers_to_m05_couplers_WREADY;
m05_couplers_to_m05_couplers_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m05_couplers_to_m05_couplers_ARREADY <= M_AXI_arready;
m05_couplers_to_m05_couplers_ARVALID <= S_AXI_arvalid;
m05_couplers_to_m05_couplers_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m05_couplers_to_m05_couplers_AWREADY <= M_AXI_awready;
m05_couplers_to_m05_couplers_AWVALID <= S_AXI_awvalid;
m05_couplers_to_m05_couplers_BREADY <= S_AXI_bready;
m05_couplers_to_m05_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m05_couplers_to_m05_couplers_BVALID <= M_AXI_bvalid;
m05_couplers_to_m05_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m05_couplers_to_m05_couplers_RREADY <= S_AXI_rready;
m05_couplers_to_m05_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m05_couplers_to_m05_couplers_RVALID <= M_AXI_rvalid;
m05_couplers_to_m05_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m05_couplers_to_m05_couplers_WREADY <= M_AXI_wready;
m05_couplers_to_m05_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m05_couplers_to_m05_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1Q6ZP2D is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC;
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC;
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1Q6ZP2D;
architecture STRUCTURE of s00_couplers_imp_1Q6ZP2D is
component ip_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component ip_design_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1 <= S_ARESETN;
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component ip_design_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1,
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_ps7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC;
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC;
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC;
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC;
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M03_ACLK : in STD_LOGIC;
M03_ARESETN : in STD_LOGIC;
M03_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_arready : in STD_LOGIC;
M03_AXI_arvalid : out STD_LOGIC;
M03_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_awready : in STD_LOGIC;
M03_AXI_awvalid : out STD_LOGIC;
M03_AXI_bready : out STD_LOGIC;
M03_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_bvalid : in STD_LOGIC;
M03_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_rready : out STD_LOGIC;
M03_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M03_AXI_rvalid : in STD_LOGIC;
M03_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M03_AXI_wready : in STD_LOGIC;
M03_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M03_AXI_wvalid : out STD_LOGIC;
M04_ACLK : in STD_LOGIC;
M04_ARESETN : in STD_LOGIC;
M04_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_arready : in STD_LOGIC;
M04_AXI_arvalid : out STD_LOGIC;
M04_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_awready : in STD_LOGIC;
M04_AXI_awvalid : out STD_LOGIC;
M04_AXI_bready : out STD_LOGIC;
M04_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_bvalid : in STD_LOGIC;
M04_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_rready : out STD_LOGIC;
M04_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M04_AXI_rvalid : in STD_LOGIC;
M04_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M04_AXI_wready : in STD_LOGIC;
M04_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M04_AXI_wvalid : out STD_LOGIC;
M05_ACLK : in STD_LOGIC;
M05_ARESETN : in STD_LOGIC;
M05_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_arready : in STD_LOGIC;
M05_AXI_arvalid : out STD_LOGIC;
M05_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_awready : in STD_LOGIC;
M05_AXI_awvalid : out STD_LOGIC;
M05_AXI_bready : out STD_LOGIC;
M05_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_bvalid : in STD_LOGIC;
M05_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_rready : out STD_LOGIC;
M05_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M05_AXI_rvalid : in STD_LOGIC;
M05_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M05_AXI_wready : in STD_LOGIC;
M05_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M05_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC;
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end ip_design_ps7_0_axi_periph_0;
architecture STRUCTURE of ip_design_ps7_0_axi_periph_0 is
component ip_design_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 23 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 17 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 191 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component ip_design_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC;
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC;
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC;
signal M03_ACLK_1 : STD_LOGIC;
signal M03_ARESETN_1 : STD_LOGIC;
signal M04_ACLK_1 : STD_LOGIC;
signal M04_ARESETN_1 : STD_LOGIC;
signal M05_ACLK_1 : STD_LOGIC;
signal M05_ARESETN_1 : STD_LOGIC;
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC;
signal m00_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m02_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m03_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC;
signal m03_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m03_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC;
signal m04_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m04_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_ARREADY : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_ARVALID : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_AWREADY : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_AWVALID : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_BREADY : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_BVALID : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_RREADY : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_RVALID : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_WREADY : STD_LOGIC;
signal m05_couplers_to_ps7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m05_couplers_to_ps7_0_axi_periph_WVALID : STD_LOGIC;
signal ps7_0_axi_periph_ACLK_net : STD_LOGIC;
signal ps7_0_axi_periph_ARESETN_net : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m03_couplers_ARADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m03_couplers_ARVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_AWADDR : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m03_couplers_AWVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_BVALID : STD_LOGIC;
signal xbar_to_m03_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m03_couplers_RREADY : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m03_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m03_couplers_RVALID : STD_LOGIC;
signal xbar_to_m03_couplers_WDATA : STD_LOGIC_VECTOR ( 127 downto 96 );
signal xbar_to_m03_couplers_WREADY : STD_LOGIC;
signal xbar_to_m03_couplers_WSTRB : STD_LOGIC_VECTOR ( 15 downto 12 );
signal xbar_to_m03_couplers_WVALID : STD_LOGIC_VECTOR ( 3 to 3 );
signal xbar_to_m04_couplers_ARADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m04_couplers_ARVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_AWADDR : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m04_couplers_AWVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_BVALID : STD_LOGIC;
signal xbar_to_m04_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m04_couplers_RREADY : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m04_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m04_couplers_RVALID : STD_LOGIC;
signal xbar_to_m04_couplers_WDATA : STD_LOGIC_VECTOR ( 159 downto 128 );
signal xbar_to_m04_couplers_WREADY : STD_LOGIC;
signal xbar_to_m04_couplers_WSTRB : STD_LOGIC_VECTOR ( 19 downto 16 );
signal xbar_to_m04_couplers_WVALID : STD_LOGIC_VECTOR ( 4 to 4 );
signal xbar_to_m05_couplers_ARADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m05_couplers_ARVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_AWADDR : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m05_couplers_AWVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_BVALID : STD_LOGIC;
signal xbar_to_m05_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m05_couplers_RREADY : STD_LOGIC_VECTOR ( 5 to 5 );
signal xbar_to_m05_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m05_couplers_RVALID : STD_LOGIC;
signal xbar_to_m05_couplers_WDATA : STD_LOGIC_VECTOR ( 191 downto 160 );
signal xbar_to_m05_couplers_WREADY : STD_LOGIC;
signal xbar_to_m05_couplers_WSTRB : STD_LOGIC_VECTOR ( 23 downto 20 );
signal xbar_to_m05_couplers_WVALID : STD_LOGIC_VECTOR ( 5 to 5 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 3 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 17 downto 3 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1 <= M00_ARESETN;
M00_AXI_araddr(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_ps7_0_axi_periph_ARPROT(2 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_ps7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_ps7_0_axi_periph_AWPROT(2 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_ps7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_ps7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_ps7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_ps7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1 <= M01_ARESETN;
M01_AXI_araddr(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M01_AXI_arvalid(0) <= m01_couplers_to_ps7_0_axi_periph_ARVALID(0);
M01_AXI_awaddr(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M01_AXI_awvalid(0) <= m01_couplers_to_ps7_0_axi_periph_AWVALID(0);
M01_AXI_bready(0) <= m01_couplers_to_ps7_0_axi_periph_BREADY(0);
M01_AXI_rready(0) <= m01_couplers_to_ps7_0_axi_periph_RREADY(0);
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid(0) <= m01_couplers_to_ps7_0_axi_periph_WVALID(0);
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1 <= M02_ARESETN;
M02_AXI_araddr(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M02_AXI_arvalid(0) <= m02_couplers_to_ps7_0_axi_periph_ARVALID(0);
M02_AXI_awaddr(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M02_AXI_awvalid(0) <= m02_couplers_to_ps7_0_axi_periph_AWVALID(0);
M02_AXI_bready(0) <= m02_couplers_to_ps7_0_axi_periph_BREADY(0);
M02_AXI_rready(0) <= m02_couplers_to_ps7_0_axi_periph_RREADY(0);
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid(0) <= m02_couplers_to_ps7_0_axi_periph_WVALID(0);
M03_ACLK_1 <= M03_ACLK;
M03_ARESETN_1 <= M03_ARESETN;
M03_AXI_araddr(31 downto 0) <= m03_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M03_AXI_arvalid <= m03_couplers_to_ps7_0_axi_periph_ARVALID;
M03_AXI_awaddr(31 downto 0) <= m03_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M03_AXI_awvalid <= m03_couplers_to_ps7_0_axi_periph_AWVALID;
M03_AXI_bready <= m03_couplers_to_ps7_0_axi_periph_BREADY;
M03_AXI_rready <= m03_couplers_to_ps7_0_axi_periph_RREADY;
M03_AXI_wdata(31 downto 0) <= m03_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M03_AXI_wstrb(3 downto 0) <= m03_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M03_AXI_wvalid <= m03_couplers_to_ps7_0_axi_periph_WVALID;
M04_ACLK_1 <= M04_ACLK;
M04_ARESETN_1 <= M04_ARESETN;
M04_AXI_araddr(31 downto 0) <= m04_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M04_AXI_arvalid <= m04_couplers_to_ps7_0_axi_periph_ARVALID;
M04_AXI_awaddr(31 downto 0) <= m04_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M04_AXI_awvalid <= m04_couplers_to_ps7_0_axi_periph_AWVALID;
M04_AXI_bready <= m04_couplers_to_ps7_0_axi_periph_BREADY;
M04_AXI_rready <= m04_couplers_to_ps7_0_axi_periph_RREADY;
M04_AXI_wdata(31 downto 0) <= m04_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M04_AXI_wstrb(3 downto 0) <= m04_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M04_AXI_wvalid <= m04_couplers_to_ps7_0_axi_periph_WVALID;
M05_ACLK_1 <= M05_ACLK;
M05_ARESETN_1 <= M05_ARESETN;
M05_AXI_araddr(31 downto 0) <= m05_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0);
M05_AXI_arvalid <= m05_couplers_to_ps7_0_axi_periph_ARVALID;
M05_AXI_awaddr(31 downto 0) <= m05_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0);
M05_AXI_awvalid <= m05_couplers_to_ps7_0_axi_periph_AWVALID;
M05_AXI_bready <= m05_couplers_to_ps7_0_axi_periph_BREADY;
M05_AXI_rready <= m05_couplers_to_ps7_0_axi_periph_RREADY;
M05_AXI_wdata(31 downto 0) <= m05_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0);
M05_AXI_wstrb(3 downto 0) <= m05_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0);
M05_AXI_wvalid <= m05_couplers_to_ps7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1 <= S00_ARESETN;
S00_AXI_arready <= ps7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= ps7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= ps7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= ps7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= ps7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= ps7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_ps7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_ps7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_ps7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_ps7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_ps7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_ps7_0_axi_periph_ARREADY(0) <= M01_AXI_arready(0);
m01_couplers_to_ps7_0_axi_periph_AWREADY(0) <= M01_AXI_awready(0);
m01_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_ps7_0_axi_periph_BVALID(0) <= M01_AXI_bvalid(0);
m01_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_ps7_0_axi_periph_RVALID(0) <= M01_AXI_rvalid(0);
m01_couplers_to_ps7_0_axi_periph_WREADY(0) <= M01_AXI_wready(0);
m02_couplers_to_ps7_0_axi_periph_ARREADY(0) <= M02_AXI_arready(0);
m02_couplers_to_ps7_0_axi_periph_AWREADY(0) <= M02_AXI_awready(0);
m02_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_ps7_0_axi_periph_BVALID(0) <= M02_AXI_bvalid(0);
m02_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_ps7_0_axi_periph_RVALID(0) <= M02_AXI_rvalid(0);
m02_couplers_to_ps7_0_axi_periph_WREADY(0) <= M02_AXI_wready(0);
m03_couplers_to_ps7_0_axi_periph_ARREADY <= M03_AXI_arready;
m03_couplers_to_ps7_0_axi_periph_AWREADY <= M03_AXI_awready;
m03_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M03_AXI_bresp(1 downto 0);
m03_couplers_to_ps7_0_axi_periph_BVALID <= M03_AXI_bvalid;
m03_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M03_AXI_rdata(31 downto 0);
m03_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M03_AXI_rresp(1 downto 0);
m03_couplers_to_ps7_0_axi_periph_RVALID <= M03_AXI_rvalid;
m03_couplers_to_ps7_0_axi_periph_WREADY <= M03_AXI_wready;
m04_couplers_to_ps7_0_axi_periph_ARREADY <= M04_AXI_arready;
m04_couplers_to_ps7_0_axi_periph_AWREADY <= M04_AXI_awready;
m04_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M04_AXI_bresp(1 downto 0);
m04_couplers_to_ps7_0_axi_periph_BVALID <= M04_AXI_bvalid;
m04_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M04_AXI_rdata(31 downto 0);
m04_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M04_AXI_rresp(1 downto 0);
m04_couplers_to_ps7_0_axi_periph_RVALID <= M04_AXI_rvalid;
m04_couplers_to_ps7_0_axi_periph_WREADY <= M04_AXI_wready;
m05_couplers_to_ps7_0_axi_periph_ARREADY <= M05_AXI_arready;
m05_couplers_to_ps7_0_axi_periph_AWREADY <= M05_AXI_awready;
m05_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0) <= M05_AXI_bresp(1 downto 0);
m05_couplers_to_ps7_0_axi_periph_BVALID <= M05_AXI_bvalid;
m05_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0) <= M05_AXI_rdata(31 downto 0);
m05_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0) <= M05_AXI_rresp(1 downto 0);
m05_couplers_to_ps7_0_axi_periph_RVALID <= M05_AXI_rvalid;
m05_couplers_to_ps7_0_axi_periph_WREADY <= M05_AXI_wready;
ps7_0_axi_periph_ACLK_net <= ACLK;
ps7_0_axi_periph_ARESETN_net <= ARESETN;
ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
ps7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
ps7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
ps7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
ps7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
ps7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_XB6WOP
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN => M00_ARESETN_1,
M_AXI_araddr(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_ps7_0_axi_periph_ARPROT(2 downto 0),
M_AXI_arready(0) => m00_couplers_to_ps7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_ps7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_ps7_0_axi_periph_AWPROT(2 downto 0),
M_AXI_awready(0) => m00_couplers_to_ps7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_ps7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_ps7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_ps7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_ps7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_ps7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_ps7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_ps7_0_axi_periph_WVALID(0),
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1CTDBQ9
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN => M01_ARESETN_1,
M_AXI_araddr(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m01_couplers_to_ps7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m01_couplers_to_ps7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m01_couplers_to_ps7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m01_couplers_to_ps7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m01_couplers_to_ps7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m01_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m01_couplers_to_ps7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m01_couplers_to_ps7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m01_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m01_couplers_to_ps7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m01_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m01_couplers_to_ps7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m01_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m01_couplers_to_ps7_0_axi_periph_WVALID(0),
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arready(0) => xbar_to_m01_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awready(0) => xbar_to_m01_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready(0) => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m01_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m01_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready(0) => xbar_to_m01_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid(0) => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_3J4E14
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN => M02_ARESETN_1,
M_AXI_araddr(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready(0) => m02_couplers_to_ps7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m02_couplers_to_ps7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready(0) => m02_couplers_to_ps7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m02_couplers_to_ps7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m02_couplers_to_ps7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m02_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m02_couplers_to_ps7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m02_couplers_to_ps7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m02_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m02_couplers_to_ps7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m02_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m02_couplers_to_ps7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m02_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m02_couplers_to_ps7_0_axi_periph_WVALID(0),
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m02_couplers_ARADDR(95 downto 64),
S_AXI_arready(0) => xbar_to_m02_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(31 downto 0) => xbar_to_m02_couplers_AWADDR(95 downto 64),
S_AXI_awready(0) => xbar_to_m02_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready(0) => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m02_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m02_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready(0) => xbar_to_m02_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid(0) => xbar_to_m02_couplers_WVALID(2)
);
m03_couplers: entity work.m03_couplers_imp_1OV3LN4
port map (
M_ACLK => M03_ACLK_1,
M_ARESETN => M03_ARESETN_1,
M_AXI_araddr(31 downto 0) => m03_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m03_couplers_to_ps7_0_axi_periph_ARREADY,
M_AXI_arvalid => m03_couplers_to_ps7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m03_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m03_couplers_to_ps7_0_axi_periph_AWREADY,
M_AXI_awvalid => m03_couplers_to_ps7_0_axi_periph_AWVALID,
M_AXI_bready => m03_couplers_to_ps7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m03_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m03_couplers_to_ps7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m03_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m03_couplers_to_ps7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m03_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m03_couplers_to_ps7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m03_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m03_couplers_to_ps7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m03_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m03_couplers_to_ps7_0_axi_periph_WVALID,
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m03_couplers_ARADDR(127 downto 96),
S_AXI_arready => xbar_to_m03_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m03_couplers_ARVALID(3),
S_AXI_awaddr(31 downto 0) => xbar_to_m03_couplers_AWADDR(127 downto 96),
S_AXI_awready => xbar_to_m03_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m03_couplers_AWVALID(3),
S_AXI_bready => xbar_to_m03_couplers_BREADY(3),
S_AXI_bresp(1 downto 0) => xbar_to_m03_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m03_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m03_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m03_couplers_RREADY(3),
S_AXI_rresp(1 downto 0) => xbar_to_m03_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m03_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m03_couplers_WDATA(127 downto 96),
S_AXI_wready => xbar_to_m03_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m03_couplers_WSTRB(15 downto 12),
S_AXI_wvalid => xbar_to_m03_couplers_WVALID(3)
);
m04_couplers: entity work.m04_couplers_imp_14CCC2J
port map (
M_ACLK => M04_ACLK_1,
M_ARESETN => M04_ARESETN_1,
M_AXI_araddr(31 downto 0) => m04_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m04_couplers_to_ps7_0_axi_periph_ARREADY,
M_AXI_arvalid => m04_couplers_to_ps7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m04_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m04_couplers_to_ps7_0_axi_periph_AWREADY,
M_AXI_awvalid => m04_couplers_to_ps7_0_axi_periph_AWVALID,
M_AXI_bready => m04_couplers_to_ps7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m04_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m04_couplers_to_ps7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m04_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m04_couplers_to_ps7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m04_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m04_couplers_to_ps7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m04_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m04_couplers_to_ps7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m04_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m04_couplers_to_ps7_0_axi_periph_WVALID,
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m04_couplers_ARADDR(159 downto 128),
S_AXI_arready => xbar_to_m04_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m04_couplers_ARVALID(4),
S_AXI_awaddr(31 downto 0) => xbar_to_m04_couplers_AWADDR(159 downto 128),
S_AXI_awready => xbar_to_m04_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m04_couplers_AWVALID(4),
S_AXI_bready => xbar_to_m04_couplers_BREADY(4),
S_AXI_bresp(1 downto 0) => xbar_to_m04_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m04_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m04_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m04_couplers_RREADY(4),
S_AXI_rresp(1 downto 0) => xbar_to_m04_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m04_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m04_couplers_WDATA(159 downto 128),
S_AXI_wready => xbar_to_m04_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m04_couplers_WSTRB(19 downto 16),
S_AXI_wvalid => xbar_to_m04_couplers_WVALID(4)
);
m05_couplers: entity work.m05_couplers_imp_JKHUF7
port map (
M_ACLK => M05_ACLK_1,
M_ARESETN => M05_ARESETN_1,
M_AXI_araddr(31 downto 0) => m05_couplers_to_ps7_0_axi_periph_ARADDR(31 downto 0),
M_AXI_arready => m05_couplers_to_ps7_0_axi_periph_ARREADY,
M_AXI_arvalid => m05_couplers_to_ps7_0_axi_periph_ARVALID,
M_AXI_awaddr(31 downto 0) => m05_couplers_to_ps7_0_axi_periph_AWADDR(31 downto 0),
M_AXI_awready => m05_couplers_to_ps7_0_axi_periph_AWREADY,
M_AXI_awvalid => m05_couplers_to_ps7_0_axi_periph_AWVALID,
M_AXI_bready => m05_couplers_to_ps7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m05_couplers_to_ps7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m05_couplers_to_ps7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m05_couplers_to_ps7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m05_couplers_to_ps7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m05_couplers_to_ps7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m05_couplers_to_ps7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m05_couplers_to_ps7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m05_couplers_to_ps7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m05_couplers_to_ps7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m05_couplers_to_ps7_0_axi_periph_WVALID,
S_ACLK => ps7_0_axi_periph_ACLK_net,
S_ARESETN => ps7_0_axi_periph_ARESETN_net,
S_AXI_araddr(31 downto 0) => xbar_to_m05_couplers_ARADDR(191 downto 160),
S_AXI_arready => xbar_to_m05_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m05_couplers_ARVALID(5),
S_AXI_awaddr(31 downto 0) => xbar_to_m05_couplers_AWADDR(191 downto 160),
S_AXI_awready => xbar_to_m05_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m05_couplers_AWVALID(5),
S_AXI_bready => xbar_to_m05_couplers_BREADY(5),
S_AXI_bresp(1 downto 0) => xbar_to_m05_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m05_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m05_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m05_couplers_RREADY(5),
S_AXI_rresp(1 downto 0) => xbar_to_m05_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m05_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m05_couplers_WDATA(191 downto 160),
S_AXI_wready => xbar_to_m05_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m05_couplers_WSTRB(23 downto 20),
S_AXI_wvalid => xbar_to_m05_couplers_WVALID(5)
);
s00_couplers: entity work.s00_couplers_imp_1Q6ZP2D
port map (
M_ACLK => ps7_0_axi_periph_ACLK_net,
M_ARESETN => ps7_0_axi_periph_ARESETN_net,
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN => S00_ARESETN_1,
S_AXI_araddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => ps7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => ps7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => ps7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => ps7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => ps7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => ps7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => ps7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => ps7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => ps7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => ps7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => ps7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => ps7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => ps7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => ps7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => ps7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => ps7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component ip_design_xbar_0
port map (
aclk => ps7_0_axi_periph_ACLK_net,
aresetn => ps7_0_axi_periph_ARESETN_net,
m_axi_araddr(191 downto 160) => xbar_to_m05_couplers_ARADDR(191 downto 160),
m_axi_araddr(159 downto 128) => xbar_to_m04_couplers_ARADDR(159 downto 128),
m_axi_araddr(127 downto 96) => xbar_to_m03_couplers_ARADDR(127 downto 96),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(17 downto 3) => NLW_xbar_m_axi_arprot_UNCONNECTED(17 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready(5) => xbar_to_m05_couplers_ARREADY,
m_axi_arready(4) => xbar_to_m04_couplers_ARREADY,
m_axi_arready(3) => xbar_to_m03_couplers_ARREADY,
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY(0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY(0),
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(5) => xbar_to_m05_couplers_ARVALID(5),
m_axi_arvalid(4) => xbar_to_m04_couplers_ARVALID(4),
m_axi_arvalid(3) => xbar_to_m03_couplers_ARVALID(3),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(191 downto 160) => xbar_to_m05_couplers_AWADDR(191 downto 160),
m_axi_awaddr(159 downto 128) => xbar_to_m04_couplers_AWADDR(159 downto 128),
m_axi_awaddr(127 downto 96) => xbar_to_m03_couplers_AWADDR(127 downto 96),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(17 downto 3) => NLW_xbar_m_axi_awprot_UNCONNECTED(17 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready(5) => xbar_to_m05_couplers_AWREADY,
m_axi_awready(4) => xbar_to_m04_couplers_AWREADY,
m_axi_awready(3) => xbar_to_m03_couplers_AWREADY,
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY(0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY(0),
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(5) => xbar_to_m05_couplers_AWVALID(5),
m_axi_awvalid(4) => xbar_to_m04_couplers_AWVALID(4),
m_axi_awvalid(3) => xbar_to_m03_couplers_AWVALID(3),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(5) => xbar_to_m05_couplers_BREADY(5),
m_axi_bready(4) => xbar_to_m04_couplers_BREADY(4),
m_axi_bready(3) => xbar_to_m03_couplers_BREADY(3),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(11 downto 10) => xbar_to_m05_couplers_BRESP(1 downto 0),
m_axi_bresp(9 downto 8) => xbar_to_m04_couplers_BRESP(1 downto 0),
m_axi_bresp(7 downto 6) => xbar_to_m03_couplers_BRESP(1 downto 0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(5) => xbar_to_m05_couplers_BVALID,
m_axi_bvalid(4) => xbar_to_m04_couplers_BVALID,
m_axi_bvalid(3) => xbar_to_m03_couplers_BVALID,
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID(0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID(0),
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(191 downto 160) => xbar_to_m05_couplers_RDATA(31 downto 0),
m_axi_rdata(159 downto 128) => xbar_to_m04_couplers_RDATA(31 downto 0),
m_axi_rdata(127 downto 96) => xbar_to_m03_couplers_RDATA(31 downto 0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(5) => xbar_to_m05_couplers_RREADY(5),
m_axi_rready(4) => xbar_to_m04_couplers_RREADY(4),
m_axi_rready(3) => xbar_to_m03_couplers_RREADY(3),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(11 downto 10) => xbar_to_m05_couplers_RRESP(1 downto 0),
m_axi_rresp(9 downto 8) => xbar_to_m04_couplers_RRESP(1 downto 0),
m_axi_rresp(7 downto 6) => xbar_to_m03_couplers_RRESP(1 downto 0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(5) => xbar_to_m05_couplers_RVALID,
m_axi_rvalid(4) => xbar_to_m04_couplers_RVALID,
m_axi_rvalid(3) => xbar_to_m03_couplers_RVALID,
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID(0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID(0),
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(191 downto 160) => xbar_to_m05_couplers_WDATA(191 downto 160),
m_axi_wdata(159 downto 128) => xbar_to_m04_couplers_WDATA(159 downto 128),
m_axi_wdata(127 downto 96) => xbar_to_m03_couplers_WDATA(127 downto 96),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(5) => xbar_to_m05_couplers_WREADY,
m_axi_wready(4) => xbar_to_m04_couplers_WREADY,
m_axi_wready(3) => xbar_to_m03_couplers_WREADY,
m_axi_wready(2) => xbar_to_m02_couplers_WREADY(0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY(0),
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(23 downto 20) => xbar_to_m05_couplers_WSTRB(23 downto 20),
m_axi_wstrb(19 downto 16) => xbar_to_m04_couplers_WSTRB(19 downto 16),
m_axi_wstrb(15 downto 12) => xbar_to_m03_couplers_WSTRB(15 downto 12),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(5) => xbar_to_m05_couplers_WVALID(5),
m_axi_wvalid(4) => xbar_to_m04_couplers_WVALID(4),
m_axi_wvalid(3) => xbar_to_m03_couplers_WVALID(3),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design is
port (
BCLK : out STD_LOGIC;
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
GPIO_tri_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_tri_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_tri_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
IIC_0_scl_i : in STD_LOGIC;
IIC_0_scl_o : out STD_LOGIC;
IIC_0_scl_t : out STD_LOGIC;
IIC_0_sda_i : in STD_LOGIC;
IIC_0_sda_o : out STD_LOGIC;
IIC_0_sda_t : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
btns_5bits_tri_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
sws_8bits_tri_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of ip_design : entity is "ip_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=ip_design,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=18,numReposBlks=10,numNonXlnxBlks=2,numHierBlks=8,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_axi4_cnt=6,da_board_cnt=2,da_clkrst_cnt=1,da_ps7_cnt=1,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of ip_design : entity is "ip_design.hwdef";
end ip_design;
architecture STRUCTURE of ip_design is
component ip_design_led_controller_0_0 is
port (
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
end component ip_design_led_controller_0_0;
component ip_design_nco_0_0 is
port (
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC
);
end component ip_design_nco_0_0;
component ip_design_lms_pcore_0_0 is
port (
IPCORE_CLK : in STD_LOGIC;
IPCORE_RESETN : in STD_LOGIC;
AXI4_Lite_ACLK : in STD_LOGIC;
AXI4_Lite_ARESETN : in STD_LOGIC;
AXI4_Lite_AWADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_AWVALID : in STD_LOGIC;
AXI4_Lite_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
AXI4_Lite_WVALID : in STD_LOGIC;
AXI4_Lite_BREADY : in STD_LOGIC;
AXI4_Lite_ARADDR : in STD_LOGIC_VECTOR ( 15 downto 0 );
AXI4_Lite_ARVALID : in STD_LOGIC;
AXI4_Lite_RREADY : in STD_LOGIC;
AXI4_Lite_AWREADY : out STD_LOGIC;
AXI4_Lite_WREADY : out STD_LOGIC;
AXI4_Lite_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_BVALID : out STD_LOGIC;
AXI4_Lite_ARREADY : out STD_LOGIC;
AXI4_Lite_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
AXI4_Lite_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
AXI4_Lite_RVALID : out STD_LOGIC
);
end component ip_design_lms_pcore_0_0;
component ip_design_processing_system7_0_0 is
port (
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component ip_design_processing_system7_0_0;
component ip_design_rst_ps7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component ip_design_rst_ps7_0_100M_0;
component ip_design_zed_audio_ctrl_0_0 is
port (
BCLK : out STD_LOGIC;
LRCLK : out STD_LOGIC;
SDATA_I : in STD_LOGIC;
SDATA_O : out STD_LOGIC;
S_AXI_ACLK : in STD_LOGIC;
S_AXI_ARESETN : in STD_LOGIC;
S_AXI_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_AWVALID : in STD_LOGIC;
S_AXI_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_WVALID : in STD_LOGIC;
S_AXI_BREADY : in STD_LOGIC;
S_AXI_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_ARVALID : in STD_LOGIC;
S_AXI_RREADY : in STD_LOGIC;
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_RVALID : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
S_AXI_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_BVALID : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC
);
end component ip_design_zed_audio_ctrl_0_0;
component ip_design_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component ip_design_axi_gpio_0_0;
component ip_design_axi_gpio_1_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 4 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component ip_design_axi_gpio_1_0;
signal SDATA_I_0_1 : STD_LOGIC;
signal axi_gpio_0_GPIO_TRI_I : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_gpio_0_GPIO_TRI_T : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_gpio_1_GPIO2_TRI_I : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_gpio_1_GPIO_TRI_I : STD_LOGIC_VECTOR ( 4 downto 0 );
signal led_controller_0_LEDs_out : STD_LOGIC_VECTOR ( 7 downto 0 );
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_CLK1 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_I : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_O : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_T : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_I : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_O : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_T : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal ps7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal ps7_0_axi_periph_M03_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M03_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M03_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M03_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M03_AXI_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M03_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M03_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M03_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M03_AXI_WVALID : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M04_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M04_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M04_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M04_AXI_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M04_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M04_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M04_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M04_AXI_WVALID : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M05_AXI_ARREADY : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_ARVALID : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M05_AXI_AWREADY : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_AWVALID : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_BREADY : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M05_AXI_BVALID : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M05_AXI_RREADY : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ps7_0_axi_periph_M05_AXI_RVALID : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal ps7_0_axi_periph_M05_AXI_WREADY : STD_LOGIC;
signal ps7_0_axi_periph_M05_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ps7_0_axi_periph_M05_AXI_WVALID : STD_LOGIC;
signal rst_ps7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_ps7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal zed_audio_ctrl_0_BCLK : STD_LOGIC;
signal zed_audio_ctrl_0_LRCLK : STD_LOGIC;
signal zed_audio_ctrl_0_SDATA_O : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of DDR_cas_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N";
attribute X_INTERFACE_INFO of DDR_ck_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N";
attribute X_INTERFACE_INFO of DDR_ck_p : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P";
attribute X_INTERFACE_INFO of DDR_cke : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE";
attribute X_INTERFACE_INFO of DDR_cs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N";
attribute X_INTERFACE_INFO of DDR_odt : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT";
attribute X_INTERFACE_INFO of DDR_ras_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N";
attribute X_INTERFACE_INFO of DDR_reset_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N";
attribute X_INTERFACE_INFO of DDR_we_n : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N";
attribute X_INTERFACE_INFO of FCLK_CLK1 : signal is "xilinx.com:signal:clock:1.0 CLK.FCLK_CLK1 CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of FCLK_CLK1 : signal is "XIL_INTERFACENAME CLK.FCLK_CLK1, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK1, FREQ_HZ 10000000, PHASE 0.000";
attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrn : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN";
attribute X_INTERFACE_PARAMETER of FIXED_IO_ddr_vrn : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false";
attribute X_INTERFACE_INFO of FIXED_IO_ddr_vrp : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP";
attribute X_INTERFACE_INFO of FIXED_IO_ps_clk : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK";
attribute X_INTERFACE_INFO of FIXED_IO_ps_porb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB";
attribute X_INTERFACE_INFO of FIXED_IO_ps_srstb : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB";
attribute X_INTERFACE_INFO of IIC_0_scl_i : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_I";
attribute X_INTERFACE_INFO of IIC_0_scl_o : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_O";
attribute X_INTERFACE_INFO of IIC_0_scl_t : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_T";
attribute X_INTERFACE_INFO of IIC_0_sda_i : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_I";
attribute X_INTERFACE_INFO of IIC_0_sda_o : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_O";
attribute X_INTERFACE_INFO of IIC_0_sda_t : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_T";
attribute X_INTERFACE_INFO of DDR_addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR";
attribute X_INTERFACE_PARAMETER of DDR_addr : signal is "XIL_INTERFACENAME DDR, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250";
attribute X_INTERFACE_INFO of DDR_ba : signal is "xilinx.com:interface:ddrx:1.0 DDR BA";
attribute X_INTERFACE_INFO of DDR_dm : signal is "xilinx.com:interface:ddrx:1.0 DDR DM";
attribute X_INTERFACE_INFO of DDR_dq : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ";
attribute X_INTERFACE_INFO of DDR_dqs_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N";
attribute X_INTERFACE_INFO of DDR_dqs_p : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P";
attribute X_INTERFACE_INFO of FIXED_IO_mio : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO";
attribute X_INTERFACE_INFO of GPIO_tri_i : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
attribute X_INTERFACE_INFO of GPIO_tri_o : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
attribute X_INTERFACE_INFO of GPIO_tri_t : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
attribute X_INTERFACE_INFO of btns_5bits_tri_i : signal is "xilinx.com:interface:gpio:1.0 btns_5bits TRI_I";
attribute X_INTERFACE_INFO of sws_8bits_tri_i : signal is "xilinx.com:interface:gpio:1.0 sws_8bits TRI_I";
begin
BCLK <= zed_audio_ctrl_0_BCLK;
FCLK_CLK1 <= processing_system7_0_FCLK_CLK1;
GPIO_tri_o(1 downto 0) <= axi_gpio_0_GPIO_TRI_O(1 downto 0);
GPIO_tri_t(1 downto 0) <= axi_gpio_0_GPIO_TRI_T(1 downto 0);
IIC_0_scl_o <= processing_system7_0_IIC_0_SCL_O;
IIC_0_scl_t <= processing_system7_0_IIC_0_SCL_T;
IIC_0_sda_o <= processing_system7_0_IIC_0_SDA_O;
IIC_0_sda_t <= processing_system7_0_IIC_0_SDA_T;
LEDs_out(7 downto 0) <= led_controller_0_LEDs_out(7 downto 0);
LRCLK <= zed_audio_ctrl_0_LRCLK;
SDATA_I_0_1 <= SDATA_I;
SDATA_O <= zed_audio_ctrl_0_SDATA_O;
axi_gpio_0_GPIO_TRI_I(1 downto 0) <= GPIO_tri_i(1 downto 0);
axi_gpio_1_GPIO2_TRI_I(7 downto 0) <= sws_8bits_tri_i(7 downto 0);
axi_gpio_1_GPIO_TRI_I(4 downto 0) <= btns_5bits_tri_i(4 downto 0);
processing_system7_0_IIC_0_SCL_I <= IIC_0_scl_i;
processing_system7_0_IIC_0_SDA_I <= IIC_0_sda_i;
axi_gpio_0: component ip_design_axi_gpio_0_0
port map (
gpio_io_i(1 downto 0) => axi_gpio_0_GPIO_TRI_I(1 downto 0),
gpio_io_o(1 downto 0) => axi_gpio_0_GPIO_TRI_O(1 downto 0),
gpio_io_t(1 downto 0) => axi_gpio_0_GPIO_TRI_T(1 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => ps7_0_axi_periph_M04_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_ps7_0_100M_peripheral_aresetn(0),
s_axi_arready => ps7_0_axi_periph_M04_AXI_ARREADY,
s_axi_arvalid => ps7_0_axi_periph_M04_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => ps7_0_axi_periph_M04_AXI_AWADDR(8 downto 0),
s_axi_awready => ps7_0_axi_periph_M04_AXI_AWREADY,
s_axi_awvalid => ps7_0_axi_periph_M04_AXI_AWVALID,
s_axi_bready => ps7_0_axi_periph_M04_AXI_BREADY,
s_axi_bresp(1 downto 0) => ps7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
s_axi_bvalid => ps7_0_axi_periph_M04_AXI_BVALID,
s_axi_rdata(31 downto 0) => ps7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
s_axi_rready => ps7_0_axi_periph_M04_AXI_RREADY,
s_axi_rresp(1 downto 0) => ps7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
s_axi_rvalid => ps7_0_axi_periph_M04_AXI_RVALID,
s_axi_wdata(31 downto 0) => ps7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
s_axi_wready => ps7_0_axi_periph_M04_AXI_WREADY,
s_axi_wstrb(3 downto 0) => ps7_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
s_axi_wvalid => ps7_0_axi_periph_M04_AXI_WVALID
);
axi_gpio_1: component ip_design_axi_gpio_1_0
port map (
gpio2_io_i(7 downto 0) => axi_gpio_1_GPIO2_TRI_I(7 downto 0),
gpio_io_i(4 downto 0) => axi_gpio_1_GPIO_TRI_I(4 downto 0),
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(8 downto 0) => ps7_0_axi_periph_M05_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_ps7_0_100M_peripheral_aresetn(0),
s_axi_arready => ps7_0_axi_periph_M05_AXI_ARREADY,
s_axi_arvalid => ps7_0_axi_periph_M05_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => ps7_0_axi_periph_M05_AXI_AWADDR(8 downto 0),
s_axi_awready => ps7_0_axi_periph_M05_AXI_AWREADY,
s_axi_awvalid => ps7_0_axi_periph_M05_AXI_AWVALID,
s_axi_bready => ps7_0_axi_periph_M05_AXI_BREADY,
s_axi_bresp(1 downto 0) => ps7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
s_axi_bvalid => ps7_0_axi_periph_M05_AXI_BVALID,
s_axi_rdata(31 downto 0) => ps7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
s_axi_rready => ps7_0_axi_periph_M05_AXI_RREADY,
s_axi_rresp(1 downto 0) => ps7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
s_axi_rvalid => ps7_0_axi_periph_M05_AXI_RVALID,
s_axi_wdata(31 downto 0) => ps7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
s_axi_wready => ps7_0_axi_periph_M05_AXI_WREADY,
s_axi_wstrb(3 downto 0) => ps7_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
s_axi_wvalid => ps7_0_axi_periph_M05_AXI_WVALID
);
led_controller_0: component ip_design_led_controller_0_0
port map (
LEDs_out(7 downto 0) => led_controller_0_LEDs_out(7 downto 0),
s00_axi_aclk => processing_system7_0_FCLK_CLK0,
s00_axi_araddr(3 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(3 downto 0),
s00_axi_aresetn => rst_ps7_0_100M_peripheral_aresetn(0),
s00_axi_arprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_ARPROT(2 downto 0),
s00_axi_arready => ps7_0_axi_periph_M00_AXI_ARREADY,
s00_axi_arvalid => ps7_0_axi_periph_M00_AXI_ARVALID(0),
s00_axi_awaddr(3 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(3 downto 0),
s00_axi_awprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_AWPROT(2 downto 0),
s00_axi_awready => ps7_0_axi_periph_M00_AXI_AWREADY,
s00_axi_awvalid => ps7_0_axi_periph_M00_AXI_AWVALID(0),
s00_axi_bready => ps7_0_axi_periph_M00_AXI_BREADY(0),
s00_axi_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s00_axi_bvalid => ps7_0_axi_periph_M00_AXI_BVALID,
s00_axi_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s00_axi_rready => ps7_0_axi_periph_M00_AXI_RREADY(0),
s00_axi_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s00_axi_rvalid => ps7_0_axi_periph_M00_AXI_RVALID,
s00_axi_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s00_axi_wready => ps7_0_axi_periph_M00_AXI_WREADY,
s00_axi_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s00_axi_wvalid => ps7_0_axi_periph_M00_AXI_WVALID(0)
);
lms_pcore_0: component ip_design_lms_pcore_0_0
port map (
AXI4_Lite_ACLK => processing_system7_0_FCLK_CLK0,
AXI4_Lite_ARADDR(15 downto 0) => ps7_0_axi_periph_M02_AXI_ARADDR(15 downto 0),
AXI4_Lite_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
AXI4_Lite_ARREADY => ps7_0_axi_periph_M02_AXI_ARREADY,
AXI4_Lite_ARVALID => ps7_0_axi_periph_M02_AXI_ARVALID(0),
AXI4_Lite_AWADDR(15 downto 0) => ps7_0_axi_periph_M02_AXI_AWADDR(15 downto 0),
AXI4_Lite_AWREADY => ps7_0_axi_periph_M02_AXI_AWREADY,
AXI4_Lite_AWVALID => ps7_0_axi_periph_M02_AXI_AWVALID(0),
AXI4_Lite_BREADY => ps7_0_axi_periph_M02_AXI_BREADY(0),
AXI4_Lite_BRESP(1 downto 0) => ps7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
AXI4_Lite_BVALID => ps7_0_axi_periph_M02_AXI_BVALID,
AXI4_Lite_RDATA(31 downto 0) => ps7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
AXI4_Lite_RREADY => ps7_0_axi_periph_M02_AXI_RREADY(0),
AXI4_Lite_RRESP(1 downto 0) => ps7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
AXI4_Lite_RVALID => ps7_0_axi_periph_M02_AXI_RVALID,
AXI4_Lite_WDATA(31 downto 0) => ps7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
AXI4_Lite_WREADY => ps7_0_axi_periph_M02_AXI_WREADY,
AXI4_Lite_WSTRB(3 downto 0) => ps7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
AXI4_Lite_WVALID => ps7_0_axi_periph_M02_AXI_WVALID(0),
IPCORE_CLK => processing_system7_0_FCLK_CLK0,
IPCORE_RESETN => rst_ps7_0_100M_peripheral_aresetn(0)
);
nco_0: component ip_design_nco_0_0
port map (
ap_clk => processing_system7_0_FCLK_CLK0,
ap_rst_n => rst_ps7_0_100M_peripheral_aresetn(0),
s_axi_AXILiteS_ARADDR(5 downto 0) => ps7_0_axi_periph_M01_AXI_ARADDR(5 downto 0),
s_axi_AXILiteS_ARREADY => ps7_0_axi_periph_M01_AXI_ARREADY,
s_axi_AXILiteS_ARVALID => ps7_0_axi_periph_M01_AXI_ARVALID(0),
s_axi_AXILiteS_AWADDR(5 downto 0) => ps7_0_axi_periph_M01_AXI_AWADDR(5 downto 0),
s_axi_AXILiteS_AWREADY => ps7_0_axi_periph_M01_AXI_AWREADY,
s_axi_AXILiteS_AWVALID => ps7_0_axi_periph_M01_AXI_AWVALID(0),
s_axi_AXILiteS_BREADY => ps7_0_axi_periph_M01_AXI_BREADY(0),
s_axi_AXILiteS_BRESP(1 downto 0) => ps7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_AXILiteS_BVALID => ps7_0_axi_periph_M01_AXI_BVALID,
s_axi_AXILiteS_RDATA(31 downto 0) => ps7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_AXILiteS_RREADY => ps7_0_axi_periph_M01_AXI_RREADY(0),
s_axi_AXILiteS_RRESP(1 downto 0) => ps7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_AXILiteS_RVALID => ps7_0_axi_periph_M01_AXI_RVALID,
s_axi_AXILiteS_WDATA(31 downto 0) => ps7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_AXILiteS_WREADY => ps7_0_axi_periph_M01_AXI_WREADY,
s_axi_AXILiteS_WSTRB(3 downto 0) => ps7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_AXILiteS_WVALID => ps7_0_axi_periph_M01_AXI_WVALID(0)
);
processing_system7_0: component ip_design_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_CLK1 => processing_system7_0_FCLK_CLK1,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
I2C0_SCL_I => processing_system7_0_IIC_0_SCL_I,
I2C0_SCL_O => processing_system7_0_IIC_0_SCL_O,
I2C0_SCL_T => processing_system7_0_IIC_0_SCL_T,
I2C0_SDA_I => processing_system7_0_IIC_0_SDA_I,
I2C0_SDA_O => processing_system7_0_IIC_0_SDA_O,
I2C0_SDA_T => processing_system7_0_IIC_0_SDA_T,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
ps7_0_axi_periph: entity work.ip_design_ps7_0_axi_periph_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN => rst_ps7_0_100M_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready(0) => ps7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => ps7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awprot(2 downto 0) => ps7_0_axi_periph_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready(0) => ps7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => ps7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => ps7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => ps7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => ps7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => ps7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => ps7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => ps7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M01_AXI_ARADDR(31 downto 0),
M01_AXI_arready(0) => ps7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid(0) => ps7_0_axi_periph_M01_AXI_ARVALID(0),
M01_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M01_AXI_AWADDR(31 downto 0),
M01_AXI_awready(0) => ps7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid(0) => ps7_0_axi_periph_M01_AXI_AWVALID(0),
M01_AXI_bready(0) => ps7_0_axi_periph_M01_AXI_BREADY(0),
M01_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid(0) => ps7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready(0) => ps7_0_axi_periph_M01_AXI_RREADY(0),
M01_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid(0) => ps7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready(0) => ps7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid(0) => ps7_0_axi_periph_M01_AXI_WVALID(0),
M02_ACLK => processing_system7_0_FCLK_CLK0,
M02_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M02_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M02_AXI_ARADDR(31 downto 0),
M02_AXI_arready(0) => ps7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid(0) => ps7_0_axi_periph_M02_AXI_ARVALID(0),
M02_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M02_AXI_AWADDR(31 downto 0),
M02_AXI_awready(0) => ps7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid(0) => ps7_0_axi_periph_M02_AXI_AWVALID(0),
M02_AXI_bready(0) => ps7_0_axi_periph_M02_AXI_BREADY(0),
M02_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid(0) => ps7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready(0) => ps7_0_axi_periph_M02_AXI_RREADY(0),
M02_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid(0) => ps7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready(0) => ps7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid(0) => ps7_0_axi_periph_M02_AXI_WVALID(0),
M03_ACLK => processing_system7_0_FCLK_CLK0,
M03_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M03_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M03_AXI_ARADDR(31 downto 0),
M03_AXI_arready => ps7_0_axi_periph_M03_AXI_ARREADY,
M03_AXI_arvalid => ps7_0_axi_periph_M03_AXI_ARVALID,
M03_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M03_AXI_AWADDR(31 downto 0),
M03_AXI_awready => ps7_0_axi_periph_M03_AXI_AWREADY,
M03_AXI_awvalid => ps7_0_axi_periph_M03_AXI_AWVALID,
M03_AXI_bready => ps7_0_axi_periph_M03_AXI_BREADY,
M03_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
M03_AXI_bvalid => ps7_0_axi_periph_M03_AXI_BVALID,
M03_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
M03_AXI_rready => ps7_0_axi_periph_M03_AXI_RREADY,
M03_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
M03_AXI_rvalid => ps7_0_axi_periph_M03_AXI_RVALID,
M03_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
M03_AXI_wready => ps7_0_axi_periph_M03_AXI_WREADY,
M03_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
M03_AXI_wvalid => ps7_0_axi_periph_M03_AXI_WVALID,
M04_ACLK => processing_system7_0_FCLK_CLK0,
M04_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M04_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M04_AXI_ARADDR(31 downto 0),
M04_AXI_arready => ps7_0_axi_periph_M04_AXI_ARREADY,
M04_AXI_arvalid => ps7_0_axi_periph_M04_AXI_ARVALID,
M04_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M04_AXI_AWADDR(31 downto 0),
M04_AXI_awready => ps7_0_axi_periph_M04_AXI_AWREADY,
M04_AXI_awvalid => ps7_0_axi_periph_M04_AXI_AWVALID,
M04_AXI_bready => ps7_0_axi_periph_M04_AXI_BREADY,
M04_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M04_AXI_BRESP(1 downto 0),
M04_AXI_bvalid => ps7_0_axi_periph_M04_AXI_BVALID,
M04_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M04_AXI_RDATA(31 downto 0),
M04_AXI_rready => ps7_0_axi_periph_M04_AXI_RREADY,
M04_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M04_AXI_RRESP(1 downto 0),
M04_AXI_rvalid => ps7_0_axi_periph_M04_AXI_RVALID,
M04_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M04_AXI_WDATA(31 downto 0),
M04_AXI_wready => ps7_0_axi_periph_M04_AXI_WREADY,
M04_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M04_AXI_WSTRB(3 downto 0),
M04_AXI_wvalid => ps7_0_axi_periph_M04_AXI_WVALID,
M05_ACLK => processing_system7_0_FCLK_CLK0,
M05_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
M05_AXI_araddr(31 downto 0) => ps7_0_axi_periph_M05_AXI_ARADDR(31 downto 0),
M05_AXI_arready => ps7_0_axi_periph_M05_AXI_ARREADY,
M05_AXI_arvalid => ps7_0_axi_periph_M05_AXI_ARVALID,
M05_AXI_awaddr(31 downto 0) => ps7_0_axi_periph_M05_AXI_AWADDR(31 downto 0),
M05_AXI_awready => ps7_0_axi_periph_M05_AXI_AWREADY,
M05_AXI_awvalid => ps7_0_axi_periph_M05_AXI_AWVALID,
M05_AXI_bready => ps7_0_axi_periph_M05_AXI_BREADY,
M05_AXI_bresp(1 downto 0) => ps7_0_axi_periph_M05_AXI_BRESP(1 downto 0),
M05_AXI_bvalid => ps7_0_axi_periph_M05_AXI_BVALID,
M05_AXI_rdata(31 downto 0) => ps7_0_axi_periph_M05_AXI_RDATA(31 downto 0),
M05_AXI_rready => ps7_0_axi_periph_M05_AXI_RREADY,
M05_AXI_rresp(1 downto 0) => ps7_0_axi_periph_M05_AXI_RRESP(1 downto 0),
M05_AXI_rvalid => ps7_0_axi_periph_M05_AXI_RVALID,
M05_AXI_wdata(31 downto 0) => ps7_0_axi_periph_M05_AXI_WDATA(31 downto 0),
M05_AXI_wready => ps7_0_axi_periph_M05_AXI_WREADY,
M05_AXI_wstrb(3 downto 0) => ps7_0_axi_periph_M05_AXI_WSTRB(3 downto 0),
M05_AXI_wvalid => ps7_0_axi_periph_M05_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
rst_ps7_0_100M: component ip_design_rst_ps7_0_100M_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_rst_ps7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_ps7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_rst_ps7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_ps7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_ps7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
zed_audio_ctrl_0: component ip_design_zed_audio_ctrl_0_0
port map (
BCLK => zed_audio_ctrl_0_BCLK,
LRCLK => zed_audio_ctrl_0_LRCLK,
SDATA_I => SDATA_I_0_1,
SDATA_O => zed_audio_ctrl_0_SDATA_O,
S_AXI_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_ARADDR(31 downto 0) => ps7_0_axi_periph_M03_AXI_ARADDR(31 downto 0),
S_AXI_ARESETN => rst_ps7_0_100M_peripheral_aresetn(0),
S_AXI_ARREADY => ps7_0_axi_periph_M03_AXI_ARREADY,
S_AXI_ARVALID => ps7_0_axi_periph_M03_AXI_ARVALID,
S_AXI_AWADDR(31 downto 0) => ps7_0_axi_periph_M03_AXI_AWADDR(31 downto 0),
S_AXI_AWREADY => ps7_0_axi_periph_M03_AXI_AWREADY,
S_AXI_AWVALID => ps7_0_axi_periph_M03_AXI_AWVALID,
S_AXI_BREADY => ps7_0_axi_periph_M03_AXI_BREADY,
S_AXI_BRESP(1 downto 0) => ps7_0_axi_periph_M03_AXI_BRESP(1 downto 0),
S_AXI_BVALID => ps7_0_axi_periph_M03_AXI_BVALID,
S_AXI_RDATA(31 downto 0) => ps7_0_axi_periph_M03_AXI_RDATA(31 downto 0),
S_AXI_RREADY => ps7_0_axi_periph_M03_AXI_RREADY,
S_AXI_RRESP(1 downto 0) => ps7_0_axi_periph_M03_AXI_RRESP(1 downto 0),
S_AXI_RVALID => ps7_0_axi_periph_M03_AXI_RVALID,
S_AXI_WDATA(31 downto 0) => ps7_0_axi_periph_M03_AXI_WDATA(31 downto 0),
S_AXI_WREADY => ps7_0_axi_periph_M03_AXI_WREADY,
S_AXI_WSTRB(3 downto 0) => ps7_0_axi_periph_M03_AXI_WSTRB(3 downto 0),
S_AXI_WVALID => ps7_0_axi_periph_M03_AXI_WVALID
);
end STRUCTURE;
| mit | d9b383e27624ee44b1470ae351ab4abb | 0.672813 | 2.705456 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/mul_61x61.vhd | 1 | 4,181 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mul_61x61
-- File: mul_61x61.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: 61x61 multiplier
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity mul_61x61 is
generic (multech : integer := 0;
fabtech : integer := 0);
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of mul_61x61 is
component dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component gen_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component axcel_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex4_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex6_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component virtex7_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
component kintex7_mul_61x61
port(
A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
begin
gen0 : if multech = 0 generate
mul0 : gen_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
dw0 : if multech = 1 generate
mul0 : dw_mul_61x61 port map (A, B, CLK, PRODUCT);
end generate;
tech0 : if multech = 3 generate
axd0 : if fabtech = axdsp generate
mul0 : axcel_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
xc5v : if fabtech = virtex5 generate
mul0 : virtex4_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
xc6v : if fabtech = virtex6 generate
mul0 : virtex6_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
gen0 : if not ((fabtech = axdsp) or (fabtech = virtex5) or (fabtech = virtex6)) generate
mul0 : gen_mul_61x61 port map (A, B, EN, CLK, PRODUCT);
end generate;
end generate;
end;
| gpl-2.0 | 9957472e48b37ee328ad84c5db941abf | 0.61038 | 3.466833 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0/zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl | 1 | 374,898 | -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:11:18 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 -prefix
-- zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_ zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_axi_bram_ctrl_0_bram_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[1:0][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[3:2][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
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DOB_REG => 0,
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EN_ECC_WRITE => false,
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[5:4][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[23:22][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[25:24][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[27:26][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[29:28][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[31:30][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[7:6][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[9:8][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[11:10][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[13:12][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[15:14][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[17:16][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[19:18][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\ : entity is "blk_mem_gen_prim_wrapper";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[21:20][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_noinit.ram\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[10].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(21 downto 20),
dinb(1 downto 0) => dinb(21 downto 20),
douta(1 downto 0) => douta(21 downto 20),
doutb(1 downto 0) => doutb(21 downto 20),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[11].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(23 downto 22),
dinb(1 downto 0) => dinb(23 downto 22),
douta(1 downto 0) => douta(23 downto 22),
doutb(1 downto 0) => doutb(23 downto 22),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[12].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(25 downto 24),
dinb(1 downto 0) => dinb(25 downto 24),
douta(1 downto 0) => douta(25 downto 24),
doutb(1 downto 0) => doutb(25 downto 24),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[13].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(27 downto 26),
dinb(1 downto 0) => dinb(27 downto 26),
douta(1 downto 0) => douta(27 downto 26),
doutb(1 downto 0) => doutb(27 downto 26),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[14].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(29 downto 28),
dinb(1 downto 0) => dinb(29 downto 28),
douta(1 downto 0) => douta(29 downto 28),
doutb(1 downto 0) => doutb(29 downto 28),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[15].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(31 downto 30),
dinb(1 downto 0) => dinb(31 downto 30),
douta(1 downto 0) => douta(31 downto 30),
doutb(1 downto 0) => doutb(31 downto 30),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[1].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(3 downto 2),
dinb(1 downto 0) => dinb(3 downto 2),
douta(1 downto 0) => douta(3 downto 2),
doutb(1 downto 0) => doutb(3 downto 2),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[2].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(5 downto 4),
dinb(1 downto 0) => dinb(5 downto 4),
douta(1 downto 0) => douta(5 downto 4),
doutb(1 downto 0) => doutb(5 downto 4),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[3].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(7 downto 6),
dinb(1 downto 0) => dinb(7 downto 6),
douta(1 downto 0) => douta(7 downto 6),
doutb(1 downto 0) => doutb(7 downto 6),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[4].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(9 downto 8),
dinb(1 downto 0) => dinb(9 downto 8),
douta(1 downto 0) => douta(9 downto 8),
doutb(1 downto 0) => doutb(9 downto 8),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[5].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(11 downto 10),
dinb(1 downto 0) => dinb(11 downto 10),
douta(1 downto 0) => douta(11 downto 10),
doutb(1 downto 0) => doutb(11 downto 10),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[6].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(13 downto 12),
dinb(1 downto 0) => dinb(13 downto 12),
douta(1 downto 0) => douta(13 downto 12),
doutb(1 downto 0) => doutb(13 downto 12),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[7].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(15 downto 14),
dinb(1 downto 0) => dinb(15 downto 14),
douta(1 downto 0) => douta(15 downto 14),
doutb(1 downto 0) => doutb(15 downto 14),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[8].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(17 downto 16),
dinb(1 downto 0) => dinb(17 downto 16),
douta(1 downto 0) => douta(17 downto 16),
doutb(1 downto 0) => doutb(17 downto 16),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[9].ram.r\: entity work.\zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(19 downto 18),
dinb(1 downto 0) => dinb(19 downto 18),
douta(1 downto 0) => douta(19 downto 18),
doutb(1 downto 0) => doutb(19 downto 18),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_top;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth is
begin
\gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen\: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "16";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "Estimated Power for IP : 20.388 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "yes";
end zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(31) <= \<const0>\;
rdaddrecc(30) <= \<const0>\;
rdaddrecc(29) <= \<const0>\;
rdaddrecc(28) <= \<const0>\;
rdaddrecc(27) <= \<const0>\;
rdaddrecc(26) <= \<const0>\;
rdaddrecc(25) <= \<const0>\;
rdaddrecc(24) <= \<const0>\;
rdaddrecc(23) <= \<const0>\;
rdaddrecc(22) <= \<const0>\;
rdaddrecc(21) <= \<const0>\;
rdaddrecc(20) <= \<const0>\;
rdaddrecc(19) <= \<const0>\;
rdaddrecc(18) <= \<const0>\;
rdaddrecc(17) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(31) <= \<const0>\;
s_axi_rdaddrecc(30) <= \<const0>\;
s_axi_rdaddrecc(29) <= \<const0>\;
s_axi_rdaddrecc(28) <= \<const0>\;
s_axi_rdaddrecc(27) <= \<const0>\;
s_axi_rdaddrecc(26) <= \<const0>\;
s_axi_rdaddrecc(25) <= \<const0>\;
s_axi_rdaddrecc(24) <= \<const0>\;
s_axi_rdaddrecc(23) <= \<const0>\;
s_axi_rdaddrecc(22) <= \<const0>\;
s_axi_rdaddrecc(21) <= \<const0>\;
s_axi_rdaddrecc(20) <= \<const0>\;
s_axi_rdaddrecc(19) <= \<const0>\;
s_axi_rdaddrecc(18) <= \<const0>\;
s_axi_rdaddrecc(17) <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth
port map (
addra(13 downto 0) => addra(15 downto 2),
addrb(13 downto 0) => addrb(15 downto 2),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 : entity is "zqynq_lab_1_design_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 : entity is "blk_mem_gen_v8_3_6,Vivado 2017.2";
end zqynq_lab_1_design_axi_bram_ctrl_0_bram_0;
architecture STRUCTURE of zqynq_lab_1_design_axi_bram_ctrl_0_bram_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "16";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 20.388 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.zqynq_lab_1_design_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6
port map (
addra(31 downto 0) => addra(31 downto 0),
addrb(31 downto 0) => addrb(31 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(31 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(31 downto 0),
regcea => '0',
regceb => '0',
rsta => rsta,
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => rstb,
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(31 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(31 downto 0),
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
| mit | 75002d524d655101135312c401588a49 | 0.741836 | 4.633003 | false | false | false | false |
VerkhovtsovPavel/BSUIR_Labs | Master/POCP/My_Designs/Stack/src/CTRL1.vhd | 1 | 5,487 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library stack;
use stack.OneHotStack.all;
entity CTRL1 is
port(
CLK, RST, Start: in std_logic;
Stop: out std_logic;
-- ROM
ROM_re: out std_logic;
ROM_addr: out mem_addr;
ROM_dout: in command;
-- RAM
RAM_rw: out std_logic;
RAM_addr: out mem_addr;
RAM_din: out operand;
RAM_dout: in operand;
--datapath
DP_op: out operand;
DP_ot: out operation;
DP_en: out std_logic;
DP_res: in operand;
DP_zf: in std_logic;
DP_stop: in std_logic
);
end CTRL1;
architecture Beh_Stack of CTRL1 is
type states is (I, F, D, R, S, H, LIN, J, DP, DPW);
-- I - idle
-- F - fetch
-- D - decode
-- R - read
-- S - store
-- H - halt
-- LIN - load indirect
-- J - jump if zero bit not set
-- DP - data path operation trigger
-- DPW - data path wait
signal nxt_state, cur_state: states;
-- instruction register
signal RI: command;
-- instruction counter
signal IC: mem_addr;
-- operation type register
signal RO: operation;
-- memory address register
signal RA: mem_addr;
-- data register
signal RD: operand;
begin
-- synchronous memory
FSM: process(CLK, RST, nxt_state)
begin
if (RST = '1') then
cur_state <= I;
elsif rising_edge(CLK) then
cur_state <= nxt_state;
end if;
end process;
-- Next state
COMB: process(cur_state, start, RO, DP_stop)
begin
case cur_state is
when I =>
if (start = '1') then
nxt_state <= F;
else
nxt_state <= I;
end if;
when F => nxt_state <= D;
when D =>
case RO is
when ADD | SUBT | SHIFT | POP => nxt_state <= DP;
when HALT => nxt_state <= H;
when JNZ => nxt_state <= J;
when others => nxt_state <= R;
end case;
when R =>
if (RO = PUSH) then
nxt_state <= DP;
elsif (RO = POPIN) then
nxt_state <= LIN;
else
nxt_state <= I;
end if;
when LIN => nxt_state <= DP;
when DP => nxt_state <= DPW;
when DPW =>
if (DP_stop = '0') then
nxt_state <= DPW;
else
if (RO = POP or RO = POPIN) then
nxt_state <= S;
else
nxt_state <= F;
end if;
end if;
when S | J => nxt_state <= F;
when H => nxt_state <= H;
when others => nxt_state <= I;
end case;
end process;
-- stop signal
PSTOP: process (cur_state)
begin
if (cur_state = H) then
stop <= '1';
else
stop <= '0';
end if;
end process;
-- instruction counter
PMC: process (CLK, RST, cur_state)
begin
if (RST = '1') then
IC <= "00000";
elsif falling_edge(CLK) then
if (cur_state = D) then
IC <= IC + 1;
elsif (cur_state = J and DP_ZF = '0') then
IC <= RA;
end if;
end if;
end process;
ROM_addr <= IC;
-- ROM read signal
PROMREAD: process (nxt_state, cur_state)
begin
if (nxt_state = F or cur_state = F) then
ROM_re <= '1';
else
ROM_re <= '0';
end if;
end process;
-- read ROM value and put it into RI
PROMDAT: process (RST, cur_state, ROM_dout)
begin
if (RST = '1') then
RI <= (others => '0');
elsif (cur_state = F) then
RI <= ROM_dout;
end if;
end process;
-- RO and RA control
PRORA: process (RST, nxt_state, RI)
begin
if (RST = '1') then
RO <= (others => '0');
RA <= (others => '0');
elsif (nxt_state = D) then
RO <= RI (7 downto 5);
RA <= RI (4 downto 0);
elsif (nxt_state = LIN) then
RA <= RD (4 downto 0);
end if;
end process;
PRAMST: process (RA)
begin
if (cur_state /= J) then
RAM_addr <= RA;
end if;
end process;
-- RAM read/write control
PRAMREAD: process (cur_state)
begin
if (cur_state = S) then
RAM_rw <= '0';
else
RAM_rw <= '1';
end if;
end process;
-- read value from RAM and put it into RD
PRAMDAR: process (cur_state)
begin
if (cur_state = R) then
RD <= RAM_dout;
end if;
end process;
-- move the value from DPATH to RAM input bus
RAM_din <= DP_res;
-- move the value from RD to datapath
DP_op <= RD;
-- move RO value to DP operation bus
DP_ot <= RO;
pdpathen: process (cur_state)
begin
if (cur_state = DP) then
DP_en <= '1';
else
DP_en <= '0';
end if;
end process;
end Beh_Stack; | mit | 01e0672f886c803aa32b8c949a571b57 | 0.439767 | 3.958874 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/cachemem.vhd | 1 | 21,810 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cachemem
-- File: cachemem.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.mmuconfig.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
entity cachemem is
generic (
tech : integer range 0 to NTECH := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
mmuen : integer range 0 to 1 := 0;
testen : integer range 0 to 3 := 0
);
port (
clk : in std_ulogic;
crami : in cram_in_type;
cramo : out cram_out_type;
sclk : in std_ulogic
);
end;
architecture rtl of cachemem is
constant DSNOOPSEP : boolean := (dsnoop > 3);
constant DSNOOPFAST : boolean := (dsnoop = 2) or (dsnoop = 6);
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant DLINE_BITS : integer := log2(dlinesize);
constant DOFFSET_BITS : integer := 8 +log2(dsetsize) - DLINE_BITS;
constant ITAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + ilinesize + 1;
constant DTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + dlinesize + 1;
constant IPTAG_BITS : integer := TAG_HIGH - IOFFSET_BITS - ILINE_BITS - 2 + 1;
constant ILRR_BIT : integer := creplalg_tbl(irepl);
constant DLRR_BIT : integer := creplalg_tbl(drepl);
constant ITAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant DTAG_LOW : integer := DOFFSET_BITS + DLINE_BITS + 2;
constant ICLOCK_BIT : integer := isetlock;
constant DCLOCK_BIT : integer := dsetlock;
constant ILRAM_BITS : integer := log2(ilramsize) + 10;
constant DLRAM_BITS : integer := log2(dlramsize) + 10;
constant ITDEPTH : natural := 2**IOFFSET_BITS;
constant DTDEPTH : natural := 2**DOFFSET_BITS;
constant MMUCTX_BITS : natural := 8*mmuen;
-- i/d tag layout
-- +-----+----------+---+--------+-----+-------+
-- | LRR | LOCK_BIT |PAR| MMUCTX | TAG | VALID |
-- +-----+----------+---+--------+-----+-------+
-- [opt] [ opt ] [ ] [ opt ] [ ]
constant ITWIDTH : natural := ITAG_BITS + ILRR_BIT + ICLOCK_BIT + MMUCTX_BITS
;
constant DTWIDTH : natural := DTAG_BITS + DLRR_BIT + DCLOCK_BIT + MMUCTX_BITS
;
constant IDWIDTH : natural := 32
;
constant DDWIDTH : natural := 32
;
constant DPTAG_BITS : integer := TAG_HIGH - DOFFSET_BITS - DLINE_BITS - 2 + 1;
constant DTLRR_BIT_POS : natural := DTWIDTH-DLRR_BIT; -- if DTLRR_BIT=0 discard (pos DTWIDTH)
constant DTLOCK_BIT_POS : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT); -- if DTCLOCK_BIT=0 but DTLRR_BIT=1 lrr will overwrite
constant DTMMU_VEC_U : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT
)-1;
constant DTMMU_VEC_D : natural := DTWIDTH-(DLRR_BIT+DCLOCK_BIT+
MMUCTX_BITS);
constant ITLRR_BIT_POS : natural := ITWIDTH-ILRR_BIT; -- if DLRR_BIT=0 discard (pos DTWIDTH)
constant ITLOCK_BIT_POS : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT); -- if DCLOCK_BIT=0 but DLRR_BIT=1 lrr will overwrite
constant ITMMU_VEC_U : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT
)-1;
constant ITMMU_VEC_D : natural := ITWIDTH-(ILRR_BIT+ICLOCK_BIT+
MMUCTX_BITS);
constant DPTAG_RAM_BITS : integer := DPTAG_BITS
;
constant DTAG_RAM_BITS : integer := DTAG_BITS
;
subtype dtdatain_vector is std_logic_vector(DTWIDTH downto 0);
type dtdatain_type is array (0 to MAXSETS-1) of dtdatain_vector;
subtype itdatain_vector is std_logic_vector(ITWIDTH downto 0);
type itdatain_type is array (0 to MAXSETS-1) of itdatain_vector;
subtype dddatain_vector is std_logic_vector(DDWIDTH-1 downto 0);
type dddatain_type is array (0 to MAXSETS-1) of dddatain_vector;
subtype itdataout_vector is std_logic_vector(ITWIDTH downto 0);
type itdataout_type is array (0 to MAXSETS-1) of itdataout_vector;
subtype iddataout_vector is std_logic_vector(IDWIDTH -1 downto 0);
type iddataout_type is array (0 to MAXSETS-1) of iddataout_vector;
subtype dtdataout_vector is std_logic_vector(DTWIDTH downto 0);
type dtdataout_type is array (0 to MAXSETS-1) of dtdataout_vector;
subtype dddataout_vector is std_logic_vector(DDWIDTH -1 downto 0);
type dddataout_type is array (0 to MAXSETS-1) of dddataout_vector;
signal itaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
signal idaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
signal ildaddr : std_logic_vector(ILRAM_BITS-3 downto 0);
signal itdatain : itdatain_type;
signal itdatainx : itdatain_type;
signal itdatain_cmp : itdatain_type;
signal itdataout : itdataout_type;
signal iddatain : std_logic_vector(IDWIDTH -1 downto 0);
signal iddatainx : std_logic_vector(IDWIDTH -1 downto 0);
signal iddatain_cmp : std_logic_vector(IDWIDTH -1 downto 0);
signal iddataout : iddataout_type;
signal ildataout : std_logic_vector(31 downto 0);
signal itenable : std_ulogic;
signal idenable : std_ulogic;
signal itwrite : std_logic_vector(0 to MAXSETS-1);
signal idwrite : std_logic_vector(0 to MAXSETS-1);
signal dtaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr2 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal dtaddr3 : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal ddaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
signal ldaddr : std_logic_vector(DLRAM_BITS-1 downto 2);
signal dtdatain : dtdatain_type;
signal dtdatainx : dtdatain_type;
signal dtdatain_cmp : dtdatain_type;
signal dtdatain2 : dtdatain_type;
signal dtdatain3 : dtdatain_type;
signal dtdatainu : dtdatain_type;
signal dtdataout : dtdataout_type;
signal dtdataout2: dtdataout_type;
signal dtdataout3: dtdataout_type;
signal dddatain : dddatain_type;
signal dddatainx : dddatain_type;
signal dddatain_cmp : dddatain_type;
signal dddataout : dddataout_type;
signal lddatain, ldataout : std_logic_vector(31 downto 0);
signal dtenable : std_logic_vector(0 to MAXSETS-1);
signal dtenable2 : std_logic_vector(0 to MAXSETS-1);
signal ddenable : std_logic_vector(0 to MAXSETS-1);
signal dtwrite : std_logic_vector(0 to MAXSETS-1);
signal dtwrite2 : std_logic_vector(0 to MAXSETS-1);
signal dtwrite3 : std_logic_vector(0 to MAXSETS-1);
signal ddwrite : std_logic_vector(0 to MAXSETS-1);
signal vcc, gnd : std_ulogic;
begin
vcc <= '1'; gnd <= '0';
itaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
idaddr <= crami.icramin.address(IOFFSET_BITS + ILINE_BITS -1 downto 0);
ildaddr <= crami.icramin.address(ILRAM_BITS-3 downto 0);
itinsel : process(clk, crami, dtdataout2, dtdataout3
)
variable viddatain : std_logic_vector(IDWIDTH -1 downto 0);
variable vdddatain : dddatain_type;
variable vitdatain : itdatain_type;
variable vdtdatain : dtdatain_type;
variable vdtdatain2 : dtdatain_type;
variable vdtdatain3 : dtdatain_type;
variable vdtdatainu : dtdatain_type;
begin
viddatain := (others => '0');
vdddatain := (others => (others => '0'));
viddatain(31 downto 0) := crami.icramin.data;
for i in 0 to DSETS-1 loop
vdtdatain(i) := (others => '0');
if mmuen = 1 then
vdtdatain(i)(DTMMU_VEC_U downto DTMMU_VEC_D) := crami.dcramin.ctx(i);
end if;
vdtdatain(i)(DTLOCK_BIT_POS) := crami.dcramin.tag(i)(CTAG_LOCKPOS);
if drepl = lrr then
vdtdatain(i)(DTLRR_BIT_POS) := crami.dcramin.tag(i)(CTAG_LRRPOS);
end if;
vdtdatain(i)(DTAG_BITS-1 downto 0) := crami.dcramin.tag(i)(TAG_HIGH downto DTAG_LOW) & crami.dcramin.tag(i)(dlinesize-1 downto 0);
if (crami.dcramin.flush = '1') then
vdtdatain(i) := (others => '0');
vdtdatain(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"FF";
vdtdatain(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
for i in 0 to DSETS-1 loop
vdtdatain2(i) := (others => '0');
vdddatain(i)(31 downto 0) := crami.dcramin.data(i);
vdtdatain2(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"FF";
vdtdatain2(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain2(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end loop;
vdtdatainu := (others => (others => '0'));
vdtdatain3 := (others => (others => '0'));
for i in 0 to DSETS-1 loop
vdtdatain3(i) := (others => '0');
vdtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-DPTAG_BITS) := crami.dcramin.ptag(i)(TAG_HIGH downto DTAG_LOW);
if DSNOOPSEP and (crami.dcramin.flush = '1') then
vdtdatain3(i) := (others => '0');
vdtdatain3(i)(DTAG_BITS-1 downto DTAG_BITS-8) := X"F3";
vdtdatain3(i)(DTAG_BITS-9 downto DTAG_BITS-10) := conv_std_logic_vector(i,2);
vdtdatain3(i)(DTAG_BITS-11 downto DTAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
for i in 0 to ISETS-1 loop
vitdatain(i) := (others => '0');
if mmuen = 1 then
vitdatain(i)(ITMMU_VEC_U downto ITMMU_VEC_D) := crami.icramin.ctx;
end if;
vitdatain(i)(ITLOCK_BIT_POS) := crami.icramin.tag(i)(CTAG_LOCKPOS);
if irepl = lrr then
vitdatain(i)(ITLRR_BIT_POS) := crami.icramin.tag(i)(CTAG_LRRPOS);
end if;
vitdatain(i)(ITAG_BITS-1 downto 0) := crami.icramin.tag(i)(TAG_HIGH downto ITAG_LOW)
& crami.icramin.tag(i)(ilinesize-1 downto 0);
if (crami.icramin.flush = '1') then
vitdatain(i) := (others => '0');
vitdatain(i)(ITAG_BITS-1 downto ITAG_BITS-8) := X"FF";
vitdatain(i)(ITAG_BITS-9 downto ITAG_BITS-10) := conv_std_logic_vector(i,2);
vitdatain(i)(ITAG_BITS-11 downto ITAG_BITS-12) := conv_std_logic_vector(i,2);
end if;
end loop;
-- pragma translate_off
itdatainx <= vitdatain; iddatainx <= viddatain;
dtdatainx <= vdtdatain; dddatainx <= vdddatain;
-- pragma translate_on
itdatain <= vitdatain; iddatain <= viddatain;
dtdatain <= vdtdatain; dtdatain2 <= vdtdatain2; dddatain <= vdddatain;
dtdatain3 <= vdtdatain3;
end process;
itwrite <= crami.icramin.twrite;
idwrite <= crami.icramin.dwrite;
itenable <= crami.icramin.tenable;
idenable <= crami.icramin.denable;
dtaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
dtaddr2 <= crami.dcramin.saddress(DOFFSET_BITS-1 downto 0);
dtaddr3 <= crami.dcramin.faddress(DOFFSET_BITS-1 downto 0);
ddaddr <= crami.dcramin.address(DOFFSET_BITS + DLINE_BITS -1 downto 0);
ldaddr <= crami.dcramin.ldramin.address(DLRAM_BITS-1 downto 2);
dtwrite <= crami.dcramin.twrite;
dtwrite2 <= crami.dcramin.swrite;
dtwrite3 <= crami.dcramin.tpwrite;
ddwrite <= crami.dcramin.dwrite;
dtenable <= crami.dcramin.tenable;
dtenable2 <= crami.dcramin.senable;
ddenable <= crami.dcramin.denable;
ime : if icen = 1 generate
im0 : for i in 0 to ISETS-1 generate
itags0 : syncram generic map (tech, IOFFSET_BITS, ITWIDTH, testen)
port map ( clk, itaddr, itdatain(i)(ITWIDTH-1 downto 0), itdataout(i)(ITWIDTH-1 downto 0), itenable, itwrite(i), crami.dcramin.tdiag);
idata0 : syncram generic map (tech, IOFFSET_BITS+ILINE_BITS, IDWIDTH, testen)
port map (clk, idaddr, iddatain, iddataout(i), idenable, idwrite(i), crami.dcramin.ddiag);
itdataout(i)(ITWIDTH) <= '0';
end generate;
end generate;
imd : if icen = 0 generate
ind0 : for i in 0 to ISETS-1 generate
itdataout(i) <= (others => '0');
iddataout(i) <= (others => '0');
end generate;
end generate;
ild0 : if ilram = 1 generate
ildata0 : syncram
generic map (tech, ILRAM_BITS-2, 32, testen)
port map (clk, ildaddr, iddatain, ildataout,
crami.icramin.ldramin.enable, crami.icramin.ldramin.write, crami.dcramin.ddiag);
end generate;
dme : if dcen = 1 generate
dtags0 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram
generic map (tech, DOFFSET_BITS, DTWIDTH, testen)
port map (clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i), crami.dcramin.tdiag);
end generate;
end generate;
dtags1 : if DSNOOP /= 0 generate
dt1 : if not DSNOOPSEP generate
dt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto 0),
dtdataout(i)(DTWIDTH-1 downto 0), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto 0),
dtdataout2(i)(DTWIDTH-1 downto 0), dtenable2(i), dtwrite2(i), crami.dcramin.tdiag);
end generate;
end generate;
-- virtual address snoop case
mdt1 : if DSNOOPSEP generate
slow : if not DSNOOPFAST generate
mdt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_dp
generic map (tech, DOFFSET_BITS, DTWIDTH-dlinesize+1) port map (
clk, dtaddr, dtdatain(i)(DTWIDTH-1 downto dlinesize-1),
dtdataout(i)(DTWIDTH-1 downto dlinesize-1), dtenable(i), dtwrite(i),
sclk, dtaddr2, dtdatain2(i)(DTWIDTH-1 downto dlinesize-1),
dtdataout2(i)(DTWIDTH-1 downto dlinesize-1), dtenable2(i), dtwrite2(i), crami.dcramin.tdiag);
dtags1 : syncram_dp
generic map (tech, DOFFSET_BITS, DPTAG_RAM_BITS) port map (
clk, dtaddr, dtdatain3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
open, dtwrite3(i), dtwrite3(i),
sclk, dtaddr2, dtdatainu(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
dtdataout3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS), dtenable2(i), dtwrite2(i), crami.dcramin.sdiag);
end generate;
end generate;
fast : if DSNOOPFAST generate
mdt0 : for i in 0 to DSETS-1 generate
dtags0 : syncram_2p
generic map (tech, DOFFSET_BITS, DTWIDTH-dlinesize+1, 0, 1, testen) port map (
clk, dtenable(i), dtaddr, dtdataout(i)(DTWIDTH-1 downto dlinesize-1),
sclk, dtwrite2(i), dtaddr3, dtdatain(i)(DTWIDTH-1 downto dlinesize-1), crami.dcramin.tdiag);
dtags1 : syncram_2p
generic map (tech, DOFFSET_BITS, DPTAG_RAM_BITS, 0, 1, testen) port map (
sclk, dtenable2(i), dtaddr2, dtdataout3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS),
clk, dtwrite3(i), dtaddr, dtdatain3(i)(DTAG_RAM_BITS-1 downto DTAG_BITS-DPTAG_BITS), crami.dcramin.sdiag);
end generate;
end generate;
end generate;
end generate;
nodtags1 : if DSNOOP = 0 generate
dt0 : for i in 0 to DSETS-1 generate
dtdataout2(i)(DTWIDTH-1 downto 0) <= zero64(DTWIDTH-1 downto 0);
end generate;
end generate;
dd0 : for i in 0 to DSETS-1 generate
ddata0 : syncram
generic map (tech, DOFFSET_BITS+DLINE_BITS, DDWIDTH, testen)
port map (clk, ddaddr, dddatain(i), dddataout(i), ddenable(i), ddwrite(i), crami.dcramin.ddiag);
dtdataout(i)(DTWIDTH) <= '0';
end generate;
end generate;
dmd : if dcen = 0 generate
dnd0 : for i in 0 to DSETS-1 generate
dtdataout(i) <= (others => '0');
dtdataout2(i) <= (others => '0');
dddataout(i) <= (others => '0');
end generate;
end generate;
ldxs0 : if not ((dlram = 1) and (DSETS > 1)) generate
lddatain <= dddatain(0)(31 downto 0);
end generate;
ldxs1 : if (dlram = 1) and (DSETS > 1) generate
lddatain <= dddatain(1)(31 downto 0);
end generate;
ld0 : if dlram = 1 generate
ldata0 : syncram
generic map (tech, DLRAM_BITS-2, 32, testen)
port map (clk, ldaddr, lddatain, ldataout, crami.dcramin.ldramin.enable,
crami.dcramin.ldramin.write, crami.dcramin.ddiag);
end generate;
itx : for i in 0 to ISETS-1 generate
cramo.icramo.tag(i)(TAG_HIGH downto ITAG_LOW) <= itdataout(i)(ITAG_BITS-1 downto (ITAG_BITS-1) - (TAG_HIGH - ITAG_LOW));
--(ITWIDTH-1-(ILRR_BIT+ICLOCK_BIT) downto ITWIDTH-(TAG_HIGH-ITAG_LOW)-(ILRR_BIT+ICLOCK_BIT)-1);
cramo.icramo.tag(i)(ilinesize-1 downto 0) <= itdataout(i)(ilinesize-1 downto 0);
cramo.icramo.tag(i)(CTAG_LRRPOS) <= itdataout(i)(ITLRR_BIT_POS);
cramo.icramo.tag(i)(CTAG_LOCKPOS) <= itdataout(i)(ITLOCK_BIT_POS);
ictx : if mmuen = 1 generate
cramo.icramo.ctx(i) <= itdataout(i)(ITMMU_VEC_U downto ITMMU_VEC_D);
end generate;
noictx : if mmuen = 0 generate
cramo.icramo.ctx(i) <= (others => '0');
end generate;
cramo.icramo.data(i) <= ildataout when (ilram = 1) and ((ISETS = 1) or (i = 1)) and (crami.icramin.ldramin.read = '1') else iddataout(i)(31 downto 0);
itv : if ilinesize = 4 generate
cramo.icramo.tag(i)(7 downto 4) <= (others => '0');
end generate;
ite : for j in 10 to ITAG_LOW-1 generate
cramo.icramo.tag(i)(j) <= '0';
end generate;
end generate;
itx2 : for i in ISETS to MAXSETS-1 generate
cramo.icramo.tag(i) <= (others => '0');
cramo.icramo.data(i) <= (others => '0');
cramo.icramo.ctx(i) <= (others => '0');
end generate;
itd : for i in 0 to DSETS-1 generate
cramo.dcramo.tag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
-- cramo.dcramo.tag(i)(dlinesize-1 downto 0) <= dtdataout(i)(dlinesize-1 downto 0);
cramo.dcramo.tag(i)(dlinesize-1 downto 0) <= (others => dtdataout(i)(dlinesize-1));
cramo.dcramo.tag(i)(CTAG_LRRPOS) <= dtdataout(i)(DTLRR_BIT_POS);
cramo.dcramo.tag(i)(CTAG_LOCKPOS) <= dtdataout(i)(DTLOCK_BIT_POS);
dctx : if mmuen /= 0 generate
cramo.dcramo.ctx(i) <= dtdataout(i)(DTMMU_VEC_U downto DTMMU_VEC_D);
end generate;
nodctx : if mmuen = 0 generate
cramo.dcramo.ctx(i) <= (others => '0');
end generate;
stagv : if DSNOOPSEP generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout3(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
cramo.dcramo.stag(i)(DTAG_LOW-1 downto 0) <= (others =>'0');
end generate;
stagp : if not DSNOOPSEP generate
cramo.dcramo.stag(i)(TAG_HIGH downto DTAG_LOW) <= dtdataout2(i)(DTAG_BITS-1 downto (DTAG_BITS-1) - (TAG_HIGH - DTAG_LOW));
cramo.dcramo.stag(i)(DTAG_LOW-1 downto 0) <= (others =>'0');
end generate;
cramo.dcramo.data(i) <= ldataout when (dlram = 1) and ((DSETS = 1) or (i = 1)) and (crami.dcramin.ldramin.read = '1')
else dddataout(i)(31 downto 0);
dtv : if dlinesize = 4 generate
cramo.dcramo.tag(i)(7 downto 4) <= (others => '0');
end generate;
dte : for j in 10 to DTAG_LOW-1 generate
cramo.dcramo.tag(i)(j) <= '0';
end generate;
end generate;
itd2 : for i in DSETS to MAXSETS-1 generate
cramo.dcramo.tag(i) <= (others => '0');
cramo.dcramo.stag(i) <= (others => '0');
cramo.dcramo.data(i) <= (others => '0');
cramo.dcramo.ctx(i) <= (others => '0');
end generate;
end ;
| gpl-2.0 | 6c7bfd7c77183ad99a9cdb023e76d6c8 | 0.618111 | 3.526273 | false | false | false | false |
freecores/mdct | source/xilinx/ram_xil.vhd | 1 | 5,133 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2004 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file ram_xil.vhd when simulating
-- the core, ram_xil. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Guide".
-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib;
ENTITY ram_xil IS
port (
addra: IN std_logic_VECTOR(5 downto 0);
addrb: IN std_logic_VECTOR(5 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(9 downto 0);
dinb: IN std_logic_VECTOR(9 downto 0);
douta: OUT std_logic_VECTOR(9 downto 0);
wea: IN std_logic;
web: IN std_logic);
END ram_xil;
ARCHITECTURE ram_xil_a OF ram_xil IS
component wrapped_ram_xil
port (
addra: IN std_logic_VECTOR(5 downto 0);
addrb: IN std_logic_VECTOR(5 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(9 downto 0);
dinb: IN std_logic_VECTOR(9 downto 0);
douta: OUT std_logic_VECTOR(9 downto 0);
wea: IN std_logic;
web: IN std_logic);
end component;
-- Configuration specification
for all : wrapped_ram_xil use entity XilinxCoreLib.blkmemdp_v6_1(behavioral)
generic map(
c_reg_inputsb => 0,
c_reg_inputsa => 0,
c_has_ndb => 0,
c_has_nda => 0,
c_ytop_addr => "1024",
c_has_rfdb => 0,
c_has_rfda => 0,
c_yena_is_high => 1,
c_ywea_is_high => 1,
c_yclka_is_rising => 1,
c_yhierarchy => "hierarchy1",
c_ysinita_is_high => 1,
c_ybottom_addr => "0",
c_width_b => 10,
c_width_a => 10,
c_sinita_value => "0",
c_sinitb_value => "0",
c_limit_data_pitch => 18,
c_write_modeb => 2,
c_write_modea => 2,
c_has_rdyb => 0,
c_has_rdya => 0,
c_yuse_single_primitive => 0,
c_addra_width => 6,
c_addrb_width => 6,
c_has_limit_data_pitch => 0,
c_default_data => "0",
c_pipe_stages_b => 0,
c_yweb_is_high => 1,
c_yenb_is_high => 1,
c_pipe_stages_a => 0,
c_yclkb_is_rising => 1,
c_yydisable_warnings => 1,
c_enable_rlocs => 0,
c_ysinitb_is_high => 1,
c_has_default_data => 1,
c_has_web => 1,
c_has_sinitb => 0,
c_has_wea => 1,
c_has_sinita => 0,
c_has_dinb => 1,
c_has_dina => 1,
c_ymake_bmm => 0,
c_has_enb => 0,
c_has_ena => 0,
c_depth_b => 64,
c_mem_init_file => "mif_file_16_1",
c_depth_a => 64,
c_has_doutb => 0,
c_has_douta => 1,
c_yprimitive_type => "16kx1");
BEGIN
U0 : wrapped_ram_xil
port map (
addra => addra,
addrb => addrb,
clka => clka,
clkb => clkb,
dina => dina,
dinb => dinb,
douta => douta,
wea => wea,
web => web);
END ram_xil_a;
-- synopsys translate_on
| lgpl-3.0 | 2be4eadf9e705ebe4488778f916867b6 | 0.549386 | 3.554709 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/Zynq_Book/hls/tut3A/matrix_mult_prj/solution5/syn/vhdl/matrix_mult_mac_mdEe.vhd | 3 | 3,018 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity matrix_mult_mac_mdEe_DSP48_1 is
port (
clk: in std_logic;
rst: in std_logic;
ce: in std_logic;
in0: in std_logic_vector(8 - 1 downto 0);
in1: in std_logic_vector(8 - 1 downto 0);
in2: in std_logic_vector(16 - 1 downto 0);
dout: out std_logic_vector(16 - 1 downto 0));
attribute use_dsp48 : string;
attribute use_dsp48 of matrix_mult_mac_mdEe_DSP48_1 : entity is "yes";
end entity;
architecture behav of matrix_mult_mac_mdEe_DSP48_1 is
signal a : signed(25-1 downto 0);
signal b : signed(18-1 downto 0);
signal c : signed(48-1 downto 0);
signal m : signed(43-1 downto 0);
signal p : signed(48-1 downto 0);
signal m_reg : signed(43-1 downto 0);
signal a_reg : signed(25-1 downto 0);
signal b_reg : signed(18-1 downto 0);
begin
a <= signed(resize(signed(in0), 25));
b <= signed(resize(signed(in1), 18));
c <= signed(resize(signed(in2), 48));
m <= a_reg * b_reg;
p <= m_reg + c;
process (clk) begin
if (clk'event and clk = '1') then
if (ce = '1') then
m_reg <= m;
a_reg <= a;
b_reg <= b;
end if;
end if;
end process;
dout <= std_logic_vector(resize(unsigned(p), 16));
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity matrix_mult_mac_mdEe is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
din2 : IN STD_LOGIC_VECTOR(din2_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of matrix_mult_mac_mdEe is
component matrix_mult_mac_mdEe_DSP48_1 is
port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
ce : IN STD_LOGIC;
in0 : IN STD_LOGIC_VECTOR;
in1 : IN STD_LOGIC_VECTOR;
in2 : IN STD_LOGIC_VECTOR;
dout : OUT STD_LOGIC_VECTOR);
end component;
begin
matrix_mult_mac_mdEe_DSP48_1_U : component matrix_mult_mac_mdEe_DSP48_1
port map (
clk => clk,
rst => reset,
ce => ce,
in0 => din0,
in1 => din1,
in2 => din2,
dout => dout);
end architecture;
| mit | 21307905ecaad5e0da24693eea734f17 | 0.526839 | 3.287582 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/CNN_Optimization/cnn_optimization/solution1_2/syn/vhdl/convolve_kernel_fcud.vhd | 1 | 3,164 | -- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
Library ieee;
use ieee.std_logic_1164.all;
entity convolve_kernel_fcud is
generic (
ID : integer := 8;
NUM_STAGE : integer := 5;
din0_WIDTH : integer := 32;
din1_WIDTH : integer := 32;
dout_WIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
ce : in std_logic;
din0 : in std_logic_vector(din0_WIDTH-1 downto 0);
din1 : in std_logic_vector(din1_WIDTH-1 downto 0);
dout : out std_logic_vector(dout_WIDTH-1 downto 0)
);
end entity;
architecture arch of convolve_kernel_fcud is
--------------------- Component ---------------------
component convolve_kernel_ap_fmul_3_max_dsp_32 is
port (
aclk : in std_logic;
aclken : in std_logic;
s_axis_a_tvalid : in std_logic;
s_axis_a_tdata : in std_logic_vector(31 downto 0);
s_axis_b_tvalid : in std_logic;
s_axis_b_tdata : in std_logic_vector(31 downto 0);
m_axis_result_tvalid : out std_logic;
m_axis_result_tdata : out std_logic_vector(31 downto 0)
);
end component;
--------------------- Local signal ------------------
signal aclk : std_logic;
signal aclken : std_logic;
signal a_tvalid : std_logic;
signal a_tdata : std_logic_vector(31 downto 0);
signal b_tvalid : std_logic;
signal b_tdata : std_logic_vector(31 downto 0);
signal r_tvalid : std_logic;
signal r_tdata : std_logic_vector(31 downto 0);
signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0);
signal din1_buf1 : std_logic_vector(din1_WIDTH-1 downto 0);
begin
--------------------- Instantiation -----------------
convolve_kernel_ap_fmul_3_max_dsp_32_u : component convolve_kernel_ap_fmul_3_max_dsp_32
port map (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => a_tvalid,
s_axis_a_tdata => a_tdata,
s_axis_b_tvalid => b_tvalid,
s_axis_b_tdata => b_tdata,
m_axis_result_tvalid => r_tvalid,
m_axis_result_tdata => r_tdata
);
--------------------- Assignment --------------------
aclk <= clk;
aclken <= ce;
a_tvalid <= '1';
a_tdata <= din0_buf1;
b_tvalid <= '1';
b_tdata <= din1_buf1;
dout <= r_tdata;
--------------------- Input buffer ------------------
process (clk) begin
if clk'event and clk = '1' then
if ce = '1' then
din0_buf1 <= din0;
din1_buf1 <= din1;
end if;
end if;
end process;
end architecture;
| mit | e139519d146b43320559780cde691eab | 0.46713 | 3.739953 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/leon3v3/grfpwx.vhd | 1 | 4,312 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwx
-- File: grfpwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity grfpwx is
generic (fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 3 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end;
architecture rtl of grfpwx is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
signal rf1rd1, rf1rd2, rf2rd1, rf2rd2, rf1wd, rf2wd : std_logic_vector(38 downto 0);
begin
x1 : if true generate
grfpw0 : grfpw_net generic map (fabtech, pclow, dsu, disas)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
rf1 : regfile_3p_l3 generic map (memtech, 4, 32, 1, 16
)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr,
rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2
);
rf2 : regfile_3p_l3 generic map (memtech, 4, 32, 1, 16
)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr,
rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2
);
end;
| gpl-2.0 | c77d64bd851c68947f38f29d878db05f | 0.507885 | 3.350427 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/ddr/ddr2spax_ahb.vhd | 1 | 16,792 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr2spa_ahb
-- File: ddr2spa_ahb.vhd
-- Author: Magnus Hjorth - Aeroflex Gaisler
-- Description: Asynch AHB interface for DDR memory controller
-- Based on ddr2sp(16/32/64)a, generalized and expanded
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
use gaisler.ddrpkg.all;
use gaisler.ddrintpkg.all;
entity ddr2spax_ahb is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
burstlen : integer := 8;
nosync : integer := 0;
ahbbits : integer := ahbdw;
revision : integer := 0;
devid : integer := GAISLER_DDR2SP;
ddrbits : integer := 32;
regarea : integer := 0
);
port (
rst : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
request : out ddr_request_type;
start_tog: out std_logic;
response : in ddr_response_type;
wbwaddr : out std_logic_vector(log2(burstlen) downto 0);
wbwdata : out std_logic_vector(ahbbits-1 downto 0);
wbwrite : out std_logic;
wbwritebig: out std_logic;
rbraddr : out std_logic_vector(log2(burstlen*32/ahbbits)-1 downto 0);
rbrdata : in std_logic_vector(ahbbits-1 downto 0);
hwidth : in std_logic;
beid : in std_logic_vector(3 downto 0)
);
end ddr2spax_ahb;
architecture rtl of ddr2spax_ahb is
constant CMD_PRE : std_logic_vector(2 downto 0) := "010";
constant CMD_REF : std_logic_vector(2 downto 0) := "100";
constant CMD_LMR : std_logic_vector(2 downto 0) := "110";
constant CMD_EMR : std_logic_vector(2 downto 0) := "111";
constant ramwt: integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, DEVID, 0, REVISION, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
5 => ahb_iobar(ioaddr, iomask),
others => zero32);
function zerov(w: integer) return std_logic_vector is
constant r: std_logic_vector(w-1 downto 0) := (others => '0');
begin
return r;
end zerov;
constant l2blen: integer := log2(burstlen)+log2(32);
constant l2ahbw: integer := log2(ahbbits);
constant l2ddrw: integer := log2(2*ddrbits);
-- Write buffer dimensions
-- Write buffer is addressable down to 32-bit level on write (AHB) side.
constant wbuf_wabits: integer := 1+l2blen-5; -- log2(burstlen);
constant wbuf_wdbits: integer := ahbbits;
-- Read buffer dimensions
constant rbuf_rabits: integer := l2blen-l2ahbw; -- log2(burstlen*32/ahbbits);
constant rbuf_rdbits: integer := ahbbits;
type ahbstate is (asnormal,asw1,asw2,asww1,asww2,aswr,aswwx);
type ahb_reg_type is record
s : ahbstate;
start_tog : std_logic;
ramaddr : std_logic_vector(l2blen-4 downto 2);
-- These are sent to the DDR layer
req : ddr_request_type;
-- Posted write following current request
nreq : ddr_request_type;
-- Read flow control
rctr_lin : std_logic_vector(3 downto 0);
endpos : std_logic_vector(7 downto log2(ddrbits/4));
block_read: std_logic_vector(1 downto 0);
-- Current AHB control signals
haddr : std_logic_vector(31 downto 0);
haddr_nonseq: std_logic_vector(9 downto 0);
hio : std_logic;
hsize : std_logic_vector(2 downto 0);
hwrite : std_logic;
hburst0 : std_logic;
-- AHB slave outputs
so_hready : std_logic;
-- From DDR layer
resp1,resp2: ddr_response_type;
end record;
signal ar,nar : ahb_reg_type;
begin
ahbcomb : process(ahbsi,rst,ar,response,rbrdata)
variable av: ahb_reg_type;
variable va2d: ddr_request_type;
variable so: ahb_slv_out_type;
variable vdone: std_logic;
variable vresp: ddr_response_type;
variable bigsize,midsize,canburst: std_logic;
variable inc_ramaddr: std_logic;
variable row: std_logic_vector(14 downto 0);
variable wbwa: std_logic_vector(wbuf_wabits-1 downto 0);
variable wbwd: std_logic_vector(wbuf_wdbits-1 downto 0);
variable wbw,wbwb: std_logic;
variable rbra: std_logic_vector(rbuf_rabits-1 downto 0);
variable ha0: std_logic_vector(31 downto 0);
variable rend,nrend: std_logic_vector(7 downto log2(ddrbits/4));
variable datavalid, writedone: std_logic;
variable rctr_gray: std_logic_vector(3 downto 0);
variable tog_start: std_logic;
variable regdata: std_logic_vector(31 downto 0);
begin
ha0 := ahbsi.haddr;
ha0(31 downto 20) := ha0(31 downto 20) and not std_logic_vector(to_unsigned(hmask,12));
av := ar;
so := (hready => ar.so_hready, hresp => HRESP_OKAY, hrdata => (others => '0'),
hsplit => (others => '0'), hirq => (others => '0'),
hconfig => hconfig, hindex => hindex);
wbw := '0';
wbwb := '0';
wbwa := ar.start_tog & ar.ramaddr;
wbwd := ahbreaddata(ahbsi.hwdata,ar.haddr(4 downto 2),
std_logic_vector(to_unsigned(log2(ahbbits/8),3)));
rbra := ar.ramaddr(l2blen-4 downto l2ahbw-3);
-- Determine whether the current hsize is a big (ahbbits-width) access
bigsize := '0';
if (ahbbits = 256 and ar.hsize(2)='1' and ar.hsize(0)='1') or
(ahbbits = 128 and ar.hsize(2)='1') or
(ahbbits = 64 and ar.hsize="011") then
bigsize := '1';
end if;
midsize := '0';
if ( (ahbbits = 256 and ((ar.hsize(2)='1' and ar.hsize(0)='0') or (ar.hsize(1 downto 0)="11"))) or
(ahbbits = 128 and ar.hsize="011") ) then
midsize := '1';
end if;
-- Determine whether sequential burst is allowed after current access
canburst := '0';
if (bigsize='1' and ar.haddr(l2blen-4 downto l2ahbw-3)/=(not zerov(l2blen-l2ahbw))) or
(ar.hsize="010" and ar.haddr(l2blen-4 downto 2)/=(not zerov(l2blen-5))) then
canburst := '1';
end if;
-- if canburst='1' then
-- print("ar.hsize=" & tost(ar.hsize) & "ar.haddr: " & tost(ar.haddr(l2blen-4 downto 2)) & " /= " & tost(not zerov(l2blen-5)));
-- end if;
if ar.hio='1' then
canburst := '0';
end if;
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
av.haddr := ha0;
av.ramaddr := ha0(log2(4*burstlen)-1 downto 2);
av.hio := ahbsi.hmbsel(1);
av.hsize := ahbsi.hsize;
av.hwrite := ahbsi.hwrite;
av.hburst0 := ahbsi.hburst(0);
if ahbsi.htrans(0)='0' or canburst='0' then
av.haddr_nonseq := ha0(9 downto 0);
end if;
end if;
-- Synchronize from DDR domain
av.resp1:=response; av.resp2:=ar.resp1;
vresp := ar.resp2;
if nosync /= 0 then vresp := response; end if;
vdone := vresp.done_tog;
-- Determine whether we can read more data in burst
datavalid := '0';
writedone := '0';
if ar.start_tog=vdone then
datavalid := '1';
writedone := '1';
end if;
if ar.rctr_lin="0000" then rend:=ar.haddr(7 downto l2ddrw-3); else rend:=ar.endpos; end if;
nrend := std_logic_vector(unsigned(rend)+1);
rctr_gray := lin2gray(ar.rctr_lin);
if ar.start_tog/=vdone and rctr_gray /= vresp.rctr_gray and ar.block_read(0)='0' then
av.rctr_lin := std_logic_vector(unsigned(ar.rctr_lin)+1);
av.endpos := nrend;
rend := nrend;
end if;
if 2*ddrbits > ahbbits then
if rend /= ar.haddr(7 downto log2(ddrbits/4)) then
datavalid := '1';
end if;
else
if rend(7 downto log2(ahbbits/8)) /= ar.haddr(7 downto log2(ahbbits/8)) then
datavalid := '1';
end if;
if 2*ddrbits < ahbbits and ahbbits > 32 then
if ar.hsize="010" or ar.hsize="001" or ar.hsize="000" then
if rend(log2(ahbbits/8)-1 downto log2(ddrbits/4)) /=
ar.haddr(log2(ahbbits/8)-1 downto log2(ddrbits/4)) then
datavalid := '1';
end if;
end if;
end if;
end if;
if ar.block_read(1)='1' or (ar.start_tog/=vdone and ar.block_read(0)='1') then
datavalid := '0';
writedone := '0';
end if;
if ar.block_read(1)='1' and ar.start_tog/=vdone then
av.block_read(1) := '0';
end if;
if ar.block_read(1)='0' and vresp.rctr_gray="0000" then
av.block_read(0) := '0';
end if;
-- FSM
inc_ramaddr := '0';
tog_start := '0';
case ar.s is
when asnormal =>
-- Idle and memory read state
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
-- Pass on address immediately to request for read case
av.req := (startaddr => ha0,
endaddr => ha0(9 downto 0),
hsize => ahbsi.hsize,
hwrite => ahbsi.hwrite,
hio => ahbsi.hmbsel(1),
burst => ahbsi.hburst(0),
maskdata => '0', maskcb => '0');
if ahbsi.hwrite='0' then
if ahbsi.htrans(0)='0' or canburst='0' then
av.so_hready := '0';
tog_start := '1';
elsif datavalid='1' then
inc_ramaddr := '1';
else
av.so_hready := '0';
-- grlib.testlib.print("Going to waitstate!");
end if;
else
av.s := asw1;
end if;
end if;
if ar.so_hready='0' and datavalid='1' then
av.so_hready := '1';
inc_ramaddr := '1';
end if;
when asw1 =>
-- Transfer data for write request
wbw := '1';
if bigsize='1' or midsize='1' then wbwb:='1'; end if;
av.so_hready := '1';
av.req.endaddr := ar.haddr(9 downto 0);
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.htrans(0)='0' or canburst='0' then
if ahbsi.hwrite='1' then
av.s := asww1;
else
av.so_hready := '0';
av.s := aswr;
end if;
tog_start := '1';
end if;
else
av.s := asw2;
tog_start := '1';
end if;
when asw2 =>
-- Write request ongoing
av.so_hready := '1';
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.hwrite='1' then
av.s := asww1;
else
av.so_hready := '0';
av.s := aswr;
end if;
elsif writedone='1' then
av.s := asnormal;
end if;
when asww1 =>
-- Transfer data for second write while write request ongoing
wbw := '1';
if bigsize='1' or midsize='1' then wbwb:='1'; end if;
av.so_hready := '1';
av.nreq := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
if ahbsi.htrans(0)='0' or canburst='0' then
av.so_hready := '0';
av.s := aswwx;
end if;
else
av.s := asww2;
end if;
when asww2 =>
-- Second write enqueued, wait for first write to finish
-- Any new request here will cause HREADY to go low
av.so_hready := '1';
if ahbsi.hready='1' and ahbsi.hsel(hindex)='1' and ahbsi.htrans(1)='1' then
av.so_hready := '0';
av.s := aswwx;
elsif writedone='1' then
av.req := ar.nreq;
tog_start := '1';
av.s := asw2;
end if;
when aswr =>
-- Read request following ongoing write request
-- HREADY is low in this state
av.so_hready := '0';
if writedone='1' then
av.req := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
av.hwrite := '0';
tog_start := '1';
av.s := asnormal;
end if;
when aswwx =>
-- Write ongoing + write posted + another AHB request (read or write)
-- Keep HREADY low
av.so_hready := '0';
if writedone='1' then
tog_start := '1';
av.req := ar.nreq;
if ar.hwrite='1' then
av.nreq := (startaddr => ar.haddr(31 downto 10) & ar.haddr_nonseq(9 downto 0),
endaddr => ar.haddr(9 downto 0),
hsize => ar.hsize,
hwrite => ar.hwrite,
hio => ar.hio,
burst => ar.hburst0,
maskdata => '0', maskcb => '0');
av.so_hready := '1';
av.s := asww1;
else
av.s := aswr;
end if;
end if;
end case;
if tog_start='1' and (regarea=0 or av.req.hio='0' or av.req.startaddr(5)='0') then
av.start_tog := not ar.start_tog;
av.rctr_lin := "0000";
if ar.start_tog /= vdone then
av.block_read(1) := '1';
end if;
av.block_read(0) := '1';
end if;
if inc_ramaddr='1' then
if bigsize='1' then
av.ramaddr(log2(4*burstlen)-1 downto log2(ahbbits/8)) :=
std_logic_vector(unsigned(ar.ramaddr(log2(4*burstlen)-1 downto log2(ahbbits/8)))+1);
else
av.ramaddr(log2(4*burstlen)-1 downto 2) :=
std_logic_vector(unsigned(ar.ramaddr(log2(4*burstlen)-1 downto 2))+1);
end if;
end if;
-- Used only if regarea /= 0
regdata := (others => '0');
regdata(18 downto 16) := std_logic_vector(to_unsigned(log2(ddrbits/8),3));
if hwidth/='0' then
regdata(18 downto 16) := std_logic_vector(to_unsigned(log2(ddrbits/16),3));
end if;
regdata(15 downto 12) := beid;
-- If we are using AMBA-compliant data muxing, nothing needs to be done to
-- the hrdata vector. Otherwise, we need to duplicate 32-bit lanes
if regarea/=0 and ar.req.hio='1' and ar.req.startaddr(5)='1' then
so.hrdata := ahbdrivedata(regdata);
elsif CORE_ACDM /= 0 then
so.hrdata := ahbdrivedata(rbrdata);
else
so.hrdata := ahbselectdata(ahbdrivedata(rbrdata),ar.haddr(4 downto 2),ar.hsize);
end if;
if rst='0' then
av.s := asnormal;
av.block_read := "00";
av.start_tog := '0';
av.so_hready := '1';
so.hready := '1';
so.hresp := HRESP_OKAY;
end if;
if l2blen-l2ddrw < 4 then
av.rctr_lin(3 downto l2blen-l2ddrw) := (others => '0');
end if;
nar <= av;
request <= ar.req;
start_tog <= ar.start_tog;
ahbso <= so;
wbwrite <= wbw;
wbwritebig <= wbwb;
wbwaddr <= wbwa;
wbwdata <= wbwd;
rbraddr <= rbra;
end process;
ahbregs : process(clk_ahb)
begin
if rising_edge(clk_ahb) then
ar <= nar;
end if;
end process;
end;
| gpl-2.0 | 8663a1a8d71027224dca481647fecd9f | 0.541925 | 3.516649 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/Zynq_Book/hls/tut3A/matrix_mult_prj/solution5/syn/vhdl/matrix_mult.vhd | 1 | 227,330 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity matrix_mult is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
a_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
a_ce0 : OUT STD_LOGIC;
a_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
a_address1 : OUT STD_LOGIC_VECTOR (4 downto 0);
a_ce1 : OUT STD_LOGIC;
a_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
b_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
b_ce0 : OUT STD_LOGIC;
b_q0 : IN STD_LOGIC_VECTOR (7 downto 0);
b_address1 : OUT STD_LOGIC_VECTOR (4 downto 0);
b_ce1 : OUT STD_LOGIC;
b_q1 : IN STD_LOGIC_VECTOR (7 downto 0);
prod_address0 : OUT STD_LOGIC_VECTOR (4 downto 0);
prod_ce0 : OUT STD_LOGIC;
prod_we0 : OUT STD_LOGIC;
prod_d0 : OUT STD_LOGIC_VECTOR (15 downto 0);
prod_address1 : OUT STD_LOGIC_VECTOR (4 downto 0);
prod_ce1 : OUT STD_LOGIC;
prod_we1 : OUT STD_LOGIC;
prod_d1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of matrix_mult is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"matrix_mult,hls_ip_2017_2,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=5.000000,HLS_INPUT_ARCH=pipeline,HLS_SYN_CLOCK=5.415000,HLS_SYN_LAT=27,HLS_SYN_TPT=13,HLS_SYN_MEM=0,HLS_SYN_DSP=75,HLS_SYN_FF=9729,HLS_SYN_LUT=5027}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_pp0_stage0 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
constant ap_ST_fsm_pp0_stage1 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000010";
constant ap_ST_fsm_pp0_stage2 : STD_LOGIC_VECTOR (12 downto 0) := "0000000000100";
constant ap_ST_fsm_pp0_stage3 : STD_LOGIC_VECTOR (12 downto 0) := "0000000001000";
constant ap_ST_fsm_pp0_stage4 : STD_LOGIC_VECTOR (12 downto 0) := "0000000010000";
constant ap_ST_fsm_pp0_stage5 : STD_LOGIC_VECTOR (12 downto 0) := "0000000100000";
constant ap_ST_fsm_pp0_stage6 : STD_LOGIC_VECTOR (12 downto 0) := "0000001000000";
constant ap_ST_fsm_pp0_stage7 : STD_LOGIC_VECTOR (12 downto 0) := "0000010000000";
constant ap_ST_fsm_pp0_stage8 : STD_LOGIC_VECTOR (12 downto 0) := "0000100000000";
constant ap_ST_fsm_pp0_stage9 : STD_LOGIC_VECTOR (12 downto 0) := "0001000000000";
constant ap_ST_fsm_pp0_stage10 : STD_LOGIC_VECTOR (12 downto 0) := "0010000000000";
constant ap_ST_fsm_pp0_stage11 : STD_LOGIC_VECTOR (12 downto 0) := "0100000000000";
constant ap_ST_fsm_pp0_stage12 : STD_LOGIC_VECTOR (12 downto 0) := "1000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_boolean_1 : BOOLEAN := true;
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_boolean_0 : BOOLEAN := false;
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_9 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001010";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001111";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001101";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_13 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010011";
constant ap_const_lv32_14 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010100";
constant ap_const_lv32_15 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010101";
constant ap_const_lv32_E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001110";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_18 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (12 downto 0) := "0000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_pp0_stage0 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage0 : signal is "none";
signal ap_enable_reg_pp0_iter0 : STD_LOGIC;
signal ap_enable_reg_pp0_iter1 : STD_LOGIC := '0';
signal ap_enable_reg_pp0_iter2 : STD_LOGIC := '0';
signal ap_idle_pp0 : STD_LOGIC;
signal ap_CS_fsm_pp0_stage12 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage12 : signal is "none";
signal ap_block_state13_pp0_stage12_iter0 : BOOLEAN;
signal ap_block_state26_pp0_stage12_iter1 : BOOLEAN;
signal ap_block_pp0_stage12_flag00011001 : BOOLEAN;
signal reg_764 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_pp0_stage1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage1 : signal is "none";
signal ap_block_state2_pp0_stage1_iter0 : BOOLEAN;
signal ap_block_state15_pp0_stage1_iter1 : BOOLEAN;
signal ap_block_state28_pp0_stage1_iter2 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage2 : signal is "none";
signal ap_block_state3_pp0_stage2_iter0 : BOOLEAN;
signal ap_block_state16_pp0_stage2_iter1 : BOOLEAN;
signal ap_block_pp0_stage2_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage4 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage4 : signal is "none";
signal ap_block_state5_pp0_stage4_iter0 : BOOLEAN;
signal ap_block_state18_pp0_stage4_iter1 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage9 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage9 : signal is "none";
signal ap_block_state10_pp0_stage9_iter0 : BOOLEAN;
signal ap_block_state23_pp0_stage9_iter1 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011001 : BOOLEAN;
signal reg_769 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_pp0_stage3 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage3 : signal is "none";
signal ap_block_state4_pp0_stage3_iter0 : BOOLEAN;
signal ap_block_state17_pp0_stage3_iter1 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage8 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage8 : signal is "none";
signal ap_block_state9_pp0_stage8_iter0 : BOOLEAN;
signal ap_block_state22_pp0_stage8_iter1 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage11 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage11 : signal is "none";
signal ap_block_state12_pp0_stage11_iter0 : BOOLEAN;
signal ap_block_state25_pp0_stage11_iter1 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011001 : BOOLEAN;
signal reg_774 : STD_LOGIC_VECTOR (7 downto 0);
signal reg_779 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_pp0_stage5 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage5 : signal is "none";
signal ap_block_state6_pp0_stage5_iter0 : BOOLEAN;
signal ap_block_state19_pp0_stage5_iter1 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011001 : BOOLEAN;
signal reg_784 : STD_LOGIC_VECTOR (7 downto 0);
signal reg_788 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_CS_fsm_pp0_stage7 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage7 : signal is "none";
signal ap_block_state8_pp0_stage7_iter0 : BOOLEAN;
signal ap_block_state21_pp0_stage7_iter1 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011001 : BOOLEAN;
signal ap_CS_fsm_pp0_stage10 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage10 : signal is "none";
signal ap_block_state11_pp0_stage10_iter0 : BOOLEAN;
signal ap_block_state24_pp0_stage10_iter1 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011001 : BOOLEAN;
signal reg_792 : STD_LOGIC_VECTOR (7 downto 0);
signal reg_796 : STD_LOGIC_VECTOR (7 downto 0);
signal reg_800 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_block_state1_pp0_stage0_iter0 : BOOLEAN;
signal ap_block_state14_pp0_stage0_iter1 : BOOLEAN;
signal ap_block_state27_pp0_stage0_iter2 : BOOLEAN;
signal ap_block_pp0_stage0_flag00011001 : BOOLEAN;
signal tmp_0_0_3_fu_805_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_3_reg_1832 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_3_fu_809_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_3_reg_1841 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_3_fu_819_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_3_reg_1850 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_3_fu_829_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_3_reg_1859 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_3_fu_845_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_3_reg_1888 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_3_fu_854_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_3_reg_1897 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_3_fu_873_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_3_reg_1926 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_3_fu_887_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_3_reg_1935 : STD_LOGIC_VECTOR (15 downto 0);
signal b_load_15_reg_1964 : STD_LOGIC_VECTOR (7 downto 0);
signal b_load_20_reg_1969 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_313_0_3_fu_913_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_3_reg_1974 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_CS_fsm_pp0_stage6 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_pp0_stage6 : signal is "none";
signal ap_block_state7_pp0_stage6_iter0 : BOOLEAN;
signal ap_block_state20_pp0_stage6_iter1 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011001 : BOOLEAN;
signal grp_fu_813_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_0_3_reg_2003 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_4_fu_922_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_4_reg_2008 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_4_fu_926_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_4_reg_2017 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_823_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_1_3_reg_2026 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_4_fu_930_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_4_reg_2031 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_833_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_0_3_reg_2040 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_4_fu_934_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_4_reg_2045 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_839_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_1_3_reg_2054 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_849_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_2_3_reg_2079 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_4_fu_954_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_4_reg_2084 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_858_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_3_3_reg_2093 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_4_fu_958_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_4_reg_2098 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_863_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_2_3_reg_2107 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_868_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_3_3_reg_2112 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_4_fu_962_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_4_reg_2117 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_3_fu_966_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_3_reg_2126 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp75_fu_990_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp75_reg_2155 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_fu_994_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_reg_2164 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1340_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp2_reg_2173 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_fu_1004_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_reg_2178 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1347_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp5_reg_2187 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_fu_1014_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_reg_2192 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_877_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_4_3_reg_2201 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_4_fu_1024_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_4_reg_2206 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1354_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp17_reg_2215 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1361_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp20_reg_2220 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_882_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_4_3_reg_2225 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_891_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_0_3_reg_2230 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_896_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_1_3_reg_2235 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_4_fu_1028_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_4_reg_2240 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_2_fu_1036_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_2_reg_2269 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_2_fu_1040_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_2_reg_2278 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1368_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp8_reg_2287 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_fu_1044_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_reg_2292 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1374_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp11_reg_2301 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_fu_1052_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_reg_2306 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_s_fu_1060_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_s_reg_2315 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1380_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp23_reg_2324 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1386_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp26_reg_2329 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1392_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp32_reg_2334 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1398_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp35_reg_2339 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_901_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_2_3_reg_2344 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_905_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_3_3_reg_2349 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_909_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_4_3_reg_2354 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_917_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_0_3_reg_2359 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_2_fu_1074_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_2_reg_2384 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1404_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp14_reg_2393 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_2_fu_1078_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_2_reg_2398 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1410_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp29_reg_2407 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_fu_1094_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_reg_2412 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1416_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp38_reg_2421 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1421_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp41_reg_2426 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1426_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp44_reg_2431 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1432_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp47_reg_2436 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_938_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_1_3_reg_2441 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_942_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_2_3_reg_2446 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_946_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_3_3_reg_2451 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_950_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_4_3_reg_2456 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_4_fu_1103_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_4_reg_2461 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_1_fu_1107_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_0_0_1_reg_2490 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_1_fu_1111_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_0_1_reg_2499 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1438_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp1_reg_2508 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_1_fu_1115_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_1_1_reg_2513 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_1_fu_1119_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_1_reg_2522 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_2_fu_1123_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_2_2_reg_2531 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1445_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp50_reg_2540 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1450_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp53_reg_2545 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1455_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp56_reg_2550 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1460_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp59_reg_2555 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_970_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_0_3_reg_2560 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_975_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_1_3_reg_2565 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_980_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_2_3_reg_2570 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_985_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_3_3_reg_2575 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_998_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_reg_2590 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1008_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_1_reg_2595 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1465_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp4_reg_2600 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1018_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_2_reg_2605 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_1_fu_1143_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_1_reg_2610 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_2_fu_1147_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_3_2_reg_2619 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_1_fu_1151_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_1_reg_2628 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_1_fu_1155_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_111_0_1_reg_2637 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1471_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp16_reg_2646 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_5_fu_1159_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_5_reg_2651 : STD_LOGIC_VECTOR (15 downto 0);
signal a_load_17_reg_2660 : STD_LOGIC_VECTOR (7 downto 0);
signal a_load_21_reg_2665 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1477_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp62_reg_2670 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1483_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp65_reg_2675 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1489_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp68_reg_2680 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1495_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp71_reg_2685 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1032_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_4_3_reg_2690 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1501_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_reg_2695 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1508_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp3_reg_2700 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1515_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp6_reg_2705 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1522_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp7_reg_2710 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1047_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_3_reg_2715 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1055_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_0_4_reg_2720 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_2_fu_1183_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_1_0_4_2_reg_2725 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1064_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_reg_2734 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1069_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_1_reg_2739 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1528_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp19_reg_2744 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_1_fu_1187_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_1_reg_2749 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_fu_1195_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_reg_2758 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1533_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp74_reg_2767 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_0_0_4_fu_1214_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of tmp_3_0_0_4_fu_1214_p2 : signal is "no";
signal tmp_3_0_0_4_reg_2772 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_0_1_4_fu_1218_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_0_1_4_fu_1218_p2 : signal is "no";
signal tmp_3_0_1_4_reg_2777 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_0_2_4_fu_1222_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_0_2_4_fu_1222_p2 : signal is "no";
signal tmp_3_0_2_4_reg_2782 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1538_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp9_reg_2787 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1544_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp10_reg_2792 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1550_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp12_reg_2797 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1556_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp15_reg_2802 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1562_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp18_reg_2807 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1082_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_2_reg_2812 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1568_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp22_reg_2817 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1086_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_3_reg_2822 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1090_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_1_4_reg_2827 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1098_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_reg_2832 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_2_fu_1226_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_212_0_2_reg_2837 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_0_3_4_fu_1238_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_0_3_4_fu_1238_p2 : signal is "no";
signal tmp_3_0_3_4_reg_2846 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1573_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp13_reg_2851 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_1_0_4_fu_1242_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_1_0_4_fu_1242_p2 : signal is "no";
signal tmp_3_1_0_4_reg_2856 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_1_1_4_fu_1246_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_1_1_4_fu_1246_p2 : signal is "no";
signal tmp_3_1_1_4_reg_2861 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1579_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp21_reg_2866 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1584_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp24_reg_2871 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1589_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp25_reg_2876 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1594_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp27_reg_2881 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1599_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp30_reg_2886 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1127_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_1_reg_2891 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1131_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_2_reg_2896 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1135_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_3_reg_2901 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1139_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_2_4_reg_2906 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_1_fu_1250_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_1_reg_2911 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_0_4_4_fu_1254_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_0_4_4_fu_1254_p2 : signal is "no";
signal tmp_3_0_4_4_reg_2920 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_1_2_4_fu_1258_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_1_2_4_fu_1258_p2 : signal is "no";
signal tmp_3_1_2_4_reg_2925 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_1_3_4_fu_1262_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_1_3_4_fu_1262_p2 : signal is "no";
signal tmp_3_1_3_4_reg_2930 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1605_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp28_reg_2935 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1610_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp31_reg_2940 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1616_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp33_reg_2945 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1621_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp36_reg_2950 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1626_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp39_reg_2955 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1631_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp42_reg_2960 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1163_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_reg_2965 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1168_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_1_reg_2970 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1173_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_2_reg_2975 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1178_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_3_reg_2980 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_1_fu_1266_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_1_reg_2985 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_1_4_4_fu_1269_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_1_4_4_fu_1269_p2 : signal is "no";
signal tmp_3_1_4_4_reg_2994 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_2_0_4_fu_1273_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_2_0_4_fu_1273_p2 : signal is "no";
signal tmp_3_2_0_4_reg_2999 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1636_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp34_reg_3004 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1641_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp37_reg_3009 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_2_fu_1277_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_313_0_2_reg_3014 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1646_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp45_reg_3023 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1652_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp48_reg_3028 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1658_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp51_reg_3033 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1664_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp54_reg_3038 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1191_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_3_4_reg_3043 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1199_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_reg_3048 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1204_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_1_reg_3053 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1209_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_2_reg_3058 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_2_1_4_fu_1280_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_2_1_4_fu_1280_p2 : signal is "no";
signal tmp_3_2_1_4_reg_3063 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_2_2_4_fu_1284_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_2_2_4_fu_1284_p2 : signal is "no";
signal tmp_3_2_2_4_reg_3068 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1670_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp40_reg_3073 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1675_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp43_reg_3078 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1680_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp57_reg_3083 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_0_2_fu_1288_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1685_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp60_reg_3097 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1691_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp63_reg_3102 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1697_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp66_reg_3107 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1230_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_3_reg_3112 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1234_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_2_4_4_reg_3117 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_2_3_4_fu_1292_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_2_3_4_fu_1292_p2 : signal is "no";
signal tmp_3_2_3_4_reg_3122 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_2_4_4_fu_1296_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_2_4_4_fu_1296_p2 : signal is "no";
signal tmp_3_2_4_4_reg_3127 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1703_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp46_reg_3132 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1709_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp49_reg_3137 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1715_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp52_reg_3142 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1721_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp55_reg_3147 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1727_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp69_reg_3152 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1732_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp72_reg_3157 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_3_0_4_fu_1300_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_3_0_4_fu_1300_p2 : signal is "no";
signal tmp_3_3_0_4_reg_3162 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_3_1_4_fu_1304_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_3_1_4_fu_1304_p2 : signal is "no";
signal tmp_3_3_1_4_reg_3167 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_3_2_4_fu_1308_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_3_2_4_fu_1308_p2 : signal is "no";
signal tmp_3_3_2_4_reg_3172 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_3_3_4_fu_1312_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_3_3_4_fu_1312_p2 : signal is "no";
signal tmp_3_3_3_4_reg_3177 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1737_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp58_reg_3182 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1742_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp61_reg_3187 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1748_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp64_reg_3192 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1754_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp67_reg_3197 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1760_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp70_reg_3202 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_1766_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp73_reg_3207 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_3_4_4_fu_1316_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_3_4_4_fu_1316_p2 : signal is "no";
signal tmp_3_3_4_4_reg_3212 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_4_0_4_fu_1320_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_4_0_4_fu_1320_p2 : signal is "no";
signal tmp_3_4_0_4_reg_3217 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_4_1_4_fu_1324_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_4_1_4_fu_1324_p2 : signal is "no";
signal tmp_3_4_1_4_reg_3222 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_4_2_4_fu_1328_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_4_2_4_fu_1328_p2 : signal is "no";
signal tmp_3_4_2_4_reg_3227 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_4_3_4_fu_1332_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_4_3_4_fu_1332_p2 : signal is "no";
signal tmp_3_4_3_4_reg_3232 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_4_4_4_fu_1336_p2 : STD_LOGIC_VECTOR (15 downto 0);
attribute use_dsp48 of tmp_3_4_4_4_fu_1336_p2 : signal is "no";
signal tmp_3_4_4_4_reg_3237 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_enable_reg_pp0_iter0_reg : STD_LOGIC := '0';
signal ap_block_pp0_stage12_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage1_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage0_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage1_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage2_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage3_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage4_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage5_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage6_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage7_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage8_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage9_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage10_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage11_flag00000000 : BOOLEAN;
signal ap_block_pp0_stage12_flag00000000 : BOOLEAN;
signal grp_fu_813_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_813_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_823_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_823_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_833_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_833_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_839_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_839_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_849_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_849_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_858_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_858_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_863_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_863_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_868_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_868_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_877_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_877_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_882_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_882_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_891_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_891_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_896_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_896_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_901_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_901_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_905_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_905_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_909_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_909_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_917_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_938_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_938_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_942_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_942_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_946_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_946_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_950_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_950_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_970_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_970_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_975_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_975_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_980_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_980_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_985_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_985_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_998_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1008_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1018_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1032_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1032_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1047_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1055_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1064_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1064_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1069_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1069_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1082_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1082_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1086_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1086_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1090_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1090_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1098_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1127_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1127_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1131_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1131_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1135_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1135_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1139_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1139_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1163_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1163_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1168_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1168_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1173_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1173_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1178_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1178_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1191_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1191_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1199_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1199_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1204_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1204_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1209_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1209_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1230_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1230_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1234_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1234_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1340_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1340_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1347_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1347_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1354_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1354_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1361_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1361_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1368_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1368_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1374_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1374_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1380_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1380_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1386_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1386_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1392_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1392_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1398_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1398_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1404_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1404_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1410_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1410_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1416_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1416_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1421_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1421_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1426_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1426_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1432_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1445_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1445_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1450_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1450_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1455_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1455_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1460_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1460_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1465_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1471_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1477_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1477_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1483_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1483_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1489_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1489_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1495_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1495_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1501_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1508_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1515_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1522_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1528_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1528_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1533_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1533_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1538_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1544_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1550_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1556_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1556_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1562_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1562_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1568_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1568_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1573_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1579_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1579_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1584_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1584_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1589_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1589_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1594_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1594_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1599_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1605_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1605_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1610_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1616_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1616_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1621_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1621_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1626_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1626_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1631_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1631_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1636_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1636_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1641_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1641_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1646_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1646_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1652_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1652_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1658_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1658_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1664_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1664_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1670_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1670_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1675_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1675_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1680_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1680_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1685_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1685_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1691_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1691_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1697_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1697_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1703_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1703_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1709_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1709_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1715_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1715_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1721_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1721_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1727_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1727_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1732_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1732_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1737_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1737_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1742_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1742_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1748_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1748_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1754_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1754_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1760_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1760_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1766_p0 : STD_LOGIC_VECTOR (7 downto 0);
signal grp_fu_1766_p1 : STD_LOGIC_VECTOR (7 downto 0);
signal ap_NS_fsm : STD_LOGIC_VECTOR (12 downto 0);
signal ap_block_pp0_stage0_flag00011011 : BOOLEAN;
signal ap_idle_pp0_1to2 : STD_LOGIC;
signal ap_idle_pp0_0to1 : STD_LOGIC;
signal ap_reset_idle_pp0 : STD_LOGIC;
signal ap_block_pp0_stage2_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage3_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage4_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage5_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage6_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage7_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage8_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage9_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage10_flag00011011 : BOOLEAN;
signal ap_block_pp0_stage11_flag00011011 : BOOLEAN;
signal ap_enable_pp0 : STD_LOGIC;
component matrix_mult_mul_8bkb IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component matrix_mult_mac_mcud IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component matrix_mult_mac_mdEe IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (7 downto 0);
din1 : IN STD_LOGIC_VECTOR (7 downto 0);
din2 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
matrix_mult_mul_8bkb_U0 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_813_p0,
din1 => grp_fu_813_p1,
ce => ap_const_logic_1,
dout => grp_fu_813_p2);
matrix_mult_mul_8bkb_U1 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_823_p0,
din1 => grp_fu_823_p1,
ce => ap_const_logic_1,
dout => grp_fu_823_p2);
matrix_mult_mul_8bkb_U2 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_833_p0,
din1 => grp_fu_833_p1,
ce => ap_const_logic_1,
dout => grp_fu_833_p2);
matrix_mult_mul_8bkb_U3 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_839_p0,
din1 => grp_fu_839_p1,
ce => ap_const_logic_1,
dout => grp_fu_839_p2);
matrix_mult_mul_8bkb_U4 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_849_p0,
din1 => grp_fu_849_p1,
ce => ap_const_logic_1,
dout => grp_fu_849_p2);
matrix_mult_mul_8bkb_U5 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_858_p0,
din1 => grp_fu_858_p1,
ce => ap_const_logic_1,
dout => grp_fu_858_p2);
matrix_mult_mul_8bkb_U6 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_863_p0,
din1 => grp_fu_863_p1,
ce => ap_const_logic_1,
dout => grp_fu_863_p2);
matrix_mult_mul_8bkb_U7 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_868_p0,
din1 => grp_fu_868_p1,
ce => ap_const_logic_1,
dout => grp_fu_868_p2);
matrix_mult_mul_8bkb_U8 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_877_p0,
din1 => grp_fu_877_p1,
ce => ap_const_logic_1,
dout => grp_fu_877_p2);
matrix_mult_mul_8bkb_U9 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_882_p0,
din1 => grp_fu_882_p1,
ce => ap_const_logic_1,
dout => grp_fu_882_p2);
matrix_mult_mul_8bkb_U10 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_891_p0,
din1 => grp_fu_891_p1,
ce => ap_const_logic_1,
dout => grp_fu_891_p2);
matrix_mult_mul_8bkb_U11 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_896_p0,
din1 => grp_fu_896_p1,
ce => ap_const_logic_1,
dout => grp_fu_896_p2);
matrix_mult_mul_8bkb_U12 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_901_p0,
din1 => grp_fu_901_p1,
ce => ap_const_logic_1,
dout => grp_fu_901_p2);
matrix_mult_mul_8bkb_U13 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_905_p0,
din1 => grp_fu_905_p1,
ce => ap_const_logic_1,
dout => grp_fu_905_p2);
matrix_mult_mul_8bkb_U14 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_909_p0,
din1 => grp_fu_909_p1,
ce => ap_const_logic_1,
dout => grp_fu_909_p2);
matrix_mult_mul_8bkb_U15 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_917_p0,
din1 => reg_779,
ce => ap_const_logic_1,
dout => grp_fu_917_p2);
matrix_mult_mul_8bkb_U16 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_938_p0,
din1 => grp_fu_938_p1,
ce => ap_const_logic_1,
dout => grp_fu_938_p2);
matrix_mult_mul_8bkb_U17 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_942_p0,
din1 => grp_fu_942_p1,
ce => ap_const_logic_1,
dout => grp_fu_942_p2);
matrix_mult_mul_8bkb_U18 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_946_p0,
din1 => grp_fu_946_p1,
ce => ap_const_logic_1,
dout => grp_fu_946_p2);
matrix_mult_mul_8bkb_U19 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_950_p0,
din1 => grp_fu_950_p1,
ce => ap_const_logic_1,
dout => grp_fu_950_p2);
matrix_mult_mul_8bkb_U20 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_970_p0,
din1 => grp_fu_970_p1,
ce => ap_const_logic_1,
dout => grp_fu_970_p2);
matrix_mult_mul_8bkb_U21 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_975_p0,
din1 => grp_fu_975_p1,
ce => ap_const_logic_1,
dout => grp_fu_975_p2);
matrix_mult_mul_8bkb_U22 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_980_p0,
din1 => grp_fu_980_p1,
ce => ap_const_logic_1,
dout => grp_fu_980_p2);
matrix_mult_mul_8bkb_U23 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_985_p0,
din1 => grp_fu_985_p1,
ce => ap_const_logic_1,
dout => grp_fu_985_p2);
matrix_mult_mul_8bkb_U24 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_769,
din1 => grp_fu_998_p1,
ce => ap_const_logic_1,
dout => grp_fu_998_p2);
matrix_mult_mul_8bkb_U25 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_774,
din1 => grp_fu_1008_p1,
ce => ap_const_logic_1,
dout => grp_fu_1008_p2);
matrix_mult_mul_8bkb_U26 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_792,
din1 => grp_fu_1018_p1,
ce => ap_const_logic_1,
dout => grp_fu_1018_p2);
matrix_mult_mul_8bkb_U27 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1032_p0,
din1 => grp_fu_1032_p1,
ce => ap_const_logic_1,
dout => grp_fu_1032_p2);
matrix_mult_mul_8bkb_U28 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_load_15_reg_1964,
din1 => grp_fu_1047_p1,
ce => ap_const_logic_1,
dout => grp_fu_1047_p2);
matrix_mult_mul_8bkb_U29 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_load_20_reg_1969,
din1 => grp_fu_1055_p1,
ce => ap_const_logic_1,
dout => grp_fu_1055_p2);
matrix_mult_mul_8bkb_U30 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1064_p0,
din1 => grp_fu_1064_p1,
ce => ap_const_logic_1,
dout => grp_fu_1064_p2);
matrix_mult_mul_8bkb_U31 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1069_p0,
din1 => grp_fu_1069_p1,
ce => ap_const_logic_1,
dout => grp_fu_1069_p2);
matrix_mult_mul_8bkb_U32 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1082_p0,
din1 => grp_fu_1082_p1,
ce => ap_const_logic_1,
dout => grp_fu_1082_p2);
matrix_mult_mul_8bkb_U33 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1086_p0,
din1 => grp_fu_1086_p1,
ce => ap_const_logic_1,
dout => grp_fu_1086_p2);
matrix_mult_mul_8bkb_U34 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1090_p0,
din1 => grp_fu_1090_p1,
ce => ap_const_logic_1,
dout => grp_fu_1090_p2);
matrix_mult_mul_8bkb_U35 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1098_p0,
din1 => reg_796,
ce => ap_const_logic_1,
dout => grp_fu_1098_p2);
matrix_mult_mul_8bkb_U36 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1127_p0,
din1 => grp_fu_1127_p1,
ce => ap_const_logic_1,
dout => grp_fu_1127_p2);
matrix_mult_mul_8bkb_U37 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1131_p0,
din1 => grp_fu_1131_p1,
ce => ap_const_logic_1,
dout => grp_fu_1131_p2);
matrix_mult_mul_8bkb_U38 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1135_p0,
din1 => grp_fu_1135_p1,
ce => ap_const_logic_1,
dout => grp_fu_1135_p2);
matrix_mult_mul_8bkb_U39 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1139_p0,
din1 => grp_fu_1139_p1,
ce => ap_const_logic_1,
dout => grp_fu_1139_p2);
matrix_mult_mul_8bkb_U40 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1163_p0,
din1 => grp_fu_1163_p1,
ce => ap_const_logic_1,
dout => grp_fu_1163_p2);
matrix_mult_mul_8bkb_U41 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1168_p0,
din1 => grp_fu_1168_p1,
ce => ap_const_logic_1,
dout => grp_fu_1168_p2);
matrix_mult_mul_8bkb_U42 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1173_p0,
din1 => grp_fu_1173_p1,
ce => ap_const_logic_1,
dout => grp_fu_1173_p2);
matrix_mult_mul_8bkb_U43 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1178_p0,
din1 => grp_fu_1178_p1,
ce => ap_const_logic_1,
dout => grp_fu_1178_p2);
matrix_mult_mul_8bkb_U44 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1191_p0,
din1 => grp_fu_1191_p1,
ce => ap_const_logic_1,
dout => grp_fu_1191_p2);
matrix_mult_mul_8bkb_U45 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1199_p0,
din1 => grp_fu_1199_p1,
ce => ap_const_logic_1,
dout => grp_fu_1199_p2);
matrix_mult_mul_8bkb_U46 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1204_p0,
din1 => grp_fu_1204_p1,
ce => ap_const_logic_1,
dout => grp_fu_1204_p2);
matrix_mult_mul_8bkb_U47 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1209_p0,
din1 => grp_fu_1209_p1,
ce => ap_const_logic_1,
dout => grp_fu_1209_p2);
matrix_mult_mul_8bkb_U48 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1230_p0,
din1 => grp_fu_1230_p1,
ce => ap_const_logic_1,
dout => grp_fu_1230_p2);
matrix_mult_mul_8bkb_U49 : component matrix_mult_mul_8bkb
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 8,
din1_WIDTH => 8,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1234_p0,
din1 => grp_fu_1234_p1,
ce => ap_const_logic_1,
dout => grp_fu_1234_p2);
matrix_mult_mac_mcud_U50 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1340_p0,
din1 => grp_fu_1340_p1,
din2 => tmp_2_0_0_3_reg_2003,
ce => ap_const_logic_1,
dout => grp_fu_1340_p3);
matrix_mult_mac_mcud_U51 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1347_p0,
din1 => grp_fu_1347_p1,
din2 => tmp_2_0_1_3_reg_2026,
ce => ap_const_logic_1,
dout => grp_fu_1347_p3);
matrix_mult_mac_mcud_U52 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1354_p0,
din1 => grp_fu_1354_p1,
din2 => tmp_2_1_0_3_reg_2040,
ce => ap_const_logic_1,
dout => grp_fu_1354_p3);
matrix_mult_mac_mcud_U53 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1361_p0,
din1 => grp_fu_1361_p1,
din2 => tmp_2_1_1_3_reg_2054,
ce => ap_const_logic_1,
dout => grp_fu_1361_p3);
matrix_mult_mac_mcud_U54 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1368_p0,
din1 => grp_fu_1368_p1,
din2 => tmp_2_0_2_3_reg_2079,
ce => ap_const_logic_1,
dout => grp_fu_1368_p3);
matrix_mult_mac_mcud_U55 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1374_p0,
din1 => grp_fu_1374_p1,
din2 => tmp_2_0_3_3_reg_2093,
ce => ap_const_logic_1,
dout => grp_fu_1374_p3);
matrix_mult_mac_mcud_U56 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1380_p0,
din1 => grp_fu_1380_p1,
din2 => tmp_2_1_2_3_reg_2107,
ce => ap_const_logic_1,
dout => grp_fu_1380_p3);
matrix_mult_mac_mcud_U57 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1386_p0,
din1 => grp_fu_1386_p1,
din2 => tmp_2_1_3_3_reg_2112,
ce => ap_const_logic_1,
dout => grp_fu_1386_p3);
matrix_mult_mac_mcud_U58 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1392_p0,
din1 => grp_fu_1392_p1,
din2 => tmp_2_2_0_3_reg_2230,
ce => ap_const_logic_1,
dout => grp_fu_1392_p3);
matrix_mult_mac_mcud_U59 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1398_p0,
din1 => grp_fu_1398_p1,
din2 => tmp_2_2_1_3_reg_2235,
ce => ap_const_logic_1,
dout => grp_fu_1398_p3);
matrix_mult_mac_mcud_U60 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1404_p0,
din1 => grp_fu_1404_p1,
din2 => tmp_2_0_4_3_reg_2201,
ce => ap_const_logic_1,
dout => grp_fu_1404_p3);
matrix_mult_mac_mcud_U61 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1410_p0,
din1 => grp_fu_1410_p1,
din2 => tmp_2_1_4_3_reg_2225,
ce => ap_const_logic_1,
dout => grp_fu_1410_p3);
matrix_mult_mac_mcud_U62 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1416_p0,
din1 => grp_fu_1416_p1,
din2 => tmp_2_2_2_3_reg_2344,
ce => ap_const_logic_1,
dout => grp_fu_1416_p3);
matrix_mult_mac_mcud_U63 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1421_p0,
din1 => grp_fu_1421_p1,
din2 => tmp_2_2_3_3_reg_2349,
ce => ap_const_logic_1,
dout => grp_fu_1421_p3);
matrix_mult_mac_mcud_U64 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1426_p0,
din1 => grp_fu_1426_p1,
din2 => tmp_2_2_4_3_reg_2354,
ce => ap_const_logic_1,
dout => grp_fu_1426_p3);
matrix_mult_mac_mcud_U65 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1432_p0,
din1 => reg_788,
din2 => tmp_2_3_0_3_reg_2359,
ce => ap_const_logic_1,
dout => grp_fu_1432_p3);
matrix_mult_mac_mdEe_U66 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q0,
din1 => a_q0,
din2 => tmp2_reg_2173,
ce => ap_const_logic_1,
dout => grp_fu_1438_p3);
matrix_mult_mac_mcud_U67 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1445_p0,
din1 => grp_fu_1445_p1,
din2 => tmp_2_3_1_3_reg_2441,
ce => ap_const_logic_1,
dout => grp_fu_1445_p3);
matrix_mult_mac_mcud_U68 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1450_p0,
din1 => grp_fu_1450_p1,
din2 => tmp_2_3_2_3_reg_2446,
ce => ap_const_logic_1,
dout => grp_fu_1450_p3);
matrix_mult_mac_mcud_U69 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1455_p0,
din1 => grp_fu_1455_p1,
din2 => tmp_2_3_3_3_reg_2451,
ce => ap_const_logic_1,
dout => grp_fu_1455_p3);
matrix_mult_mac_mcud_U70 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1460_p0,
din1 => grp_fu_1460_p1,
din2 => tmp_2_3_4_3_reg_2456,
ce => ap_const_logic_1,
dout => grp_fu_1460_p3);
matrix_mult_mac_mdEe_U71 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q0,
din1 => grp_fu_1465_p1,
din2 => tmp5_reg_2187,
ce => ap_const_logic_1,
dout => grp_fu_1465_p3);
matrix_mult_mac_mdEe_U72 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1471_p0,
din1 => a_q0,
din2 => tmp17_reg_2215,
ce => ap_const_logic_1,
dout => grp_fu_1471_p3);
matrix_mult_mac_mcud_U73 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1477_p0,
din1 => grp_fu_1477_p1,
din2 => tmp_2_4_0_3_reg_2560,
ce => ap_const_logic_1,
dout => grp_fu_1477_p3);
matrix_mult_mac_mcud_U74 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1483_p0,
din1 => grp_fu_1483_p1,
din2 => tmp_2_4_1_3_reg_2565,
ce => ap_const_logic_1,
dout => grp_fu_1483_p3);
matrix_mult_mac_mcud_U75 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1489_p0,
din1 => grp_fu_1489_p1,
din2 => tmp_2_4_2_3_reg_2570,
ce => ap_const_logic_1,
dout => grp_fu_1489_p3);
matrix_mult_mac_mcud_U76 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1495_p0,
din1 => grp_fu_1495_p1,
din2 => tmp_2_4_3_3_reg_2575,
ce => ap_const_logic_1,
dout => grp_fu_1495_p3);
matrix_mult_mac_mcud_U77 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_769,
din1 => grp_fu_1501_p1,
din2 => tmp_2_reg_2590,
ce => ap_const_logic_1,
dout => grp_fu_1501_p3);
matrix_mult_mac_mcud_U78 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_774,
din1 => grp_fu_1508_p1,
din2 => tmp_2_0_1_reg_2595,
ce => ap_const_logic_1,
dout => grp_fu_1508_p3);
matrix_mult_mac_mcud_U79 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_792,
din1 => grp_fu_1515_p1,
din2 => tmp_2_0_2_reg_2605,
ce => ap_const_logic_1,
dout => grp_fu_1515_p3);
matrix_mult_mac_mdEe_U80 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q0,
din1 => grp_fu_1522_p1,
din2 => tmp8_reg_2287,
ce => ap_const_logic_1,
dout => grp_fu_1522_p3);
matrix_mult_mac_mdEe_U81 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1528_p0,
din1 => grp_fu_1528_p1,
din2 => tmp20_reg_2220,
ce => ap_const_logic_1,
dout => grp_fu_1528_p3);
matrix_mult_mac_mcud_U82 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1533_p0,
din1 => grp_fu_1533_p1,
din2 => tmp_2_4_4_3_reg_2690,
ce => ap_const_logic_1,
dout => grp_fu_1533_p3);
matrix_mult_mac_mcud_U83 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => reg_769,
din1 => grp_fu_1538_p1,
din2 => tmp_2_0_3_reg_2715,
ce => ap_const_logic_1,
dout => grp_fu_1538_p3);
matrix_mult_mac_mdEe_U84 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q0,
din1 => grp_fu_1544_p1,
din2 => tmp11_reg_2301,
ce => ap_const_logic_1,
dout => grp_fu_1544_p3);
matrix_mult_mac_mcud_U85 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q1,
din1 => grp_fu_1550_p1,
din2 => tmp_2_0_4_reg_2720,
ce => ap_const_logic_1,
dout => grp_fu_1550_p3);
matrix_mult_mac_mcud_U86 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1556_p0,
din1 => grp_fu_1556_p1,
din2 => tmp_2_1_reg_2734,
ce => ap_const_logic_1,
dout => grp_fu_1556_p3);
matrix_mult_mac_mcud_U87 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1562_p0,
din1 => grp_fu_1562_p1,
din2 => tmp_2_1_1_reg_2739,
ce => ap_const_logic_1,
dout => grp_fu_1562_p3);
matrix_mult_mac_mdEe_U88 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1568_p0,
din1 => grp_fu_1568_p1,
din2 => tmp23_reg_2324,
ce => ap_const_logic_1,
dout => grp_fu_1568_p3);
matrix_mult_mac_mdEe_U89 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => b_q0,
din1 => grp_fu_1573_p1,
din2 => tmp14_reg_2393,
ce => ap_const_logic_1,
dout => grp_fu_1573_p3);
matrix_mult_mac_mcud_U90 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1579_p0,
din1 => grp_fu_1579_p1,
din2 => tmp_2_1_2_reg_2812,
ce => ap_const_logic_1,
dout => grp_fu_1579_p3);
matrix_mult_mac_mcud_U91 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1584_p0,
din1 => grp_fu_1584_p1,
din2 => tmp_2_1_3_reg_2822,
ce => ap_const_logic_1,
dout => grp_fu_1584_p3);
matrix_mult_mac_mdEe_U92 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1589_p0,
din1 => grp_fu_1589_p1,
din2 => tmp26_reg_2329,
ce => ap_const_logic_1,
dout => grp_fu_1589_p3);
matrix_mult_mac_mcud_U93 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1594_p0,
din1 => grp_fu_1594_p1,
din2 => tmp_2_1_4_reg_2827,
ce => ap_const_logic_1,
dout => grp_fu_1594_p3);
matrix_mult_mac_mcud_U94 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1599_p0,
din1 => reg_788,
din2 => tmp_2_2_reg_2832,
ce => ap_const_logic_1,
dout => grp_fu_1599_p3);
matrix_mult_mac_mdEe_U95 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1605_p0,
din1 => grp_fu_1605_p1,
din2 => tmp29_reg_2407,
ce => ap_const_logic_1,
dout => grp_fu_1605_p3);
matrix_mult_mac_mdEe_U96 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1610_p0,
din1 => reg_784,
din2 => tmp32_reg_2334,
ce => ap_const_logic_1,
dout => grp_fu_1610_p3);
matrix_mult_mac_mcud_U97 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1616_p0,
din1 => grp_fu_1616_p1,
din2 => tmp_2_2_1_reg_2891,
ce => ap_const_logic_1,
dout => grp_fu_1616_p3);
matrix_mult_mac_mcud_U98 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1621_p0,
din1 => grp_fu_1621_p1,
din2 => tmp_2_2_2_reg_2896,
ce => ap_const_logic_1,
dout => grp_fu_1621_p3);
matrix_mult_mac_mcud_U99 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1626_p0,
din1 => grp_fu_1626_p1,
din2 => tmp_2_2_3_reg_2901,
ce => ap_const_logic_1,
dout => grp_fu_1626_p3);
matrix_mult_mac_mcud_U100 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1631_p0,
din1 => grp_fu_1631_p1,
din2 => tmp_2_2_4_reg_2906,
ce => ap_const_logic_1,
dout => grp_fu_1631_p3);
matrix_mult_mac_mdEe_U101 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1636_p0,
din1 => grp_fu_1636_p1,
din2 => tmp35_reg_2339,
ce => ap_const_logic_1,
dout => grp_fu_1636_p3);
matrix_mult_mac_mdEe_U102 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1641_p0,
din1 => grp_fu_1641_p1,
din2 => tmp38_reg_2421,
ce => ap_const_logic_1,
dout => grp_fu_1641_p3);
matrix_mult_mac_mcud_U103 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1646_p0,
din1 => grp_fu_1646_p1,
din2 => tmp_2_3_reg_2965,
ce => ap_const_logic_1,
dout => grp_fu_1646_p3);
matrix_mult_mac_mcud_U104 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1652_p0,
din1 => grp_fu_1652_p1,
din2 => tmp_2_3_1_reg_2970,
ce => ap_const_logic_1,
dout => grp_fu_1652_p3);
matrix_mult_mac_mcud_U105 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1658_p0,
din1 => grp_fu_1658_p1,
din2 => tmp_2_3_2_reg_2975,
ce => ap_const_logic_1,
dout => grp_fu_1658_p3);
matrix_mult_mac_mcud_U106 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1664_p0,
din1 => grp_fu_1664_p1,
din2 => tmp_2_3_3_reg_2980,
ce => ap_const_logic_1,
dout => grp_fu_1664_p3);
matrix_mult_mac_mdEe_U107 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1670_p0,
din1 => grp_fu_1670_p1,
din2 => tmp41_reg_2426,
ce => ap_const_logic_1,
dout => grp_fu_1670_p3);
matrix_mult_mac_mdEe_U108 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1675_p0,
din1 => grp_fu_1675_p1,
din2 => tmp44_reg_2431,
ce => ap_const_logic_1,
dout => grp_fu_1675_p3);
matrix_mult_mac_mcud_U109 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1680_p0,
din1 => grp_fu_1680_p1,
din2 => tmp_2_3_4_reg_3043,
ce => ap_const_logic_1,
dout => grp_fu_1680_p3);
matrix_mult_mac_mcud_U110 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1685_p0,
din1 => grp_fu_1685_p1,
din2 => tmp_2_4_reg_3048,
ce => ap_const_logic_1,
dout => grp_fu_1685_p3);
matrix_mult_mac_mcud_U111 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1691_p0,
din1 => grp_fu_1691_p1,
din2 => tmp_2_4_1_reg_3053,
ce => ap_const_logic_1,
dout => grp_fu_1691_p3);
matrix_mult_mac_mcud_U112 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1697_p0,
din1 => grp_fu_1697_p1,
din2 => tmp_2_4_2_reg_3058,
ce => ap_const_logic_1,
dout => grp_fu_1697_p3);
matrix_mult_mac_mdEe_U113 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1703_p0,
din1 => grp_fu_1703_p1,
din2 => tmp47_reg_2436,
ce => ap_const_logic_1,
dout => grp_fu_1703_p3);
matrix_mult_mac_mdEe_U114 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1709_p0,
din1 => grp_fu_1709_p1,
din2 => tmp50_reg_2540,
ce => ap_const_logic_1,
dout => grp_fu_1709_p3);
matrix_mult_mac_mdEe_U115 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1715_p0,
din1 => grp_fu_1715_p1,
din2 => tmp53_reg_2545,
ce => ap_const_logic_1,
dout => grp_fu_1715_p3);
matrix_mult_mac_mdEe_U116 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1721_p0,
din1 => grp_fu_1721_p1,
din2 => tmp56_reg_2550,
ce => ap_const_logic_1,
dout => grp_fu_1721_p3);
matrix_mult_mac_mcud_U117 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1727_p0,
din1 => grp_fu_1727_p1,
din2 => tmp_2_4_3_reg_3112,
ce => ap_const_logic_1,
dout => grp_fu_1727_p3);
matrix_mult_mac_mcud_U118 : component matrix_mult_mac_mcud
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1732_p0,
din1 => grp_fu_1732_p1,
din2 => tmp_2_4_4_reg_3117,
ce => ap_const_logic_1,
dout => grp_fu_1732_p3);
matrix_mult_mac_mdEe_U119 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1737_p0,
din1 => grp_fu_1737_p1,
din2 => tmp59_reg_2555,
ce => ap_const_logic_1,
dout => grp_fu_1737_p3);
matrix_mult_mac_mdEe_U120 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1742_p0,
din1 => grp_fu_1742_p1,
din2 => tmp62_reg_2670,
ce => ap_const_logic_1,
dout => grp_fu_1742_p3);
matrix_mult_mac_mdEe_U121 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1748_p0,
din1 => grp_fu_1748_p1,
din2 => tmp65_reg_2675,
ce => ap_const_logic_1,
dout => grp_fu_1748_p3);
matrix_mult_mac_mdEe_U122 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1754_p0,
din1 => grp_fu_1754_p1,
din2 => tmp68_reg_2680,
ce => ap_const_logic_1,
dout => grp_fu_1754_p3);
matrix_mult_mac_mdEe_U123 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1760_p0,
din1 => grp_fu_1760_p1,
din2 => tmp71_reg_2685,
ce => ap_const_logic_1,
dout => grp_fu_1760_p3);
matrix_mult_mac_mdEe_U124 : component matrix_mult_mac_mdEe
generic map (
ID => 1,
NUM_STAGE => 3,
din0_WIDTH => 8,
din1_WIDTH => 8,
din2_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_1766_p0,
din1 => grp_fu_1766_p1,
din2 => tmp74_reg_2767,
ce => ap_const_logic_1,
dout => grp_fu_1766_p3);
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_enable_reg_pp0_iter0_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter0_reg <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then
ap_enable_reg_pp0_iter0_reg <= ap_start;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter1 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end if;
end if;
end if;
end process;
ap_enable_reg_pp0_iter2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0))) then
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0) and (ap_enable_reg_pp0_iter1 = ap_const_logic_0))) then
ap_enable_reg_pp0_iter2 <= ap_const_logic_0;
end if;
end if;
end if;
end process;
reg_764_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
reg_764 <= a_q1;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)))) then
reg_764 <= a_q0;
end if;
end if;
end process;
reg_769_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
reg_769 <= b_q1;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)))) then
reg_769 <= b_q0;
end if;
end if;
end process;
reg_774_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
reg_774 <= b_q0;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)))) then
reg_774 <= b_q1;
end if;
end if;
end process;
reg_779_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
reg_779 <= a_q0;
elsif ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)))) then
reg_779 <= a_q1;
end if;
end if;
end process;
reg_800_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
reg_800 <= a_q0;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
reg_800 <= a_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
a_load_17_reg_2660 <= a_q0;
a_load_21_reg_2665 <= a_q1;
tmp16_reg_2646 <= grp_fu_1471_p3;
tmp4_reg_2600 <= grp_fu_1465_p3;
tmp62_reg_2670 <= grp_fu_1477_p3;
tmp65_reg_2675 <= grp_fu_1483_p3;
tmp68_reg_2680 <= grp_fu_1489_p3;
tmp71_reg_2685 <= grp_fu_1495_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
b_load_15_reg_1964 <= b_q0;
b_load_20_reg_1969 <= b_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)))) then
reg_784 <= a_q0;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)))) then
reg_788 <= a_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)))) then
reg_792 <= b_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)))) then
reg_796 <= a_q1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
tmp10_reg_2792 <= grp_fu_1544_p3;
tmp12_reg_2797 <= grp_fu_1550_p3;
tmp15_reg_2802 <= grp_fu_1556_p3;
tmp18_reg_2807 <= grp_fu_1562_p3;
tmp22_reg_2817 <= grp_fu_1568_p3;
tmp9_reg_2787 <= grp_fu_1538_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
tmp11_reg_2301 <= grp_fu_1374_p3;
tmp23_reg_2324 <= grp_fu_1380_p3;
tmp26_reg_2329 <= grp_fu_1386_p3;
tmp32_reg_2334 <= grp_fu_1392_p3;
tmp35_reg_2339 <= grp_fu_1398_p3;
tmp8_reg_2287 <= grp_fu_1368_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
tmp13_reg_2851 <= grp_fu_1573_p3;
tmp21_reg_2866 <= grp_fu_1579_p3;
tmp24_reg_2871 <= grp_fu_1584_p3;
tmp25_reg_2876 <= grp_fu_1589_p3;
tmp27_reg_2881 <= grp_fu_1594_p3;
tmp30_reg_2886 <= grp_fu_1599_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then
tmp14_reg_2393 <= grp_fu_1404_p3;
tmp29_reg_2407 <= grp_fu_1410_p3;
tmp38_reg_2421 <= grp_fu_1416_p3;
tmp41_reg_2426 <= grp_fu_1421_p3;
tmp44_reg_2431 <= grp_fu_1426_p3;
tmp47_reg_2436 <= grp_fu_1432_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then
tmp17_reg_2215 <= grp_fu_1354_p3;
tmp20_reg_2220 <= grp_fu_1361_p3;
tmp2_reg_2173 <= grp_fu_1340_p3;
tmp5_reg_2187 <= grp_fu_1347_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
tmp19_reg_2744 <= grp_fu_1528_p3;
tmp3_reg_2700 <= grp_fu_1508_p3;
tmp6_reg_2705 <= grp_fu_1515_p3;
tmp74_reg_2767 <= grp_fu_1533_p3;
tmp7_reg_2710 <= grp_fu_1522_p3;
tmp_reg_2695 <= grp_fu_1501_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
tmp1_reg_2508 <= grp_fu_1438_p3;
tmp50_reg_2540 <= grp_fu_1445_p3;
tmp53_reg_2545 <= grp_fu_1450_p3;
tmp56_reg_2550 <= grp_fu_1455_p3;
tmp59_reg_2555 <= grp_fu_1460_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
tmp28_reg_2935 <= grp_fu_1605_p3;
tmp31_reg_2940 <= grp_fu_1610_p3;
tmp33_reg_2945 <= grp_fu_1616_p3;
tmp36_reg_2950 <= grp_fu_1621_p3;
tmp39_reg_2955 <= grp_fu_1626_p3;
tmp42_reg_2960 <= grp_fu_1631_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
tmp34_reg_3004 <= grp_fu_1636_p3;
tmp37_reg_3009 <= grp_fu_1641_p3;
tmp45_reg_3023 <= grp_fu_1646_p3;
tmp48_reg_3028 <= grp_fu_1652_p3;
tmp51_reg_3033 <= grp_fu_1658_p3;
tmp54_reg_3038 <= grp_fu_1664_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
tmp40_reg_3073 <= grp_fu_1670_p3;
tmp43_reg_3078 <= grp_fu_1675_p3;
tmp57_reg_3083 <= grp_fu_1680_p3;
tmp60_reg_3097 <= grp_fu_1685_p3;
tmp63_reg_3102 <= grp_fu_1691_p3;
tmp66_reg_3107 <= grp_fu_1697_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then
tmp46_reg_3132 <= grp_fu_1703_p3;
tmp49_reg_3137 <= grp_fu_1709_p3;
tmp52_reg_3142 <= grp_fu_1715_p3;
tmp55_reg_3147 <= grp_fu_1721_p3;
tmp69_reg_3152 <= grp_fu_1727_p3;
tmp72_reg_3157 <= grp_fu_1732_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1))) then
tmp58_reg_3182 <= grp_fu_1737_p3;
tmp61_reg_3187 <= grp_fu_1742_p3;
tmp64_reg_3192 <= grp_fu_1748_p3;
tmp67_reg_3197 <= grp_fu_1754_p3;
tmp70_reg_3202 <= grp_fu_1760_p3;
tmp73_reg_3207 <= grp_fu_1766_p3;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0))) then
tmp75_reg_2155 <= tmp75_fu_990_p1;
tmp_1_0_1_reg_2178 <= tmp_1_0_1_fu_1004_p1;
tmp_1_0_2_reg_2192 <= tmp_1_0_2_fu_1014_p1;
tmp_1_0_4_4_reg_2206 <= tmp_1_0_4_4_fu_1024_p1;
tmp_1_reg_2164 <= tmp_1_fu_994_p1;
tmp_2_0_4_3_reg_2201 <= grp_fu_877_p2;
tmp_2_1_4_3_reg_2225 <= grp_fu_882_p2;
tmp_2_2_0_3_reg_2230 <= grp_fu_891_p2;
tmp_2_2_1_3_reg_2235 <= grp_fu_896_p2;
tmp_313_0_4_reg_2240 <= tmp_313_0_4_fu_1028_p1;
tmp_3_3_4_4_reg_3212 <= tmp_3_3_4_4_fu_1316_p2;
tmp_3_4_0_4_reg_3217 <= tmp_3_4_0_4_fu_1320_p2;
tmp_3_4_1_4_reg_3222 <= tmp_3_4_1_4_fu_1324_p2;
tmp_3_4_2_4_reg_3227 <= tmp_3_4_2_4_fu_1328_p2;
tmp_3_4_3_4_reg_3232 <= tmp_3_4_3_4_fu_1332_p2;
tmp_3_4_4_4_reg_3237 <= tmp_3_4_4_4_fu_1336_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0))) then
tmp_0_0_1_reg_2490 <= tmp_0_0_1_fu_1107_p1;
tmp_1_0_0_1_reg_2499 <= tmp_1_0_0_1_fu_1111_p1;
tmp_1_0_1_1_reg_2513 <= tmp_1_0_1_1_fu_1115_p1;
tmp_1_0_2_1_reg_2522 <= tmp_1_0_2_1_fu_1119_p1;
tmp_1_0_2_2_reg_2531 <= tmp_1_0_2_2_fu_1123_p1;
tmp_2_4_0_3_reg_2560 <= grp_fu_970_p2;
tmp_2_4_1_3_reg_2565 <= grp_fu_975_p2;
tmp_2_4_2_3_reg_2570 <= grp_fu_980_p2;
tmp_2_4_3_3_reg_2575 <= grp_fu_985_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0))) then
tmp_0_0_2_reg_2269 <= tmp_0_0_2_fu_1036_p1;
tmp_1_0_0_2_reg_2278 <= tmp_1_0_0_2_fu_1040_p1;
tmp_1_0_3_reg_2292 <= tmp_1_0_3_fu_1044_p1;
tmp_1_0_4_reg_2306 <= tmp_1_0_4_fu_1052_p1;
tmp_2_2_2_3_reg_2344 <= grp_fu_901_p2;
tmp_2_2_3_3_reg_2349 <= grp_fu_905_p2;
tmp_2_2_4_3_reg_2354 <= grp_fu_909_p2;
tmp_2_3_0_3_reg_2359 <= grp_fu_917_p2;
tmp_s_reg_2315 <= tmp_s_fu_1060_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0))) then
tmp_0_0_3_reg_1832 <= tmp_0_0_3_fu_805_p1;
tmp_111_0_3_reg_1859 <= tmp_111_0_3_fu_829_p1;
tmp_1_0_0_3_reg_1841 <= tmp_1_0_0_3_fu_809_p1;
tmp_1_0_1_3_reg_1850 <= tmp_1_0_1_3_fu_819_p1;
tmp_2_2_1_reg_2891 <= grp_fu_1127_p2;
tmp_2_2_2_reg_2896 <= grp_fu_1131_p2;
tmp_2_2_3_reg_2901 <= grp_fu_1135_p2;
tmp_2_2_4_reg_2906 <= grp_fu_1139_p2;
tmp_313_0_1_reg_2911 <= tmp_313_0_1_fu_1250_p1;
tmp_3_0_3_4_reg_2846 <= tmp_3_0_3_4_fu_1238_p2;
tmp_3_1_0_4_reg_2856 <= tmp_3_1_0_4_fu_1242_p2;
tmp_3_1_1_4_reg_2861 <= tmp_3_1_1_4_fu_1246_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0))) then
tmp_0_0_4_reg_2008 <= tmp_0_0_4_fu_922_p1;
tmp_111_0_4_reg_2045 <= tmp_111_0_4_fu_934_p1;
tmp_1_0_0_4_reg_2017 <= tmp_1_0_0_4_fu_926_p1;
tmp_1_0_1_4_reg_2031 <= tmp_1_0_1_4_fu_930_p1;
tmp_2_0_0_3_reg_2003 <= grp_fu_813_p2;
tmp_2_0_1_3_reg_2026 <= grp_fu_823_p2;
tmp_2_1_0_3_reg_2040 <= grp_fu_833_p2;
tmp_2_1_1_3_reg_2054 <= grp_fu_839_p2;
tmp_3_2_3_4_reg_3122 <= tmp_3_2_3_4_fu_1292_p2;
tmp_3_2_4_4_reg_3127 <= tmp_3_2_4_4_fu_1296_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
tmp_111_0_1_reg_2637 <= tmp_111_0_1_fu_1155_p1;
tmp_1_0_3_1_reg_2610 <= tmp_1_0_3_1_fu_1143_p1;
tmp_1_0_3_2_reg_2619 <= tmp_1_0_3_2_fu_1147_p1;
tmp_1_0_4_1_reg_2628 <= tmp_1_0_4_1_fu_1151_p1;
tmp_2_0_1_reg_2595 <= grp_fu_1008_p2;
tmp_2_0_2_reg_2605 <= grp_fu_1018_p2;
tmp_2_4_4_3_reg_2690 <= grp_fu_1032_p2;
tmp_2_reg_2590 <= grp_fu_998_p2;
tmp_5_reg_2651 <= tmp_5_fu_1159_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0))) then
tmp_111_0_2_reg_2398 <= tmp_111_0_2_fu_1078_p1;
tmp_1_0_1_2_reg_2384 <= tmp_1_0_1_2_fu_1074_p1;
tmp_2_3_1_3_reg_2441 <= grp_fu_938_p2;
tmp_2_3_2_3_reg_2446 <= grp_fu_942_p2;
tmp_2_3_3_3_reg_2451 <= grp_fu_946_p2;
tmp_2_3_4_3_reg_2456 <= grp_fu_950_p2;
tmp_3_reg_2412 <= tmp_3_fu_1094_p1;
tmp_4_0_4_reg_2461 <= tmp_4_0_4_fu_1103_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0))) then
tmp_1_0_2_3_reg_1888 <= tmp_1_0_2_3_fu_845_p1;
tmp_1_0_3_3_reg_1897 <= tmp_1_0_3_3_fu_854_p1;
tmp_2_3_1_reg_2970 <= grp_fu_1168_p2;
tmp_2_3_2_reg_2975 <= grp_fu_1173_p2;
tmp_2_3_3_reg_2980 <= grp_fu_1178_p2;
tmp_2_3_reg_2965 <= grp_fu_1163_p2;
tmp_3_0_4_4_reg_2920 <= tmp_3_0_4_4_fu_1254_p2;
tmp_3_1_2_4_reg_2925 <= tmp_3_1_2_4_fu_1258_p2;
tmp_3_1_3_4_reg_2930 <= tmp_3_1_3_4_fu_1262_p2;
tmp_4_0_1_reg_2985 <= tmp_4_0_1_fu_1266_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0))) then
tmp_1_0_2_4_reg_2084 <= tmp_1_0_2_4_fu_954_p1;
tmp_1_0_3_4_reg_2098 <= tmp_1_0_3_4_fu_958_p1;
tmp_212_0_4_reg_2117 <= tmp_212_0_4_fu_962_p1;
tmp_2_0_2_3_reg_2079 <= grp_fu_849_p2;
tmp_2_0_3_3_reg_2093 <= grp_fu_858_p2;
tmp_2_1_2_3_reg_2107 <= grp_fu_863_p2;
tmp_2_1_3_3_reg_2112 <= grp_fu_868_p2;
tmp_3_3_0_4_reg_3162 <= tmp_3_3_0_4_fu_1300_p2;
tmp_3_3_1_4_reg_3167 <= tmp_3_3_1_4_fu_1304_p2;
tmp_3_3_2_4_reg_3172 <= tmp_3_3_2_4_fu_1308_p2;
tmp_3_3_3_4_reg_3177 <= tmp_3_3_3_4_fu_1312_p2;
tmp_4_0_3_reg_2126 <= tmp_4_0_3_fu_966_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0))) then
tmp_1_0_4_2_reg_2725 <= tmp_1_0_4_2_fu_1183_p1;
tmp_212_0_1_reg_2749 <= tmp_212_0_1_fu_1187_p1;
tmp_2_0_3_reg_2715 <= grp_fu_1047_p2;
tmp_2_0_4_reg_2720 <= grp_fu_1055_p2;
tmp_2_1_1_reg_2739 <= grp_fu_1069_p2;
tmp_2_1_reg_2734 <= grp_fu_1064_p2;
tmp_4_reg_2758 <= tmp_4_fu_1195_p1;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0))) then
tmp_1_0_4_3_reg_1926 <= tmp_1_0_4_3_fu_873_p1;
tmp_212_0_3_reg_1935 <= tmp_212_0_3_fu_887_p1;
tmp_2_3_4_reg_3043 <= grp_fu_1191_p2;
tmp_2_4_1_reg_3053 <= grp_fu_1204_p2;
tmp_2_4_2_reg_3058 <= grp_fu_1209_p2;
tmp_2_4_reg_3048 <= grp_fu_1199_p2;
tmp_313_0_2_reg_3014 <= tmp_313_0_2_fu_1277_p1;
tmp_3_1_4_4_reg_2994 <= tmp_3_1_4_4_fu_1269_p2;
tmp_3_2_0_4_reg_2999 <= tmp_3_2_0_4_fu_1273_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0))) then
tmp_212_0_2_reg_2837 <= tmp_212_0_2_fu_1226_p1;
tmp_2_1_2_reg_2812 <= grp_fu_1082_p2;
tmp_2_1_3_reg_2822 <= grp_fu_1086_p2;
tmp_2_1_4_reg_2827 <= grp_fu_1090_p2;
tmp_2_2_reg_2832 <= grp_fu_1098_p2;
tmp_3_0_0_4_reg_2772 <= tmp_3_0_0_4_fu_1214_p2;
tmp_3_0_1_4_reg_2777 <= tmp_3_0_1_4_fu_1218_p2;
tmp_3_0_2_4_reg_2782 <= tmp_3_0_2_4_fu_1222_p2;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0))) then
tmp_2_4_3_reg_3112 <= grp_fu_1230_p2;
tmp_2_4_4_reg_3117 <= grp_fu_1234_p2;
tmp_313_0_3_reg_1974 <= tmp_313_0_3_fu_913_p1;
tmp_3_2_1_4_reg_3063 <= tmp_3_2_1_4_fu_1280_p2;
tmp_3_2_2_4_reg_3068 <= tmp_3_2_2_4_fu_1284_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_block_pp0_stage12_flag00011011, ap_block_pp0_stage1_flag00011011, ap_block_pp0_stage0_flag00011011, ap_idle_pp0_1to2, ap_reset_idle_pp0, ap_block_pp0_stage2_flag00011011, ap_block_pp0_stage3_flag00011011, ap_block_pp0_stage4_flag00011011, ap_block_pp0_stage5_flag00011011, ap_block_pp0_stage6_flag00011011, ap_block_pp0_stage7_flag00011011, ap_block_pp0_stage8_flag00011011, ap_block_pp0_stage9_flag00011011, ap_block_pp0_stage10_flag00011011, ap_block_pp0_stage11_flag00011011)
begin
case ap_CS_fsm is
when ap_ST_fsm_pp0_stage0 =>
if (((ap_block_pp0_stage0_flag00011011 = ap_const_boolean_0) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_1to2))))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
end if;
when ap_ST_fsm_pp0_stage1 =>
if (((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0) and (ap_reset_idle_pp0 = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
elsif (((ap_block_pp0_stage1_flag00011011 = ap_const_boolean_0) and (ap_const_logic_1 = ap_reset_idle_pp0))) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage1;
end if;
when ap_ST_fsm_pp0_stage2 =>
if ((ap_block_pp0_stage2_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage2;
end if;
when ap_ST_fsm_pp0_stage3 =>
if ((ap_block_pp0_stage3_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage3;
end if;
when ap_ST_fsm_pp0_stage4 =>
if ((ap_block_pp0_stage4_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage4;
end if;
when ap_ST_fsm_pp0_stage5 =>
if ((ap_block_pp0_stage5_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage5;
end if;
when ap_ST_fsm_pp0_stage6 =>
if ((ap_block_pp0_stage6_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage6;
end if;
when ap_ST_fsm_pp0_stage7 =>
if ((ap_block_pp0_stage7_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage7;
end if;
when ap_ST_fsm_pp0_stage8 =>
if ((ap_block_pp0_stage8_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage8;
end if;
when ap_ST_fsm_pp0_stage9 =>
if ((ap_block_pp0_stage9_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage9;
end if;
when ap_ST_fsm_pp0_stage10 =>
if ((ap_block_pp0_stage10_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage10;
end if;
when ap_ST_fsm_pp0_stage11 =>
if ((ap_block_pp0_stage11_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage11;
end if;
when ap_ST_fsm_pp0_stage12 =>
if ((ap_block_pp0_stage12_flag00011011 = ap_const_boolean_0)) then
ap_NS_fsm <= ap_ST_fsm_pp0_stage0;
else
ap_NS_fsm <= ap_ST_fsm_pp0_stage12;
end if;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXX";
end case;
end process;
a_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_16(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_11(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_C(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_7(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_2(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_E(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_4(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_F(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_5(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_0(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_D(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
a_address0 <= ap_const_lv32_3(5 - 1 downto 0);
else
a_address0 <= "XXXXX";
end if;
else
a_address0 <= "XXXXX";
end if;
end process;
a_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_15(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_10(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_B(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_6(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_18(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_13(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_9(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_14(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_A(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_17(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_12(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
a_address1 <= ap_const_lv32_8(5 - 1 downto 0);
else
a_address1 <= "XXXXX";
end if;
else
a_address1 <= "XXXXX";
end if;
end process;
a_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)))) then
a_ce0 <= ap_const_logic_1;
else
a_ce0 <= ap_const_logic_0;
end if;
end process;
a_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)))) then
a_ce1 <= ap_const_logic_1;
else
a_ce1 <= ap_const_logic_0;
end if;
end process;
ap_CS_fsm_pp0_stage0 <= ap_CS_fsm(0);
ap_CS_fsm_pp0_stage1 <= ap_CS_fsm(1);
ap_CS_fsm_pp0_stage10 <= ap_CS_fsm(10);
ap_CS_fsm_pp0_stage11 <= ap_CS_fsm(11);
ap_CS_fsm_pp0_stage12 <= ap_CS_fsm(12);
ap_CS_fsm_pp0_stage2 <= ap_CS_fsm(2);
ap_CS_fsm_pp0_stage3 <= ap_CS_fsm(3);
ap_CS_fsm_pp0_stage4 <= ap_CS_fsm(4);
ap_CS_fsm_pp0_stage5 <= ap_CS_fsm(5);
ap_CS_fsm_pp0_stage6 <= ap_CS_fsm(6);
ap_CS_fsm_pp0_stage7 <= ap_CS_fsm(7);
ap_CS_fsm_pp0_stage8 <= ap_CS_fsm(8);
ap_CS_fsm_pp0_stage9 <= ap_CS_fsm(9);
ap_block_pp0_stage0_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage0_flag00011001_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0)
begin
ap_block_pp0_stage0_flag00011001 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0));
end process;
ap_block_pp0_stage0_flag00011011_assign_proc : process(ap_start, ap_enable_reg_pp0_iter0)
begin
ap_block_pp0_stage0_flag00011011 <= ((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0));
end process;
ap_block_pp0_stage10_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage10_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage11_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage12_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage1_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage2_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage3_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage4_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage5_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage6_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage7_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage8_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00000000 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011001 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_pp0_stage9_flag00011011 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state10_pp0_stage9_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state11_pp0_stage10_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state12_pp0_stage11_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state13_pp0_stage12_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state14_pp0_stage0_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state15_pp0_stage1_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state16_pp0_stage2_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state17_pp0_stage3_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state18_pp0_stage4_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state19_pp0_stage5_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state1_pp0_stage0_iter0_assign_proc : process(ap_start)
begin
ap_block_state1_pp0_stage0_iter0 <= (ap_const_logic_0 = ap_start);
end process;
ap_block_state20_pp0_stage6_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state21_pp0_stage7_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state22_pp0_stage8_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state23_pp0_stage9_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state24_pp0_stage10_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state25_pp0_stage11_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state26_pp0_stage12_iter1 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state27_pp0_stage0_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state28_pp0_stage1_iter2 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state2_pp0_stage1_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state3_pp0_stage2_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state4_pp0_stage3_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state5_pp0_stage4_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state6_pp0_stage5_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state7_pp0_stage6_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state8_pp0_stage7_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_block_state9_pp0_stage8_iter0 <= not((ap_const_boolean_1 = ap_const_boolean_1));
ap_done_assign_proc : process(ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_enable_pp0 <= (ap_idle_pp0 xor ap_const_logic_1);
ap_enable_reg_pp0_iter0_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0_reg)
begin
if ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0)) then
ap_enable_reg_pp0_iter0 <= ap_start;
else
ap_enable_reg_pp0_iter0 <= ap_enable_reg_pp0_iter0_reg;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_pp0_stage0, ap_idle_pp0)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_idle_pp0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then
ap_idle_pp0 <= ap_const_logic_1;
else
ap_idle_pp0 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_0to1_assign_proc : process(ap_enable_reg_pp0_iter0, ap_enable_reg_pp0_iter1)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter0) and (ap_const_logic_0 = ap_enable_reg_pp0_iter1))) then
ap_idle_pp0_0to1 <= ap_const_logic_1;
else
ap_idle_pp0_0to1 <= ap_const_logic_0;
end if;
end process;
ap_idle_pp0_1to2_assign_proc : process(ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2)
begin
if (((ap_const_logic_0 = ap_enable_reg_pp0_iter1) and (ap_const_logic_0 = ap_enable_reg_pp0_iter2))) then
ap_idle_pp0_1to2 <= ap_const_logic_1;
else
ap_idle_pp0_1to2 <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reset_idle_pp0_assign_proc : process(ap_start, ap_idle_pp0_0to1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_idle_pp0_0to1))) then
ap_reset_idle_pp0 <= ap_const_logic_1;
else
ap_reset_idle_pp0 <= ap_const_logic_0;
end if;
end process;
b_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_E(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_D(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_C(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_B(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_A(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_5(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_16(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_14(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_3(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_1(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_0(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_11(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
b_address0 <= ap_const_lv32_F(5 - 1 downto 0);
else
b_address0 <= "XXXXX";
end if;
else
b_address0 <= "XXXXX";
end if;
end process;
b_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000)
begin
if ((ap_const_logic_1 = ap_enable_reg_pp0_iter0)) then
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_9(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_8(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_7(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_6(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_18(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_17(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_15(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_4(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_2(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_13(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_12(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0))) then
b_address1 <= ap_const_lv32_10(5 - 1 downto 0);
else
b_address1 <= "XXXXX";
end if;
else
b_address1 <= "XXXXX";
end if;
end process;
b_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)))) then
b_ce0 <= ap_const_logic_1;
else
b_ce0 <= ap_const_logic_0;
end if;
end process;
b_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter0, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter0) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)))) then
b_ce1 <= ap_const_logic_1;
else
b_ce1 <= ap_const_logic_0;
end if;
end process;
grp_fu_1008_p1 <= tmp75_fu_990_p1(8 - 1 downto 0);
grp_fu_1018_p1 <= tmp75_fu_990_p1(8 - 1 downto 0);
grp_fu_1032_p0 <= tmp_1_0_4_3_reg_1926(8 - 1 downto 0);
grp_fu_1032_p1 <= tmp_4_0_3_reg_2126(8 - 1 downto 0);
grp_fu_1047_p1 <= tmp75_reg_2155(8 - 1 downto 0);
grp_fu_1055_p1 <= tmp75_reg_2155(8 - 1 downto 0);
grp_fu_1064_p0 <= tmp_1_reg_2164(8 - 1 downto 0);
grp_fu_1064_p1 <= tmp_s_fu_1060_p1(8 - 1 downto 0);
grp_fu_1069_p0 <= tmp_1_0_1_reg_2178(8 - 1 downto 0);
grp_fu_1069_p1 <= tmp_s_fu_1060_p1(8 - 1 downto 0);
grp_fu_1082_p0 <= tmp_1_0_2_reg_2192(8 - 1 downto 0);
grp_fu_1082_p1 <= tmp_s_reg_2315(8 - 1 downto 0);
grp_fu_1086_p0 <= tmp_1_0_3_reg_2292(8 - 1 downto 0);
grp_fu_1086_p1 <= tmp_s_reg_2315(8 - 1 downto 0);
grp_fu_1090_p0 <= tmp_1_0_4_reg_2306(8 - 1 downto 0);
grp_fu_1090_p1 <= tmp_s_reg_2315(8 - 1 downto 0);
grp_fu_1098_p0 <= tmp_1_reg_2164(8 - 1 downto 0);
grp_fu_1127_p0 <= tmp_1_0_1_reg_2178(8 - 1 downto 0);
grp_fu_1127_p1 <= tmp_3_reg_2412(8 - 1 downto 0);
grp_fu_1131_p0 <= tmp_1_0_2_reg_2192(8 - 1 downto 0);
grp_fu_1131_p1 <= tmp_3_reg_2412(8 - 1 downto 0);
grp_fu_1135_p0 <= tmp_1_0_3_reg_2292(8 - 1 downto 0);
grp_fu_1135_p1 <= tmp_3_reg_2412(8 - 1 downto 0);
grp_fu_1139_p0 <= tmp_1_0_4_reg_2306(8 - 1 downto 0);
grp_fu_1139_p1 <= tmp_3_reg_2412(8 - 1 downto 0);
grp_fu_1163_p0 <= tmp_1_reg_2164(8 - 1 downto 0);
grp_fu_1163_p1 <= tmp_5_fu_1159_p1(8 - 1 downto 0);
grp_fu_1168_p0 <= tmp_1_0_1_reg_2178(8 - 1 downto 0);
grp_fu_1168_p1 <= tmp_5_fu_1159_p1(8 - 1 downto 0);
grp_fu_1173_p0 <= tmp_1_0_2_reg_2192(8 - 1 downto 0);
grp_fu_1173_p1 <= tmp_5_fu_1159_p1(8 - 1 downto 0);
grp_fu_1178_p0 <= tmp_1_0_3_reg_2292(8 - 1 downto 0);
grp_fu_1178_p1 <= tmp_5_fu_1159_p1(8 - 1 downto 0);
grp_fu_1191_p0 <= tmp_1_0_4_reg_2306(8 - 1 downto 0);
grp_fu_1191_p1 <= tmp_5_reg_2651(8 - 1 downto 0);
grp_fu_1199_p0 <= tmp_1_reg_2164(8 - 1 downto 0);
grp_fu_1199_p1 <= tmp_4_fu_1195_p1(8 - 1 downto 0);
grp_fu_1204_p0 <= tmp_1_0_1_reg_2178(8 - 1 downto 0);
grp_fu_1204_p1 <= tmp_4_fu_1195_p1(8 - 1 downto 0);
grp_fu_1209_p0 <= tmp_1_0_2_reg_2192(8 - 1 downto 0);
grp_fu_1209_p1 <= tmp_4_fu_1195_p1(8 - 1 downto 0);
grp_fu_1230_p0 <= tmp_1_0_3_reg_2292(8 - 1 downto 0);
grp_fu_1230_p1 <= tmp_4_reg_2758(8 - 1 downto 0);
grp_fu_1234_p0 <= tmp_1_0_4_reg_2306(8 - 1 downto 0);
grp_fu_1234_p1 <= tmp_4_reg_2758(8 - 1 downto 0);
grp_fu_1340_p0 <= tmp_1_0_0_4_fu_926_p1(8 - 1 downto 0);
grp_fu_1340_p1 <= tmp_0_0_4_fu_922_p1(8 - 1 downto 0);
grp_fu_1347_p0 <= tmp_1_0_1_4_fu_930_p1(8 - 1 downto 0);
grp_fu_1347_p1 <= tmp_0_0_4_fu_922_p1(8 - 1 downto 0);
grp_fu_1354_p0 <= tmp_1_0_0_4_fu_926_p1(8 - 1 downto 0);
grp_fu_1354_p1 <= tmp_111_0_4_fu_934_p1(8 - 1 downto 0);
grp_fu_1361_p0 <= tmp_1_0_1_4_fu_930_p1(8 - 1 downto 0);
grp_fu_1361_p1 <= tmp_111_0_4_fu_934_p1(8 - 1 downto 0);
grp_fu_1368_p0 <= tmp_1_0_2_4_fu_954_p1(8 - 1 downto 0);
grp_fu_1368_p1 <= tmp_0_0_4_reg_2008(8 - 1 downto 0);
grp_fu_1374_p0 <= tmp_1_0_3_4_fu_958_p1(8 - 1 downto 0);
grp_fu_1374_p1 <= tmp_0_0_4_reg_2008(8 - 1 downto 0);
grp_fu_1380_p0 <= tmp_1_0_2_4_fu_954_p1(8 - 1 downto 0);
grp_fu_1380_p1 <= tmp_111_0_4_reg_2045(8 - 1 downto 0);
grp_fu_1386_p0 <= tmp_1_0_3_4_fu_958_p1(8 - 1 downto 0);
grp_fu_1386_p1 <= tmp_111_0_4_reg_2045(8 - 1 downto 0);
grp_fu_1392_p0 <= tmp_1_0_0_4_reg_2017(8 - 1 downto 0);
grp_fu_1392_p1 <= tmp_212_0_4_fu_962_p1(8 - 1 downto 0);
grp_fu_1398_p0 <= tmp_1_0_1_4_reg_2031(8 - 1 downto 0);
grp_fu_1398_p1 <= tmp_212_0_4_fu_962_p1(8 - 1 downto 0);
grp_fu_1404_p0 <= tmp_1_0_4_4_fu_1024_p1(8 - 1 downto 0);
grp_fu_1404_p1 <= tmp_0_0_4_reg_2008(8 - 1 downto 0);
grp_fu_1410_p0 <= tmp_1_0_4_4_fu_1024_p1(8 - 1 downto 0);
grp_fu_1410_p1 <= tmp_111_0_4_reg_2045(8 - 1 downto 0);
grp_fu_1416_p0 <= tmp_1_0_2_4_reg_2084(8 - 1 downto 0);
grp_fu_1416_p1 <= tmp_212_0_4_reg_2117(8 - 1 downto 0);
grp_fu_1421_p0 <= tmp_1_0_3_4_reg_2098(8 - 1 downto 0);
grp_fu_1421_p1 <= tmp_212_0_4_reg_2117(8 - 1 downto 0);
grp_fu_1426_p0 <= tmp_1_0_4_4_fu_1024_p1(8 - 1 downto 0);
grp_fu_1426_p1 <= tmp_212_0_4_reg_2117(8 - 1 downto 0);
grp_fu_1432_p0 <= tmp_1_0_0_4_reg_2017(8 - 1 downto 0);
grp_fu_1445_p0 <= tmp_1_0_1_4_reg_2031(8 - 1 downto 0);
grp_fu_1445_p1 <= tmp_313_0_4_reg_2240(8 - 1 downto 0);
grp_fu_1450_p0 <= tmp_1_0_2_4_reg_2084(8 - 1 downto 0);
grp_fu_1450_p1 <= tmp_313_0_4_reg_2240(8 - 1 downto 0);
grp_fu_1455_p0 <= tmp_1_0_3_4_reg_2098(8 - 1 downto 0);
grp_fu_1455_p1 <= tmp_313_0_4_reg_2240(8 - 1 downto 0);
grp_fu_1460_p0 <= tmp_1_0_4_4_reg_2206(8 - 1 downto 0);
grp_fu_1460_p1 <= tmp_313_0_4_reg_2240(8 - 1 downto 0);
grp_fu_1465_p1 <= tmp_0_0_2_reg_2269(8 - 1 downto 0);
grp_fu_1471_p0 <= tmp_1_0_0_2_reg_2278(8 - 1 downto 0);
grp_fu_1477_p0 <= tmp_1_0_0_4_reg_2017(8 - 1 downto 0);
grp_fu_1477_p1 <= tmp_4_0_4_fu_1103_p1(8 - 1 downto 0);
grp_fu_1483_p0 <= tmp_1_0_1_4_reg_2031(8 - 1 downto 0);
grp_fu_1483_p1 <= tmp_4_0_4_fu_1103_p1(8 - 1 downto 0);
grp_fu_1489_p0 <= tmp_1_0_2_4_reg_2084(8 - 1 downto 0);
grp_fu_1489_p1 <= tmp_4_0_4_fu_1103_p1(8 - 1 downto 0);
grp_fu_1495_p0 <= tmp_1_0_3_4_reg_2098(8 - 1 downto 0);
grp_fu_1495_p1 <= tmp_4_0_4_fu_1103_p1(8 - 1 downto 0);
grp_fu_1501_p1 <= tmp_0_0_1_fu_1107_p1(8 - 1 downto 0);
grp_fu_1508_p1 <= tmp_0_0_1_fu_1107_p1(8 - 1 downto 0);
grp_fu_1515_p1 <= tmp_0_0_1_fu_1107_p1(8 - 1 downto 0);
grp_fu_1522_p1 <= tmp_0_0_2_reg_2269(8 - 1 downto 0);
grp_fu_1528_p0 <= tmp_1_0_1_2_reg_2384(8 - 1 downto 0);
grp_fu_1528_p1 <= tmp_111_0_2_reg_2398(8 - 1 downto 0);
grp_fu_1533_p0 <= tmp_1_0_4_4_reg_2206(8 - 1 downto 0);
grp_fu_1533_p1 <= tmp_4_0_4_reg_2461(8 - 1 downto 0);
grp_fu_1538_p1 <= tmp_0_0_1_reg_2490(8 - 1 downto 0);
grp_fu_1544_p1 <= tmp_0_0_2_reg_2269(8 - 1 downto 0);
grp_fu_1550_p1 <= tmp_0_0_1_reg_2490(8 - 1 downto 0);
grp_fu_1556_p0 <= tmp_1_0_0_1_reg_2499(8 - 1 downto 0);
grp_fu_1556_p1 <= tmp_111_0_1_fu_1155_p1(8 - 1 downto 0);
grp_fu_1562_p0 <= tmp_1_0_1_1_reg_2513(8 - 1 downto 0);
grp_fu_1562_p1 <= tmp_111_0_1_fu_1155_p1(8 - 1 downto 0);
grp_fu_1568_p0 <= tmp_1_0_2_2_reg_2531(8 - 1 downto 0);
grp_fu_1568_p1 <= tmp_111_0_2_reg_2398(8 - 1 downto 0);
grp_fu_1573_p1 <= tmp_0_0_2_reg_2269(8 - 1 downto 0);
grp_fu_1579_p0 <= tmp_1_0_2_1_reg_2522(8 - 1 downto 0);
grp_fu_1579_p1 <= tmp_111_0_1_reg_2637(8 - 1 downto 0);
grp_fu_1584_p0 <= tmp_1_0_3_1_reg_2610(8 - 1 downto 0);
grp_fu_1584_p1 <= tmp_111_0_1_reg_2637(8 - 1 downto 0);
grp_fu_1589_p0 <= tmp_1_0_3_2_reg_2619(8 - 1 downto 0);
grp_fu_1589_p1 <= tmp_111_0_2_reg_2398(8 - 1 downto 0);
grp_fu_1594_p0 <= tmp_1_0_4_1_reg_2628(8 - 1 downto 0);
grp_fu_1594_p1 <= tmp_111_0_1_reg_2637(8 - 1 downto 0);
grp_fu_1599_p0 <= tmp_1_0_0_1_reg_2499(8 - 1 downto 0);
grp_fu_1605_p0 <= tmp_1_0_4_2_reg_2725(8 - 1 downto 0);
grp_fu_1605_p1 <= tmp_111_0_2_reg_2398(8 - 1 downto 0);
grp_fu_1610_p0 <= tmp_1_0_0_2_reg_2278(8 - 1 downto 0);
grp_fu_1616_p0 <= tmp_1_0_1_1_reg_2513(8 - 1 downto 0);
grp_fu_1616_p1 <= tmp_212_0_1_reg_2749(8 - 1 downto 0);
grp_fu_1621_p0 <= tmp_1_0_2_1_reg_2522(8 - 1 downto 0);
grp_fu_1621_p1 <= tmp_212_0_1_reg_2749(8 - 1 downto 0);
grp_fu_1626_p0 <= tmp_1_0_3_1_reg_2610(8 - 1 downto 0);
grp_fu_1626_p1 <= tmp_212_0_1_reg_2749(8 - 1 downto 0);
grp_fu_1631_p0 <= tmp_1_0_4_1_reg_2628(8 - 1 downto 0);
grp_fu_1631_p1 <= tmp_212_0_1_reg_2749(8 - 1 downto 0);
grp_fu_1636_p0 <= tmp_1_0_1_2_reg_2384(8 - 1 downto 0);
grp_fu_1636_p1 <= tmp_212_0_2_reg_2837(8 - 1 downto 0);
grp_fu_1641_p0 <= tmp_1_0_2_2_reg_2531(8 - 1 downto 0);
grp_fu_1641_p1 <= tmp_212_0_2_reg_2837(8 - 1 downto 0);
grp_fu_1646_p0 <= tmp_1_0_0_1_reg_2499(8 - 1 downto 0);
grp_fu_1646_p1 <= tmp_313_0_1_fu_1250_p1(8 - 1 downto 0);
grp_fu_1652_p0 <= tmp_1_0_1_1_reg_2513(8 - 1 downto 0);
grp_fu_1652_p1 <= tmp_313_0_1_fu_1250_p1(8 - 1 downto 0);
grp_fu_1658_p0 <= tmp_1_0_2_1_reg_2522(8 - 1 downto 0);
grp_fu_1658_p1 <= tmp_313_0_1_fu_1250_p1(8 - 1 downto 0);
grp_fu_1664_p0 <= tmp_1_0_3_1_reg_2610(8 - 1 downto 0);
grp_fu_1664_p1 <= tmp_313_0_1_fu_1250_p1(8 - 1 downto 0);
grp_fu_1670_p0 <= tmp_1_0_3_2_reg_2619(8 - 1 downto 0);
grp_fu_1670_p1 <= tmp_212_0_2_reg_2837(8 - 1 downto 0);
grp_fu_1675_p0 <= tmp_1_0_4_2_reg_2725(8 - 1 downto 0);
grp_fu_1675_p1 <= tmp_212_0_2_reg_2837(8 - 1 downto 0);
grp_fu_1680_p0 <= tmp_1_0_4_1_reg_2628(8 - 1 downto 0);
grp_fu_1680_p1 <= tmp_313_0_1_reg_2911(8 - 1 downto 0);
grp_fu_1685_p0 <= tmp_1_0_0_1_reg_2499(8 - 1 downto 0);
grp_fu_1685_p1 <= tmp_4_0_1_fu_1266_p1(8 - 1 downto 0);
grp_fu_1691_p0 <= tmp_1_0_1_1_reg_2513(8 - 1 downto 0);
grp_fu_1691_p1 <= tmp_4_0_1_fu_1266_p1(8 - 1 downto 0);
grp_fu_1697_p0 <= tmp_1_0_2_1_reg_2522(8 - 1 downto 0);
grp_fu_1697_p1 <= tmp_4_0_1_fu_1266_p1(8 - 1 downto 0);
grp_fu_1703_p0 <= tmp_1_0_0_2_reg_2278(8 - 1 downto 0);
grp_fu_1703_p1 <= tmp_313_0_2_fu_1277_p1(8 - 1 downto 0);
grp_fu_1709_p0 <= tmp_1_0_1_2_reg_2384(8 - 1 downto 0);
grp_fu_1709_p1 <= tmp_313_0_2_fu_1277_p1(8 - 1 downto 0);
grp_fu_1715_p0 <= tmp_1_0_2_2_reg_2531(8 - 1 downto 0);
grp_fu_1715_p1 <= tmp_313_0_2_fu_1277_p1(8 - 1 downto 0);
grp_fu_1721_p0 <= tmp_1_0_3_2_reg_2619(8 - 1 downto 0);
grp_fu_1721_p1 <= tmp_313_0_2_fu_1277_p1(8 - 1 downto 0);
grp_fu_1727_p0 <= tmp_1_0_3_1_reg_2610(8 - 1 downto 0);
grp_fu_1727_p1 <= tmp_4_0_1_reg_2985(8 - 1 downto 0);
grp_fu_1732_p0 <= tmp_1_0_4_1_reg_2628(8 - 1 downto 0);
grp_fu_1732_p1 <= tmp_4_0_1_reg_2985(8 - 1 downto 0);
grp_fu_1737_p0 <= tmp_1_0_4_2_reg_2725(8 - 1 downto 0);
grp_fu_1737_p1 <= tmp_313_0_2_reg_3014(8 - 1 downto 0);
grp_fu_1742_p0 <= tmp_1_0_0_2_reg_2278(8 - 1 downto 0);
grp_fu_1742_p1 <= tmp_4_0_2_fu_1288_p1(8 - 1 downto 0);
grp_fu_1748_p0 <= tmp_1_0_1_2_reg_2384(8 - 1 downto 0);
grp_fu_1748_p1 <= tmp_4_0_2_fu_1288_p1(8 - 1 downto 0);
grp_fu_1754_p0 <= tmp_1_0_2_2_reg_2531(8 - 1 downto 0);
grp_fu_1754_p1 <= tmp_4_0_2_fu_1288_p1(8 - 1 downto 0);
grp_fu_1760_p0 <= tmp_1_0_3_2_reg_2619(8 - 1 downto 0);
grp_fu_1760_p1 <= tmp_4_0_2_fu_1288_p1(8 - 1 downto 0);
grp_fu_1766_p0 <= tmp_1_0_4_2_reg_2725(8 - 1 downto 0);
grp_fu_1766_p1 <= tmp_4_0_2_fu_1288_p1(8 - 1 downto 0);
grp_fu_813_p0 <= tmp_1_0_0_3_fu_809_p1(8 - 1 downto 0);
grp_fu_813_p1 <= tmp_0_0_3_fu_805_p1(8 - 1 downto 0);
grp_fu_823_p0 <= tmp_1_0_1_3_fu_819_p1(8 - 1 downto 0);
grp_fu_823_p1 <= tmp_0_0_3_fu_805_p1(8 - 1 downto 0);
grp_fu_833_p0 <= tmp_1_0_0_3_fu_809_p1(8 - 1 downto 0);
grp_fu_833_p1 <= tmp_111_0_3_fu_829_p1(8 - 1 downto 0);
grp_fu_839_p0 <= tmp_1_0_1_3_fu_819_p1(8 - 1 downto 0);
grp_fu_839_p1 <= tmp_111_0_3_fu_829_p1(8 - 1 downto 0);
grp_fu_849_p0 <= tmp_1_0_2_3_fu_845_p1(8 - 1 downto 0);
grp_fu_849_p1 <= tmp_0_0_3_reg_1832(8 - 1 downto 0);
grp_fu_858_p0 <= tmp_1_0_3_3_fu_854_p1(8 - 1 downto 0);
grp_fu_858_p1 <= tmp_0_0_3_reg_1832(8 - 1 downto 0);
grp_fu_863_p0 <= tmp_1_0_2_3_fu_845_p1(8 - 1 downto 0);
grp_fu_863_p1 <= tmp_111_0_3_reg_1859(8 - 1 downto 0);
grp_fu_868_p0 <= tmp_1_0_3_3_fu_854_p1(8 - 1 downto 0);
grp_fu_868_p1 <= tmp_111_0_3_reg_1859(8 - 1 downto 0);
grp_fu_877_p0 <= tmp_1_0_4_3_fu_873_p1(8 - 1 downto 0);
grp_fu_877_p1 <= tmp_0_0_3_reg_1832(8 - 1 downto 0);
grp_fu_882_p0 <= tmp_1_0_4_3_fu_873_p1(8 - 1 downto 0);
grp_fu_882_p1 <= tmp_111_0_3_reg_1859(8 - 1 downto 0);
grp_fu_891_p0 <= tmp_1_0_0_3_reg_1841(8 - 1 downto 0);
grp_fu_891_p1 <= tmp_212_0_3_fu_887_p1(8 - 1 downto 0);
grp_fu_896_p0 <= tmp_1_0_1_3_reg_1850(8 - 1 downto 0);
grp_fu_896_p1 <= tmp_212_0_3_fu_887_p1(8 - 1 downto 0);
grp_fu_901_p0 <= tmp_1_0_2_3_reg_1888(8 - 1 downto 0);
grp_fu_901_p1 <= tmp_212_0_3_reg_1935(8 - 1 downto 0);
grp_fu_905_p0 <= tmp_1_0_3_3_reg_1897(8 - 1 downto 0);
grp_fu_905_p1 <= tmp_212_0_3_reg_1935(8 - 1 downto 0);
grp_fu_909_p0 <= tmp_1_0_4_3_reg_1926(8 - 1 downto 0);
grp_fu_909_p1 <= tmp_212_0_3_reg_1935(8 - 1 downto 0);
grp_fu_917_p0 <= tmp_1_0_0_3_reg_1841(8 - 1 downto 0);
grp_fu_938_p0 <= tmp_1_0_1_3_reg_1850(8 - 1 downto 0);
grp_fu_938_p1 <= tmp_313_0_3_reg_1974(8 - 1 downto 0);
grp_fu_942_p0 <= tmp_1_0_2_3_reg_1888(8 - 1 downto 0);
grp_fu_942_p1 <= tmp_313_0_3_reg_1974(8 - 1 downto 0);
grp_fu_946_p0 <= tmp_1_0_3_3_reg_1897(8 - 1 downto 0);
grp_fu_946_p1 <= tmp_313_0_3_reg_1974(8 - 1 downto 0);
grp_fu_950_p0 <= tmp_1_0_4_3_reg_1926(8 - 1 downto 0);
grp_fu_950_p1 <= tmp_313_0_3_reg_1974(8 - 1 downto 0);
grp_fu_970_p0 <= tmp_1_0_0_3_reg_1841(8 - 1 downto 0);
grp_fu_970_p1 <= tmp_4_0_3_fu_966_p1(8 - 1 downto 0);
grp_fu_975_p0 <= tmp_1_0_1_3_reg_1850(8 - 1 downto 0);
grp_fu_975_p1 <= tmp_4_0_3_fu_966_p1(8 - 1 downto 0);
grp_fu_980_p0 <= tmp_1_0_2_3_reg_1888(8 - 1 downto 0);
grp_fu_980_p1 <= tmp_4_0_3_fu_966_p1(8 - 1 downto 0);
grp_fu_985_p0 <= tmp_1_0_3_3_reg_1897(8 - 1 downto 0);
grp_fu_985_p1 <= tmp_4_0_3_fu_966_p1(8 - 1 downto 0);
grp_fu_998_p1 <= tmp75_fu_990_p1(8 - 1 downto 0);
prod_address0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
prod_address0 <= ap_const_lv32_18(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
prod_address0 <= ap_const_lv32_16(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_15(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_13(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_11(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_F(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_D(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_B(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_9(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_7(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_5(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_3(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
prod_address0 <= ap_const_lv32_1(5 - 1 downto 0);
else
prod_address0 <= "XXXXX";
end if;
end process;
prod_address1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
prod_address1 <= ap_const_lv32_17(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_14(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_12(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_10(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_E(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_C(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_A(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_8(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_6(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_4(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_2(5 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
prod_address1 <= ap_const_lv32_0(5 - 1 downto 0);
else
prod_address1 <= "XXXXX";
end if;
end process;
prod_ce0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)))) then
prod_ce0 <= ap_const_logic_1;
else
prod_ce0 <= ap_const_logic_0;
end if;
end process;
prod_ce1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)))) then
prod_ce1 <= ap_const_logic_1;
else
prod_ce1 <= ap_const_logic_0;
end if;
end process;
prod_d0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage1, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, tmp_3_0_1_4_reg_2777, tmp_3_0_3_4_reg_2846, tmp_3_1_0_4_reg_2856, tmp_3_1_2_4_reg_2925, tmp_3_1_4_4_reg_2994, tmp_3_2_1_4_reg_3063, tmp_3_2_3_4_reg_3122, tmp_3_3_0_4_reg_3162, tmp_3_3_2_4_reg_3172, tmp_3_3_4_4_reg_3212, tmp_3_4_1_4_reg_3222, tmp_3_4_2_4_reg_3227, tmp_3_4_4_4_reg_3237, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage1_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
prod_d0 <= tmp_3_4_4_4_reg_3237;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
prod_d0 <= tmp_3_4_2_4_reg_3227;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_4_1_4_reg_3222;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_3_4_4_reg_3212;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_3_2_4_reg_3172;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_3_0_4_reg_3162;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_2_3_4_reg_3122;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_2_1_4_reg_3063;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_1_4_4_reg_2994;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_1_2_4_reg_2925;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_1_0_4_reg_2856;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_0_3_4_reg_2846;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
prod_d0 <= tmp_3_0_1_4_reg_2777;
else
prod_d0 <= "XXXXXXXXXXXXXXXX";
end if;
end process;
prod_d1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_CS_fsm_pp0_stage2, ap_CS_fsm_pp0_stage4, ap_CS_fsm_pp0_stage9, ap_CS_fsm_pp0_stage3, ap_CS_fsm_pp0_stage8, ap_CS_fsm_pp0_stage11, ap_CS_fsm_pp0_stage5, ap_CS_fsm_pp0_stage7, ap_CS_fsm_pp0_stage10, ap_CS_fsm_pp0_stage6, tmp_3_0_0_4_reg_2772, tmp_3_0_2_4_reg_2782, tmp_3_1_1_4_reg_2861, tmp_3_0_4_4_reg_2920, tmp_3_1_3_4_reg_2930, tmp_3_2_0_4_reg_2999, tmp_3_2_2_4_reg_3068, tmp_3_2_4_4_reg_3127, tmp_3_3_1_4_reg_3167, tmp_3_3_3_4_reg_3177, tmp_3_4_0_4_reg_3217, tmp_3_4_3_4_reg_3232, ap_block_pp0_stage0_flag00000000, ap_block_pp0_stage2_flag00000000, ap_block_pp0_stage3_flag00000000, ap_block_pp0_stage4_flag00000000, ap_block_pp0_stage5_flag00000000, ap_block_pp0_stage6_flag00000000, ap_block_pp0_stage7_flag00000000, ap_block_pp0_stage8_flag00000000, ap_block_pp0_stage9_flag00000000, ap_block_pp0_stage10_flag00000000, ap_block_pp0_stage11_flag00000000, ap_block_pp0_stage12_flag00000000)
begin
if (((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00000000 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2))) then
prod_d1 <= tmp_3_4_3_4_reg_3232;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage12_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_4_0_4_reg_3217;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage11_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_3_3_4_reg_3177;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage10_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_3_1_4_reg_3167;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage9_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_2_4_4_reg_3127;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage8_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_2_2_4_reg_3068;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage7_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_2_0_4_reg_2999;
elsif (((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_1_3_4_reg_2930;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage5_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_1_1_4_reg_2861;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage4_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_0_4_4_reg_2920;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage3_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_0_2_4_reg_2782;
elsif (((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_block_pp0_stage2_flag00000000 = ap_const_boolean_0))) then
prod_d1 <= tmp_3_0_0_4_reg_2772;
else
prod_d1 <= "XXXXXXXXXXXXXXXX";
end if;
end process;
prod_we0_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage1, ap_block_pp0_stage1_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage1) and (ap_block_pp0_stage1_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)))) then
prod_we0 <= ap_const_logic_1;
else
prod_we0 <= ap_const_logic_0;
end if;
end process;
prod_we1_assign_proc : process(ap_CS_fsm_pp0_stage0, ap_enable_reg_pp0_iter1, ap_enable_reg_pp0_iter2, ap_CS_fsm_pp0_stage12, ap_block_pp0_stage12_flag00011001, ap_CS_fsm_pp0_stage2, ap_block_pp0_stage2_flag00011001, ap_CS_fsm_pp0_stage4, ap_block_pp0_stage4_flag00011001, ap_CS_fsm_pp0_stage9, ap_block_pp0_stage9_flag00011001, ap_CS_fsm_pp0_stage3, ap_block_pp0_stage3_flag00011001, ap_CS_fsm_pp0_stage8, ap_block_pp0_stage8_flag00011001, ap_CS_fsm_pp0_stage11, ap_block_pp0_stage11_flag00011001, ap_CS_fsm_pp0_stage5, ap_block_pp0_stage5_flag00011001, ap_CS_fsm_pp0_stage7, ap_block_pp0_stage7_flag00011001, ap_CS_fsm_pp0_stage10, ap_block_pp0_stage10_flag00011001, ap_block_pp0_stage0_flag00011001, ap_CS_fsm_pp0_stage6, ap_block_pp0_stage6_flag00011001)
begin
if ((((ap_const_logic_1 = ap_CS_fsm_pp0_stage2) and (ap_block_pp0_stage2_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage3) and (ap_block_pp0_stage3_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage4) and (ap_block_pp0_stage4_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage5) and (ap_block_pp0_stage5_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_enable_reg_pp0_iter1) and (ap_const_logic_1 = ap_CS_fsm_pp0_stage6) and (ap_block_pp0_stage6_flag00011001 = ap_const_boolean_0)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage7) and (ap_block_pp0_stage7_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage8) and (ap_block_pp0_stage8_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage9) and (ap_block_pp0_stage9_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage10) and (ap_block_pp0_stage10_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage11) and (ap_block_pp0_stage11_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage12) and (ap_block_pp0_stage12_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter1)) or ((ap_const_logic_1 = ap_CS_fsm_pp0_stage0) and (ap_block_pp0_stage0_flag00011001 = ap_const_boolean_0) and (ap_const_logic_1 = ap_enable_reg_pp0_iter2)))) then
prod_we1 <= ap_const_logic_1;
else
prod_we1 <= ap_const_logic_0;
end if;
end process;
tmp75_fu_990_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_784),16));
tmp_0_0_1_fu_1107_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_784),16));
tmp_0_0_2_fu_1036_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_q0),16));
tmp_0_0_3_fu_805_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_764),16));
tmp_0_0_4_fu_922_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_q0),16));
tmp_111_0_1_fu_1155_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_764),16));
tmp_111_0_2_fu_1078_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_q0),16));
tmp_111_0_3_fu_829_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_779),16));
tmp_111_0_4_fu_934_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_q1),16));
tmp_1_0_0_1_fu_1111_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_769),16));
tmp_1_0_0_2_fu_1040_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_0_3_fu_809_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_769),16));
tmp_1_0_0_4_fu_926_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_1_1_fu_1115_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_774),16));
tmp_1_0_1_2_fu_1074_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_1_3_fu_819_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_774),16));
tmp_1_0_1_4_fu_930_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q1),16));
tmp_1_0_1_fu_1004_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_774),16));
tmp_1_0_2_1_fu_1119_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_792),16));
tmp_1_0_2_2_fu_1123_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_2_3_fu_845_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_769),16));
tmp_1_0_2_4_fu_954_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_2_fu_1014_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_792),16));
tmp_1_0_3_1_fu_1143_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_769),16));
tmp_1_0_3_2_fu_1147_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_3_3_fu_854_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_774),16));
tmp_1_0_3_4_fu_958_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q1),16));
tmp_1_0_3_fu_1044_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_load_15_reg_1964),16));
tmp_1_0_4_1_fu_1151_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q1),16));
tmp_1_0_4_2_fu_1183_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q0),16));
tmp_1_0_4_3_fu_873_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_774),16));
tmp_1_0_4_4_fu_1024_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_q1),16));
tmp_1_0_4_fu_1052_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(b_load_20_reg_1969),16));
tmp_1_fu_994_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_769),16));
tmp_212_0_1_fu_1187_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_788),16));
tmp_212_0_2_fu_1226_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_784),16));
tmp_212_0_3_fu_887_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_764),16));
tmp_212_0_4_fu_962_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_q0),16));
tmp_313_0_1_fu_1250_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_796),16));
tmp_313_0_2_fu_1277_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_load_17_reg_2660),16));
tmp_313_0_3_fu_913_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_779),16));
tmp_313_0_4_fu_1028_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_788),16));
tmp_3_0_0_4_fu_1214_p2 <= std_logic_vector(signed(tmp1_reg_2508) + signed(tmp_reg_2695));
tmp_3_0_1_4_fu_1218_p2 <= std_logic_vector(signed(tmp4_reg_2600) + signed(tmp3_reg_2700));
tmp_3_0_2_4_fu_1222_p2 <= std_logic_vector(signed(tmp7_reg_2710) + signed(tmp6_reg_2705));
tmp_3_0_3_4_fu_1238_p2 <= std_logic_vector(signed(tmp10_reg_2792) + signed(tmp9_reg_2787));
tmp_3_0_4_4_fu_1254_p2 <= std_logic_vector(signed(tmp13_reg_2851) + signed(tmp12_reg_2797));
tmp_3_1_0_4_fu_1242_p2 <= std_logic_vector(signed(tmp16_reg_2646) + signed(tmp15_reg_2802));
tmp_3_1_1_4_fu_1246_p2 <= std_logic_vector(signed(tmp19_reg_2744) + signed(tmp18_reg_2807));
tmp_3_1_2_4_fu_1258_p2 <= std_logic_vector(signed(tmp22_reg_2817) + signed(tmp21_reg_2866));
tmp_3_1_3_4_fu_1262_p2 <= std_logic_vector(signed(tmp25_reg_2876) + signed(tmp24_reg_2871));
tmp_3_1_4_4_fu_1269_p2 <= std_logic_vector(signed(tmp28_reg_2935) + signed(tmp27_reg_2881));
tmp_3_2_0_4_fu_1273_p2 <= std_logic_vector(signed(tmp31_reg_2940) + signed(tmp30_reg_2886));
tmp_3_2_1_4_fu_1280_p2 <= std_logic_vector(signed(tmp34_reg_3004) + signed(tmp33_reg_2945));
tmp_3_2_2_4_fu_1284_p2 <= std_logic_vector(signed(tmp37_reg_3009) + signed(tmp36_reg_2950));
tmp_3_2_3_4_fu_1292_p2 <= std_logic_vector(signed(tmp40_reg_3073) + signed(tmp39_reg_2955));
tmp_3_2_4_4_fu_1296_p2 <= std_logic_vector(signed(tmp43_reg_3078) + signed(tmp42_reg_2960));
tmp_3_3_0_4_fu_1300_p2 <= std_logic_vector(signed(tmp46_reg_3132) + signed(tmp45_reg_3023));
tmp_3_3_1_4_fu_1304_p2 <= std_logic_vector(signed(tmp49_reg_3137) + signed(tmp48_reg_3028));
tmp_3_3_2_4_fu_1308_p2 <= std_logic_vector(signed(tmp52_reg_3142) + signed(tmp51_reg_3033));
tmp_3_3_3_4_fu_1312_p2 <= std_logic_vector(signed(tmp55_reg_3147) + signed(tmp54_reg_3038));
tmp_3_3_4_4_fu_1316_p2 <= std_logic_vector(signed(tmp58_reg_3182) + signed(tmp57_reg_3083));
tmp_3_4_0_4_fu_1320_p2 <= std_logic_vector(signed(tmp61_reg_3187) + signed(tmp60_reg_3097));
tmp_3_4_1_4_fu_1324_p2 <= std_logic_vector(signed(tmp64_reg_3192) + signed(tmp63_reg_3102));
tmp_3_4_2_4_fu_1328_p2 <= std_logic_vector(signed(tmp67_reg_3197) + signed(tmp66_reg_3107));
tmp_3_4_3_4_fu_1332_p2 <= std_logic_vector(signed(tmp70_reg_3202) + signed(tmp69_reg_3152));
tmp_3_4_4_4_fu_1336_p2 <= std_logic_vector(signed(tmp73_reg_3207) + signed(tmp72_reg_3157));
tmp_3_fu_1094_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_796),16));
tmp_4_0_1_fu_1266_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(a_load_21_reg_2665),16));
tmp_4_0_2_fu_1288_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_800),16));
tmp_4_0_3_fu_966_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_788),16));
tmp_4_0_4_fu_1103_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_788),16));
tmp_4_fu_1195_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_800),16));
tmp_5_fu_1159_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_779),16));
tmp_s_fu_1060_p1 <= std_logic_vector(IEEE.numeric_std.resize(signed(reg_764),16));
end behav;
| mit | 7e9bddbdeb83e618cfcc4d7ed3c70f30 | 0.581837 | 2.733153 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-digilent-xc7z020/leon3mp.vhd | 1 | 23,831 | -----------------------------------------------------------------------------
-- LEON3 Zedboard Demonstration design
-- Copyright (C) 2012 Fredrik Ringhage, Aeroflex Gaisler
-- Modifed by Jiri Gaisler to provide working AXI interface, 2014-04-05
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.config.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false
);
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : inout std_logic;
processing_system7_0_PS_CLK : inout std_logic;
processing_system7_0_PS_PORB : inout std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : inout std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
component leon3_zedboard_stub
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end component;
constant maxahbm : integer := (CFG_LEON3*CFG_NCPU)+CFG_AHB_JTAG;
constant maxahbs : integer := 8;
constant maxapbs : integer := 16;
signal vcc, gnd : std_logic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rsti, rst : std_ulogic;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
constant BOARD_FREQ : integer := 83333; -- CLK0 frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ;
signal stati : ahbstat_in_type;
constant CIDSZ : integer := 6;
constant CLENSZ : integer := 4;
signal S_AXI_GP0_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_arcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_arid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_arlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_arlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_awqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_arready : STD_LOGIC;
signal S_AXI_GP0_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arvalid : STD_LOGIC;
signal S_AXI_GP0_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_awcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_awid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_awlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_awlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awready : STD_LOGIC;
signal S_AXI_GP0_awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awvalid : STD_LOGIC;
signal S_AXI_GP0_bid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_bready : STD_LOGIC;
signal S_AXI_GP0_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_bvalid : STD_LOGIC;
signal S_AXI_GP0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_rid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_rlast : STD_LOGIC;
signal S_AXI_GP0_rready : STD_LOGIC;
signal S_AXI_GP0_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_rvalid : STD_LOGIC;
signal S_AXI_GP0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_wlast : STD_LOGIC;
signal S_AXI_GP0_wready : STD_LOGIC;
signal S_AXI_GP0_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_wvalid : STD_LOGIC;
signal S_AXI_GP0_wid : STD_LOGIC_VECTOR ( 5 downto 0 ); --
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
reset_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech)
port map (button(0), rsti);
rstn <= rst and not rsti;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3_0 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
nocpu : if CFG_LEON3 = 0 generate dbgo(0) <= dbgo_none; end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= gpioi.din(0);
end generate;
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(0), dsuo.active);
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_LEON3*CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_LEON3*CFG_NCPU),
open, open, open, open, open, open, open, gnd);
end generate;
leon3_zedboard_stub_i : leon3_zedboard_stub
port map (
DDR_ck_p => processing_system7_0_DDR_Clk,
DDR_ck_n => processing_system7_0_DDR_Clk_n,
DDR_cke => processing_system7_0_DDR_CKE,
DDR_cs_n => processing_system7_0_DDR_CS_n,
DDR_ras_n => processing_system7_0_DDR_RAS_n,
DDR_cas_n => processing_system7_0_DDR_CAS_n,
DDR_we_n => processing_system7_0_DDR_WEB_pin,
DDR_ba => processing_system7_0_DDR_BankAddr,
DDR_addr => processing_system7_0_DDR_Addr,
DDR_odt => processing_system7_0_DDR_ODT,
DDR_reset_n => processing_system7_0_DDR_DRSTB,
DDR_dq => processing_system7_0_DDR_DQ,
DDR_dm => processing_system7_0_DDR_DM,
DDR_dqs_p => processing_system7_0_DDR_DQS,
DDR_dqs_n => processing_system7_0_DDR_DQS_n,
FCLK_CLK0 => clkm,
FCLK_RESET0_N => rst,
FIXED_IO_mio => processing_system7_0_MIO,
FIXED_IO_ps_srstb => processing_system7_0_PS_SRSTB,
FIXED_IO_ps_clk => processing_system7_0_PS_CLK,
FIXED_IO_ps_porb => processing_system7_0_PS_PORB,
FIXED_IO_ddr_vrn => processing_system7_0_DDR_VRN,
FIXED_IO_ddr_vrp => processing_system7_0_DDR_VRP,
S_AXI_GP0_araddr => S_AXI_GP0_araddr,
S_AXI_GP0_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
S_AXI_GP0_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
S_AXI_GP0_arid => S_AXI_GP0_arid,
S_AXI_GP0_arlen => S_AXI_GP0_arlen,
S_AXI_GP0_arlock => S_AXI_GP0_arlock,
S_AXI_GP0_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
S_AXI_GP0_arqos => S_AXI_GP0_arqos,
S_AXI_GP0_awqos => S_AXI_GP0_awqos,
S_AXI_GP0_arready => S_AXI_GP0_arready,
S_AXI_GP0_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
S_AXI_GP0_arvalid => S_AXI_GP0_arvalid,
S_AXI_GP0_awaddr => S_AXI_GP0_awaddr,
S_AXI_GP0_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
S_AXI_GP0_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
S_AXI_GP0_awid => S_AXI_GP0_awid,
S_AXI_GP0_awlen => S_AXI_GP0_awlen,
S_AXI_GP0_awlock => S_AXI_GP0_awlock,
S_AXI_GP0_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
S_AXI_GP0_awready => S_AXI_GP0_awready,
S_AXI_GP0_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
S_AXI_GP0_awvalid => S_AXI_GP0_awvalid,
S_AXI_GP0_bid => S_AXI_GP0_bid,
S_AXI_GP0_bready => S_AXI_GP0_bready,
S_AXI_GP0_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
S_AXI_GP0_bvalid => S_AXI_GP0_bvalid,
S_AXI_GP0_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
S_AXI_GP0_rid => S_AXI_GP0_rid,
S_AXI_GP0_rlast => S_AXI_GP0_rlast,
S_AXI_GP0_rready => S_AXI_GP0_rready,
S_AXI_GP0_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
S_AXI_GP0_rvalid => S_AXI_GP0_rvalid,
S_AXI_GP0_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
S_AXI_GP0_wid => S_AXI_GP0_wid,
S_AXI_GP0_wlast => S_AXI_GP0_wlast,
S_AXI_GP0_wready => S_AXI_GP0_wready,
S_AXI_GP0_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
S_AXI_GP0_wvalid => S_AXI_GP0_wvalid
);
ahb2axi0 : entity work.ahb2axi
generic map(
hindex => 3, haddr => 16#400#, hmask => 16#F00#,
pindex => 0, paddr => 0, cidsz => CIDSZ, clensz => CLENSZ)
port map(
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(3),
apbi => apbi,
apbo => apbo(0),
M_AXI_araddr => S_AXI_GP0_araddr,
M_AXI_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
M_AXI_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
M_AXI_arid => S_AXI_GP0_arid,
M_AXI_arlen => S_AXI_GP0_arlen,
M_AXI_arlock => S_AXI_GP0_arlock,
M_AXI_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
M_AXI_arqos => S_AXI_GP0_arqos,
M_AXI_arready => S_AXI_GP0_arready,
M_AXI_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
M_AXI_arvalid => S_AXI_GP0_arvalid,
M_AXI_awaddr => S_AXI_GP0_awaddr,
M_AXI_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
M_AXI_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
M_AXI_awid => S_AXI_GP0_awid,
M_AXI_awlen => S_AXI_GP0_awlen,
M_AXI_awlock => S_AXI_GP0_awlock,
M_AXI_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
M_AXI_awqos => S_AXI_GP0_awqos,
M_AXI_awready => S_AXI_GP0_awready,
M_AXI_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
M_AXI_awvalid => S_AXI_GP0_awvalid,
M_AXI_bid => S_AXI_GP0_bid,
M_AXI_bready => S_AXI_GP0_bready,
M_AXI_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
M_AXI_bvalid => S_AXI_GP0_bvalid,
M_AXI_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
M_AXI_rid => S_AXI_GP0_rid,
M_AXI_rlast => S_AXI_GP0_rlast,
M_AXI_rready => S_AXI_GP0_rready,
M_AXI_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
M_AXI_rvalid => S_AXI_GP0_rvalid,
M_AXI_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
M_AXI_wlast => S_AXI_GP0_wlast,
M_AXI_wready => S_AXI_GP0_wready,
M_AXI_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
M_AXI_wvalid => S_AXI_GP0_wvalid
);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqgen : if CFG_LEON3 = 1 generate
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
end generate;
irqctrl : if (CFG_IRQ3_ENABLE + CFG_LEON3) /= 2 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => 0)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 8 to 10 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (button(i-8+1), gpioi.din(i));
end generate;
pio_pads3 : for i in 11 to 14 generate
pio_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (led(i-11+4), gpioo.dout(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
hready_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(2), ahbmi.hready);
rsti_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(3), rsti);
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
end generate;
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (maxahbs+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx Zedboard Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | bea9cc4dae7f326d1d978cf8a3c27891 | 0.569804 | 3.244962 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.ip_user_files/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_0/sim/zqynq_lab_1_design_axi_gpio_1_0.vhd | 1 | 9,004 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
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-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
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-- rights to the materials distributed herewith. Except as
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-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_15;
USE axi_gpio_v2_0_15.axi_gpio;
ENTITY zqynq_lab_1_design_axi_gpio_1_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END zqynq_lab_1_design_axi_gpio_1_0;
ARCHITECTURE zqynq_lab_1_design_axi_gpio_1_0_arch OF zqynq_lab_1_design_axi_gpio_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_gpio_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 5,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zqynq_lab_1_design_axi_gpio_1_0_arch;
| mit | aecfd67f58015f0cfb296a1c64464a82 | 0.681364 | 3.221467 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/maps/ddr_ireg.vhd | 1 | 2,926 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ddr_ireg
-- File: ddr_ireg.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: DDR input reg with tech selection
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.allddr.all;
entity ddr_ireg is
generic ( tech : integer; arch : integer := 0);
port ( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end;
architecture rtl of ddr_ireg is
begin
inf : if not((is_unisim(tech) = 1) or (tech = axcel) or
(tech = axdsp) or (tech = apa3) or (tech = apa3e) or
(tech = apa3l) or (tech = rhumc)) generate
inf0 : gen_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
ax : if (tech = axcel) or (tech = axdsp) generate
axc0 : axcel_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
pa3 : if (tech = apa3) generate
pa0 : apa3_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
pa3e : if (tech = apa3e) generate
pa0 : apa3e_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
pa3l : if (tech = apa3l) generate
pa0 : apa3l_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
xil : if is_unisim(tech) = 1 generate
xil0 : unisim_iddr_reg generic map (tech, arch) port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
rhu : if (tech = rhumc) generate
rhu0: rhumc_iddr_reg port map (Q1, Q2, C1, C2, CE, D, R, S);
end generate;
--pragma translate_off
assert (tech /= easic45) and (tech /= easic90)
report "ddr_ireg: Not supported on eASIC. Use DDR pad instead."
severity failure;
--pragma translate_on
end architecture;
| gpl-2.0 | 67ef6bad13f26830a687e65dccb71b68 | 0.594327 | 3.410256 | false | false | false | false |
kloboves/sicxe | vhdl/gio_device.vhd | 1 | 4,795 | library ieee;
use ieee.std_logic_1164.all;
entity gio_device is
Port (
clock_i : in std_logic;
reset_i : in std_logic;
-- device access
switches_data_o : out std_logic_vector(7 downto 0);
buttons_data_o : out std_logic_vector(7 downto 0);
event_o : out std_logic;
data_i : in std_logic_vector(7 downto 0);
write_leds_i : std_logic;
-- physical connections
leds_o : out std_logic_vector(7 downto 0);
switches_i : in std_logic_vector(7 downto 0);
buttons_i : in std_logic_vector(1 downto 0)
);
end gio_device;
architecture behavioral of gio_device is
component debouncer
Port (
clock_i : in std_logic;
reset_i : in std_logic;
input_i : in std_logic;
output_o : out std_logic;
change_on_o : out std_logic;
change_off_o : out std_logic
);
end component;
-- leds
signal reg_leds : std_logic_vector(7 downto 0);
-- switches and buttons
signal switches : std_logic_vector(7 downto 0);
signal buttons : std_logic_vector(1 downto 0);
-- events
signal switches_event1 : std_logic_vector(7 downto 0);
signal switches_event2 : std_logic_vector(7 downto 0);
signal buttons_event1 : std_logic_vector(1 downto 0);
signal buttons_event2 : std_logic_vector(1 downto 0);
begin
leds_proc : process(clock_i)
begin
if (rising_edge(clock_i)) then
if (reset_i = '1') then
reg_leds <= (others => '0');
else
if (write_leds_i = '1') then
reg_leds <= data_i;
else
reg_leds <= reg_leds;
end if;
end if;
end if;
end process;
leds_o <= reg_leds;
switches_data_o <= switches;
buttons_data_o <= "000000" & buttons;
event_o <= switches_event1(0) or switches_event1(1) or
switches_event1(2) or switches_event1(3) or
switches_event1(4) or switches_event1(5) or
switches_event1(6) or switches_event1(7) or
switches_event2(0) or switches_event2(1) or
switches_event2(2) or switches_event2(3) or
switches_event2(4) or switches_event2(5) or
switches_event2(6) or switches_event2(7) or
buttons_event1(0) or buttons_event1(1) or
buttons_event2(0) or buttons_event2(1);
sw0_debounce_cmpt : debouncer
port map (
clock_i => clock_i,
reset_i => reset_i,
input_i => switches_i(0),
output_o => switches(0),
change_on_o => switches_event1(0),
change_off_o => switches_event2(0)
);
sw1_debounce_cmpt : debouncer
port map (
clock_i => clock_i,
reset_i => reset_i,
input_i => switches_i(1),
output_o => switches(1),
change_on_o => switches_event1(1),
change_off_o => switches_event2(1)
);
sw2_debounce_cmpt : debouncer
port map (
clock_i => clock_i,
reset_i => reset_i,
input_i => switches_i(2),
output_o => switches(2),
change_on_o => switches_event1(2),
change_off_o => switches_event2(2)
);
sw3_debounce_cmpt : debouncer
port map (
clock_i => clock_i,
reset_i => reset_i,
input_i => switches_i(3),
output_o => switches(3),
change_on_o => switches_event1(3),
change_off_o => switches_event2(3)
);
sw4_debounce_cmpt : debouncer
port map (
clock_i => clock_i,
reset_i => reset_i,
input_i => switches_i(4),
output_o => switches(4),
change_on_o => switches_event1(4),
change_off_o => switches_event2(4)
);
sw5_debounce_cmpt : debouncer
port map (
clock_i => clock_i,
reset_i => reset_i,
input_i => switches_i(5),
output_o => switches(5),
change_on_o => switches_event1(5),
change_off_o => switches_event2(5)
);
sw6_debounce_cmpt : debouncer
port map (
clock_i => clock_i,
reset_i => reset_i,
input_i => switches_i(6),
output_o => switches(6),
change_on_o => switches_event1(6),
change_off_o => switches_event2(6)
);
sw7_debounce_cmpt : debouncer
port map (
clock_i => clock_i,
reset_i => reset_i,
input_i => switches_i(7),
output_o => switches(7),
change_on_o => switches_event1(7),
change_off_o => switches_event2(7)
);
btn0_debounce_cmpt : debouncer
port map (
clock_i => clock_i,
reset_i => reset_i,
input_i => buttons_i(0),
output_o => buttons(0),
change_on_o => buttons_event1(0),
change_off_o => buttons_event2(0)
);
btn1_debounce_cmpt : debouncer
port map (
clock_i => clock_i,
reset_i => reset_i,
input_i => buttons_i(1),
output_o => buttons(1),
change_on_o => buttons_event1(1),
change_off_o => buttons_event2(1)
);
end behavioral;
| mit | 3447dcd8f27fe11a603510be1662db78 | 0.5756 | 3.1692 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/misc/ahbram.vhd | 1 | 9,173 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: ahbram
-- File: ahbram.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Jan Andersson - Aeroflex Gaisler
-- Description: AHB ram. 0-waitstate read, 0/1-waitstate write.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
entity ahbram is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
tech : integer := DEFMEMTECH;
kbytes : integer := 1;
pipe : integer := 0;
maccsz : integer := AHBDW;
scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbram is
constant abits : integer := log2ext(kbytes) + 8 - maccsz/64;
constant dw : integer := maccsz;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBRAM, 0, abits+2+maccsz/64, 0),
4 => ahb_membar(haddr, '1', '1', hmask),
others => zero32);
type reg_type is record
hwrite : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
addr : std_logic_vector(abits-1+log2(dw/8) downto 0);
size : std_logic_vector(2 downto 0);
prdata : std_logic_vector((dw-1)*pipe downto 0);
pwrite : std_ulogic;
pready : std_ulogic;
end record;
constant RESET_ALL : boolean := GRLIB_CONFIG_ARRAY(grlib_sync_reset_enable_all) = 1;
constant RES : reg_type :=
(hwrite => '0', hready => '1', hsel => '0', addr => (others => '0'),
size => (others => '0'), prdata => (others => '0'), pwrite => '0',
pready => '1');
signal r, c : reg_type;
signal ramsel : std_logic_vector(dw/8-1 downto 0);
signal write : std_logic_vector(dw/8-1 downto 0);
signal ramaddr : std_logic_vector(abits-1 downto 0);
signal ramdata : std_logic_vector(dw-1 downto 0);
signal hwdata : std_logic_vector(dw-1 downto 0);
begin
comb : process (ahbsi, r, rst, ramdata)
variable bs : std_logic_vector(dw/8-1 downto 0);
variable v : reg_type;
variable haddr : std_logic_vector(abits-1 downto 0);
variable hrdata : std_logic_vector(dw-1 downto 0);
variable seldata : std_logic_vector(dw-1 downto 0);
variable raddr : std_logic_vector(3 downto 2);
variable adsel : std_logic;
begin
v := r; v.hready := '1'; bs := (others => '0');
v.pready := r.hready;
if pipe=0 then
adsel := r.hwrite or not r.hready;
else
adsel := r.hwrite or r.pwrite;
v.hready := r.hready or not r.pwrite;
end if;
if adsel = '1' then
haddr := r.addr(abits-1+log2(dw/8) downto log2(dw/8));
else
haddr := ahbsi.haddr(abits-1+log2(dw/8) downto log2(dw/8));
bs := (others => '0');
end if;
raddr := (others => '0');
v.pwrite := '0';
if pipe/=0 and (r.hready='1' or r.pwrite='0') then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
if ahbsi.hready = '1' then
if pipe=0 then
v.addr := ahbsi.haddr(abits-1+log2(dw/8) downto 0);
end if;
v.hsel := ahbsi.hsel(hindex) and ahbsi.htrans(1);
v.size := ahbsi.hsize(2 downto 0);
v.hwrite := ahbsi.hwrite and v.hsel;
if pipe = 1 and v.hsel = '1' and ahbsi.hwrite = '0' and (r.pready='1' or ahbsi.htrans(0)='0') then
v.hready := '0';
v.pwrite := r.hwrite;
end if;
end if;
if r.hwrite = '1' then
case r.size is
when HSIZE_BYTE =>
bs(bs'left-conv_integer(r.addr(log2(dw/16) downto 0))) := '1';
when HSIZE_HWORD =>
for i in 0 to dw/16-1 loop
if i = conv_integer(r.addr(log2(dw/16) downto 1)) then
bs(bs'left-i*2 downto bs'left-i*2-1) := (others => '1');
end if;
end loop; -- i
when HSIZE_WORD =>
if dw = 32 then bs := (others => '1');
else
for i in 0 to dw/32-1 loop
if i = conv_integer(r.addr(log2(dw/8)-1 downto 2)) then
bs(bs'left-i*4 downto bs'left-i*4-3) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_DWORD =>
if dw = 32 then null;
elsif dw = 64 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when HSIZE_4WORD =>
if dw < 128 then null;
elsif dw = 128 then bs := (others => '1');
else
for i in 0 to dw/64-1 loop
if i = conv_integer(r.addr(3)) then
bs(bs'left-i*8 downto bs'left-i*8-7) := (others => '1');
end if;
end loop; -- i
end if;
when others => --HSIZE_8WORD
if dw < 256 then null;
else bs := (others => '1'); end if;
end case;
v.hready := not (v.hsel and not ahbsi.hwrite);
v.hwrite := v.hwrite and v.hready;
end if;
-- Duplicate read data on word basis, unless CORE_ACDM is enabled
if CORE_ACDM = 0 then
if dw = 32 then
seldata := ramdata;
elsif dw = 64 then
if r.size = HSIZE_DWORD then seldata := ramdata; else
if r.addr(2) = '0' then
seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else
seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0);
end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
end if;
elsif dw = 128 then
if r.size = HSIZE_4WORD then
seldata := ramdata;
elsif r.size = HSIZE_DWORD then
if r.addr(3) = '0' then seldata(dw/2-1 downto 0) := ramdata(dw-1 downto dw/2);
else seldata(dw/2-1 downto 0) := ramdata(dw/2-1 downto 0); end if;
seldata(dw-1 downto dw/2) := seldata(dw/2-1 downto 0);
else
raddr := r.addr(3 downto 2);
case raddr is
when "00" => seldata(dw/4-1 downto 0) := ramdata(4*dw/4-1 downto 3*dw/4);
when "01" => seldata(dw/4-1 downto 0) := ramdata(3*dw/4-1 downto 2*dw/4);
when "10" => seldata(dw/4-1 downto 0) := ramdata(2*dw/4-1 downto 1*dw/4);
when others => seldata(dw/4-1 downto 0) := ramdata(dw/4-1 downto 0);
end case;
seldata(dw-1 downto dw/4) := seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0) &
seldata(dw/4-1 downto 0);
end if;
else
seldata := ahbselectdata(ramdata, r.addr(4 downto 2), r.size);
end if;
else
seldata := ramdata;
end if;
if pipe = 0 then
v.prdata := (others => '0');
hrdata := seldata;
else
v.prdata := seldata;
hrdata := r.prdata;
end if;
if (not RESET_ALL) and (rst = '0') then
v.hwrite := RES.hwrite; v.hready := RES.hready;
end if;
write <= bs; for i in 0 to dw/8-1 loop ramsel(i) <= v.hsel or r.hwrite; end loop;
ramaddr <= haddr; c <= v;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hready <= r.hready;
end process;
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
-- Select correct write data
hwdata <= ahbreaddata(ahbsi.hwdata, r.addr(4 downto 2),
conv_std_logic_vector(log2(dw/8), 3));
aram : syncrambw generic map (tech, abits, dw, scantest) port map (
clk, ramaddr, hwdata, ramdata, ramsel, write, ahbsi.testin);
reg : process (clk)
begin
if rising_edge(clk) then
r <= c;
if RESET_ALL and rst = '0' then
r <= RES;
end if;
end if;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbram" & tost(hindex) &
": AHB SRAM Module rev 1, " & tost(kbytes) & " kbytes");
-- pragma translate_on
end;
| gpl-2.0 | 45e4d52ddd41e6ae952fa1ae41dd8b2b | 0.555216 | 3.36377 | false | false | false | false |
dawsonjon/FPGA-TX | synthesis/nexys_4/tx/lfsr.vhd | 3 | 643 | library ieee;
use ieee.std_logic_1164.all;
entity lfsr is
generic(
init : in std_logic_vector(63 downto 0) := X"0000000000000001"
);
port(
clk : in std_logic;
rand : out std_logic_vector(31 downto 0)
);
end entity lfsr;
architecture rtl of lfsr is
signal shifter : std_logic_vector(63 downto 0) := init;
begin
process
begin
wait until rising_edge(clk);
if shifter(0) = '1' then
shifter <= ('0' & shifter(63 downto 1)) xor (X"d800000000000000");
else
shifter <= ('0' & shifter(63 downto 1));
end if;
rand <= shifter(63 downto 32) xor shifter(31 downto 0);
end process;
end rtl;
| mit | 1e650f8d29eaaf013f24d4f8dc916999 | 0.634526 | 3.331606 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/gaisler/greth/greth_mb.vhd | 1 | 13,884 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_mb
-- File: greth_mb.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link and dual AHB master interfaces
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greth_mb is
generic(
hindex : integer := 0;
ehindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahb : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbmi2 : in ahb_mst_in_type;
ahbmo2 : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ethi : in eth_in_type;
etho : out eth_out_type
);
end entity;
architecture rtl of greth_mb is
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
constant fabits : integer := log2(fifosize);
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant eabits : integer := log2(edclbufsz) + 8;
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant REVISION : amba_version_type := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_ETHMAC, 0, revision, 0),
others => zero32);
constant ehconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_EDCLMST, 0, REVISION, 0),
others => zero32);
signal irq : std_ulogic;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
signal lmdio_oe : std_ulogic;
-- Fix for wider bus
signal hwdata : std_logic_vector(31 downto 0);
signal hrdata : std_logic_vector(31 downto 0);
signal ehwdata : std_logic_vector(31 downto 0);
signal ehrdata : std_logic_vector(31 downto 0);
begin
ethc0: grethc
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
oepol => oepol,
scanen => scanen,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
edclsepahbg => edclsepahb,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => rst,
clk => clk,
--ahb mst in
hgrant => ahbmi.hgrant(hindex),
hready => ahbmi.hready,
hresp => ahbmi.hresp,
hrdata => hrdata,
--ahb mst out
hbusreq => ahbmo.hbusreq,
hlock => ahbmo.hlock,
htrans => ahbmo.htrans,
haddr => ahbmo.haddr,
hwrite => ahbmo.hwrite,
hsize => ahbmo.hsize,
hburst => ahbmo.hburst,
hprot => ahbmo.hprot,
hwdata => hwdata,
--edcl ahb mst in
ehgrant => ahbmi2.hgrant(ehindex),
ehready => ahbmi2.hready,
ehresp => ahbmi2.hresp,
ehrdata => ehrdata,
--edcl ahb mst out
ehbusreq => ahbmo2.hbusreq,
ehlock => ahbmo2.hlock,
ehtrans => ahbmo2.htrans,
ehaddr => ahbmo2.haddr,
ehwrite => ahbmo2.hwrite,
ehsize => ahbmo2.hsize,
ehburst => ahbmo2.hburst,
ehprot => ahbmo2.hprot,
ehwdata => ehwdata,
--apb slv in
psel => apbi.psel(pindex),
penable => apbi.penable,
paddr => apbi.paddr,
pwrite => apbi.pwrite,
pwdata => apbi.pwdata,
--apb slv out
prdata => apbo.prdata,
--irq
irq => irq,
--rx ahb fifo
rxrenable => rxrenable,
rxraddress => rxraddress,
rxwrite => rxwrite,
rxwdata => rxwdata,
rxwaddress => rxwaddress,
rxrdata => rxrdata,
--tx ahb fifo
txrenable => txrenable,
txraddress => txraddress,
txwrite => txwrite,
txwdata => txwdata,
txwaddress => txwaddress,
txrdata => txrdata,
--edcl buf
erenable => erenable,
eraddress => eraddress,
ewritem => ewritem,
ewritel => ewritel,
ewaddressm => ewaddressm,
ewaddressl => ewaddressl,
ewdata => ewdata,
erdata => erdata,
--ethernet input signals
rmii_clk => ethi.rmii_clk,
tx_clk => ethi.tx_clk,
tx_dv => ethi.tx_dv,
rx_clk => ethi.rx_clk,
rxd => ethi.rxd(3 downto 0),
rx_dv => ethi.rx_dv,
rx_er => ethi.rx_er,
rx_col => ethi.rx_col,
rx_crs => ethi.rx_crs,
rx_en => ethi.rx_en,
mdio_i => ethi.mdio_i,
phyrstaddr => ethi.phyrstaddr,
mdint => ethi.mdint,
--ethernet output signals
reset => etho.reset,
txd => etho.txd(3 downto 0),
tx_en => etho.tx_en,
tx_er => etho.tx_er,
mdc => etho.mdc,
mdio_o => etho.mdio_o,
mdio_oe => lmdio_oe,
--scantest
testrst => ahbmi.testrst,
testen => ahbmi.testen,
testoen => ahbmi.testoen,
edcladdr => ethi.edcladdr,
edclsepahb => ethi.edclsepahb,
edcldisable => ethi.edcldisable);
etho.mdio_oe <= ahbmi.testoen when (scanen = 1) and (ahbmi.testen = '1')
else lmdio_oe;
irqdrv : process(irq)
begin
apbo.pirq <= (others => '0');
apbo.pirq(pirq) <= irq;
end process;
hrdata <= ahbreadword(ahbmi.hrdata);
ahbmo.hwdata <= ahbdrivedata(hwdata);
ahbmo.hconfig <= hconfig;
ahbmo.hindex <= hindex;
ahbmo.hirq <= (others => '0');
ehrdata <= ahbreadword(ahbmi2.hrdata);
ahbmo2.hwdata <= ahbdrivedata(ehwdata);
ahbmo2.hconfig <= ehconfig;
ahbmo2.hindex <= ehindex;
ahbmo2.hirq <= (others => '0');
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-------------------------------------------------------------------------------
-- FIFOS ----------------------------------------------------------------------
-------------------------------------------------------------------------------
nft : if ft = 0 generate
tx_fifo0 : syncram_2p generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2p generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
ft1 : if ft /= 0 generate
tx_fifo0 : syncram_2pft generic map(tech => memtech, abits => txfabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, txrenable, txraddress(txfabits-1 downto 0), txrdata, clk,
txwrite, txwaddress(txfabits-1 downto 0), txwdata);
rx_fifo0 : syncram_2pft generic map(tech => memtech, abits => fabits,
dbits => 32, sepclk => 0, ft => ft)
port map(clk, rxrenable, rxraddress(fabits-1 downto 0), rxrdata, clk,
rxwrite, rxwaddress(fabits-1 downto 0), rxwdata);
end generate;
-------------------------------------------------------------------------------
-- EDCL buffer ram ------------------------------------------------------------
-------------------------------------------------------------------------------
edclramnft : if (edcl /= 0) and (edclft = 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
edclramft1 : if (edcl /= 0) and (edclft /= 0) generate
r0 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(31 downto 16), clk,
ewritem, ewaddressm(eabits-1 downto 0), ewdata(31 downto 16));
r1 : syncram_2p generic map (memtech, eabits, 16, 0, 0, ft) port map(
clk, erenable, eraddress(eabits-1 downto 0), erdata(15 downto 0), clk,
ewritel, ewaddressl(eabits-1 downto 0), ewdata(15 downto 0));
end generate;
-- pragma translate_off
bootmsg : report_version
generic map (
"greth" & tost(hindex) & ": 10/100 Mbit Ethernet MAC rev " & tost(REVISION)
& tost(hindex) & ", EDCL " & tost(edcl) & ", buffer " &
tost(edclbufsz) & " kbyte " & tost(txfifosize) & " txfifo," &
" irq " & tost(pirq)
);
-- pragma translate_on
end architecture;
| gpl-2.0 | 2931bbd7e9a204591bfc3bcd42aa467d | 0.537165 | 4.083529 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-altera-c5ekit/pllsim.vhd | 1 | 1,440 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
entity syspll1 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end;
architecture sim of syspll1 is
begin
p: process
variable vclk: std_logic := '0';
begin
outclk_0 <= vclk;
wait for 5.555 ns;
vclk := not vclk;
end process;
locked <= '0', '1' after 1 us;
end;
| gpl-2.0 | f2cfc261f44cd0cbccfb2a9429ca4250 | 0.63125 | 3.870968 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/techmap/umc18/pads_umc18.vhd | 1 | 8,514 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: umcpads_gen
-- File: umcpads_gen.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: UMC pad wrappers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package umcpads is
-- input pad
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-up
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
-- input pad with pull-down
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
-- schmitt input pad
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
-- output pads
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
-- tri-state output pads
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
-- bidirectional pads
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.ICMT3V;
use umc18.ICMT3VPU;
use umc18.ICMT3VPD;
use umc18.ISTRT3V;
-- pragma translate_on
entity umc_inpad is
generic (level : integer := 0; voltage : integer := 0; filter : integer := 0);
port (pad : in std_logic; o : out std_logic);
end;
architecture rtl of umc_inpad is
component ICMT3V port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPU port( A : in std_logic; Z : out std_logic); end component;
component ICMT3VPD port( A : in std_logic; Z : out std_logic); end component;
component ISTRT3V port( A : in std_logic; Z : out std_logic); end component;
begin
norm : if filter = 0 generate
ip : ICMT3V port map (a => pad, z => o);
end generate;
pu : if filter = pullup generate
ip : ICMT3VPU port map (a => pad, z => o);
end generate;
pd : if filter = pulldown generate
ip : ICMT3VPD port map (a => pad, z => o);
end generate;
sch : if filter = schmitt generate
ip : ISTRT3V port map (a => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.BICM3V4;
use umc18.BICM3V12;
use umc18.BICM3V24;
-- pragma translate_on
entity umc_iopad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : inout std_logic; i, en : in std_logic; o : out std_logic);
end ;
architecture rtl of umc_iopad is
component BICM3V4 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V12 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component BICM3V24 port( IO : inout std_logic; EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : BICM3V4 port map (a => i, en => en, io => pad, z => o);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : BICM3V12 port map (a => i, en => en, io => pad, z => o);
end generate;
f24 : if (strength > 16) generate
op : BICM3V24 port map (a => i, en => en, io => pad, z => o);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCM3V4;
use umc18.OCM3V12;
use umc18.OCM3V24;
-- pragma translate_on
entity umc_outpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i : in std_logic);
end ;
architecture rtl of umc_outpad is
component OCM3V4 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V12 port( Z : out std_logic; A : in std_logic); end component;
component OCM3V24 port( Z : out std_logic; A : in std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCM3V4 port map (a => i, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCM3V12 port map (a => i, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCM3V24 port map (a => i, z => pad);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library umc18;
use umc18.OCMTR4;
use umc18.OCMTR12;
use umc18.OCMTR24;
-- pragma translate_on
entity umc_toutpad is
generic (level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 0);
port (pad : out std_logic; i, en : in std_logic);
end ;
architecture rtl of umc_toutpad is
component OCMTR4 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR12 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
component OCMTR24 port( EN : in std_logic; A : in std_logic; Z : out std_logic); end component;
begin
f4 : if (strength <= 4) generate
op : OCMTR4 port map (a => i, en => en, z => pad);
end generate;
f12 : if (strength > 4) and (strength <= 12) generate
op : OCMTR12 port map (a => i, en => en, z => pad);
end generate;
f24 : if (strength > 12) generate
op : OCMTR24 port map (a => i, en => en, z => pad);
end generate;
end;
library umc18;
-- pragma translate_off
use umc18.LVDS_Driver;
use umc18.LVDS_Receiver;
use umc18.LVDS_Biasmodule;
-- pragma translate_on
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity umc_lvds_combo is
generic (voltage : integer := 0; width : integer := 1);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
lvdsref : in std_logic);
end ;
architecture rtl of umc_lvds_combo is
component LVDS_Driver port ( A, Vref, HI : in std_logic; Z, ZN : out std_logic); end component;
component LVDS_Receiver port ( A, AN : in std_logic; Z : out std_logic); end component;
component LVDS_Biasmodule port ( RefR : in std_logic; Vref, HI : out std_logic); end component;
signal vref, hi : std_logic;
begin
lvds_bias: LVDS_Biasmodule port map (lvdsref, vref, hi);
swloop : for i in 0 to width-1 generate
spw_rxd_pad : LVDS_Receiver port map (idpadp(i), idpadn(i), idval(i));
spw_rxs_pad : LVDS_Receiver port map (ispadp(i), ispadn(i), isval(i));
spw_txd_pad : LVDS_Driver port map (odval(i), vref, hi, odpadp(i), odpadn(i));
spw_txs_pad : LVDS_Driver port map (osval(i), vref, hi, ospadp(i), ospadn(i));
end generate;
end;
| gpl-2.0 | 48785d6c497b4db452c1992848a21056 | 0.653512 | 3.253344 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/designs/leon3-avnet-3s1500/leon3mp.vhd | 1 | 26,269 | -----------------------------------------------------------------------------
-- LEON3 Demonstration design for AVNET Spartan3 Evaluation Board
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.pci.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.can.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
mezz : integer := CFG_ADS_DAU_MEZZ
);
port (
clk_66mhz : in std_logic;
clk_socket : in std_logic;
leds : out std_logic_vector(7 downto 0);
switches : in std_logic_vector(5 downto 0);
sram_a : out std_logic_vector(24 downto 0);
sram_ben_l : out std_logic_vector(0 to 3);
sram_cs_l : out std_logic_vector(1 downto 0);
sram_oe_l : out std_logic;
sram_we_l : out std_logic;
sram_dq : inout std_logic_vector(31 downto 0);
flash_cs_l : out std_logic;
flash_rst_l : out std_logic;
iosn : out std_logic;
sdclk : out std_logic;
rasn : out std_logic;
casn : out std_logic;
sdcke : out std_logic;
sdcsn : out std_logic;
tx : out std_logic;
rx : in std_logic;
can_txd : out std_logic;
can_rxd : in std_logic;
phy_txck : in std_logic;
phy_rxck : in std_logic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxdv : in std_logic;
phy_rxer : in std_logic;
phy_col : in std_logic;
phy_crs : in std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txen : out std_logic;
phy_txer : out std_logic;
phy_mdc : out std_logic;
phy_mdio : inout std_logic; -- ethernet PHY interface
phy_reset_l : inout std_logic;
video_clk : in std_logic;
comp_sync : out std_logic;
horiz_sync : out std_logic;
vert_sync : out std_logic;
blank : out std_logic;
video_out : out std_logic_vector(23 downto 0);
msclk : inout std_logic;
msdata : inout std_logic;
kbclk : inout std_logic;
kbdata : inout std_logic;
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant mahbmax : integer := CFG_NCPU+CFG_AHB_UART+CFG_PCI+
CFG_SVGA_ENABLE + CFG_GRETH+CFG_AHB_JTAG;
signal vcc, gnd : std_logic_vector(23 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal abus : std_logic_vector(17 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clk, rstn, rstraw, pciclk, sdclkl : std_logic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal tck, tms, tdi, tdo : std_logic;
signal pllref, errorn, pci_rst : std_logic;
signal pci_arb_req_n, pci_arb_gnt_n : std_logic_vector(0 to 3);
signal dac_clk, clk25, clk_66mhzl, pci_lclk : std_logic;
signal can_ltx, can_lrx : std_logic;
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clk : signal is true;
attribute syn_preserve of clk : signal is true;
attribute keep of clk : signal is true;
signal switchesl : std_logic_vector(5 downto 0);
constant padlevel : integer := 0;
constant IOAEN : integer := CFG_CAN;
constant BOARD_FREQ : integer := 66667; -- input frequency in KHz
constant CPU_FREQ : integer := (BOARD_FREQ * CFG_CLKMUL) / CFG_CLKDIV;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
---------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0'); pllref <= '0';
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= pllref;
clkgen0 : clkgen -- clock generator
generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
CFG_CLK_NOFB, CFG_PCI, CFG_PCIDLL, CFG_PCISYSCLK, 66000)
port map (clk_66mhzl, pci_lclk, clk, open, open, sdclkl, pciclk, cgi, cgo);
sdclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 8)
port map (sdclk, sdclkl);
clk_pad : clkpad generic map (tech => padtech, level => padlevel)
port map (clk_66mhz, clk_66mhzl);
clk2_pad : clkpad generic map (tech => padtech, level => padlevel)
port map (clk_socket, open);
pci_clk_pad : clkpad generic map (tech => padtech, level => pci33)
port map (pci_clk, pci_lclk);
rst0 : rstgen generic map (acthigh => 1)
port map (switchesl(4), clk, cgo.clklock, rstn, rstraw);
flash_rst_l_pad : outpad generic map (level => padlevel, tech => padtech)
port map (flash_rst_l, rstraw);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
nahbm => mahbmax, nahbs => 8, ioen => IOAEN)
port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1, 0, 0,
CFG_MMU_PAGE, CFG_BP)
port map (clk, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clk, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
end generate;
dsui.break <= switchesl(5);
dsui.enable <= '1';
dsuact_pad : outpad generic map (tech => padtech, level => padlevel)
port map (leds(1), dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clk, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clk, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
dcompads : if CFG_AHB_UART = 1 generate
dsurx_pad : inpad generic map (tech => padtech, level => padlevel)
port map (rx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech, level => padlevel)
port map (tx, duo.txd);
u1i.rxd <= '1';
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : entity work.mctrl_avnet generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4, sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK,
pageburst => CFG_MCTRL_PAGE, avnetmezz => mezz)
port map (rstn, clk, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
sdpads : if CFG_MCTRL_SDEN = 1 generate -- no SDRAM controller
-- sdwen_pad : outpad generic map (tech => padtech)
-- port map (sdwen, sdo.sdwen);
sdras_pad : outpad generic map (tech => padtech)
port map (rasn, sdo.rasn);
sdcas_pad : outpad generic map (tech => padtech)
port map (casn, sdo.casn);
-- sddqm_pad : outpadv generic map (width =>4, tech => padtech)
-- port map (sddqm, sdo.dqm);
end generate;
sdcke_pad : outpad generic map (tech => padtech)
port map (sdcke, sdo.sdcke(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdcsn, sdo.sdcsn(0));
end generate;
nosd0 : if (CFG_MCTRL_SDEN = 0) generate -- no SDRAM controller
sdcke_pad : outpad generic map (tech => padtech)
port map (sdcke, vcc(0));
sdcsn_pad : outpad generic map (tech => padtech)
port map (sdcsn, vcc(0));
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- None PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rams_pad : outpadv generic map (level => padlevel, tech => padtech, width => 2)
port map (sram_cs_l, vcc(1 downto 0));
end generate;
mgpads : if CFG_MCTRL_LEON2 /= 0 generate -- prom/sram pads
addr_pad : outpadv generic map (level => padlevel, width => 25, tech => padtech)
port map (sram_a, memo.address(24 downto 0));
rams_pad : outpadv generic map (level => padlevel, tech => padtech, width => 2)
port map (sram_cs_l, memo.ramsn(1 downto 0));
flash_pad : outpad generic map (level => padlevel, tech => padtech)
port map (flash_cs_l, memo.romsn(0));
oen_pad : outpad generic map (level => padlevel, tech => padtech)
port map (sram_oe_l, memo.oen);
iosn_pad : outpad generic map (level => padlevel, tech => padtech)
port map (iosn, memo.iosn);
wri_pad : outpad generic map (level => padlevel, tech => padtech)
port map (sram_we_l, memo.writen);
bdr : for i in 0 to 3 generate
data_pad : iopadv generic map (level => padlevel, tech => padtech, width => 8)
port map (sram_dq(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
end generate;
ben_pad : outpadv generic map (level => padlevel, width => 4, tech => padtech)
port map (sram_ben_l, memo.mben);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clk, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clk, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua1pads : if CFG_AHB_UART = 0 generate
rx_pad : inpad generic map (tech => padtech, level => padlevel)
port map (rx, u1i.rxd);
tx_pad : outpad generic map (tech => padtech, level => padlevel)
port map (tx, u1o.txd);
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clk, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clk, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clk, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clk, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate
apbo(4) <= apb_none; mouo <= ps2o_none;
apbo(5) <= apb_none; kbdo <= ps2o_none;
end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (kbclk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (kbdata, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (msclk,mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (msdata, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clk, clk25, apbi, apbo(6), vgao);
vgaclk0 : entity techmap.clkmul_virtex2 generic map (3, 8) -- 25 MHz video clock
port map (rstn, clk, dac_clk, open);
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 39722, clk1 => 0, clk2 => 0, clk3 => 0, burstlen => 5)
port map(rstn, clk, clk25, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
clk25 <= not dac_clk;
end generate;
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
video_clk_pad : inpad generic map (tech => padtech)
port map (video_clk, dac_clk);
blank_pad : outpad generic map (tech => padtech)
port map (blank, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (comp_sync, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vert_sync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (horiz_sync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (video_out(23 downto 16), vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (video_out(15 downto 8), vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (video_out(7 downto 0), vgao.video_out_b);
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
-----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_gr0 : if CFG_PCI = 1 generate -- simple target-only
pci0 : pci_target generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
device_id => CFG_PCIDID, vendor_id => CFG_PCIVID)
port map (rstn, clk, pciclk, pcii, pcio, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE));
end generate;
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech, hmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 4, pindex => 9, paddr => 9, haddr => 16#E00#,
ioaddr => 16#400#, nsync => 2)
port map (rstn, clk, pciclk, pcii, pcio, apbi, apbo(9),
ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), ahbsi, ahbso(4));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech, dmstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1+CFG_SVGA_ENABLE,
dapbndx => 5, dapbaddr => 5, blength => blength, mstndx => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 4, apbndx => 9, apbaddr => 9, haddr => 16#E00#, ioaddr => 16#800#,
nsync => 1)
port map (rstn, clk, pciclk, pcii, pcio, apbo(9), ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+1+CFG_SVGA_ENABLE),
apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE), ahbsi, ahbso(4));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 8, paddr => 16#100#, pmask => 16#f00#)
port map ( rstn, clk, pciclk, pcii, apbi, apbo(8));
end generate;
end generate;
pcipads0 : pcipads
generic map (padtech => padtech, noreset => 1, host => 0)-- PCI pads
port map ( pci_rst, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr,
pci_par, pci_req, pci_serr, pci_host, pci_66, pcii, pcio );
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : greth generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL)
port map( rst => rstn, clk => clk, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG+CFG_SVGA_ENABLE), apbi => apbi,
apbo => apbo(11), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 0) generate -- no eth
etho <= eth_out_none;
end generate;
emdio_pad : iopad generic map (tech => padtech, level => padlevel)
port map (phy_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, level => padlevel, arch => 1)
port map (phy_txck, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, level => padlevel, arch => 1)
port map (phy_rxck, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, level => padlevel, width => 4)
port map (phy_rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_rxdv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_rxer, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech, level => padlevel)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, level => padlevel, width => 4)
port map (phy_txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech, level => padlevel)
port map ( phy_txen, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech, level => padlevel)
port map (phy_txer, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech, level => padlevel)
port map (phy_mdc, etho.mdc);
phy_reset_pad : iodpad generic map (tech => padtech, level => padlevel)
port map (phy_reset_l, rstn, pci_rst);
can0 : if CFG_CAN = 1 generate
can0 : can_oc generic map (slvndx => 6, ioaddr => CFG_CANIO,
iomask => 16#FF0#, irq => CFG_CANIRQ, memtech => memtech)
port map (rstn, clk, ahbsi, ahbso(6), can_lrx, can_ltx );
can_tx_pad : outpad generic map (tech => padtech)
port map (can_txd, can_ltx);
can_rx_pad : inpad generic map (tech => padtech)
port map (can_rxd, can_lrx);
end generate;
ncan : if CFG_CAN = 0 generate ahbso(6) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clk, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Misc ----------------------------------------------------------
-----------------------------------------------------------------------
errorn <= not dbgo(0).error;
led0_pad : outpad generic map (level => padlevel, tech => padtech)
port map (leds(0), errorn);
led2_7_pad : outpadv generic map (level => padlevel, width => 6, tech => padtech)
port map (leds(7 downto 2), gnd(5 downto 0));
disp_seg1_pad : outpadv generic map (level => padlevel, width => 8, tech => padtech)
port map (disp_seg1, gnd(7 downto 0));
disp_seg2_pad : outpadv generic map (level => padlevel, width => 8, tech => padtech)
port map (disp_seg2, gnd(7 downto 0));
switche_pad : inpadv generic map (tech => padtech, level => padlevel, width => 6)
port map (switches, switchesl);
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_PCI+ CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
nam2 : if CFG_PCI > 1 generate
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_PCI+CFG_AHB_JTAG-1+CFG_SVGA_ENABLE) <= ahbm_none;
end generate;
nap0 : for i in 12 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet Spartan3-1500 Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
| gpl-2.0 | 9b70460d1bea883585c72c8a0aaef154 | 0.582017 | 3.421334 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab2/ug871-design-files/Interface_Synthesis/lab2/adders_io_prj/solution1/syn/vhdl/adders_io.vhd | 1 | 11,467 | -- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.2
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity adders_io is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
in1 : IN STD_LOGIC_VECTOR (31 downto 0);
in1_ap_vld : IN STD_LOGIC;
in2 : IN STD_LOGIC_VECTOR (31 downto 0);
in2_ap_ack : OUT STD_LOGIC;
in_out1_i : IN STD_LOGIC_VECTOR (31 downto 0);
in_out1_i_ap_vld : IN STD_LOGIC;
in_out1_i_ap_ack : OUT STD_LOGIC;
in_out1_o : OUT STD_LOGIC_VECTOR (31 downto 0);
in_out1_o_ap_vld : OUT STD_LOGIC;
in_out1_o_ap_ack : IN STD_LOGIC );
end;
architecture behav of adders_io is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"adders_io,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=2.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=1.728000,HLS_SYN_LAT=1,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=302,HLS_SYN_LUT=154}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_fsm_state1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_ST_fsm_state2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal ap_CS_fsm : STD_LOGIC_VECTOR (1 downto 0) := "01";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_CS_fsm_state1 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state1 : signal is "none";
signal in1_preg : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal in1_in_sig : STD_LOGIC_VECTOR (31 downto 0);
signal in1_ap_vld_preg : STD_LOGIC := '0';
signal in1_ap_vld_in_sig : STD_LOGIC;
signal in1_blk_n : STD_LOGIC;
signal in_out1_i_blk_n : STD_LOGIC;
signal in_out1_o_blk_n : STD_LOGIC;
signal ap_CS_fsm_state2 : STD_LOGIC;
attribute fsm_encoding of ap_CS_fsm_state2 : signal is "none";
signal in_out1_read_reg_68 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_block_state1 : BOOLEAN;
signal tmp1_fu_57_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp1_reg_73 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_reg_ioackin_in_out1_o_ap_ack : STD_LOGIC := '0';
signal ap_sig_ioackin_in_out1_o_ap_ack : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (1 downto 0);
begin
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_fsm_state1;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
ap_reg_ioackin_in_out1_o_ap_ack_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ioackin_in_out1_o_ap_ack <= ap_const_logic_0;
else
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
if ((ap_sig_ioackin_in_out1_o_ap_ack = ap_const_logic_1)) then
ap_reg_ioackin_in_out1_o_ap_ack <= ap_const_logic_0;
elsif ((ap_const_logic_1 = in_out1_o_ap_ack)) then
ap_reg_ioackin_in_out1_o_ap_ack <= ap_const_logic_1;
end if;
end if;
end if;
end if;
end process;
in1_ap_vld_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
in1_ap_vld_preg <= ap_const_logic_0;
else
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_sig_ioackin_in_out1_o_ap_ack = ap_const_logic_1))) then
in1_ap_vld_preg <= ap_const_logic_0;
elsif (((ap_const_logic_1 = in1_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
in1_ap_vld_preg <= in1_ap_vld;
end if;
end if;
end if;
end process;
in1_preg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
in1_preg <= ap_const_lv32_0;
else
if (((ap_const_logic_1 = in1_ap_vld) and not(((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))))) then
in1_preg <= in1;
end if;
end if;
end if;
end process;
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = in1_ap_vld_in_sig) or (ap_const_logic_0 = in_out1_i_ap_vld))))) then
in_out1_read_reg_68 <= in_out1_i;
tmp1_reg_73 <= tmp1_fu_57_p2;
end if;
end if;
end process;
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, ap_CS_fsm_state1, in1_ap_vld_in_sig, in_out1_i_ap_vld, ap_CS_fsm_state2, ap_sig_ioackin_in_out1_o_ap_ack)
begin
case ap_CS_fsm is
when ap_ST_fsm_state1 =>
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = in1_ap_vld_in_sig) or (ap_const_logic_0 = in_out1_i_ap_vld))))) then
ap_NS_fsm <= ap_ST_fsm_state2;
else
ap_NS_fsm <= ap_ST_fsm_state1;
end if;
when ap_ST_fsm_state2 =>
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_sig_ioackin_in_out1_o_ap_ack = ap_const_logic_1))) then
ap_NS_fsm <= ap_ST_fsm_state1;
else
ap_NS_fsm <= ap_ST_fsm_state2;
end if;
when others =>
ap_NS_fsm <= "XX";
end case;
end process;
ap_CS_fsm_state1 <= ap_CS_fsm(0);
ap_CS_fsm_state2 <= ap_CS_fsm(1);
ap_block_state1_assign_proc : process(ap_start, in1_ap_vld_in_sig, in_out1_i_ap_vld)
begin
ap_block_state1 <= ((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = in1_ap_vld_in_sig) or (ap_const_logic_0 = in_out1_i_ap_vld));
end process;
ap_done_assign_proc : process(ap_CS_fsm_state2, ap_sig_ioackin_in_out1_o_ap_ack)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_sig_ioackin_in_out1_o_ap_ack = ap_const_logic_1))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
ap_idle_assign_proc : process(ap_start, ap_CS_fsm_state1)
begin
if (((ap_const_logic_0 = ap_start) and (ap_const_logic_1 = ap_CS_fsm_state1))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
ap_ready_assign_proc : process(ap_CS_fsm_state2, ap_sig_ioackin_in_out1_o_ap_ack)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_sig_ioackin_in_out1_o_ap_ack = ap_const_logic_1))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_sig_ioackin_in_out1_o_ap_ack_assign_proc : process(in_out1_o_ap_ack, ap_reg_ioackin_in_out1_o_ap_ack)
begin
if ((ap_const_logic_0 = ap_reg_ioackin_in_out1_o_ap_ack)) then
ap_sig_ioackin_in_out1_o_ap_ack <= in_out1_o_ap_ack;
else
ap_sig_ioackin_in_out1_o_ap_ack <= ap_const_logic_1;
end if;
end process;
in1_ap_vld_in_sig_assign_proc : process(in1_ap_vld, in1_ap_vld_preg)
begin
if ((ap_const_logic_1 = in1_ap_vld)) then
in1_ap_vld_in_sig <= in1_ap_vld;
else
in1_ap_vld_in_sig <= in1_ap_vld_preg;
end if;
end process;
in1_blk_n_assign_proc : process(ap_start, ap_CS_fsm_state1, in1_ap_vld)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
in1_blk_n <= in1_ap_vld;
else
in1_blk_n <= ap_const_logic_1;
end if;
end process;
in1_in_sig_assign_proc : process(in1, in1_preg, in1_ap_vld)
begin
if ((ap_const_logic_1 = in1_ap_vld)) then
in1_in_sig <= in1;
else
in1_in_sig <= in1_preg;
end if;
end process;
in2_ap_ack_assign_proc : process(ap_start, ap_CS_fsm_state1, in1_ap_vld_in_sig, in_out1_i_ap_vld)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = in1_ap_vld_in_sig) or (ap_const_logic_0 = in_out1_i_ap_vld))))) then
in2_ap_ack <= ap_const_logic_1;
else
in2_ap_ack <= ap_const_logic_0;
end if;
end process;
in_out1_i_ap_ack_assign_proc : process(ap_start, ap_CS_fsm_state1, in1_ap_vld_in_sig, in_out1_i_ap_vld)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and not(((ap_const_logic_0 = ap_start) or (ap_const_logic_0 = in1_ap_vld_in_sig) or (ap_const_logic_0 = in_out1_i_ap_vld))))) then
in_out1_i_ap_ack <= ap_const_logic_1;
else
in_out1_i_ap_ack <= ap_const_logic_0;
end if;
end process;
in_out1_i_blk_n_assign_proc : process(ap_start, ap_CS_fsm_state1, in_out1_i_ap_vld)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state1) and (ap_start = ap_const_logic_1))) then
in_out1_i_blk_n <= in_out1_i_ap_vld;
else
in_out1_i_blk_n <= ap_const_logic_1;
end if;
end process;
in_out1_o <= std_logic_vector(unsigned(tmp1_reg_73) + unsigned(in_out1_read_reg_68));
in_out1_o_ap_vld_assign_proc : process(ap_CS_fsm_state2, ap_reg_ioackin_in_out1_o_ap_ack)
begin
if (((ap_const_logic_1 = ap_CS_fsm_state2) and (ap_const_logic_0 = ap_reg_ioackin_in_out1_o_ap_ack))) then
in_out1_o_ap_vld <= ap_const_logic_1;
else
in_out1_o_ap_vld <= ap_const_logic_0;
end if;
end process;
in_out1_o_blk_n_assign_proc : process(in_out1_o_ap_ack, ap_CS_fsm_state2)
begin
if ((ap_const_logic_1 = ap_CS_fsm_state2)) then
in_out1_o_blk_n <= in_out1_o_ap_ack;
else
in_out1_o_blk_n <= ap_const_logic_1;
end if;
end process;
tmp1_fu_57_p2 <= std_logic_vector(unsigned(in2) + unsigned(in1_in_sig));
end behav;
| mit | 2a0a9b3df50d11d06880527c88a41330 | 0.544345 | 2.901569 | false | false | false | false |
schmr/grlib | grlib-gpl-1.3.7-b4144/lib/grlib/amba/dma2ahb.vhd | 1 | 25,629 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
--============================================================================--
-- Design unit : DMA2AHB (Entity & architecture declarations)
--
-- File name : dma2ahb.vhd
--
-- Purpose : AMBA AHB master interface with DMA input
--
-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
-- 13th May 1999, issue A, first release, ARM Limited
-- The document can be retrieved from http://www.arm.com
-- AMBA is a trademark of ARM Limited.
-- ARM is a registered trademark of ARM Limited.
--
-- Note : Naming convention according to AMBA(TM) Specification:
-- Signal names are in upper case, except for the following:
-- A lower case 'n' in the name indicates that the signal
-- is active low.
-- Constant names are in upper case.
-- The least significant bit of an array is located to the right,
-- carrying the index number zero.
--
-- Limitations : The AMBA AHB interface has been reduced in function to support
-- only what is required. The following features are constrained:
-- Optionally generates HSIZE=BYTE, HWORD and WORD
-- Only generates HPROT="0011"
-- Allways generates HBURST=HBURST_SINGLE, HBURST_INCR
-- Optionally generates HBURST_INCR4, HBURST_INCR8, HBURST_INCR16
--
-- Generates the following on reponses on DMA interface:
-- HRESP=HRESP_OKAY => DMAOut.Ready
-- HRESP=HRESP_ERROR => DMAOut.Fault
-- HRESP=HRESP_RETRY => DMAOut.Retry (normally not used)
-- HRESP=HRESP_SPLIT => DMAOut.Retry (normally not used)
--
-- Assumes pipelined data input (after OKAY asserted).
--
-- Only big-endianness is supported.
--
-- Supports Early Bus Termination with automatic restart.
-- Supports Retry/Split with automatic restart.
--
-- Library : gaisler
--
-- Authors : Aeroflex Gaisler AB
--
-- Contact : mailto:[email protected]
-- http://www.gaisler.com
--
-- Disclaimer : All information is provided "as is", there is no warranty that
-- the information is correct or suitable for any purpose,
-- neither implicit nor explicit.
--
--------------------------------------------------------------------------------
-- Version Author Date Changes
--
-- 0.1 SH 1 Jul 2003 New version
-- 0.2 SH 21 Jul 2003 Combinatorial response introduced
-- 0.3 SH 25 Jan 2004 Support for interrupted bursts introduced
-- (early burst termination)
-- Optimised coding
-- Idle transfer initiated in 1st error phase
-- 1.3 SH 1 Oct 2004 Ported to GRLIB
-- 1.4 SH 1 Jul 2005 Support for fixed length incrementing bursts
-- Support for record types
-- 1.5 SH 1 Sep 2005 New library gaisler
-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
-- 1.6 SH 1 Nov 2005 DMAOut.Grant asserted only while HREADY high
-- 1.8 SH 10 Nov 2005 Re-ported to GRLIB
-- 1.8.1 SH 12 Dec 2005 Ensured no HTRANS=seq occurs after idle
-- 1.9 SH 1 Jan 2006 Resolve retry/early burst termination
-- 1.9.2 SH 3 Jan 2006 DelDataPhase dealyed with HREADY signal
-- 1.9.3 SH 24 Feb 2006 Added syncrst generic
-- 1.9.4 MI 27 Mar 2007 Driving HSIZE with address
-- 1.9.5 SH 14 Dec 2007 Automatic 1kbyte boundary crossing (merged)
-- 1.9.6 JA 14 Dec 2007 Support for halfword and byte bursts
-- 1.9.7 MI 4 Aug 2008 Support for Lock
-- 1.9.8 SH 16 Apr 2009 Address recovery after SPLIT/RETRY moved
-- 1.9.9 SH 9 Oct 2009 HPROT defult to 0x3
-- 2.0 SH 4 Mar 2011 DMAOut.Grant masked while ReAddrPhase set
--------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library GRLIB;
use GRLIB.AMBA.all;
use GRLIB.STDLIB.all;
use GRLIB.DMA2AHB_Package.all;
entity DMA2AHB is
generic(
hindex: in Integer := 0;
vendorid: in Integer := 0;
deviceid: in Integer := 0;
version: in Integer := 0;
syncrst: in Integer := 1;
boundary: in Integer := 1);
port(
-- AMBA AHB system signals
HCLK: in Std_ULogic; -- system clock
HRESETn: in Std_ULogic; -- asynchronous reset
-- Direct Memory Access Interface
DMAIn: in DMA_In_Type;
DMAOut: out DMA_OUt_Type;
-- AMBA AHB Master Interface
AHBIn: in AHB_Mst_In_Type;
AHBOut: out AHB_Mst_Out_Type);
end entity DMA2AHB;
--============================== Architecture ================================--
architecture RTL of DMA2AHB is
--=========================================================================--
-- Configuration GRLIB
-----------------------------------------------------------------------------
constant HConfig: AHB_Config_Type := (
0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
others => (others => '0'));
--=========================================================================--
-----------------------------------------------------------------------------
-- Local signals
-----------------------------------------------------------------------------
signal Address: Std_Logic_Vector(31 downto 0);
signal AddressSave: Std_Logic_Vector(31 downto 0);
signal ActivePhase: Std_ULogic; -- ongoing access
signal AddressPhase: Std_ULogic; -- address phase
signal DataPhase: Std_ULogic; -- data phase
signal ReDataPhase: Std_ULogic; -- restart first
signal ReAddrPhase: Std_ULogic; -- restart second
signal IdlePhase: Std_ULogic; -- idle phase
signal EarlyPhase: Std_ULogic; -- early termination
signal BoundaryPhase: Std_ULogic; -- boundary crossing
signal SingleAcc: Std_ULogic; -- single access
signal WriteAcc: Std_ULogic; -- write access
signal DelDataPhase: Std_ULogic; -- restart first
signal DelAddrPhase: Std_ULogic; -- restart second
signal AHBInHGRANTx: Std_ULogic; -- decoded grant
begin
--=========================================================================--
-- AMBA AHB master interface
-----------------------------------------------------------------------------
AHBOut.HIRQ <= (others => '0');
AHBOut.HCONFIG <= HConfig;
AHBOut.HINDEX <= hindex;
AHBInHGRANTx <= AHBIn.HGRANT(hindex);
--=========================================================================--
-----------------------------------------------------------------------------
-- AMBA AHB Master interface with fast issuing of accesses
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Fixed AMBA AHB signals
-----------------------------------------------------------------------------
AHBOut.HPROT <= "0011";
-----------------------------------------------------------------------------
-- Combinatorial paths
-----------------------------------------------------------------------------
AHBOut.HADDR <= Address; -- internal to external
AHBOut.HWDATA <= ahbdrivedata(DMAIn.Data); -- combinatorial path
DMAOut.OKAY <= '1' when AHBIn.HREADY='1' and
DataPhase ='1' and
AHBIN.HRESP=HRESP_OKAY else
'0';
DMAOut.Retry <= '1' when AHBIn.HREADY='0' and
DataPhase ='1' and
(AHBIN.HRESP=HRESP_RETRY or
AHBIN.HRESP=HRESP_SPLIT) else
'0';
DMAOut.Fault <= '1' when AHBIn.HREADY='0' and
DataPhase ='1' and
AHBIN.HRESP=HRESP_ERROR else
'0';
DMAOut.Grant <= '0' when ReDataPhase='1' or ReAddrPhase='1' else
'1' when AHBIn.HREADY='1' and
AHBInHGRANTx='1' and
DMAIn.Request='1' else
'0';
AHBOut.HBUSREQ <= '0' when IdlePhase='1' else
'1' when DMAIn.Request='1' else
'1' when DMAIn.Burst='1' else
'1' when ReDataPhase='1' else
'1' when ReAddrPhase='1' else
'0';
AHBOut.HLOCK <= '0' when IdlePhase='1' else
'1' when (DMAIn.Lock and
(DMAIn.Request or ReDataPhase)) = '1'else
'0';
-----------------------------------------------------------------------------
-- The AMBA AHB interfacing is done in this process
-----------------------------------------------------------------------------
AHBMaster: process(HCLK, HRESETn)
variable BoundaryCrossing: Std_ULogic;
variable AddressInc: Std_Logic_Vector(3 downto 0);
--------------------------------------------------------------------------
-- This procedure is used to define all reset values for the
-- asynchronous or synchronous reset statements in this process. This
-- is done to avoid source code duplication.
--------------------------------------------------------------------------
procedure Reset is
begin
ActivePhase <= '0';
EarlyPhase <= '0';
AddressPhase <= '0';
DataPhase <= '0';
ReDataPhase <= '0';
ReAddrPhase <= '0';
DelDataPhase <= '0';
DelAddrPhase <= '0';
BoundaryPhase <= '0';
IdlePhase <= '0';
EarlyPhase <= '0';
SingleAcc <= '0';
WriteAcc <= '0';
Address <= (others => '0');
AddressSave <= (others => '0');
DMAOut.Ready <= '0';
DMAOut.Data <= (others => '0');
AHBOut.HSIZE <= HSIZE_BYTE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HWRITE <= '0';
end Reset; ---------------------------------------------------------------
begin
if HRESETn='0' and syncrst=0 then -- asynchronous reset
Reset;
elsif Rising_Edge(HCLK) then
if DMAIn.Reset='1' or -- functional reset
(syncrst/=0 and HRESETn='0') then -- synchronous reset
Reset;
else -- no reset
--------------------------------------------------------------------
-- Temporary variables
--------------------------------------------------------------------
BoundaryCrossing := '0';
AddressInc := (others => '0');
--------------------------------------------------------------------
-- AMBA AHB interface - data phase handling
--------------------------------------------------------------------
-- indicate when no more activies are pending
if AddressPhase='0' and DataPhase='0' and
ReDataPhase='0' and ReAddrPhase='0' and
DMAIn.Burst='0' then
ActivePhase <= '0';
end if;
if AHBIn.HREADY='0' and DataPhase='1' then
-- error check
if AHBIN.HRESP=HRESP_ERROR then
DataPhase <= '0'; -- data phase aborted
end if;
-- split or retry check
if AHBIN.HRESP=HRESP_SPLIT or
AHBIN.HRESP=HRESP_RETRY then
ReDataPhase <= DataPhase; -- restart phases
ReAddrPhase <= AddressPhase or ReAddrPhase;
AddressPhase <= '0'; -- addr phase aborted
DataPhase <= '0'; -- data phase aborted
end if;
end if;
if AHBIn.HREADY='1' and DataPhase='1' then
-- sample AHB input data at end of data phase
DMAOut.Data <= ahbreadword(AHBIn.HRDATA);
DataPhase <= '0'; -- data phase ends
DMAOut.Ready <= '1';
else
-- remove acknowledgement after one cycle
DMAOut.Ready <= '0';
end if;
--------------------------------------------------------------------
-- AMBA AHB interface - address phase handling
--------------------------------------------------------------------
-- initialize data phase on AHB after previous address phase
if AddressPhase='1' and AHBIn.HREADY='1' then
DataPhase <= '1'; -- data phase start
end if;
-- address generation on AHB
if AHBIn.HREADY='1' then
if AddressPhase='1' then
-- burst continuation, sequential transfer
AddressInc(conv_integer(DMAIn.Size)) := '1';
if boundary=1 then -- automatic boundary
Address <= Address + AddressInc;
AddressSave <= Address;
if Address(9 downto 2)="11111111" then
BoundaryCrossing := '1';
BoundaryPhase <= '1';
end if;
else
Address(31 downto 10) <= DMAIn.Address(31 downto 10);
Address( 9 downto 0) <= Address(9 downto 0) + AddressInc;
AddressSave(9 downto 0) <= Address(9 downto 0);
end if;
if DMAIn.Size=HSIZE8 then
AHBOut.HSIZE <= HSIZE_BYTE;
elsif DMAIn.Size=HSIZE16 then
AHBOut.HSIZE <= HSIZE_HWORD;
else
AHBOut.HSIZE <= HSIZE_WORD;
end if;
elsif AHBInHGRANTx='1' and ActivePhase='0' and DMAIn.Request='1' then
-- start of burst, non-sequential transfer
-- start of single, non-sequential transfer
if boundary=1 then -- automatic boundary
Address <= DMAIn.Address;
AddressSave <= DMAIn.Address;
BoundaryCrossing := '0';
BoundaryPhase <= '0';
else
Address <= DMAIn.Address;
AddressSave(9 downto 0) <= DMAIn.Address(9 downto 0);
end if;
if DMAIn.Size=HSIZE8 then
AHBOut.HSIZE <= HSIZE_BYTE;
elsif DMAIn.Size=HSIZE16 then
AHBOut.HSIZE <= HSIZE_HWORD;
else
AHBOut.HSIZE <= HSIZE_WORD;
end if;
end if;
end if;
-- address generation on AHB
if AHBIn.HREADY='1' then
IdlePhase <= '0'; -- one clock cycle only
end if;
-- initialize address phase on AHB
if AHBIn.HREADY='1' then
-- granted the AHB bus
if AHBInHGRANTx='1' then
if ReDataPhase='1' then
ReDataPhase <= '0';
AddressPhase <= '1'; -- address phase start
EarlyPhase <= '0';
AHBOut.HTRANS <= HTRANS_NONSEQ;
if SingleAcc='1' then
AHBOut.HBURST <= HBURST_SINGLE;
else
AHBOut.HBURST <= HBURST_INCR;
end if;
AHBOut.HWRITE <= WriteAcc;
-- go back with address
if boundary=1 then
Address <= AddressSave;
else
Address(9 downto 0) <= AddressSave(9 downto 0);
end if;
elsif ReAddrPhase='1' then
AddressPhase <= '1'; -- address phase start
ReAddrPhase <= '0';
if AddressPhase='1' then
if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then
-- new bursts, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
BoundaryPhase <= '0';
else
-- burst continuation, sequential transfer
AHBOut.HTRANS <= HTRANS_SEQ;
end if;
else
AHBOut.HTRANS <= HTRANS_NONSEQ;
end if;
EarlyPhase <= '0';
if SingleAcc='1' then
AHBOut.HBURST <= HBURST_SINGLE;
else
AHBOut.HBURST <= HBURST_INCR;
end if;
AHBOut.HWRITE <= WriteAcc;
elsif EarlyPhase='1' then
-- early terminated burst resumed
AddressPhase <= '1'; -- address phase start
EarlyPhase <= '0';
AHBOut.HTRANS <= HTRANS_NONSEQ;
AHBOut.HBURST <= HBURST_INCR;
AHBOut.HWRITE <= WriteAcc;
elsif DMAIn.Request='1' and DMAIn.Burst='1' then
AddressPhase <= '1'; -- address phase start
if ActivePhase='1' then
-- burst continuation, sequential transfer
if boundary=1 and (BoundaryCrossing='1' or BoundaryPhase='1') then
-- new bursts, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
BoundaryPhase <= '0';
else
-- burst continuation, sequential transfer
AHBOut.HTRANS <= HTRANS_SEQ;
end if;
else
-- start of burst, non-sequential transfer
AHBOut.HTRANS <= HTRANS_NONSEQ;
if DMAIn.Beat ="00" then
AHBOut.HBURST <= HBURST_INCR;
elsif DMAIn.Beat ="01" then
AHBOut.HBURST <= HBURST_INCR4;
elsif DMAIn.Beat ="10" then
AHBOut.HBURST <= HBURST_INCR8;
else
AHBOut.HBURST <= HBURST_INCR16;
end if;
AHBOut.HWRITE <= DMAIn.Store;
ActivePhase <= '1';
SingleAcc <= '0';
WriteAcc <= DMAIn.Store;
end if;
elsif DMAIn.Request='0' and DMAIn.Burst='1' and ActivePhase='1' then
-- burst in wait state
AddressPhase <= '0'; -- no address phase
AHBOut.HTRANS <= HTRANS_BUSY;
elsif DMAIn.Request='1' and DMAIn.Burst='0' then
-- start of single, non-sequential transfer
AddressPhase <= '1'; -- address phase start
ActivePhase <= '1';
SingleAcc <= '1';
WriteAcc <= DMAIn.Store;
AHBOut.HTRANS <= HTRANS_NONSEQ;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= DMAIn.Store;
else
-- drive idle transfer as default master
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
-- not granted the AHB bus, but early burst termination
elsif (DMAIn.Request='1' or DMAIn.Burst='1') and ActivePhase='1'then
-- must restart a burst transfer since grant removed
AddressPhase <= '0'; -- no address phase
EarlyPhase <= '1';
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
-- not granted the AHB bus
else
-- drive idle transfer as default master
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
elsif AHBIn.HREADY='0' and DataPhase='1' then
if AHBIN.HRESP=HRESP_ERROR or
AHBIN.HRESP=HRESP_SPLIT or
AHBIN.HRESP=HRESP_RETRY then
-- drive idle transfer due to error, retry or split
-- the next cycle will start the address phase
AddressPhase <= '0'; -- no useful address
IdlePhase <= '1';
AHBOut.HTRANS <= HTRANS_IDLE;
AHBOut.HBURST <= HBURST_SINGLE;
AHBOut.HWRITE <= '0';
end if;
end if;
end if;
if AHBIn.HREADY='1' then -- delay one phase
DelDataPhase <= ReDataPhase;
DelAddrPhase <= ReAddrPhase;
end if;
-- temporary variables cleared
BoundaryCrossing := '0';
AddressInc := (others => '0');
else
null;
end if;
end process AHBMaster;
end architecture RTL; --======================================================--
| gpl-2.0 | 9c1853aeebd1bbd55b82666ca12a1061 | 0.405907 | 5.677669 | false | false | false | false |
MarkBlanco/FPGA_Sandbox | RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_gpio_1_1/synth/zqynq_lab_1_design_axi_gpio_1_1.vhd | 1 | 9,956 | -- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 15
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_15;
USE axi_gpio_v2_0_15.axi_gpio;
ENTITY zqynq_lab_1_design_axi_gpio_1_1 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END zqynq_lab_1_design_axi_gpio_1_1;
ARCHITECTURE zqynq_lab_1_design_axi_gpio_1_1_arch OF zqynq_lab_1_design_axi_gpio_1_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zqynq_lab_1_design_axi_gpio_1_1_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF zqynq_lab_1_design_axi_gpio_1_1_arch: ARCHITECTURE IS "axi_gpio,Vivado 2017.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF zqynq_lab_1_design_axi_gpio_1_1_arch : ARCHITECTURE IS "zqynq_lab_1_design_axi_gpio_1_1,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF zqynq_lab_1_design_axi_gpio_1_1_arch: ARCHITECTURE IS "zqynq_lab_1_design_axi_gpio_1_1,axi_gpio,{x_ipProduct=Vivado 2017.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=15,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=5,C_GPIO2_WIDTH=32,C_ALL_INPUTS=1,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=1,C_DOUT_DEFAULT=0x00000000,C_TRI_DEFAULT=0xFFFFFFFF,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 IP2INTC_IRQ INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 5,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 1,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
gpio_io_i => gpio_io_i,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END zqynq_lab_1_design_axi_gpio_1_1_arch;
| mit | 1a58349fe2e7775ce8d4138a20d7a118 | 0.689434 | 3.14665 | false | false | false | false |
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