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emabello42/FREAK-on-FPGA | embeddedretina_ise/DescriptorMaker.vhd | 1 | 3,639 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_3coJ3K
-- /___/ /\ Timestamp : 04/06/2014 00:34:14
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity DescriptorMaker is
port ( clk : in std_logic;
rst : in std_logic;
pointIndexs1: in T_POINT_INDEX;
pointIndexs2: in T_POINT_INDEX;
enableInPointSet : in std_logic;
pointSet : in T_POINT_SET;
descriptor : out std_logic_vector (DESCRIPTOR_SIZE-1 downto 0);
enableOut : out std_logic
);
end DescriptorMaker;
architecture BEHAVIORAL of DescriptorMaker is
signal counter: integer range 0 to 31 := 0;
signal sDescriptor : std_logic_vector (DESCRIPTOR_SIZE-1 downto 0) := (others => '0');
signal innerEnable: std_logic := '0';
signal sPointSet: T_POINT_SET := (others => (others => '0'));
begin
createDescriptor: process(clk)
variable index_i: integer range 0 to 42;
variable index_j: integer range 0 to 42;
begin
if rising_edge(clk) then
if rst = '1' then
counter <= 0;
enableOut <= '0';
sPointSet <= (others => (others => '0'));
innerEnable <= '0';
sDescriptor <= (others => '0');
elsif enableInPointSet = '1' then
sPointSet <= pointSet;
innerEnable <= '1';
enableOut <= '0';
elsif innerEnable = '1' then
for i in 0 to 15 loop
index_i := to_integer(resize(unsigned(pointIndexs1(i)),6));
index_j := to_integer(resize(unsigned(pointIndexs2(i)),6));
if unsigned(sPointSet(index_i)) > unsigned(sPointSet(index_j)) then
sDescriptor(counter*16+i) <= '1';
else
sDescriptor(counter*16+i) <= '0';
end if;
end loop;
if counter = 31 then
counter <= 0;
innerEnable <= '0';
enableOut <= '1';
else
innerEnable <= '1';
enableOut <= '0';
counter <= counter +1;
end if;
else
enableOut <= '0';
end if;
end if;
end process;
descriptor <= sDescriptor;
end BEHAVIORAL;
| gpl-3.0 | bbead00b5faa665477ec1c57b3f7bcba | 0.548777 | 3.790625 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/vram.vhd | 1 | 6,061 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file vram.vhd when simulating
-- the core, vram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY vram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END vram;
ARCHITECTURE vram_a OF vram IS
-- synthesis translate_off
COMPONENT wrapped_vram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_vram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 13,
c_addrb_width => 13,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "00",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 7168,
c_read_depth_b => 7168,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 7168,
c_write_depth_b => 7168,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_vram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END vram_a;
| mit | 6877f03f5f390253f660bb9a15bf9b32 | 0.53539 | 3.887749 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cpu_unit/vhdl_source/dm_cache_custom.vhd | 5 | 19,631 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dm_cache_custom is
generic (
-- g_allocate_on_write : boolean := true;
-- g_write_through : boolean := false;
g_write_support : boolean := true;
g_early_resume : boolean := false;
g_init_file : string := "none";
g_address_width : natural := 24;
g_data_width : natural := 32;
g_id_width : natural := 8;
g_cache_size_bits : natural := 11;
g_line_size_bits : natural := 1 ); -- 2K*32 BL=2
port (
clock : in std_logic;
reset : in std_logic;
client_request : in std_logic;
client_req_id : in std_logic_vector(g_id_width-1 downto 0);
client_rwn : in std_logic;
client_address : in unsigned(g_address_width-1 downto 0);
client_wdata : in std_logic_vector(g_data_width-1 downto 0);
client_byte_en : in std_logic_vector((g_data_width/8)-1 downto 0);
client_rdata : out std_logic_vector(g_data_width-1 downto 0);
client_rack : out std_logic;
client_rack_id : out std_logic_vector(g_id_width-1 downto 0);
client_dack_id : out std_logic_vector(g_id_width-1 downto 0);
mem_request : out std_logic;
mem_read_writen : out std_logic;
mem_address : out unsigned(g_address_width-1 downto 0);
mem_wdata : out std_logic_vector(g_data_width-1 downto 0);
mem_data_push : out std_logic;
mem_data_pop : out std_logic;
mem_rdata : in std_logic_vector(g_data_width-1 downto 0);
mem_ready : in std_logic; -- can accept requests
mem_rdata_av : in std_logic; -- indicates if there is data in read fifo
hit_count : out unsigned(31 downto 0);
miss_count : out unsigned(31 downto 0) );
end dm_cache_custom;
architecture gideon of dm_cache_custom is
constant c_tag_size_bits : integer := g_cache_size_bits - g_line_size_bits;
constant c_tag_width : natural := 2 + g_address_width - g_cache_size_bits;
function cache_index_of(a: unsigned(g_address_width-1 downto 0)) return unsigned is
begin
return a(g_cache_size_bits-1 downto 0);
end function;
function tag_index_of(a: unsigned(g_address_width-1 downto 0)) return unsigned is
begin
return a(g_cache_size_bits-1 downto g_line_size_bits);
end function;
function get_addr_high(a: unsigned(g_address_width-1 downto 0)) return unsigned is
begin
return a(g_address_width-1 downto g_cache_size_bits);
end function;
type t_tag is record
address_high : unsigned(g_address_width-1 downto g_cache_size_bits);
dirty : std_logic;
valid : std_logic;
end record;
constant c_tag_pre_init : t_tag := (
address_high => to_unsigned(0, g_address_width - g_cache_size_bits),
dirty => '1',
valid => '1' );
function tag_pack(t : t_tag) return std_logic_vector is
variable ret : std_logic_vector(c_tag_width-1 downto 0);
begin
ret := t.dirty & t.valid & std_logic_vector(t.address_high);
return ret;
end function;
function tag_unpack(v : std_logic_vector(c_tag_width-1 downto 0)) return t_tag is
variable ret : t_tag;
begin
ret.dirty := v(v'high);
ret.valid := v(v'high-1);
ret.address_high := unsigned(v(v'high-2 downto 0));
return ret;
end function;
signal any_request : std_logic := '0';
signal read_request : std_logic := '0';
signal read_request_d : std_logic := '0';
signal write_request : std_logic := '0';
signal write_request_d : std_logic := '0';
signal ready : std_logic := '0';
signal read_la : std_logic := '0';
signal write_la : std_logic := '0';
signal tag_la : std_logic_vector(g_id_width-1 downto 0);
signal do_query_d : std_logic;
signal rd_address : unsigned(g_address_width-1 downto 0);
signal wr_address : unsigned(g_address_width-1 downto 0);
signal cache_rd_index : unsigned(g_cache_size_bits-1 downto 0);
signal cache_wr_index : unsigned(g_cache_size_bits-1 downto 0);
signal cache_wdata : std_logic_vector(g_data_width-1 downto 0);
signal cache_byte_en : std_logic_vector(client_byte_en'range);
signal cache_data_out : std_logic_vector(g_data_width-1 downto 0) := (others => '0');
signal cache_rdata : std_logic_vector(g_data_width-1 downto 0);
signal cache_we : std_logic;
signal cache_b_en : std_logic;
signal cache_rd_en : std_logic;
signal tag_rd_index : unsigned(g_cache_size_bits-1 downto g_line_size_bits);
signal tag_wr_index : unsigned(g_cache_size_bits-1 downto g_line_size_bits);
signal tag_wdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_rdata : std_logic_vector(c_tag_width-1 downto 0);
signal rd_tag : t_tag;
signal wr_tag : t_tag;
signal fill_tag : t_tag;
signal last_write_tag : t_tag;
signal hit_i : std_logic := '0';
signal cache_miss : std_logic := '0';
signal cache_hit : std_logic := '0';
signal old_address : unsigned(g_address_width-1 downto 0);
signal address_la : unsigned(g_address_width-1 downto 0);
-- back office
signal fill_high : unsigned(g_address_width-1 downto g_line_size_bits) := (others => '0');
signal fill_address : unsigned(g_address_width-1 downto 0) := (others => '0');
signal fill_valid : std_logic;
signal fill_data : std_logic_vector(g_data_width-1 downto 0);
signal burst_count : unsigned(g_line_size_bits-1 downto 0);
signal burst_count_d : unsigned(g_line_size_bits-1 downto 0);
type t_state is (idle, check_dirty, fill, deferred);
signal state : t_state;
signal dirty_d : std_logic;
-- signals related to delayed write register
signal last_write_address : unsigned(g_address_width-1 downto 0);
signal last_write_data : std_logic_vector(g_data_width-1 downto 0);
signal last_write_byte_en : std_logic_vector(client_byte_en'range);
signal last_write_valid : std_logic;
signal store_reg : std_logic := '0';
signal store_after_fill : std_logic := '0';
-- memory interface
signal mem_busy : std_logic := '0';
signal need_mem_access : std_logic := '0';
signal mem_req_i : std_logic;
signal mem_rwn : std_logic;
signal mem_addr_i : unsigned(g_address_width-1 downto 0);
signal mem_wrfifo_put : std_logic;
signal mem_rdfifo_get : std_logic;
signal helper_data_to_ram : std_logic_vector(g_data_width-1 downto 0);
signal helper_data_from_ram : std_logic_vector(g_data_width-1 downto 0);
-- statistics
signal hit_count_i : unsigned(31 downto 0) := (others => '0');
signal miss_count_i : unsigned(31 downto 0) := (others => '0');
begin
any_request <= client_request and ready;
read_request <= client_request and client_rwn and ready;
write_request <= client_request and not client_rwn and ready;
ready <= '1' when mem_busy='0' and need_mem_access='0' else '0';
need_mem_access <= cache_miss;
process(clock)
begin
if rising_edge(clock) then
read_request_d <= read_request;
write_request_d <= write_request;
do_query_d <= '0';
if ready='1' then
do_query_d <= client_request;
tag_la <= client_req_id;
address_la <= client_address;
read_la <= client_request and client_rwn;
write_la <= client_request and not client_rwn;
end if;
end if;
end process;
-- main address multiplexer
rd_address <= client_address;
wr_address <= fill_address when (mem_rdfifo_get='1' or dirty_d='1') else
last_write_address;
cache_rd_index <= cache_index_of(rd_address);
cache_wr_index <= cache_index_of(wr_address);
cache_wdata <= fill_data when mem_rdfifo_get='1' else
last_write_data;
cache_byte_en <= (others => '1') when mem_rdfifo_get='1' else
last_write_byte_en;
wr_tag <= fill_tag when mem_rdfifo_get='1' else
last_write_tag;
cache_we <= mem_rdfifo_get or store_reg;
cache_b_en <= cache_we or dirty_d; -- dirty_d is set during fill operation and causes read enable here
cache_rd_en <= client_request and ready;
fill_tag.address_high <= get_addr_high(fill_address);
fill_tag.dirty <= '0';
fill_tag.valid <= '1';
last_write_tag.address_high <= get_addr_high(last_write_address);
last_write_tag.dirty <= '1';
last_write_tag.valid <= last_write_valid;
r_write_byte_en: if g_write_support generate
i_cache_ram: entity work.dpram_rdw_byte
generic map (
g_rdw_check => g_early_resume,
g_width_bits => g_data_width,
g_depth_bits => g_cache_size_bits,
g_init_file => g_init_file,
g_storage => "auto" )
port map (
clock => clock,
a_address => cache_rd_index,
a_rdata => cache_rdata,
a_en => cache_rd_en,
b_address => cache_wr_index,
b_rdata => cache_data_out,
b_wdata => cache_wdata,
b_byte_en => cache_byte_en,
b_en => cache_b_en,
b_we => cache_we );
end generate;
r_write_fill_only: if not g_write_support generate
i_cache_ram_nobe: entity work.dpram_rdw
generic map (
g_rdw_check => g_early_resume,
g_width_bits => g_data_width,
g_depth_bits => g_cache_size_bits,
g_init_value => X"00000000",
g_init_file => g_init_file,
g_init_width => g_data_width/8,
g_init_offset => 0,
g_storage => "auto" )
port map (
clock => clock,
a_address => cache_rd_index,
a_rdata => cache_rdata,
a_en => cache_rd_en,
b_address => cache_wr_index,
b_rdata => cache_data_out,
b_wdata => fill_data,
b_en => cache_b_en,
b_we => mem_rdfifo_get );
end generate;
tag_rd_index <= tag_index_of(rd_address);
tag_wr_index <= tag_index_of(wr_address);
rd_tag <= tag_unpack(tag_rdata);
tag_wdata <= tag_pack(wr_tag);
i_tag_ram: entity work.dpram_rdw
generic map (
g_rdw_check => g_early_resume,
g_width_bits => c_tag_width,
g_init_value => tag_pack(c_tag_pre_init),
g_depth_bits => c_tag_size_bits )
port map (
clock => clock,
a_address => tag_rd_index,
a_rdata => tag_rdata,
a_en => cache_rd_en,
b_address => tag_wr_index,
b_wdata => tag_wdata,
b_en => cache_we,
b_we => cache_we );
hit_i <= '1' when rd_tag.valid='1' and (rd_tag.address_high = get_addr_high(address_la)) else '0';
cache_hit <= hit_i and do_query_d;
cache_miss <= not hit_i and do_query_d;
old_address <= rd_tag.address_high & address_la(g_cache_size_bits-1 downto 0); -- recombine
-- handle writes
process(clock)
begin
if rising_edge(clock) then
if client_request='1' and client_rwn='0' and ready='1' then
last_write_data <= client_wdata;
last_write_byte_en <= client_byte_en;
last_write_address <= client_address;
last_write_valid <= '1';
elsif store_reg='1' then
last_write_valid <= '0';
end if;
end if;
end process;
store_reg <= '1' when (last_write_valid='1' and (cache_hit='1' or store_after_fill='1')) else
'0';
-- end handle writes
-- read data multiplexer
fill_valid <= mem_rdata_av;
fill_data <= mem_rdata;
client_rack <= client_request and ready;
client_rack_id <= client_req_id when client_request='1' and ready='1' else (others => '0');
process(cache_hit, cache_rdata, read_request_d, tag_la,
fill_data, fill_valid, burst_count, read_la, address_la)
begin
client_dack_id <= (others => '0');
if cache_hit='1' then
client_rdata <= cache_rdata;
if read_request_d='1' then
client_dack_id <= tag_la;
end if;
else
client_rdata <= fill_data;
-- Generate dack when correct word passes by (not necessary, but will increase performance)
-- (In this setup it is necessary, because there is no other cause to let the client continue,
-- as 'hit' will not automatically become '1', as we already acknowledged the request itself.)
if fill_valid='1' and burst_count = address_la(burst_count'range) and read_la='1' then
client_dack_id <= tag_la;
end if;
end if;
end process;
-- end read data multiplexer
p_cache_control: process(clock)
begin
if rising_edge(clock) then
burst_count_d <= burst_count;
store_after_fill <= '0';
mem_req_i <= '0';
if cache_miss='1' then
miss_count_i <= miss_count_i + 1;
end if;
if cache_hit='1' then
hit_count_i <= hit_count_i + 1;
end if;
case state is
when idle =>
-- There are a few scenarios that could cause a miss:
-- Read miss: last_write_register is not valid, because it should already have been written in the cache!
-- Write miss: last_write_register is always valid, since it was just set. In this scenario the last write register
-- holds data that still needs to be written to the cache, BUT couldn't do it because of the miss. The data in the cache
-- that is flushed to DRAM is never the data in the register, otherwise it would have been a hit. The fill cycle that
-- follows will check dirty, do a write out of the dirty data from cache, and then fills the cacheline with data from
-- the DRAM, and then will issue the command to store the register. Obviously this immediately sets the line to dirty.
if cache_miss='1' then
if mem_ready='1' then
-- issue read access (priority read over write)
mem_req_i <= '1';
mem_rwn <= '1';
mem_addr_i <= address_la;
state <= check_dirty;
else
state <= deferred;
end if;
end if;
dirty_d <= rd_tag.dirty and cache_miss; -- dirty will be our read enable from cache :)
--fill_high <= old_address(old_address'high downto g_line_size_bits); -- high bits don't matter here (this is correct!)
--fill_high <= address_la(old_address'high downto g_line_size_bits); -- high bits don't matter here (optimization!!)
when deferred =>
if mem_ready='1' then
-- issue read access (priority read over write)
mem_req_i <= '1';
mem_rwn <= '1';
mem_addr_i <= address_la;
state <= check_dirty;
end if;
when check_dirty => -- sequences through 'line_size' words
mem_addr_i <= old_address;
mem_rwn <= '0'; -- write
if dirty_d='0' then
--fill_high <= address_la(address_la'high downto g_line_size_bits); -- high bits do matter here
state <= fill;
else -- dirty_d='1'
burst_count <= burst_count + 1;
if signed(burst_count) = -1 then -- last?
mem_req_i <= '1'; -- issue the write request to memctrl
dirty_d <= '0';
--fill_high <= address_la(address_la'high downto g_line_size_bits); -- high bits do matter here
state <= fill;
end if;
end if;
when fill =>
if mem_rdata_av='1' then
burst_count <= burst_count + 1;
if signed(burst_count) = -1 then -- last?
state <= idle;
store_after_fill <= last_write_valid; -- this will occur during idle
end if;
end if;
-- asynchronously: mem_rdfifo_get <= '1' when state = fill and mem_rdata_av='1'.
when others =>
null;
end case;
mem_wrfifo_put <= dirty_d; -- latency of blockram
if reset='1' then
burst_count <= (others => '0');
dirty_d <= '0';
state <= idle;
mem_rwn <= '1';
mem_req_i <= '0';
end if;
end if;
end process;
mem_rdfifo_get <= '1' when state = fill and mem_rdata_av='1' else '0';
-- index to the cache for back-office operations (line in, line out)
fill_high <= address_la(old_address'high downto g_line_size_bits);
fill_address <= fill_high & burst_count;
mem_busy <= '1' when (state/= idle) else '0';
mem_request <= mem_req_i;
mem_read_writen <= mem_rwn;
mem_address <= mem_addr_i(mem_address'high downto g_line_size_bits) & to_unsigned(0, g_line_size_bits);
mem_wdata <= cache_data_out;
mem_data_pop <= mem_rdfifo_get;
mem_data_push <= mem_wrfifo_put;
helper_data_to_ram <= cache_data_out when mem_wrfifo_put='1' else (others => 'Z');
helper_data_from_ram <= mem_rdata when mem_rdfifo_get='1' else (others => 'Z');
hit_count <= hit_count_i;
miss_count <= miss_count_i;
end gideon;
| gpl-3.0 | c9ed6c508ea2b82dbf79885ba4752df6 | 0.512302 | 3.743516 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op332_15sk1_0.vhdl | 1 | 7,013 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.15e-06,
W => Wdiff_0,
Wdiff_0init => 3.95e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.15e-06,
W => Wdiff_0,
Wdiff_0init => 3.95e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.2e-06,
W => W_0,
W_0init => 1.175e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.95e-06,
W => Wcm_2,
Wcm_2init => 1.2e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.95e-06,
W => Wcmout_2,
Wcmout_2init => 7.56e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.95e-06,
W => Wcm_2,
Wcm_2init => 1.2e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.95e-06,
W => Wcmout_2,
Wcmout_2init => 7.56e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.2e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 7.71e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias3,
S => net6
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.6e-06,
W => Wcm_1,
Wcm_1init => 5.36e-05,
scope => private
)
port map(
D => net6,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.6e-06,
W => Wcmout_1,
Wcmout_1init => 6.55e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.2e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 7.71e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6.2e-06,
W => (pfak)*(WBias),
WBiasinit => 4.195e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6.2e-06,
W => (pfak)*(WBias),
WBiasinit => 4.195e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6.2e-06,
W => WBias,
WBiasinit => 4.195e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.2e-06,
W => WBias,
WBiasinit => 4.195e-05
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.2e-06,
W => WBias,
WBiasinit => 4.195e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.2e-06,
W => WBias,
WBiasinit => 4.195e-05
)
port map(
D => net8,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net9,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net9,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net9,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 92a4d5ec74029f72a846351d9af4fbf0 | 0.583345 | 2.913585 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DPR_Xilinx.vhd | 2 | 12,077 | ------------------------------------------------------------------------------------------------------------------------
-- OpenMAC - DPR for Xilinx FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 zelenkaj Converted to official version.
-- 2011-10-12 V0.10 zelenkaj Implementation is based on UG687 (v13.2)
-- 2012-03-01 V0.11 mairt added memory init for pdi dpr
------------------------------------------------------------------------------------------------------------------------
--
-- dual clocked DPRAM for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr is
generic (
WIDTH : integer := 16;
SIZE : integer := 128;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr;
architecture xilinx of dc_dpr is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
shared variable ram : ramType := (others => (others => '0'));
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
ram(conv_integer(addrA)) := diA;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
ram(conv_integer(addrB)) := diB;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with byte enables for XILINX SPARTAN 6 --
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dc_dpr_be is
generic (
gDoInit : boolean := false; -- if dpr is used in pdi init state field with invalid state
WIDTH : integer := 16;
SIZE : integer := 128;
ADDRWIDTH : integer := 7
);
port (
clkA : in std_logic;
clkB : in std_logic;
enA : in std_logic;
enB : in std_logic;
weA : in std_logic;
weB : in std_logic;
beA : in std_logic_vector(WIDTH/8-1 downto 0);
beB : in std_logic_vector(WIDTH/8-1 downto 0);
addrA : in std_logic_vector(ADDRWIDTH-1 downto 0);
addrB : in std_logic_vector(ADDRWIDTH-1 downto 0);
diA : in std_logic_vector(WIDTH-1 downto 0);
diB : in std_logic_vector(WIDTH-1 downto 0);
doA : out std_logic_vector(WIDTH-1 downto 0);
doB : out std_logic_vector(WIDTH-1 downto 0)
);
end dc_dpr_be;
architecture xilinx of dc_dpr_be is
function log2 (val: INTEGER) return natural is
variable res : natural;
begin
for i in 0 to 31 loop
if (val <= (2**i)) then
res := i;
exit;
end if;
end loop;
return res;
end function Log2;
type ramType is array (0 to SIZE-1) of std_logic_vector(WIDTH-1 downto 0);
function InitRam return ramType is
variable RAM : ramType := (others => (others => '0'));
begin
if gDoInit = true then
for i in ramType'range loop
RAM(i) := X"00000000";
if i = 4 then -- init state field with invalid state
RAM(i) := X"00EEFFFF";
end if;
end loop;
end if;
return RAM;
end function;
shared variable ram : ramType := InitRam;
constant BYTE : integer := 8;
signal readA : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
signal readB : std_logic_vector(WIDTH-1 downto 0):= (others => '0');
begin
process (clkA)
begin
if rising_edge(clkA) then
if enA = '1' then
if weA = '1' then
for i in beA'range loop
if beA(i) = '1' then
ram(conv_integer(addrA))((i+1)*BYTE-1 downto i*BYTE) := diA((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readA <= ram(conv_integer(addrA));
end if;
end if;
end process;
doA <= readA;
process (clkB)
begin
if rising_edge(clkB) then
if enB = '1' then
if weB = '1' then
for i in beB'range loop
if beB(i) = '1' then
ram(conv_integer(addrB))((i+1)*BYTE-1 downto i*BYTE) := diB((i+1)*BYTE-1 downto i*BYTE);
end if;
end loop;
end if;
readB <= ram(conv_integer(addrB));
end if;
end if;
end process;
doB <= readB;
end xilinx;
-- dual clocked DPRAM with 16x16 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 16,
SIZE => 2**AddrA'length,
ADDRWIDTH => AddrA'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => AddrA, addrB => AddrB,
diA => DiA, diB => DiB,
doA => DoA, doB => DoB,
weA => WeA, weB => WeB,
beA => BeA, beB => BeB
);
end struct;
-- dual clocked DPRAM with 16x32 --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
signal addra_s : std_logic_vector(AddrB'range);
signal dia_s : std_logic_vector(DoB'range);
signal bea_s : std_logic_vector(DoB'length/8-1 downto 0);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 32,
SIZE => 2**AddrB'length,
ADDRWIDTH => AddrB'length
)
port map (
clkA => ClkA, clkB => ClkB,
enA => EnA, enB => EnB,
addrA => addra_s, addrB => AddrB,
diA => dia_s, diB => (others => '0'),
doA => open, doB => DoB,
weA => weA, weB => '0',
beA => bea_s, beB => (others => '1')
);
addra_s <= AddrA(AddrA'left downto 1);
dia_s <= DiA & DiA;
bea_s(3) <= BeA(1) and AddrA(0);
bea_s(2) <= BeA(0) and AddrA(0);
bea_s(1) <= BeA(1) and not AddrA(0);
bea_s(0) <= BeA(0) and not AddrA(0);
end struct;
-- dual clocked DPRAM with 32x32 for packets --
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
architecture struct of OpenMAC_DPRpackets is
signal address_a_s : std_logic_vector(address_b'range);
signal bea : std_logic_vector(byteena_b'range);
signal q_a_s, q_b_s, data_a_s : std_logic_vector(q_b'range);
signal q_a_s1 : std_logic_vector(q_a'range);
begin
dpr_packet: entity work.dc_dpr_be
generic map (
gDoInit => false,
WIDTH => 32,
SIZE => memSize_g/4,
ADDRWIDTH => memSizeLOG2_g-2
)
port map (
clkA => clock_a, clkB => clock_b,
enA => '1', enB => '1',
addrA => address_a_s, addrB => address_b,
diA => data_a_s, diB => data_b,
doA => q_a_s, doB => q_b_s,
weA => wren_a, weB => wren_b,
beA => bea, beB => byteena_b
);
address_a_s <= address_a(address_a'left downto 1);
bea(3) <= byteena_a(1) and address_a(0);
bea(2) <= byteena_a(0) and address_a(0);
bea(1) <= byteena_a(1) and not address_a(0);
bea(0) <= byteena_a(0) and not address_a(0);
data_a_s <= data_a & data_a;
q_a_s1 <= q_a_s(q_a'length*2-1 downto q_a'length) when address_a(0) = '1' else
q_a_s(q_a'range);
--sync outputs
process(clock_a)
begin
if rising_edge(clock_a) then
q_a <= q_a_s1;
end if;
end process;
process(clock_b)
begin
if rising_edge(clock_b) then
q_b <= q_b_s;
end if;
end process;
end struct;
| gpl-2.0 | cbcf815b762fd7fd414199688cf8a9bd | 0.57978 | 2.9864 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_source/char_generator_timing.vhd | 5 | 9,039 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_timing.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.char_generator_pkg.all;
entity char_generator_timing is
generic (
g_divider : integer := 5 );
port (
clock : in std_logic;
reset : in std_logic;
h_sync : in std_logic;
v_sync : in std_logic;
control : in t_chargen_control;
screen_addr : out unsigned(10 downto 0);
screen_data : in std_logic_vector(7 downto 0);
char_addr : out unsigned(10 downto 0);
char_data : in std_logic_vector(7 downto 0);
sync_n : out std_logic;
clock_en : out std_logic;
pixel_active : out std_logic;
pixel_data : out std_logic );
end entity;
architecture gideon of char_generator_timing is
signal clock_div : integer range 0 to g_divider-1;
signal clock_en_i : std_logic;
signal force_sync : std_logic;
signal x_counter : unsigned(10 downto 0) := (others => '0');
signal y_counter : unsigned(8 downto 0) := (others => '0');
signal pointer : unsigned(10 downto 0) := (others => '0');
signal char_x : unsigned(6 downto 0) := (others => '0');
signal char_y : unsigned(3 downto 0) := (others => '0');
signal char_y_d : unsigned(3 downto 0) := (others => '0');
signal pixel_count : unsigned(2 downto 0) := (others => '0');
signal remaining_lines : unsigned(4 downto 0) := (others => '0');
signal h_sync_c : std_logic;
signal h_sync_d : std_logic;
signal v_sync_c : std_logic;
type t_state is (idle, active_line, draw);
signal state : t_state;
type t_line_type is (normal, half, serration);
signal line_type : t_line_type;
-- pipeline
signal active_d1 : std_logic;
signal pixel_sel_d1 : unsigned(2 downto 0);
signal active_d2 : std_logic;
signal pixel_sel_d2 : unsigned(2 downto 0);
begin
clock_en <= clock_en_i;
process(clock)
begin
if rising_edge(clock) then
h_sync_c <= h_sync;
h_sync_d <= h_sync_c;
v_sync_c <= v_sync;
-- force_sync <= '0';
-- if control.perform_sync='1' and v_sync_c='1' and h_sync_d='0' and h_sync_c='1' then
-- y_counter <= (others => '0');
-- x_counter <= (others => '0');
-- end if;
-- -- x/y counters, zonder gehinderd door enige sync-kennis
-- if clock_en_i = '1' then
-- if x_counter = control.clocks_per_line-1 then
-- x_counter <= (others => '0');
-- if y_counter = 311 then
-- y_counter <= (others => '0');
-- force_sync <= '1';
-- else
-- y_counter <= y_counter + 1;
-- end if;
-- else
-- x_counter <= x_counter + 1;
-- end if;
-- end if;
if h_sync_c='1' and h_sync_d='0' then -- rising_edge
x_counter <= (others => '0');
if v_sync_c='1' then
y_counter <= (others => '0');
else
y_counter <= y_counter + 1;
end if;
clock_en_i <= '0';
clock_div <= g_divider-1;
elsif clock_div = 0 then
x_counter <= x_counter + 1;
clock_en_i <= '1';
clock_div <= g_divider-1;
else
clock_en_i <= '0';
clock_div <= clock_div - 1;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if clock_en_i='1' then
line_type <= normal;
if (y_counter < 3) or (y_counter > 305) then
line_type <= half;
end if;
if (y_counter > 308) then
line_type <= serration;
end if;
if x_counter=0 then
sync_n <= '0';
else
case line_type is
when normal =>
if x_counter = 64 then
sync_n <= '1';
end if;
when half =>
if x_counter = 32 then
sync_n <= '1';
elsif x_counter = 448 then
sync_n <= '0';
elsif x_counter = 480 then
sync_n <= '1';
end if;
when serration =>
if x_counter = 416 then
sync_n <= '1';
elsif x_counter = 448 then
sync_n <= '0';
elsif x_counter = 864 then
sync_n <= '1';
end if;
when others =>
null;
end case;
end if;
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
if clock_en_i='1' then
active_d1 <= '0';
char_y_d <= char_y;
case state is
when idle =>
pointer <= control.pointer;
char_y <= (others => '0');
remaining_lines <= control.active_lines;
if y_counter = control.y_on then
state <= active_line;
end if;
when active_line =>
char_x <= (others => '0');
pixel_count <= control.char_width;
if remaining_lines = 0 then
state <= idle;
elsif x_counter = control.x_on then
state <= draw;
end if;
when draw =>
if pixel_count = 1 then
pixel_count <= control.char_width;
char_x <= char_x + 1;
if char_x = control.chars_per_line-1 then
state <= active_line;
char_x <= (others => '0');
if char_y = control.char_height-1 then
pointer <= pointer + control.chars_per_line;
char_y <= (others => '0');
remaining_lines <= remaining_lines - 1;
else
char_y <= char_y + 1;
end if;
end if;
else
pixel_count <= pixel_count - 1;
end if;
active_d1 <= '1';
when others =>
null;
end case;
-- pipeline forwards
pixel_sel_d1 <= pixel_count - 1;
pixel_sel_d2 <= pixel_sel_d1;
active_d2 <= active_d1;
-- pixel output
pixel_active <= active_d2;
pixel_data <= active_d2 and char_data(to_integer(pixel_sel_d2));
if force_sync='1' then
state <= idle;
end if;
end if;
if reset='1' then
state <= idle;
end if;
end if;
end process;
screen_addr <= pointer + char_x;
char_addr <= unsigned(screen_data) & char_y_d(2 downto 0) when char_y_d(3)='0' else
screen_data(7) & "0000000000";
end architecture;
| gpl-3.0 | f25cd03b98275100cd378b9be6521c18 | 0.372054 | 4.526289 | false | false | false | false |
chrismasters/fpga-notes | vga_test/ipcore_dir/vga_clk.vhd | 1 | 6,190 | -- file: vga_clk.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____25.000______0.000______50.0_____1000.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________32____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity vga_clk is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end vga_clk;
architecture xilinx of vga_clk is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "vga_clk,clk_wiz_v3_6,{component_name=vga_clk,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=31.25,clkin2_period=31.25,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.25,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => open,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkfx);
end xilinx;
| mit | 2f72ae6da494079c8aa7c9f14f8b605d | 0.572375 | 4.313589 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op334_2sk1_0.vhdl | 1 | 5,738 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 2.685e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 2.685e-05,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.1e-06,
W => W_0,
W_0init => 7.345e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.1e-06,
W => Wcasc_2,
Wcasc_2init => 6.95e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.1e-06,
W => Wcasc_2,
Wcasc_2init => 6.95e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias3,
S => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 6.4e-06,
W => Wcm_1,
Wcm_1init => 7.145e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 6.4e-06,
W => Wcmout_1,
Wcmout_1init => 7.54e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.1e-06,
W => (pfak)*(WBias),
WBiasinit => 3.7e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.1e-06,
W => (pfak)*(WBias),
WBiasinit => 3.7e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.1e-06,
W => WBias,
WBiasinit => 3.7e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.1e-06,
W => WBias,
WBiasinit => 3.7e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.1e-06,
W => WBias,
WBiasinit => 3.7e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.1e-06,
W => WBias,
WBiasinit => 3.7e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | fbd3e1130b0b2fd8d594d68558c275cd | 0.589404 | 2.996345 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ipcore_dir/ROM_GAUSS_COE/simulation/ROM_GAUSS_COE_tb_synth.vhd | 1 | 8,325 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_GAUSS_COE_tb_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.ROM_GAUSS_COE_TB_PKG.ALL;
ENTITY ROM_GAUSS_COE_tb_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 0
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ROM_GAUSS_COE_tb_synth;
ARCHITECTURE ROM_GAUSS_COE_synth_ARCH OF ROM_GAUSS_COE_tb_synth IS
COMPONENT ROM_GAUSS_COE_exdes
PORT (
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(135-1 downto 0);
A : IN STD_LOGIC_VECTOR(4-1-(4*0*boolean'pos(4>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0')
);
END COMPONENT;
CONSTANT STIM_CNT : INTEGER := if_then_else(C_ROM_SYNTH = 0, 8, 22);
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i : STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ADDR: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDR_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL WE : STD_LOGIC:='0';
SIGNAL WE_R : STD_LOGIC:='0';
SIGNAL SPO: STD_LOGIC_VECTOR(134 DOWNTO 0) := (OTHERS => '0');
SIGNAL SPO_R: STD_LOGIC_VECTOR(134 DOWNTO 0) := (OTHERS => '0');
SIGNAL D: STD_LOGIC_VECTOR(134 DOWNTO 0) := (OTHERS => '0');
SIGNAL D_R: STD_LOGIC_VECTOR(134 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_EN: STD_LOGIC:='0';
SIGNAL CHECKER_EN_R: STD_LOGIC:='0';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
ROM_GAUSS_COE_TB_STIM_GEN_INST:ENTITY work.ROM_GAUSS_COE_TB_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
A => ADDR,
D => D,
WE => WE,
DATA_IN => SPO_R,
CHECK_DATA => CHECKER_EN
);
DMG_DATA_CHECKER_INST: ENTITY work.ROM_GAUSS_COE_TB_CHECKER
GENERIC MAP (
WRITE_WIDTH => 135,
READ_WIDTH => 135 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => SPO_R,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(STIM_CNT);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDR(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW + 1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WE_R <= '0' AFTER 50 ns;
SPO_R <= (OTHERS=>'0') AFTER 50 ns;
D_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WE_R <= WE AFTER 50 ns;
SPO_R <= SPO AFTER 50 ns;
D_R <= D AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDR_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDR_R <= ADDR AFTER 50 ns;
END IF;
END IF;
END PROCESS;
DMG_PORT: ROM_GAUSS_COE_exdes PORT MAP (
CLK => CLKA,
WE => WE_R,
SPO => SPO,
A => ADDR_R,
D => D_R
);
END ARCHITECTURE;
| gpl-3.0 | fdbe6c85e72ac402fb5e68f232e102bf | 0.548709 | 3.724832 | false | false | false | false |
chrismasters/fpga-space-invaders | project/spaceinvaders.vhd | 1 | 6,783 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity spaceinvaders is port (
clk : in std_logic;
-- video pins
red : out STD_LOGIC_VECTOR (3 downto 0);
green : out STD_LOGIC_VECTOR (3 downto 0);
blue : out STD_LOGIC_VECTOR (3 downto 0);
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
-- reset pin
reset : in std_logic;
leds : out STD_LOGIC_VECTOR(3 downto 0));
end spaceinvaders;
architecture Behavioral of spaceinvaders is
signal clk10mhz : STD_LOGIC;
signal clk133mhz : STD_LOGIC;
signal clk133mhzinv : STD_LOGIC;
signal clk25mhz : STD_LOGIC;
signal addressBus : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal dataBusReady : STD_LOGIC := '0';
signal cpuInt : STD_LOGIC := '0';
signal cpuHold : STD_LOGIC := '0';
signal cpuDataIn : STD_LOGIC_VECTOR(7 downto 0);
signal cpuDataOut : STD_LOGIC_VECTOR(7 downto 0);
signal cpuDataBusInputMode : STD_LOGIC;
signal cpuStatus : std_logic_vector(3 downto 0);
signal cpuSync : std_logic;
signal cpuWaitAck : std_logic;
signal cpuWr : std_logic;
signal cpuHlda : std_logic;
signal cpuInte : std_logic;
signal romDataOut : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal romAddr : STD_LOGIC_VECTOR(12 DOWNTO 0) := (others => '0');
signal ramAddr : STD_LOGIC_VECTOR(9 DOWNTO 0) := (others => '0');
signal ramDataOut : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal ramDataIn : STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
signal ramWea : STD_LOGIC_VECTOR(0 DOWNTO 0) := "0";
signal vramAddrA : STD_LOGIC_VECTOR(12 DOWNTO 0) := (others => '0');
signal vramDataOutA: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal vramDataInA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (others => '0');
signal vramAddrB : STD_LOGIC_VECTOR(12 DOWNTO 0) := (others => '0');
signal vramDataOutB : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal vramWea : STD_LOGIC_VECTOR(0 DOWNTO 0) := "0";
COMPONENT clocks PORT (
clkin : in STD_LOGIC;
clk10mhz : out STD_LOGIC;
clk133mhz : out STD_LOGIC;
clk133mhzinv : out STD_LOGIC;
clk25mhz : out STD_LOGIC);
END COMPONENT;
COMPONENT video PORT (
clkin25mhz : in STD_LOGIC;
red : out STD_LOGIC_VECTOR (3 downto 0);
green : out STD_LOGIC_VECTOR (3 downto 0);
blue : out STD_LOGIC_VECTOR (3 downto 0);
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
vramAddr : out STD_LOGIC_VECTOR (12 downto 0);
vramData : in STD_LOGIC_VECTOR (7 downto 0);
colourOutput : in STD_LOGIC);
END COMPONENT;
COMPONENT vram PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT ram PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT rom PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END COMPONENT;
COMPONENT i8080 PORT (
clk : IN std_logic;
dataIn : IN std_logic_vector(7 downto 0);
ready : IN std_logic;
hold : IN std_logic;
int : IN std_logic;
reset : IN std_logic;
addressBus : OUT std_logic_vector(15 downto 0);
dataOut : OUT std_logic_vector(7 downto 0);
sync : OUT std_logic;
dataBusIn : OUT std_logic;
waitAck : OUT std_logic;
wr : OUT std_logic;
hlda : OUT std_logic;
inte : OUT std_logic;
status : OUT std_logic_vector(3 downto 0));
END COMPONENT;
type memControllerState is (idle, read0, read1, write0);
signal memState : memControllerState := idle;
signal vgaVsync : std_logic;
BEGIN
process (vgaVsync)
begin
if (rising_edge(vgaVsync)) then
-- interrupt at end of scan (RST 10)
cpuInt <= '1';
else
if (cpuInte = '0') then
cpuInt <= '0';
end if;
end if;
end process;
process (clk10mhz)
variable writing : std_logic := '0';
variable vramAddrAWide : STD_LOGIC_VECTOR(15 DOWNTO 0);
variable ramAddrWide : STD_LOGIC_VECTOR(15 DOWNTO 0);
begin
if (falling_edge(clk10mhz)) then
case (memState) is
when idle =>
vramWea <= "0";
ramWea <= "0";
if (addressBus >= X"2400") then
vramAddrAWide := (addressBus - X"2400");
vramAddrA <= vramAddrAWide(12 downto 0);
elsif (addressBus >= X"2000") then
ramAddrWide := (addressBus - X"2000");
ramAddr <= ramAddrWide(9 downto 0);
else
romAddr <= addressBus(12 downto 0);
end if;
if (cpuDataBusInputMode = '1') then
memState <= read0;
elsif (cpuWr = '1') then
memState <= write0;
end if;
when read0 =>
dataBusReady <= '0';
memState <= read1;
when read1 =>
if (addressBus < X"2000") then
cpuDataIn <= romDataOut;
elsif (addressBus < X"2400") then
cpuDataIn <= ramDataOut;
else
cpuDataIn <= vramDataOutB;
end if;
dataBusReady <= '1';
memState <= idle;
when write0 =>
if (addressBus >= X"2400") then
vramDataInA <= cpuDataOut;
vramWea <= "1";
elsif (addressBus >= X"2000") then
ramDataIn <= cpuDataOut;
ramWea <= "1";
else
report "Attempt to write to ROM address!";
end if;
memState <= idle;
end case;
end if;
end process;
leds <= cpuStatus;
vsync <= vgaVsync;
videoController : video PORT MAP (
clkin25mhz => clk25mhz,
red => red,
green => green,
blue => blue,
hsync => hsync,
vsync => vgaVsync,
vramAddr => vramAddrB,
vramData => vramDataOutB,
colourOutput => '1');
allClocks : clocks PORT MAP (
clkin => clk,
clk10mhz => clk10mhz,
clk133mhz => clk133mhz,
clk133mhzinv => clk133mhzinv,
clk25mhz => clk25mhz);
videoRam : vram PORT MAP (
clka => clk10mhz,
wea => vramWea,
addra => vramAddrA,
dina => vramDataInA,
douta => vramDataOutA,
clkb => clk25mhz,
web => "0",
addrb => vramAddrB,
dinb => "00000000",
doutb => vramDataOutB);
readWriteMemory : ram PORT MAP (
clka => clk10mhz,
wea => ramWea,
addra => ramAddr,
dina => ramDataIn,
douta => ramDataOut);
invadersRom : rom PORT MAP (
clka => clk10mhz,
addra => romAddr,
douta => romDataOut);
cpu: i8080 PORT MAP(
clk => clk10mhz,
dataIn => cpuDataIn,
ready => dataBusReady,
hold => cpuHold,
int => cpuInt,
reset => reset,
addressBus => addressBus,
dataOut => cpuDataOut,
sync => cpuSync,
dataBusIn => cpuDataBusInputMode,
waitAck => cpuWaitAck,
wr => cpuWr,
hlda => cpuHlda,
inte => cpuInte,
status => cpuStatus);
END Behavioral;
| mit | 923f70afd2593aea6eb53f4c81577100 | 0.652661 | 2.923707 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/async_fifo/vhdl_source/gray_code_pkg.vhd | 4 | 3,209 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : gray_code_pkg
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: gray code package, only the functions needed for the
-- asynchronous fifo
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package gray_code_pkg is
---------------------------------------------------------------------------
-- type
---------------------------------------------------------------------------
type t_gray is array (natural range <>) of std_logic;
---------------------------------------------------------------------------
-- conversion function
---------------------------------------------------------------------------
function to_unsigned (arg : t_gray) return unsigned;
---------------------------------------------------------------------------
-- arithmetic function
---------------------------------------------------------------------------
function increment (arg : t_gray) return t_gray;
end gray_code_pkg;
-------------------------------------------------------------------------------
-- package body
-------------------------------------------------------------------------------
package body gray_code_pkg is
function to_unsigned (arg : t_gray) return unsigned is
variable mybin : unsigned(arg'range);
variable temp : std_logic;
begin
for i in arg'low to arg'high-1 loop
temp := '0';
for j in i+1 to arg'high loop
temp := temp xor arg(j);
end loop;
mybin(i) := arg(i) xor temp;
end loop;
mybin(mybin'high) := arg(arg'high);
return mybin;
end to_unsigned;
function increment (arg : t_gray) return t_gray is
alias xarg : t_gray((arg'length-1) downto 0) is arg;
variable grayinc : t_gray(xarg'range);
variable temp : std_logic;
begin
for i in xarg'range loop
-- rule: high downto i: xnor
-- i-1: and
-- i-2 downto 0: and not
temp := '0';
if i = xarg'high then
temp := xarg(i) xor xarg(i-1);
else
for j in i to arg'high loop
temp := temp xor xarg(j);
end loop;
temp := not(temp);
if i >= 1 then
temp := temp and xarg(i-1);
end if;
end if;
if i >= 2 then
for j in 0 to i-2 loop
temp := temp and not(xarg(j));
end loop;
end if;
grayinc(i) := xarg(i) xor temp;
end loop;
return grayinc;
end increment;
end;
| gpl-3.0 | ebe2b5f31599a16f03f9c6a1af9dc094 | 0.346837 | 5.448217 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_source/dma_bus_pkg.vhd | 5 | 1,033 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package dma_bus_pkg is
type t_dma_req is record
request : std_logic;
read_writen : std_logic;
address : unsigned(15 downto 0);
data : std_logic_vector(7 downto 0);
end record;
type t_dma_resp is record
data : std_logic_vector(7 downto 0);
rack : std_logic;
dack : std_logic;
end record;
constant c_dma_req_init : t_dma_req := (
request => '0',
read_writen => '1',
address => (others => '0'),
data => X"00" );
constant c_dma_resp_init : t_dma_resp := (
data => X"00",
rack => '0',
dack => '0' );
type t_dma_req_array is array(natural range <>) of t_dma_req;
type t_dma_resp_array is array(natural range <>) of t_dma_resp;
end package;
package body dma_bus_pkg is
end package body;
| gpl-3.0 | 37086a2a9071b01dbb3f19dd965f430e | 0.491772 | 3.537671 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/AddDiv2.vhd | 1 | 1,680 | LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_Std.all;
entity bit_AddDiv2 is
port
(
denominator : out std_logic_vector(15 downto 0) := "0000000000110100";
out_bus : out std_logic_vector(15 downto 0);
in_Bus : in std_logic_vector(7 downto 0);
WindowEnable : in std_logic;
clk : in std_logic;
U_enable : std_logic;
TrainFlag: in std_logic;
aclr : in std_logic;
AccumulateSIGNAL: in std_logic;
CalculateSIGNAL: in std_logic;
last_row : in std_logic
);
end bit_AddDiv2;
architecture str_AddDiv1 of bit_AddDiv2 is
signal data_total : std_logic_vector (15 downto 0);
signal DT : integer;
signal add : integer;
begin
TRAINaccumulate: process(clk, TrainFlag, aclr, AccumulateSIGNAL,WindowEnable)
begin
DT <= to_integer(unsigned(in_Bus)); --transform in bus to integer
if (aclr = '1') then
DT <= 0;
add <= 0;
elsif (clk'event) and (clk='0') then
if (TrainFlag='1')and (AccumulateSIGNAL='1') and (WindowEnable ='1') then
add <= add + DT;
end if;
end if;
end process TRAINaccumulate;
TRAINcalculate: process(TrainFlag,CalculateSIGNAL) -- at end of training period do this, but only at start of a frame (and end of Vsync period)
begin
if (CalculateSIGNAL'event) and (CalculateSIGNAL='1') then
data_total <= std_logic_vector(to_unsigned(add, data_total'length)); --s <= std_logic_vector(to_unsigned(i,s'length));
out_bus <= data_total;
if (TrainFlag = '1')then
--here
end if;
end if;
end process TRAINcalculate;
end str_AddDiv1;
--to_integer(unsigned(current_state));
| gpl-2.0 | 9cf4a791fd122110e2ded1ee71753407 | 0.669643 | 3.099631 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_source/boot_700a.vhd | 5 | 9,109 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity boot_700a is
generic (
g_version : unsigned(7 downto 0) := X"02" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end boot_700a;
architecture structural of boot_700a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_boot_rom => true,
g_icap => true,
g_uart => true,
g_cartridge => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
| gpl-3.0 | 47794e7a59f9c8219cfce06be74a94bd | 0.476452 | 3.398881 | false | false | false | false |
KB777/1541UltimateII | fpga/cpu_unit/mblite/hw/core/core_Pkg.vhd | 1 | 18,613 | ----------------------------------------------------------------------------------------------
--
-- Input file : core_Pkg.vhd
-- Design name : core_Pkg
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Package with components and type definitions for the interface
-- of the components
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.std_Pkg.all;
use mblite.config_Pkg.all;
package core_Pkg is
constant C_8_ZEROS : std_logic_vector ( 7 downto 0) := (others => '0');
constant C_16_ZEROS : std_logic_vector (15 downto 0) := (others => '0');
constant C_24_ZEROS : std_logic_vector (23 downto 0) := (others => '0');
constant C_32_ZEROS : std_logic_vector (31 downto 0) := (others => '0');
----------------------------------------------------------------------------------------------
-- TYPES USED IN MB-LITE
----------------------------------------------------------------------------------------------
type alu_operation is (ALU_ADD, ALU_OR, ALU_AND, ALU_XOR, ALU_SHIFT, ALU_SEXT8, ALU_SEXT16, ALU_MUL, ALU_BS);
type src_type_a is (ALU_SRC_REGA, ALU_SRC_NOT_REGA, ALU_SRC_PC, ALU_SRC_SPR);
type src_type_b is (ALU_SRC_REGB, ALU_SRC_NOT_REGB, ALU_SRC_IMM, ALU_SRC_NOT_IMM);
type carry_type is (CARRY_ZERO, CARRY_ONE, CARRY_ALU, CARRY_ARITH);
type carry_keep_type is (CARRY_NOT_KEEP, CARRY_KEEP);
type branch_condition is (NOP, BNC, BEQ, BNE, BLT, BLE, BGT, BGE);
type transfer_size is (WORD, HALFWORD, BYTE);
type msr_update is (NOP, LOAD_MSR, MSR_SET, MSR_CLR, MSR_SET_I, MSR_CLR_I);
type ctrl_execution is record
alu_op : alu_operation;
alu_src_a : src_type_a;
alu_src_b : src_type_b;
operation : std_logic_vector(1 downto 0);
carry : carry_type;
carry_keep : carry_keep_type;
branch_cond : branch_condition;
delay : std_logic;
msr_op : msr_update;
end record;
type ctrl_memory is record
mem_write : std_logic;
mem_read : std_logic;
transfer_size : transfer_size;
end record;
type ctrl_memory_writeback_type is record
mem_read : std_logic;
transfer_size : transfer_size;
end record;
type forward_type is record
reg_d : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
reg_write : std_logic;
end record;
type imem_in_type is record
dat_i : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
ena_i : std_logic;
end record;
type imem_out_type is record
adr_o : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
ena_o : std_logic;
end record;
type fetch_in_type is record
hazard : std_logic;
branch : std_logic;
branch_target : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
end record;
type fetch_out_type is record
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
inst_valid : std_logic;
end record;
type gprf_out_type is record
dat_a_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_b_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_d_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
end record;
type decode_in_type is record
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
inst_valid : std_logic;
ctrl_wrb : forward_type;
ctrl_mem_wrb : ctrl_memory_writeback_type;
mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
interrupt : std_logic;
interrupt_enable: std_logic;
flush_id : std_logic;
end record;
type decode_out_type is record
reg_a : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
reg_b : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
imm : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
hazard : std_logic;
ctrl_ex : ctrl_execution;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
fwd_dec_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
fwd_dec : forward_type;
int_ack : std_logic;
end record;
type gprf_in_type is record
adr_a_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
adr_b_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
adr_d_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
dat_w_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
adr_w_i : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
wre_i : std_logic;
end record;
type execute_out_type is record
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
branch : std_logic;
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
flush_id : std_logic;
interrupt_enable: std_logic;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
end record;
type execute_in_type is record
reg_a : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
dat_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
reg_b : std_logic_vector(CFG_GPRF_SIZE - 1 downto 0);
dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
imm : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
fwd_dec : forward_type;
fwd_dec_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
fwd_mem : forward_type;
ctrl_ex : ctrl_execution;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
ctrl_mem_wrb : ctrl_memory_writeback_type;
mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
end record;
type mem_in_type is record
dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
branch : std_logic;
ctrl_mem : ctrl_memory;
ctrl_wrb : forward_type;
end record;
type mem_out_type is record
alu_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
ctrl_wrb : forward_type;
ctrl_mem_wrb : ctrl_memory_writeback_type;
end record;
type dmem_in_type is record
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
ena_i : std_logic;
end record;
type dmem_out_type is record
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
sel_o : std_logic_vector(3 downto 0);
we_o : std_logic;
ena_o : std_logic;
end record;
type dmem_in_array_type is array(natural range <>) of dmem_in_type;
type dmem_out_array_type is array(natural range <>) of dmem_out_type;
-- WB-master inputs from the wb-slaves
type wb_mst_in_type is record
clk_i : std_logic; -- master clock input
rst_i : std_logic; -- synchronous active high reset
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus input
ack_i : std_logic; -- buscycle acknowledge input
int_i : std_logic; -- interrupt request input
end record;
-- WB-master outputs to the wb-slaves
type wb_mst_out_type is record
adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0); -- address bits
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- databus output
we_o : std_logic; -- write enable output
stb_o : std_logic; -- strobe signals
sel_o : std_logic_vector(3 downto 0); -- select output array
cyc_o : std_logic; -- valid BUS cycle output
end record;
-- WB-slave inputs, from the WB-master
type wb_slv_in_type is record
clk_i : std_logic; -- master clock input
rst_i : std_logic; -- synchronous active high reset
adr_i : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0); -- address bits
dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- Databus input
we_i : std_logic; -- Write enable input
stb_i : std_logic; -- strobe signals / core select signal
sel_i : std_logic_vector(3 downto 0); -- select output array
cyc_i : std_logic; -- valid BUS cycle input
end record;
-- WB-slave outputs to the WB-master
type wb_slv_out_type is record
dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0); -- Databus output
ack_o : std_logic; -- Bus cycle acknowledge output
int_o : std_logic; -- interrupt request output
end record;
----------------------------------------------------------------------------------------------
-- COMPONENTS USED IN MB-LITE
----------------------------------------------------------------------------------------------
component core
generic (
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port (
imem_o : out imem_out_type;
dmem_o : out dmem_out_type;
imem_i : in imem_in_type;
dmem_i : in dmem_in_type;
int_i : in std_logic;
int_o : out std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
component core_wb
generic (
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port (
imem_o : out imem_out_type;
wb_o : out wb_mst_out_type;
imem_i : in imem_in_type;
wb_i : in wb_mst_in_type
);
end component;
component core_wb_adapter
port (
dmem_i : out dmem_in_type;
wb_o : out wb_mst_out_type;
dmem_o : in dmem_out_type;
wb_i : in wb_mst_in_type
);
end component;
component core_wb_async_adapter
port (
dmem_i : out dmem_in_type;
wb_o : out wb_mst_out_type;
dmem_o : in dmem_out_type;
wb_i : in wb_mst_in_type
);
end component;
component fetch
port (
fetch_o : out fetch_out_type;
imem_o : out imem_out_type;
fetch_i : in fetch_in_type;
imem_i : in imem_in_type;
rst_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
component decode
generic (
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_DEBUG : boolean := CFG_DEBUG
);
port (
decode_o : out decode_out_type;
gprf_o : out gprf_out_type;
decode_i : in decode_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
component gprf
port (
gprf_o : out gprf_out_type;
gprf_i : in gprf_in_type;
ena_i : in std_logic;
clk_i : in std_logic
);
end component;
component execute
generic (
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
port (
exec_o : out execute_out_type;
exec_i : in execute_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
component mem
port (
mem_o : out mem_out_type;
dmem_o : out dmem_out_type;
mem_i : in mem_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end component;
component core_address_decoder
generic (
G_NUM_SLAVES : positive := CFG_NUM_SLAVES
);
port (
m_dmem_i : out dmem_in_type;
s_dmem_o : out dmem_out_array_type;
m_dmem_o : in dmem_out_type;
s_dmem_i : in dmem_in_array_type;
clk_i : in std_logic
);
end component;
----------------------------------------------------------------------------------------------
-- FUNCTIONS USED IN MB-LITE
----------------------------------------------------------------------------------------------
function select_register_data (reg_dat, wb_dat : std_logic_vector; write : std_logic) return std_logic_vector;
function forward_condition (reg_write : std_logic; reg_a, reg_d : std_logic_vector) return std_logic;
function align_mem_load (data : std_logic_vector; size : transfer_size; address : std_logic_vector) return std_logic_vector;
function align_mem_store (data : std_logic_vector; size : transfer_size) return std_logic_vector;
function decode_mem_store (address : std_logic_vector(1 downto 0); size : transfer_size) return std_logic_vector;
end core_Pkg;
package body core_Pkg is
-- This function select the register value:
-- A) zero
-- B) bypass value read from register file
-- C) value from register file
function select_register_data (reg_dat, wb_dat : std_logic_vector; write : std_logic) return std_logic_vector is
variable tmp : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
if CFG_REG_FWD_WRB = true and write = '1' then
tmp := wb_dat;
else
tmp := reg_dat;
end if;
return tmp;
end select_register_data;
-- This function checks if a forwarding condition is met. The condition is met of register A and D match
-- and the signal needs to be written back to the register file.
function forward_condition (reg_write : std_logic; reg_a, reg_d : std_logic_vector ) return std_logic is
begin
return reg_write and compare(reg_a, reg_d);
end forward_condition;
-- This function aligns the memory load operation (Big endian decoding).
function align_mem_load (data : std_logic_vector; size : transfer_size; address : std_logic_vector ) return std_logic_vector is
begin
case size is
when byte =>
case address(1 downto 0) is
when "00" => return C_24_ZEROS & data(31 downto 24);
when "01" => return C_24_ZEROS & data(23 downto 16);
when "10" => return C_24_ZEROS & data(15 downto 8);
when "11" => return C_24_ZEROS & data( 7 downto 0);
when others => return C_32_ZEROS;
end case;
when halfword =>
case address(1 downto 0) is
when "00" => return C_16_ZEROS & data(31 downto 16);
when "10" => return C_16_ZEROS & data(15 downto 0);
when others => return C_32_ZEROS;
end case;
when others =>
return data;
end case;
end align_mem_load;
-- This function repeats the operand to all positions in a memory store operation.
function align_mem_store (data : std_logic_vector; size : transfer_size) return std_logic_vector is
begin
case size is
when byte => return data( 7 downto 0) & data( 7 downto 0) & data(7 downto 0) & data(7 downto 0);
when halfword => return data(15 downto 0) & data(15 downto 0);
when others => return data;
end case;
end align_mem_store;
-- This function selects the correct bytes for memory writes (Big endian encoding).
function decode_mem_store (address : std_logic_vector(1 downto 0); size : transfer_size) return std_logic_vector is
begin
case size is
when BYTE =>
case address is
when "00" => return "1000";
when "01" => return "0100";
when "10" => return "0010";
when "11" => return "0001";
when others => return "0000";
end case;
when HALFWORD =>
case address is
-- Big endian encoding
when "10" => return "0011";
when "00" => return "1100";
when others => return "0000";
end case;
when others =>
return "1111";
end case;
end decode_mem_store;
end core_Pkg; | gpl-3.0 | 4696124a35af1d8ed8e01ec1891b5ba3 | 0.51045 | 3.865628 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op970_9.vhdl | 1 | 5,009 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net6,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net6,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias3,
S => net3
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 6e3daaa0651d961ab357c6ddc9a9c1fb | 0.580954 | 3.180317 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/lib/edgedet.vhd | 3 | 3,158 | -------------------------------------------------------------------------------
--
-- Title : sync
-- Design : plk_mn
--
-------------------------------------------------------------------------------
--
-- File : edgedet.vhd
-- Generated : Wed Jul 27 09:33:40 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-11-29 V0.02 zelenkaj omitted out reset
-- 2011-12-12 V0.03 zelenkaj reduced to one FF
-- 2012-07-30 V0.04 zelenkaj reverted to two FFs to reduce glitch
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
ENTITY edgeDet IS
PORT (
din : IN STD_LOGIC;
rising : OUT STD_LOGIC;
falling : OUT STD_LOGIC;
any : OUT STD_LOGIC;
clk : IN STD_LOGIC;
rst : IN STD_LOGIC
);
END ENTITY edgeDet;
ARCHITECTURE rtl OF edgeDet IS
signal RegDin, RegDinL : std_logic;
BEGIN
any <= RegDinL xor RegDin;
falling <= RegDinL and not RegDin;
rising <= not RegDinL and RegDin;
process(clk)
begin
if rising_edge(clk) then
RegDin <= din;
RegDinL <= RegDin;
end if;
end process;
END ARCHITECTURE rtl;
| gpl-2.0 | 5c698b831da92385c7063d47267c1412 | 0.597213 | 4.138925 | false | false | false | false |
KB777/1541UltimateII | fpga/cpu_unit/vhdl_source/mblite_wrapper.vhd | 1 | 3,136 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: mblite_sdram
-- Date:2015-01-02
-- Author: Gideon
-- Description: mblite processor with sdram interface - test module
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
library mblite;
use mblite.core_Pkg.all;
entity mblite_wrapper is
generic (
g_tag_i : std_logic_vector(7 downto 0) := X"20";
g_tag_d : std_logic_vector(7 downto 0) := X"21" );
port (
clock : in std_logic;
reset : in std_logic;
irq_i : in std_logic := '0';
irq_o : out std_logic;
invalidate : in std_logic := '0';
inv_addr : in std_logic_vector(31 downto 0);
io_req : out t_io_req;
io_resp : in t_io_resp;
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32 );
end entity;
architecture arch of mblite_wrapper is
signal dmem_o : dmem_out_type;
signal dmem_i : dmem_in_type;
signal imem_o : dmem_out_type;
signal imem_i : dmem_in_type;
signal dmem_req : t_mem_req_32;
signal dmem_resp : t_mem_resp_32;
signal imem_req : t_mem_req_32;
signal imem_resp : t_mem_resp_32;
begin
i_proc: entity mblite.cached_mblite
port map (
clock => clock,
reset => reset,
invalidate => invalidate,
inv_addr => inv_addr,
dmem_o => dmem_o,
dmem_i => dmem_i,
imem_o => imem_o,
imem_i => imem_i,
irq_i => irq_i,
irq_o => irq_o );
i_imem: entity work.dmem_splitter
generic map (
g_tag => g_tag_i,
g_support_io => false )
port map (
clock => clock,
reset => reset,
dmem_i => imem_i,
dmem_o => imem_o,
mem_req => imem_req,
mem_resp => imem_resp,
io_req => open,
io_resp => c_io_resp_init );
i_dmem: entity work.dmem_splitter
generic map (
g_tag => g_tag_d,
g_support_io => true )
port map (
clock => clock,
reset => reset,
dmem_i => dmem_i,
dmem_o => dmem_o,
mem_req => dmem_req,
mem_resp => dmem_resp,
io_req => io_req,
io_resp => io_resp );
i_arb: entity work.mem_bus_arbiter_pri_32
generic map (
g_registered => false,
g_ports => 2 )
port map (
clock => clock,
reset => reset,
reqs(0) => imem_req,
reqs(1) => dmem_req,
resps(0) => imem_resp,
resps(1) => dmem_resp,
req => mem_req,
resp => mem_resp );
end arch;
| gpl-3.0 | f3c9e0f8ad4a53ab0c228244ca5e14c3 | 0.445791 | 3.5 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/sid_io_regs.vhd | 4 | 4,237 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_io_regs is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_sid_control );
end sid_io_regs;
architecture registers of sid_io_regs is
signal control_i : t_sid_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_base_left =>
control_i.base_left <= unsigned(io_req.data);
when c_sid_base_right =>
control_i.base_right <= unsigned(io_req.data);
when c_sid_snoop_left =>
control_i.snoop_left <= io_req.data(0);
when c_sid_snoop_right =>
control_i.snoop_right <= io_req.data(0);
when c_sid_enable_left =>
control_i.enable_left <= io_req.data(0);
when c_sid_enable_right =>
control_i.enable_right <= io_req.data(0);
when c_sid_extend_left =>
control_i.extend_left <= io_req.data(0);
when c_sid_extend_right =>
control_i.extend_right <= io_req.data(0);
when c_sid_wavesel_left =>
control_i.comb_wave_left <= io_req.data(0);
when c_sid_wavesel_right =>
control_i.comb_wave_right <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_sid_voices =>
io_resp.data <= std_logic_vector(to_unsigned(g_num_voices, 8));
when c_sid_filter_div =>
io_resp.data <= std_logic_vector(to_unsigned(g_filter_div, 8));
when c_sid_base_left =>
io_resp.data <= std_logic_vector(control_i.base_left);
when c_sid_base_right =>
io_resp.data <= std_logic_vector(control_i.base_right);
when c_sid_snoop_left =>
io_resp.data(0) <= control_i.snoop_left;
when c_sid_snoop_right =>
io_resp.data(0) <= control_i.snoop_right;
when c_sid_enable_left =>
io_resp.data(0) <= control_i.enable_left;
when c_sid_enable_right =>
io_resp.data(0) <= control_i.enable_right;
when c_sid_extend_left =>
io_resp.data(0) <= control_i.extend_left;
when c_sid_extend_right =>
io_resp.data(0) <= control_i.extend_right;
when c_sid_wavesel_left =>
io_resp.data(0) <= control_i.comb_wave_left;
when c_sid_wavesel_right =>
io_resp.data(0) <= control_i.comb_wave_right;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_sid_control_init;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 2c8fbcd34fd54ef6909a6e040f717d54 | 0.453859 | 3.880037 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op991_32.vhdl | 1 | 7,489 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
terminal net14: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net10
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net11,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net11
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net12
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net12,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net13,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net13
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net14
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net14,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 8e2a5dfa0f251ef94f47be2ad3e424c5 | 0.570837 | 3.044309 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/reu.vhd | 4 | 18,481 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reu_pkg.all;
use work.mem_bus_pkg.all;
use work.dma_bus_pkg.all;
use work.slot_bus_pkg.all;
-- Standard: 433 LUT/148 FF
-- Extended: 564 LUT/195 FF
entity reu is
generic (
g_ram_tag : std_logic_vector(7 downto 0) := X"10";
g_extended : boolean := true;
g_ram_base : unsigned(27 downto 0) := X"1000000" ); -- second (=upper 16M)
port (
clock : in std_logic;
reset : in std_logic;
-- register interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
-- system interface
phi2_tick : in std_logic := '0';
reu_dma_n : out std_logic := '1';
size_ctrl : in std_logic_vector(2 downto 0) := "001";
enable : in std_logic;
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
dma_req : out t_dma_req;
dma_resp : in t_dma_resp );
end reu;
-- The REU is actually really simple.
-- There are 4 modes of operation, and 4 active states:
-- r = reu read, w = reu write, R = c64 read, W = c64 write
-- Copy from c64 to reu (00): Rw
-- Copy from reu to c64 (01): rW
-- Swap (10): rRwW (RrWw or rRWw or RrwW or rRwW)
-- Verify (11): rR (Rr or rR)
-- The smallest implementation is very likely when only one bit is needed to select between
-- transition options, and reducing the total number of transitions makes sense too.
architecture gideon of reu is
type t_state is (idle, do_read_c64, do_write_c64, do_read_reu, do_write_reu, check_end, delay);
signal state : t_state;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
signal io_wdatau : unsigned(7 downto 0);
signal io_rdata : std_logic_vector(7 downto 0);
signal io_write : std_logic;
signal io_read : std_logic;
signal c64_base : unsigned(15 downto 0) := (others => '0');
signal reu_base : unsigned(23 downto 0) := (others => '0');
signal length_reg : unsigned(23 downto 0) := (others => '1');
signal c64_addr : unsigned(15 downto 0) := (others => '0');
signal reu_addr : unsigned(23 downto 0) := (others => '0');
signal count : unsigned(23 downto 0) := (others => '1');
signal c64_req : std_logic;
signal c64_rack : std_logic;
signal c64_dack : std_logic;
signal reu_req : std_logic;
signal reu_rack : std_logic;
signal reu_dack : std_logic;
signal glob_rwn : std_logic;
signal write_ff00 : std_logic;
signal masked_reu_addr : unsigned(23 downto 0);
signal mask : unsigned(7 downto 0);
signal c64_read_reg : std_logic_vector(7 downto 0) := (others => '0');
signal reu_read_reg : std_logic_vector(7 downto 0) := (others => '0');
signal verify_error : std_logic;
signal trans_done : std_logic;
signal irq_pend : std_logic;
signal reserved : std_logic_vector(2 downto 0);
type t_control is record
irq_en : std_logic;
irq_done : std_logic;
irq_error : std_logic;
fix_reu : std_logic;
fix_c64 : std_logic;
end record;
type t_command is record
execute : std_logic;
autoload : std_logic;
ff00 : std_logic;
mode : std_logic_vector(1 downto 0);
end record;
constant c_control_def : t_control := (others => '0');
constant c_command_def : t_command := (
mode => "00",
execute => '0',
ff00 => '1',
autoload => '0' );
signal control : t_control;
signal command : t_command;
-- signals for extended mode
signal rate_div : unsigned(7 downto 0) := (others => '0');
signal start_delay : unsigned(7 downto 0) := (others => '0');
signal ext_count : unsigned(7 downto 0) := (others => '0');
begin
write_ff00 <= '1' when slot_req.late_write='1' and slot_req.io_address=X"FF00" else '0';
with size_ctrl select mask <=
"00000001" when "000",
"00000011" when "001",
"00000111" when "010",
"00001111" when "011",
"00011111" when "100",
"00111111" when "101",
"01111111" when "110",
"11111111" when others;
masked_reu_addr(23 downto 19) <= (reu_base(23 downto 19) and mask(7 downto 3)) when not g_extended else
(reu_addr(23 downto 19) and mask(7 downto 3));
masked_reu_addr(18 downto 16) <= (reu_addr(18 downto 16) and mask(2 downto 0));
masked_reu_addr(15 downto 0) <= reu_addr(15 downto 0);
reu_rack <= '1' when mem_resp.rack_tag = g_ram_tag else '0';
reu_dack <= '1' when mem_resp.dack_tag = g_ram_tag else '0';
io_wdatau <= unsigned(slot_req.data);
-- fill mem request structure
mem_req.tag <= g_ram_tag;
mem_req.request <= reu_req;
mem_req.address <= g_ram_base(25 downto 24) & masked_reu_addr;
mem_req.read_writen <= glob_rwn;
mem_req.data <= c64_read_reg;
mem_req.size <= "00"; -- 1 byte at a time
-- fill dma request structure
dma_req.request <= c64_req;
dma_req.address <= c64_addr;
dma_req.read_writen <= glob_rwn;
dma_req.data <= reu_read_reg;
c64_rack <= dma_resp.rack;
c64_dack <= dma_resp.dack;
p_main: process(clock)
procedure next_address is
begin
if control.fix_c64='0' then
c64_addr <= c64_addr + 1;
end if;
if control.fix_reu='0' then
reu_addr <= reu_addr + 1;
end if;
if (count(15 downto 0) = 1 and not g_extended) or
(count = 1 and g_extended) then
trans_done <= '1';
else
count <= count - 1;
end if;
end procedure;
procedure transfer_end is
begin
if command.autoload='1' then
c64_addr <= c64_base;
reu_addr <= reu_base(reu_addr'range);
if g_extended then
count <= length_reg;
else
count(15 downto 0) <= length_reg(15 downto 0);
end if;
end if;
command.ff00 <= '1'; -- reset to default state
state <= idle;
end procedure;
procedure dispatch is
begin
glob_rwn <= '1'; -- we're going to read.
case command.mode is
when c_mode_toreu => -- C64 to REU
c64_req <= '1';
state <= do_read_c64;
when others => -- in all other cases, read reu first
reu_req <= '1';
state <= do_read_reu;
end case;
end procedure;
begin
if rising_edge(clock) then
if io_write='1' then --$DF00-$DF1F, decoded below in a concurrent statement
case slot_req.io_address(4 downto 0) is
when c_c64base_l => c64_base(7 downto 0) <= io_wdatau;
c64_addr <= c64_base(15 downto 8) & io_wdatau; -- half autoload bug
when c_c64base_h => c64_base(15 downto 8) <= io_wdatau;
c64_addr <= io_wdatau & c64_base(7 downto 0); -- half autoload bug
when c_reubase_l => reu_base(7 downto 0) <= io_wdatau;
reu_addr(15 downto 0) <= reu_base(15 downto 8) & io_wdatau; -- half autoload bug
when c_reubase_m => reu_base(15 downto 8) <= io_wdatau;
reu_addr(15 downto 0) <= io_wdatau & reu_base(7 downto 0); -- half autoload bug
when c_reubase_h => reu_base(23 downto 16) <= io_wdatau;
reu_addr(23 downto 16) <= io_wdatau;
when c_translen_l => length_reg(7 downto 0) <= io_wdatau;
count(15 downto 0) <= length_reg(15 downto 8) & io_wdatau; -- half autoload bug
when c_translen_h => length_reg(15 downto 8) <= io_wdatau;
count(15 downto 0) <= io_wdatau & length_reg(7 downto 0); -- half autoload bug
when c_irqmask =>
control.irq_en <= io_wdatau(7);
control.irq_done <= io_wdatau(6);
control.irq_error <= io_wdatau(5);
when c_control =>
control.fix_reu <= io_wdatau(6);
control.fix_c64 <= io_wdatau(7);
when c_command =>
command.execute <= io_wdatau(7);
reserved(2) <= io_wdatau(6);
command.autoload <= io_wdatau(5);
command.ff00 <= io_wdatau(4);
reserved(1) <= io_wdatau(3);
reserved(0) <= io_wdatau(2);
command.mode <= slot_req.data(1 downto 0);
when others =>
null;
end case;
end if;
-- extended registers
if io_write='1' and g_extended then --$DF00-$DF1F, decoded below in a concurrent statement
case slot_req.io_address(4 downto 0) is
when c_start_delay =>
start_delay <= io_wdatau;
when c_rate_div =>
rate_div <= io_wdatau;
when c_translen_x =>
length_reg(23 downto 16) <= io_wdatau;
count(23 downto 16) <= io_wdatau;
when others =>
null;
end case;
end if;
-- clear on read flags
if io_read='1' then
if slot_req.io_address(4 downto 0) = c_status then
verify_error <= '0';
trans_done <= '0';
end if;
end if;
case state is
when idle =>
reu_dma_n <= '1';
glob_rwn <= '1';
ext_count <= start_delay;
if command.execute='1' then
if (command.ff00='0' and write_ff00='1') or
(command.ff00='1') then
verify_error <= '0';
trans_done <= '0';
command.execute <= '0';
if g_extended then
state <= delay;
else
dispatch;
reu_dma_n <= '0';
end if;
end if;
end if;
when delay =>
if ext_count = 0 then
dispatch;
reu_dma_n <= '0';
elsif phi2_tick='1' then
ext_count <= ext_count - 1;
end if;
when do_read_reu =>
if reu_rack='1' then
reu_req <= '0';
end if;
if reu_dack='1' then
reu_read_reg <= mem_resp.data;
case command.mode is
when c_mode_swap | c_mode_verify =>
c64_req <= '1';
glob_rwn <= '1';
state <= do_read_c64;
when others =>
c64_req <= '1';
glob_rwn <= '0';
state <= do_write_c64;
end case;
end if;
when do_write_c64 =>
if c64_rack='1' then
c64_req <= '0';
next_address;
state <= check_end;
end if;
when do_read_c64 =>
if c64_rack='1' then
c64_req <= '0';
end if;
if c64_dack='1' then
c64_read_reg <= dma_resp.data;
case command.mode is
when c_mode_verify =>
if dma_resp.data /= reu_read_reg then
verify_error <= '1';
state <= idle;
else
next_address;
state <= check_end;
end if;
when others =>
reu_req <= '1';
glob_rwn <= '0';
state <= do_write_reu;
end case;
end if;
when do_write_reu =>
if reu_rack='1' then
reu_req <= '0';
case command.mode is
when c_mode_swap =>
c64_req <= '1';
glob_rwn <= '0';
state <= do_write_c64;
when others =>
next_address;
state <= check_end;
end case;
end if;
when check_end =>
ext_count <= rate_div;
if trans_done='1' then
transfer_end;
elsif g_extended then
state <= delay;
else
dispatch;
end if;
when others =>
null;
end case;
if reset='1' then
reu_req <= '0';
c64_req <= '0';
glob_rwn <= '1';
control <= c_control_def;
command <= c_command_def;
state <= idle;
reserved <= (others => '0');
verify_error <= '0';
trans_done <= '0';
reu_dma_n <= '1';
c64_base <= (others => '0');
reu_base <= (others => '0');
length_reg <= X"00FFFF";
c64_addr <= (others => '0');
reu_addr <= (others => '0');
count <= (others => '1');
rate_div <= (others => '0');
start_delay <= (others => '0');
rate_div <= (others => '0');
ext_count <= (others => '0');
end if;
end if;
end process;
p_read: process(slot_req, control, command, count, c64_addr, reu_addr, verify_error, trans_done, irq_pend,
c64_base, reu_base, length_reg, reserved, mask, start_delay, rate_div)
begin
io_rdata <= X"FF";
case slot_req.bus_address(4 downto 0) is
when c_status =>
io_rdata(7) <= irq_pend;
io_rdata(6) <= trans_done;
io_rdata(5) <= verify_error;
io_rdata(4) <= mask(1); -- for 256k and larger, this is set to '1'.
io_rdata(3 downto 0) <= X"0"; -- version
when c_command =>
io_rdata(7) <= command.execute;
io_rdata(6) <= reserved(2);
io_rdata(5) <= command.autoload;
io_rdata(4) <= command.ff00;
io_rdata(3 downto 2) <= reserved(1 downto 0);
io_rdata(1 downto 0) <= command.mode;
when c_irqmask =>
io_rdata(7) <= control.irq_en;
io_rdata(6) <= control.irq_done;
io_rdata(5) <= control.irq_error;
when c_control =>
io_rdata(7) <= control.fix_c64;
io_rdata(6) <= control.fix_reu;
when c_c64base_l => io_rdata <= std_logic_vector(c64_addr(7 downto 0));
when c_c64base_h => io_rdata <= std_logic_vector(c64_addr(15 downto 8));
when c_reubase_l => io_rdata <= std_logic_vector(reu_addr(7 downto 0));
when c_reubase_m => io_rdata <= std_logic_vector(reu_addr(15 downto 8));
when c_reubase_h =>
if g_extended then
io_rdata <= std_logic_vector(reu_addr(23 downto 16));
else
io_rdata <= "11111" & std_logic_vector(reu_addr(18 downto 16)); -- maximum 19 bits
end if;
when c_translen_l => io_rdata <= std_logic_vector(count(7 downto 0));
when c_translen_h => io_rdata <= std_logic_vector(count(15 downto 8));
when c_size_read => if g_extended then io_rdata <= std_logic_vector(mask); end if;
when c_start_delay => if g_extended then io_rdata <= std_logic_vector(start_delay); end if;
when c_rate_div => if g_extended then io_rdata <= std_logic_vector(rate_div); end if;
when others =>
null;
end case;
end process;
irq_pend <= control.irq_en and ((control.irq_done and trans_done) or (control.irq_error and verify_error));
slot_resp.irq <= irq_pend;
slot_resp.data <= io_rdata;
slot_resp.reg_output <= enable when slot_req.bus_address(8 downto 5)=X"8" and
slot_req.bus_address(4 downto 2)/="111" and
(state = idle)
else '0';
io_write <= (enable and slot_req.io_write) when slot_req.io_address(8 downto 5)=X"8" else '0';
io_read <= (enable and slot_req.io_read) when slot_req.io_address(8 downto 5)=X"8" else '0';
end gideon;
| gpl-3.0 | 391d50a4bb3592c7bc18652865c72c02 | 0.436394 | 3.930455 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/lpm_compare1.vhd | 1 | 3,968 | -- megafunction wizard: %LPM_COMPARE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_compare
-- ============================================================
-- File Name: lpm_compare1.vhd
-- Megafunction Name(s):
-- lpm_compare
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_compare1 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (30 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (30 DOWNTO 0);
AleB : OUT STD_LOGIC
);
END lpm_compare1;
ARCHITECTURE SYN OF lpm_compare1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
COMPONENT lpm_compare
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (30 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (30 DOWNTO 0);
AleB : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
AleB <= sub_wire0;
lpm_compare_component : lpm_compare
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "LPM_COMPARE",
lpm_width => 31
)
PORT MAP (
dataa => dataa,
datab => datab,
AleB => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: AeqB NUMERIC "0"
-- Retrieval info: PRIVATE: AgeB NUMERIC "0"
-- Retrieval info: PRIVATE: AgtB NUMERIC "0"
-- Retrieval info: PRIVATE: AleB NUMERIC "1"
-- Retrieval info: PRIVATE: AltB NUMERIC "0"
-- Retrieval info: PRIVATE: AneB NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: PortBValue NUMERIC "0"
-- Retrieval info: PRIVATE: Radix NUMERIC "10"
-- Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "31"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "31"
-- Retrieval info: USED_PORT: AleB 0 0 0 0 OUTPUT NODEFVAL AleB
-- Retrieval info: USED_PORT: dataa 0 0 31 0 INPUT NODEFVAL dataa[30..0]
-- Retrieval info: USED_PORT: datab 0 0 31 0 INPUT NODEFVAL datab[30..0]
-- Retrieval info: CONNECT: AleB 0 0 0 0 @AleB 0 0 0 0
-- Retrieval info: CONNECT: @dataa 0 0 31 0 dataa 0 0 31 0
-- Retrieval info: CONNECT: @datab 0 0 31 0 datab 0 0 31 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_compare1_inst.vhd TRUE
| gpl-2.0 | c5646e3cee8edd2b5a5cc4ac1efd4c39 | 0.65121 | 3.81172 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op962_3.vhdl | 1 | 4,111 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias4: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net3,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_3,
scope => Wprivate
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net4,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | fe91f555296d48c6a4f826457c09c2f4 | 0.585989 | 3.257528 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_sim/tb_floppy_stream.vhd | 4 | 4,531 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : tb_floppy_stream.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.floppy_emu_pkg.all;
entity tb_floppy_stream is
end tb_floppy_stream;
architecture tb of tb_floppy_stream is
signal clock : std_logic := '0';
signal clock_en : std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
signal reset : std_logic;
signal drv_rdata : std_logic_vector(7 downto 0) := X"01";
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal track : std_logic_vector(6 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal read_data : std_logic_vector(7 downto 0);
signal write_data : std_logic_vector(7 downto 0) := X"55";
signal fifo_put : std_logic;
signal fifo_command : std_logic_vector(2 downto 0);
signal fifo_parameter : std_logic_vector(10 downto 0);
type t_buffer_array is array (natural range <>) of std_logic_vector(7 downto 0);
shared variable my_buffer : t_buffer_array(0 to 15) := (others => X"FF");
type t_integer_array is array (natural range <>) of integer;
constant rate_table : t_integer_array(0 to 63) := (
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
2, 2, 2, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 );
begin
clock <= not clock after 31.25 ns;
reset <= '1', '0' after 400 ns;
process
begin
wait until clock='1';
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
end process;
mut: entity work.floppy_stream
port map (
clock => clock,
clock_en => clock_en, -- combi clk/cke that yields 4 MHz; eg. 16/4
reset => reset,
drv_rdata => drv_rdata,
floppy_inserted => '1',
write_data => write_data,
fifo_put => fifo_put,
fifo_command => fifo_command,
fifo_parameter => fifo_parameter,
track => track,
motor_on => motor_on,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
soe => soe,
rate_ctrl => rate_ctrl,
read_data => read_data );
test: process
begin
motor_on <= '1';
mode <= '1';
write_prot_n <= '1';
soe <= '1';
wait for 700 us;
mode <= '0'; -- switch to write
wait;
end process;
fill: process
begin
wait until fifo_put='1';
wait for 10 ns;
if fifo_command = c_cmd_next then
drv_rdata <= drv_rdata + 1;
end if;
end process;
move: process
begin
wait for 2 us;
for i in 0 to 100 loop
step <= step + 1;
wait for 2 us;
end loop;
wait for 2 us;
for i in 0 to 100 loop
step <= step - 1;
wait for 2 us;
end loop;
end process;
rate_ctrl <= conv_std_logic_vector(rate_table(conv_integer(track(6 downto 1))), 2);
end tb; | gpl-3.0 | 3fbcdba48a689e6d0b2a8234677eeb16 | 0.443169 | 3.895959 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op982_13.vhdl | 1 | 5,463 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net7
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net7,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net8,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | b6b5365ab115fef695f9aeab97eaa5c3 | 0.578071 | 3.145078 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op324_0.vhdl | 1 | 3,877 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => out1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net1
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net3
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net3,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 994446073da76bf5ca9918cdd046dcd8 | 0.589373 | 3.285593 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op978_17.vhdl | 1 | 6,411 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias2,
S => net7
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias2,
S => net9
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net9,
G => net2,
S => vdd
);
subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net10,
G => net2,
S => vdd
);
subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net10
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net11
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net11,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net12,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net12
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 406b8d8826f80dc92620cce349a90ed9 | 0.577445 | 3.110626 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/tb_DescriptorMaker.vhd | 1 | 3,021 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:54:53 05/28/2014
-- Design Name:
-- Module Name: /media/DATA42/Dropbox/EmbeddedRetina/embeddedretina_ise/tb_DescriptorMaker.vhd
-- Project Name: EmbeddedRetina_ISE
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: DescriptorMaker
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_DescriptorMaker IS
END tb_DescriptorMaker;
ARCHITECTURE behavior OF tb_DescriptorMaker IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT DescriptorMaker
PORT(
clk : IN std_logic;
rst : IN std_logic;
pointIndexs1 : IN std_logic_vector(15 downto 0);
pointIndexs2 : IN std_logic_vector(15 downto 0);
enableInPointSet : IN std_logic;
pointSet : IN std_logic_vector(42 downto 0);
descriptor : OUT std_logic_vector(511 downto 0);
enableOut : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal pointIndexs1 : std_logic_vector(15 downto 0) := (others => '0');
signal pointIndexs2 : std_logic_vector(15 downto 0) := (others => '0');
signal enableInPointSet : std_logic := '0';
signal pointSet : std_logic_vector(42 downto 0) := (others => '0');
--Outputs
signal descriptor : std_logic_vector(511 downto 0);
signal enableOut : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: DescriptorMaker PORT MAP (
clk => clk,
rst => rst,
pointIndexs1 => pointIndexs1,
pointIndexs2 => pointIndexs2,
enableInPointSet => enableInPointSet,
pointSet => pointSet,
descriptor => descriptor,
enableOut => enableOut
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | d3c4277a740bfd8534027c6c38ad81ff | 0.61238 | 3.923377 | false | true | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/IntermediateRegsConv.vhd | 1 | 3,137 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_F8MKfI
-- /___/ /\ Timestamp : 04/05/2014 20:58:17
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity IntermediateRegsConv is
port ( clk : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_VERT_CONV_BW-1 downto 0);
rst : in std_logic;
enableOut : out std_logic;
outputData : out T_INPUT_HORIZONTAL_CONVOLUTION
);
end IntermediateRegsConv;
architecture BEHAVIORAL of IntermediateRegsConv is
--type T_SCALE_VALUES_FIFO is array std_logic_vector(NUMBER_OF_SCALES-1 downto 0) of std_logic_vector(OUT_VERT_CONV_BW-1 downto 0);
signal intermediate_registers: T_INPUT_HORIZONTAL_CONVOLUTION := (others =>(others => '0'));
signal counter: integer range 0 to KERNEL_SIZE-1 := 0;
begin
proceso1: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
intermediate_registers <= (others => (others => '0'));
counter <= 0;
enableOut <= '0';
elsif enableIn = '1' then
intermediate_registers(0) <= inputValue;
loop1: for i in 1 to KERNEL_SIZE-1 loop
intermediate_registers(i) <= intermediate_registers(i-1);
end loop loop1;
if counter = KERNEL_SIZE-1 then
counter <= 0;
enableOut <= '1';
else
counter <= counter + 1;
enableOut <= '0';
end if;
else
enableOut <= '0';
end if;
end if;--end if rising_edge(clk)
end process proceso1;
outputData <= intermediate_registers;
end BEHAVIORAL;
| gpl-3.0 | 7fa18ae933e7e21c0bccd5d6e455e7f4 | 0.572522 | 3.834963 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_source/ulpi_bus.vhd | 1 | 8,362 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
operational : in std_logic := '1';
-- chirp interface
do_chirp : in std_logic := '0';
chirp_data : in std_logic := '0';
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of ulpi_bus : entity is "yes";
end ulpi_bus;
architecture gideon of ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
signal bus_has_our_data : std_logic;
type t_state is ( idle, chirp, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1 and operational;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d3;
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif do_chirp='1' then
if ULPI_DIR='0' then
ulpi_last <= '0';
state <= chirp;
end if;
ulpi_data_out <= X"40"; -- PIDless packet
elsif tx_valid = '1' and tx_start = '1' then
if ULPI_DIR='0' then
ulpi_last <= tx_last;
state <= transmit;
end if;
ulpi_data_out <= tx_data;
end if;
when chirp =>
if ULPI_NXT = '1' then
if do_chirp = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= (others => chirp_data);
end if;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_DIR='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
elsif ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
when writing_data =>
if ULPI_DIR='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
elsif ULPI_NXT='1' then
ulpi_data_out <= X"00";
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '1';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write, bus_has_our_data)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start; -- first byte is transferred to register
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and bus_has_our_data and tx_valid and not ulpi_last; -- phy accepted this data.
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when bus_has_our_data = '1' else (others => 'Z');
bus_has_our_data <= '1' when ULPI_DIR='0' and ulpi_dir_d1='0' else '0';
end gideon;
| gpl-3.0 | d2e694a20fb6cc287dd28bd4cb4acacd | 0.437814 | 3.816522 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op982_17.vhdl | 1 | 6,411 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias2,
S => net7
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net7,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net8
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias2,
S => net9
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net4,
S => vdd
);
subnet0_subnet4_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => vdd
);
subnet0_subnet4_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net10
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net11
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net11,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net12,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net12
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | ccae992f63a81eb32479b8799d8bc8d8 | 0.577445 | 3.110626 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/fall_through/vhdl_source/fall_through_add_on.vhd | 5 | 2,208 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : fall_through_add_on
-------------------------------------------------------------------------------
-- Description: fall_through_add_on, one position deep fifo-add-on
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity fall_through_add_on is
generic (
g_data_width : natural := 32);
port (
clock : in std_logic;
reset : in std_logic;
-- fifo side
rd_dout : in std_logic_vector(g_data_width - 1 downto 0);
rd_empty : in std_logic;
rd_en : out std_logic;
-- consumer side
data_out : out std_logic_vector(g_data_width - 1 downto 0);
data_valid : out std_logic;
data_next : in std_logic);
end fall_through_add_on;
architecture structural of fall_through_add_on is
type t_state is (empty, full);
signal state : t_state;
begin -- structural
fsm : process (clock)
begin -- process fsm
if clock'event and clock = '1' then -- rising clock edge
case state is
when empty =>
if rd_empty = '0' then
state <= full;
end if;
when full =>
if data_next = '1' and rd_empty = '1' then
state <= empty;
end if;
when others => null;
end case;
if reset = '1' then -- synchronous reset (active high)
state <= empty;
end if;
end if;
end process fsm;
data_valid <= '1' when state = full else
'0';
rd_en <= '1' when ((state = empty and rd_empty = '0') or
(state = full and rd_empty = '0' and data_next = '1')) else
'0';
data_out <= rd_dout;
end structural;
| gpl-3.0 | 1b9e83804c445407b84d68467759acc2 | 0.405797 | 4.506122 | false | false | false | false |
KB777/1541UltimateII | fpga/ip/nano_cpu/vhdl_source/nano.vhd | 1 | 8,347 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity nano is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : out unsigned(7 downto 0);
io_write : out std_logic;
io_read : out std_logic;
io_wdata : out std_logic_vector(15 downto 0);
io_rdata : in std_logic_vector(15 downto 0);
stall : in std_logic;
-- system interface (to write code into the nano)
sys_clock : in std_logic := '0';
sys_reset : in std_logic := '0';
sys_io_req : in t_io_req := c_io_req_init;
sys_io_resp : out t_io_resp );
end entity;
architecture structural of nano is
signal sys_enable : std_logic;
signal sys_bram_addr : std_logic_vector(10 downto 0);
-- instruction/data ram
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_en : std_logic;
signal ram_we : std_logic;
signal ram_wdata : std_logic_vector(15 downto 0);
signal ram_rdata : std_logic_vector(15 downto 0);
signal sys_io_req_bram : t_io_req;
signal sys_io_resp_bram : t_io_resp;
signal sys_io_req_regs : t_io_req;
signal sys_io_resp_regs : t_io_resp;
signal sys_core_reset : std_logic;
signal usb_reset_tig : std_logic;
signal usb_core_reset : std_logic;
signal bram_reset : std_logic;
signal bram_data : std_logic_vector(7 downto 0);
begin
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 11,
g_ports => 2 )
port map (
clock => sys_clock,
req => sys_io_req,
resp => sys_io_resp,
reqs(0) => sys_io_req_bram,
reqs(1) => sys_io_req_regs,
resps(0) => sys_io_resp_bram,
resps(1) => sys_io_resp_regs );
i_core: entity work.nano_cpu
port map (
clock => clock,
reset => usb_core_reset,
-- instruction/data ram
ram_addr => ram_addr,
ram_en => ram_en,
ram_we => ram_we,
ram_wdata => ram_wdata,
ram_rdata => ram_rdata,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_read => io_read,
io_wdata => io_wdata,
io_rdata => io_rdata,
stall => stall );
i_buf_ram: RAMB16_S9_S18
generic map (
INIT_00 => X"A028A02783E60AA7E8C1A0CA0AC3C0180BFFA03783E60AA4A0C40AB9A0CA0AB2",
INIT_01 => X"E84D0AB0C0262AB27893E026A0CA0AAEE00B83E683FD0AA4C0100BFDE9EAE8F7",
INIT_02 => X"0AA4C8352AA7783FE84D08F5A0C40AC1A0CA0AC3E028A0CA0AB2C0262AA67893",
INIT_03 => X"C03CE854C8420BFDA02883E60AA5A03EA0263AA55AA5E028C0312AA7783F83E6",
INIT_04 => X"08ECE8E780ECE05AA03EE84D0AA6A02783E60AA7E8AA83E683FD0AA4E028A028",
INIT_05 => X"C8630BFCC8420BFDC840E854B800A03783E6A03ED859783EB800C84E80EC5AA5",
INIT_06 => X"C87E52A60BFEA0C488CA80CA4AC92AA70BFEA03783E61AA80BE6E05AE9EAE8F7",
INIT_07 => X"C828E854A03EE074E8E7C87D2AA7783F80CA5AA5C07D08CA80CA0AB0A0260AA5",
INIT_08 => X"E099C87E52A52AA7783FE8E7C87E52A52AA7783FC8900BFEC09A0BFCC8420BFD",
INIT_09 => X"E8C1A030E84D0AB8A020A031A025C87E52A62AA7783FE8E7C87E52A62AA7783F",
INIT_0A => X"E0B283FE0AA4C0B02AA6783FE05A83E62ACB0BE6E8E7E8E7A027D8A15AA50ABB",
INIT_0B => X"80EC5AA508ECE8E7D0CB7839C0E10BFEA039A02980EC0ACAA0C40ABC83FE0AA5",
INIT_0C => X"08F6A020A03183FE0AA60000B800A03EA0C488CA80CA4AC62AA7A0260BFEC8BA",
INIT_0D => X"0AA7A030E0D1C8DB5AA50AC7A021C0DE80EC5AA508ECC8D35AA50AC7A03180EC",
INIT_0E => X"00400045004600000000B800D8E85AA50ABDE0C1C8E180EC5AA508ECE8E780EC",
INIT_0F => X"81E10BF281E00BF181DF0BF0B800C8FA0BF0004B15E000500055005500560050",
INIT_10 => X"B80083F00AA483F209E183F709E6E91081E50BF681E40BF581E30BF481E20BF3",
INIT_11 => X"A06309E5A06109DEA07009E4A07109E3D18B09DF81DC0AA481DB0AA7A06209E0",
INIT_12 => X"C96F52B6C13B52B5C14252B4C14852A42AAA81E6D9247864C93509E5A06009DF",
INIT_13 => X"09DFA0631AAD09E5E8E7C93052B12AAA81E6D9357864E11C81DB5AA5C16F09DB",
INIT_14 => X"2ABA39E609DF81DB0AA781DD2ACD09E6E16FC91C2AB309DFC91C09DCE124A060",
INIT_15 => X"49DD09DCA0724AA7C16109DDA07409DED956783DC1612AB609DF81DD0AA4C153",
INIT_16 => X"783DD91C51E209DDD16FC16F81E159DD09E181DE4AB609DE81DF3ABA09DF81DC",
INIT_17 => X"4AA781DD09E2D17E51E209E1A07409DE81E72AA7A07009E4A07109E3B800D96F",
INIT_18 => X"19DE1AB4C98F09DDE972B80081E36AA409E381E449DD09E4A0734AA749E72ACC",
INIT_19 => X"09E5E972C19F81E159DD09E181DE4AB609DEA06009DFD993783DA06309E5A061",
INIT_1A => X"81E6D9AD7864E1CA52B6C1D252B4C1D852B5C1C052B12AAA81E6D9A17864C9AD",
INIT_1B => X"E1D581DB5AA5C1CA09DBE1A1A0602AB709DFE8E7A0631AAD09E5C9CA52B12AAA",
INIT_1C => X"18EB2AAB09E680EB2ABA09DFC98C09E181DC49DD09DC81DB0AA781DF3ABA09DF",
INIT_1D => X"00000000000000000000E1B6C1C009E5E1A1A06009DFC1CA2AB309DFB80081E6",
INIT_1E => X"80EB89E881E90AA481E80AC00000000000000000000000000000000000000000",
INIT_1F => X"00000000B800C9EE52BF81E84AAC09E881E94AA509E9CA012ABEC9EE50EB89E8",
INIT_20 => X"DA1F51FE59FF783B81FF88EB80EB4AA909E881FE88EB80EB4AA809E881DF0000",
INIT_21 => X"783BB80090EB09FE80EB4AA409E881FEB80090EB09FE80EB4AA909E881FEE1F5",
INIT_22 => X"81E36AA409E381E449E40A00E1F5CA4B2AB189E8CA312AB409DFC1F5EA92EA11",
INIT_23 => X"09DFE910EA70EA2AEA2AEA2A81E36AA40BE481E44BE58200EA88C1F5EA85B800",
INIT_24 => X"6AA40BE081E44BE30BE1E1F5EA8DA028EA9709DCEA9719E90A00C26509DCEA18",
INIT_25 => X"83E34AAF0BE3A028EA9709DCEA9719E90BE3C26509DCEA1809DFE910EA7081E3",
INIT_26 => X"E1F5A028EA9709E6EA9719E90AC8C1F552B42AAA09E6E1F583E30AA4C9F553E2",
INIT_27 => X"09E881E288EB80EB4AA709E881E188EB80EB4AA609E881E088EB80EB4AA509E8",
INIT_28 => X"2AC44AA50BFAB8008AA382A34AC20BFAB8003BFA0BFBB80081E588EB80EB4AB2",
INIT_29 => X"2AC54AA50BF992A30AA282A34ABF0BF982A2B8003BF82AC54AA50BF9B80083FA",
INIT_2A => X"0010000E00800008F7FF700000050004000300020001000000000000B80083F9",
INIT_2B => X"0320FDFF0751005000200800004500A0FFBF4000300020000400000610000FA0",
INIT_2C => X"0000000003FFFFFCFFFB007800F1FFF002EE00ED007F003F006603A0006102E0",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKB => clock,
SSRB => reset,
ENB => ram_en,
WEB => ram_we,
ADDRB => ram_addr,
DIB => ram_wdata,
DIPB => "00",
DOB => ram_rdata,
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_enable,
WEA => sys_io_req_bram.write,
ADDRA => sys_bram_addr,
DIA => sys_io_req_bram.data,
DIPA => "0",
DOA => bram_data );
sys_bram_addr(10 downto 1) <= std_logic_vector(sys_io_req_bram.address(10 downto 1));
sys_bram_addr(0) <= not sys_io_req_bram.address(0);
sys_enable <= sys_io_req_bram.write or sys_io_req_bram.read;
bram_reset <= not sys_enable;
sys_io_resp_bram.data <= bram_data when sys_io_resp_bram.ack = '1' else X"00";
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_io_resp_bram.ack <= sys_enable;
sys_io_resp_regs <= c_io_resp_init;
sys_io_resp_regs.ack <= sys_io_req_regs.write or sys_io_req_regs.read;
if sys_io_req_regs.write = '1' then -- any address
sys_core_reset <= not sys_io_req_regs.data(0);
end if;
if sys_reset = '1' then
sys_core_reset <= '1';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
usb_reset_tig <= sys_core_reset;
usb_core_reset <= usb_reset_tig;
end if;
end process;
end architecture;
| gpl-3.0 | 910894c7a546b38fa28e547bb4df48dd | 0.651132 | 2.598692 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op330_5sk1_0.vhdl | 1 | 7,284 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.9e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.9e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 2.995e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.71e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net2,
G => vbias3,
S => net6
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.4e-06,
W => Wcm_2,
Wcm_2init => 1.3e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.4e-06,
W => Wcmout_2,
Wcmout_2init => 3.32e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net7,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.71e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias3,
S => net7
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.71e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.4e-06,
W => Wcm_2,
Wcm_2init => 1.3e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.4e-06,
W => Wcmout_2,
Wcmout_2init => 3.32e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcmcasc_2,
Wcmcasc_2init => 6.71e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 3e-06,
W => Wcm_1,
Wcm_1init => 7.835e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 3e-06,
W => Wcmout_1,
Wcmout_1init => 3.795e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 3.05e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 3.05e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 3.05e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 3.05e-06
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 3.05e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 3.05e-06
)
port map(
D => net10,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net11,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net11,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net11,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | bd9fd940278e1e04039632c77b00f828 | 0.582784 | 2.919439 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op980_17.vhdl | 1 | 7,747 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
terminal net14: electrical;
terminal net15: electrical;
terminal net16: electrical;
terminal net17: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias2,
S => net7
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias2,
S => net9
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net9,
G => net2,
S => vdd
);
subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net10,
G => net2,
S => vdd
);
subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net10
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net11
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net11,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net12,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net12
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net13
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net13,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net14,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net14
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net15
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net15,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net16,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net16
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net17
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net17,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | fc391671d812fe91a4cf9a94ff9f0501 | 0.573383 | 3.063266 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/uart_lite/vhdl_source/uart_peripheral_zpu.vhd | 5 | 4,794 | library ieee;
use ieee.std_logic_1164.all;
entity uart_peripheral_zpu is
generic (
tx_fifo : boolean := true;
divisor : natural := 417 );
port (
clock : in std_logic;
reset : in std_logic;
bus_read : in std_logic;
bus_write : in std_logic;
bus_rack : out std_logic;
bus_dack : out std_logic;
bus_addr : in std_logic_vector(3 downto 2);
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
uart_irq : out std_logic;
txd : out std_logic;
rxd : in std_logic );
end uart_peripheral_zpu;
architecture gideon of uart_peripheral_zpu is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxfifo_get : std_logic;
signal rxfifo_dout : std_logic_vector(7 downto 0);
signal rxfifo_full : std_logic;
signal rxfifo_dav : std_logic;
signal overflow : std_logic;
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(7 downto 6);
signal rdata_mux : std_logic_vector(7 downto 0);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
begin
my_tx: entity work.tx
generic map (divisor)
port map (
clk => clock,
reset => reset,
dotx => dotx,
txchar => txchar,
txd => txd,
done => done );
my_rx: entity work.rx
generic map (divisor)
port map (
clk => clock,
reset => reset,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
my_rxfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => rxfifo_get,
PutElement => rx_ack,
FlushFifo => '0',
DataIn => rxchar,
DataOut => rxfifo_dout,
SpaceInFifo => open,
AlmostFull => rxfifo_full,
DataInFifo => rxfifo_dav );
gentx: if tx_fifo generate
my_txfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => txfifo_get,
PutElement => txfifo_put,
FlushFifo => '0',
DataIn => bus_wdata,
DataOut => txfifo_dout,
SpaceInFifo => open,
AlmostFull => txfifo_full,
DataInFifo => txfifo_dav );
end generate;
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
bus_rack <= '0';
bus_dack <= '0';
bus_rdata <= (others => '0');
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
txfifo_put <= '0';
if tx_fifo then
dotx <= txfifo_dav and done and not dotx;
txchar <= txfifo_dout;
else
dotx <= '0';
end if;
if bus_write='1' then
bus_rack <= '1';
case bus_addr is
when "00" => -- dout
if not tx_fifo then
txchar <= bus_wdata;
dotx <= '1';
else -- there is a fifo
txfifo_put <= '1';
end if;
when "01" => -- din
rxfifo_get <= '1';
when "10" => -- clear flags
overflow <= overflow and not bus_wdata(0);
when "11" => -- interrupt control
imask <= bus_wdata(7 downto 6);
when others =>
null;
end case;
elsif bus_read='1' then
bus_rack <= '1';
bus_rdata <= rdata_mux;
bus_dack <= '1';
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= '0';
flags(3) <= '0';
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
with bus_addr select rdata_mux <=
rxfifo_dout when "00",
flags when "10",
imask & "000000" when "11",
X"00" when others;
uart_irq <= '1' when (flags(7 downto 6) and imask) /= "00" else '0';
end gideon;
| gpl-3.0 | fcf193a0a4eb81072dbabd978d255ad6 | 0.487693 | 3.41453 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op982_7.vhdl | 1 | 5,054 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 6fdba66b1ff01c1610e1c7924bc65bef | 0.579145 | 3.17263 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/Q_table.vhd | 5 | 1,580 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Q_table is
port (
Q_reg : in unsigned(3 downto 0);
filter_q : out signed(17 downto 0) );
end Q_table;
architecture Gideon of Q_table is
type t_18_bit_array is array(natural range <>) of signed(17 downto 0);
function create_factors(max_Q: real) return t_18_bit_array is
variable critical : real := 0.70710678; -- no resonance at 0.5*sqrt(2)
variable q_step : real;
variable q : real;
variable scaled : real;
variable ret : t_18_bit_array(0 to 15);
begin
q_step := (max_Q - critical) / 15.0; -- linear
for i in 0 to 15 loop
q := critical + (real(i) * q_step);
scaled := 65536.0 / q;
ret(i) := to_signed(integer(scaled), 18);
end loop;
return ret;
end function;
constant c_table : t_18_bit_array(0 to 15) := create_factors(1.8);
begin
filter_q <= c_table(to_integer(Q_reg));
end Gideon;
| gpl-3.0 | 9448d17d507fff424491fe3c0648b611 | 0.496835 | 3.834951 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/pdi_dpr_Altera_qsys.vhd | 2 | 6,132 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-06-28 V0.01 zelenkaj First version
-- 2010-08-16 V0.02 zelenkaj changed header
-- 2012-01-03 V0.03 zelenkaj added initialization file (mif)
-- 2012-02-21 V0.05 zelenkaj replaced initialization files to support ip-core repos
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
ARCHITECTURE SYN OF pdi_dpr IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byteena_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
init_file => "pdi_dpr.mif",
intended_device_family => "Cyclone IV",
lpm_type => "altsyncram",
numwords_a => NUM_WORDS,
numwords_b => NUM_WORDS,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_WITH_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_WITH_NBE_READ",
widthad_a => LOG2_NUM_WORDS,
widthad_b => LOG2_NUM_WORDS,
width_a => 32,
width_b => 32,
width_byteena_a => 4,
width_byteena_b => 4,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
byteena_a => byteena_a,
byteena_b => byteena_b,
address_a => address_a,
address_b => address_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
| gpl-2.0 | 0679f277fb838c1ff02a708cc66ba16c | 0.609589 | 3.152699 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/rom/simulation/bmg_stim_gen.vhd | 1 | 12,570 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (7 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0):= hex_to_std_logic_vector("0",8);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (8191 downto 0) of std_logic_vector(7 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
1,
"rom.mif",
DEFAULT_DATA,
8,
8192);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>8192 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(12 DOWNTO 0) <= READ_ADDR(12 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 8192 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| mit | 2f2ae630d3b3ccda753b33bd68bb3cd7 | 0.547414 | 3.685136 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_sim/tb_dac.vhd | 5 | 3,726 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_dac is
end tb_dac;
architecture tb of tb_dac is
signal clk, reset : std_logic := '0';
signal dac_in : signed(11 downto 0) := (others => '0');
signal dac_out_1 : std_logic;
signal dac_out_2 : std_logic;
signal vc_1 : real := 0.0;
signal vc_2 : real := 0.0;
signal diff : real := 0.0;
constant R : real := 2200.0;
constant C : real := 0.000000022;
begin
clk <= not clk after 10 ns; -- 50 MHz
reset <= '1', '0' after 100 ns;
dac1: entity work.sigma_delta_dac
generic map (12, 0)
port map (
clock => clk,
reset => reset,
dac_in => dac_in,
dac_out => dac_out_1 );
dac2: entity work.sigma_delta_dac
generic map (12, 1)
port map (
clock => clk,
reset => reset,
dac_in => dac_in,
dac_out => dac_out_2 );
test:process
begin
dac_in <= X"800";
wait for 1000 us;
dac_in <= X"A00";
wait for 1000 us;
dac_in <= X"C00";
wait for 1000 us;
dac_in <= X"E00";
wait for 1000 us;
dac_in <= X"000";
wait for 1000 us;
dac_in <= X"200";
wait for 1000 us;
dac_in <= X"400";
wait for 1000 us;
dac_in <= X"600";
wait for 1000 us;
dac_in <= X"7FF";
wait for 1000 us;
-- dac_in <= X"002";
-- wait for 2000 us;
-- dac_in <= X"7FF";
-- wait for 500 us;
-- dac_in <= X"800";
-- wait for 500 us;
for i in 0 to 15 loop
dac_in <= to_signed(i * 16#111#, 12);
wait for 10 us; -- 10 kHz
end loop;
for i in 0 to 15 loop
dac_in <= to_signed(i * 16#111#, 12);
wait for 20 us; -- 10 kHz
end loop;
-- now generate a 2 kHz wave (sample rate = 500 kHz, 250 clocks / sample, 100 samples per sine wave)
for i in 0 to 400 loop
dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12);
wait for 5 us;
end loop;
-- now generate a 5 kHz wave (sample rate = 500 kHz, 100 clocks / sample, 100 samples per sine wave)
for i in 0 to 1000 loop
dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12);
wait for 2 us;
end loop;
-- now generate a 10 kHz wave (sample rate = 500 kHz, 50 clocks / sample, 100 samples per sine wave)
for i in 0 to 2000 loop
dac_in <= to_signed(integer(2000.0 * sin(real(i) / 15.91549430919)), 12);
wait for 1 us;
end loop;
dac_in <= X"7FF";
wait;
end process;
filter: process(clk)
variable v_dac : real;
variable i_r : real;
variable q_c : real;
begin
if rising_edge(clk) then
if dac_out_1='0' then
v_dac := -1.2;
else
v_dac := 1.2;
end if;
i_r := (v_dac - vc_1) / R;
q_c := i_r * 20.0e-9; -- 20 ns;
vc_1 <= vc_1 + (q_c / C);
-------
if dac_out_2='0' then
v_dac := -1.0;
else
v_dac := 1.0;
end if;
i_r := (v_dac - vc_2) / R;
q_c := i_r * 20.0e-9;
vc_2 <= vc_2 + (q_c / C);
end if;
end process;
diff <= vc_2 - vc_1;
end tb;
| gpl-3.0 | e2c121153aa4138b600e4b4b2066e9b7 | 0.441492 | 3.396536 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_source/data_crc.vhd | 5 | 1,812 | -------------------------------------------------------------------------------
-- Title : data_crc.vhd
-------------------------------------------------------------------------------
-- File : data_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB data
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity data_crc is
port (
clock : in std_logic;
sync : in std_logic;
valid : in std_logic;
data_in : in std_logic_vector(7 downto 0);
crc : out std_logic_vector(15 downto 0) );
end data_crc;
architecture Gideon of data_crc is
constant polynom : std_logic_vector(15 downto 0) := X"8004";
-- CRC-5 = x5 + x2 + 1
begin
process(clock)
variable tmp : std_logic_vector(crc'range);
variable d : std_logic;
begin
if rising_edge(clock) then
if sync = '1' then
tmp := (others => '1');
end if;
if valid = '1' then
for i in data_in'reverse_range loop -- LSB first!
d := data_in(i) xor tmp(tmp'high);
tmp := tmp(tmp'high-1 downto 0) & d; --'0';
if d = '1' then
tmp := tmp xor polynom;
end if;
end loop;
end if;
for i in tmp'range loop -- reverse and invert
crc(crc'high-i) <= not(tmp(i));
end loop;
end if;
end process;
end Gideon;
| gpl-3.0 | 3f701aa194861c0d25e3c96b92e82819 | 0.390728 | 4.452088 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_source/char_generator.vhd | 5 | 3,411 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator is
generic (
g_divider : integer := 5 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
h_sync : in std_logic;
v_sync : in std_logic;
pixel_active : out std_logic;
pixel_data : out std_logic;
sync_out_n : out std_logic );
end entity;
architecture structural of char_generator is
signal clock_en : std_logic;
signal control : t_chargen_control;
signal screen_addr : unsigned(10 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
begin
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
control => control );
i_timing: entity work.char_generator_timing
generic map (
g_divider => g_divider )
port map (
clock => clock,
reset => reset,
h_sync => h_sync,
v_sync => v_sync,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_data => pixel_data,
clock_en => clock_en,
sync_n => sync_out_n );
i_rom: entity work.char_generator_rom
port map (
clock => clock,
enable => clock_en,
address => char_addr,
data => char_data );
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
screen_data <= std_logic_vector(screen_addr(7 downto 0));
end if;
end if;
end process;
-- i_ram: entity work.char_generator_rom
-- port map (
-- clock => clock,
-- enable => clock_en,
-- address => screen_addr,
-- data => screen_data );
end structural;
| gpl-3.0 | 61bf467fefeef495a8c68e2606f75520 | 0.400469 | 4.52988 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op963_5.vhdl | 1 | 4,520 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias3,
S => net3
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net4
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_3,
scope => Wprivate
)
port map(
D => out1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 6792d48c1040b5747dda9a54eed3e0c5 | 0.584071 | 3.214794 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAmaster/ipif_master_handler.vhd | 4 | 11,074 | -------------------------------------------------------------------------------
--
-- Title : plb_master_handler
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : c:\my_designs\POWERLINK\src\plb_master_handler.vhd
-- Generated : Mon Nov 7 13:17:30 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-12-01 V0.02 zelenkaj Fixed read transfer error (dst_rdy_n earlier)
-- 2011-12-05 V0.03 zelenkaj Avoid preset of FFs
-- 2012-01-16 V0.04 zelenkaj Renamed to IPIF master handler
-- Added zero-padding to address bus
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ipif_master_handler is
generic(
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
dma_highadr_g : integer := 31;
C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32;
C_MAC_DMA_IPIF_AWIDTH : integer := 32;
m_burstcount_width_g : integer := 4
);
port(
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_byteenable : in std_logic_vector(3 downto 0);
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_writedata : in std_logic_vector(31 downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_readdata : out std_logic_vector(31 downto 0);
m_waitrequest : out std_logic := '1';
m_readdatavalid : out std_logic := '0';
m_clk : out std_logic
);
end ipif_master_handler;
architecture rtl of ipif_master_handler is
signal clk, rst : std_logic;
--signals for requesting transfers
signal m_write_s, m_read_s, m_wrd_en_n : std_logic;
signal m_write_l, m_read_l : std_logic;
signal m_write_rise, m_read_rise : std_logic;
signal m_write_fall, m_read_fall : std_logic;
signal mst_write_req, mst_write_req_next : std_logic;
signal mst_read_req, mst_read_req_next : std_logic;
--what if master wants to req new transfer, but previous is not yet completed (= no Mst_Cmplt pulse!!!)
signal mst_done : std_logic;
--signals for the transfer
type tran_t is (idle, sof, tran, eof, seof, wait4cmplt); --seof = start/end of frame (single beat)
signal wr_tran, wr_tran_next : tran_t;
signal rd_tran : tran_t;
--avoid preset of FFs
signal MAC_DMA2Bus_MstRd_dst_rdy : std_logic;
begin
--some assignments..
m_clk <= MAC_DMA_CLK;
clk <= MAC_DMA_CLK;
rst <= MAC_DMA_Rst;
mst_done <= Bus2MAC_DMA_Mst_Cmplt;
m_write_s <= m_write and not m_wrd_en_n; --NOTE: write/read enable is low-active!
m_read_s <= m_read and not m_wrd_en_n; --NOTE: write/read enable is low-active!
--reserved
MAC_DMA2Bus_Mst_Lock <= '0';
MAC_DMA2Bus_Mst_Reset <= '0';
--delay some signals..
del_proc : process(clk, rst)
begin
if rst = '1' then
m_write_l <= '0'; m_read_l <= '0';
m_wrd_en_n <= '0'; --is low-active to avoid preset of FF
elsif rising_edge(clk) then
m_write_l <= m_write_s; m_read_l <= m_read_s;
if mst_done = '1' then
m_wrd_en_n <= '0';
elsif m_write_fall = '1' or m_read_fall = '1' then
m_wrd_en_n <= '1'; --write/read done, wait for Mst_Cmplt
end if;
end if;
end process;
--generate pulse if write/read is asserted
m_write_rise <= '1' when m_write_l = '0' and m_write_s = '1' else '0';
m_read_rise <= '1' when m_read_l = '0' and m_read_s = '1' else '0';
m_write_fall <= '1' when m_write_l = '1' and m_write_s = '0' else '0';
m_read_fall <= '1' when m_read_l = '1' and m_read_s = '0' else '0';
--generate req qualifiers
req_proc : process(clk, rst)
begin
if rst = '1' then
mst_write_req <= '0'; mst_read_req <= '0';
MAC_DMA2Bus_MstRd_dst_rdy <= '0';
elsif rising_edge(clk) then
mst_write_req <= mst_write_req_next; mst_read_req <= mst_read_req_next;
if m_read_s = '1' then
MAC_DMA2Bus_MstRd_dst_rdy <= '1';
elsif rd_tran = eof and Bus2MAC_DMA_MstRd_src_rdy_n = '0' then
MAC_DMA2Bus_MstRd_dst_rdy <= '0';
end if;
end if;
end process;
MAC_DMA2Bus_MstRd_dst_rdy_n <= not MAC_DMA2Bus_MstRd_dst_rdy;
mst_write_req_next <= '0' when mst_write_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else
'1' when mst_write_req = '0' and m_write_rise = '1' else
mst_write_req;
mst_read_req_next <= '0' when mst_read_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else
'1' when mst_read_req = '0' and m_read_rise = '1' else
mst_read_req;
MAC_DMA2Bus_MstRd_Req <= mst_read_req;
MAC_DMA2Bus_MstWr_Req <= mst_write_req;
MAC_DMA2Bus_Mst_Type <= '0' when m_burstcount < 2 else --single beat
mst_read_req or mst_write_req; --we are talking about bursts..
--assign address, byteenable and burst size
comb_addrZeroPad : process(m_address)
begin
for i in MAC_DMA2Bus_Mst_Addr'range loop
if i <= m_address'high then
MAC_DMA2Bus_Mst_Addr(i) <= m_address(i);
else
MAC_DMA2Bus_Mst_Addr(i) <= '0'; --zero padding
end if;
end loop;
end process;
--MAC_DMA2Bus_Mst_Addr <= m_address;
MAC_DMA2Bus_Mst_BE <= "1111";
MAC_DMA2Bus_Mst_Length <= conv_std_logic_vector(conv_integer(m_burstcount),
MAC_DMA2Bus_Mst_Length'length - 2) & "00"; -- dword x 4 = byte
--write/read link
wrd_proc : process(clk, rst)
begin
if rst = '1' then
wr_tran <= idle;
elsif rising_edge(clk) then
wr_tran <= wr_tran_next;
end if;
end process;
--generate fsm for write and read transfers
wr_tran_next <=
seof when wr_tran = idle and mst_write_req_next = '1' and (m_burstcount <= 1 or m_burstcount'length = 1) else
sof when wr_tran = idle and mst_write_req_next = '1' and m_burstcount'length > 1 else
eof when wr_tran = sof and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount = 2 and m_burstcount'length > 1 else
tran when wr_tran = sof and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount'length > 1 else
eof when wr_tran = tran and m_burstcounter <= 2 and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' and m_burstcount'length > 1 else
wait4cmplt when (wr_tran = eof or wr_tran = seof) and Bus2MAC_DMA_MstWr_dst_rdy_n = '0' else
idle when wr_tran = wait4cmplt and mst_done = '1' else
wr_tran;
rd_tran <=
seof when Bus2MAC_DMA_MstRd_sof_n = '0' and Bus2MAC_DMA_MstRd_eof_n = '0' else
sof when Bus2MAC_DMA_MstRd_sof_n = '0' else
eof when Bus2MAC_DMA_MstRd_eof_n = '0' else
tran when Bus2MAC_DMA_MstRd_src_rdy_n = '0' else
idle;
--set write qualifiers
MAC_DMA2Bus_MstWr_sof_n <= '0' when wr_tran = sof or wr_tran = seof else '1';
MAC_DMA2Bus_MstWr_eof_n <= '0' when wr_tran = eof or wr_tran = seof else '1';
MAC_DMA2Bus_MstWr_src_rdy_n <= '0' when wr_tran /= idle and wr_tran /= wait4cmplt else '1';
MAC_DMA2Bus_MstWr_src_dsc_n <= '1'; --no support
MAC_DMA2Bus_MstWr_rem <= (others => '0'); --no support
--set read qualifiers
MAC_DMA2Bus_MstRd_dst_dsc_n <= '1'; --no support
--connect ipif with avalon
m_waitrequest <= --waitrequest if not ready or no write active
not m_write when Bus2MAC_DMA_MstWr_dst_rdy_n = '0' else
not m_read when mst_read_req = '1' and Bus2MAC_DMA_Mst_CmdAck = '1' else '1';
m_readdatavalid <= not Bus2MAC_DMA_MstRd_src_rdy_n;
MAC_DMA2Bus_MstWr_d <= m_writedata;
m_readdata <= Bus2MAC_DMA_MstRd_d;
end rtl;
| gpl-2.0 | c05750a02f8dd8e3ae070d7ac81d8830 | 0.63175 | 2.865201 | false | false | false | false |
chrismasters/fpga-space-invaders | project/i8080.vhd | 1 | 34,347 |
library work;
use work.opcodes.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
entity i8080 is
Port (
clk : in STD_LOGIC;
addressBus : out STD_LOGIC_VECTOR (15 downto 0);
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0);
sync : out STD_LOGIC; -- not implemented
dataBusIn : out STD_LOGIC;
ready : in STD_LOGIC;
waitAck : out STD_LOGIC;
wr : out STD_LOGIC;
hold : in STD_LOGIC; -- not implemented
hlda : out STD_LOGIC; -- not implemented
inte : out STD_LOGIC;
int : in STD_LOGIC;
reset : in STD_LOGIC;
status : out STD_LOGIC_VECTOR(3 downto 0));
end i8080;
architecture Behavioral of i8080 is
COMPONENT RegisterArray PORT(
clk : IN std_logic;
selector : IN std_logic_vector(7 downto 0);
dataIn : IN std_logic_vector(15 downto 0);
load : IN std_logic;
dataOut : OUT std_logic_vector(15 downto 0));
END COMPONENT;
COMPONENT alu PORT(
clk : IN std_logic;
operandA : IN std_logic_vector(7 downto 0);
operandB : IN std_logic_vector(7 downto 0);
operatorSelect : IN std_logic_vector(2 downto 0);
carryIn : IN std_logic;
carryOut : OUT std_logic;
zeroOut : OUT std_logic;
signOut : OUT std_logic;
parityOut : OUT std_logic;
auxCarryOut : OUT std_logic;
result : OUT std_logic_vector(7 downto 0));
END COMPONENT;
type stateType is (
halted0, badopcode,
fetch0, fetch1,
decode,
readDirect0,readDirect1,readDirect2,readDirect3,
readImmediate0, readImmediate1,
readRegPair0, readRegPair1, readRegPair2,
dad1, dad2,
lxi0, lxi1,
mvi0, mvi1a, mvi2a, mvi3a, mvi1b,
stax0, stax1, stax2,
ldax0, ldax1, ldax2,
shld0, shld1, shld2, shld3, shld4,
lhld0, lhld1, lhld2, lhld3, lhld4,
sta0, sta1, sta2,
lda0, lda1, lda2,
inxdcx0, inxdcx1,
inrdcrmem0, inrdcrmem1, inrdcrmem2, inrdcrmem3, inrdcrmem4,
inrdcrreg0, inrdcrreg1,
aluOp0a, aluOp0b, aluOp1,
postRotate0,
daa0,
call0, call1, call2, call3, call4,
jump0,
ret0, ret1, ret2, ret3, ret4,
movmemtoreg0, movmemtoreg1, movmemtoreg2, movmemtoreg3,
movregtomem0, movregtomem1, movregtomem2, movregtomem3,
movregtoreg0, movregtoreg1, movregtoreg2,
pop0, pop1, pop2, pop3, pop4,
push0, push1, push2, push3, push4, push5,
pchl0,
sphl0, sphl1,
ani0, ani1,
ori0, ori1,
inout0,
xchg0, xchg1, xchg2, xchg3
);
signal currentState : stateType := fetch0;
signal readMemReturnState : stateType := fetch0;
signal pc : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal regSelector : STD_LOGIC_VECTOR (7 downto 0);
signal regDataIn : STD_LOGIC_VECTOR (15 downto 0);
signal regDataOut : STD_LOGIC_VECTOR (15 downto 0);
signal regLoad : STD_LOGIC := '0';
signal tempReg1 : STD_LOGIC_VECTOR (7 downto 0);
signal tempReg2 : STD_LOGIC_VECTOR (7 downto 0);
signal a : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal flagsSign : STD_LOGIC := '0';
signal flagsZero : STD_LOGIC := '0';
signal flagsAuxCarry : STD_LOGIC := '0';
signal flagsParity : STD_LOGIC := '0';
signal flagsCarry : STD_LOGIC := '0';
signal aluOperandA : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal aluOperandB : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
signal aluCarryIn : STD_LOGIC := '0';
signal aluCarryOut : STD_LOGIC := '0';
signal aluZeroOut : STD_LOGIC := '0';
signal aluSignOut : STD_LOGIC := '0';
signal aluParityOut : STD_LOGIC := '0';
signal aluAuxCarryOut : STD_LOGIC := '0';
signal aluResult : STD_LOGIC_VECTOR (7 downto 0);
signal aluOpSelect : STD_LOGIC_VECTOR (2 downto 0) := "000";
signal intEnabled : STD_LOGIC := '1';
constant regBC : std_logic_vector(1 downto 0) := "00";
constant regDE : std_logic_vector(1 downto 0) := "01";
constant regHL : std_logic_vector(1 downto 0) := "10";
constant regSP : std_logic_vector(1 downto 0) := "11";
constant regA : std_logic_vector(2 downto 0) := "111";
constant regB : std_logic_vector(2 downto 0) := "000";
constant regC : std_logic_vector(2 downto 0) := "001";
constant regD : std_logic_vector(2 downto 0) := "010";
constant regE : std_logic_vector(2 downto 0) := "011";
constant regH : std_logic_vector(2 downto 0) := "100";
constant regL : std_logic_vector(2 downto 0) := "101";
begin
registers: RegisterArray PORT MAP(
clk => clk,
selector => regSelector,
dataIn => regDataIn,
dataOut => regDataOut,
load => regLoad
);
ialu: alu PORT MAP(
clk => clk,
operandA => aluOperandA,
operandB => aluOperandB,
operatorSelect => aluOpSelect,
carryIn => aluCarryIn,
carryOut => aluCarryOut,
zeroOut => aluZeroOut,
signOut => aluSignOut,
parityOut => aluParityOut,
auxCarryOut => aluAuxCarryOut,
result => aluResult
);
procloop:
process (clk, reset)
pure function regToSelector(reg : std_logic_vector(2 downto 0)) return std_logic_vector is
variable regSelector : std_logic_vector(7 downto 0);
begin
case reg is
when regB => regSelector := "00000001";
when regC => regSelector := "00000010";
when regD => regSelector := "00000100";
when regE => regSelector := "00001000";
when regH => regSelector := "00010000";
when others => regSelector := "00100000"; -- regL
end case;
return regSelector;
end function regToSelector;
--impure function incrementByte(v : std_logic_vector) return std_logic_vector(7 downto 0) is
-- variable newValue : std_logic_vector(7 downto 0);
--begin
--flagsParity <= v(0) xor v(1) xor v(2) xor v(3) xor v(4) xor v(5) xor v(6) xor v(7);
--flagsAuxCarry <= and_reduce((v and X"F") + 1 and X"10");
--newValue := v + 1; -- todo fix
--flagsSign <= or_reduce(newValue and X"80");
--flagsZero <= not(or_reduce(v));
-- return "00000000"; --newValue;
--end function incrementByte;
--impure function decrementByte(v : std_logic_vector) return std_logic_vector(7 downto 0) is
-- variable newValue : std_logic_vector(7 downto 0);
--begin
--flagsParity <= v(0) xor v(1) xor v(2) xor v(3) xor v(4) xor v(5) xor v(6) xor v(7);
--flagsAuxCarry <= and_reduce((v and X"F") - 1 and X"10");
--newValue := v - 1; -- todo fix
--flagsSign <= or_reduce(newValue and X"80");
--flagsZero <= not(or_reduce(v));
-- return "00000000"; -- newValue;
--end function decrementByte;
function to_hstring (value : STD_LOGIC_VECTOR) return STRING is
constant ne : INTEGER := (value'length+3)/4;
variable pad : STD_LOGIC_VECTOR(0 to (ne*4 - value'length) - 1);
variable ivalue : STD_LOGIC_VECTOR(0 to ne*4 - 1);
variable result : STRING(1 to ne);
variable quad : STD_LOGIC_VECTOR(0 to 3);
begin
if value'length < 1 then
return result;
else
if value (value'left) = 'Z' then
pad := (others => 'Z');
else
pad := (others => '0');
end if;
ivalue := pad & value;
for i in 0 to ne-1 loop
quad := To_X01Z(ivalue(4*i to 4*i+3));
case quad is
when x"0" => result(i+1) := '0';
when x"1" => result(i+1) := '1';
when x"2" => result(i+1) := '2';
when x"3" => result(i+1) := '3';
when x"4" => result(i+1) := '4';
when x"5" => result(i+1) := '5';
when x"6" => result(i+1) := '6';
when x"7" => result(i+1) := '7';
when x"8" => result(i+1) := '8';
when x"9" => result(i+1) := '9';
when x"A" => result(i+1) := 'A';
when x"B" => result(i+1) := 'B';
when x"C" => result(i+1) := 'C';
when x"D" => result(i+1) := 'D';
when x"E" => result(i+1) := 'E';
when x"F" => result(i+1) := 'F';
when "ZZZZ" => result(i+1) := 'Z';
when others => result(i+1) := 'X';
end case;
end loop;
return "0x" & result;
end if;
end function to_hstring;
variable waitCycleCount : integer := 0;
variable opcode : STD_LOGIC_VECTOR (7 downto 0);
begin
if (reset = '1') then
currentState <= fetch0;
pc <= (others => '0');
regLoad <= '0';
wr <= '0';
dataOut <= (others => '0');
status <= "0001";
elsif (rising_edge(clk)) then
case (currentState) is
when fetch0 =>
report to_hstring(pc);
if (int and intEnabled) then
else
end if;
addressBus <= pc;
dataBusIn <= '1';
currentState <= fetch1;
regLoad <= '0';
regSelector <= "01000000"; -- default to selecting the SP
when fetch1 =>
-- wait
if (pc = X"0A9E") then -- DrawStatus - ix3
pc <= pc + 1;
end if;
pc <= pc + 1;
currentState <= decode;
when decode =>
if (not ready = '1') then
waitAck <= '1';
else
-- once external memory is ready, take the opcode off the data bus
opcode := dataIn;
aluOpSelect <= opcode(5 downto 3);
dataBusIn <= '0';
waitAck <= '0';
-- work out what to do with the opcode
if (opcode = opcNOP) then
-- nothing to see here...
currentState <= fetch0;
elsif (opcode(7 downto 6) = "00" and opcode(2 downto 0) = "001") then
if (opcode(3) = '0') then
-- LXI instructions - read two more bytes
addressBus <= pc;
dataBusIn <= '1';
readMemReturnState <= lxi0;
currentState <= readDirect0;
else
-- DAD instructions (double add) - 16 bit number in srcDReg is added to the 16 bit number in HL
case opcode(5 downto 4) is
when regBC => regSelector <= "00000011";
when regDE => regSelector <= "00001100";
when regHL => regSelector <= "00110000";
when others => regSelector <= "01000000"; -- regSP
end case;
currentState <= dad1;
end if;
elsif (opcode(7 downto 6) = "00" and opcode(2 downto 0) = "010") then
if (opcode(5) = '0') then
-- STAX - store accumulator - contents of accumulator are placed in the address in BC or DE
-- LDAX - load accumulator - contents of the address in BC or DE are placed in the accumulator
case opcode(4) is
when '0' => regSelector <= "00000011"; -- BC
when others => regSelector <= "00001100"; -- DE
end case;
regLoad <= '0';
case opcode(3) is
when '0' => currentState <= stax0;
when others => currentState <= ldax0;
end case;
elsif (opcode(5 downto 4) = "10") then
-- SHLD - store HL direct - contents of L are stored at the address following the instruction,
-- and the contents of H are stored at the location after that
-- LHLD - load HL direct
case opcode(3) is
when '0' => readMemReturnState <= shld0;
when others => readMemReturnState <= lhld0;
end case;
regSelector <= "00110000"; -- HL
regLoad <= '0';
addressBus <= pc;
dataBusIn <= '1';
currentState <= readDirect0;
elsif (opcode(5 downto 4) = "11") then
-- STA -- store accumulator direct - the contents of the accumulator replace the byte at the address following the instruction
-- LDA -- load accumulatro direct - the contents of the accumulator are replaced by the byte at the address following the instruction
case opcode(3) is
when '0' => readMemReturnState <= sta0;
when others => readMemReturnState <= lda0;
end case;
addressBus <= pc;
dataBusIn <= '1';
currentState <= readDirect0;
end if;
elsif (opcode(7 downto 6) = "00" and opcode(2 downto 0) = "011") then
-- INX - increment register pair
-- DCX - increment register pair
-- no flags affected
case opcode(5 downto 4) is
when regBC => regSelector <= "00000011";
when regDE => regSelector <= "00001100";
when regHL => regSelector <= "00110000";
when others => regSelector <= "01000000"; -- regSP
end case;
currentState <= inxdcx0;
elsif (opcode(7 downto 6) = "00" and opcode(2 downto 1) = "10") then
if (opcode(5 downto 3) = "110") then -- mem ref
regSelector <= "00110000"; -- load mem ref from HL
currentState <= inrdcrmem0;
elsif (opcode(5 downto 3) = "111") then -- accumulator
if (opcode(0) = '0') then -- INR
a <= (a(7 downto 0) + 1); -- incrementByte(regDataOut);
else -- DCR
a <= (a(7 downto 0) - 1); --decrementByte(regDataOut);
end if;
currentState <= fetch0; -- todo
else
regSelector <= regToSelector(opcode(5 downto 3));
currentState <= inrdcrreg0;
end if;
elsif (opcode(7 downto 6) = "00" and opcode(2 downto 0) = "110") then
-- MVI -- todo
readMemReturnState <= mvi0;
addressBus <= pc;
dataBusIn <= '1';
currentState <= readImmediate0;
elsif (opcode(7 downto 5) = "000" and opcode(2 downto 0) = "111") then
-- rotate accumulator instructions
if (opcode = opcRLC) then
tempReg1(7 downto 1) <= a(6 downto 0);
tempReg1(0) <= a(7);
flagsCarry <= a(7);
elsif (opcode = opcRRC) then
tempReg1(6 downto 0) <= a(7 downto 1);
tempReg1(7) <= a(0);
flagsCarry <= a(0);
elsif (opcode = opcRAL) then
tempReg1(7 downto 0) <= a(6 downto 0) & flagsCarry;
flagsCarry <= a(7); -- todo: verify you can do this as its used above
elsif (opcode = opcRAR) then
tempReg1(7 downto 0) <= flagsCarry & a(7 downto 1);
flagsCarry <= a(0); -- todo: verify you can do this as its used above
end if;
currentState <= postRotate0;
elsif (opcode(7 downto 5) = "001" and opcode(2 downto 0) = "111") then
if (opcode(4 downto 3) = "00") then
-- DAA -- decimal adjust accumulator 00100111
if (a(3 downto 0) > 9 or flagsAuxCarry = '1') then
a <= a + 6;
-- todo set aux carry if reqd
end if;
currentState <= daa0;
elsif (opcode(4 downto 3) = "01") then
-- CMA -- complement accumulator 00101111
a <= not a;
currentState <= fetch0;
else
if (opcode(3) = '0') then
-- STC -- set carry (carry to 1) 00110111
flagsCarry <= '1';
else
-- CMC -- complement carry 00111111
flagsCarry <= not flagsCarry;
end if;
currentState <= fetch0;
end if;
elsif (opcode(7 downto 6) = "01") then
-- this covers 0x40 to 0x7F for data transfer... also HLT is in here (76)
if (opcode = opcHLT) then
-- who goes there?
currentState <= halted0;
elsif (opcode(2 downto 0) = "110") then
-- read from memory address in HL
regSelector <= "00110000";
currentState <= movmemtoreg0;
elsif (opcode(5 downto 3) = "110") then
-- write to memory address in HL
if (opcode(2 downto 0) = "111") then -- a
dataOut <= a;
regSelector <= "00110000";
currentState <= movregtomem1;
else
regSelector <= regToSelector(opcode(2 downto 0));
currentState <= movregtomem0;
end if;
else
-- register transfer
if (opcode(2 downto 0) = "111") then -- a
tempReg1 <= a;
currentState <= movregtoreg1;
else
regSelector <= regToSelector(opcode(2 downto 0));
currentState <= movregtoreg0;
end if;
end if;
elsif (opcode(7 downto 6) = "10") then
-- arithmetic from 0x80 to 0x9F, logical from 0xA0 to 0xBF
-- operation already connected to alu
aluOperandA <= a;
aluCarryIn <= flagsCarry;
if (opcode(2 downto 0) = "110") then -- memory
regSelector <= "00110000"; -- load mem ref from HL
readMemReturnState <= aluOp0b;
currentState <= readRegPair0;
else -- register
regSelector <= regToSelector(opcode(2 downto 0));
currentState <= aluOp0a;
end if;
elsif (opcode(7 downto 6) = "11") then
-- from 0xC0 to 0xFF
if (opcode(2 downto 0) = "111") then
-- RST -- todo
-- opcode(5 downto 3) * 8
currentState <= fetch0;
elsif (opcode = opcCALL or opcode(2 downto 0) = "100") then -- conditional calls
addressBus <= pc;
dataBusIn <= '1';
readMemReturnState <= call0;
regSelector <= "01000000";
currentState <= readDirect0;
elsif (opcode = opcJMP or opcode(2 downto 0) = "010") then -- conditional jumps
addressBus <= pc;
dataBusIn <= '1';
readMemReturnState <= jump0;
regSelector <= "01000000";
currentState <= readDirect0;
elsif (opcode = opcRET or opcode(2 downto 0) = "000") then -- conditional returns
if (opcode = opcRET
or (opcode(5 downto 3) = "000" and flagsZero = '0')
or (opcode(5 downto 3) = "001" and flagsZero = '1')
or (opcode(5 downto 3) = "010" and flagsCarry = '0')
or (opcode(5 downto 3) = "011" and flagsCarry = '1')
or (opcode(5 downto 3) = "100" and flagsParity = '0')
or (opcode(5 downto 3) = "101" and flagsParity = '1')
or (opcode(5 downto 3) = "110" and flagsSign = '0')
or (opcode(5 downto 3) = "111" and flagsSign = '1')) then
regSelector <= "01000000";
currentState <= ret0;
else
currentState <= fetch0;
end if;
elsif (opcode(3 downto 0) = "0001") then
-- pop
addressBus <= regDataOut;
dataBusIn <= '1';
currentState <= pop0;
elsif (opcode(3 downto 0) = "0101") then
-- push
if (opcode(5 downto 4) = "11") then
-- push from A and flags
tempReg1 <= a;
tempReg2 <= flagsSign & flagsZero & "0" & flagsAuxCarry & "0" & flagsParity & "1" & flagsCarry;
currentState <= push1;
else
case opcode(5 downto 4) is
when regBC => regSelector <= "00000011";
when regDE => regSelector <= "00001100";
when others => regSelector <= "00110000"; -- regHL
end case;
currentState <= push0;
end if;
elsif (opcode = opcPCHL) then
-- PC <= HL
regSelector <= "00110000";
currentState <= pchl0;
elsif (opcode = opcSPHL) then
-- SP <= HL
regSelector <= "00110000";
currentState <= sphl0;
elsif (opcode = opcOUT or opcode = opcIN) then
readMemReturnState <= inout0;
addressBus <= pc;
dataBusIn <= '1';
currentState <= readImmediate0;
--elsif (opcode = opcXTHL) then
elsif (opcode = opcXCHG) then
-- register exchange DE <-> HL
regSelector <= "00001100";
currentState <= xchg0;
elsif (opcode = opcDI) then
intEnabled <= '0';
currentState <= fetch0;
elsif (opcode = opcEI) then
intEnabled <= '1';
currentState <= fetch0;
elsif (opcode(7 downto 6) = "11" and opcode(2 downto 0) = "110") then
aluOpSelect <= opcode(5 downto 3);
aluOperandA <= a;
addressBus <= pc;
dataBusIn <= '1';
readMemReturnState <= ani0;
currentState <= readImmediate0;
else
currentState <= badopcode;
end if;
else
currentState <= badopcode;
end if;
end if;
when readDirect0 =>
-- wait
pc <= pc + 1;
currentState <= readDirect1;
when readDirect1 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
tempReg1 <= dataIn;
waitAck <= '0';
addressBus <= pc;
dataBusIn <= '1';
currentState <= readDirect2;
end if;
when readDirect2 =>
-- wait
pc <= pc + 1;
currentState <= readDirect3;
when readDirect3 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
tempReg2 <= dataIn;
waitAck <= '0';
dataBusIn <= '0';
currentState <= readMemReturnState;
end if;
when readImmediate0 =>
-- wait
pc <= pc + 1;
currentState <= readImmediate1;
when readImmediate1 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
tempReg1 <= dataIn;
waitAck <= '0';
dataBusIn <= '0';
currentState <= readMemReturnState;
end if;
when readRegPair0 =>
addressBus <= regDataOut;
regLoad <= '0';
dataBusIn <= '1';
currentState <= readRegPair1;
when readRegPair1 =>
-- wait
currentState <= readRegPair2;
when readRegPair2 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
tempReg1 <= dataIn;
waitAck <= '0';
dataBusIn <= '0';
currentState <= readMemReturnState;
end if;
when dad1 =>
waitCycleCount := 0;
tempReg1 <= regDataOut(7 downto 0); -- latch register array output
tempReg2 <= regDataOut(15 downto 8);
regSelector <= "00110000"; -- read hl
currentState <= dad2;
when dad2 =>
if (waitCycleCount = 0) then
regDataIn <= regDataOut + (tempReg2 & tempReg1); -- add temp and register output and store
regLoad <= '1';
waitCycleCount := waitCycleCount + 1;
elsif (waitCycleCount = 5) then
regLoad <= '0';
currentState <= fetch0;
else
waitCycleCount := waitCycleCount + 1;
end if;
when lxi0 =>
case opcode(5 downto 4) is
when regBC => regSelector <= "00000011";
when regDE => regSelector <= "00001100";
when regHL => regSelector <= "00110000";
when others => regSelector <= "01000000"; -- SP
end case;
regDataIn <= tempReg2 & tempReg1;
regLoad <= '1';
currentState <= lxi1;
when lxi1 =>
regLoad <= '0';
currentState <= fetch0;
when stax0 =>
addressBus <= regDataOut;
dataOut <= a;
wr <= '1';
currentState <= stax1;
when stax1 =>
-- wait
currentState <= stax2;
when stax2 =>
-- stored.
wr <= '0';
currentState <= fetch0;
when ldax0 =>
addressBus <= regDataOut;
dataBusIn <= '1';
currentState <= ldax1;
when ldax1 =>
-- wait
currentState <= ldax2;
when ldax2 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
a <= dataIn;
dataBusIn <= '0';
currentState <= fetch0;
end if;
when shld0 =>
-- contents of L are stored at the address following the instruction,
-- and the contents of H are stored at the location after that
addressBus <= (tempReg2 & tempReg1);
dataOut <= regDataOut(7 downto 0);
wr <= '1';
currentState <= shld1;
when shld1 =>
-- wait
currentState <= shld2;
when shld2 =>
addressBus <= (tempReg2 & tempReg1) + 1;
dataOut <= regDataOut(15 downto 8);
wr <= '1';
currentState <= shld3;
when shld3 =>
-- wait
currentState <= shld4;
when shld4 =>
wr <= '0';
currentState <= fetch0;
when lhld0 =>
-- the byte at the address following the instruction in stored in L
-- and the contents of the address following that are stored in H
addressBus <= (tempReg2 & tempReg1);
dataBusIn <= '1';
currentState <= lhld1;
when lhld1 =>
-- wait
currentState <= lhld2;
when lhld2 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
regDataIn <= "00000000" & dataIn;
regSelector <= "00100000";
regLoad <= '1';
waitAck <= '0';
addressBus <= (tempReg2 & tempReg1) + 1;
dataBusIn <= '1';
currentState <= lhld3;
end if;
when lhld3 =>
-- wait
currentState <= lhld4;
when lhld4 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
regDataIn <= "00000000" & dataIn;
regSelector <= "00010000";
regLoad <= '1';
waitAck <= '0';
dataBusIn <= '0';
currentState <= fetch0;
end if;
when sta0 =>
addressBus <= (tempReg2 & tempReg1);
dataOut <= a;
wr <= '1';
currentState <= sta1;
when sta1 =>
-- wait
currentState <= sta2;
when sta2 =>
-- stored.
wr <= '0';
currentState <= fetch0;
when lda0 =>
-- the byte at the address following the instruction in stored in L
-- and the contents of the address following that are stored in H
addressBus <= (tempReg2 & tempReg1);
dataBusIn <= '1';
currentState <= lda1;
when lda1 =>
-- wait
currentState <= lda2;
when lda2 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
a <= dataIn;
waitAck <= '0';
dataBusIn <= '0';
currentState <= fetch0;
end if;
when inxdcx0 =>
if (opcode(3) = '0') then
regDataIn <= regDataOut + 1;
else
regDataIn <= regDataOut - 1;
end if;
regLoad <= '1';
currentState <= inxdcx1;
when inxdcx1 =>
regLoad <= '0';
currentState <= fetch0;
when inrdcrreg0 =>
if (opcode(0) = '0') then
regDataIn <= "00000000" & (regDataOut(7 downto 0) + 1); -- incrementByte(regDataOut);
else
regDataIn <= "00000000" & (regDataOut(7 downto 0) - 1); --decrementByte(regDataOut);
end if;
regLoad <= '1';
currentState <= inrdcrreg1;
when inrdcrreg1 =>
flagsZero <= not(or_reduce(regDataIn(7 downto 0)));
regLoad <= '0';
currentState <= fetch0;
when inrdcrmem0 =>
addressBus <= regDataOut;
dataBusIn <= '1';
currentState <= inrdcrmem1;
when inrdcrmem1 =>
-- wait
currentState <= inrdcrmem2;
when inrdcrmem2 =>
if (not ready = '1') then
waitAck <= '1';
else -- once external memory is ready, take the data off the data bus
if (opcode(0) = '1') then
--dataOut <= incrementByte(dataIn);
else
--dataOut <= decrementByte(dataIn);
end if;
waitAck <= '0';
wr <= '1';
--addressBus <= stays the same as we're writing back
currentState <= inrdcrmem3;
end if;
when inrdcrmem3 =>
-- wait
currentState <= inrdcrmem4;
when inrdcrmem4 =>
-- stored.
wr <= '0';
currentState <= fetch0;
when mvi0 =>
if (opcode(5 downto 3) = "110") then
dataOut <= tempReg1;
regSelector <= "00110000"; -- HL
currentState <= mvi1a;
else
regSelector <= regToSelector(opcode(5 downto 3));
regDataIn <= "00000000" & tempReg1;
regLoad <= '1';
currentState <= mvi1b;
end if;
when mvi1a =>
addressBus <= regDataOut;
wr <= '1';
currentState <= mvi2a;
when mvi2a =>
-- wait
currentState <= mvi3a;
when mvi3a =>
-- stored.
wr <= '0';
currentState <= fetch0;
when mvi1b =>
regLoad <= '0';
currentState <= fetch0;
when aluOp0a => -- from reg
aluOperandB <= regDataOut(7 downto 0);
currentState <= aluOp1;
when aluOp0b => -- from memory
aluOperandB <= tempReg1;
currentState <= aluOp1;
when aluOp1 =>
a <= aluResult;
currentState <= fetch0;
when postRotate0 =>
a <= tempReg1;
currentState <= fetch0;
when daa0 =>
if (a(7 downto 4) > 9 or flagsCarry = '1') then
a(7 downto 4) <= a(7 downto 4) + 6;
-- todo set carry if reqd
end if;
currentState <= fetch0;
when call0 =>
if (opcode = opcCALL
or (opcode(5 downto 3) = "000" and flagsZero = '0')
or (opcode(5 downto 3) = "001" and flagsZero = '1')
or (opcode(5 downto 3) = "010" and flagsCarry = '0')
or (opcode(5 downto 3) = "011" and flagsCarry = '1')
or (opcode(5 downto 3) = "100" and flagsParity = '0')
or (opcode(5 downto 3) = "101" and flagsParity = '1')
or (opcode(5 downto 3) = "110" and flagsSign = '0')
or (opcode(5 downto 3) = "111" and flagsSign = '1')) then
-- push pc to stack (high then low)
addressBus <= regDataOut - 1;
dataOut <= pc(15 downto 8);
wr <= '1';
currentState <= call1;
else
currentState <= fetch0;
end if;
when call1 =>
-- wait
currentState <= call2;
when call2 =>
-- stored
addressBus <= regDataOut - 2;
dataOut <= pc(7 downto 0);
currentState <= call3;
when call3 =>
-- wait and set pc to call site
pc <= tempReg2 & tempReg1;
regDataIn <= regDataOut - 2;
regLoad <= '1';
currentState <= call4;
when call4 =>
wr <= '0';
regLoad <= '0';
currentState <= fetch0;
when jump0 =>
if (opcode = opcJMP
or (opcode(5 downto 3) = "000" and flagsZero = '0')
or (opcode(5 downto 3) = "001" and flagsZero = '1')
or (opcode(5 downto 3) = "010" and flagsCarry = '0')
or (opcode(5 downto 3) = "011" and flagsCarry = '1')
or (opcode(5 downto 3) = "100" and flagsParity = '0')
or (opcode(5 downto 3) = "101" and flagsParity = '1')
or (opcode(5 downto 3) = "110" and flagsSign = '0')
or (opcode(5 downto 3) = "111" and flagsSign = '1')) then
pc <= tempReg2 & tempReg1;
end if;
currentState <= fetch0;
when ret0 =>
addressBus <= regDataOut;
dataBusIn <= '1';
currentState <= ret1;
when ret1 =>
-- wait
currentState <= ret2;
when ret2 =>
regLoad <= '0';
if (not ready = '1') then
waitAck <= '1';
else
tempReg1 <= dataIn;
addressBus <= regDataOut + 1;
waitAck <= '0';
currentState <= ret3;
end if;
when ret3 =>
-- wait
regDataIn <= regDataOut + 2;
regLoad <= '1';
currentState <= ret4;
when ret4 =>
regLoad <= '0';
if (not ready = '1') then
waitAck <= '1';
else
dataBusIn <= '0';
waitAck <= '0';
pc <= dataIn & tempReg1;
currentState <= fetch0;
end if;
when movmemtoreg0 =>
addressBus <= regDataOut;
dataBusIn <= '1';
currentState <= movmemtoreg1;
when movmemtoreg1 =>
-- wait
currentState <= movmemtoreg2;
when movmemtoreg2 =>
if (not ready = '1') then
waitAck <= '1';
else
dataBusIn <= '0';
waitAck <= '0';
if (opcode(5 downto 3) = "111") then
a <= dataIn;
currentState <= fetch0;
else
regSelector <= regToSelector(opcode(5 downto 3));
regDataIn(7 downto 0) <= dataIn;
regLoad <= '1';
currentState <= movmemtoreg3;
end if;
end if;
when movmemtoreg3 =>
regLoad <= '0';
currentState <= fetch0;
when movregtomem0 =>
dataOut <= regDataOut(7 downto 0);
regSelector <= "00110000";
currentState <= movregtomem1;
when movregtomem1 =>
addressBus <= regDataOut;
wr <= '1';
currentState <= movregtomem2;
when movregtomem2 =>
-- wait
currentState <= movregtomem3;
when movregtomem3 =>
wr <= '0';
currentState <= fetch0;
when movregtoreg0 =>
tempReg1 <= regDataOut(7 downto 0);
currentState <= movregtoreg1;
when movregtoreg1 =>
if (opcode(5 downto 3) = "111") then
a <= tempReg1;
currentState <= fetch0;
else
regSelector <= regToSelector(opcode(5 downto 3));
regDataIn <= "00000000" & tempReg1;
regLoad <= '1';
currentState <= movregtoreg2;
end if;
when movregtoreg2 =>
regLoad <= '0';
currentState <= fetch0;
when pop0 =>
-- wait
currentState <= pop1;
when pop1 =>
if (not ready = '1') then
waitAck <= '1';
else
waitAck <= '0';
tempReg2 <= dataIn;
addressBus <= regDataOut + 1;
dataBusIn <= '1';
currentState <= pop2;
end if;
when pop2 =>
-- wait and update SP
regDataIn <= regDataOut + 2;
regLoad <= '1';
currentState <= pop3;
when pop3 =>
if (not ready = '1') then
waitAck <= '1';
else
waitAck <= '0';
dataBusIn <= '0';
regLoad <= '0';
if (opcode(5 downto 4) = "11") then
-- pop to A and flags
a <= dataIn;
flagsSign <= tempReg2(7);
flagsZero <= tempReg2(6);
flagsAuxCarry <= tempReg2(4);
flagsParity <= tempReg2(2);
flagsCarry <= tempReg2(0);
currentState <= fetch0;
else
case opcode(5 downto 4) is
when regBC => regSelector <= "00000011";
when regDE => regSelector <= "00001100";
when others => regSelector <= "00110000"; -- regHL
end case;
regDataIn <= dataIn & tempReg2;
regLoad <= '1';
currentState <= pop4;
end if;
end if;
when pop4 =>
regLoad <= '0';
currentState <= fetch0;
when push0 =>
tempReg1 <= regDataOut(15 downto 8);
tempReg2 <= regDataOut(7 downto 0);
regSelector <= "01000000";
currentState <= push1;
when push1 =>
addressBus <= regDataOut - 1;
dataOut <= tempReg1;
wr <= '1';
currentState <= push2;
when push2 =>
-- wait
currentState <= push3;
when push3 =>
addressBus <= regDataOut - 2;
dataOut <= tempReg2;
currentState <= push4;
when push4 =>
-- wait and update SP
regDataIn <= regDataOut - 2;
regLoad <= '1';
currentState <= push5;
when push5 =>
wr <= '0';
regLoad <= '0';
currentState <= fetch0;
when pchl0 =>
pc <= regDataOut;
currentState <= fetch0;
when sphl0 =>
regDataIn <= regDataOut;
regSelector <= "01000000";
regLoad <= '1';
currentState <= sphl1;
when sphl1 =>
regLoad <= '0';
currentState <= fetch0;
when ani0 =>
aluOperandB <= tempReg1;
currentState <= ani1;
when ani1 =>
a <= aluResult;
currentState <= fetch0;
when ori0 =>
aluOperandB <= tempReg1;
when ori1 =>
a <= aluResult;
currentState <= fetch0;
when inout0 =>
-- device num in tempReg1
-- opcode(3) = 1 for in 0 for out
-- todo read/send accumulator
currentState <= fetch0;
when xchg0 =>
tempReg1 <= regDataOut(15 downto 8);
tempReg2 <= regDataOut(7 downto 0);
regSelector <= "00110000"; -- regHL
currentState <= xchg1;
when xchg1 =>
tempReg1 <= regDataOut(15 downto 8);
tempReg2 <= regDataOut(7 downto 0);
regDataIn <= tempReg1 & tempReg2;
regLoad <= '1';
currentState <= xchg2;
when xchg2 =>
regSelector <= "00001100"; -- regDE
regDataIn <= tempReg1 & tempReg2;
currentState <= xchg3;
when xchg3 =>
regLoad <= '0';
currentState <= fetch0;
when badopcode =>
status <= "1110";
when halted0 =>
status <= "1111";
end case;
end if;
end process;
end Behavioral;
| mit | 86f7aa515d927203a8e4df41ea31d2da | 0.58008 | 3.167374 | false | false | false | false |
andygill/kansas-lava | Prelude/VHDL/Lava.vhd | 2 | 13,061 | -- These are core Lava built-in functions Lava programs can rely on having
-- Todo: Consider prepending lava_ to the names.
-- These are core Lava built-in functions Lava programs can rely on having
-- Todo: Consider prepending lava_ to the names.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package lava is
function lava_to_std_logic (i0 : std_logic_vector(0 downto 0)) return std_logic;
end;
package body lava is
-- This is because we store memories of booleans as vector(0 downto 0)
function lava_to_std_logic (i0 : std_logic_vector(0 downto 0)) return std_logic is
begin
return i0(0);
end;
end lava;
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lava_register is
generic(
width : natural;
def : integer
);
port(
rst : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
i0 : in std_logic_vector(width-1 downto 0);
o0 : out std_logic_vector(width-1 downto 0)
);
end entity lava_register;
architecture Behavioral of lava_register is
signal reg : std_logic_vector(width-1 downto 0) := STD_LOGIC_VECTOR(TO_SIGNED(def,width));
begin
proc : process(rst, clk, clk_en) is
begin
if rst = '1' then
reg <= STD_LOGIC_VECTOR(TO_SIGNED(def,width));
elsif rising_edge(clk) then
if (clk_en = '1') then
reg <= i0;
end if;
end if;
end process proc;
o0 <= reg;
end Behavioral;
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lava_delay is
generic(
width : natural
);
port(
rst : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
i0 : in std_logic_vector(width-1 downto 0);
o0 : out std_logic_vector(width-1 downto 0)
);
end entity lava_delay;
architecture Behavioral of lava_delay is
begin
proc : process(rst, clk, clk_en) is
begin
if rising_edge(clk) then
if (clk_en = '1') then
o0 <= i0;
end if;
end if;
end process proc;
end Behavioral;
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lava_bram is
generic(
addr_width : natural;
data_width : natural;
element_count : natural;
sync : natural
);
port (
rst : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
wEn : in std_logic;
wAddr : in std_logic_vector(addr_width-1 downto 0);
wData : in std_logic_vector(data_width-1 downto 0);
rAddr : in std_logic_vector(addr_width-1 downto 0);
o0 : out std_logic_vector(data_width-1 downto 0)
);
end entity lava_bram;
architecture Behavioral of lava_bram is
type mem_type is array (element_count-1 downto 0) of std_logic_vector(data_width-1 downto 0);
signal mem : mem_type := (others => (others => 'X'));
begin
proc : process(rst, clk, clk_en) is
begin
if rising_edge(clk) then
if (clk_en = '1') then
if (wEn = '1') then
mem(to_integer(unsigned(wAddr))) <= wData;
end if;
end if;
end if;
if sync = 0 then
-- async; someone else adding any delays on writing.
o0 <= mem(to_integer(unsigned(rAddr)));
else
if rising_edge(clk) then
if (clk_en = '1') then
-- sync; with built in delay
o0 <= mem(to_integer(unsigned(rAddr)));
end if;
end if;
end if;
end process proc;
end Behavioral;
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lava_unsigned_mul is
generic(
width : natural
);
port (
i0 : in std_logic_vector(width-1 downto 0);
i1 : in std_logic_vector(width-1 downto 0);
o0 : out std_logic_vector(width-1 downto 0)
);
end entity lava_unsigned_mul;
architecture Behavioral of lava_unsigned_mul is
signal tmp : std_logic_vector(2*width-1 downto 0);
begin
-- a version of multiply that has the same sized output
tmp <= std_logic_vector((unsigned(i0)) * (unsigned(i1)));
o0 <= tmp(width-1 downto 0);
end Behavioral;
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lava_signed_mul is
generic(
width : natural
);
port (
i0 : in std_logic_vector(width-1 downto 0);
i1 : in std_logic_vector(width-1 downto 0);
o0 : out std_logic_vector(width-1 downto 0)
);
end entity lava_signed_mul;
architecture Behavioral of lava_signed_mul is
signal tmp : std_logic_vector(2*width-1 downto 0);
begin
-- a version of multiply that has the same sized output
tmp <= std_logic_vector((signed(i0)) * (signed(i1)));
o0 <= tmp(width-1 downto 0);
end Behavioral;
--------------------------------------------------------------------------------
-- TO fix below this
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lava_sampled_add is
generic (
width : natural := 8; -- signal width
frac_width : natural := 8); -- value for max * min
port(i0 : in std_logic_vector(width-1 downto 0);
i1 : in std_logic_vector(width-1 downto 0);
o0 : out std_logic_vector(width-1 downto 0));
end entity lava_sampled_add;
architecture Behavioral of lava_sampled_add is
signal tmp : signed(width-1 + 1 downto 0);
signal top2Bits : std_logic_vector(1 downto 0);
constant zeros : std_logic_vector(width - 2 downto 0) := (others => '0');
constant ones : std_logic_vector(width - 2 downto 0) := (others => '1');
begin
tmp <= signed (i0(width-1) & i0) + signed (i1(width-1) & i1);
top2Bits <= std_logic_vector(tmp(width downto width-1));
o0 <= '0' & ones when top2Bits = "01" else
'1' & zeros when top2Bits = "10" else
std_logic_vector(tmp(width-1 downto 0));
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lava_sampled_sub is
generic (
width : natural := 8; -- signal width
frac_width : natural := 8); -- value for max * min
port(i0 : in std_logic_vector(width-1 downto 0);
i1 : in std_logic_vector(width-1 downto 0);
o0 : out std_logic_vector(width-1 downto 0));
end entity lava_sampled_sub;
architecture Behavioral of lava_sampled_sub is
signal tmp : signed(width-1 + 1 downto 0);
constant zeros : std_logic_vector(width - 2 downto 0) := (others => '0');
constant ones : std_logic_vector(width - 2 downto 0) := (others => '1');
begin
tmp <= signed (i0(width-1) & i0) - signed (i1(width-1) & i1);
o0 <= '0' & ones when tmp(width downto width-1) = "01" else
'1' & zeros when tmp(width downto width-1) = "10" else
std_logic_vector(tmp(width-1 downto 0));
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lava_sampled_mul is
generic (
width : natural := 8; -- signal width
frac_width : natural := 4); -- value for max * min
port(i0 : in std_logic_vector(width-1 downto 0);
i1 : in std_logic_vector(width-1 downto 0);
o0 : out std_logic_vector(width-1 downto 0));
end entity lava_sampled_mul;
architecture Behavioral of lava_sampled_mul is
signal tmp : signed(2*width-1 downto 0);
signal topBits : signed(width-1 downto 0);
signal r0 : signed(2*width-1 downto frac_width);
signal r1 : signed(2*width-1 downto frac_width);
constant zeros : std_logic_vector(width - 2 downto 0) := (others => '0');
constant ones : std_logic_vector(width - 2 downto 0) := (others => '1');
begin
tmp <= signed (i0) * signed (i1);
r0 <= tmp(2*width-1 downto frac_width);
-- This is Round half to even (http://en.wikipedia.org/wiki/Rounding#Round_half_to_even)
r1 <= r0 when tmp(frac_width-1) = '0' else
r0 when tmp(frac_width) = '0' and tmp(frac_width-1) = '1' and tmp (frac_width - 2 downto 0) = 0 else
r0 + 1;
o0 <= std_logic_vector(r1(frac_width + width - 1 downto frac_width))
when r1(2*width-1 downto frac_width + width-1) = 0 else
std_logic_vector(r1(frac_width + width - 1 downto frac_width))
when r1(2*width-1 downto frac_width + width-1) = -1 else
'1' & zeros when tmp(2*width-1) = '1' else '0' & ones;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity lava_sampled_negate is
generic (
width : natural := 8; -- signal width
frac_width : natural := 8); -- value for max * min
port(i0 : in std_logic_vector(width-1 downto 0);
o0 : out std_logic_vector(width-1 downto 0));
end entity lava_sampled_negate;
architecture Behavioral of lava_sampled_negate is
signal tmp : signed(width-1 + 1 downto 0);
constant zeros : std_logic_vector(width - 2 downto 0) := (others => '0');
constant ones : std_logic_vector(width - 2 downto 0) := (others => '1');
begin
tmp <= - signed (i0(width-1) & i0);
o0 <= '0' & ones when tmp(width downto width-1) = "01" else
'1' & zeros when tmp(width downto width-1) = "10" else
std_logic_vector(tmp(width-1 downto 0));
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity sampled_fixedDivPowOfTwo is
generic (
width : natural := 8; -- signal width
frac_width : natural := 8; -- value for max * min
shift_by : natural);
port(i0 : in std_logic_vector(width-1 downto 0);
o0 : out std_logic_vector(width-1 downto 0));
end entity sampled_fixedDivPowOfTwo;
architecture Behavioral of sampled_fixedDivPowOfTwo is
signal r0 : std_logic_vector(width-1 downto 0);
begin
-- sign extend
r0 <= (width-1 downto width-(shift_by +1) => i0(width-1)) & i0(width-2 downto shift_by);
-- This is Round half to even (http://en.wikipedia.org/wiki/Rounding#Round_half_to_even)
o0 <= r0 when i0(shift_by-1) = '0' else
r0 when i0(shift_by) = '0' and i0(shift_by-1) = '1' and (shift_by = 1 or i0(shift_by - 2 downto 0) = 0) else
r0 + 1;
end Behavioral;
-------------------------------------------------------------------------------
-- Flux stuff
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity upflux is
port(i0 : in std_logic_vector;
go : in std_logic;
clk_en : in std_logic;
clk : in std_logic;
rst : in std_logic;
o_en : out std_logic;
o0 : out std_logic_vector;
o_clk_en : out std_logic);
end entity upflux;
architecture Behavioral of upflux is
signal reg : std_logic := '0';
begin
o_en <= reg;
o0 <= i0; -- Flowthrough
o_clk_en <= go and clk_en; -- go, based on your clock enable
proc : process(rst, clk, clk_en) is
begin
if rising_edge(clk) then
if (clk_en = '1') then
reg <= go;
end if;
end if;
end process proc;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity downflux is
generic(
width : natural
);
port (i0 : in std_logic_vector(width-1 downto 0);
en : in std_logic;
clk : in std_logic;
rst : in std_logic;
clk_en : in std_logic;
go : out std_logic;
o0 : out std_logic_vector(width-1 downto 0));
end entity downflux;
architecture Behavioral of downflux is
signal reg : std_logic_vector(width-1 downto 0);
begin
go <= en; -- this signal becomes the clock enable.
o0 <= reg; -- this is a lava delay
proc : process(rst, clk, clk_en) is
begin
if rising_edge(clk) then
if (clk_en = '1') then
reg <= i0;
end if;
end if;
end process proc;
end Behavioral;
| bsd-3-clause | f77bddad17920455d0ae50211ceb4978 | 0.575147 | 3.388067 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/command_interface/vhdl_source/command_if_pkg.vhd | 3 | 2,647 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package command_if_pkg is
constant c_cif_io_slot_base : unsigned(3 downto 0) := X"0";
constant c_cif_io_slot_enable : unsigned(3 downto 0) := X"1";
constant c_cif_io_handshake_out : unsigned(3 downto 0) := X"2"; -- write will also cause pointers to be reset
constant c_cif_io_handshake_in : unsigned(3 downto 0) := X"3";
constant c_cif_io_command_start : unsigned(3 downto 0) := X"4"; -- read only; tells software where the buffers are.
constant c_cif_io_command_end : unsigned(3 downto 0) := X"5";
constant c_cif_io_response_start : unsigned(3 downto 0) := X"6"; -- read only; tells software where the buffers are.
constant c_cif_io_response_end : unsigned(3 downto 0) := X"7";
constant c_cif_io_status_start : unsigned(3 downto 0) := X"8"; -- read only; tells software where the buffers are.
constant c_cif_io_status_end : unsigned(3 downto 0) := X"9";
constant c_cif_io_status_length : unsigned(3 downto 0) := X"A"; -- write will reset status readout
constant c_cif_io_response_len_l : unsigned(3 downto 0) := X"C"; -- write will reset response readout
constant c_cif_io_response_len_h : unsigned(3 downto 0) := X"D";
constant c_cif_io_command_len_l : unsigned(3 downto 0) := X"E"; -- read only
constant c_cif_io_command_len_h : unsigned(3 downto 0) := X"F";
constant c_cif_slot_control : unsigned(1 downto 0) := "00"; -- R/W
constant c_cif_slot_command : unsigned(1 downto 0) := "01"; -- WO
constant c_cif_slot_response : unsigned(1 downto 0) := "10"; -- RO
constant c_cif_slot_status : unsigned(1 downto 0) := "11"; -- RO
constant c_cmd_if_command_buffer_addr : unsigned(10 downto 0) := to_unsigned( 0, 11);
constant c_cmd_if_response_buffer_addr : unsigned(10 downto 0) := to_unsigned( 896, 11);
constant c_cmd_if_status_buffer_addr : unsigned(10 downto 0) := to_unsigned(1792, 11);
constant c_cmd_if_command_buffer_size : integer := 896;
constant c_cmd_if_response_buffer_size : integer := 896;
constant c_cmd_if_status_buffer_size : integer := 256;
constant c_cmd_if_command_buffer_end : unsigned(10 downto 0) := to_unsigned( 0 + c_cmd_if_command_buffer_size-1, 11);
constant c_cmd_if_response_buffer_end : unsigned(10 downto 0) := to_unsigned( 896 + c_cmd_if_response_buffer_size-1, 11);
constant c_cmd_if_status_buffer_end : unsigned(10 downto 0) := to_unsigned(1792 + c_cmd_if_status_buffer_size-1, 11);
end package;
| gpl-3.0 | 67917168ffe8c025f82355acd3a0afb2 | 0.63657 | 3.158711 | false | false | false | false |
KB777/1541UltimateII | fpga/cpu_unit/vhdl_source/dm_simple.vhd | 1 | 13,210 | --------------------------------------------------------------------------------
-- Entity: dm_simple
-- Date: 2014-12-08
-- Author: Gideon
--
-- Description: Simple direct mapped cache controller, compatible with the
-- I/D buses of the mblite
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.core_Pkg.all;
-- type dmem_in_type is record
-- dat_i : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- ena_i : std_logic;
-- end record;
--
-- type dmem_out_type is record
-- dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
-- sel_o : std_logic_vector(3 downto 0);
-- we_o : std_logic;
-- ena_o : std_logic;
-- end record;
-- type imem_in_type is record
-- dat_i : std_logic_vector(CFG_dmem_WIDTH - 1 downto 0);
-- ena_i : std_logic;
-- end record;
--
-- type imem_out_type is record
-- adr_o : std_logic_vector(CFG_dmem_SIZE - 1 downto 0);
-- ena_o : std_logic;
-- end record;
entity dm_simple is
generic (
g_address_swap : std_logic_vector(31 downto 0) := X"00000000";
g_registered_out: boolean := false;
g_data_register : boolean := true;
g_mem_direct : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
dmem_i : in dmem_out_type;
dmem_o : out dmem_in_type;
mem_o : out dmem_out_type;
mem_i : in dmem_in_type );
end entity;
architecture arch of dm_simple is
constant c_cachable_area_bits : natural := 25;
constant c_cache_size_bits : natural := 11; -- 2**11 bytes = 2KB
-- constant c_tag_compare_width : natural := c_cachable_area_bits - c_cache_size_bits;
constant c_tag_size_bits : natural := c_cache_size_bits - 2; -- 4 bytes per cache entry
type t_tag is record
addr_high : std_logic_vector(c_cachable_area_bits-1 downto c_cache_size_bits);
valid : std_logic;
end record;
constant c_valid_zero_tag : t_tag := ( addr_high => (others => '0'), valid => '1' );
function extend32(a : std_logic_vector) return std_logic_vector is
variable ret : std_logic_vector(31 downto 0) := (others => '0');
begin
ret(a'length-1 downto 0) := a;
return ret;
end function;
function address_to_tag (addr : std_logic_vector;
valid : std_logic) return t_tag is
variable v_addr : std_logic_vector(31 downto 0);
variable ret : t_tag;
begin
v_addr := extend32(addr);
ret.addr_high := v_addr(c_cachable_area_bits-1 downto c_cache_size_bits);
ret.valid := valid;
return ret;
end function;
constant c_tag_width : natural := c_cachable_area_bits - c_cache_size_bits + 1;
function tag_to_vector(i: t_tag) return std_logic_vector is
begin
return i.valid & i.addr_high;
end function;
constant c_valid_zero_tag_vector : std_logic_vector(c_tag_width-1 downto 0) := tag_to_vector(c_valid_zero_tag);
function vector_to_tag(i : std_logic_vector(c_tag_width-1 downto 0)) return t_tag is
variable ret : t_tag;
begin
ret.valid := i(c_tag_width-1);
ret.addr_high := i(c_tag_width-2 downto 0);
return ret;
end function;
function get_tag_index (addr : std_logic_vector) return unsigned is
begin
return unsigned(addr(c_tag_size_bits+1 downto 2));
end function;
function is_cacheable (addr : std_logic_vector) return boolean is
variable v_addr : std_logic_vector(31 downto 0);
begin
v_addr := extend32(addr);
return unsigned(v_addr(31 downto c_cachable_area_bits)) = 0;
end function;
-- type t_tag_ram is record
--
-- end record;
signal tag_ram_a_address : unsigned(c_tag_size_bits-1 downto 0);
signal tag_ram_a_rdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_ram_a_wdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_ram_a_en : std_logic;
signal tag_ram_a_we : std_logic;
signal tag_ram_b_address : unsigned(c_tag_size_bits-1 downto 0) := (others => '0');
signal tag_ram_b_rdata : std_logic_vector(c_tag_width-1 downto 0) := (others => '0');
signal tag_ram_b_wdata : std_logic_vector(c_tag_width-1 downto 0) := (others => '0');
signal tag_ram_b_en : std_logic := '0';
signal tag_ram_b_we : std_logic := '0';
signal cache_ram_a_address : unsigned(c_cache_size_bits-1 downto 2);
signal cache_ram_a_rdata : std_logic_vector(31 downto 0);
signal cache_ram_a_wdata : std_logic_vector(31 downto 0);
signal cache_ram_a_en : std_logic;
signal cache_ram_a_we : std_logic;
signal cache_ram_b_address : unsigned(c_cache_size_bits-1 downto 2) := (others => '0');
signal cache_ram_b_rdata : std_logic_vector(31 downto 0) := (others => '0');
signal cache_ram_b_wdata : std_logic_vector(31 downto 0) := (others => '0');
signal cache_ram_b_en : std_logic := '0';
signal cache_ram_b_we : std_logic := '0';
signal d_tag_ram_out : t_tag;
signal d_miss : std_logic;
signal data_reg : std_logic_vector(31 downto 0);
signal dmem_r : dmem_out_type;
signal dmem_o_comb : dmem_in_type;
signal dmem_o_reg : dmem_in_type;
type t_state is (idle, fill, reg);
signal state : t_state;
begin
i_tag_ram: entity work.dpram_sc
generic map (
g_width_bits => c_tag_width,
g_depth_bits => c_tag_size_bits,
g_global_init => c_valid_zero_tag_vector,
g_read_first_a => true,
g_read_first_b => true,
g_storage => "block" )
port map (
clock => clock,
a_address => tag_ram_a_address,
a_rdata => tag_ram_a_rdata,
a_wdata => tag_ram_a_wdata,
a_en => tag_ram_a_en,
a_we => tag_ram_a_we,
b_address => tag_ram_b_address,
b_rdata => tag_ram_b_rdata,
b_wdata => tag_ram_b_wdata,
b_en => tag_ram_b_en,
b_we => tag_ram_b_we );
i_cache_ram: entity work.dpram_sc
generic map (
g_width_bits => 32,
g_depth_bits => c_cache_size_bits-2,
g_global_init => X"FFFFFFFF",
g_read_first_a => true,
g_read_first_b => true,
g_storage => "block" )
port map (
clock => clock,
a_address => cache_ram_a_address,
a_rdata => cache_ram_a_rdata,
a_wdata => cache_ram_a_wdata,
a_en => cache_ram_a_en,
a_we => cache_ram_a_we,
b_address => cache_ram_b_address,
b_rdata => cache_ram_b_rdata,
b_wdata => cache_ram_b_wdata,
b_en => cache_ram_b_en,
b_we => cache_ram_b_we );
d_tag_ram_out <= vector_to_tag(tag_ram_a_rdata);
-- handle the dmem address request here; split it up
process(state, dmem_i, dmem_r, mem_i, d_tag_ram_out, cache_ram_a_rdata, data_reg)
begin
if g_registered_out then
dmem_o_comb.ena_i <= '0'; -- registered out, use this signal as register load enable
else
dmem_o_comb.ena_i <= '1'; -- direct out, use this signal as enable output
end if;
dmem_o_comb.dat_i <= (others => 'X');
d_miss <= '0';
tag_ram_a_address <= get_tag_index(dmem_i.adr_o);
tag_ram_a_wdata <= (others => 'X');
tag_ram_a_we <= '0';
tag_ram_a_en <= '0';
cache_ram_a_address <= unsigned(dmem_i.adr_o(c_cache_size_bits-1 downto 2));
cache_ram_a_wdata <= dmem_i.dat_o;
cache_ram_a_we <= '0';
cache_ram_a_en <= '0';
tag_ram_b_address <= get_tag_index(dmem_r.adr_o);
tag_ram_b_wdata <= tag_to_vector(address_to_tag(dmem_r.adr_o, '1'));
tag_ram_b_we <= '0';
tag_ram_b_en <= '0';
cache_ram_b_address <= unsigned(dmem_r.adr_o(c_cache_size_bits-1 downto 2));
cache_ram_b_wdata <= mem_i.dat_i;
cache_ram_b_we <= '0';
cache_ram_b_en <= '0';
if dmem_i.ena_o = '1' then -- processor address is valid, let's do our thing
if dmem_i.we_o = '0' then -- read
tag_ram_a_en <= '1';
cache_ram_a_en <= '1';
else -- write
tag_ram_a_en <= '1';
cache_ram_a_en <= '1';
tag_ram_a_we <= '1';
cache_ram_a_we <= '1';
if dmem_i.sel_o = "1111" then -- full word results in a valid cache line
tag_ram_a_wdata <= tag_to_vector(address_to_tag(dmem_i.adr_o, '1')); -- valid
else
tag_ram_a_wdata <= tag_to_vector(address_to_tag(dmem_i.adr_o, '0')); -- invalid
end if;
end if;
end if;
-- response to processor
case state is
when idle =>
if dmem_r.ena_o = '1' then -- registered (=delayed request valid)
if (address_to_tag(dmem_r.adr_o, '1') = d_tag_ram_out) and (dmem_r.we_o='0') and is_cacheable(dmem_r.adr_o) then -- read hit!
dmem_o_comb.dat_i <= cache_ram_a_rdata;
dmem_o_comb.ena_i <= '1';
else -- miss or write
dmem_o_comb.ena_i <= '0';
d_miss <= '1';
end if;
end if; -- else use default values, hence X
when fill =>
dmem_o_comb.ena_i <= '0';
if mem_i.ena_i = '1' then
if g_mem_direct then
dmem_o_comb.dat_i <= mem_i.dat_i; -- ouch, 32-bit multiplexer!
dmem_o_comb.ena_i <= '1';
end if;
if dmem_r.we_o='0' then -- was a read
tag_ram_b_en <= '1';
cache_ram_b_en <= '1';
tag_ram_b_we <= '1';
cache_ram_b_we <= '1';
end if;
end if;
when reg =>
dmem_o_comb.dat_i <= data_reg; -- ouch, 3rd input to 32-bit multiplexer!
dmem_o_comb.ena_i <= '1';
end case;
end process;
-- type dmem_out_type is record
-- dat_o : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
-- adr_o : std_logic_vector(CFG_DMEM_SIZE - 1 downto 0);
-- sel_o : std_logic_vector(3 downto 0);
-- we_o : std_logic;
-- ena_o : std_logic;
-- end record;
r_comb: if not g_registered_out generate
dmem_o <= dmem_o_comb;
end generate;
r_reg: if g_registered_out generate
dmem_o <= dmem_o_reg;
end generate;
process(state, dmem_r, d_miss)
begin
mem_o <= dmem_r;
mem_o.adr_o <= dmem_r.adr_o xor g_address_swap(dmem_r.adr_o'range);
mem_o.ena_o <= d_miss;
end process;
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
if d_miss = '1' then
state <= fill;
end if;
when fill =>
if mem_i.ena_i = '1' then
data_reg <= mem_i.dat_i; -- ouch, 32-bit register
dmem_r.ena_o <= '0';
if g_registered_out then
state <= idle;
elsif dmem_i.ena_o = '0' then
if g_data_register then
state <= reg;
else
report "No data register support, but it seems to be needed!"
severity error;
end if;
else
state <= idle;
end if;
end if;
when reg =>
if dmem_i.ena_o = '1' then
if d_miss = '1' then
state <= fill;
else
state <= idle;
end if;
end if;
end case;
if dmem_i.ena_o = '1' then
dmem_o_reg.ena_i <= '0';
elsif dmem_o_comb.ena_i = '1' then
dmem_o_reg.dat_i <= dmem_o_comb.dat_i;
dmem_o_reg.ena_i <= '1';
end if;
if dmem_i.ena_o = '1' then
dmem_r <= dmem_i;
end if;
if reset='1' then
state <= idle;
dmem_o_reg.ena_i <= '1';
end if;
end if;
end process;
end arch;
| gpl-3.0 | 214e573d0129ccc2c98647b3c7aadf01 | 0.485541 | 3.351941 | false | false | false | false |
KB777/1541UltimateII | fpga/io/itu/vhdl_source/itu_pkg.vhd | 1 | 1,529 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package itu_pkg is
constant c_itu_irq_global : unsigned(3 downto 0) := X"0";
constant c_itu_irq_enable : unsigned(3 downto 0) := X"1";
constant c_itu_irq_disable : unsigned(3 downto 0) := X"2";
constant c_itu_irq_edge : unsigned(3 downto 0) := X"3";
constant c_itu_irq_clear : unsigned(3 downto 0) := X"4";
constant c_itu_irq_active : unsigned(3 downto 0) := X"5";
constant c_itu_timer : unsigned(3 downto 0) := X"6";
constant c_itu_irq_timer_en : unsigned(3 downto 0) := X"7";
constant c_itu_irq_timer_hi : unsigned(3 downto 0) := X"8"; -- big endian word
constant c_itu_irq_timer_lo : unsigned(3 downto 0) := X"9";
constant c_itu_hw_flags : unsigned(3 downto 0) := X"A";
constant c_itu_fpga_version : unsigned(3 downto 0) := X"B";
constant c_itu_capabilities0 : unsigned(3 downto 0) := X"C";
constant c_itu_capabilities1 : unsigned(3 downto 0) := X"D";
constant c_itu_capabilities2 : unsigned(3 downto 0) := X"E";
constant c_itu_capabilities3 : unsigned(3 downto 0) := X"F";
-- second block
constant c_itu_ms_timer_hi : unsigned(3 downto 0) := X"2";
constant c_itu_ms_timer_lo : unsigned(3 downto 0) := X"3";
constant c_itu_usb_busy : unsigned(3 downto 0) := X"4";
constant c_itu_sd_busy : unsigned(3 downto 0) := X"5";
constant c_itu_misc_io : unsigned(3 downto 0) := X"6";
end package;
| gpl-3.0 | 5ee6aa5f8be2f425eb125848613eb848 | 0.605625 | 2.974708 | false | false | false | false |
ferdoctor/I2S_RX | i2s_fifo.vhd | 1 | 5,687 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2006 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file i2s_fifo.vhd when simulating
-- the core, i2s_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY i2s_fifo IS
port (
din: IN std_logic_VECTOR(27 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(27 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
overflow: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(9 downto 0));
END i2s_fifo;
ARCHITECTURE i2s_fifo_a OF i2s_fifo IS
-- synthesis translate_off
component wrapped_i2s_fifo
port (
din: IN std_logic_VECTOR(27 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(27 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
overflow: OUT std_logic;
wr_data_count: OUT std_logic_VECTOR(9 downto 0));
end component;
-- Configuration specification
for all : wrapped_i2s_fifo use entity XilinxCoreLib.fifo_generator_v3_2(behavioral)
generic map(
c_rd_freq => 100,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 0,
c_din_width => 28,
c_has_wr_data_count => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_has_wr_rst => 0,
c_wr_freq => 100,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 1,
c_preload_latency => 1,
c_dout_width => 28,
c_rd_depth => 1024,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 10,
c_has_wr_ack => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 10,
c_has_almost_empty => 0,
c_rd_data_count_width => 10,
c_enable_rlocs => 0,
c_wr_pntr_width => 10,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 10,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 1021,
c_wr_depth => 1024,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 1022,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "1kx36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_i2s_fifo
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
overflow => overflow,
wr_data_count => wr_data_count);
-- synthesis translate_on
END i2s_fifo_a;
| lgpl-3.0 | 0470ed2e637b9124fb72179c3f46e1bf | 0.550554 | 3.493243 | false | false | false | false |
KB777/1541UltimateII | fpga/ip/nano_cpu/vhdl_source/nano_cpu_pkg.vhd | 1 | 2,908 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package nano_cpu_pkg is
-- Instruction bit 14..12: alu operation
-- Instruction bit 11: when 1, accu is updated
-- Instruction bit 15: when 0, flags are updated
-- Instruction Set (bit 10...0) are address when needed
-- ALU
constant c_load : std_logic_vector(15 downto 11) := X"0" & '1'; -- load
constant c_or : std_logic_vector(15 downto 11) := X"1" & '1'; -- or
constant c_and : std_logic_vector(15 downto 11) := X"2" & '1'; -- and
constant c_xor : std_logic_vector(15 downto 11) := X"3" & '1'; -- xor
constant c_add : std_logic_vector(15 downto 11) := X"4" & '1'; -- add
constant c_sub : std_logic_vector(15 downto 11) := X"5" & '1'; -- sub
constant c_compare : std_logic_vector(15 downto 11) := X"5" & '0'; -- sub
constant c_addc : std_logic_vector(15 downto 11) := X"6" & '1'; -- addc
constant c_in : std_logic_vector(15 downto 11) := X"7" & '1'; -- ext
-- constant c_shr : std_logic_vector(15 downto 11) := X"7" & '1'; -- shr
-- no update flags
constant c_store : std_logic_vector(15 downto 11) := X"8" & '0'; -- xxx
constant c_load_ind : std_logic_vector(15 downto 11) := X"8" & '1'; -- load
constant c_store_ind: std_logic_vector(15 downto 11) := X"9" & '0'; -- xxx
constant c_out : std_logic_vector(15 downto 11) := X"A" & '0'; -- xxx
-- Specials
constant c_return : std_logic_vector(15 downto 11) := X"B" & '1'; -- xxx
constant c_branch : std_logic_vector(15 downto 14) := "11";
-- Branches (bit 10..0) are address
constant c_br_eq : std_logic_vector(13 downto 11) := "000"; -- zero
constant c_br_neq : std_logic_vector(13 downto 11) := "001"; -- not zero
constant c_br_mi : std_logic_vector(13 downto 11) := "010"; -- negative
constant c_br_pl : std_logic_vector(13 downto 11) := "011"; -- not negative
constant c_br_always: std_logic_vector(13 downto 11) := "100"; -- always (jump)
constant c_br_call : std_logic_vector(13 downto 11) := "101"; -- always (call)
constant c_br_c : std_logic_vector(13 downto 11) := "110"; -- carry
constant c_br_nc : std_logic_vector(13 downto 11) := "111"; -- not carry
-- ALU operations
constant c_alu_load : std_logic_vector(2 downto 0) := "000";
constant c_alu_or : std_logic_vector(2 downto 0) := "001";
constant c_alu_and : std_logic_vector(2 downto 0) := "010";
constant c_alu_xor : std_logic_vector(2 downto 0) := "011";
constant c_alu_add : std_logic_vector(2 downto 0) := "100";
constant c_alu_sub : std_logic_vector(2 downto 0) := "101";
constant c_alu_addc : std_logic_vector(2 downto 0) := "110";
end;
| gpl-3.0 | f1fd2a809b77eed28c1a5f07f57ed447 | 0.56293 | 3.116827 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/nano_cpu/vhdl_sim/nano_cpu_tb.vhd | 5 | 5,023 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_cpu_tb is
end entity;
architecture tb of nano_cpu_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_en : std_logic;
signal ram_we : std_logic;
signal ram_wdata : std_logic_vector(15 downto 0);
signal ram_rdata : std_logic_vector(15 downto 0);
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
type t_instructions is array(natural range <>) of std_logic_vector(15 downto 0);
-- constant c_load : std_logic_vector(15 downto 11) := X"0" & '1'; -- load
-- constant c_or : std_logic_vector(15 downto 11) := X"1" & '1'; -- or
-- constant c_and : std_logic_vector(15 downto 11) := X"2" & '1'; -- and
-- constant c_xor : std_logic_vector(15 downto 11) := X"3" & '1'; -- xor
-- constant c_add : std_logic_vector(15 downto 11) := X"4" & '1'; -- add
-- constant c_sub : std_logic_vector(15 downto 11) := X"5" & '1'; -- sub
-- constant c_compare : std_logic_vector(15 downto 11) := X"5" & '0'; -- sub
-- constant c_store : std_logic_vector(15 downto 11) := X"8" & '0'; -- xxx
-- constant c_load_ind : std_logic_vector(15 downto 11) := X"8" & '1'; -- load
-- constant c_store_ind: std_logic_vector(15 downto 11) := X"9" & '0'; -- xxx
-- constant c_out : std_logic_vector(15 downto 11) := X"A" & '0'; -- xxx
-- constant c_in : std_logic_vector(15 downto 11) := X"A" & '1'; -- load
--
-- -- Specials
-- constant c_return : std_logic_vector(15 downto 11) := X"B" & '1'; -- xxx
-- constant c_branch : std_logic_vector(15 downto 14) := "11";
--
-- -- Branches (bit 10..0) are address
-- constant c_br_eq : std_logic_vector(13 downto 11) := "000"; -- zero
-- constant c_br_neq : std_logic_vector(13 downto 11) := "001"; -- not zero
-- constant c_br_mi : std_logic_vector(13 downto 11) := "010"; -- negative
-- constant c_br_pl : std_logic_vector(13 downto 11) := "011"; -- not negative
-- constant c_br_always: std_logic_vector(13 downto 11) := "100"; -- always (jump)
-- constant c_br_call : std_logic_vector(13 downto 11) := "101"; -- always (call)
--
constant c_program : t_instructions := (
X"0840", -- 00 -- load $40
X"804E", -- 01 -- store $44
X"4841", -- 02 -- add $41
X"8045", -- 03 -- store $45
X"0840", -- 04 -- load $40
X"1841", -- 05 -- or $41
X"8046", -- 06 -- store $46
X"0840", -- 07 -- load $40
X"2841", -- 08 -- and $41
X"8047", -- 09 -- store $47
X"8842", -- 0a -- load ($42)
X"9043", -- 0b -- store ($43)
X"0840", -- 0c -- load $40
X"5041", -- 0d -- comp $41
X"C000", -- 0e -- equal? => 0
X"D800", -- 0f -- not negative? => 0
X"A055", -- 10 -- out to $55
X"6857", -- 11 -- in from $57
X"E818", -- 12 -- call $18
X"8048", -- 13 -- store $48
X"E01A", -- 14 -- jump $1a
X"0000", -- 15
X"0000", -- 16
X"0000", -- 17
X"0844", -- 18 -- load $44
X"B800", -- 19 -- return
X"6801", -- 1A -- in 1
X"804F", -- 1B -- store in $4f
X"A002", -- 1C -- out to $2
X"5842", -- 1D -- sub 1
X"C81C", -- 1E -- bne $1d
X"E01F" -- 1F -- jump self
);
constant c_data : t_instructions(64 to 68) := (
X"237A",
X"59B2",
X"0001",
X"0049",
X"FFFF" );
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano_cpu
port map (
clock => clock,
reset => reset,
-- instruction/data ram
ram_addr => ram_addr,
ram_en => ram_en,
ram_we => ram_we,
ram_wdata => ram_wdata,
ram_rdata => ram_rdata,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
p_ram: process
variable ram : t_instructions(0 to 1023) := (others => (others => '1'));
begin
ram(c_program'range) := c_program;
ram(c_data'range) := c_data;
while true loop
wait until clock='1';
if ram_en='1' then
ram_rdata <= ram(to_integer(unsigned(ram_addr)));
if ram_we='1' then
ram(to_integer(unsigned(ram_addr))) := ram_wdata;
end if;
end if;
end loop;
end process;
io_rdata <= X"0006";
end tb;
| gpl-3.0 | 2cf1d5ace3e4f164f82d91153d0f176e | 0.484173 | 3.10637 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/floppy_stream.vhd | 4 | 8,542 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : floppy_stream.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_arith.all;
--use ieee.std_logic_unsigned.all;
--library work;
--use work.floppy_emu_pkg.all;
entity floppy_stream is
port (
clock : in std_logic;
clock_en : in std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
reset : in std_logic;
-- data from memory
drv_rdata : in std_logic_vector(7 downto 0);
do_read : out std_logic;
do_write : out std_logic;
do_advance : out std_logic;
-- info about the head
track : out std_logic_vector(6 downto 0);
track_is_0 : out std_logic;
do_head_bang : out std_logic;
do_track_out : out std_logic;
do_track_in : out std_logic;
-- control i/o
floppy_inserted : in std_logic;
motor_on : in std_logic;
sync : out std_logic;
mode : in std_logic;
write_prot_n : in std_logic;
step : in std_logic_vector(1 downto 0);
byte_ready : out std_logic;
soe : in std_logic;
rate_ctrl : in std_logic_vector(1 downto 0); -- dont have any effect anymore
bit_time : in unsigned(8 downto 0); -- in steps of 10 ns
-- data to drive CPU
read_data : out std_logic_vector(7 downto 0) );
end floppy_stream;
architecture gideon of floppy_stream is
signal bit_square : std_logic;
signal bit_tick : std_logic;
signal bit_timer : unsigned(7 downto 0);
signal bit_carry : std_logic;
signal mem_bit_cnt : unsigned(2 downto 0);
signal rd_bit_cnt : unsigned(2 downto 0) := "000";
signal mem_shift : std_logic_vector(7 downto 0);
signal rd_shift : std_logic_vector(9 downto 0) := (others => '0');
signal sync_i : std_logic;
signal byte_rdy_i : std_logic;
alias mem_rd_bit : std_logic is mem_shift(7);
--signal track_c : unsigned(6 downto 2);
signal track_i : unsigned(6 downto 0);
signal up, down : std_logic;
signal step_d : std_logic_vector(1 downto 0);
signal step_dd0 : std_logic;
signal mode_d : std_logic;
signal write_delay : integer range 0 to 3;
signal random_data : std_logic_vector(15 downto 0);
begin
p_clock_div: process(clock)
begin
if rising_edge(clock) then
bit_tick <= '0';
if bit_timer = 0 then
bit_tick <= motor_on;
bit_carry <= not bit_carry and bit_time(0); -- toggle if bit 0 is set
if bit_carry='1' then
bit_timer <= bit_time(8 downto 1);
else
bit_timer <= bit_time(8 downto 1) - 1;
end if;
else
bit_timer <= bit_timer - 1;
end if;
bit_square <= '0';
if bit_timer < ('0' & bit_time(8 downto 2)) then
bit_square <= '1';
end if;
if reset='1' then
bit_timer <= to_unsigned(10, bit_timer'length);
bit_carry <= '0';
end if;
-- if clock_en='1' then
-- if bit_div="1111" then
-- bit_div <= "00" & unsigned(rate_ctrl);
-- bit_tick <= motor_on;
-- else
-- bit_div <= bit_div + 1;
-- end if;
-- end if;
-- if reset='1' then
-- bit_div <= "0000";
-- end if;
end if;
end process;
-- stream from memory
p_stream: process(clock)
variable new_bit : std_logic;
begin
if rising_edge(clock) then
do_read <= '0';
if bit_tick='1' then
new_bit := random_data(15) xor random_data(13) xor random_data(12) xor random_data(10);
mem_bit_cnt <= mem_bit_cnt + 1;
if mem_bit_cnt="000" then
random_data <= random_data(14 downto 0) & new_bit;
if drv_rdata = X"00" then
mem_shift <= random_data(15 downto 8) and random_data(7 downto 0);
else
mem_shift <= drv_rdata;
end if;
-- issue command to fifo
do_read <= mode; --'1'; does not pulse when in write mode
else
mem_shift <= mem_shift(6 downto 0) & '1';
end if;
end if;
if reset='1' then
mem_shift <= (others => '1');
mem_bit_cnt <= "000";
random_data <= X"ABCD";
end if;
end if;
end process;
-- parallelize stream and generate sync
-- and handle writes
p_reading: process(clock)
variable s : std_logic;
begin
if rising_edge(clock) then
if rd_shift = "1111111111" and mode='1' then
s := '0';
else
s := '1';
end if;
sync_i <= s;
do_advance <= '0';
mode_d <= mode;
if mode_d='1' and mode='0' then -- going to write
write_delay <= 2;
do_advance <= '0';
end if;
do_write <= '0';
if rd_bit_cnt = "111" and mode='0' and bit_tick='1' then
if write_delay = 0 then
do_write <= floppy_inserted; --'1';
else
do_advance <= '1';
write_delay <= write_delay - 1;
end if;
end if;
if bit_tick='1' then
rd_shift <= rd_shift(8 downto 0) & mem_rd_bit;
rd_bit_cnt <= rd_bit_cnt + 1;
end if;
if s = '0' then
rd_bit_cnt <= "000";
end if;
if (rd_bit_cnt="111") and (soe = '1') and (bit_square='1') then
byte_rdy_i <= '0';
else
byte_rdy_i <= '1';
end if;
end if;
end process;
p_move: process(clock)
variable st : std_logic_vector(3 downto 0);
begin
if rising_edge(clock) then
do_track_in <= '0';
do_track_out <= '0';
do_head_bang <= '0';
if motor_on='1' then
st := std_logic_vector(track_i(1 downto 0)) & step;
down <= '0';
up <= '0';
case st is
when "0001" | "0110" | "1011" | "1100" => -- up
do_track_in <= '1';
if track_i /= 83 then
track_i <= track_i + 1;
end if;
when "0011" | "0100" | "1001" | "1110" => -- down
do_track_out <= '1';
if track_i /= 0 then
track_i <= track_i - 1;
end if;
when others =>
null;
end case;
end if;
if reset='1' then
track_i <= "0100000";
end if;
end if;
end process;
-- track_i <= track_c & unsigned(step_d);
-- outputs
sync <= sync_i;
read_data <= rd_shift(7 downto 0);
byte_ready <= byte_rdy_i;
track <= std_logic_vector(track_i);
track_is_0 <= '1' when track_i = "0000000" else '0';
end gideon;
| gpl-3.0 | 2e22ce36cdec26eb69cc99a23245bff7 | 0.416647 | 4.021657 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op990_5.vhdl | 1 | 6,130 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 869d5faae83bb14259a75affd157cd16 | 0.570636 | 3.077309 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op336_6.vhdl | 1 | 5,610 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
W => Wsrc_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
W => Wsrc_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => out1,
N => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 7fe96b4cecc251ac1d696f7c9064ab12 | 0.574688 | 3.102876 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/plb_powerlink.vhd | 1 | 97,172 | -------------------------------------------------------------------------------
-- Entity : plb_powerlink
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the toplevel file for using the POWERLINK IP-Core
-- with Xilinx PLB V4.6.
--
-------------------------------------------------------------------------------
--
-- 2011-09-13 V0.01 zelenkaj First version
-- 2011-11-24 V0.02 mairt added slave interface for pdi pcp and pdi ap
-- 2011-11-26 V0.03 mairt added slave interface for simpleIO
-- 2011-12-02 V0.04 zelenkaj Exchanged IOs with _I, _O and _T
-- 2011-12-06 V0.05 zelenkaj Changed instance names
-- 2011-12-07 V0.06 zelenkaj Fixed address assignments for PDI PCP/AP
-- 2011-12-16 V0.07 mairt added TX/RX burst size feature
-- 2012-01-19 V0.08 zelenkaj Added bus to core clock ration feature
-- 2012-01-26 V0.09 zelenkaj Added number of SMI generic feature
-- 2012-01-16 V0.10 zelenkaj Replace plb_* with ipif_master_handler
-- 2012-01-27 V0.20 zelenkaj Incremented PdiRev
-- 2012-02-01 V0.21 zelenkaj Added attributes and RMII clk out
-- 2012-03-23 V0.22 zelenkaj fixed to/downto issue
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library plbv46_slave_single_v1_01_a;
use plbv46_slave_single_v1_01_a.plbv46_slave_single;
-- standard libraries declarations
library UNISIM;
use UNISIM.vcomponents.all;
-- pragma synthesis_off
library IEEE;
use IEEE.vital_timing.all;
-- pragma synthesis_on
-- other libraries declarations
library PLBV46_MASTER_BURST_V1_01_A;
library PLBV46_SLAVE_SINGLE_V1_01_A;
entity plb_powerlink is
generic(
-- general
C_GEN_PDI : boolean := false;
C_GEN_PAR_IF : boolean := false;
C_GEN_SPI_IF : boolean := false;
C_GEN_PLB_BUS_IF : boolean := false;
C_GEN_SIMPLE_IO : boolean := false;
-- openMAC
C_MAC_PKT_SIZE : integer := 1024;
C_MAC_PKT_SIZE_LOG2 : integer := 10;
C_MAC_RX_BUFFERS : integer := 16;
C_USE_RMII : boolean := false;
C_TX_INT_PKT : boolean := false;
C_RX_INT_PKT : boolean := false;
C_USE_2ND_PHY : boolean := true;
C_NUM_SMI : integer range 1 to 2 := 2;
--pdi
C_PDI_GEN_ASYNC_BUF_0 : boolean := true;
C_PDI_ASYNC_BUF_0 : integer := 50;
C_PDI_GEN_ASYNC_BUF_1 : boolean := true;
C_PDI_ASYNC_BUF_1 : integer := 50;
C_PDI_GEN_LED : boolean := false;
C_PDI_GEN_TIME_SYNC : boolean := true;
C_PDI_GEN_SECOND_TIMER : boolean := false;
C_PDI_GEN_EVENT : boolean := true;
--global pdi and mac
C_NUM_RPDO : integer := 3;
C_RPDO_0_BUF_SIZE : integer := 100;
C_RPDO_1_BUF_SIZE : integer := 100;
C_RPDO_2_BUF_SIZE : integer := 100;
C_NUM_TPDO : integer := 1;
C_TPDO_BUF_SIZE : integer := 100;
-- pap
C_PAP_DATA_WIDTH : integer := 16;
--C_PAP_BIG_END : boolean := false;
C_PAP_LOW_ACT : boolean := false;
-- spi
C_SPI_CPOL : boolean := false;
C_SPI_CPHA : boolean := false;
--C_SPI_BIG_END : boolean := false;
-- simpleIO
C_PIO_VAL_LENGTH : integer := 50;
-- debug
C_OBSERVER_ENABLE : boolean := false;
-- clock stabiliser
C_INSTANCE_ODDR2 : boolean := false;
-- PDI AP PLB Slave
C_PDI_AP_BASEADDR : std_logic_vector := X"00000000";
C_PDI_AP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_PDI_AP_NUM_MASTERS : INTEGER := 1;
C_PDI_AP_PLB_AWIDTH : INTEGER := 32;
C_PDI_AP_PLB_DWIDTH : INTEGER := 32;
C_PDI_AP_PLB_MID_WIDTH : INTEGER := 1;
C_PDI_AP_PLB_P2P : INTEGER := 0;
C_PDI_AP_PLB_NUM_MASTERS : INTEGER := 1;
C_PDI_AP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_PDI_AP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- PDI AP PLB Slave
C_SMP_PCP_BASEADDR : std_logic_vector := X"00000000";
C_SMP_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_SMP_PCP_NUM_MASTERS : INTEGER := 1;
C_SMP_PCP_PLB_AWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_DWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_MID_WIDTH : INTEGER := 1;
C_SMP_PCP_PLB_P2P : INTEGER := 0;
C_SMP_PCP_PLB_NUM_MASTERS : INTEGER := 1;
C_SMP_PCP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_SMP_PCP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- PDI PCP PLB Slave
C_PDI_PCP_BASEADDR : std_logic_vector := X"00000000";
C_PDI_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_PDI_PCP_NUM_MASTERS : INTEGER := 1;
C_PDI_PCP_PLB_AWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_DWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_MID_WIDTH : INTEGER := 1;
C_PDI_PCP_PLB_P2P : INTEGER := 0;
C_PDI_PCP_PLB_NUM_MASTERS : INTEGER := 1;
C_PDI_PCP_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_PDI_PCP_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- openMAC CMP PLB Slave
C_MAC_PKT_BASEADDR : std_logic_vector := X"00000000";
C_MAC_PKT_HIGHADDR : std_logic_vector := X"000FFFFF";
C_MAC_PKT_NUM_MASTERS : INTEGER := 1;
C_MAC_PKT_PLB_AWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_DWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_MID_WIDTH : INTEGER := 1;
C_MAC_PKT_PLB_P2P : INTEGER := 0;
C_MAC_PKT_PLB_NUM_MASTERS : INTEGER := 1;
C_MAC_PKT_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_PKT_PLB_SUPPORT_BURSTS : INTEGER := 0;
-- openMAC DMA PLB Master
C_MAC_DMA_PLB_AWIDTH : INTEGER := 32;
C_MAC_DMA_PLB_DWIDTH : INTEGER := 32;
C_MAC_DMA_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_DMA_BURST_SIZE_RX : INTEGER := 8; --in bytes
C_MAC_DMA_BURST_SIZE_TX : INTEGER := 8; --in bytes
C_MAC_DMA_FIFO_SIZE_RX : INTEGER := 32; --in bytes
C_MAC_DMA_FIFO_SIZE_TX : INTEGER := 32; --in bytes
-- openMAC REG PLB Slave
C_MAC_REG_BASEADDR : std_logic_vector := X"00000000";
C_MAC_REG_HIGHADDR : std_logic_vector := X"0000FFFF";
C_MAC_CMP_BASEADDR : std_logic_vector := X"00000000";
C_MAC_CMP_HIGHADDR : std_logic_vector := X"0000FFFF";
C_MAC_REG_BUS2CORE_CLK_RATIO : integer := 2;
C_MAC_REG_NUM_MASTERS : INTEGER := 1;
C_MAC_REG_PLB_AWIDTH : INTEGER := 32;
C_MAC_REG_PLB_DWIDTH : INTEGER := 32;
C_MAC_REG_PLB_MID_WIDTH : INTEGER := 1;
C_MAC_REG_PLB_P2P : INTEGER := 0;
C_MAC_REG_PLB_NUM_MASTERS : INTEGER := 1;
C_MAC_REG_PLB_NATIVE_DWIDTH : INTEGER := 32;
C_MAC_REG_PLB_SUPPORT_BURSTS : INTEGER := 0
);
port(
MAC_DMA_Clk : in std_logic;
MAC_DMA_MAddrAck : in std_logic;
MAC_DMA_MBusy : in std_logic;
MAC_DMA_MIRQ : in std_logic;
MAC_DMA_MRdBTerm : in std_logic;
MAC_DMA_MRdDAck : in std_logic;
MAC_DMA_MRdErr : in std_logic;
MAC_DMA_MRearbitrate : in std_logic;
MAC_DMA_MTimeout : in std_logic;
MAC_DMA_MWrBTerm : in std_logic;
MAC_DMA_MWrDAck : in std_logic;
MAC_DMA_MWrErr : in std_logic;
MAC_DMA_Rst : in std_logic;
MAC_PKT_Clk : in std_logic;
MAC_PKT_PAValid : in std_logic;
MAC_PKT_RNW : in std_logic;
MAC_PKT_Rst : in std_logic;
MAC_PKT_SAValid : in std_logic;
MAC_PKT_abort : in std_logic;
MAC_PKT_busLock : in std_logic;
MAC_PKT_lockErr : in std_logic;
MAC_PKT_rdBurst : in std_logic;
MAC_PKT_rdPendReq : in std_logic;
MAC_PKT_rdPrim : in std_logic;
MAC_PKT_wrBurst : in std_logic;
MAC_PKT_wrPendReq : in std_logic;
MAC_PKT_wrPrim : in std_logic;
MAC_REG_Clk : in std_logic;
MAC_REG_PAValid : in std_logic;
MAC_REG_RNW : in std_logic;
MAC_REG_Rst : in std_logic;
MAC_REG_SAValid : in std_logic;
MAC_REG_abort : in std_logic;
MAC_REG_busLock : in std_logic;
MAC_REG_lockErr : in std_logic;
MAC_REG_rdBurst : in std_logic;
MAC_REG_rdPendReq : in std_logic;
MAC_REG_rdPrim : in std_logic;
MAC_REG_wrBurst : in std_logic;
MAC_REG_wrPendReq : in std_logic;
MAC_REG_wrPrim : in std_logic;
PDI_AP_Clk : in std_logic;
PDI_AP_PAValid : in std_logic;
PDI_AP_RNW : in std_logic;
PDI_AP_Rst : in std_logic;
PDI_AP_SAValid : in std_logic;
PDI_AP_abort : in std_logic;
PDI_AP_busLock : in std_logic;
PDI_AP_lockErr : in std_logic;
PDI_AP_rdBurst : in std_logic;
PDI_AP_rdPendReq : in std_logic;
PDI_AP_rdPrim : in std_logic;
PDI_AP_wrBurst : in std_logic;
PDI_AP_wrPendReq : in std_logic;
PDI_AP_wrPrim : in std_logic;
PDI_PCP_Clk : in std_logic;
PDI_PCP_PAValid : in std_logic;
PDI_PCP_RNW : in std_logic;
PDI_PCP_Rst : in std_logic;
PDI_PCP_SAValid : in std_logic;
PDI_PCP_abort : in std_logic;
PDI_PCP_busLock : in std_logic;
PDI_PCP_lockErr : in std_logic;
PDI_PCP_rdBurst : in std_logic;
PDI_PCP_rdPendReq : in std_logic;
PDI_PCP_rdPrim : in std_logic;
PDI_PCP_wrBurst : in std_logic;
PDI_PCP_wrPendReq : in std_logic;
PDI_PCP_wrPrim : in std_logic;
SMP_PCP_Clk : in std_logic;
SMP_PCP_PAValid : in std_logic;
SMP_PCP_RNW : in std_logic;
SMP_PCP_Rst : in std_logic;
SMP_PCP_SAValid : in std_logic;
SMP_PCP_abort : in std_logic;
SMP_PCP_busLock : in std_logic;
SMP_PCP_lockErr : in std_logic;
SMP_PCP_rdBurst : in std_logic;
SMP_PCP_rdPendReq : in std_logic;
SMP_PCP_rdPrim : in std_logic;
SMP_PCP_wrBurst : in std_logic;
SMP_PCP_wrPendReq : in std_logic;
SMP_PCP_wrPrim : in std_logic;
clk100 : in std_logic;
clk50 : in std_logic;
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic;
phy0_link : in std_logic;
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic;
phy1_link : in std_logic;
phyMii0_RxClk : in std_logic;
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic;
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
MAC_DMA_MRdDBus : in std_logic_vector(0 to C_MAC_DMA_PLB_DWIDTH-1);
MAC_DMA_MRdWdAddr : in std_logic_vector(0 to 3);
MAC_DMA_MSSize : in std_logic_vector(0 to 1);
MAC_PKT_ABus : in std_logic_vector(0 to 31);
MAC_PKT_BE : in std_logic_vector(0 to (C_MAC_PKT_PLB_DWIDTH/8)-1);
MAC_PKT_MSize : in std_logic_vector(0 to 1);
MAC_PKT_TAttribute : in std_logic_vector(0 to 15);
MAC_PKT_UABus : in std_logic_vector(0 to 31);
MAC_PKT_masterID : in std_logic_vector(0 to C_MAC_PKT_PLB_MID_WIDTH-1);
MAC_PKT_rdPendPri : in std_logic_vector(0 to 1);
MAC_PKT_reqPri : in std_logic_vector(0 to 1);
MAC_PKT_size : in std_logic_vector(0 to 3);
MAC_PKT_type : in std_logic_vector(0 to 2);
MAC_PKT_wrDBus : in std_logic_vector(0 to C_MAC_PKT_PLB_DWIDTH-1);
MAC_PKT_wrPendPri : in std_logic_vector(0 to 1);
MAC_REG_ABus : in std_logic_vector(0 to 31);
MAC_REG_BE : in std_logic_vector(0 to (C_MAC_REG_PLB_DWIDTH / 8) - 1);
MAC_REG_MSize : in std_logic_vector(0 to 1);
MAC_REG_TAttribute : in std_logic_vector(0 to 15);
MAC_REG_UABus : in std_logic_vector(0 to 31);
MAC_REG_masterID : in std_logic_vector(0 to C_MAC_REG_PLB_MID_WIDTH - 1);
MAC_REG_rdPendPri : in std_logic_vector(0 to 1);
MAC_REG_reqPri : in std_logic_vector(0 to 1);
MAC_REG_size : in std_logic_vector(0 to 3);
MAC_REG_type : in std_logic_vector(0 to 2);
MAC_REG_wrDBus : in std_logic_vector(0 to C_MAC_REG_PLB_DWIDTH - 1);
MAC_REG_wrPendPri : in std_logic_vector(0 to 1);
PDI_AP_ABus : in std_logic_vector(0 to 31);
PDI_AP_BE : in std_logic_vector(0 to (C_PDI_AP_PLB_DWIDTH/8)-1);
PDI_AP_MSize : in std_logic_vector(0 to 1);
PDI_AP_TAttribute : in std_logic_vector(0 to 15);
PDI_AP_UABus : in std_logic_vector(0 to 31);
PDI_AP_masterID : in std_logic_vector(0 to C_PDI_AP_PLB_MID_WIDTH-1);
PDI_AP_rdPendPri : in std_logic_vector(0 to 1);
PDI_AP_reqPri : in std_logic_vector(0 to 1);
PDI_AP_size : in std_logic_vector(0 to 3);
PDI_AP_type : in std_logic_vector(0 to 2);
PDI_AP_wrDBus : in std_logic_vector(0 to C_PDI_AP_PLB_DWIDTH-1);
PDI_AP_wrPendPri : in std_logic_vector(0 to 1);
PDI_PCP_ABus : in std_logic_vector(0 to 31);
PDI_PCP_BE : in std_logic_vector(0 to (C_PDI_PCP_PLB_DWIDTH/8)-1);
PDI_PCP_MSize : in std_logic_vector(0 to 1);
PDI_PCP_TAttribute : in std_logic_vector(0 to 15);
PDI_PCP_UABus : in std_logic_vector(0 to 31);
PDI_PCP_masterID : in std_logic_vector(0 to C_PDI_PCP_PLB_MID_WIDTH-1);
PDI_PCP_rdPendPri : in std_logic_vector(0 to 1);
PDI_PCP_reqPri : in std_logic_vector(0 to 1);
PDI_PCP_size : in std_logic_vector(0 to 3);
PDI_PCP_type : in std_logic_vector(0 to 2);
PDI_PCP_wrDBus : in std_logic_vector(0 to C_PDI_PCP_PLB_DWIDTH-1);
PDI_PCP_wrPendPri : in std_logic_vector(0 to 1);
SMP_PCP_ABus : in std_logic_vector(0 to 31);
SMP_PCP_BE : in std_logic_vector(0 to (C_SMP_PCP_PLB_DWIDTH/8)-1);
SMP_PCP_MSize : in std_logic_vector(0 to 1);
SMP_PCP_TAttribute : in std_logic_vector(0 to 15);
SMP_PCP_UABus : in std_logic_vector(0 to 31);
SMP_PCP_masterID : in std_logic_vector(0 to C_SMP_PCP_PLB_MID_WIDTH-1);
SMP_PCP_rdPendPri : in std_logic_vector(0 to 1);
SMP_PCP_reqPri : in std_logic_vector(0 to 1);
SMP_PCP_size : in std_logic_vector(0 to 3);
SMP_PCP_type : in std_logic_vector(0 to 2);
SMP_PCP_wrDBus : in std_logic_vector(0 to C_SMP_PCP_PLB_DWIDTH-1);
SMP_PCP_wrPendPri : in std_logic_vector(0 to 1);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_be_n : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_data_I : in std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy1_RxDat : in std_logic_vector(1 downto 0);
phyMii0_RxDat : in std_logic_vector(3 downto 0);
phyMii1_RxDat : in std_logic_vector(3 downto 0);
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0);
MAC_DMA_RNW : out std_logic;
MAC_DMA_abort : out std_logic;
MAC_DMA_busLock : out std_logic;
MAC_DMA_error : out std_logic;
MAC_DMA_lockErr : out std_logic;
MAC_DMA_rdBurst : out std_logic;
MAC_DMA_request : out std_logic;
MAC_DMA_wrBurst : out std_logic;
MAC_PKT_addrAck : out std_logic;
MAC_PKT_rdBTerm : out std_logic;
MAC_PKT_rdComp : out std_logic;
MAC_PKT_rdDAck : out std_logic;
MAC_PKT_rearbitrate : out std_logic;
MAC_PKT_wait : out std_logic;
MAC_PKT_wrBTerm : out std_logic;
MAC_PKT_wrComp : out std_logic;
MAC_PKT_wrDAck : out std_logic;
MAC_REG_addrAck : out std_logic;
MAC_REG_rdBTerm : out std_logic;
MAC_REG_rdComp : out std_logic;
MAC_REG_rdDAck : out std_logic;
MAC_REG_rearbitrate : out std_logic;
MAC_REG_wait : out std_logic;
MAC_REG_wrBTerm : out std_logic;
MAC_REG_wrComp : out std_logic;
MAC_REG_wrDAck : out std_logic;
PDI_AP_addrAck : out std_logic;
PDI_AP_rdBTerm : out std_logic;
PDI_AP_rdComp : out std_logic;
PDI_AP_rdDAck : out std_logic;
PDI_AP_rearbitrate : out std_logic;
PDI_AP_wait : out std_logic;
PDI_AP_wrBTerm : out std_logic;
PDI_AP_wrComp : out std_logic;
PDI_AP_wrDAck : out std_logic;
PDI_PCP_addrAck : out std_logic;
PDI_PCP_rdBTerm : out std_logic;
PDI_PCP_rdComp : out std_logic;
PDI_PCP_rdDAck : out std_logic;
PDI_PCP_rearbitrate : out std_logic;
PDI_PCP_wait : out std_logic;
PDI_PCP_wrBTerm : out std_logic;
PDI_PCP_wrComp : out std_logic;
PDI_PCP_wrDAck : out std_logic;
SMP_PCP_addrAck : out std_logic;
SMP_PCP_rdBTerm : out std_logic;
SMP_PCP_rdComp : out std_logic;
SMP_PCP_rdDAck : out std_logic;
SMP_PCP_rearbitrate : out std_logic;
SMP_PCP_wait : out std_logic;
SMP_PCP_wrBTerm : out std_logic;
SMP_PCP_wrComp : out std_logic;
SMP_PCP_wrDAck : out std_logic;
ap_asyncIrq : out std_logic;
ap_asyncIrq_n : out std_logic;
ap_syncIrq : out std_logic;
ap_syncIrq_n : out std_logic;
led_error : out std_logic;
led_status : out std_logic;
mac_irq : out std_logic;
pap_ack : out std_logic;
pap_ack_n : out std_logic;
pap_data_T : out std_logic;
phy0_Rst_n : out std_logic;
phy0_SMIClk : out std_logic;
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxEn : out std_logic;
phy0_clk : out std_logic;
phy1_Rst_n : out std_logic;
phy1_SMIClk : out std_logic;
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxEn : out std_logic;
phy1_clk : out std_logic;
phyMii0_TxEn : out std_logic;
phyMii0_TxEr : out std_logic;
phyMii1_TxEn : out std_logic;
phyMii1_TxEr : out std_logic;
phy_Rst_n : out std_logic;
phy_SMIClk : out std_logic;
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic;
spi_miso : out std_logic;
tcp_irq : out std_logic;
MAC_DMA_ABus : out std_logic_vector(0 to 31);
MAC_DMA_BE : out std_logic_vector(0 to (C_MAC_DMA_PLB_DWIDTH/8)-1);
MAC_DMA_MSize : out std_logic_vector(0 to 1);
MAC_DMA_TAttribute : out std_logic_vector(0 to 15);
MAC_DMA_UABus : out std_logic_vector(0 to 31);
MAC_DMA_priority : out std_logic_vector(0 to 1);
MAC_DMA_size : out std_logic_vector(0 to 3);
MAC_DMA_type : out std_logic_vector(0 to 2);
MAC_DMA_wrDBus : out std_logic_vector(0 to C_MAC_DMA_PLB_DWIDTH-1);
MAC_PKT_MBusy : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MIRQ : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MRdErr : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_MWrErr : out std_logic_vector(0 to C_MAC_PKT_NUM_MASTERS-1);
MAC_PKT_SSize : out std_logic_vector(0 to 1);
MAC_PKT_rdDBus : out std_logic_vector(0 to C_MAC_PKT_PLB_DWIDTH-1);
MAC_PKT_rdWdAddr : out std_logic_vector(0 to 3);
MAC_REG_MBusy : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MIRQ : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MRdErr : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_MWrErr : out std_logic_vector(0 to C_MAC_REG_NUM_MASTERS-1);
MAC_REG_SSize : out std_logic_vector(0 to 1);
MAC_REG_rdDBus : out std_logic_vector(0 to C_MAC_REG_PLB_DWIDTH-1);
MAC_REG_rdWdAddr : out std_logic_vector(0 to 3);
PDI_AP_MBusy : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MIRQ : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MRdErr : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_MWrErr : out std_logic_vector(0 to C_PDI_AP_PLB_NUM_MASTERS-1);
PDI_AP_SSize : out std_logic_vector(0 to 1);
PDI_AP_rdDBus : out std_logic_vector(0 to C_PDI_AP_PLB_DWIDTH-1);
PDI_AP_rdWdAddr : out std_logic_vector(0 to 3);
PDI_PCP_MBusy : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MIRQ : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MRdErr : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_MWrErr : out std_logic_vector(0 to C_PDI_PCP_NUM_MASTERS-1);
PDI_PCP_SSize : out std_logic_vector(0 to 1);
PDI_PCP_rdDBus : out std_logic_vector(0 to C_PDI_PCP_PLB_DWIDTH-1);
PDI_PCP_rdWdAddr : out std_logic_vector(0 to 3);
SMP_PCP_MBusy : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MIRQ : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MRdErr : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_MWrErr : out std_logic_vector(0 to C_SMP_PCP_PLB_NUM_MASTERS-1);
SMP_PCP_SSize : out std_logic_vector(0 to 1);
SMP_PCP_rdDBus : out std_logic_vector(0 to C_SMP_PCP_PLB_DWIDTH-1);
SMP_PCP_rdWdAddr : out std_logic_vector(0 to 3);
led_gpo : out std_logic_vector(7 downto 0);
led_opt : out std_logic_vector(1 downto 0);
led_phyAct : out std_logic_vector(1 downto 0);
led_phyLink : out std_logic_vector(1 downto 0);
pap_data_O : out std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
phy0_TxDat : out std_logic_vector(1 downto 0);
phy1_TxDat : out std_logic_vector(1 downto 0);
phyMii0_TxDat : out std_logic_vector(3 downto 0);
phyMii1_TxDat : out std_logic_vector(3 downto 0);
pio_portOutValid : out std_logic_vector(3 downto 0);
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
test_port : out std_logic_vector(255 downto 0) := (others => '0')
);
-- Entity declarations --
-- Click here to add additional declarations --
attribute SIGIS : string;
-- Entity attributes --
attribute SIGIS of MAC_DMA_Clk : signal is "Clk";
attribute SIGIS of MAC_DMA_Rst : signal is "Rst";
attribute SIGIS of MAC_PKT_Clk : signal is "Clk";
attribute SIGIS of MAC_PKT_Rst : signal is "Rst";
attribute SIGIS of MAC_REG_Clk : signal is "Clk";
attribute SIGIS of MAC_REG_Rst : signal is "Rst";
attribute SIGIS of PDI_AP_Clk : signal is "Clk";
attribute SIGIS of PDI_AP_Rst : signal is "Rst";
attribute SIGIS of PDI_PCP_Clk : signal is "Clk";
attribute SIGIS of PDI_PCP_Rst : signal is "Rst";
attribute SIGIS of SMP_PCP_Clk : signal is "Clk";
attribute SIGIS of SMP_PCP_Rst : signal is "Rst";
attribute SIGIS of clk100 : signal is "Clk";
attribute SIGIS of clk50 : signal is "Clk";
attribute SIGIS of phy0_clk : signal is "Clk";
attribute SIGIS of phy1_clk : signal is "Clk";
end plb_powerlink;
architecture struct of plb_powerlink is
---- Architecture declarations -----
function get_max( a, b : integer) return integer is
begin
if a < b then
return b;
else
return a;
end if;
end get_max;
---- Component declarations -----
component ipif_master_handler
generic(
C_MAC_DMA_IPIF_AWIDTH : integer := 32;
C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32;
dma_highadr_g : integer := 31;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4
);
port (
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : in std_logic_vector(3 downto 0);
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_writedata : in std_logic_vector(31 downto 0);
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
m_clk : out std_logic;
m_readdata : out std_logic_vector(31 downto 0);
m_readdatavalid : out std_logic := '0';
m_waitrequest : out std_logic := '1'
);
end component;
component openMAC_16to32conv
generic(
bus_address_width : integer := 10;
gEndian : string := "little"
);
port (
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_byteenable : in std_logic_vector(3 downto 0);
bus_read : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_writedata : in std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_waitrequest : in std_logic;
bus_ack_rd : out std_logic;
bus_ack_wr : out std_logic;
bus_readdata : out std_logic_vector(31 downto 0);
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_chipselect : out std_logic;
s_read : out std_logic;
s_write : out std_logic;
s_writedata : out std_logic_vector(15 downto 0)
);
end component;
component powerlink
generic(
Simulate : boolean := false;
endian_g : string := "little";
gNumSmi : integer range 1 to 2 := 2;
genABuf1_g : boolean := true;
genABuf2_g : boolean := true;
genEvent_g : boolean := false;
genInternalAp_g : boolean := true;
genIoBuf_g : boolean := true;
genLedGadget_g : boolean := false;
genOnePdiClkDomain_g : boolean := false;
genPdi_g : boolean := true;
genSimpleIO_g : boolean := false;
genSmiIO : boolean := true;
genSpiAp_g : boolean := false;
genTimeSync_g : boolean := false;
gen_dma_observer_g : boolean := true;
iAsyBuf1Size_g : integer := 100;
iAsyBuf2Size_g : integer := 100;
iBufSizeLOG2_g : integer := 10;
iBufSize_g : integer := 1024;
iPdiRev_g : integer := 21930;
iRpdo0BufSize_g : integer := 100;
iRpdo1BufSize_g : integer := 100;
iRpdo2BufSize_g : integer := 100;
iRpdos_g : integer := 3;
iTpdoBufSize_g : integer := 100;
iTpdos_g : integer := 1;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_data_width_g : integer := 16;
m_rx_burst_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_tx_fifo_size_g : integer := 16;
papBigEnd_g : boolean := false;
papDataWidth_g : integer := 8;
papLowAct_g : boolean := false;
pioValLen_g : integer := 50;
spiBigEnd_g : boolean := false;
spiCPHA_g : boolean := false;
spiCPOL_g : boolean := false;
use2ndCmpTimer_g : boolean := true;
use2ndPhy_g : boolean := true;
useIntPacketBuf_g : boolean := true;
useRmii_g : boolean := true;
useRxIntPacketBuf_g : boolean := true
);
port (
ap_address : in std_logic_vector(12 downto 0);
ap_byteenable : in std_logic_vector(3 downto 0);
ap_chipselect : in std_logic;
ap_read : in std_logic;
ap_write : in std_logic;
ap_writedata : in std_logic_vector(31 downto 0);
clk50 : in std_logic;
clkAp : in std_logic;
clkEth : in std_logic;
clkPcp : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
m_readdatavalid : in std_logic := '0';
m_waitrequest : in std_logic;
mac_address : in std_logic_vector(11 downto 0);
mac_byteenable : in std_logic_vector(1 downto 0);
mac_chipselect : in std_logic;
mac_read : in std_logic;
mac_write : in std_logic;
mac_writedata : in std_logic_vector(15 downto 0);
mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0);
mbf_byteenable : in std_logic_vector(3 downto 0);
mbf_chipselect : in std_logic;
mbf_read : in std_logic;
mbf_write : in std_logic;
mbf_writedata : in std_logic_vector(31 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
pcp_address : in std_logic_vector(12 downto 0);
pcp_byteenable : in std_logic_vector(3 downto 0);
pcp_chipselect : in std_logic;
pcp_read : in std_logic;
pcp_write : in std_logic;
pcp_writedata : in std_logic_vector(31 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic := '1';
phy0_link : in std_logic := '0';
phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0');
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic := '1';
phy1_link : in std_logic := '0';
phyMii0_RxClk : in std_logic;
phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic := '1';
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
pkt_clk : in std_logic;
rst : in std_logic;
rstAp : in std_logic;
rstPcp : in std_logic;
smp_address : in std_logic;
smp_byteenable : in std_logic_vector(3 downto 0);
smp_read : in std_logic;
smp_write : in std_logic;
smp_writedata : in std_logic_vector(31 downto 0);
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
tcp_address : in std_logic_vector(1 downto 0);
tcp_byteenable : in std_logic_vector(3 downto 0);
tcp_chipselect : in std_logic;
tcp_read : in std_logic;
tcp_write : in std_logic;
tcp_writedata : in std_logic_vector(31 downto 0);
ap_asyncIrq : out std_logic := '0';
ap_asyncIrq_n : out std_logic := '1';
ap_irq : out std_logic := '0';
ap_irq_n : out std_logic := '1';
ap_readdata : out std_logic_vector(31 downto 0) := (others => '0');
ap_syncIrq : out std_logic := '0';
ap_syncIrq_n : out std_logic := '1';
ap_waitrequest : out std_logic;
led_error : out std_logic := '0';
led_gpo : out std_logic_vector(7 downto 0) := (others => '0');
led_opt : out std_logic_vector(1 downto 0) := (others => '0');
led_phyAct : out std_logic_vector(1 downto 0) := (others => '0');
led_phyLink : out std_logic_vector(1 downto 0) := (others => '0');
led_status : out std_logic := '0';
m_address : out std_logic_vector(29 downto 0) := (others => '0');
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0) := (others => '0');
m_read : out std_logic := '0';
m_write : out std_logic := '0';
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
mac_irq : out std_logic := '0';
mac_readdata : out std_logic_vector(15 downto 0) := (others => '0');
mac_waitrequest : out std_logic;
mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0');
mbf_waitrequest : out std_logic;
pap_ack : out std_logic := '0';
pap_ack_n : out std_logic := '1';
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
pcp_waitrequest : out std_logic;
phy0_Rst_n : out std_logic := '1';
phy0_SMIClk : out std_logic := '0';
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy0_TxEn : out std_logic := '0';
phy1_Rst_n : out std_logic := '1';
phy1_SMIClk : out std_logic := '0';
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy1_TxEn : out std_logic := '0';
phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii0_TxEn : out std_logic := '0';
phyMii0_TxEr : out std_logic := '0';
phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii1_TxEn : out std_logic := '0';
phyMii1_TxEr : out std_logic := '0';
phy_Rst_n : out std_logic := '1';
phy_SMIClk : out std_logic := '0';
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic := '0';
pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0');
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
smp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
smp_waitrequest : out std_logic;
spi_miso : out std_logic := '0';
tcp_irq : out std_logic := '0';
tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
tcp_waitrequest : out std_logic;
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0');
phy0_SMIDat : inout std_logic := '1';
phy1_SMIDat : inout std_logic := '1';
phy_SMIDat : inout std_logic := '1';
pio_portio : inout std_logic_vector(31 downto 0) := (others => '0')
);
end component;
component plbv46_master_burst
generic(
C_FAMILY : string := "virtex5";
C_INHIBIT_CC_BLE_INCLUSION : integer range 0 to 1 := 0;
C_MPLB_AWIDTH : integer range 32 to 36 := 32;
C_MPLB_DWIDTH : integer range 32 to 128 := 32;
C_MPLB_NATIVE_DWIDTH : integer range 32 to 128 := 32;
C_MPLB_SMALLEST_SLAVE : integer range 32 to 128 := 32
);
port (
IP2Bus_MstRd_Req : in std_logic;
IP2Bus_MstRd_dst_dsc_n : in std_logic;
IP2Bus_MstRd_dst_rdy_n : in std_logic;
IP2Bus_MstWr_Req : in std_logic;
IP2Bus_MstWr_d : in std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
IP2Bus_MstWr_eof_n : in std_logic;
IP2Bus_MstWr_rem : in std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
IP2Bus_MstWr_sof_n : in std_logic;
IP2Bus_MstWr_src_dsc_n : in std_logic;
IP2Bus_MstWr_src_rdy_n : in std_logic;
IP2Bus_Mst_Addr : in std_logic_vector(0 to C_MPLB_AWIDTH-1);
IP2Bus_Mst_BE : in std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
IP2Bus_Mst_Length : in std_logic_vector(0 to 11);
IP2Bus_Mst_Lock : in std_logic;
IP2Bus_Mst_Reset : in std_logic;
IP2Bus_Mst_Type : in std_logic;
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MBusy : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to C_MPLB_DWIDTH-1);
PLB_MRdErr : in std_logic;
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MTimeout : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrErr : in std_logic;
Bus2IP_MstRd_d : out std_logic_vector(0 to C_MPLB_NATIVE_DWIDTH-1);
Bus2IP_MstRd_eof_n : out std_logic;
Bus2IP_MstRd_rem : out std_logic_vector(0 to (C_MPLB_NATIVE_DWIDTH/8)-1);
Bus2IP_MstRd_sof_n : out std_logic;
Bus2IP_MstRd_src_dsc_n : out std_logic;
Bus2IP_MstRd_src_rdy_n : out std_logic;
Bus2IP_MstWr_dst_dsc_n : out std_logic;
Bus2IP_MstWr_dst_rdy_n : out std_logic;
Bus2IP_Mst_CmdAck : out std_logic;
Bus2IP_Mst_Cmd_Timeout : out std_logic;
Bus2IP_Mst_Cmplt : out std_logic;
Bus2IP_Mst_Error : out std_logic;
Bus2IP_Mst_Rearbitrate : out std_logic;
MD_Error : out std_logic;
M_ABus : out std_logic_vector(0 to 31);
M_BE : out std_logic_vector(0 to (C_MPLB_DWIDTH/8)-1);
M_MSize : out std_logic_vector(0 to 1);
M_RNW : out std_logic;
M_TAttribute : out std_logic_vector(0 to 15);
M_UABus : out std_logic_vector(0 to 31);
M_abort : out std_logic;
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_MPLB_DWIDTH-1)
);
end component;
component plbv46_slave_single
generic(
C_ARD_ADDR_RANGE_ARRAY : slv64_array_type := (X"0000_0000_7000_0000",X"0000_0000_7000_00FF",X"0000_0000_7000_0100",X"0000_0000_7000_01FF");
C_ARD_NUM_CE_ARRAY : integer_array_type := (1,8);
C_BUS2CORE_CLK_RATIO : integer range 1 to 2 := 1;
C_FAMILY : string := "virtex4";
C_INCLUDE_DPHASE_TIMER : integer range 0 to 1 := 1;
C_SIPIF_DWIDTH : integer range 32 to 32 := 32;
C_SPLB_AWIDTH : integer range 32 to 32 := 32;
C_SPLB_DWIDTH : integer range 32 to 128 := 32;
C_SPLB_MID_WIDTH : integer range 1 to 4 := 2;
C_SPLB_NUM_MASTERS : integer range 1 to 16 := 8;
C_SPLB_P2P : integer range 0 to 1 := 0
);
port (
IP2Bus_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
IP2Bus_Error : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_WrAck : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_BE : in std_logic_vector(0 to (C_SPLB_DWIDTH/8)-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_PAValid : in std_logic;
PLB_RNW : in std_logic;
PLB_SAValid : in std_logic;
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_lockErr : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_rdBurst : in std_logic;
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_rdPendReq : in std_logic;
PLB_rdPrim : in std_logic;
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrBurst : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_wrPendReq : in std_logic;
PLB_wrPrim : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
Bus2IP_Addr : out std_logic_vector(0 to C_SPLB_AWIDTH-1);
Bus2IP_BE : out std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
Bus2IP_CS : out std_logic_vector(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
Bus2IP_Clk : out std_logic;
Bus2IP_Data : out std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_RNW : out std_logic;
Bus2IP_RdCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Bus2IP_Reset : out std_logic;
Bus2IP_WrCE : out std_logic_vector(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_SSize : out std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdDAck : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rearbitrate : out std_logic;
Sl_wait : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrDAck : out std_logic
);
end component;
---- Architecture declarations -----
constant C_FAMILY : string := "spartan6";
constant C_ADDR_PAD_ZERO : std_logic_vector(31 downto 0) := (others => '0');
-- openMAC REG PLB Slave
constant C_MAC_REG_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_REG_BASEADDR;
constant C_MAC_REG_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_REG_HIGHADDR;
-- openMAC CMP PLB Slave
constant C_MAC_CMP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_CMP_BASEADDR;
constant C_MAC_CMP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_CMP_HIGHADDR;
-- openMAC PKT PLB Slave
constant C_MAC_PKT_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_PKT_BASEADDR;
constant C_MAC_PKT_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_MAC_PKT_HIGHADDR;
-- SimpleIO Slave
constant C_SMP_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_SMP_PCP_BASEADDR;
constant C_SMP_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_SMP_PCP_HIGHADDR;
-- PDI PCP Slave
constant C_PDI_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_PCP_BASEADDR;
constant C_PDI_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_PCP_HIGHADDR;
-- AP PCP Slave
constant C_PDI_AP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_AP_BASEADDR;
constant C_PDI_AP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_PDI_AP_HIGHADDR;
-- POWERLINK IP-core
constant C_MAC_PKT_EN : boolean := C_TX_INT_PKT or C_RX_INT_PKT;
constant C_MAC_PKT_RX_EN : boolean := C_RX_INT_PKT;
constant C_DMA_EN : boolean := not C_TX_INT_PKT or not C_RX_INT_PKT;
constant C_PKT_BUF_EN : boolean := C_MAC_PKT_EN;
constant C_M_BURSTCOUNT_WIDTH : integer := integer(ceil(log2(real(get_max(C_MAC_DMA_BURST_SIZE_RX,C_MAC_DMA_BURST_SIZE_TX)/4)))) + 1; --in dwords
constant C_M_FIFO_SIZE_RX : integer := C_MAC_DMA_FIFO_SIZE_RX/4; --in dwords
constant C_M_FIFO_SIZE_TX : integer := C_MAC_DMA_FIFO_SIZE_TX/4; --in dwords
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
constant GND_CONSTANT : std_logic := '0';
---- Signal declarations used on the diagram ----
signal ap_chipselect : std_logic;
signal ap_read : std_logic;
signal ap_waitrequest : std_logic;
signal ap_write : std_logic;
signal Bus2MAC_CMP_Reset : std_logic;
signal Bus2MAC_DMA_MstRd_eof_n : std_logic;
signal Bus2MAC_DMA_MstRd_sof_n : std_logic;
signal Bus2MAC_DMA_MstRd_src_dsc_n : std_logic;
signal Bus2MAC_DMA_MstRd_src_rdy_n : std_logic;
signal Bus2MAC_DMA_MstWr_dst_dsc_n : std_logic;
signal Bus2MAC_DMA_MstWr_dst_rdy_n : std_logic;
signal Bus2MAC_DMA_Mst_CmdAck : std_logic;
signal Bus2MAC_DMA_Mst_Cmd_Timeout : std_logic;
signal Bus2MAC_DMA_Mst_Cmplt : std_logic;
signal Bus2MAC_DMA_Mst_Error : std_logic;
signal Bus2MAC_DMA_Mst_Rearbitrate : std_logic;
signal Bus2MAC_PKT_Clk : std_logic;
signal Bus2MAC_PKT_Reset : std_logic;
signal Bus2MAC_PKT_RNW : std_logic;
signal Bus2MAC_REG_Clk : std_logic;
signal Bus2MAC_REG_Reset : std_logic;
signal Bus2MAC_REG_RNW : std_logic;
signal Bus2MAC_REG_RNW_n : std_logic;
signal Bus2PDI_AP_Clk : std_logic;
signal Bus2PDI_AP_Reset : std_logic;
signal Bus2PDI_AP_RNW : std_logic;
signal Bus2PDI_PCP_Clk : std_logic;
signal Bus2PDI_PCP_Reset : std_logic;
signal Bus2PDI_PCP_RNW : std_logic;
signal Bus2SMP_PCP_Clk : std_logic;
signal Bus2SMP_PCP_Reset : std_logic;
signal Bus2SMP_PCP_RNW : std_logic;
signal clkAp : std_logic;
signal clkPcp : std_logic;
signal GND : std_logic;
signal IP2Bus_Error_s : std_logic;
signal IP2Bus_RdAck_s : std_logic;
signal IP2Bus_WrAck_s : std_logic;
signal mac_chipselect : std_logic;
signal MAC_CMP2Bus_Error : std_logic;
signal MAC_CMP2Bus_RdAck : std_logic;
signal MAC_CMP2Bus_WrAck : std_logic;
signal MAC_DMA2Bus_MstRd_dst_dsc_n : std_logic;
signal MAC_DMA2Bus_MstRd_dst_rdy_n : std_logic;
signal MAC_DMA2Bus_MstRd_Req : std_logic;
signal MAC_DMA2Bus_MstWr_eof_n : std_logic;
signal MAC_DMA2Bus_MstWr_Req : std_logic;
signal MAC_DMA2Bus_MstWr_sof_n : std_logic;
signal MAC_DMA2Bus_MstWr_src_dsc_n : std_logic;
signal MAC_DMA2Bus_MstWr_src_rdy_n : std_logic;
signal MAC_DMA2Bus_Mst_Lock : std_logic;
signal MAC_DMA2Bus_Mst_Reset : std_logic;
signal MAC_DMA2Bus_Mst_Type : std_logic;
signal mac_irq_s : std_logic;
signal MAC_PKT2Bus_Error : std_logic;
signal MAC_PKT2Bus_RdAck : std_logic;
signal MAC_PKT2Bus_WrAck : std_logic;
signal mac_read : std_logic;
signal MAC_REG2Bus_Error : std_logic;
signal MAC_REG2Bus_RdAck : std_logic;
signal MAC_REG2Bus_WrAck : std_logic;
signal mac_waitrequest : std_logic;
signal mac_write : std_logic;
signal mbf_chipselect : std_logic;
signal mbf_read : std_logic;
signal mbf_waitrequest : std_logic;
signal mbf_write : std_logic;
signal m_clk : std_logic;
signal m_read : std_logic;
signal m_readdatavalid : std_logic;
signal m_waitrequest : std_logic;
signal m_write : std_logic;
signal NET118078 : std_ulogic;
signal NET118214 : std_ulogic;
signal pcp_chipselect : std_logic;
signal pcp_read : std_logic;
signal pcp_waitrequest : std_logic;
signal pcp_write : std_logic;
signal PDI_AP2Bus_Error : std_logic;
signal PDI_AP2Bus_RdAck : std_logic;
signal PDI_AP2Bus_WrAck : std_logic;
signal PDI_PCP2Bus_Error : std_logic;
signal PDI_PCP2Bus_RdAck : std_logic;
signal PDI_PCP2Bus_WrAck : std_logic;
signal pkt_clk : std_logic;
signal rst : std_logic;
signal rstAp : std_logic;
signal rstPcp : std_logic;
signal smp_address : std_logic;
signal smp_chipselect : std_logic;
signal SMP_PCP2Bus_Error : std_logic;
signal SMP_PCP2Bus_RdAck : std_logic;
signal SMP_PCP2Bus_WrAck : std_logic;
signal smp_read : std_logic;
signal smp_waitrequest : std_logic;
signal smp_write : std_logic;
signal tcp_chipselect : std_logic;
signal tcp_irq_s : std_logic;
signal tcp_read : std_logic;
signal tcp_waitrequest : std_logic;
signal tcp_write : std_logic;
signal VCC : std_logic;
signal ap_address : std_logic_vector (12 downto 0);
signal ap_byteenable : std_logic_vector (3 downto 0);
signal ap_readdata : std_logic_vector (31 downto 0);
signal ap_writedata : std_logic_vector (31 downto 0);
signal Bus2MAC_DMA_MstRd_d : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal Bus2MAC_DMA_MstRd_d_s : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal Bus2MAC_DMA_MstRd_rem : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal Bus2MAC_PKT_Addr : std_logic_vector (C_MAC_PKT_PLB_AWIDTH-1 downto 0);
signal Bus2MAC_PKT_BE : std_logic_vector ((C_MAC_PKT_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_PKT_CS : std_logic_vector (0 downto 0);
signal Bus2MAC_PKT_Data : std_logic_vector (C_MAC_PKT_PLB_DWIDTH-1 downto 0);
signal Bus2MAC_REG_Addr : std_logic_vector (C_MAC_REG_PLB_AWIDTH-1 downto 0);
signal Bus2MAC_REG_BE : std_logic_vector ((C_MAC_REG_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_REG_BE_s : std_logic_vector ((C_MAC_REG_PLB_DWIDTH/8)-1 downto 0);
signal Bus2MAC_REG_CS : std_logic_vector (1 downto 0);
signal Bus2MAC_REG_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal Bus2MAC_REG_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal Bus2PDI_AP_Addr : std_logic_vector (C_PDI_AP_PLB_AWIDTH-1 downto 0);
signal Bus2PDI_AP_BE : std_logic_vector ((C_PDI_AP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2PDI_AP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_AP_Data : std_logic_vector (C_PDI_AP_PLB_DWIDTH-1 downto 0);
signal Bus2PDI_PCP_Addr : std_logic_vector (C_PDI_PCP_PLB_AWIDTH-1 downto 0);
signal Bus2PDI_PCP_BE : std_logic_vector ((C_PDI_PCP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2PDI_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_PCP_Data : std_logic_vector (C_PDI_PCP_PLB_DWIDTH-1 downto 0);
signal Bus2SMP_PCP_Addr : std_logic_vector (C_SMP_PCP_PLB_AWIDTH-1 downto 0);
signal Bus2SMP_PCP_BE : std_logic_vector ((C_SMP_PCP_PLB_DWIDTH/8)-1 downto 0);
signal Bus2SMP_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2SMP_PCP_Data : std_logic_vector (C_SMP_PCP_PLB_DWIDTH-1 downto 0);
signal IP2Bus_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal mac_address : std_logic_vector (C_MAC_REG_PLB_AWIDTH-1 downto 0);
signal mac_byteenable : std_logic_vector (1 downto 0);
signal MAC_CMP2Bus_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_d : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_d_s : std_logic_vector (C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_rem : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal MAC_DMA2Bus_Mst_Addr : std_logic_vector (0 to C_MAC_DMA_PLB_AWIDTH-1);
signal MAC_DMA2Bus_Mst_BE : std_logic_vector (0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1);
signal MAC_DMA2Bus_Mst_Length : std_logic_vector (0 to 11);
signal MAC_PKT2Bus_Data : std_logic_vector (C_MAC_PKT_PLB_DWIDTH-1 downto 0);
signal mac_readdata : std_logic_vector (15 downto 0);
signal MAC_REG2Bus_Data : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal MAC_REG2Bus_Data_s : std_logic_vector (C_MAC_REG_PLB_DWIDTH-1 downto 0);
signal mac_writedata : std_logic_vector (15 downto 0);
signal mbf_address : std_logic_vector (C_MAC_PKT_SIZE_LOG2-3 downto 0);
signal mbf_byteenable : std_logic_vector (3 downto 0);
signal mbf_readdata : std_logic_vector (31 downto 0);
signal mbf_writedata : std_logic_vector (31 downto 0);
signal m_address : std_logic_vector (31 downto 0) := (others => '0');
signal m_burstcount : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_burstcounter : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_byteenable : std_logic_vector (3 downto 0);
signal m_readdata : std_logic_vector (31 downto 0);
signal m_writedata : std_logic_vector (31 downto 0);
signal pcp_address : std_logic_vector (12 downto 0);
signal pcp_byteenable : std_logic_vector (3 downto 0);
signal pcp_readdata : std_logic_vector (31 downto 0);
signal pcp_writedata : std_logic_vector (31 downto 0);
signal PDI_AP2Bus_Data : std_logic_vector (C_PDI_AP_PLB_DWIDTH-1 downto 0);
signal PDI_PCP2Bus_Data : std_logic_vector (C_PDI_PCP_PLB_DWIDTH-1 downto 0);
signal smp_byteenable : std_logic_vector (3 downto 0);
signal SMP_PCP2Bus_Data : std_logic_vector (C_SMP_PCP_PLB_DWIDTH-1 downto 0);
signal smp_readdata : std_logic_vector (31 downto 0);
signal smp_writedata : std_logic_vector (31 downto 0);
signal tcp_address : std_logic_vector (1 downto 0);
signal tcp_byteenable : std_logic_vector (3 downto 0);
signal tcp_readdata : std_logic_vector (31 downto 0);
signal tcp_writedata : std_logic_vector (31 downto 0);
begin
---- User Signal Assignments ----
-- connect mac reg with mac cmp or reg output signals
with Bus2MAC_REG_CS select
IP2Bus_Data_s(C_MAC_REG_PLB_DWIDTH-1 downto 0) <= MAC_REG2Bus_Data(C_MAC_REG_PLB_DWIDTH-1 downto 0) when "10",
MAC_CMP2Bus_Data(C_MAC_REG_PLB_DWIDTH-1 downto 0) when "01",
(others => '0') when others;
with Bus2MAC_REG_CS select
IP2Bus_WrAck_s <= MAC_REG2Bus_WrAck when "10",
MAC_CMP2Bus_WrAck when "01",
'0' when others;
with Bus2MAC_REG_CS select
IP2Bus_RdAck_s <= MAC_REG2Bus_RdAck when "10",
MAC_CMP2Bus_RdAck when "01",
'0' when others;
with Bus2MAC_REG_CS select
IP2Bus_Error_s <= MAC_REG2Bus_Error when "10",
MAC_CMP2Bus_Error when "01",
'0' when others;
Bus2MAC_REG_BE_s <=
Bus2MAC_REG_BE(0) & Bus2MAC_REG_BE(1) &
Bus2MAC_REG_BE(2) & Bus2MAC_REG_BE(3);
Bus2MAC_REG_Data_s <=
Bus2MAC_REG_Data(7 downto 0) & Bus2MAC_REG_Data(15 downto 8) &
Bus2MAC_REG_Data(23 downto 16) & Bus2MAC_REG_Data(31 downto 24);
MAC_REG2Bus_Data <=
MAC_REG2Bus_Data_s(7 downto 0) & MAC_REG2Bus_Data_s(15 downto 8) &
MAC_REG2Bus_Data_s(23 downto 16) & MAC_REG2Bus_Data_s(31 downto 24);
--test_port
test_port(181 downto 179) <= mac_chipselect & mac_write & mac_read;
test_port(178) <= mac_waitrequest;
test_port(177 downto 176) <= mac_byteenable;
test_port(171 downto 160) <= mac_address(11 downto 0);
test_port(159 downto 144) <= mac_writedata;
test_port(143 downto 128) <= mac_readdata;
test_port(104 downto 102) <= Bus2MAC_REG_CS & Bus2MAC_REG_RNW;
test_port(101 downto 100) <= IP2Bus_WrAck_s & IP2Bus_RdAck_s;
test_port(99 downto 96) <= Bus2MAC_REG_BE;
test_port(95 downto 64) <= Bus2MAC_REG_Addr;
test_port(63 downto 32) <= Bus2MAC_REG_Data;
test_port(31 downto 0) <= IP2Bus_Data_s;
--test_port(255 downto 251) <= m_read & m_write & m_waitrequest & m_readdatavalid & MAC_DMA2Bus_Mst_Type;
--test_port(244 downto 240) <= MAC_DMA2Bus_MstWr_Req & MAC_DMA2Bus_MstWr_sof_n & MAC_DMA2Bus_MstWr_eof_n & MAC_DMA2Bus_MstWr_src_rdy_n & Bus2MAC_DMA_MstWr_dst_rdy_n;
--test_port(234 downto 230) <= MAC_DMA2Bus_MstRd_Req & Bus2MAC_DMA_MstRd_sof_n & Bus2MAC_DMA_MstRd_eof_n & Bus2MAC_DMA_MstRd_src_rdy_n & MAC_DMA2Bus_MstRd_dst_rdy_n;
--test_port(142 downto 140) <= Bus2MAC_DMA_Mst_Cmplt & Bus2MAC_DMA_Mst_Error & Bus2MAC_DMA_Mst_Cmd_Timeout;
--test_port(MAC_DMA2Bus_Mst_Length'length+120-1 downto 120) <= MAC_DMA2Bus_Mst_Length;
--test_port(m_burstcount'length+110-1 downto 110) <= m_burstcount;
--test_port(m_burstcounter'length+96-1 downto 96) <= m_burstcounter;
--test_port(95 downto 64) <= m_address;
--test_port(63 downto 32) <= m_writedata;
--test_port(31 downto 0) <= m_readdata;
--mac_cmp assignments
---cmp_clk <= Bus2MAC_CMP_Clk;
tcp_writedata <=
Bus2MAC_REG_Data(7 downto 0) & Bus2MAC_REG_Data(15 downto 8) &
Bus2MAC_REG_Data(23 downto 16) & Bus2MAC_REG_Data(31 downto 24);
tcp_read <= Bus2MAC_REG_RNW;
tcp_write <= not Bus2MAC_REG_RNW;
tcp_chipselect <= Bus2MAC_REG_CS(0);
tcp_byteenable <=
Bus2MAC_REG_BE(0) & Bus2MAC_REG_BE(1) &
Bus2MAC_REG_BE(2) & Bus2MAC_REG_BE(3);
tcp_address <= Bus2MAC_REG_Addr(3 downto 2);
MAC_CMP2Bus_Data <=
tcp_readdata(7 downto 0) & tcp_readdata(15 downto 8) &
tcp_readdata(23 downto 16) & tcp_readdata(31 downto 24);
MAC_CMP2Bus_RdAck <= tcp_chipselect and tcp_read and not tcp_waitrequest;
MAC_CMP2Bus_WrAck <= tcp_chipselect and tcp_write and not tcp_waitrequest;
MAC_CMP2Bus_Error <= '0';
--mac_pkt assignments
pkt_clk <= Bus2MAC_PKT_Clk;
mbf_writedata <=
Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
mbf_read <= Bus2MAC_PKT_RNW;
mbf_write <= not Bus2MAC_PKT_RNW;
mbf_chipselect <= Bus2MAC_PKT_CS(0);
mbf_byteenable <=
Bus2MAC_PKT_BE(0) & Bus2MAC_PKT_BE(1) &
Bus2MAC_PKT_BE(2) & Bus2MAC_PKT_BE(3);
mbf_address <= Bus2MAC_PKT_Addr(C_MAC_PKT_SIZE_LOG2-1 downto 2);
MAC_PKT2Bus_Data <=
mbf_readdata(7 downto 0) & mbf_readdata(15 downto 8) &
mbf_readdata(23 downto 16) & mbf_readdata(31 downto 24);
MAC_PKT2Bus_RdAck <= mbf_chipselect and mbf_read and not mbf_waitrequest;
MAC_PKT2Bus_WrAck <= mbf_chipselect and mbf_write and not mbf_waitrequest;
MAC_PKT2Bus_Error <= '0';
---- Component instantiations ----
MAC_REG_16to32 : openMAC_16to32conv
generic map (
bus_address_width => C_MAC_REG_PLB_AWIDTH,
gEndian => "big"
)
port map(
bus_ack_rd => MAC_REG2Bus_RdAck,
bus_ack_wr => MAC_REG2Bus_WrAck,
bus_address => Bus2MAC_REG_Addr( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
bus_byteenable => Bus2MAC_REG_BE_s( (C_MAC_REG_PLB_DWIDTH/8)-1 downto 0 ),
bus_read => Bus2MAC_REG_RNW,
bus_readdata => MAC_REG2Bus_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
bus_select => Bus2MAC_REG_CS(1),
bus_write => Bus2MAC_REG_RNW_n,
bus_writedata => Bus2MAC_REG_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
clk => clk50,
rst => rst,
s_address => mac_address( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
s_byteenable => mac_byteenable,
s_chipselect => mac_chipselect,
s_read => mac_read,
s_readdata => mac_readdata,
s_waitrequest => mac_waitrequest,
s_write => mac_write,
s_writedata => mac_writedata
);
MAC_REG_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_REG_BASE,C_MAC_REG_HIGH,C_MAC_CMP_BASE,C_MAC_CMP_HIGH),
C_ARD_NUM_CE_ARRAY => (1, 1),
C_BUS2CORE_CLK_RATIO => C_MAC_REG_BUS2CORE_CLK_RATIO,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_MAC_REG_PLB_DWIDTH,
C_SPLB_AWIDTH => C_MAC_REG_PLB_AWIDTH,
C_SPLB_DWIDTH => C_MAC_REG_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_MAC_REG_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_MAC_REG_PLB_NUM_MASTERS,
C_SPLB_P2P => C_MAC_REG_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2MAC_REG_Addr( C_MAC_REG_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_REG_BE( (C_MAC_REG_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_REG_CS( 1 downto 0 ),
Bus2IP_Clk => Bus2MAC_REG_Clk,
Bus2IP_Data => Bus2MAC_REG_Data( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_REG_RNW,
Bus2IP_Reset => Bus2MAC_REG_Reset,
IP2Bus_Data => IP2Bus_Data_s( C_MAC_REG_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => IP2Bus_Error_s,
IP2Bus_RdAck => IP2Bus_RdAck_s,
IP2Bus_WrAck => IP2Bus_WrAck_s,
PLB_ABus => MAC_REG_ABus,
PLB_BE => MAC_REG_BE( 0 to (C_MAC_REG_PLB_DWIDTH / 8) - 1 ),
PLB_MSize => MAC_REG_MSize,
PLB_PAValid => MAC_REG_PAValid,
PLB_RNW => MAC_REG_RNW,
PLB_SAValid => MAC_REG_SAValid,
PLB_TAttribute => MAC_REG_TAttribute,
PLB_UABus => MAC_REG_UABus,
PLB_abort => MAC_REG_abort,
PLB_busLock => MAC_REG_busLock,
PLB_lockErr => MAC_REG_lockErr,
PLB_masterID => MAC_REG_masterID( 0 to C_MAC_REG_PLB_MID_WIDTH - 1 ),
PLB_rdBurst => MAC_REG_rdBurst,
PLB_rdPendPri => MAC_REG_rdPendPri,
PLB_rdPendReq => MAC_REG_rdPendReq,
PLB_rdPrim => MAC_REG_rdPrim,
PLB_reqPri => MAC_REG_reqPri,
PLB_size => MAC_REG_size,
PLB_type => MAC_REG_type,
PLB_wrBurst => MAC_REG_wrBurst,
PLB_wrDBus => MAC_REG_wrDBus( 0 to C_MAC_REG_PLB_DWIDTH - 1 ),
PLB_wrPendPri => MAC_REG_wrPendPri,
PLB_wrPendReq => MAC_REG_wrPendReq,
PLB_wrPrim => MAC_REG_wrPrim,
SPLB_Clk => MAC_REG_Clk,
SPLB_Rst => MAC_REG_Rst,
Sl_MBusy => MAC_REG_MBusy( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MIRQ => MAC_REG_MIRQ( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MRdErr => MAC_REG_MRdErr( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_MWrErr => MAC_REG_MWrErr( 0 to C_MAC_REG_NUM_MASTERS-1 ),
Sl_SSize => MAC_REG_SSize,
Sl_addrAck => MAC_REG_addrAck,
Sl_rdBTerm => MAC_REG_rdBTerm,
Sl_rdComp => MAC_REG_rdComp,
Sl_rdDAck => MAC_REG_rdDAck,
Sl_rdDBus => MAC_REG_rdDBus( 0 to C_MAC_REG_PLB_DWIDTH-1 ),
Sl_rdWdAddr => MAC_REG_rdWdAddr,
Sl_rearbitrate => MAC_REG_rearbitrate,
Sl_wait => MAC_REG_wait,
Sl_wrBTerm => MAC_REG_wrBTerm,
Sl_wrComp => MAC_REG_wrComp,
Sl_wrDAck => MAC_REG_wrDAck
);
THE_POWERLINK_IP_CORE : powerlink
generic map (
Simulate => false,
endian_g => "big",
gNumSmi => C_NUM_SMI,
genABuf1_g => C_PDI_GEN_ASYNC_BUF_0,
genABuf2_g => C_PDI_GEN_ASYNC_BUF_1,
genEvent_g => C_PDI_GEN_EVENT,
genInternalAp_g => C_GEN_PLB_BUS_IF,
genIoBuf_g => false,
genLedGadget_g => C_PDI_GEN_LED,
genOnePdiClkDomain_g => false,
genPdi_g => C_GEN_PDI,
genSimpleIO_g => C_GEN_SIMPLE_IO,
genSmiIO => false,
genSpiAp_g => C_GEN_SPI_IF,
genTimeSync_g => C_PDI_GEN_TIME_SYNC,
gen_dma_observer_g => C_OBSERVER_ENABLE,
iAsyBuf1Size_g => C_PDI_ASYNC_BUF_0,
iAsyBuf2Size_g => C_PDI_ASYNC_BUF_1,
iBufSizeLOG2_g => C_MAC_PKT_SIZE_LOG2,
iBufSize_g => C_MAC_PKT_SIZE,
iPdiRev_g => 2,
iRpdo0BufSize_g => C_RPDO_0_BUF_SIZE,
iRpdo1BufSize_g => C_RPDO_1_BUF_SIZE,
iRpdo2BufSize_g => C_RPDO_2_BUF_SIZE,
iRpdos_g => C_NUM_RPDO,
iTpdoBufSize_g => C_TPDO_BUF_SIZE,
iTpdos_g => C_NUM_TPDO,
m_burstcount_const_g => true,
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH,
m_data_width_g => 32,
m_rx_burst_size_g => C_MAC_DMA_BURST_SIZE_RX/4,
m_rx_fifo_size_g => C_M_FIFO_SIZE_RX,
m_tx_burst_size_g => C_MAC_DMA_BURST_SIZE_TX/4,
m_tx_fifo_size_g => C_M_FIFO_SIZE_TX,
papBigEnd_g => false,
papDataWidth_g => C_PAP_DATA_WIDTH,
papLowAct_g => C_PAP_LOW_ACT,
pioValLen_g => C_PIO_VAL_LENGTH,
spiBigEnd_g => false,
spiCPHA_g => C_SPI_CPHA,
spiCPOL_g => C_SPI_CPOL,
use2ndCmpTimer_g => C_PDI_GEN_SECOND_TIMER,
use2ndPhy_g => C_USE_2ND_PHY,
useIntPacketBuf_g => C_MAC_PKT_EN,
useRmii_g => C_USE_RMII,
useRxIntPacketBuf_g => C_MAC_PKT_RX_EN
)
port map(
mac_address(0) => mac_address(0),
mac_address(1) => mac_address(1),
mac_address(2) => mac_address(2),
mac_address(3) => mac_address(3),
mac_address(4) => mac_address(4),
mac_address(5) => mac_address(5),
mac_address(6) => mac_address(6),
mac_address(7) => mac_address(7),
mac_address(8) => mac_address(8),
mac_address(9) => mac_address(9),
mac_address(10) => mac_address(10),
mac_address(11) => mac_address(11),
m_address(0) => m_address(0),
m_address(1) => m_address(1),
m_address(2) => m_address(2),
m_address(3) => m_address(3),
m_address(4) => m_address(4),
m_address(5) => m_address(5),
m_address(6) => m_address(6),
m_address(7) => m_address(7),
m_address(8) => m_address(8),
m_address(9) => m_address(9),
m_address(10) => m_address(10),
m_address(11) => m_address(11),
m_address(12) => m_address(12),
m_address(13) => m_address(13),
m_address(14) => m_address(14),
m_address(15) => m_address(15),
m_address(16) => m_address(16),
m_address(17) => m_address(17),
m_address(18) => m_address(18),
m_address(19) => m_address(19),
m_address(20) => m_address(20),
m_address(21) => m_address(21),
m_address(22) => m_address(22),
m_address(23) => m_address(23),
m_address(24) => m_address(24),
m_address(25) => m_address(25),
m_address(26) => m_address(26),
m_address(27) => m_address(27),
m_address(28) => m_address(28),
m_address(29) => m_address(29),
ap_address => ap_address,
ap_asyncIrq => ap_asyncIrq,
ap_asyncIrq_n => ap_asyncIrq_n,
ap_byteenable => ap_byteenable,
ap_chipselect => ap_chipselect,
ap_read => ap_read,
ap_readdata => ap_readdata,
ap_syncIrq => ap_syncIrq,
ap_syncIrq_n => ap_syncIrq_n,
ap_waitrequest => ap_waitrequest,
ap_write => ap_write,
ap_writedata => ap_writedata,
clk50 => clk50,
clkAp => clkAp,
clkEth => clk100,
clkPcp => clkPcp,
led_error => led_error,
led_gpo => led_gpo,
led_opt => led_opt,
led_phyAct => led_phyAct,
led_phyLink => led_phyLink,
led_status => led_status,
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable( 3 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( 31 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( 31 downto 0 ),
mac_byteenable => mac_byteenable,
mac_chipselect => mac_chipselect,
mac_irq => mac_irq_s,
mac_read => mac_read,
mac_readdata => mac_readdata,
mac_waitrequest => mac_waitrequest,
mac_write => mac_write,
mac_writedata => mac_writedata,
mbf_address => mbf_address( C_MAC_PKT_SIZE_LOG2-3 downto 0 ),
mbf_byteenable => mbf_byteenable,
mbf_chipselect => mbf_chipselect,
mbf_read => mbf_read,
mbf_readdata => mbf_readdata,
mbf_waitrequest => mbf_waitrequest,
mbf_write => mbf_write,
mbf_writedata => mbf_writedata,
pap_ack => pap_ack,
pap_ack_n => pap_ack_n,
pap_addr => pap_addr,
pap_be => pap_be( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_be_n => pap_be_n( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_cs => pap_cs,
pap_cs_n => pap_cs_n,
pap_data_I => pap_data_I( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_O => pap_data_O( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_T => pap_data_T,
pap_gpio_I => pap_gpio_I,
pap_gpio_O => pap_gpio_O,
pap_gpio_T => pap_gpio_T,
pap_rd => pap_rd,
pap_rd_n => pap_rd_n,
pap_wr => pap_wr,
pap_wr_n => pap_wr_n,
pcp_address => pcp_address,
pcp_byteenable => pcp_byteenable,
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_write => pcp_write,
pcp_writedata => pcp_writedata,
phy0_Rst_n => phy0_Rst_n,
phy0_RxDat => phy0_RxDat,
phy0_RxDv => phy0_RxDv,
phy0_RxErr => phy0_RxErr,
phy0_SMIClk => phy0_SMIClk,
phy0_SMIDat_I => phy0_SMIDat_I,
phy0_SMIDat_O => phy0_SMIDat_O,
phy0_SMIDat_T => phy0_SMIDat_T,
phy0_TxDat => phy0_TxDat,
phy0_TxEn => phy0_TxEn,
phy0_link => phy0_link,
phy1_Rst_n => phy1_Rst_n,
phy1_RxDat => phy1_RxDat,
phy1_RxDv => phy1_RxDv,
phy1_RxErr => phy1_RxErr,
phy1_SMIClk => phy1_SMIClk,
phy1_SMIDat_I => phy1_SMIDat_I,
phy1_SMIDat_O => phy1_SMIDat_O,
phy1_SMIDat_T => phy1_SMIDat_T,
phy1_TxDat => phy1_TxDat,
phy1_TxEn => phy1_TxEn,
phy1_link => phy1_link,
phyMii0_RxClk => phyMii0_RxClk,
phyMii0_RxDat => phyMii0_RxDat,
phyMii0_RxDv => phyMii0_RxDv,
phyMii0_RxEr => phyMii0_RxEr,
phyMii0_TxClk => phyMii0_TxClk,
phyMii0_TxDat => phyMii0_TxDat,
phyMii0_TxEn => phyMii0_TxEn,
phyMii0_TxEr => phyMii0_TxEr,
phyMii1_RxClk => phyMii1_RxClk,
phyMii1_RxDat => phyMii1_RxDat,
phyMii1_RxDv => phyMii1_RxDv,
phyMii1_RxEr => phyMii1_RxEr,
phyMii1_TxClk => phyMii1_TxClk,
phyMii1_TxDat => phyMii1_TxDat,
phyMii1_TxEn => phyMii1_TxEn,
phyMii1_TxEr => phyMii1_TxEr,
phy_Rst_n => phy_Rst_n,
phy_SMIClk => phy_SMIClk,
phy_SMIDat_I => phy_SMIDat_I,
phy_SMIDat_O => phy_SMIDat_O,
phy_SMIDat_T => phy_SMIDat_T,
pio_operational => pio_operational,
pio_pconfig => pio_pconfig,
pio_portInLatch => pio_portInLatch,
pio_portOutValid => pio_portOutValid,
pio_portio_I => pio_portio_I,
pio_portio_O => pio_portio_O,
pio_portio_T => pio_portio_T,
pkt_clk => pkt_clk,
rst => rst,
rstAp => rstAp,
rstPcp => rstPcp,
smp_address => smp_address,
smp_byteenable => smp_byteenable,
smp_read => smp_read,
smp_readdata => smp_readdata,
smp_waitrequest => smp_waitrequest,
smp_write => smp_write,
smp_writedata => smp_writedata,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
spi_sel_n => spi_sel_n,
tcp_address => tcp_address,
tcp_byteenable => tcp_byteenable,
tcp_chipselect => tcp_chipselect,
tcp_irq => tcp_irq_s,
tcp_read => tcp_read,
tcp_readdata => tcp_readdata,
tcp_waitrequest => tcp_waitrequest,
tcp_write => tcp_write,
tcp_writedata => tcp_writedata
);
rst <= Bus2MAC_REG_Reset or Bus2MAC_CMP_Reset or MAC_DMA_RST or Bus2MAC_PKT_Reset;
Bus2MAC_REG_RNW_n <= not(Bus2MAC_REG_RNW);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
GND <= GND_CONSTANT;
MAC_REG2Bus_Error <= GND;
---- Terminal assignment ----
-- Output\buffer terminals
mac_irq <= mac_irq_s;
tcp_irq <= tcp_irq_s;
---- Generate statements ----
genMacDmaPlbBurst : if C_DMA_EN = TRUE generate
begin
MAC_DMA_PLB_BURST_MASTER : plbv46_master_burst
generic map (
C_FAMILY => C_FAMILY,
C_INHIBIT_CC_BLE_INCLUSION => 1,
C_MPLB_AWIDTH => C_MAC_DMA_PLB_AWIDTH,
C_MPLB_DWIDTH => C_MAC_DMA_PLB_DWIDTH,
C_MPLB_NATIVE_DWIDTH => C_MAC_DMA_PLB_NATIVE_DWIDTH,
C_MPLB_SMALLEST_SLAVE => 32
)
port map(
Bus2IP_MstRd_d => Bus2MAC_DMA_MstRd_d( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
Bus2IP_MstRd_eof_n => Bus2MAC_DMA_MstRd_eof_n,
Bus2IP_MstRd_rem => Bus2MAC_DMA_MstRd_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
Bus2IP_MstRd_sof_n => Bus2MAC_DMA_MstRd_sof_n,
Bus2IP_MstRd_src_dsc_n => Bus2MAC_DMA_MstRd_src_dsc_n,
Bus2IP_MstRd_src_rdy_n => Bus2MAC_DMA_MstRd_src_rdy_n,
Bus2IP_MstWr_dst_dsc_n => Bus2MAC_DMA_MstWr_dst_dsc_n,
Bus2IP_MstWr_dst_rdy_n => Bus2MAC_DMA_MstWr_dst_rdy_n,
Bus2IP_Mst_CmdAck => Bus2MAC_DMA_Mst_CmdAck,
Bus2IP_Mst_Cmd_Timeout => Bus2MAC_DMA_Mst_Cmd_Timeout,
Bus2IP_Mst_Cmplt => Bus2MAC_DMA_Mst_Cmplt,
Bus2IP_Mst_Error => Bus2MAC_DMA_Mst_Error,
Bus2IP_Mst_Rearbitrate => Bus2MAC_DMA_Mst_Rearbitrate,
IP2Bus_MstRd_Req => MAC_DMA2Bus_MstRd_Req,
IP2Bus_MstRd_dst_dsc_n => MAC_DMA2Bus_MstRd_dst_dsc_n,
IP2Bus_MstRd_dst_rdy_n => MAC_DMA2Bus_MstRd_dst_rdy_n,
IP2Bus_MstWr_Req => MAC_DMA2Bus_MstWr_Req,
IP2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
IP2Bus_MstWr_eof_n => MAC_DMA2Bus_MstWr_eof_n,
IP2Bus_MstWr_rem => MAC_DMA2Bus_MstWr_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
IP2Bus_MstWr_sof_n => MAC_DMA2Bus_MstWr_sof_n,
IP2Bus_MstWr_src_dsc_n => MAC_DMA2Bus_MstWr_src_dsc_n,
IP2Bus_MstWr_src_rdy_n => MAC_DMA2Bus_MstWr_src_rdy_n,
IP2Bus_Mst_Addr => MAC_DMA2Bus_Mst_Addr( 0 to C_MAC_DMA_PLB_AWIDTH-1 ),
IP2Bus_Mst_BE => MAC_DMA2Bus_Mst_BE( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
IP2Bus_Mst_Length => MAC_DMA2Bus_Mst_Length,
IP2Bus_Mst_Lock => MAC_DMA2Bus_Mst_Lock,
IP2Bus_Mst_Reset => MAC_DMA2Bus_Mst_Reset,
IP2Bus_Mst_Type => MAC_DMA2Bus_Mst_Type,
MD_Error => MAC_DMA_error,
MPLB_Clk => MAC_DMA_Clk,
MPLB_Rst => MAC_DMA_Rst,
M_ABus => MAC_DMA_ABus,
M_BE => MAC_DMA_BE( 0 to (C_MAC_DMA_PLB_DWIDTH/8)-1 ),
M_MSize => MAC_DMA_MSize,
M_RNW => MAC_DMA_RNW,
M_TAttribute => MAC_DMA_TAttribute,
M_UABus => MAC_DMA_UABus,
M_abort => MAC_DMA_abort,
M_busLock => MAC_DMA_busLock,
M_lockErr => MAC_DMA_lockErr,
M_priority => MAC_DMA_priority,
M_rdBurst => MAC_DMA_rdBurst,
M_request => MAC_DMA_request,
M_size => MAC_DMA_size,
M_type => MAC_DMA_type,
M_wrBurst => MAC_DMA_wrBurst,
M_wrDBus => MAC_DMA_wrDBus( 0 to C_MAC_DMA_PLB_DWIDTH-1 ),
PLB_MAddrAck => MAC_DMA_MAddrAck,
PLB_MBusy => MAC_DMA_MBusy,
PLB_MIRQ => MAC_DMA_MIRQ,
PLB_MRdBTerm => MAC_DMA_MRdBTerm,
PLB_MRdDAck => MAC_DMA_MRdDAck,
PLB_MRdDBus => MAC_DMA_MRdDBus( 0 to C_MAC_DMA_PLB_DWIDTH-1 ),
PLB_MRdErr => MAC_DMA_MRdErr,
PLB_MRdWdAddr => MAC_DMA_MRdWdAddr,
PLB_MRearbitrate => MAC_DMA_MRearbitrate,
PLB_MSSize => MAC_DMA_MSSize,
PLB_MTimeout => MAC_DMA_MTimeout,
PLB_MWrBTerm => MAC_DMA_MWrBTerm,
PLB_MWrDAck => MAC_DMA_MWrDAck,
PLB_MWrErr => MAC_DMA_MWrErr
);
end generate genMacDmaPlbBurst;
oddr2_0 : if not C_INSTANCE_ODDR2 generate
begin
phy0_clk <= clk50;
phy1_clk <= clk50;
end generate oddr2_0;
oddr2_1 : if C_INSTANCE_ODDR2 generate
begin
U4 : ODDR2
port map(
C0 => clk50,
C1 => NET118078,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy0_clk,
R => GND,
S => GND
);
NET118078 <= not(clk50);
U6 : ODDR2
port map(
C0 => clk50,
C1 => NET118214,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy1_clk,
R => GND,
S => GND
);
NET118214 <= not(clk50);
end generate oddr2_1;
genThePlbMaster : if C_DMA_EN = TRUE generate
begin
THE_IPIF_MASTER_HANDLER : ipif_master_handler
generic map (
dma_highadr_g => m_address'high,
gen_rx_fifo_g => not C_RX_INT_PKT,
gen_tx_fifo_g => not C_TX_INT_PKT,
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH
)
port map(
Bus2MAC_DMA_MstRd_d => Bus2MAC_DMA_MstRd_d_s( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
Bus2MAC_DMA_MstRd_eof_n => Bus2MAC_DMA_MstRd_eof_n,
Bus2MAC_DMA_MstRd_rem => Bus2MAC_DMA_MstRd_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
Bus2MAC_DMA_MstRd_sof_n => Bus2MAC_DMA_MstRd_sof_n,
Bus2MAC_DMA_MstRd_src_dsc_n => Bus2MAC_DMA_MstRd_src_dsc_n,
Bus2MAC_DMA_MstRd_src_rdy_n => Bus2MAC_DMA_MstRd_src_rdy_n,
Bus2MAC_DMA_MstWr_dst_dsc_n => Bus2MAC_DMA_MstWr_dst_dsc_n,
Bus2MAC_DMA_MstWr_dst_rdy_n => Bus2MAC_DMA_MstWr_dst_rdy_n,
Bus2MAC_DMA_Mst_CmdAck => Bus2MAC_DMA_Mst_CmdAck,
Bus2MAC_DMA_Mst_Cmd_Timeout => Bus2MAC_DMA_Mst_Cmd_Timeout,
Bus2MAC_DMA_Mst_Cmplt => Bus2MAC_DMA_Mst_Cmplt,
Bus2MAC_DMA_Mst_Error => Bus2MAC_DMA_Mst_Error,
Bus2MAC_DMA_Mst_Rearbitrate => Bus2MAC_DMA_Mst_Rearbitrate,
MAC_DMA2Bus_MstRd_Req => MAC_DMA2Bus_MstRd_Req,
MAC_DMA2Bus_MstRd_dst_dsc_n => MAC_DMA2Bus_MstRd_dst_dsc_n,
MAC_DMA2Bus_MstRd_dst_rdy_n => MAC_DMA2Bus_MstRd_dst_rdy_n,
MAC_DMA2Bus_MstWr_Req => MAC_DMA2Bus_MstWr_Req,
MAC_DMA2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d_s( C_MAC_DMA_PLB_NATIVE_DWIDTH-1 downto 0 ),
MAC_DMA2Bus_MstWr_eof_n => MAC_DMA2Bus_MstWr_eof_n,
MAC_DMA2Bus_MstWr_rem => MAC_DMA2Bus_MstWr_rem( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
MAC_DMA2Bus_MstWr_sof_n => MAC_DMA2Bus_MstWr_sof_n,
MAC_DMA2Bus_MstWr_src_dsc_n => MAC_DMA2Bus_MstWr_src_dsc_n,
MAC_DMA2Bus_MstWr_src_rdy_n => MAC_DMA2Bus_MstWr_src_rdy_n,
MAC_DMA2Bus_Mst_Addr => MAC_DMA2Bus_Mst_Addr( 0 to C_MAC_DMA_PLB_AWIDTH-1 ),
MAC_DMA2Bus_Mst_BE => MAC_DMA2Bus_Mst_BE( 0 to (C_MAC_DMA_PLB_NATIVE_DWIDTH/8)-1 ),
MAC_DMA2Bus_Mst_Length => MAC_DMA2Bus_Mst_Length,
MAC_DMA2Bus_Mst_Lock => MAC_DMA2Bus_Mst_Lock,
MAC_DMA2Bus_Mst_Reset => MAC_DMA2Bus_Mst_Reset,
MAC_DMA2Bus_Mst_Type => MAC_DMA2Bus_Mst_Type,
MAC_DMA_CLK => MAC_DMA_CLK,
MAC_DMA_Rst => MAC_DMA_Rst,
m_address => m_address( 31 downto 0 ),
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable,
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata
);
Bus2MAC_DMA_MstRd_d_s <= Bus2MAC_DMA_MstRd_d(7 downto 0) & Bus2MAC_DMA_MstRd_d(15 downto 8) &
Bus2MAC_DMA_MstRd_d(23 downto 16) & Bus2MAC_DMA_MstRd_d(31 downto 24);
MAC_DMA2Bus_MstWr_d <= MAC_DMA2Bus_MstWr_d_s(7 downto 0) & MAC_DMA2Bus_MstWr_d_s(15 downto 8) &
MAC_DMA2Bus_MstWr_d_s(23 downto 16) & MAC_DMA2Bus_MstWr_d_s(31 downto 24);
end generate genThePlbMaster;
genMacPktPLbSingleSlave : if C_PKT_BUF_EN generate
begin
MAC_PKT_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_PKT_BASE,C_MAC_PKT_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_MAC_PKT_PLB_DWIDTH,
C_SPLB_AWIDTH => C_MAC_PKT_PLB_AWIDTH,
C_SPLB_DWIDTH => C_MAC_PKT_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_MAC_PKT_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_MAC_PKT_PLB_NUM_MASTERS,
C_SPLB_P2P => C_MAC_PKT_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2MAC_PKT_Addr( C_MAC_PKT_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_PKT_BE( (C_MAC_PKT_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_PKT_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2MAC_PKT_Clk,
Bus2IP_Data => Bus2MAC_PKT_Data( C_MAC_PKT_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_PKT_RNW,
Bus2IP_Reset => Bus2MAC_PKT_Reset,
IP2Bus_Data => MAC_PKT2Bus_Data( C_MAC_PKT_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => MAC_PKT2Bus_Error,
IP2Bus_RdAck => MAC_PKT2Bus_RdAck,
IP2Bus_WrAck => MAC_PKT2Bus_WrAck,
PLB_ABus => MAC_PKT_ABus,
PLB_BE => MAC_PKT_BE( 0 to (C_MAC_PKT_PLB_DWIDTH/8)-1 ),
PLB_MSize => MAC_PKT_MSize,
PLB_PAValid => MAC_PKT_PAValid,
PLB_RNW => MAC_PKT_RNW,
PLB_SAValid => MAC_PKT_SAValid,
PLB_TAttribute => MAC_PKT_TAttribute,
PLB_UABus => MAC_PKT_UABus,
PLB_abort => MAC_PKT_abort,
PLB_busLock => MAC_PKT_busLock,
PLB_lockErr => MAC_PKT_lockErr,
PLB_masterID => MAC_PKT_masterID( 0 to C_MAC_PKT_PLB_MID_WIDTH-1 ),
PLB_rdBurst => MAC_PKT_rdBurst,
PLB_rdPendPri => MAC_PKT_rdPendPri,
PLB_rdPendReq => MAC_PKT_rdPendReq,
PLB_rdPrim => MAC_PKT_rdPrim,
PLB_reqPri => MAC_PKT_reqPri,
PLB_size => MAC_PKT_size,
PLB_type => MAC_PKT_type,
PLB_wrBurst => MAC_PKT_wrBurst,
PLB_wrDBus => MAC_PKT_wrDBus( 0 to C_MAC_PKT_PLB_DWIDTH-1 ),
PLB_wrPendPri => MAC_PKT_wrPendPri,
PLB_wrPendReq => MAC_PKT_wrPendReq,
PLB_wrPrim => MAC_PKT_wrPrim,
SPLB_Clk => MAC_PKT_Clk,
SPLB_Rst => MAC_PKT_Rst,
Sl_MBusy => MAC_PKT_MBusy( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MIRQ => MAC_PKT_MIRQ( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MRdErr => MAC_PKT_MRdErr( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_MWrErr => MAC_PKT_MWrErr( 0 to C_MAC_PKT_NUM_MASTERS-1 ),
Sl_SSize => MAC_PKT_SSize,
Sl_addrAck => MAC_PKT_addrAck,
Sl_rdBTerm => MAC_PKT_rdBTerm,
Sl_rdComp => MAC_PKT_rdComp,
Sl_rdDAck => MAC_PKT_rdDAck,
Sl_rdDBus => MAC_PKT_rdDBus( 0 to C_MAC_PKT_PLB_DWIDTH-1 ),
Sl_rdWdAddr => MAC_PKT_rdWdAddr,
Sl_rearbitrate => MAC_PKT_rearbitrate,
Sl_wait => MAC_PKT_wait,
Sl_wrBTerm => MAC_PKT_wrBTerm,
Sl_wrComp => MAC_PKT_wrComp,
Sl_wrDAck => MAC_PKT_wrDAck
);
end generate genMacPktPLbSingleSlave;
genPdiPcp : if (C_GEN_PDI) generate
begin
PDI_PCP_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_PCP_BASE,C_PDI_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_PDI_PCP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_PDI_PCP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_PDI_PCP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_PDI_PCP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_PDI_PCP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_PDI_PCP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2PDI_PCP_Addr( C_PDI_PCP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_PCP_BE( (C_PDI_PCP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_PCP_Clk,
Bus2IP_Data => Bus2PDI_PCP_Data( C_PDI_PCP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_PCP_RNW,
Bus2IP_Reset => Bus2PDI_PCP_Reset,
IP2Bus_Data => PDI_PCP2Bus_Data( C_PDI_PCP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => PDI_PCP2Bus_Error,
IP2Bus_RdAck => PDI_PCP2Bus_RdAck,
IP2Bus_WrAck => PDI_PCP2Bus_WrAck,
PLB_ABus => PDI_PCP_ABus,
PLB_BE => PDI_PCP_BE( 0 to (C_PDI_PCP_PLB_DWIDTH/8)-1 ),
PLB_MSize => PDI_PCP_MSize,
PLB_PAValid => PDI_PCP_PAValid,
PLB_RNW => PDI_PCP_RNW,
PLB_SAValid => PDI_PCP_SAValid,
PLB_TAttribute => PDI_PCP_TAttribute,
PLB_UABus => PDI_PCP_UABus,
PLB_abort => PDI_PCP_abort,
PLB_busLock => PDI_PCP_busLock,
PLB_lockErr => PDI_PCP_lockErr,
PLB_masterID => PDI_PCP_masterID( 0 to C_PDI_PCP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => PDI_PCP_rdBurst,
PLB_rdPendPri => PDI_PCP_rdPendPri,
PLB_rdPendReq => PDI_PCP_rdPendReq,
PLB_rdPrim => PDI_PCP_rdPrim,
PLB_reqPri => PDI_PCP_reqPri,
PLB_size => PDI_PCP_size,
PLB_type => PDI_PCP_type,
PLB_wrBurst => PDI_PCP_wrBurst,
PLB_wrDBus => PDI_PCP_wrDBus( 0 to C_PDI_PCP_PLB_DWIDTH-1 ),
PLB_wrPendPri => PDI_PCP_wrPendPri,
PLB_wrPendReq => PDI_PCP_wrPendReq,
PLB_wrPrim => PDI_PCP_wrPrim,
SPLB_Clk => PDI_PCP_Clk,
SPLB_Rst => PDI_PCP_Rst,
Sl_MBusy => PDI_PCP_MBusy( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MIRQ => PDI_PCP_MIRQ( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MRdErr => PDI_PCP_MRdErr( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_MWrErr => PDI_PCP_MWrErr( 0 to C_PDI_PCP_NUM_MASTERS-1 ),
Sl_SSize => PDI_PCP_SSize,
Sl_addrAck => PDI_PCP_addrAck,
Sl_rdBTerm => PDI_PCP_rdBTerm,
Sl_rdComp => PDI_PCP_rdComp,
Sl_rdDAck => PDI_PCP_rdDAck,
Sl_rdDBus => PDI_PCP_rdDBus( 0 to C_PDI_PCP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => PDI_PCP_rdWdAddr,
Sl_rearbitrate => PDI_PCP_rearbitrate,
Sl_wait => PDI_PCP_wait,
Sl_wrBTerm => PDI_PCP_wrBTerm,
Sl_wrComp => PDI_PCP_wrComp,
Sl_wrDAck => PDI_PCP_wrDAck
);
end generate genPdiPcp;
genPcpPdiLink : if C_GEN_PDI generate
begin
--pdi_pcp assignments
clkPcp <= Bus2PDI_PCP_Clk;
rstPcp <= Bus2PDI_PCP_Reset;
--pcp_writedata <= Bus2PDI_PCP_Data;
pcp_writedata <= Bus2PDI_PCP_Data(7 downto 0) & Bus2PDI_PCP_Data(15 downto 8) & Bus2PDI_PCP_Data(23 downto 16) & Bus2PDI_PCP_Data(31 downto 24);
--pcp_writedata <= Bus2PDI_PCP_Data(15 downto 0) & Bus2PDI_PCP_Data(31 downto 16) when Bus2PDI_PCP_BE = "1100" or Bus2PDI_PCP_BE = "0011" else
-- Bus2PDI_PCP_Data(15 downto 8) & Bus2PDI_PCP_Data(7 downto 0) & Bus2PDI_PCP_Data(31 downto 24) & Bus2PDI_PCP_Data(23 downto 16) when Bus2PDI_PCP_BE = "1000" or Bus2PDI_PCP_BE = "0100" or Bus2PDI_PCP_BE = "0010" or Bus2PDI_PCP_BE = "0001" else
-- Bus2PDI_PCP_Data;
pcp_read <= Bus2PDI_PCP_RNW;
pcp_write <= not Bus2PDI_PCP_RNW;
pcp_chipselect <= Bus2PDI_PCP_CS(0);
--pcp_byteenable <= Bus2PDI_PCP_BE;
pcp_byteenable <= Bus2PDI_PCP_BE(0) & Bus2PDI_PCP_BE(1) & Bus2PDI_PCP_BE(2) & Bus2PDI_PCP_BE(3);
pcp_address <= Bus2PDI_PCP_Addr(14 downto 2);
--PDI_PCP2Bus_Data <= pcp_readdata;
PDI_PCP2Bus_Data <= pcp_readdata(7 downto 0) & pcp_readdata(15 downto 8) & pcp_readdata(23 downto 16) & pcp_readdata(31 downto 24);
PDI_PCP2Bus_RdAck <= pcp_chipselect and pcp_read and not pcp_waitrequest;
PDI_PCP2Bus_WrAck <= pcp_chipselect and pcp_write and not pcp_waitrequest;
PDI_PCP2Bus_Error <= '0';
end generate genPcpPdiLink;
genPdiAp : if (C_GEN_PLB_BUS_IF) generate
begin
PDI_AP_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_AP_BASE,C_PDI_AP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_PDI_AP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_PDI_AP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_PDI_AP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_PDI_AP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_PDI_AP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_PDI_AP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2PDI_AP_Addr( C_PDI_AP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_AP_BE( (C_PDI_AP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_AP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_AP_Clk,
Bus2IP_Data => Bus2PDI_AP_Data( C_PDI_AP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_AP_RNW,
Bus2IP_Reset => Bus2PDI_AP_Reset,
IP2Bus_Data => PDI_AP2Bus_Data( C_PDI_AP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => PDI_AP2Bus_Error,
IP2Bus_RdAck => PDI_AP2Bus_RdAck,
IP2Bus_WrAck => PDI_AP2Bus_WrAck,
PLB_ABus => PDI_AP_ABus,
PLB_BE => PDI_AP_BE( 0 to (C_PDI_AP_PLB_DWIDTH/8)-1 ),
PLB_MSize => PDI_AP_MSize,
PLB_PAValid => PDI_AP_PAValid,
PLB_RNW => PDI_AP_RNW,
PLB_SAValid => PDI_AP_SAValid,
PLB_TAttribute => PDI_AP_TAttribute,
PLB_UABus => PDI_AP_UABus,
PLB_abort => PDI_AP_abort,
PLB_busLock => PDI_AP_busLock,
PLB_lockErr => PDI_AP_lockErr,
PLB_masterID => PDI_AP_masterID( 0 to C_PDI_AP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => PDI_AP_rdBurst,
PLB_rdPendPri => PDI_AP_rdPendPri,
PLB_rdPendReq => PDI_AP_rdPendReq,
PLB_rdPrim => PDI_AP_rdPrim,
PLB_reqPri => PDI_AP_reqPri,
PLB_size => PDI_AP_size,
PLB_type => PDI_AP_type,
PLB_wrBurst => PDI_AP_wrBurst,
PLB_wrDBus => PDI_AP_wrDBus( 0 to C_PDI_AP_PLB_DWIDTH-1 ),
PLB_wrPendPri => PDI_AP_wrPendPri,
PLB_wrPendReq => PDI_AP_wrPendReq,
PLB_wrPrim => PDI_AP_wrPrim,
SPLB_Clk => PDI_AP_Clk,
SPLB_Rst => PDI_AP_Rst,
Sl_MBusy => PDI_AP_MBusy( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MIRQ => PDI_AP_MIRQ( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MRdErr => PDI_AP_MRdErr( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_MWrErr => PDI_AP_MWrErr( 0 to C_PDI_AP_PLB_NUM_MASTERS-1 ),
Sl_SSize => PDI_AP_SSize,
Sl_addrAck => PDI_AP_addrAck,
Sl_rdBTerm => PDI_AP_rdBTerm,
Sl_rdComp => PDI_AP_rdComp,
Sl_rdDAck => PDI_AP_rdDAck,
Sl_rdDBus => PDI_AP_rdDBus( 0 to C_PDI_AP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => PDI_AP_rdWdAddr,
Sl_rearbitrate => PDI_AP_rearbitrate,
Sl_wait => PDI_AP_wait,
Sl_wrBTerm => PDI_AP_wrBTerm,
Sl_wrComp => PDI_AP_wrComp,
Sl_wrDAck => PDI_AP_wrDAck
);
end generate genPdiAp;
genApPdiLink : if C_GEN_PDI generate
begin
--ap_pcp assignments
clkAp <= Bus2PDI_AP_Clk;
rstAp <= Bus2PDI_AP_Reset;
--ap_writedata <= Bus2PDI_AP_Data;
ap_writedata <= Bus2PDI_AP_Data(7 downto 0) & Bus2PDI_AP_Data(15 downto 8) & Bus2PDI_AP_Data(23 downto 16) & Bus2PDI_AP_Data(31 downto 24);
ap_read <= Bus2PDI_AP_RNW;
ap_write <= not Bus2PDI_AP_RNW;
ap_chipselect <= Bus2PDI_AP_CS(0);
--ap_byteenable <= Bus2PDI_AP_BE;
ap_byteenable <= Bus2PDI_AP_BE(0) & Bus2PDI_AP_BE(1) & Bus2PDI_AP_BE(2) & Bus2PDI_AP_BE(3);
ap_address <= Bus2PDI_AP_Addr(14 downto 2);
--PDI_AP2Bus_Data <= ap_readdata;
PDI_AP2Bus_Data <= ap_readdata(7 downto 0) & ap_readdata(15 downto 8) & ap_readdata(23 downto 16) & ap_readdata(31 downto 24);
PDI_AP2Bus_RdAck <= ap_chipselect and ap_read and not ap_waitrequest;
PDI_AP2Bus_WrAck <= ap_chipselect and ap_write and not ap_waitrequest;
PDI_AP2Bus_Error <= '0';
end generate genApPdiLink;
genSimpleIoSignals : if C_GEN_SIMPLE_IO generate
begin
--SMP_PCP assignments
clkPcp <= Bus2SMP_PCP_Clk;
rstPcp <= Bus2SMP_PCP_Reset;
--smp_writedata <= Bus2SMP_PCP_Data;
smp_writedata <= Bus2SMP_PCP_Data(7 downto 0) & Bus2SMP_PCP_Data(15 downto 8) & Bus2SMP_PCP_Data(23 downto 16) & Bus2SMP_PCP_Data(31 downto 24);
smp_read <= Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_write <= not Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_chipselect <= Bus2SMP_PCP_CS(0);
--smp_byteenable <= Bus2SMP_PCP_BE;
smp_byteenable <= Bus2SMP_PCP_BE(0) & Bus2SMP_PCP_BE(1) & Bus2SMP_PCP_BE(2) & Bus2SMP_PCP_BE(3);
smp_address <= Bus2SMP_PCP_Addr(2);
--SMP_PCP2Bus_Data <= smp_readdata;
SMP_PCP2Bus_Data <= smp_readdata(7 downto 0) & smp_readdata(15 downto 8) & smp_readdata(23 downto 16) & smp_readdata(31 downto 24);
SMP_PCP2Bus_RdAck <= smp_chipselect and smp_read and not smp_waitrequest;
SMP_PCP2Bus_WrAck <= smp_chipselect and smp_write and not smp_waitrequest;
SMP_PCP2Bus_Error <= '0';
end generate genSimpleIoSignals;
genSmpIo : if (C_GEN_SIMPLE_IO) generate
begin
SMP_IO_PLB_SINGLE_SLAVE : plbv46_slave_single
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_SMP_PCP_BASE,C_SMP_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0 => 1),
C_BUS2CORE_CLK_RATIO => 1,
C_FAMILY => C_FAMILY,
C_INCLUDE_DPHASE_TIMER => 0,
C_SIPIF_DWIDTH => C_SMP_PCP_PLB_DWIDTH,
C_SPLB_AWIDTH => C_SMP_PCP_PLB_AWIDTH,
C_SPLB_DWIDTH => C_SMP_PCP_PLB_DWIDTH,
C_SPLB_MID_WIDTH => C_SMP_PCP_PLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SMP_PCP_PLB_NUM_MASTERS,
C_SPLB_P2P => C_SMP_PCP_PLB_P2P
)
port map(
Bus2IP_Addr => Bus2SMP_PCP_Addr( C_SMP_PCP_PLB_AWIDTH-1 downto 0 ),
Bus2IP_BE => Bus2SMP_PCP_BE( (C_SMP_PCP_PLB_DWIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2SMP_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2SMP_PCP_Clk,
Bus2IP_Data => Bus2SMP_PCP_Data( C_SMP_PCP_PLB_DWIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2SMP_PCP_RNW,
Bus2IP_Reset => Bus2SMP_PCP_Reset,
IP2Bus_Data => SMP_PCP2Bus_Data( C_SMP_PCP_PLB_DWIDTH-1 downto 0 ),
IP2Bus_Error => SMP_PCP2Bus_Error,
IP2Bus_RdAck => SMP_PCP2Bus_RdAck,
IP2Bus_WrAck => SMP_PCP2Bus_WrAck,
PLB_ABus => SMP_PCP_ABus,
PLB_BE => SMP_PCP_BE( 0 to (C_SMP_PCP_PLB_DWIDTH/8)-1 ),
PLB_MSize => SMP_PCP_MSize,
PLB_PAValid => SMP_PCP_PAValid,
PLB_RNW => SMP_PCP_RNW,
PLB_SAValid => SMP_PCP_SAValid,
PLB_TAttribute => SMP_PCP_TAttribute,
PLB_UABus => SMP_PCP_UABus,
PLB_abort => SMP_PCP_abort,
PLB_busLock => SMP_PCP_busLock,
PLB_lockErr => SMP_PCP_lockErr,
PLB_masterID => SMP_PCP_masterID( 0 to C_SMP_PCP_PLB_MID_WIDTH-1 ),
PLB_rdBurst => SMP_PCP_rdBurst,
PLB_rdPendPri => SMP_PCP_rdPendPri,
PLB_rdPendReq => SMP_PCP_rdPendReq,
PLB_rdPrim => SMP_PCP_rdPrim,
PLB_reqPri => SMP_PCP_reqPri,
PLB_size => SMP_PCP_size,
PLB_type => SMP_PCP_type,
PLB_wrBurst => SMP_PCP_wrBurst,
PLB_wrDBus => SMP_PCP_wrDBus( 0 to C_SMP_PCP_PLB_DWIDTH-1 ),
PLB_wrPendPri => SMP_PCP_wrPendPri,
PLB_wrPendReq => SMP_PCP_wrPendReq,
PLB_wrPrim => SMP_PCP_wrPrim,
SPLB_Clk => SMP_PCP_Clk,
SPLB_Rst => SMP_PCP_Rst,
Sl_MBusy => SMP_PCP_MBusy( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MIRQ => SMP_PCP_MIRQ( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MRdErr => SMP_PCP_MRdErr( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_MWrErr => SMP_PCP_MWrErr( 0 to C_SMP_PCP_PLB_NUM_MASTERS-1 ),
Sl_SSize => SMP_PCP_SSize,
Sl_addrAck => SMP_PCP_addrAck,
Sl_rdBTerm => SMP_PCP_rdBTerm,
Sl_rdComp => SMP_PCP_rdComp,
Sl_rdDAck => SMP_PCP_rdDAck,
Sl_rdDBus => SMP_PCP_rdDBus( 0 to C_SMP_PCP_PLB_DWIDTH-1 ),
Sl_rdWdAddr => SMP_PCP_rdWdAddr,
Sl_rearbitrate => SMP_PCP_rearbitrate,
Sl_wait => SMP_PCP_wait,
Sl_wrBTerm => SMP_PCP_wrBTerm,
Sl_wrComp => SMP_PCP_wrComp,
Sl_wrDAck => SMP_PCP_wrDAck
);
end generate genSmpIo;
end struct;
| gpl-2.0 | 157853ea4bc168b94ae070627eef26e4 | 0.609239 | 2.979914 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/altaccumulate2_inst.vhd | 1 | 164 | altaccumulate2_inst : altaccumulate2 PORT MAP (
aclr => aclr_sig,
clken => clken_sig,
clock => clock_sig,
data => data_sig,
result => result_sig
);
| gpl-2.0 | 1e9dd37f2769f1013e03ffbef867332d | 0.621951 | 2.827586 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_source/usb_cmd_nano.vhd | 1 | 3,549 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_cmd_nano
-- Date:2015-02-14
-- Author: Gideon
-- Description: I/O registers for controlling commands directly, 16 bits for
-- attachment to nano cpu.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_cmd_pkg.all;
entity usb_cmd_nano is
port (
clock : in std_logic;
reset : in std_logic;
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
cmd_req : out t_usb_cmd_req;
cmd_resp : in t_usb_cmd_resp );
end entity;
architecture arch of usb_cmd_nano is
signal done_latch : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if cmd_resp.done = '1' then
cmd_req.request <= '0';
done_latch <= '1';
end if;
if io_write = '1' then
case io_addr is
when X"60" => -- command request
cmd_req.request <= '1';
done_latch <= '0';
cmd_req.togglebit <= io_wdata(11);
--cmd_req.do_split <= io_wdata(7);
cmd_req.do_data <= io_wdata(6);
cmd_req.command <= c_usb_commands_decoded(to_integer(unsigned(io_wdata(2 downto 0))));
when X"61" => -- data buffer control
cmd_req.buffer_index <= unsigned(io_wdata(15 downto 14));
cmd_req.no_data <= io_wdata(13);
cmd_req.data_length(9 downto 0) <= unsigned(io_wdata(9 downto 0));
when X"62" => -- device/endpoint
cmd_req.device_addr <= unsigned(io_wdata(14 downto 8));
cmd_req.endp_addr <= unsigned(io_wdata(3 downto 0));
when X"63" => -- split info
cmd_req.do_split <= io_wdata(15);
cmd_req.split_hub_addr <= unsigned(io_wdata(14 downto 8));
cmd_req.split_port_addr <= unsigned(io_wdata(3 downto 0));
cmd_req.split_sc <= io_wdata(7);
cmd_req.split_sp <= io_wdata(6);
cmd_req.split_et <= io_wdata(5 downto 4);
when others =>
null;
end case;
end if;
if reset='1' then
done_latch <= '0';
cmd_req.request <= '0';
end if;
end if;
end process;
process(io_read, io_addr, cmd_resp, done_latch)
begin
io_rdata <= (others => '0');
if io_read = '1' then
case io_addr is
when X"64" =>
io_rdata(15) <= done_latch;
io_rdata(14 downto 12) <= std_logic_vector(to_unsigned(t_usb_result'pos(cmd_resp.result), 3));
io_rdata(11) <= cmd_resp.togglebit;
io_rdata(10) <= cmd_resp.no_data;
io_rdata(9 downto 0) <= std_logic_vector(cmd_resp.data_length(9 downto 0));
when others =>
null;
end case;
end if;
end process;
end arch;
| gpl-3.0 | 0243106a87deab3ba1f8d3c9307c0d9e | 0.455621 | 3.90429 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_source/slot_to_io_bridge.vhd | 4 | 3,386 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2012 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Bus bridge between C64 Slot cycles and internal I/O bus.
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the bus-bridge between the C64 I/O
-- expansion and the internal I/O bus to the peripherals.
-- Due to the nature of the I/O bus, reads are not yet implemented.
-- In order to make this work an io_bus read shall be initiated
-- when a read takes place, but before the end of the C64 cycle.
-- The necessary signal is not defined yet in the slot_bus
-- definition.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
entity slot_to_io_bridge is
generic (
g_io_base : unsigned(19 downto 0);
g_slot_start : unsigned(8 downto 0);
g_slot_stop : unsigned(8 downto 0) );
port (
clock : in std_logic;
reset : in std_logic;
enable : in std_logic := '1';
irq_in : in std_logic := '0';
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
io_req : out t_io_req;
io_resp : in t_io_resp );
end entity;
architecture rtl of slot_to_io_bridge is
signal last_read : std_logic_vector(7 downto 0);
signal reg_output : std_logic;
begin
slot_resp.irq <= irq_in and enable;
slot_resp.data <= last_read when reg_output='1' else X"00";
process(clock)
variable addr : unsigned(8 downto 0);
begin
if rising_edge(clock) then
io_req <= c_io_req_init;
-- writes
addr := slot_req.io_address(8 downto 0);
if (addr >= g_slot_start) and (addr <= g_slot_stop) and (enable = '1') then
if slot_req.io_write='1' then
io_req.write <= '1';
io_req.address <= g_io_base + (addr - g_slot_start);
io_req.data <= slot_req.data;
end if;
end if;
-- reads
addr := slot_req.bus_address(8 downto 0);
if (addr >= g_slot_start) and (addr <= g_slot_stop) and (enable = '1') then
if slot_req.io_read_early='1' then
io_req.read <= '1';
io_req.address <= g_io_base + (addr - g_slot_start);
last_read <= X"AA";
end if;
end if;
if io_resp.ack = '1' then
last_read <= io_resp.data;
end if;
end if;
end process;
-- reads
reg_output <= enable when (slot_req.bus_address(8 downto 0) >= g_slot_start) and
(slot_req.bus_address(8 downto 0) <= g_slot_stop) else '0';
slot_resp.reg_output <= reg_output;
end architecture;
| gpl-3.0 | 26b6a40985fe23caa5ae0e9724acae9c | 0.462493 | 3.887486 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb2/vhdl_sim/usb_controller_tb.vhd | 5 | 3,711 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
--use work.tl_string_util_pkg.all;
entity usb_controller_tb is
end usb_controller_tb;
architecture tb of usb_controller_tb is
signal clock_50 : std_logic := '0';
signal clock_60 : std_logic := '0';
signal clock_50_shifted : std_logic := '1';
signal reset : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
-- ULPI Interface
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
-- LED interface
signal usb_busy : std_logic;
-- Memory interface
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp := c_mem_resp_init;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(14 downto 0);
signal SDRAM_D : std_logic_vector(7 downto 0) := (others => 'Z');
begin
clock_50 <= not clock_50 after 10 ns;
clock_60 <= not clock_60 after 8.3 ns;
reset <= '1', '0' after 100 ns;
i_io_bfm1: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock_50,
req => io_req,
resp => io_resp );
process
variable iom : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm", iom);
io_write(iom, X"1000", X"01"); -- enable core
wait;
end process;
i_phy: entity work.ulpi_phy_bfm
port map (
clock => clock_60,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
i_mut: entity work.usb_controller
port map (
ulpi_clock => clock_60,
ulpi_reset => reset,
-- ULPI Interface
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
-- LED interface
usb_busy => usb_busy,
-- register interface bus
sys_clock => clock_50,
sys_reset => reset,
sys_mem_req => mem_req,
sys_mem_resp=> mem_resp,
sys_io_req => io_req,
sys_io_resp => io_resp );
clock_50_shifted <= transport clock_50 after 15 ns; -- 270 deg
i_mc: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => true )
port map (
clock => clock_50,
clk_shifted => clock_50_shifted,
reset => reset,
inhibit => '0',
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
MEM_A => SDRAM_A,
MEM_D => SDRAM_D );
end architecture;
| gpl-3.0 | 4b32539a984c035370f8f5e6de40303d | 0.498518 | 3.426593 | false | false | false | false |
KB777/1541UltimateII | fpga/cart_slot/vhdl_source/slot_server_v4.vhd | 1 | 28,466 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.dma_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.cart_slot_pkg.all;
entity slot_server_v4 is
generic (
g_tag_slot : std_logic_vector(7 downto 0) := X"08";
g_tag_reu : std_logic_vector(7 downto 0) := X"10";
g_ram_base_reu : unsigned(27 downto 0) := X"1000000"; -- should be on 16M boundary, or should be limited in size
g_ram_base_cart : unsigned(27 downto 0) := X"0F70000"; -- should be on a 64K boundary
g_rom_base_cart : unsigned(27 downto 0) := X"0F80000"; -- should be on a 512K boundary
g_control_read : boolean := true;
g_command_intf : boolean := true;
g_ram_expansion : boolean := true;
g_extended_reu : boolean := false;
g_sampler : boolean := false;
g_implement_sid : boolean := true;
g_sid_voices : natural := 3;
g_vic_copper : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : inout std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
PHI2 : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
DMAn : out std_logic := '1';
BA : in std_logic := '0';
ROMLn : in std_logic;
ROMHn : in std_logic;
GAMEn : inout std_logic;
EXROMn : inout std_logic;
RWn : inout std_logic;
ADDRESS : inout std_logic_vector(15 downto 0);
DATA : inout std_logic_vector(7 downto 0);
-- other hardware pins
BUFFER_ENn : out std_logic;
buttons : in std_logic_vector(2 downto 0);
cart_led_n : out std_logic;
trigger_1 : out std_logic;
trigger_2 : out std_logic;
-- debug
freezer_state : out std_logic_vector(1 downto 0);
-- audio output
sid_pwm_left : out std_logic := '0';
sid_pwm_right : out std_logic := '0';
samp_pwm_left : out std_logic := '0';
samp_pwm_right : out std_logic := '0';
-- timing output
phi2_tick : out std_logic;
c64_stopped : out std_logic;
-- master on memory bus
memctrl_inhibit : out std_logic;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- slave on io bus
io_req : in t_io_req;
io_resp : out t_io_resp;
io_irq_cmd : out std_logic );
end slot_server_v4;
architecture structural of slot_server_v4 is
signal phi2_tick_i : std_logic;
signal phi2_recovered : std_logic;
signal vic_cycle : std_logic;
signal do_sample_addr : std_logic;
signal do_sample_io : std_logic;
signal do_io_event : std_logic;
signal do_probe_end : std_logic;
signal timing_inhibit : std_logic;
signal slave_dout : std_logic_vector(7 downto 0);
signal slave_dtri : std_logic := '0';
signal master_dout : std_logic_vector(7 downto 0);
signal master_dtri : std_logic := '0';
signal address_tri_l : std_logic;
signal address_tri_h : std_logic;
signal address_out : std_logic_vector(15 downto 0);
signal rwn_tri : std_logic;
signal rwn_out : std_logic;
signal control : t_cart_control;
signal status : t_cart_status;
signal allow_serve : std_logic;
-- interface with freezer (cartridge) logic
signal serve_enable : std_logic := '0'; -- from cartridge emulation logic
signal serve_vic : std_logic := '0';
signal serve_rom : std_logic := '0'; -- ROML or ROMH
signal serve_io1 : std_logic := '0'; -- IO1n
signal serve_io2 : std_logic := '0'; -- IO2n
signal allow_write : std_logic := '0';
-- kernal replacement logic
signal kernal_area : std_logic := '0';
signal kernal_probe : std_logic := '0';
signal kernal_addr_out : std_logic := '0';
signal force_ultimax : std_logic := '0';
signal cpu_write : std_logic;
signal epyx_timeout : std_logic;
signal reu_dma_n : std_logic := '1'; -- direct from REC
signal cmd_if_freeze : std_logic := '0'; -- same function as reu_dma_n, but then from CI
signal mask_buttons : std_logic := '0';
signal reset_button : std_logic;
signal freeze_button : std_logic;
signal actual_c64_reset : std_logic;
signal dma_n : std_logic := '1';
signal nmi_n : std_logic := '1';
signal irq_n : std_logic := '1';
signal exrom_n : std_logic := '1';
signal game_n : std_logic := '1';
signal irq_oc, nmi_oc, rst_oc, dma_oc, exrom_oc, game_oc : std_logic;
signal unfreeze : std_logic;
signal freeze_trig : std_logic;
signal freeze_act : std_logic;
signal io_req_dma : t_io_req;
signal io_resp_dma : t_io_resp := c_io_resp_init;
signal io_req_peri : t_io_req;
signal io_resp_peri : t_io_resp := c_io_resp_init;
signal io_req_sid : t_io_req;
signal io_resp_sid : t_io_resp := c_io_resp_init;
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_req_cmd : t_io_req;
signal io_resp_cmd : t_io_resp := c_io_resp_init;
signal io_req_copper : t_io_req;
signal io_resp_copper : t_io_resp := c_io_resp_init;
signal io_req_samp_cpu : t_io_req;
signal io_resp_samp_cpu : t_io_resp := c_io_resp_init;
signal dma_req_io : t_dma_req;
signal dma_resp_io : t_dma_resp := c_dma_resp_init;
signal dma_req_reu : t_dma_req;
signal dma_resp_reu : t_dma_resp := c_dma_resp_init;
signal dma_req_copper : t_dma_req;
signal dma_resp_copper : t_dma_resp := c_dma_resp_init;
signal dma_req : t_dma_req;
signal dma_resp : t_dma_resp := c_dma_resp_init;
signal slot_req : t_slot_req;
signal slot_resp : t_slot_resp := c_slot_resp_init;
signal slot_resp_reu : t_slot_resp := c_slot_resp_init;
signal slot_resp_cart : t_slot_resp := c_slot_resp_init;
signal slot_resp_sid : t_slot_resp := c_slot_resp_init;
signal slot_resp_cmd : t_slot_resp := c_slot_resp_init;
signal slot_resp_samp : t_slot_resp := c_slot_resp_init;
signal mem_req_slot : t_mem_req := c_mem_req_init;
signal mem_resp_slot : t_mem_resp := c_mem_resp_init;
signal mem_req_reu : t_mem_req := c_mem_req_init;
signal mem_resp_reu : t_mem_resp := c_mem_resp_init;
signal mem_req_samp : t_mem_req := c_mem_req_init;
signal mem_resp_samp : t_mem_resp := c_mem_resp_init;
-- signal mem_req_trace : t_mem_req;
-- signal mem_resp_trace : t_mem_resp;
signal mem_rack_slot : std_logic;
signal mem_dack_slot : std_logic;
signal sid_sample_left : signed(17 downto 0);
signal sid_sample_right : signed(17 downto 0);
signal sample_L : signed(17 downto 0);
signal sample_R : signed(17 downto 0);
signal phi2_tick_avail : std_logic;
signal stand_alone_tick : std_logic;
signal tick_div : integer range 0 to 63;
begin
reset_button <= buttons(0) when control.swap_buttons='0' else buttons(2);
freeze_button <= buttons(2) when control.swap_buttons='0' else buttons(0);
i_split_64K: entity work.io_bus_splitter
generic map (
g_range_lo => 16,
g_range_hi => 16,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_peri, -- 4040000
reqs(1) => io_req_dma, -- 4050000
resps(0) => io_resp_peri,
resps(1) => io_resp_dma );
i_bridge: entity work.io_to_dma_bridge
port map (
clock => clock,
reset => reset,
c64_stopped => status.c64_stopped,
io_req => io_req_dma,
io_resp => io_resp_dma,
dma_req => dma_req_io,
dma_resp => dma_resp_io );
i_split_8K: entity work.io_bus_splitter
generic map (
g_range_lo => 13,
g_range_hi => 15,
g_ports => 5 )
port map (
clock => clock,
req => io_req_peri,
resp => io_resp_peri,
reqs(0) => io_req_regs, -- 4040000
reqs(1) => io_req_sid, -- 4042000
reqs(2) => io_req_cmd, -- 4044000
reqs(3) => io_req_copper, -- 4046000
reqs(4) => io_req_samp_cpu, -- 4048000
resps(0) => io_resp_regs,
resps(1) => io_resp_sid,
resps(2) => io_resp_cmd,
resps(3) => io_resp_copper,
resps(4) => io_resp_samp_cpu );
i_registers: entity work.cart_slot_registers
generic map (
g_rom_base => g_rom_base_cart,
g_ram_base => g_ram_base_cart,
-- g_control_read => g_control_read,
g_ram_expansion => g_ram_expansion )
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control,
status => status );
i_timing: entity work.slot_timing
port map (
clock => clock,
reset => reset,
-- Cartridge pins
PHI2 => PHI2,
BA => BA,
serve_vic => serve_vic,
serve_enable => serve_enable,
serve_inhibit => status.c64_stopped,
allow_serve => allow_serve,
timing_addr => control.timing_addr_valid,
edge_recover => control.phi2_edge_recover,
phi2_tick => phi2_tick_i,
phi2_recovered => phi2_recovered,
clock_det => status.clock_detect,
vic_cycle => vic_cycle,
inhibit => timing_inhibit,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_probe_end => do_probe_end,
do_io_event => do_io_event );
mem_req_slot.tag <= g_tag_slot;
mem_rack_slot <= '1' when mem_resp_slot.rack_tag = g_tag_slot else '0';
mem_dack_slot <= '1' when mem_resp_slot.dack_tag = g_tag_slot else '0';
i_slave: entity work.slot_slave
port map (
clock => clock,
reset => reset,
-- Cartridge pins
RSTn => RSTn,
IO1n => IO1n,
IO2n => IO2n,
ROMLn => ROMLn,
ROMHn => ROMHn,
GAMEn => GAMEn,
EXROMn => EXROMn,
RWn => RWn,
BA => BA,
ADDRESS => ADDRESS,
DATA_in => DATA,
DATA_out => slave_dout,
DATA_tri => slave_dtri,
-- interface with memory controller
mem_req => mem_req_slot.request,
mem_rwn => mem_req_slot.read_writen,
mem_wdata => mem_req_slot.data,
mem_size => mem_req_slot.size,
mem_rack => mem_rack_slot,
mem_dack => mem_dack_slot,
mem_rdata => mem_resp_slot.data,
mem_count => mem_resp.count,
-- mem_addr comes from cartridge logic
-- synchronized outputs
reset_out => actual_c64_reset,
-- timing inputs
phi2_tick => phi2_tick_i,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_io_event => do_io_event,
do_probe_end => do_probe_end,
-- interface with freezer (cartridge) logic
allow_serve => allow_serve,
serve_rom => serve_rom, -- ROML or ROMH
serve_io1 => serve_io1, -- IO1n
serve_io2 => serve_io2, -- IO2n
allow_write => allow_write,
-- kernal emulation
kernal_enable => control.kernal_enable,
kernal_probe => kernal_probe,
kernal_area => kernal_area,
force_ultimax => force_ultimax,
cpu_write => cpu_write,
epyx_timeout => epyx_timeout,
slot_req => slot_req,
slot_resp => slot_resp,
-- interface with hardware
BUFFER_ENn => BUFFER_ENn );
i_master: entity work.slot_master_v4
port map (
clock => clock,
reset => reset,
-- Cartridge pins
DMAn => dma_n,
BA => BA,
RWn_in => RWn,
RWn_out => rwn_out,
RWn_tri => rwn_tri,
ADDRESS_out => address_out,
ADDRESS_tri_h => address_tri_h,
ADDRESS_tri_l => address_tri_l,
DATA_in => DATA,
DATA_out => master_dout,
DATA_tri => master_dtri,
-- timing inputs
vic_cycle => vic_cycle,
phi2_recovered => phi2_recovered,
phi2_tick => phi2_tick_i,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_io_event => do_io_event,
reu_dma_n => reu_dma_n,
cmd_if_freeze => cmd_if_freeze,
-- request from the cpu to do a cycle on the cart bus
dma_req => dma_req,
dma_resp => dma_resp,
-- system control
stop_cond => control.c64_stop_mode,
c64_stop => control.c64_stop,
c64_stopped => status.c64_stopped );
i_freeze: entity work.freezer
port map (
clock => clock,
reset => reset,
RST_in => reset_button,
button_freeze => freeze_button,
cpu_cycle_done => do_io_event,
cpu_write => cpu_write,
freezer_state => freezer_state,
unfreeze => unfreeze,
freeze_trig => freeze_trig,
freeze_act => freeze_act );
i_cart_logic: entity work.all_carts_v4
generic map (
g_rom_base => std_logic_vector(g_rom_base_cart),
g_ram_base => std_logic_vector(g_ram_base_cart) )
port map (
clock => clock,
reset => reset,
RST_in => reset_button,
c64_reset => control.c64_reset,
ethernet_enable => control.eth_enable,
freeze_trig => freeze_trig,
freeze_act => freeze_act,
unfreeze => unfreeze,
cart_active => status.cart_active,
cart_logic => control.cartridge_type,
cart_kill => control.cartridge_kill,
epyx_timeout => epyx_timeout,
slot_req => slot_req,
slot_resp => slot_resp_cart,
mem_addr => mem_req_slot.address,
serve_enable => serve_enable,
serve_vic => serve_vic,
serve_rom => serve_rom, -- ROML or ROMH
serve_io1 => serve_io1, -- IO1n
serve_io2 => serve_io2, -- IO2n
allow_write => allow_write,
kernal_area => kernal_area,
kernal_enable => control.kernal_enable,
irq_n => irq_n,
nmi_n => nmi_n,
exrom_n => exrom_n,
game_n => game_n,
CART_LEDn => cart_led_n );
r_sid: if g_implement_sid generate
begin
-- i_trce: entity work.sid_trace
-- generic map (
-- g_mem_tag => X"CE" )
-- port map (
-- clock => clock,
-- reset => actual_c64_reset,
--
-- addr => unsigned(slot_addr(6 downto 0)),
-- wren => sid_write,
-- wdata => io_wdata,
--
-- phi2_tick => phi2_tick_i,
--
-- io_req => io_req_trace,
-- io_resp => io_resp_trace,
--
-- mem_req => mem_req_trace,
-- mem_resp => mem_resp_trace );
i_sid: entity work.sid_peripheral
generic map (
g_num_voices => g_sid_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req_sid,
io_resp => io_resp_sid,
slot_req => slot_req,
slot_resp => slot_resp_sid,
start_iter => phi2_tick_avail,
sample_left => sid_sample_left,
sample_right => sid_sample_right );
i_pdm_sid_L: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => sid_sample_left'length )
port map (
clock => clock,
reset => reset,
dac_in => sid_sample_left,
dac_out => sid_pwm_left );
i_pdm_sid_R: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => sid_sample_right'length )
port map (
clock => clock,
reset => reset,
dac_in => sid_sample_right,
dac_out => sid_pwm_right );
end generate;
g_cmd: if g_command_intf generate
i_cmd: entity work.command_interface
port map (
clock => clock,
reset => reset,
-- C64 side interface
slot_req => slot_req,
slot_resp => slot_resp_cmd,
freeze => cmd_if_freeze,
-- io interface for local cpu
io_req => io_req_cmd, -- we get an 8K range
io_resp => io_resp_cmd,
io_irq => io_irq_cmd );
end generate;
g_reu: if g_ram_expansion generate
begin
i_reu: entity work.reu
generic map (
g_extended => g_extended_reu,
g_ram_base => g_ram_base_reu,
g_ram_tag => g_tag_reu )
port map (
clock => clock,
reset => actual_c64_reset,
-- register interface
slot_req => slot_req,
slot_resp => slot_resp_reu,
-- system interface
phi2_tick => do_io_event,
reu_dma_n => reu_dma_n,
size_ctrl => control.reu_size,
enable => control.reu_enable,
-- memory interface
mem_req => mem_req_reu,
mem_resp => mem_resp_reu,
dma_req => dma_req_reu,
dma_resp => dma_resp_reu );
end generate;
r_copper: if g_vic_copper generate
i_copper: entity work.copper
port map (
clock => clock,
reset => reset,
irq_n => IRQn,
phi2_tick => phi2_tick_i,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
io_req => io_req_copper,
io_resp => io_resp_copper,
dma_req => dma_req_copper,
dma_resp => dma_resp_copper,
slot_req => slot_req,
slot_resp => open ); -- never required, just snoop!
end generate;
r_sampler: if g_sampler generate
signal local_io_req : t_io_req := c_io_req_init;
signal local_io_resp : t_io_resp;
signal io_req_samp : t_io_req;
signal io_resp_samp : t_io_resp;
signal irq_samp : std_logic;
begin
i_io_bridge: entity work.slot_to_io_bridge
generic map (
g_io_base => X"48000", -- dont care in this context
g_slot_start => "100100000",
g_slot_stop => "111111111" )
port map (
clock => clock,
reset => reset,
enable => control.sampler_enable,
irq_in => irq_samp,
slot_req => slot_req,
slot_resp => slot_resp_samp,
io_req => local_io_req,
io_resp => local_io_resp );
i_io_arb_sampler: entity work.io_bus_arbiter_pri
generic map (
g_ports => 2 )
port map (
clock => clock,
reset => reset,
reqs(0) => io_req_samp_cpu,
reqs(1) => local_io_req,
resps(0) => io_resp_samp_cpu,
resps(1) => local_io_resp,
req => io_req_samp,
resp => io_resp_samp );
i_sampler: entity work.sampler
generic map (
g_num_voices => 8 )
port map (
clock => clock,
reset => actual_c64_reset,
io_req => io_req_samp,
io_resp => io_resp_samp,
mem_req => mem_req_samp,
mem_resp => mem_resp_samp,
irq => irq_samp,
sample_L => sample_L,
sample_R => sample_R,
new_sample => open );
i_pdm_samp_L: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => 18 )
port map (
clock => clock,
reset => reset,
dac_in => sample_L,
dac_out => samp_pwm_left );
i_pdm_samp_R: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => 18 )
port map (
clock => clock,
reset => reset,
dac_in => sample_R,
dac_out => samp_pwm_right );
end generate;
slot_resp <= or_reduce(slot_resp_reu & slot_resp_cart & slot_resp_sid & slot_resp_cmd & slot_resp_samp);
p_probe_address_delay: process(clock)
variable kernal_probe_d : std_logic_vector(2 downto 0) := (others => '0');
begin
if rising_edge(clock) then
kernal_addr_out <= kernal_probe_d(0);
kernal_probe_d := kernal_probe & kernal_probe_d(kernal_probe_d'high downto 1);
end if;
end process;
ADDRESS(7 downto 0) <= address_out(7 downto 0) when address_tri_l='1' else (others => 'Z');
ADDRESS(12 downto 8) <= address_out(12 downto 8) when address_tri_h='1' else (others => 'Z');
ADDRESS(15 downto 13) <= "101" when (kernal_addr_out='1' and kernal_probe='1') else
address_out(15 downto 13) when address_tri_h='1' else (others => 'Z');
RWn <= rwn_out when rwn_tri='1' else 'Z';
DATA <= slave_dout when (slave_dtri='1') else
master_dout when (master_dtri='1') else (others => 'Z');
-- open drain outputs
irq_oc <= '0' when irq_n='0' or slot_resp.irq='1' else '1';
nmi_oc <= '0' when (control.c64_nmi='1') or (nmi_n='0') else '1';
rst_oc <= '0' when (reset_button='1' and status.c64_stopped='0' and mask_buttons='0') or
(control.c64_reset='1') else '1';
dma_oc <= '0' when (dma_n='0' or kernal_probe='1') else '1';
-- dma_oc <= '0' when (dma_n='0') else '1';
process(control, serve_enable, exrom_n, game_n, force_ultimax, kernal_probe)
begin
exrom_oc <= '1';
game_oc <= '1';
if (force_ultimax = '1') or (control.c64_ultimax = '1') then
game_oc <= '0';
elsif kernal_probe = '1' then
game_oc <= '0';
exrom_oc <= '0';
else
if (serve_enable='1' and exrom_n='0') then
exrom_oc <= '0';
end if;
if (serve_enable='1' and game_n='0') then
game_oc <= '0';
end if;
end if;
end process;
irq_push: entity work.oc_pusher port map(clock => clock, sig_in => irq_oc, oc_out => IRQn);
nmi_push: entity work.oc_pusher port map(clock => clock, sig_in => nmi_oc, oc_out => NMIn);
rst_push: entity work.oc_pusher port map(clock => clock, sig_in => rst_oc, oc_out => RSTn);
dma_push: entity work.oc_pusher port map(clock => clock, sig_in => dma_oc, oc_out => DMAn);
exr_push: entity work.oc_pusher port map(clock => clock, sig_in => exrom_oc, oc_out => EXROMn);
gam_push: entity work.oc_pusher port map(clock => clock, sig_in => game_oc, oc_out => GAMEn);
-- arbitration
i_dma_arb: entity work.dma_bus_arbiter_pri
generic map (
g_ports => 3 )
port map (
clock => clock,
reset => reset,
reqs(0) => dma_req_io,
reqs(1) => dma_req_reu,
reqs(2) => dma_req_copper,
resps(0) => dma_resp_io,
resps(1) => dma_resp_reu,
resps(2) => dma_resp_copper,
req => dma_req,
resp => dma_resp );
i_mem_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 3 )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_slot,
reqs(1) => mem_req_reu,
reqs(2) => mem_req_samp,
-- reqs(3) => mem_req_trace,
resps(0) => mem_resp_slot,
resps(1) => mem_resp_reu,
resps(2) => mem_resp_samp,
-- resps(3) => mem_resp_trace,
req => mem_req,
resp => mem_resp );
-- Delay the inhibit one clock cycle, because our
-- arbiter introduces one clock cycle delay as well.
process(clock)
begin
if rising_edge(clock) then
memctrl_inhibit <= timing_inhibit;
end if;
end process;
-- Stand alone tick output
process(clock)
begin
if rising_edge(clock) then
stand_alone_tick <= '0';
if tick_div = 0 then
stand_alone_tick <= '1';
if control.tick_ntsc = '1' then
tick_div <= 48; -- 49 => 1.0204 MHz (-0.15%)
else
tick_div <= 50; -- 51 => 0.9804 MHz (-0.49%)
end if;
else
tick_div <= tick_div - 1;
end if;
end if;
end process;
phi2_tick_avail <= stand_alone_tick when status.clock_detect = '0' else phi2_tick_i;
phi2_tick <= phi2_tick_avail;
c64_stopped <= status.c64_stopped;
end structural;
| gpl-3.0 | 708e54357ccfb5bf0d2da11194ec4ba3 | 0.46329 | 3.523456 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op2.vhdl | 1 | 11,378 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7.6e-06,
W => Wdiff_0,
Wdiff_0init => 6.8e-06,
scope => private
)
port map(
D => net1,
G => in1,
S => net7
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7.6e-06,
W => Wdiff_0,
Wdiff_0init => 6.8e-06,
scope => private
)
port map(
D => net2,
G => in2,
S => net7
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.05e-06,
W => W_0,
W_0init => 6.79e-05
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7.6e-06,
W => Wdiff_0,
Wdiff_0init => 6.8e-06,
scope => private
)
port map(
D => net8,
G => in1,
S => net7
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7.6e-06,
W => Wdiff_0,
Wdiff_0init => 6.8e-06,
scope => private
)
port map(
D => net8,
G => in2,
S => net7
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.05e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.5e-06,
scope => private
)
port map(
D => net8,
G => net8,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.05e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.5e-06,
scope => private
)
port map(
D => net8,
G => net8,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.05e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.5e-06,
scope => private
)
port map(
D => net1,
G => net8,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.05e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.5e-06,
scope => private
)
port map(
D => net2,
G => net8,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => L_2,
L_2init => 6.15e-06,
W => Wsrc_1,
Wsrc_1init => 7.57e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => L_3,
L_3init => 3.5e-06,
W => Wsrc_1,
Wsrc_1init => 7.57e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8.5e-07,
W => Wcm_2,
Wcm_2init => 1.925e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8.5e-07,
W => Wcmcout_2,
Wcmcout_2init => 6.135e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => C_4,
symmetry_scope => sym_4
)
port map(
P => net5,
N => net3
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8.5e-07,
W => Wcm_2,
Wcm_2init => 1.925e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8.5e-07,
W => Wcmcout_2,
Wcmcout_2init => 6.135e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net6,
G => net4,
S => gnd
);
subnet0_subnet4_c1 : entity cap(behave)
generic map(
C => C_5,
symmetry_scope => sym_4
)
port map(
P => net6,
N => net4
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 4e-07,
W => Wcm_3,
Wcm_3init => 1.49e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 4e-07,
W => Wcmout_3,
Wcmout_3init => 7.05e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet0_subnet6_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 4e-07,
W => Wcm_3,
Wcm_3init => 1.49e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet6_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 4e-07,
W => Wcmout_3,
Wcmout_3init => 7.05e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out2,
G => net6,
S => vdd
);
subnet0_subnet7_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.05e-06,
W => Wcursrc_4,
Wcursrc_4init => 3.35e-06,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet8_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.05e-06,
W => Wcursrc_4,
Wcursrc_4init => 3.35e-06,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net9,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net9,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net12,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net11,
N => net9
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7.05e-06,
W => W_1,
W_1init => 3.585e-05
)
port map(
D => net10,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 4.95e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 6.32e-05,
scope => private
)
port map(
D => net12,
G => vref,
S => net10
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 4.95e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 6.32e-05,
scope => private
)
port map(
D => net11,
G => net9,
S => net10
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 8.5e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 2.15e-06,
scope => private
)
port map(
D => net11,
G => net11,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 8.5e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 2.15e-06,
scope => private
)
port map(
D => net12,
G => net11,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 1.5e-06,
W => Wcmbias_0,
Wcmbias_0init => 3.345e-05,
scope => private
)
port map(
D => out1,
G => net12,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 1.5e-06,
W => Wcmbias_0,
Wcmbias_0init => 3.345e-05,
scope => private
)
port map(
D => out2,
G => net12,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7.05e-06,
W => (pfak)*(WBias),
WBiasinit => 2.83e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7.05e-06,
W => (pfak)*(WBias),
WBiasinit => 2.83e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7.05e-06,
W => WBias,
WBiasinit => 2.83e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.05e-06,
W => WBias,
WBiasinit => 2.83e-05
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.05e-06,
W => WBias,
WBiasinit => 2.83e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.05e-06,
W => WBias,
WBiasinit => 2.83e-05
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 84521742ec2b4f8e94885046ef532362 | 0.564423 | 2.78463 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/clocks/simulation/timing/clocks_tb.vhd | 1 | 6,295 | -- file: clocks_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clocks_tb is
end clocks_tb;
architecture test of clocks_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.250 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(4 downto 1);
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(4 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clocks_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(4 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(4 downto 1)
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clocks_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
| mit | f98535561d9ef9d27170ba2639b97d4e | 0.644003 | 4.264905 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DPR_Altera_qsys.vhd | 2 | 9,499 | ------------------------------------------------------------------------------------------------------------------------
-- OpenMAC - DPR for Altera FPGA
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted to official version.
-- 2010-05-03 V0.02 added packet buffer dpr
-- 2011-12-22 V0.03 added initialization files
-- removed dpr_8_8
-- 2012-01-04 V0.04 replaced initialization files with mif
-- 2012-02-21 V0.05 replaced initialization files to support ip-core repos
------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- 16 / 16 DPR
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity Dpr_16_16 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA, WeB : in std_logic := '0';
EnA, EnB : in std_logic := '1';
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
DoA : out std_logic_vector(15 downto 0);
BeB : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 7 downto 0);
DiB : in std_logic_vector (15 downto 0) := (others => '0');
DoB : out std_logic_vector(15 downto 0)
);
end Dpr_16_16;
architecture struct of Dpr_16_16 is
begin
Ram: COMPONENT altsyncram
GENERIC MAP ( OPERATION_MODE => "BIDIR_DUAL_PORT", INIT_FILE => "dpr_16_16.mif",
WIDTH_A => 16, WIDTHAD_A => 8, NUMWORDS_A => 256, WIDTH_BYTEENA_A => 2,
WIDTH_B => 16, WIDTHAD_B => 8, NUMWORDS_B => 256, WIDTH_BYTEENA_B => 2
)
PORT MAP(
clock0 => ClkA, clock1 => ClkB,
wren_a => WeA, wren_b => WeB,
clocken0 => EnA, clocken1 => EnB,
byteena_a => BeA, byteena_b => BeB,
address_a => AddrA, address_b => AddrB,
data_a => DiA, data_b => DiB,
q_a => DoA, q_b => DoB
);
end struct;
-------------------------------------------------------------------------------
-- 16 / 32 DPR
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity Dpr_16_32 is
generic(Simulate : in boolean);
port (
ClkA, ClkB : in std_logic;
WeA : in std_logic := '0';
EnA, EnB : in std_logic := '1';
AddrA : in std_logic_vector ( 7 downto 0);
DiA : in std_logic_vector (15 downto 0) := (others => '0');
BeA : in std_logic_vector ( 1 downto 0) := "11";
AddrB : in std_logic_vector ( 6 downto 0);
DoB : out std_logic_vector(31 downto 0)
);
end Dpr_16_32;
architecture struct of Dpr_16_32 is
begin
Ram: COMPONENT altsyncram
GENERIC MAP ( OPERATION_MODE => "DUAL_PORT", INIT_FILE => "dpr_16_32.mif",
WIDTH_A => 16, WIDTHAD_A => 8, NUMWORDS_A => 256, WIDTH_BYTEENA_A => 2,
WIDTH_B => 32, WIDTHAD_B => 7, NUMWORDS_B => 128
)
PORT MAP(
clock0 => ClkA, clock1 => ClkB,
wren_a => WeA,
clocken0 => EnA, clocken1 => EnB,
byteena_a => BeA,
address_a => AddrA, address_b => AddrB,
data_a => DiA,
q_b => DoB
);
end struct;
-------------------------------------------------------------------------------
-- Packet buffer
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
USE ieee.math_real.log2;
USE ieee.math_real.ceil;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY OpenMAC_DPRpackets IS
GENERIC
(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
rden_a : IN STD_LOGIC := '1';
rden_b : IN STD_LOGIC := '1';
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END OpenMAC_DPRpackets;
ARCHITECTURE SYN OF openmac_dprpackets IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_reg_b : STRING;
byteena_reg_b : STRING;
byte_size : NATURAL;
clock_enable_input_a : STRING;
clock_enable_input_b : STRING;
clock_enable_output_a : STRING;
clock_enable_output_b : STRING;
indata_reg_b : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
numwords_b : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_aclr_b : STRING;
outdata_reg_a : STRING;
outdata_reg_b : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
read_during_write_mode_port_b : STRING;
widthad_a : NATURAL;
widthad_b : NATURAL;
width_a : NATURAL;
width_b : NATURAL;
width_byteena_a : NATURAL;
width_byteena_b : NATURAL;
wrcontrol_wraddress_reg_b : STRING
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
wren_b : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
address_a : IN STD_LOGIC_VECTOR (memSizeLOG2_g-2 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (memSizeLOG2_g-3 DOWNTO 0);
rden_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rden_b : IN STD_LOGIC ;
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q_a <= sub_wire0(15 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK1",
byteena_reg_b => "CLOCK1",
byte_size => 8,
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK1",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => memSize_g/2,
numwords_b => memSize_g/4,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "NONE",
outdata_aclr_b => "NONE",
outdata_reg_a => "CLOCK0",
outdata_reg_b => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => memSizeLOG2_g-1,
widthad_b => memSizeLOG2_g-2,
width_a => 16,
width_b => 32,
width_byteena_a => 2,
width_byteena_b => 4,
wrcontrol_wraddress_reg_b => "CLOCK1"
)
PORT MAP (
wren_a => wren_a,
clock0 => clock_a,
wren_b => wren_b,
clock1 => clock_b,
byteena_a => byteena_a,
byteena_b => byteena_b,
address_a => address_a,
address_b => address_b,
rden_a => rden_a,
rden_b => rden_b,
data_a => data_a,
data_b => data_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
| gpl-2.0 | 7dc2848c3f0582cc7d3a29c5468e1392 | 0.583114 | 3.044551 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op972_1.vhdl | 1 | 4,599 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net4,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net3,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias4,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | e634cf2e602fd233b51c75c8db3b4cc7 | 0.582301 | 3.213836 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_source/proc_core.vhd | 2 | 7,157 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
entity proc_core is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF";
support_bcd : boolean := true );
port(
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
irq_n : in std_logic := '1';
nmi_n : in std_logic := '1';
so_n : in std_logic := '1';
sync_out : out std_logic;
pc_out : out std_logic_vector(15 downto 0);
addr_out : out std_logic_vector(16 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
read_write_n : out std_logic );
end proc_core;
architecture structural of proc_core is
signal index_carry : std_logic;
signal pc_carry : std_logic;
signal branch_taken : boolean;
signal i_reg : std_logic_vector(7 downto 0);
signal d_reg : std_logic_vector(7 downto 0);
signal a_reg : std_logic_vector(7 downto 0);
signal x_reg : std_logic_vector(7 downto 0);
signal y_reg : std_logic_vector(7 downto 0);
signal s_reg : std_logic_vector(7 downto 0);
signal p_reg : std_logic_vector(7 downto 0);
signal latch_dreg : std_logic;
signal reg_update : std_logic;
signal copy_d2p : std_logic;
signal sync : std_logic;
signal rwn : std_logic;
signal vect_bit : std_logic;
signal a_mux : t_amux;
signal pc_oper : t_pc_oper;
signal s_oper : t_sp_oper;
signal adl_oper : t_adl_oper;
signal adh_oper : t_adh_oper;
signal dout_mux : t_dout_mux;
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal vect_addr : std_logic_vector(3 downto 0);
signal interrupt : std_logic;
signal new_flags : std_logic_vector(7 downto 0);
signal n_out : std_logic;
signal v_out : std_logic;
signal c_out : std_logic;
signal z_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal set_b : std_logic;
signal clear_b : std_logic;
signal a16 : std_logic;
begin
new_flags(7) <= n_out;
new_flags(6) <= v_out;
new_flags(5) <= '1';
new_flags(4) <= p_reg(4);
new_flags(3) <= d_out;
new_flags(2) <= i_out;
new_flags(1) <= z_out;
new_flags(0) <= c_out;
ctrl: entity work.proc_control
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
interrupt => interrupt,
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
sync => sync,
latch_dreg => latch_dreg,
reg_update => reg_update,
set_b => set_b,
copy_d2p => copy_d2p,
vect_bit => vect_bit,
a16 => a16,
rwn => rwn,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper );
oper: entity work.data_oper
generic map (
support_bcd => support_bcd )
port map (
inst => i_reg,
n_in => p_reg(7),
v_in => p_reg(6),
z_in => p_reg(1),
c_in => p_reg(0),
d_in => p_reg(3),
i_in => p_reg(2),
data_in => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
regs: entity work.proc_registers
generic map (
vector_page => vector_page )
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- package pins
data_in => data_in,
data_out => data_out,
so_n => so_n,
-- data from "data_oper"
alu_data => alu_out,
mem_data => mem_out,
new_flags => new_flags,
-- from implied handler
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
set_data => impl_out,
-- from interrupt controller
vect_addr => vect_addr,
interrupt => interrupt,
set_b => set_b,
clear_b => clear_b,
-- from processor state machine and decoder
sync => sync,
latch_dreg => latch_dreg,
vect_bit => vect_bit,
reg_update => reg_update,
copy_d2p => copy_d2p,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper,
-- outputs to processor state machine
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
-- register outputs
addr_out => addr_out(15 downto 0),
d_reg => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
p_reg => p_reg,
pc_out => pc_out );
intr: entity work.proc_interrupt
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
i_flag => p_reg(2),
clear_b => clear_b,
vect_bit => vect_bit,
interrupt => interrupt,
vect_addr => vect_addr );
read_write_n <= rwn;
addr_out(16) <= a16;
sync_out <= sync;
end structural;
| gpl-3.0 | 4eaecf697bbf86cccf290ab3af55d437 | 0.428951 | 3.503182 | false | false | false | false |
KB777/1541UltimateII | target/simulation/packages/vhdl_source/tl_math_pkg.vhd | 5 | 12,297 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Miscelaneous mathematic operations
-------------------------------------------------------------------------------
-- Description: This file contains math functions
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tl_math_pkg is
---------------------------------------------------------------------------
-- increment/decrement functions
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- wrapping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that wraps when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector;
function incr(old_value: unsigned; increment: natural := 1) return unsigned;
function incr(old_value: signed; increment: natural := 1) return signed;
function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector;
function decr(old_value: unsigned; decrement: natural := 1) return unsigned;
function decr(old_value: signed; decrement: natural := 1) return signed;
---------------------------------------------------------------------------
-- clipping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that clips when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector;
function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned;
function incr_clip(old_value: signed; increment: natural := 1) return signed;
function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector;
function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned;
function decr_clip(old_value: signed; decrement: natural := 1) return signed;
---------------------------------------------------------------------------
-- log functions
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- log2
---------------------------------------------------------------------------
-- Description: This functions returns the log2 value of a number. The
-- result is in the natural range and rounded depended on the
-- selected mode.
-- NOTE: use an argument of type unsigned when using this function for
-- synthesis
---------------------------------------------------------------------------
type log2mode is (ceil, floor);
function log2(arg: integer) return natural;
function log2(arg: integer; mode: log2mode) return natural;
function log2_floor(arg: integer) return natural;
function log2_ceil(arg: integer) return natural;
function log2(arg: unsigned) return natural;
function log2(arg: unsigned; mode: log2mode) return natural;
function log2_floor(arg: unsigned) return natural;
function log2_ceil(arg: unsigned) return natural;
---------------------------------------------------------------------------
-- min/max
---------------------------------------------------------------------------
-- Description: These functions return the minimum/maximum of two values
---------------------------------------------------------------------------
function max(a, b: integer) return integer;
function max(a, b: unsigned) return unsigned;
function min(a, b: integer) return integer;
function min(a, b: unsigned) return unsigned;
end tl_math_pkg;
library work;
use work.tl_vector_pkg.all;
package body tl_math_pkg is
---------------------------------------------------------------------------
-- increment/decrement functions
---------------------------------------------------------------------------
function incr(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is
begin
return std_logic_vector(incr(unsigned(old_value), increment));
end function;
function incr(old_value: unsigned; increment: natural := 1) return unsigned is
variable v_result : unsigned(old_value'range);
begin
v_result := (old_value + increment) mod 2**old_value'length;
return v_result;
end function;
function incr(old_value: signed; increment: natural := 1) return signed is
begin
return signed(incr(unsigned(old_value), increment));
end function;
function decr(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is
begin
return std_logic_vector(decr(unsigned(old_value), decrement));
end function;
function decr(old_value: unsigned; decrement: natural := 1) return unsigned is
constant c_norm_decrement : integer := decrement mod 2**old_value'length;
variable v_result : unsigned(old_value'range);
begin
v_result := (2**old_value'length + (old_value - c_norm_decrement)) mod 2**old_value'length;
return v_result;
end function;
function decr(old_value: signed; decrement: natural := 1) return signed is
begin
return signed(decr(unsigned(old_value), decrement));
end function;
---------------------------------------------------------------------------
-- clipping decrement/increment
---------------------------------------------------------------------------
-- Description: These functions give an increment/decrement that clips when
-- the maximal vector range is reached.
---------------------------------------------------------------------------
function incr_clip(old_value: std_logic_vector; increment: natural := 1) return std_logic_vector is
begin
return std_logic_vector(incr_clip(unsigned(old_value), increment));
end function;
function incr_clip(old_value: unsigned; increment: natural := 1) return unsigned is
constant c_max_value : unsigned(old_value'range) := (others => '1');
variable v_result : unsigned(old_value'range);
begin
assert increment < 2**old_value'length report "ERROR: Increment value is larger than vector range" severity error;
if old_value <= (c_max_value - increment) then
v_result := old_value + increment;
else
v_result := c_max_value;
end if;
return v_result;
end function;
function incr_clip(old_value: signed; increment: natural := 1) return signed is
variable c_max_value : signed(old_value'range) := to_signed(2**old_value'length / 2 - 1, old_value'length);
variable v_result : signed(old_value'range);
begin
if old_value <= (c_max_value - increment) then
v_result := old_value + increment;
else
v_result := c_max_value;
end if;
return v_result;
end function;
function decr_clip(old_value: std_logic_vector; decrement: natural := 1) return std_logic_vector is
begin
return std_logic_vector(decr_clip(unsigned(old_value), decrement));
end function;
function decr_clip(old_value: unsigned; decrement: natural := 1) return unsigned is
constant c_min_value : unsigned(old_value'range) := (others => '0');
variable v_result : unsigned(old_value'range);
begin
if old_value >= (c_min_value + decrement) then
v_result := old_value - decrement;
else
v_result := c_min_value;
end if;
return v_result;
end function;
function decr_clip(old_value: signed; decrement: natural := 1) return signed is
constant c_min_value : signed(old_value'range) := to_signed(2**old_value'length / 2, old_value'length);
variable v_result : signed(old_value'range);
begin
if old_value >= (c_min_value + decrement) then
v_result := old_value - decrement;
else
v_result := c_min_value;
end if;
return v_result;
end function;
---------------------------------------------------------------------------
-- log functions
---------------------------------------------------------------------------
function log2(arg: integer) return natural is
begin
return log2_ceil(arg);
end function;
function log2(arg: integer; mode: log2mode) return natural is
begin
if mode = floor then
return log2_floor(arg);
else
return log2_ceil(arg);
end if;
end;
function log2_ceil(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := log2_floor(arg);
if 2**v_result < arg then
return v_result + 1;
else
return v_result;
end if;
end function;
function log2_floor(arg: integer) return natural is
variable v_temp : integer;
variable v_result : natural;
begin
v_result := 0;
v_temp := arg / 2;
while v_temp /= 0 loop
v_temp := v_temp / 2;
v_result := v_result + 1;
end loop;
return v_result;
end function;
function log2(arg: unsigned) return natural is
begin
return log2_ceil(arg);
end function;
function log2(arg: unsigned; mode: log2mode) return natural is
begin
if mode = ceil then
return log2_ceil(arg);
else
return log2_floor(arg);
end if;
end function;
function log2_floor(arg: unsigned) return natural is
alias w : unsigned(arg'length - 1 downto 0) is arg;
begin
return highest_bit(w);
end function;
function log2_ceil(arg: unsigned) return natural is
alias w : unsigned(arg'length - 1 downto 0) is arg;
begin
if ones(arg) > 1 then
return highest_bit(w) + 1;
else
return highest_bit(w);
end if;
end function;
---------------------------------------------------------------------------
-- min/max
---------------------------------------------------------------------------
-- Description: These functions return the minimum/maximum of two values
---------------------------------------------------------------------------
function max(a, b: integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function max(a, b: unsigned) return unsigned is
begin
if a > b then
return a;
else
return b;
end if;
end function;
function min(a, b: integer) return integer is
begin
if a < b then
return a;
else
return b;
end if;
end function;
function min(a, b: unsigned) return unsigned is
begin
if a < b then
return a;
else
return b;
end if;
end function;
end tl_math_pkg;
| gpl-3.0 | 1dd8e7848596a20605dc424ba574b833 | 0.484264 | 5.04182 | false | false | false | false |
KB777/1541UltimateII | fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_1541_700a.vhd | 1 | 9,853 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_1541_700a is
generic (
g_version : unsigned(7 downto 0) := X"F9" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate_1541_700a;
architecture structural of ultimate_1541_700a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => false,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => true,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => false,
g_usb_host => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => true,
g_analyzer => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4b
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
| gpl-3.0 | 79a53ccb69c76df99e1bcb5e54cccd25 | 0.476606 | 3.377785 | false | false | false | false |
KB777/1541UltimateII | fpga/ip/synchroniser/vhdl_source/level_synchronizer.vhd | 1 | 2,736 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2008, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Level synchronizer block
-------------------------------------------------------------------------------
-- Description: The level synchronizer block synchronizes an asynchronous
-- input to the clock of the receiving module. Two flip-flops are
-- used to avoid metastability of the synchronized signal.
--
-- Please read Ran Ginosars paper "Fourteen ways to fool your
-- synchronizer" before considering modifications to this module!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity level_synchronizer is
generic (
g_reset_val : std_logic := '0'
);
port (
-- Clock signal
clock : in std_logic;
-- Asynchronous input
reset : in std_logic;
-- Asynchronous input
input : in std_logic;
-- Synchronized input
input_c : out std_logic
);
---------------------------------------------------------------------------
-- Synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of level_synchronizer : entity is "no";
attribute register_balancing : string;
attribute register_balancing of level_synchronizer : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of level_synchronizer : entity is true;
attribute dont_retime : boolean;
attribute dont_retime of level_synchronizer : entity is true;
---------------------------------------------------------------------------
end level_synchronizer;
architecture rtl of level_synchronizer is
signal sync1 : std_logic;
signal sync2 : std_logic;
begin
p_input_synchronization : process(clock)
begin
if rising_edge(clock) then
sync1 <= input;
sync2 <= sync1;
if reset = '1' then
sync1 <= g_reset_val;
sync2 <= g_reset_val;
end if;
end if;
end process;
input_c <= sync2;
end rtl;
| gpl-3.0 | 476ca1990a79f10d945682dbe3f6ab72 | 0.442982 | 5.676349 | false | false | false | false |
nick1au/Home-Sec-SYS | JamesBond.vhd | 1 | 532 | Library ieee;
Use ieee.std_logic_1164.all;
Entity JamesBond is
port( Go, clock: in std_logic;
Digit: in std_logic_vector(2 downto 0);
GetCode: out std_logic);
End Entity JamesBond;
Architecture goldeneye of JamesBond is
signal Q1, Q2, Q3: std_logic_vector(2 downto 0);
begin
Q1 <= Digit when Rising_edge(clock) AND Go = '1';
Q2 <= Q1 when Rising_edge(clock) AND Go = '1';
Q3 <= Q2 when Rising_edge(clock) AND Go = '1';
GetCode <= '1' when digit = "111" AND Q1 = "000" AND Q2 = "000" and go = '1' else '0';
End goldeneye;
| gpl-3.0 | d85a7a83fc6def314c288d9f7f548116 | 0.672932 | 2.607843 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/KeypointReader.vhd | 1 | 4,720 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_5vbn0d
-- /___/ /\ Timestamp : 04/06/2014 00:33:22
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity KeypointReader is
port ( addr : in std_logic_vector (31 downto 0);
enableIn : in std_logic;
clk : in std_logic;
memData : in std_logic_vector (31 downto 0);
request : in std_logic;
rst : in std_logic;
busy : out std_logic;
kptCoordX : out std_logic_vector (KPT_COORD_BW-1 downto 0);--keypoint's column possition
kptCoordY : out std_logic_vector (KPT_COORD_BW-1 downto 0);--keypoint's row possition
kptScale : out std_logic_vector(KPT_SCALE_BW-1 downto 0);
kptOctave : out std_logic_vector(KPT_OCTAVE_BW-1 downto 0);
memAddr : out std_logic_vector (31 downto 0);
read_mem : out std_logic
);
end KeypointReader;
architecture BEHAVIORAL of KeypointReader is
signal addrAux: std_logic_vector(31 downto 0) := (others => '0');
signal enableAux: std_logic := '0';
type reading_mem_states is (INIT, READING, READY);
signal s_readingMemState: reading_mem_states;
type producer_FSM_states is (INIT, REQ);
signal s_producerState: producer_FSM_states;
--signal s_memData: std_logic_vector (31 downto 0);
signal s_offset: natural range 0 to integer'HIGH;
begin
producer_proc: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_producerState <= INIT;
busy <= '0';
else
case s_producerState is
when INIT =>
if request = '1' then
busy <= '1';
s_producerState <= REQ;
end if;
when REQ =>
if s_readingMemState = READY then
busy <= '0';
s_producerState <= INIT;
end if;
end case;
end if;
end if;
end process;
load_kpt_data: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
addrAux <= (others => '0');
elsif enableIn = '1' then
addrAux <= addr;
enableAux <= enableIn;
end if;
end if;
end process;
read_keypoints: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_readingMemState <= INIT;
kptCoordX <= (others => '0');
kptCoordY <= (others => '0');
memAddr <= (others => '0');
s_offset <= 0;
read_mem <= '0';
else
if enableAux = '1' AND s_producerState = REQ then
case s_readingMemState is
when INIT =>
memAddr <= std_logic_vector(resize(unsigned(addrAux) + s_offset,32));
read_mem <= '1';
s_offset <= s_offset + 4;
s_readingMemState <= READING;
when READING =>
read_mem <= '0';
s_readingMemState <= READY;
when READY =>
kptCoordX <= memData(KPT_COORD_BW-1 downto 0);--9 a 0
kptCoordY <= memData(2*KPT_COORD_BW-1 downto KPT_COORD_BW);--19 a 10
kptScale <= memData((2*KPT_COORD_BW+KPT_SCALE_BW)-1 downto 2*KPT_COORD_BW);--25 a 20
kptOctave <= memData((2*KPT_COORD_BW+KPT_SCALE_BW+KPT_OCTAVE_BW)-1 downto (2*KPT_COORD_BW+KPT_SCALE_BW));
s_readingMemState <= INIT;
end case;
end if;
end if;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | 3046e1e846b1ed35789a0e527f65c86b | 0.574576 | 3.376252 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cpu_unit/vhdl_source/dm_cache.vhd | 5 | 17,774 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity dm_cache is
port (
clock : in std_logic;
reset : in std_logic;
client_req : in t_mem_req;
client_resp : out t_mem_resp;
mem_req : out t_mem_burst_req;
mem_resp : in t_mem_burst_resp;
hit_count : out unsigned(31 downto 0);
miss_count : out unsigned(31 downto 0) );
end dm_cache;
architecture gideon of dm_cache is
-- Our cache is 2K, and is one-set associative (direct mapped)
-- This means that the lower 11 bits are taken from the CPU address
-- while the upper address bits are matched against the tag ram.
-- Cache line size is 4 bytes, and hence we need 2K/4 = 512 tag entries.
-- Only the lower 32M is cachable, since I/O is above that range.
constant c_address_width : integer := client_req.address'length;
constant c_data_width : integer := client_req.data'length;
constant c_cache_size_bits : integer := 11;
constant c_line_size_bits : integer := 2; -- 4 words per line (entry)
constant c_tag_size_bits : integer := c_cache_size_bits - c_line_size_bits;
constant c_tag_width : natural := 2 + c_address_width - c_cache_size_bits;
function cache_index_of(a: unsigned(c_address_width-1 downto 0)) return unsigned is
begin
return a(c_cache_size_bits-1 downto 0);
end function;
function tag_index_of(a: unsigned(c_address_width-1 downto 0)) return unsigned is
begin
return a(c_cache_size_bits-1 downto c_line_size_bits);
end function;
function get_addr_high(a: unsigned(c_address_width-1 downto 0)) return unsigned is
begin
return a(c_address_width-1 downto c_cache_size_bits);
end function;
type t_tag is record
address_high : unsigned(c_address_width-1 downto c_cache_size_bits);
dirty : std_logic;
valid : std_logic;
end record;
function tag_pack(t : t_tag) return std_logic_vector is
variable ret : std_logic_vector(c_tag_width-1 downto 0);
begin
ret := t.dirty & t.valid & std_logic_vector(t.address_high);
return ret;
end function;
function tag_unpack(v : std_logic_vector(c_tag_width-1 downto 0)) return t_tag is
variable ret : t_tag;
begin
ret.dirty := v(v'high);
ret.valid := v(v'high-1);
ret.address_high := unsigned(v(v'high-2 downto 0));
return ret;
end function;
signal any_request : std_logic := '0';
signal read_request : std_logic := '0';
signal read_request_d : std_logic := '0';
signal write_request : std_logic := '0';
signal write_request_d : std_logic := '0';
signal ready : std_logic := '0';
signal read_la : std_logic := '0';
signal write_la : std_logic := '0';
signal tag_la : std_logic_vector(client_req.tag'range);
signal do_query_d : std_logic;
signal rd_address : unsigned(c_address_width-1 downto 0);
signal wr_address : unsigned(c_address_width-1 downto 0);
signal cache_rd_index : unsigned(c_cache_size_bits-1 downto 0);
signal cache_wr_index : unsigned(c_cache_size_bits-1 downto 0);
signal cache_wdata : std_logic_vector(c_data_width-1 downto 0);
signal cache_data_out : std_logic_vector(c_data_width-1 downto 0);
signal cache_rdata : std_logic_vector(c_data_width-1 downto 0);
signal cache_we : std_logic;
signal cache_b_en : std_logic;
signal cache_rd_en : std_logic;
signal tag_rd_index : unsigned(c_cache_size_bits-1 downto c_line_size_bits);
signal tag_wr_index : unsigned(c_cache_size_bits-1 downto c_line_size_bits);
signal tag_wdata : std_logic_vector(c_tag_width-1 downto 0);
signal tag_rdata : std_logic_vector(c_tag_width-1 downto 0);
signal rd_tag : t_tag;
signal wr_tag : t_tag;
signal fill_tag : t_tag;
signal last_write_tag : t_tag;
signal hit_i : std_logic := '0';
signal cache_miss : std_logic := '0';
signal cache_hit : std_logic := '0';
signal old_address : unsigned(c_address_width-1 downto 0);
signal address_la : unsigned(c_address_width-1 downto 0);
-- back office
signal fill_high : unsigned(c_address_width-1 downto c_line_size_bits) := (others => '0');
signal fill_address : unsigned(c_address_width-1 downto 0) := (others => '0');
signal fill_valid : std_logic;
signal fill_data : std_logic_vector(c_data_width-1 downto 0);
signal burst_count : unsigned(c_line_size_bits-1 downto 0);
signal burst_count_d : unsigned(c_line_size_bits-1 downto 0);
type t_state is (idle, check_dirty, fill, deferred);
signal state : t_state;
signal dirty_d : std_logic;
-- signals related to delayed write register
signal last_write_address : unsigned(c_address_width-1 downto 0);
signal last_write_data : std_logic_vector(c_data_width-1 downto 0);
signal last_write_hit : std_logic;
signal last_write_valid : std_logic;
signal store_reg : std_logic := '0';
signal store_after_fill : std_logic := '0';
-- memory interface
signal mem_busy : std_logic := '0';
signal need_mem_access : std_logic := '0';
signal mem_req_i : std_logic;
signal mem_rwn : std_logic;
signal mem_address : unsigned(c_address_width-1 downto 0);
signal mem_wdata : std_logic_vector(c_data_width-1 downto 0);
signal mem_wrfifo_put : std_logic;
signal mem_rdfifo_get : std_logic;
signal helper_data_to_ram : std_logic_vector(c_data_width-1 downto 0);
signal helper_data_from_ram : std_logic_vector(c_data_width-1 downto 0);
-- statistics
signal hit_count_i : unsigned(31 downto 0) := (others => '0');
signal miss_count_i : unsigned(31 downto 0) := (others => '0');
begin
any_request <= client_req.request and ready;
read_request <= client_req.request and client_req.read_writen and ready;
write_request <= client_req.request and not client_req.read_writen and ready;
ready <= '1' when mem_busy='0' and need_mem_access='0' else '0';
need_mem_access <= cache_miss;
process(clock)
begin
if rising_edge(clock) then
read_request_d <= read_request;
write_request_d <= write_request;
do_query_d <= '0';
if ready='1' then
do_query_d <= client_req.request;
tag_la <= client_req.tag;
address_la <= client_req.address;
read_la <= client_req.request and client_req.read_writen;
write_la <= client_req.request and not client_req.read_writen;
end if;
end if;
end process;
-- main address multiplexer
rd_address <= client_req.address;
wr_address <= fill_address when (fill_valid='1' or dirty_d='1') else
last_write_address;
cache_rd_index <= cache_index_of(rd_address);
cache_wr_index <= cache_index_of(wr_address);
cache_wdata <= fill_data when fill_valid='1' else
last_write_data;
wr_tag <= fill_tag when fill_valid='1' else
last_write_tag;
cache_we <= fill_valid or store_reg;
cache_b_en <= cache_we or dirty_d; -- dirty_d is set during fill operation and causes read enable here
cache_rd_en <= client_req.request and ready;
fill_tag.address_high <= get_addr_high(fill_address);
fill_tag.dirty <= '0';
fill_tag.valid <= '1';
last_write_tag.address_high <= get_addr_high(last_write_address);
last_write_tag.dirty <= '1';
last_write_tag.valid <= last_write_valid;
i_cache_ram: entity work.dpram_rdw
generic map (
g_width_bits => c_data_width,
g_depth_bits => c_cache_size_bits,
g_storage => "auto" )
port map (
clock => clock,
a_address => cache_rd_index,
a_rdata => cache_rdata,
a_en => cache_rd_en,
b_address => cache_wr_index,
b_rdata => cache_data_out,
b_wdata => cache_wdata,
b_en => cache_b_en,
b_we => cache_we );
tag_rd_index <= tag_index_of(rd_address);
tag_wr_index <= tag_index_of(wr_address);
rd_tag <= tag_unpack(tag_rdata);
tag_wdata <= tag_pack(wr_tag);
i_tag_ram: entity work.dpram_rdw
generic map (
g_width_bits => c_tag_width,
g_depth_bits => c_tag_size_bits )
port map (
clock => clock,
a_address => tag_rd_index,
a_rdata => tag_rdata,
a_en => cache_rd_en,
b_address => tag_wr_index,
b_wdata => tag_wdata,
b_en => cache_we,
b_we => cache_we );
hit_i <= '1' when rd_tag.valid='1' and (rd_tag.address_high = get_addr_high(address_la)) else '0';
cache_hit <= hit_i and do_query_d;
cache_miss <= not hit_i and do_query_d;
old_address <= rd_tag.address_high & address_la(c_cache_size_bits-1 downto 0); -- recombine
-- handle writes
process(clock)
begin
if rising_edge(clock) then
last_write_hit <= '0';
if client_req.request='1' and client_req.read_writen='1' and ready='1' then -- hit only occurs on reads
if (last_write_address = client_req.address) and last_write_valid='1' then -- address equal and valid?
last_write_hit <= '1';
end if;
end if;
if client_req.request='1' and client_req.read_writen='0' and ready='1' then
last_write_data <= client_req.data;
last_write_address <= client_req.address;
last_write_valid <= '1';
elsif store_reg='1' then
last_write_valid <= '0';
end if;
end if;
end process;
store_reg <= '1' when (last_write_valid='1' and (cache_hit='1' or store_after_fill='1')) else
'0';
-- end handle writes
-- read data multiplexer
fill_valid <= mem_resp.rdata_av;
fill_data <= mem_resp.data;
client_resp.rack <= client_req.request and ready;
client_resp.rack_tag <= client_req.tag when client_req.request='1' and ready='1' else (others => '0');
process(read_request_d, tag_la, cache_hit, cache_rdata,
fill_data, fill_valid, burst_count, read_la, address_la)
begin
client_resp.dack_tag <= (others => '0');
if cache_hit='1' then
client_resp.data <= cache_rdata;
if read_request_d='1' then
client_resp.dack_tag <= tag_la;
end if;
else
client_resp.data <= fill_data;
-- Generate dack when correct word passes by (not necessary, but will increase performance)
-- (In this setup it is necessary, because there is no other cause to let the client continue,
-- as 'hit' will not automatically become '1', as we already acknowledged the request itself.)
if fill_valid='1' and burst_count = address_la(burst_count'range) and read_la='1' then
client_resp.dack_tag <= tag_la;
end if;
end if;
end process;
-- end read data multiplexer
p_cache_control: process(clock)
begin
if rising_edge(clock) then
burst_count_d <= burst_count;
store_after_fill <= '0';
mem_req_i <= '0';
if cache_miss='1' then
miss_count_i <= miss_count_i + 1;
end if;
if cache_hit='1' then
hit_count_i <= hit_count_i + 1;
end if;
case state is
when idle =>
-- There are a few scenarios that could cause a miss:
-- Read miss: last_write_register is not valid, because it should already have been written in the cache!
-- Write miss: last_write_register is always valid, since it was just set. In this scenario the last write register
-- holds data that still needs to be written to the cache, BUT couldn't do it because of the miss. The data in the cache
-- that is flushed to DRAM is never the data in the register, otherwise it would have been a hit. The fill cycle that
-- follows will check dirty, do a write out of the dirty data from cache, and then fills the cacheline with data from
-- the DRAM, and then will issue the command to store the register. Obviously this immediately sets the line to dirty.
if cache_miss='1' then
if mem_resp.ready='1' then
-- issue read access (priority read over write)
mem_req_i <= '1';
mem_rwn <= '1';
mem_address <= address_la;
state <= check_dirty;
else
state <= deferred;
end if;
end if;
dirty_d <= rd_tag.dirty and cache_miss; -- dirty will be our read enable from cache :)
--fill_high <= old_address(old_address'high downto c_line_size_bits); -- high bits don't matter here (this is correct!)
--fill_high <= address_la(old_address'high downto c_line_size_bits); -- high bits don't matter here (optimization!!)
when deferred =>
if mem_resp.ready='1' then
-- issue read access (priority read over write)
mem_req_i <= '1';
mem_rwn <= '1';
mem_address <= address_la;
state <= check_dirty;
end if;
when check_dirty => -- sequences through 'line_size' words
mem_address <= old_address;
mem_rwn <= '0'; -- write
if dirty_d='0' then
--fill_high <= address_la(address_la'high downto c_line_size_bits); -- high bits do matter here
state <= fill;
else -- dirty_d='1'
burst_count <= burst_count + 1;
if signed(burst_count) = -1 then -- last?
mem_req_i <= '1'; -- issue the write request to memctrl
dirty_d <= '0';
--fill_high <= address_la(address_la'high downto c_line_size_bits); -- high bits do matter here
state <= fill;
end if;
end if;
when fill =>
if mem_resp.rdata_av='1' then
burst_count <= burst_count + 1;
if signed(burst_count) = -1 then -- last?
state <= idle;
store_after_fill <= last_write_valid; -- this will occur during idle
end if;
end if;
-- asynchronously: mem_rdfifo_get <= '1' when state = fill and mem_resp.rdata_av='1'.
when others =>
null;
end case;
mem_wrfifo_put <= dirty_d; -- latency of blockram
if reset='1' then
burst_count <= (others => '0');
dirty_d <= '0';
state <= idle;
mem_rwn <= '1';
mem_req_i <= '0';
end if;
end if;
end process;
mem_rdfifo_get <= '1' when state = fill and mem_resp.rdata_av='1' else '0';
-- index to the cache for back-office operations (line in, line out)
fill_high <= address_la(old_address'high downto c_line_size_bits);
fill_address <= fill_high & burst_count;
mem_busy <= '1' when (state/= idle) else '0';
mem_wdata <= cache_data_out;
mem_req.request <= mem_req_i;
mem_req.read_writen <= mem_rwn;
mem_req.address <= mem_address(mem_address'high downto c_line_size_bits) & to_unsigned(0, c_line_size_bits);
mem_req.data <= mem_wdata;
mem_req.data_pop <= mem_rdfifo_get;
mem_req.data_push <= mem_wrfifo_put;
helper_data_to_ram <= mem_wdata when mem_wrfifo_put='1' else (others => 'Z');
helper_data_from_ram <= mem_resp.data when mem_rdfifo_get='1' else (others => 'Z');
hit_count <= hit_count_i;
miss_count <= miss_count_i;
end gideon;
| gpl-3.0 | fd8c0ebd7448e15ae44253b7ab946dee | 0.522449 | 3.810075 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op330_17sk1_0.vhdl | 1 | 7,819 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.15e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.15e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1e-06,
W => W_0,
W_0init => 4.47e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 7.705e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net2,
G => vbias3,
S => net6
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7e-07,
W => Wcm_2,
Wcm_2init => 7e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7e-07,
W => Wcmout_2,
Wcmout_2init => 2.035e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net7,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 7.705e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias3,
S => net7
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 7.705e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7e-07,
W => Wcm_2,
Wcm_2init => 7e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7e-07,
W => Wcmout_2,
Wcmout_2init => 2.035e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 7.705e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 7.305e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias2,
S => net10
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.5e-07,
W => Wcm_1,
Wcm_1init => 7.59e-05,
scope => private
)
port map(
D => net10,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.5e-07,
W => Wcmout_1,
Wcmout_1init => 4.61e-05,
scope => private
)
port map(
D => net11,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 7.305e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net11
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1e-06,
W => (pfak)*(WBias),
WBiasinit => 4.8e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1e-06,
W => (pfak)*(WBias),
WBiasinit => 4.8e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1e-06,
W => WBias,
WBiasinit => 4.8e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1e-06,
W => WBias,
WBiasinit => 4.8e-06
)
port map(
D => vbias2,
G => vbias3,
S => net12
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1e-06,
W => WBias,
WBiasinit => 4.8e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1e-06,
W => WBias,
WBiasinit => 4.8e-06
)
port map(
D => net12,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net13,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net13,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net13,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 8093ac62b237dedb3b8e4ac20554a122 | 0.582683 | 2.909937 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/zpu_tiny.vhd | 5 | 29,873 | ------------------------------------------------------------------------------
---- ----
---- ZPU Exec ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has a third (8-bit) port for ----
---- fetching instructions. This modification reduces the LUT size by ----
---- approximately 10% and increases the performance with 21%. ----
---- Needs external dual ported memory, plus single cycle external ----
---- program memory. It also requires a different linker script to ----
---- place the text segment on a logically different address to stick to ----
---- the single-, flat memory model programming paradigm. ----
---- ----
---- To Do: ----
---- Add a 'ready' for the external code memory ----
---- More thorough testing, cleanup code a bit more ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_tiny(Behave) (Entity and architecture) ----
---- File name: zpu_tiny.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_tiny is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_i : in unsigned(c_opcode_width-1 downto 0);
c_o : out unsigned(c_opcode_width-1 downto 0);
c_we_o : out std_logic;
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
addr_o : out unsigned(g_addr_size-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity zpu_tiny;
architecture Behave of zpu_tiny is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant SP_START : unsigned(g_stack_size-1 downto 2):=
SP_START_1(g_stack_size-1 downto 2);
constant IO_BIT : integer:=g_addr_size-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(c_max_addr_bit downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, some data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_en_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal first : std_logic := '0';
signal byte_cnt : unsigned(1 downto 0) := "00";
signal byte_cnt_d : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic;
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem, st_read_io, st_write_io,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_i;
c_addr_o <= resize(pc_r(g_prog_size-1 downto 0), g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-- c_addr_o(g_prog_size-1 downto 2) <= pc_r(g_prog_size-1 downto 2);
-- c_addr_o(1 downto 0) <= not pc_r(1 downto 0); -- fix big endianess
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_en_r <= '0';
byte_cnt_d <= byte_cnt;
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
c_mux_r <= '0';
first <= '0';
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
-- a_r <= (others => g_dont_care);
b_r <= (others => g_dont_care);
sp_offset:=(others => g_dont_care);
a_addr_r <= (others => g_dont_care);
-- b_addr_r <= (others => g_dont_care);
-- addr_r <= a_i(g_addr_size-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_addr_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, c_max_addr_bit+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
posted_wr_a <= '1';
state <= st_resync;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- DEBUG
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
addr_r <= a_i(g_addr_size-1 downto 0);
if a_i(IO_BIT)='1' then
read_en_o <= '1';
state <= st_read_io;
elsif a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
posted_wr_a <= '1';
state <= st_resync;
else
c_en_r <= '1';
c_mux_r <= '1';
state <= st_read_mem;
byte_cnt <= "11"; -- 4 bytes
byte_cnt_d <= "11";
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
b_addr_r <= sp_r+1; -- added from store/io_store
if a_i(IO_BIT)='1' then
state <= st_write_io;
elsif a_i(31) = '1' then
state <= st_store;
b_addr_r <= sp_r+1;
else
state <= st_write_mem;
byte_cnt <= "11"; -- 4 bytes
first <= '1';
c_mux_r <= '1';
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_resync;
when st_read_mem =>
-- BIG ENDIAN
case byte_cnt_d is
when "00" =>
a_r(7 downto 0) <= c_i;
when "01" =>
a_r(15 downto 8) <= c_i;
when "10" =>
a_r(23 downto 16) <= c_i;
when others => -- 11
a_r(31 downto 24) <= c_i;
end case;
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_cnt <= byte_cnt - 1;
if byte_cnt_d = "00" then
a_addr_r <= sp_r;
a_we_r <= '1';
state <= st_fetch;
c_mux_r <= '0';
c_en_r <= '0';
end if;
when st_write_mem =>
case byte_cnt is
when "00" =>
c_o <= b_i(7 downto 0);
when "01" =>
c_o <= b_i(15 downto 8);
when "10" =>
c_o <= b_i(23 downto 16);
when others => -- 11
c_o <= b_i(31 downto 24);
end case;
if first='1' then
first <= '0';
addr_r <= a_i(g_addr_size-1 downto 0);
else
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
end if;
c_en_r <= '1';
c_we_r <= '1';
byte_cnt <= byte_cnt - 1;
if byte_cnt = "00" then
sp_r <= sp_r+1;
state <= st_resync;
end if;
when st_read_io =>
-- Wait until memory I/O isn't busy
a_addr_r <= sp_r;
a_r <= data_i;
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(g_addr_size-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_we_r <= posted_wr_a;
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
c_mux_r <= '0';
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: zpu_tiny
| gpl-3.0 | a13a2346ef1fa59189bf16459815f0dd | 0.309008 | 4.876428 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op984_9.vhdl | 1 | 5,009 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net6,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net6,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias3,
S => net3
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 70d7716ba1ef5bc590faad999b391e84 | 0.580954 | 3.180317 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_source/proc_control.vhd | 2 | 15,945 |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
entity proc_control is
port (
clock : in std_logic;
clock_en : in std_logic;
reset : in std_logic;
interrupt : in std_logic;
i_reg : in std_logic_vector(7 downto 0);
index_carry : in std_logic;
pc_carry : in std_logic;
branch_taken : in boolean;
sync : out std_logic;
dummy_cycle : out std_logic;
set_b : out std_logic;
latch_dreg : out std_logic;
copy_d2p : out std_logic;
reg_update : out std_logic;
rwn : out std_logic;
vect_bit : out std_logic := '0';
a16 : out std_logic;
a_mux : out t_amux := c_amux_pc;
dout_mux : out t_dout_mux;
pc_oper : out t_pc_oper;
s_oper : out t_sp_oper;
adl_oper : out t_adl_oper;
adh_oper : out t_adh_oper );
end proc_control;
architecture gideon of proc_control is
type t_state is (fetch, decode, absolute, abs_hi, abs_fix, branch, branch_fix,
indir1, indir2, jump_sub, jump, retrn, rmw1, rmw2, vector, startup,
zp, zp_idx, zp_indir, push1, push2, push3, pull1, pull2, pull3 );
signal state : t_state;
signal next_state : t_state;
signal next_cp_p : std_logic;
signal next_rwn : std_logic;
signal next_dreg : std_logic;
signal next_amux : t_amux;
signal next_dout : t_dout_mux;
signal next_set_b : std_logic;
signal next_dummy : std_logic;
signal vectoring : std_logic;
begin
-- combinatroial process
process(state, i_reg, index_carry, pc_carry, branch_taken, interrupt, vectoring)
variable v_stack_idx : std_logic_vector(1 downto 0);
begin
-- defaults
sync <= '0';
pc_oper <= increment;
next_amux <= c_amux_pc;
next_rwn <= '1';
next_state <= state;
adl_oper <= keep;
adh_oper <= keep;
s_oper <= keep;
next_dreg <= '1';
next_cp_p <= '0';
next_dout <= reg_d;
next_set_b <= '0';
next_dummy <= '0';
v_stack_idx := stack_idx(i_reg);
case state is
when fetch =>
sync <= '1';
if interrupt='1' then
pc_oper <= keep;
next_rwn <= '0';
next_dout <= reg_pch;
next_state <= push1;
next_amux <= c_amux_stack;
else
next_state <= decode;
next_set_b <= '1';
end if;
when decode =>
adl_oper <= load_bus;
adh_oper <= clear;
if is_absolute(i_reg) then
if is_abs_jump(i_reg) then
next_state <= jump;
else
next_state <= absolute;
end if;
elsif is_implied(i_reg) then
pc_oper <= keep;
if is_stack(i_reg) then -- PHP, PLP, PHA, PLA
next_amux <= c_amux_stack;
case v_stack_idx is
when "00" => -- PHP
next_state <= push3;
next_rwn <= '0';
next_dout <= reg_flags;
when "10" => -- PHA
next_state <= push3;
next_rwn <= '0';
next_dout <= reg_accu;
when others =>
next_state <= pull1;
end case;
else
next_state <= fetch;
end if;
elsif is_zeropage(i_reg) then
next_amux <= c_amux_addr;
if is_indirect(i_reg) then
if is_postindexed(i_reg) then
next_state <= zp_indir;
else
next_state <= zp;
next_dummy <= '1';
end if;
else
next_state <= zp;
if is_store(i_reg) and not is_postindexed(i_reg) then
next_rwn <= '0';
next_dout <= reg_axy;
end if;
end if;
elsif is_relative(i_reg) then
next_state <= branch;
elsif is_stack(i_reg) then -- non-implied stack operations like BRK, JSR, RTI and RTS
next_amux <= c_amux_stack;
case v_stack_idx is
when c_stack_idx_brk =>
-- next_set_b <= '1';
next_rwn <= '0';
next_dout <= reg_pch;
next_state <= push1;
when c_stack_idx_jsr =>
next_dreg <= '0';
next_dout <= reg_pch;
next_state <= jump_sub;
when c_stack_idx_rti =>
next_state <= pull1;
when c_stack_idx_rts =>
next_state <= pull2;
when others =>
null;
end case;
elsif is_immediate(i_reg) then
next_state <= fetch;
end if;
when absolute =>
next_state <= abs_hi;
next_amux <= c_amux_addr;
adh_oper <= load_bus;
if is_postindexed(i_reg) then
adl_oper <= add_idx;
elsif not is_zeropage(i_reg) then
if is_store(i_reg) then
next_rwn <='0';
next_dout <= reg_axy;
end if;
end if;
if is_zeropage(i_reg) then
pc_oper <= keep;
else
pc_oper <= increment;
end if;
when abs_hi =>
pc_oper <= keep;
if is_postindexed(i_reg) then
if is_load(i_reg) and index_carry='0' then
next_amux <= c_amux_pc;
next_state <= fetch;
else
next_amux <= c_amux_addr;
next_state <= abs_fix;
if index_carry='1' then
adh_oper <= increment;
end if;
end if;
if is_store(i_reg) then
next_rwn <= '0';
next_dout <= reg_axy;
end if;
else -- not post-indexed
if is_jump(i_reg) then
next_amux <= c_amux_addr;
next_state <= jump;
adl_oper <= increment;
elsif is_rmw(i_reg) then
next_rwn <= '0';
next_dout <= reg_d;
next_dummy <= '1';
next_state <= rmw1;
next_amux <= c_amux_addr;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
end if;
when abs_fix =>
pc_oper <= keep;
if is_rmw(i_reg) then
next_state <= rmw1;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dout <= reg_d;
next_dummy <= '1';
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when branch =>
next_amux <= c_amux_pc;
if branch_taken then
pc_oper <= from_alu; -- add offset
next_state <= branch_fix;
else
pc_oper <= increment;
next_state <= decode;
sync <= '1';
end if;
when branch_fix =>
next_amux <= c_amux_pc;
if pc_carry='1' then
next_state <= fetch;
pc_oper <= keep; -- this will fix the PCH, since the carry is set
else
sync <= '1';
next_state <= decode;
pc_oper <= increment;
end if;
when indir1 =>
pc_oper <= keep;
next_state <= indir2;
next_amux <= c_amux_addr;
adl_oper <= copy_dreg;
adh_oper <= load_bus;
if is_store(i_reg) then
next_rwn <= '0';
next_dout <= reg_axy;
end if;
when indir2 =>
pc_oper <= keep;
if is_rmw(i_reg) then
next_dummy <= '1';
next_rwn <= '0';
next_dout <= reg_d;
next_state <= rmw1;
next_amux <= c_amux_addr;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when jump_sub =>
next_state <= push1;
pc_oper <= keep;
next_dout <= reg_pch;
next_rwn <= '0';
next_dreg <= '0';
next_amux <= c_amux_stack;
when jump =>
pc_oper <= copy;
next_amux <= c_amux_pc;
if is_stack(i_reg) and v_stack_idx=c_stack_idx_rts and vectoring='0' then
next_state <= retrn;
else
next_state <= fetch;
end if;
when retrn =>
pc_oper <= increment;
next_state <= fetch;
when pull1 =>
s_oper <= increment;
next_state <= pull2;
next_amux <= c_amux_stack;
pc_oper <= keep;
when pull2 =>
pc_oper <= keep;
if is_implied(i_reg) then
next_state <= fetch;
next_amux <= c_amux_pc;
next_cp_p <= not v_stack_idx(1); -- only for PLP
else -- it was a stack operation, but not implied (RTS/RTI)
s_oper <= increment;
next_state <= pull3;
next_amux <= c_amux_stack;
next_cp_p <= not v_stack_idx(0); -- only for RTI
end if;
when pull3 =>
pc_oper <= keep;
s_oper <= increment;
next_state <= jump;
next_amux <= c_amux_stack;
when push1 =>
pc_oper <= keep;
s_oper <= decrement;
next_state <= push2;
next_amux <= c_amux_stack;
next_rwn <= '0';
next_dreg <= '0';
next_dout <= reg_pcl;
when push2 =>
pc_oper <= keep;
s_oper <= decrement;
if (v_stack_idx=c_stack_idx_jsr) and vectoring='0' then
next_state <= jump;
next_amux <= c_amux_pc;
else
next_state <= push3;
next_rwn <= '0';
next_dout <= reg_flags;
next_amux <= c_amux_stack;
end if;
when push3 =>
pc_oper <= keep;
s_oper <= decrement;
if is_implied(i_reg) and vectoring='0' then -- PHP, PHA
next_amux <= c_amux_pc;
next_state <= fetch;
else
next_state <= vector;
next_amux <= c_amux_vector;
end if;
when rmw1 =>
pc_oper <= keep;
next_state <= rmw2;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dout <= shift_res;
when rmw2 =>
pc_oper <= keep;
next_state <= fetch;
next_amux <= c_amux_pc;
when vector =>
next_state <= jump;
pc_oper <= keep;
next_amux <= c_amux_vector;
when startup =>
next_state <= vector;
pc_oper <= keep;
next_amux <= c_amux_vector;
when zp =>
pc_oper <= keep;
if is_postindexed(i_reg) or is_indirect(i_reg) then
adl_oper <= add_idx;
next_state <= zp_idx;
next_amux <= c_amux_addr;
if is_postindexed(i_reg) and is_store(i_reg) then
next_rwn <= '0';
next_dout <= reg_axy;
end if;
elsif is_rmw(i_reg) then
next_dummy <= '1';
next_state <= rmw1;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dout <= reg_d;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when zp_idx =>
pc_oper <= keep;
if is_indirect(i_reg) then
next_state <= indir1;
adl_oper <= increment;
next_amux <= c_amux_addr;
elsif is_rmw(i_reg) then
next_state <= rmw1;
next_amux <= c_amux_addr;
next_rwn <= '0';
next_dout <= reg_d;
else
next_state <= fetch;
next_amux <= c_amux_pc;
end if;
when zp_indir =>
pc_oper <= keep;
next_state <= absolute;
next_amux <= c_amux_addr;
adl_oper <= increment;
when others =>
null;
end case;
end process;
reg_update <= '1' when (state = fetch) and vectoring='0' and
not is_stack(i_reg) and not is_relative(i_reg) else '0';
vect_bit <= '0' when state = vector else '1';
process(clock)
begin
if rising_edge(clock) then
if clock_en='1' then
state <= next_state;
a_mux <= next_amux;
dout_mux <= next_dout;
rwn <= next_rwn;
latch_dreg <= next_dreg and next_rwn; -- disable dreg latch for writes
copy_d2p <= next_cp_p;
set_b <= next_set_b;
dummy_cycle <= next_dummy;
if next_amux = c_amux_vector or next_amux = c_amux_pc then
a16 <= '1';
else
a16 <= '0';
end if;
if state = fetch then
vectoring <= interrupt;
end if;
end if;
if reset='1' then
a16 <= '1';
state <= startup; --vector;
a_mux <= c_amux_vector;
rwn <= '1';
latch_dreg <= '1';
dout_mux <= reg_d;
copy_d2p <= '0';
set_b <= '0';
vectoring <= '0';
dummy_cycle <= '0';
end if;
end if;
end process;
end gideon;
| gpl-3.0 | ba4281e2e36e8fefa0e3dbe0727907ef | 0.374224 | 4.21937 | false | false | false | false |
KB777/1541UltimateII | target/simulation/vhdl_sim/mblite_simu.vhd | 1 | 4,321 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
use work.tl_string_util_pkg.all;
library std;
use std.textio.all;
entity mblite_simu is
end entity;
architecture test of mblite_simu is
signal clock : std_logic := '0';
signal reset : std_logic;
signal imem_o : imem_out_type;
signal imem_i : imem_in_type;
signal dmem_o : dmem_out_type;
signal dmem_i : dmem_in_type;
signal irq_i : std_logic := '0';
signal irq_o : std_logic;
type t_mem_array is array(natural range <>) of std_logic_vector(31 downto 0);
shared variable memory : t_mem_array(0 to 1048575) := (others => (others => '0')); -- 4MB
BEGIN
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
core0 : core
port map (
imem_o => imem_o,
imem_i => imem_i,
dmem_o => dmem_o,
dmem_i => dmem_i,
int_i => irq_i,
int_o => irq_o,
rst_i => reset,
clk_i => clock );
-- memory and IO
process(clock)
variable s : line;
variable char : character;
variable byte : std_logic_vector(7 downto 0);
begin
if rising_edge(clock) then
if imem_o.ena_o = '1' then
imem_i.dat_i <= memory(to_integer(unsigned(imem_o.adr_o(21 downto 2))));
-- if (imem_i.dat_i(31 downto 26) = "000101") and (imem_i.dat_i(1 downto 0) = "01") then
-- report "Suspicious CMPS" severity warning;
-- end if;
end if;
if dmem_o.ena_o = '1' then
if dmem_o.adr_o(31 downto 25) = "0000000" then
if dmem_o.we_o = '1' then
for i in 0 to 3 loop
if dmem_o.sel_o(i) = '1' then
memory(to_integer(unsigned(dmem_o.adr_o(21 downto 2))))(i*8+7 downto i*8) := dmem_o.dat_o(i*8+7 downto i*8);
end if;
end loop;
else -- read
dmem_i.dat_i <= memory(to_integer(unsigned(dmem_o.adr_o(21 downto 2))));
end if;
else -- I/O
if dmem_o.we_o = '1' then -- write
case dmem_o.adr_o(19 downto 0) is
when X"00000" => -- interrupt
null;
when X"00010" => -- UART_DATA
byte := dmem_o.dat_o(31 downto 24);
char := character'val(to_integer(unsigned(byte)));
if byte = X"0D" then
-- Ignore character 13
elsif byte = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
when others =>
report "I/O write to " & hstr(dmem_o.adr_o) & " dropped";
end case;
else -- read
case dmem_o.adr_o(19 downto 0) is
when X"0000C" => -- Capabilities
dmem_i.dat_i <= X"00000002";
when X"00012" => -- UART_FLAGS
dmem_i.dat_i <= X"40404040";
when X"2000A" => -- 1541_A memmap
dmem_i.dat_i <= X"3F3F3F3F";
when X"2000B" => -- 1541_A audiomap
dmem_i.dat_i <= X"3E3E3E3E";
when others =>
report "I/O read to " & hstr(dmem_o.adr_o) & " dropped";
dmem_i.dat_i <= X"00000000";
end case;
end if;
end if;
end if;
if reset = '1' then
imem_i.ena_i <= '1';
dmem_i.ena_i <= '1';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 62fa15d49765def3616d3ccd1b00d927 | 0.425364 | 3.871864 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op338_4sk1_0.vhdl | 1 | 7,236 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 5.5e-07,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 5.5e-07,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.35e-06,
W => W_0,
W_0init => 6.6e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 5.5e-07,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 5.5e-07,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.43e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5e-07,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.43e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5e-07,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.43e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5e-07,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.43e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 5e-07,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 7.75e-06,
W => Wsrc_2,
Wsrc_2init => 5.055e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 7.75e-06,
W => Wsrc_2,
Wsrc_2init => 5.055e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.35e-06,
W => Wcm_1,
Wcm_1init => 1.41e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.35e-06,
W => Wcmout_1,
Wcmout_1init => 7.965e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 5.35e-06,
W => (pfak)*(WBias),
WBiasinit => 2.52e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 5.35e-06,
W => (pfak)*(WBias),
WBiasinit => 2.52e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 5.35e-06,
W => WBias,
WBiasinit => 2.52e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.35e-06,
W => WBias,
WBiasinit => 2.52e-05
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.35e-06,
W => WBias,
WBiasinit => 2.52e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.35e-06,
W => WBias,
WBiasinit => 2.52e-05
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net8,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net8,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net8,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 1ae92d053cfb76734d2c9dbfca444a41 | 0.582504 | 2.880573 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/ram/example_design/ram_prod.vhd | 1 | 10,048 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: ram_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END ram_prod;
ARCHITECTURE xilinx OF ram_prod IS
COMPONENT ram_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : ram_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | 31dbf019097d34e6483d7f3952aa6f35 | 0.49174 | 3.830728 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op960_5.vhdl | 1 | 5,995 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net7
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net7,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net8
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net9
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net10
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 12653fceca71ac385bc11b67aaf1753b | 0.577815 | 3.127282 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/c2n_playback/vhdl_source/c2n_playback_io.vhd | 3 | 7,052 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity c2n_playback_io is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
phi2_tick : in std_logic;
c64_stopped : in std_logic;
c2n_motor : in std_logic;
c2n_sense : out std_logic;
c2n_out_r : out std_logic;
c2n_out_w : out std_logic );
end c2n_playback_io;
architecture gideon of c2n_playback_io is
signal enabled : std_logic;
signal counter : unsigned(23 downto 0);
signal error : std_logic;
signal status : std_logic_vector(7 downto 0);
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal fifo_flush : std_logic;
signal fifo_write : std_logic;
signal pulse : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 63;
signal stream_en : std_logic;
type t_state is (idle, multi1, multi2, multi3, count_down);
signal state : t_state;
signal state_enc : std_logic_vector(1 downto 0);
signal mode : std_logic;
signal sel : std_logic_vector(1 downto 0);
signal c2n_out : std_logic;
attribute register_duplication : string;
attribute register_duplication of stream_en : signal is "no";
begin
process(clock)
begin
if rising_edge(clock) then
-- c2n pin out and sync
if sel = "00" then
c2n_sense <= enabled and not fifo_empty;
else
c2n_sense <= '0';
end if;
stream_en <= enabled and c2n_motor;
if fifo_empty='1' and enabled='1' then
error <= '1';
end if;
-- create a pulse of 50 ticks
if cnt2 = 0 then
pulse <= '0';
elsif phi2_tick='1' then
cnt2 <= cnt2 - 1;
end if;
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1'; -- ack for fifo write as well.
if req.address(11)='0' then
enabled <= req.data(0);
if req.data(1)='1' then
error <= '0';
end if;
fifo_flush <= req.data(2);
mode <= req.data(3);
sel <= req.data(7 downto 6);
end if;
elsif req.read='1' then
resp.ack <= '1';
resp.data <= status;
end if;
case state is
when idle =>
if enabled='1' and fifo_empty='0' then
if fifo_dout=X"00" then
if mode='1' then
state <= multi1;
else
counter <= to_unsigned(256*8, counter'length);
state <= count_down;
end if;
else
counter <= unsigned("0000000000000" & fifo_dout & "000");
state <= count_down;
end if;
else
toggle <= '0';
end if;
when multi1 =>
if fifo_empty='0' then
counter(7 downto 0) <= unsigned(fifo_dout);
state <= multi2;
elsif enabled = '0' then
state <= idle;
end if;
when multi2 =>
if fifo_empty='0' then
counter(15 downto 8) <= unsigned(fifo_dout);
state <= multi3;
elsif enabled = '0' then
state <= idle;
end if;
when multi3 =>
if fifo_empty='0' then
counter(23 downto 16) <= unsigned(fifo_dout);
state <= count_down;
elsif enabled = '0' then
state <= idle;
end if;
when count_down =>
if phi2_tick='1' and stream_en='1' and c64_stopped='0' then
if (counter = 1) or (counter = 0) then
pulse <= '1';
toggle <= not toggle;
cnt2 <= 49;
state <= idle;
else
counter <= counter - 1;
end if;
elsif enabled = '0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
enabled <= '0';
counter <= (others => '0');
pulse <= '0';
error <= '0';
mode <= '0';
sel <= "00";
end if;
end if;
end process;
fifo_write <= req.write and req.address(11); -- 0x800-0xFFF (2K)
fifo_read <= '0' when state = count_down else (enabled and not fifo_empty);
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 1536,
g_storage => "block",
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => req.data,
dout => fifo_dout,
flush => fifo_flush,
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= state_enc(0);
status(5) <= state_enc(1);
status(6) <= stream_en;
status(7) <= fifo_empty;
c2n_out <= not pulse;
with sel select c2n_out_r <=
c2n_out when "00",
pulse when "10",
'1' when others;
c2n_out_w <= pulse when sel="01" else '1';
with state select state_enc <=
"00" when idle,
"01" when multi1,
"01" when multi2,
"01" when multi3,
"10" when count_down,
"11" when others;
end gideon;
| gpl-3.0 | 30628de342744653a038454d51be9322 | 0.408678 | 4.302624 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/altaccumulate1.vhd | 1 | 4,686 | -- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: altaccumulate1.vhd
-- Megafunction Name(s):
-- altaccumulate
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altaccumulate1 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
overflow : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END altaccumulate1;
ARCHITECTURE SYN OF altaccumulate1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altaccumulate
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
width_in : NATURAL;
width_out : NATURAL
);
PORT (
overflow : OUT STD_LOGIC ;
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
overflow <= sub_wire0;
result <= sub_wire1(31 DOWNTO 0);
altaccumulate_component : altaccumulate
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "altaccumulate",
width_in => 8,
width_out => 32
)
PORT MAP (
clken => clken,
aclr => aclr,
clock => clock,
data => data,
overflow => sub_wire0,
result => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
-- Retrieval info: PRIVATE: CIN NUMERIC "0"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "1"
-- Retrieval info: PRIVATE: COUT NUMERIC "0"
-- Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "1"
-- Retrieval info: PRIVATE: OVERFLOW NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_IN NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
-- Retrieval info: CONSTANT: WIDTH_IN NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "32"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: overflow 0 0 0 0 OUTPUT NODEFVAL overflow
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: overflow 0 0 0 0 @overflow 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate1_inst.vhd TRUE
| gpl-2.0 | a5ef926fa6271412b8e6fcfb51283e49 | 0.655143 | 3.736842 | false | false | false | false |
KB777/1541UltimateII | fpga/cart_slot/vhdl_source/all_carts_v4.vhd | 1 | 20,048 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity all_carts_v4 is
generic (
g_kernal_base : std_logic_vector(27 downto 0) := X"0ECC000"; -- multiple of 16K
g_rom_base : std_logic_vector(27 downto 0) := X"0F00000"; -- multiple of 1M
g_ram_base : std_logic_vector(27 downto 0) := X"0EF0000" ); -- multiple of 64K
port (
clock : in std_logic;
reset : in std_logic;
RST_in : in std_logic;
c64_reset : in std_logic;
ethernet_enable : in std_logic := '1';
kernal_enable : in std_logic;
kernal_area : in std_logic;
freeze_trig : in std_logic; -- goes '1' when the button has been pressed and we're waiting to enter the freezer
freeze_act : in std_logic; -- goes '1' when we need to switch in the cartridge for freeze mode
unfreeze : out std_logic; -- indicates the freeze logic to switch back to non-freeze mode.
cart_active : out std_logic; -- indicates that the cartridge is active
cart_kill : in std_logic;
cart_logic : in std_logic_vector(3 downto 0); -- 1 out of 16 logic emulations
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
epyx_timeout : in std_logic;
serve_enable : out std_logic; -- enables fetching bus address PHI2=1
serve_vic : out std_logic; -- enables doing so for PHI2=0
serve_rom : out std_logic; -- ROML or ROMH
serve_io1 : out std_logic; -- IO1n
serve_io2 : out std_logic; -- IO2n
allow_write : out std_logic;
mem_addr : out unsigned(25 downto 0);
irq_n : out std_logic;
nmi_n : out std_logic;
exrom_n : out std_logic;
game_n : out std_logic;
CART_LEDn : out std_logic );
end all_carts_v4;
architecture gideon of all_carts_v4 is
signal reset_in : std_logic;
signal ext_bank : std_logic_vector(18 downto 16);
signal bank_bits : std_logic_vector(15 downto 13);
signal mode_bits : std_logic_vector(2 downto 0);
signal ram_select : std_logic;
-- signal rom_enable : std_logic;
signal freeze_act_d : std_logic;
signal cart_en : std_logic;
signal do_io2 : std_logic;
signal allow_bank : std_logic;
signal hold_nmi : std_logic;
signal eth_addr : boolean;
signal cart_logic_d : std_logic_vector(cart_logic'range) := (others => '0');
signal mem_addr_i : std_logic_vector(27 downto 0);
constant c_none : std_logic_vector(3 downto 0) := "0000";
constant c_8k : std_logic_vector(3 downto 0) := "0001";
constant c_16k : std_logic_vector(3 downto 0) := "0010";
constant c_16k_umax : std_logic_vector(3 downto 0) := "0011";
constant c_fc3 : std_logic_vector(3 downto 0) := "0100";
constant c_ss5 : std_logic_vector(3 downto 0) := "0101";
constant c_retro : std_logic_vector(3 downto 0) := "0110";
constant c_action : std_logic_vector(3 downto 0) := "0111";
constant c_system3 : std_logic_vector(3 downto 0) := "1000";
constant c_domark : std_logic_vector(3 downto 0) := "1001";
constant c_ocean128 : std_logic_vector(3 downto 0) := "1010";
constant c_ocean256 : std_logic_vector(3 downto 0) := "1011";
constant c_easy_flash : std_logic_vector(3 downto 0) := "1100";
constant c_epyx : std_logic_vector(3 downto 0) := "1110";
constant c_serve_rom_rr : std_logic_vector(0 to 7) := "11011111";
constant c_serve_io_rr : std_logic_vector(0 to 7) := "10101111";
-- alias
signal slot_addr : std_logic_vector(15 downto 0);
signal io_read : std_logic;
signal io_write : std_logic;
signal io_addr : std_logic_vector(8 downto 0);
signal io_wdata : std_logic_vector(7 downto 0);
begin
serve_enable <= cart_en or kernal_enable;
cart_active <= cart_en;
slot_addr <= std_logic_vector(slot_req.bus_address);
io_write <= slot_req.io_write;
io_read <= slot_req.io_read;
io_addr <= std_logic_vector(slot_req.io_address(8 downto 0));
io_wdata <= slot_req.data;
process(clock)
begin
if rising_edge(clock) then
reset_in <= reset or RST_in or c64_reset;
freeze_act_d <= freeze_act;
unfreeze <= '0';
-- control register
if reset_in='1' then
cart_logic_d <= cart_logic; -- activate change of mode!
mode_bits <= (others => '0');
bank_bits <= (others => '0');
ext_bank <= (others => '0');
allow_bank <= '0';
ram_select <= '0';
do_io2 <= '1';
cart_en <= '1';
-- unfreeze <= '0';
hold_nmi <= '0';
elsif freeze_act='1' and freeze_act_d='0' then
bank_bits <= (others => '0');
mode_bits <= (others => '0');
--allow_bank <= '0';
ram_select <= '0';
cart_en <= '1';
-- unfreeze <= '0';
hold_nmi <= '1';
elsif cart_en = '0' then
cart_logic_d <= cart_logic; -- activate change of mode!
end if;
serve_vic <= '0';
case cart_logic_d is
when c_fc3 =>
-- unfreeze <= '0';
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
bank_bits <= io_wdata(1 downto 0) & '0';
mode_bits <= '0' & io_wdata(4) & io_wdata(5);
unfreeze <= '1';
cart_en <= not io_wdata(7);
hold_nmi <= not io_wdata(6);
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
else
game_n <= mode_bits(0);
exrom_n <= mode_bits(1);
end if;
if mode_bits(1 downto 0)="10" then
serve_vic <= '1';
end if;
serve_rom <= '1';
serve_io1 <= '1';
serve_io2 <= '1';
irq_n <= '1';
nmi_n <= not(freeze_trig or freeze_act or hold_nmi);
when c_retro | c_action =>
if io_write='1' and io_addr(8 downto 1) = X"00" and cart_en='1' then -- DE00/DE01
if io_addr(0)='0' then
bank_bits <= io_wdata(7) & io_wdata(4 downto 3);
mode_bits <= io_wdata(5) & io_wdata(1 downto 0);
unfreeze <= io_wdata(6);
cart_en <= not io_wdata(2);
else
if io_wdata(6)='1' then
do_io2 <= '0';
end if;
if io_wdata(1)='1' then
allow_bank <= '1';
end if;
end if;
end if;
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
else
game_n <= not mode_bits(0);
exrom_n <= mode_bits(1);
serve_io1 <= c_serve_io_rr(to_integer(unsigned(mode_bits)));
serve_io2 <= c_serve_io_rr(to_integer(unsigned(mode_bits))) and do_io2;
serve_rom <= c_serve_rom_rr(to_integer(unsigned(mode_bits)));
end if;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_easy_flash =>
if io_write='1' and io_addr(8)='0' and cart_en='1' then -- DExx
if io_addr(1)='0' then -- DE00
ext_bank <= io_wdata(5 downto 3);
bank_bits <= io_wdata(2 downto 0);
else -- DE02
mode_bits <= io_wdata(2 downto 0); -- LED not implemented
end if;
end if;
game_n <= not (mode_bits(0) or not mode_bits(2));
exrom_n <= not mode_bits(1);
serve_rom <= '1';
serve_io1 <= '0'; -- write registers only, no reads
serve_io2 <= '1'; -- RAM
irq_n <= '1';
nmi_n <= '1';
when c_ss5 =>
if io_write='1' and io_addr(8) = '0' and cart_en='1' then -- DE00-DEFF
bank_bits <= io_wdata(4) & io_wdata(2) & '0';
mode_bits <= io_wdata(3) & io_wdata(1) & io_wdata(0);
unfreeze <= not io_wdata(0);
cart_en <= not io_wdata(3);
end if;
game_n <= mode_bits(0);
exrom_n <= not mode_bits(1);
serve_io1 <= cart_en;
serve_io2 <= '0';
serve_rom <= cart_en;
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
when c_8k =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
cart_en <= '0'; -- permanent off
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '1'; -- for EPYX test
irq_n <= '1';
nmi_n <= '1';
when c_16k =>
-- if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
-- cart_en <= '0'; -- permanent off
-- end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_16k_umax =>
if io_write='1' and io_addr(8 downto 0) = "111111111" and cart_en='1' then -- DFFF
cart_en <= '0'; -- permanent off
end if;
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_ocean128 =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= io_wdata(5 downto 3);
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_domark =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= '0' & io_wdata(4 downto 3);
mode_bits(0) <= io_wdata(7);
-- if io_wdata(7 downto 5) /= "000" then -- permanent off
-- cart_en <= '0';
-- end if;
cart_en <= not (io_wdata(7) or io_wdata(6) or io_wdata(5));
end if;
game_n <= '1';
exrom_n <= mode_bits(0);
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_ocean256 =>
if io_write='1' and io_addr(8)='0' then -- DE00 range
bank_bits <= io_wdata(2 downto 0);
ext_bank <= "00" & io_wdata(3);
end if;
game_n <= '0';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_system3 => -- 16K, only 8K used?
if (io_write='1' or io_read='1') and io_addr(8)='0' then -- DE00 range
bank_bits <= io_addr(2 downto 0);
ext_bank <= io_addr(5 downto 3);
end if;
game_n <= '1';
exrom_n <= '0';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
when c_epyx =>
game_n <= '1';
exrom_n <= epyx_timeout;
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '1'; -- rom visible df00-dfff
irq_n <= '1';
nmi_n <= '1';
when others =>
game_n <= '1';
exrom_n <= '1';
serve_rom <= '0';
serve_io1 <= '0';
serve_io2 <= '0';
irq_n <= '1';
nmi_n <= '1';
end case;
if cart_kill='1' then
cart_en <= '0';
hold_nmi <= '0';
end if;
end if;
end process;
CART_LEDn <= not cart_en;
-- decode address DE02-DE0F
eth_addr <= slot_addr(15 downto 4) = X"DE0" and slot_addr(3 downto 1) /= "000" and ethernet_enable='1';
-- determine address
-- process(cart_logic_d, cart_base_d, slot_addr, mode_bits, bank_bits, do_io2, allow_bank, eth_addr)
process(cart_logic_d, slot_addr, mode_bits, bank_bits, ext_bank, do_io2, allow_bank, eth_addr, kernal_area)
begin
mem_addr_i <= g_rom_base;
-- defaults
-- 64K, 8K banks, no writes
mem_addr_i(15 downto 0) <= bank_bits(15 downto 13) & slot_addr(12 downto 0);
allow_write <= '0';
case cart_logic_d is
when c_retro =>
-- 64K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 16) & bank_bits(15 downto 13) & slot_addr(12 downto 0);
if allow_bank='0' and slot_addr(15 downto 13)="110" then -- io range exceptions
mem_addr_i <= g_ram_base(27 downto 16) & "000" & slot_addr(12 downto 0);
end if;
end if;
if slot_addr(15 downto 13)="100" then--and mode_bits(1 downto 0)/="10" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
when c_action =>
-- 32K RAM
if mode_bits(2)='1' then
if slot_addr(13)='0' then
mem_addr_i <= g_ram_base(27 downto 15) & bank_bits(14 downto 13) & slot_addr(12 downto 0);
if allow_bank='0' and slot_addr(15 downto 13)="110" then -- io range exceptions
mem_addr_i <= g_ram_base(27 downto 15) & "00" & slot_addr(12 downto 0);
end if;
end if;
if slot_addr(15 downto 13)="100" then -- and mode_bits(1 downto 0)="11" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
end if;
when c_easy_flash =>
-- Little RAM
if slot_addr(15 downto 8)=X"DF" then
mem_addr_i <= g_ram_base(27 downto 8) & slot_addr(7 downto 0);
allow_write <= '1';
else
mem_addr_i <= g_rom_base(27 downto 20) & slot_addr(13) & ext_bank & bank_bits & slot_addr(12 downto 0);
end if;
when c_fc3 =>
mem_addr_i(15 downto 0) <= bank_bits(15 downto 14) & slot_addr(13 downto 0); -- 16K banks
when c_ss5 =>
if mode_bits(1 downto 0)="00" then
if slot_addr(15 downto 13)="100" then
allow_write <= '1';
mem_addr_i <= g_ram_base(27 downto 15) & bank_bits(15 downto 14) & slot_addr(12 downto 0);
else
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0);
end if;
else
mem_addr_i <= g_rom_base(27 downto 16) & bank_bits(15 downto 14) & slot_addr(13 downto 0);
end if;
when c_8k | c_epyx =>
mem_addr_i(27 downto 13) <= g_rom_base(27 downto 13);
mem_addr_i(12 downto 0) <= slot_addr(12 downto 0);
when c_16k | c_16k_umax =>
mem_addr_i(27 downto 14) <= g_rom_base(27 downto 14);
mem_addr_i(13 downto 0) <= slot_addr(13 downto 0);
when c_ocean128 | c_system3 | c_domark | c_ocean256 =>
mem_addr_i <= g_rom_base(27 downto 20) & slot_addr(13) & ext_bank & bank_bits & slot_addr(12 downto 0);
-- when c_ocean256 =>
-- mem_addr_i(18 downto 0) <= ext_bank & bank_bits & slot_addr(12 downto 0);
-- mem_addr_i(19) <= slot_addr(13); -- map banks 16-31 to $A000. (second 128K)
when others =>
null;
end case;
if kernal_area='1' then
mem_addr_i <= g_kernal_base(27 downto 14) & slot_addr(12 downto 0) & '0';
end if;
-- if eth_addr then
-- mem_addr_i(25 downto 21) <= eth_base(25 downto 21);
-- mem_addr_i(20) <= '1'; -- indicate it is a slot access
-- allow_write <= '1'; -- we should also be able to write to the ethernet chip
-- -- invert bit 3
-- mem_addr_i(3) <= not slot_addr(3);
-- -- leave other bits in tact
-- end if;
end process;
mem_addr <= unsigned(mem_addr_i(mem_addr'range));
slot_resp.data(7) <= bank_bits(15);
slot_resp.data(6) <= '1';
slot_resp.data(5) <= '0';
slot_resp.data(4) <= bank_bits(14);
slot_resp.data(3) <= bank_bits(13);
slot_resp.data(2) <= '0'; -- freeze button pressed
slot_resp.data(1) <= allow_bank; -- '1'; -- allow bank bit stuck at '1' for 1541U
slot_resp.data(0) <= '0';
slot_resp.reg_output <= '1' when (slot_addr(8 downto 1)="00000000") and (cart_logic_d = c_retro) else '0';
end gideon;
| gpl-3.0 | a5e021d92638c0393605ea8c3bb192f8 | 0.424032 | 3.615509 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op11.vhdl | 1 | 10,343 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.45e-06,
W => Wdiff_0,
Wdiff_0init => 3.82e-05,
scope => private
)
port map(
D => net2,
G => in1,
S => net5
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.45e-06,
W => Wdiff_0,
Wdiff_0init => 3.82e-05,
scope => private
)
port map(
D => net1,
G => in2,
S => net5
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 5.3e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.45e-06,
W => Wdiff_0,
Wdiff_0init => 3.82e-05,
scope => private
)
port map(
D => net6,
G => in1,
S => net5
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.45e-06,
W => Wdiff_0,
Wdiff_0init => 3.82e-05,
scope => private
)
port map(
D => net6,
G => in2,
S => net5
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.15e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2.65e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.15e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2.65e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.15e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2.65e-06,
scope => private
)
port map(
D => net1,
G => net6,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.15e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2.65e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc_1,
Lsrc_1init => 4.5e-07,
W => Wsrc_1,
Wsrc_1init => 5.385e-05,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => C_2,
C_2init => 4.31e-12,
symmetry_scope => sym_3
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc_1,
Lsrc_1init => 4.5e-07,
W => Wsrc_1,
Wsrc_1init => 5.385e-05,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => C_3,
C_3init => 1.308e-12,
symmetry_scope => sym_3
)
port map(
P => net4,
N => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.55e-06,
W => Wcm_2,
Wcm_2init => 5.125e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.55e-06,
W => Wcmcout_2,
Wcmcout_2init => 1.28e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.55e-06,
W => Wcm_2,
Wcm_2init => 5.125e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.55e-06,
W => Wcmcout_2,
Wcmcout_2init => 1.28e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => out2,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcursrc_3,
Wcursrc_3init => 7.83e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias1,
S => vdd
);
subnet0_subnet6_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => Wcursrc_3,
Wcursrc_3init => 7.83e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out2,
G => vbias1,
S => vdd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net7,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net10,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net9,
N => net7
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_1,
W_1init => 6.765e-05
)
port map(
D => net8,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 2.75e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 3.505e-05,
scope => private
)
port map(
D => net10,
G => vref,
S => net8
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 2.75e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 3.505e-05,
scope => private
)
port map(
D => net9,
G => net7,
S => net8
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 2.3e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 4.45e-05,
scope => private
)
port map(
D => net9,
G => net9,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 2.3e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 4.45e-05,
scope => private
)
port map(
D => net10,
G => net9,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 7.4e-06,
W => Wcmbias_0,
Wcmbias_0init => 6.5e-07,
scope => private
)
port map(
D => out1,
G => net10,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 7.4e-06,
W => Wcmbias_0,
Wcmbias_0init => 6.5e-07,
scope => private
)
port map(
D => out2,
G => net10,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.6e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.6e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.6e-06
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 3d10d0b6d0a417116c4bf53542ed2921 | 0.56705 | 2.807546 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op988_8.vhdl | 1 | 6,153 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net8
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net8,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net9,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 9f5bfb858f4ac91b4f4e7d7754578273 | 0.574516 | 3.088855 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op10.vhdl | 1 | 9,426 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.7e-06,
W => Wdiff_0,
Wdiff_0init => 6.99e-05,
scope => private
)
port map(
D => net2,
G => in1,
S => net3
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.7e-06,
W => Wdiff_0,
Wdiff_0init => 6.99e-05,
scope => private
)
port map(
D => net1,
G => in2,
S => net3
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => W_0,
W_0init => 1.5e-06
)
port map(
D => net3,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.45e-06,
W => Wcm_1,
Wcm_1init => 1.5e-06,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.45e-06,
W => Wcmcout_1,
Wcmcout_1init => 4.4e-06,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.45e-06,
W => Wcm_1,
Wcm_1init => 1.5e-06,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.45e-06,
W => Wcmcout_1,
Wcmcout_1init => 4.4e-06,
scope => private,
symmetry_scope => sym_3
)
port map(
D => net5,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcursrc_2,
Wcursrc_2init => 1.55e-06,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcursrc_2,
Wcursrc_2init => 1.55e-06,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lsrc_3,
Lsrc_3init => 7.5e-07,
W => Wsrc_3,
Wsrc_3init => 6.81e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_c1 : entity cap(behave)
generic map(
C => C_2,
C_2init => 2.461e-12,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net4
);
subnet0_subnet6_m1 : entity nmos(behave)
generic map(
L => Lsrc_3,
Lsrc_3init => 7.5e-07,
W => Wsrc_3,
Wsrc_3init => 6.81e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out2,
G => net5,
S => gnd
);
subnet0_subnet6_c1 : entity cap(behave)
generic map(
C => C_3,
C_3init => 2.17e-12,
symmetry_scope => sym_5
)
port map(
P => out2,
N => net5
);
subnet0_subnet7_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcursrc_4,
Wcursrc_4init => 4.825e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out1,
G => vbias1,
S => vdd
);
subnet0_subnet8_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcursrc_4,
Wcursrc_4init => 4.825e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out2,
G => vbias1,
S => vdd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net6,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net6,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net9,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net8,
N => net6
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => W_1,
W_1init => 3.5e-05
)
port map(
D => net7,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 1.08e-05,
W => Wcmdiff_0,
Wcmdiff_0init => 2.865e-05,
scope => private
)
port map(
D => net9,
G => vref,
S => net7
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 1.08e-05,
W => Wcmdiff_0,
Wcmdiff_0init => 2.865e-05,
scope => private
)
port map(
D => net8,
G => net6,
S => net7
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 1.25e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 3.55e-06,
scope => private
)
port map(
D => net8,
G => net8,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 1.25e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 3.55e-06,
scope => private
)
port map(
D => net9,
G => net8,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 7.45e-06,
W => Wcmbias_0,
Wcmbias_0init => 3.345e-05,
scope => private
)
port map(
D => out1,
G => net9,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 7.45e-06,
W => Wcmbias_0,
Wcmbias_0init => 3.345e-05,
scope => private
)
port map(
D => out2,
G => net9,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.45e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.45e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 14732ec21926af438887155dcb7692e8 | 0.568746 | 2.841724 | false | false | false | false |
KB777/1541UltimateII | fpga/cpu_unit/mblite/hw/core/execute.vhd | 1 | 11,793 | ----------------------------------------------------------------------------------------------
--
-- Input file : execute.vhd
-- Design name : execute
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The Execution Unit performs all arithmetic operations and makes
-- the branch decision. Furthermore the forwarding logic is located
-- here. Everything is computed within a single clock-cycle
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity execute is generic
(
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
port
(
exec_o : out execute_out_type;
exec_i : in execute_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end execute;
architecture arch of execute is
type execute_reg_type is record
carry : std_logic;
break_in_progress : std_logic;
flush_ex : std_logic;
end record;
signal r, rin : execute_out_type;
signal reg, regin : execute_reg_type;
begin
exec_o <= r;
execute_comb: process(exec_i, r, reg)
variable v : execute_out_type;
variable v_reg : execute_reg_type;
variable alu_src_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable alu_src_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable carry : std_logic;
variable result : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable result_add : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable zero : std_logic;
variable dat_a, dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable sel_dat_a, sel_dat_b, sel_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable special_reg : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
v_reg := reg;
sel_dat_a := select_register_data(exec_i.dat_a, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_a));
sel_dat_b := select_register_data(exec_i.dat_b, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_b));
sel_dat_d := select_register_data(exec_i.dat_d, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.ctrl_wrb.reg_d));
if reg.flush_ex = '1' then
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
v.ctrl_wrb.reg_d := (others => '0');
else
v.ctrl_mem := exec_i.ctrl_mem;
v.ctrl_wrb := exec_i.ctrl_wrb;
if exec_i.ctrl_wrb.reg_d = "00000" then
v.ctrl_wrb.reg_write := '0';
end if;
end if;
if exec_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(exec_i.mem_result, exec_i.ctrl_mem_wrb.transfer_size, exec_i.alu_result(1 downto 0));
else
mem_result := exec_i.alu_result;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_a) = '1' then
-- Forward Execution Result to REG a
dat_a := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_a) = '1' then
-- Forward Memory Result to REG a
dat_a := mem_result;
else
-- DEFAULT: value of REG a
dat_a := sel_dat_a;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_b) = '1' then
-- Forward (latched) Execution Result to REG b
dat_b := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_b) = '1' then
-- Forward Memory Result to REG b
dat_b := mem_result;
else
-- DEFAULT: value of REG b
dat_b := sel_dat_b;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Execution Result to REG d
v.dat_d := align_mem_store(r.alu_result, exec_i.ctrl_mem.transfer_size);
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Memory Result to REG d
v.dat_d := align_mem_store(mem_result, exec_i.ctrl_mem.transfer_size);
else
-- DEFAULT: value of REG d
v.dat_d := align_mem_store(sel_dat_d, exec_i.ctrl_mem.transfer_size);
end if;
-- In case more than just one special register needs to be supported, a multiplexer can be made here. For now, just MSR.
special_reg := (31 => reg.carry,
3 => reg.break_in_progress,
2 => reg.carry,
1 => r.interrupt_enable,
others => '0' );
-- Set the first operand of the ALU
case exec_i.ctrl_ex.alu_src_a is
when ALU_SRC_PC => alu_src_a := sign_extend(exec_i.program_counter, '0', 32);
when ALU_SRC_NOT_REGA => alu_src_a := not dat_a;
when ALU_SRC_SPR => alu_src_a := special_reg;
when others => alu_src_a := dat_a;
end case;
-- Set the second operand of the ALU
case exec_i.ctrl_ex.alu_src_b is
when ALU_SRC_IMM => alu_src_b := exec_i.imm;
when ALU_SRC_NOT_IMM => alu_src_b := not exec_i.imm;
when ALU_SRC_NOT_REGB => alu_src_b := not dat_b;
when others => alu_src_b := dat_b;
end case;
-- Determine value of carry in
case exec_i.ctrl_ex.carry is
when CARRY_ALU => carry := reg.carry;
when CARRY_ONE => carry := '1';
when CARRY_ARITH => carry := alu_src_a(CFG_DMEM_WIDTH - 1);
when others => carry := '0';
end case;
result_add := add(alu_src_a, alu_src_b, carry);
case exec_i.ctrl_ex.alu_op is
when ALU_ADD => result := result_add;
when ALU_OR => result := '0' & (alu_src_a or alu_src_b);
when ALU_AND => result := '0' & (alu_src_a and alu_src_b);
when ALU_XOR => result := '0' & (alu_src_a xor alu_src_b);
when ALU_SHIFT => result := alu_src_a(0) & carry & alu_src_a(CFG_DMEM_WIDTH - 1 downto 1);
when ALU_SEXT8 => result := '0' & sign_extend(alu_src_a(7 downto 0), alu_src_a(7), 32);
when ALU_SEXT16 => result := '0' & sign_extend(alu_src_a(15 downto 0), alu_src_a(15), 32);
when ALU_MUL =>
if G_USE_HW_MUL = true then
result := '0' & multiply(alu_src_a, alu_src_b);
else
result := (others => '0');
end if;
when ALU_BS =>
if G_USE_BARREL = true then
result := '0' & shift(alu_src_a, alu_src_b(4 downto 0), exec_i.imm(10), exec_i.imm(9));
else
result := (others => '0');
end if;
when others =>
result := (others => '0');
report "Invalid ALU operation" severity FAILURE;
end case;
if reg.flush_ex = '0' then
-- Set carry register
if exec_i.ctrl_ex.carry_keep = CARRY_KEEP then
v_reg.carry := reg.carry;
else
v_reg.carry := result(CFG_DMEM_WIDTH);
end if;
-- MSR operations
case exec_i.ctrl_ex.msr_op is
when MSR_SET_I =>
v.interrupt_enable := '1';
when MSR_CLR_I =>
v.interrupt_enable := '0';
when LOAD_MSR =>
v_reg.break_in_progress := dat_a(3);
v_reg.carry := dat_a(2);
v.interrupt_enable := dat_a(1);
when MSR_SET =>
v_reg.break_in_progress := exec_i.imm(3) or reg.break_in_progress;
v_reg.carry := exec_i.imm(2) or reg.carry;
v.interrupt_enable := exec_i.imm(1) or r.interrupt_enable;
when MSR_CLR =>
v_reg.break_in_progress := not exec_i.imm(3) and reg.break_in_progress;
v_reg.carry := not exec_i.imm(2) and reg.carry;
v.interrupt_enable := not exec_i.imm(1) and r.interrupt_enable;
when others =>
null;
end case;
end if;
zero := is_zero(dat_a);
-- Overwrite branch condition
if reg.flush_ex = '1' then
v.branch := '0';
else
-- Determine branch condition
case exec_i.ctrl_ex.branch_cond is
when BNC => v.branch := '1';
when BEQ => v.branch := zero;
when BNE => v.branch := not zero;
when BLT => v.branch := dat_a(CFG_DMEM_WIDTH - 1);
when BLE => v.branch := dat_a(CFG_DMEM_WIDTH - 1) or zero;
when BGT => v.branch := not (dat_a(CFG_DMEM_WIDTH - 1) or zero);
when BGE => v.branch := not dat_a(CFG_DMEM_WIDTH - 1);
when others => v.branch := '0';
end case;
end if;
v.alu_result := result(CFG_DMEM_WIDTH - 1 downto 0);
-- Handle CMPU and CMP
if ( exec_i.ctrl_ex.operation = "11" ) then
v.alu_result(CFG_DMEM_WIDTH - 1) := not result_add(CFG_DMEM_WIDTH); -- unsigned = bit 32 of result
elsif ( exec_i.ctrl_ex.operation = "01" ) then
v.alu_result(CFG_DMEM_WIDTH - 1) := (result_add(CFG_DMEM_WIDTH) xor alu_src_a(CFG_DMEM_WIDTH-1) xor alu_src_b(CFG_DMEM_WIDTH-1)); -- signed
end if;
v.program_counter := exec_i.program_counter;
-- Determine flush signals
v.flush_id := v.branch;
v_reg.flush_ex := v.branch and not exec_i.ctrl_ex.delay;
rin <= v;
regin <= v_reg;
end process;
execute_seq: process(clk_i)
procedure proc_execute_reset is
begin
r.alu_result <= (others => '0');
r.dat_d <= (others => '0');
r.branch <= '0';
r.program_counter <= (others => '0');
r.flush_id <= '0';
r.interrupt_enable <= '0';
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.mem_read <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
reg.carry <= '0';
reg.break_in_progress <= '0';
reg.flush_ex <= '0';
end procedure proc_execute_reset;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_execute_reset;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
end arch;
| gpl-3.0 | 8c6e13d25f3bf725b6c07316bb0f123e | 0.499364 | 3.488021 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/old/final3_logic.vhd | 5 | 3,289 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity final3_logic is
generic (
rom_base : std_logic_vector(27 downto 0) := X"1010000" );
port (
clock : in std_logic;
reset : in std_logic;
RSTn_in : in std_logic;
cart_kill : in std_logic := '0';
freeze_trig : in std_logic;
freeze_act : in std_logic;
unfreeze : out std_logic;
io_write : in std_logic;
io_addr : in std_logic_vector(8 downto 0);
io_data : in std_logic_vector(7 downto 0);
serve_enable : out std_logic; -- enables fetching bus address PHI2=1
serve_vic : out std_logic; -- enables doing so for PHI2=0
serve_rom : out std_logic; -- ROML or ROMH
serve_io1 : out std_logic; -- IO1n
serve_io2 : out std_logic; -- IO2n
allow_write : out std_logic;
slot_addr : in std_logic_vector(15 downto 0);
mem_addr : out std_logic_vector(25 downto 0);
-- debug
cart_mode : out std_logic_vector(7 downto 0);
irq_n : out std_logic;
nmi_n : out std_logic;
exrom_n : out std_logic;
game_n : out std_logic;
CART_LEDn : out std_logic );
end final3_logic;
architecture gideon of final3_logic is
signal cart_ctrl : std_logic_vector(7 downto 0);
signal reset_in : std_logic;
signal cart_en : std_logic;
begin
serve_enable <= cart_en;
process(clock)
begin
if rising_edge(clock) then
reset_in <= not RSTn_in or reset;
cart_en <= not cart_ctrl(7) or freeze_act;
unfreeze <= '0';
-- flipflops
if io_write='1' and io_addr = "111111111" then
cart_ctrl <= io_data;
unfreeze <= freeze_act;
end if;
if cart_kill='1' then
cart_ctrl(7) <= '1';
end if;
if cart_en='1' then
exrom_n <= cart_ctrl(4);
game_n <= cart_ctrl(5) and not freeze_act;
else
game_n <= '1';
exrom_n <= '1';
end if;
-- reset
if reset_in='1' then
cart_ctrl <= X"00"; --(others => '0'); -- fix = X"20" => 8K rom only to test
end if;
end if;
end process;
-- game_n <= '0' when (cart_en='1') and (cnt_q(3)='0' or cart_ctrl(5)='0') else '1';
-- exrom_n <= '0' when (cart_en='1') and (cart_ctrl(4)='0') else '1';
-- open drains
irq_n <= '1';
nmi_n <= not(freeze_trig or freeze_act or not cart_ctrl(6));
mem_addr <= rom_base(25 downto 16) & cart_ctrl(1 downto 0) & slot_addr(13 downto 0);
CART_LEDn <= not cart_en;
cart_mode <= cart_ctrl;
serve_vic <= '1' when cart_ctrl(5 downto 4) = "01" else '0'; -- in Ultimax mode, serve VIC
serve_rom <= '1';
serve_io1 <= '1';
serve_io2 <= '1';
allow_write <= '0';
-- cart_ctrl(3 downto 2) is unused
end gideon;
| gpl-3.0 | 86853e6b1ba709c40979b02fe61e38fc | 0.482822 | 3.322222 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/floppy_sound.vhd | 4 | 6,762 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity floppy_sound is
generic (
g_tag : std_logic_vector(7 downto 0) := X"04";
rate_div : natural := 2176; -- 22050 Hz
sound_base : unsigned(27 downto 16) := X"103";
motor_hum_addr : unsigned(15 downto 0) := X"0000";
flop_slip_addr : unsigned(15 downto 0) := X"1200";
track_in_addr : unsigned(15 downto 0) := X"2400";
track_out_addr : unsigned(15 downto 0) := X"2E00";
head_bang_addr : unsigned(15 downto 0) := X"3800";
motor_len : integer := 4410;
track_in_len : unsigned(15 downto 0) := X"089D"; -- 100 ms;
track_out_len : unsigned(15 downto 0) := X"089D"; -- 100 ms;
head_bang_len : unsigned(15 downto 0) := X"089D" ); -- 100 ms;
port (
clock : in std_logic;
reset : in std_logic;
do_trk_out : in std_logic;
do_trk_in : in std_logic;
do_head_bang : in std_logic;
en_hum : in std_logic;
en_slip : in std_logic;
-- memory interface
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- audio
sample_out : out signed(12 downto 0) := (others => '0'));
end floppy_sound;
architecture gideon of floppy_sound is
signal rate_count : integer range 0 to rate_div;
signal motor_sample : signed(7 downto 0);
signal head_sample : signed(7 downto 0);
signal sample_tick : std_logic;
type t_voice_state is (idle, play);
type t_serve_state is (idle, wait_voice1, serve_voice2, wait_voice2);
signal voice1 : t_voice_state;
signal serve_state : t_serve_state;
signal voice1_cnt : unsigned(13 downto 0); -- max 16K
signal voice1_addr : unsigned(15 downto 0);
signal voice2_cnt : unsigned(13 downto 0); -- max 16K
signal mem_addr_i : unsigned(15 downto 0);
signal mem_rack : std_logic;
signal mem_dack : std_logic;
begin
mem_req.tag <= g_tag;
mem_req.read_writen <= '1'; -- always read
mem_req.address <= sound_base(25 downto 16) & mem_addr_i;
mem_req.data <= X"00";
mem_req.size <= "00"; -- 1 byte at a time
mem_rack <= '1' when mem_resp.rack_tag = g_tag else '0';
mem_dack <= '1' when mem_resp.dack_tag = g_tag else '0';
process(clock)
variable signed_sum : signed(12 downto 0);
begin
if rising_edge(clock) then
sample_tick <= '0';
if rate_count = 0 then
signed_sum := motor_sample + (head_sample(head_sample'high) & head_sample & "0000");
sample_out <= signed_sum;
rate_count <= rate_div;
sample_tick <= '1';
else
rate_count <= rate_count - 1;
end if;
case serve_state is
when idle =>
if sample_tick='1' then
case voice1 is
when play =>
if voice1_cnt = 0 then
voice1 <= idle;
else
mem_req.request <= '1';
mem_addr_i <= voice1_addr;
serve_state <= wait_voice1;
end if;
when others =>
head_sample <= X"00";
serve_state <= serve_voice2;
end case;
end if;
when wait_voice1 =>
if mem_rack='1' then
mem_req.request <= '0';
end if;
if mem_dack='1' then
head_sample <= signed(mem_resp.data);
voice1_cnt <= voice1_cnt - 1;
voice1_addr <= voice1_addr + 1;
serve_state <= serve_voice2;
end if;
when serve_voice2 =>
if en_hum = '1' then
mem_req.request <= '1';
mem_addr_i <= motor_hum_addr(15 downto 0) + ("00" & voice2_cnt);
serve_state <= wait_voice2;
elsif en_slip = '1' then
mem_req.request <= '1';
mem_addr_i <= flop_slip_addr(15 downto 0) + ("00" & voice2_cnt);
serve_state <= wait_voice2;
else
serve_state <= idle;
-- if motor_sample(7)='1' then
-- motor_sample <= motor_sample + 1; -- is negative, go to zero
-- elsif motor_sample /= 0 then
-- motor_sample <= motor_sample - 1;
-- end if;
end if;
when wait_voice2 =>
if mem_rack='1' then
mem_req.request <= '0';
end if;
if mem_dack='1' then
motor_sample <= signed(mem_resp.data);
if voice2_cnt = motor_len-1 then
voice2_cnt <= (others => '0');
else
voice2_cnt <= voice2_cnt + 1;
end if;
serve_state <= idle;
end if;
when others =>
null;
end case;
if do_trk_out = '1' then
voice1 <= play;
voice1_cnt <= track_out_len(voice1_cnt'range);
voice1_addr <= track_out_addr(voice1_addr'range);
end if;
if do_trk_in = '1' then
voice1 <= play;
voice1_cnt <= track_in_len(voice1_cnt'range);
voice1_addr <= track_in_addr(voice1_addr'range);
end if;
if do_head_bang = '1' then
voice1 <= play;
voice1_cnt <= head_bang_len(voice1_cnt'range);
voice1_addr <= head_bang_addr(voice1_addr'range);
end if;
if reset='1' then
mem_req.request <= '0';
serve_state <= idle;
voice1 <= idle;
voice1_cnt <= (others => '0');
voice2_cnt <= (others => '0');
voice1_addr <= (others => '0');
sample_out <= (others => '0');
motor_sample <= (others => '0');
end if;
end if;
end process;
end gideon;
| gpl-3.0 | e8386a4542a2c78bf88bd565a8966b03 | 0.435078 | 3.881745 | false | false | false | false |
KB777/1541UltimateII | fpga/io/iec_interface/vhdl_source/iec_processor_io.vhd | 1 | 9,029 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 260/111/136/1
library work;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity iec_processor_io is
generic (
g_mhz : natural := 50);
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
irq : out std_logic;
clk_o : out std_logic;
clk_i : in std_logic;
data_o : out std_logic;
data_i : in std_logic;
atn_o : out std_logic;
atn_i : in std_logic;
srq_o : out std_logic;
srq_i : in std_logic );
end iec_processor_io;
architecture structural of iec_processor_io is
signal proc_reset : std_logic;
signal enable : std_logic;
-- irq
signal irq_event : std_logic;
signal irq_enable : std_logic;
signal irq_status : std_logic;
-- instruction ram interface
signal instr_addr : unsigned(8 downto 0);
signal instr_en : std_logic;
signal instr_data : std_logic_vector(31 downto 0);
-- software fifo interface
signal up_fifo_get : std_logic;
signal up_fifo_put : std_logic;
signal up_fifo_din : std_logic_vector(8 downto 0);
signal up_fifo_dout : std_logic_vector(8 downto 0);
signal up_fifo_empty : std_logic;
signal up_fifo_full : std_logic;
signal up_dav : std_logic;
signal up_space : std_logic;
signal down_fifo_flush : std_logic;
signal down_fifo_empty : std_logic;
signal down_fifo_full : std_logic;
signal down_fifo_get : std_logic;
signal down_fifo_put : std_logic;
signal down_fifo_din : std_logic_vector(8 downto 0);
signal down_fifo_dout : std_logic_vector(8 downto 0);
signal down_dav : std_logic;
signal down_space : std_logic;
signal ram_en : std_logic;
signal ram_rdata : std_logic_vector(7 downto 0);
signal ram_sel : std_logic;
signal reg_rdata : std_logic_vector(7 downto 0);
begin
i_proc: entity work.iec_processor
generic map (
g_mhz => g_mhz )
port map (
clock => clock,
reset => proc_reset,
-- instruction ram interface
instr_addr => instr_addr,
instr_en => instr_en,
instr_data => instr_data(29 downto 0),
-- software fifo interface
up_fifo_put => up_fifo_put,
up_fifo_din => up_fifo_din,
up_fifo_full => up_fifo_full,
down_fifo_empty => down_fifo_empty,
down_fifo_get => down_fifo_get,
down_fifo_dout => down_fifo_dout,
down_fifo_flush => down_fifo_flush,
irq_event => irq_event,
clk_o => clk_o,
clk_i => clk_i,
data_o => data_o,
data_i => data_i,
atn_o => atn_o,
atn_i => atn_i,
srq_o => srq_o,
srq_i => srq_i );
i_ram: RAMB16_S9_S36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST" )
port map (
DOA => ram_rdata,
ADDRA => std_logic_vector(req.address(10 downto 0)),
CLKA => clock,
DIA => req.data,
DIPA => "0",
ENA => ram_en,
SSRA => '0',
WEA => req.write,
DOB(31 downto 24) => instr_data(7 downto 0), -- CPU is big endian
DOB(23 downto 16) => instr_data(15 downto 8),
DOB(15 downto 8) => instr_data(23 downto 16),
DOB(7 downto 0) => instr_data(31 downto 24),
ADDRB => std_logic_vector(instr_addr),
CLKB => clock,
DIB => X"00000000",
DIPB => X"0",
ENB => instr_en,
SSRB => '0',
WEB => '0' );
-- i_up_fifo: entity work.srl_fifo
-- generic map (
-- Width => 9,
-- Depth => 15, -- 15 is the maximum
-- Threshold => 13 )
-- port map (
-- clock => clock,
-- reset => reset,
-- GetElement => up_fifo_get,
-- PutElement => up_fifo_put,
-- FlushFifo => '0',
-- DataIn => up_fifo_din,
-- DataOut => up_fifo_dout,
-- SpaceInFifo => up_space,
-- AlmostFull => open,
-- DataInFifo => up_dav);
--
-- up_fifo_empty <= not up_dav;
-- up_fifo_full <= not up_space;
i_up_fifo: entity work.sync_fifo
generic map (
g_depth => 2048,
g_data_width => 9,
g_threshold => 500,
g_storage => "blockram", -- can also be "blockram" or "distributed"
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => up_fifo_get,
wr_en => up_fifo_put,
din => up_fifo_din,
dout => up_fifo_dout,
flush => '0',
full => up_fifo_full,
almost_full => open,
empty => up_fifo_empty,
count => open );
i_down_fifo: entity work.srl_fifo
generic map (
Width => 9,
Depth => 15, -- 15 is the maximum
Threshold => 13 )
port map (
clock => clock,
reset => reset,
GetElement => down_fifo_get,
PutElement => down_fifo_put,
FlushFifo => down_fifo_flush,
DataIn => down_fifo_din,
DataOut => down_fifo_dout,
SpaceInFifo => down_space,
AlmostFull => open,
DataInFifo => down_dav);
down_fifo_empty <= not down_dav;
down_fifo_full <= not down_space;
process(clock)
begin
if rising_edge(clock) then
ram_sel <= '0';
reg_rdata <= (others => '0');
proc_reset <= not enable;
resp.ack <= '0';
if req.read='1' then
resp.ack <= '1'; -- data handled outside clocked process if ram
ram_sel <= req.address(11);
case req.address(3 downto 0) is
when X"0" =>
reg_rdata <= X"23"; -- version
when X"1" =>
reg_rdata(0) <= down_fifo_empty;
reg_rdata(1) <= down_fifo_full;
when X"2" =>
reg_rdata(0) <= up_fifo_empty;
reg_rdata(1) <= up_fifo_full;
reg_rdata(7) <= up_fifo_dout(8);
when X"6"|X"8"|X"9"|X"A"|X"B" =>
reg_rdata <= up_fifo_dout(7 downto 0);
when X"7" =>
reg_rdata <= "0000000" & up_fifo_dout(8);
when X"C" =>
reg_rdata <= "0000000" & irq_status;
when others => null;
end case;
elsif req.write='1' then
resp.ack <= '1'; -- data handled outside clocked process if ram
if req.address(11)='0' then
case req.address(3 downto 0) is
when X"3" =>
proc_reset <= '1';
enable <= req.data(0);
when X"C" =>
irq_status <= '0';
irq_enable <= req.data(0);
when others =>
null;
end case;
end if;
end if;
if irq_event='1' then
irq_status <= '1';
end if;
irq <= irq_enable and irq_status;
if reset='1' then
proc_reset <= '1';
enable <= '0';
end if;
end if;
end process;
resp.data <= ram_rdata when ram_sel='1' else reg_rdata;
down_fifo_put <= '1' when req.write='1' and req.address(11)='0' and req.address(3 downto 1) = "10" else '0';
up_fifo_get <= '1' when req.read='1' and req.address(11)='0' and ((req.address(3 downto 0) = "0110") or (req.address(3 downto 2) = "10")) else '0';
down_fifo_din <= req.address(0) & req.data;
ram_en <= (req.write or req.read) and req.address(11);
end structural;
| gpl-3.0 | 0f87d17988bcac7286bc7b10d4a8e37f | 0.433492 | 3.784158 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/coregen/fifo_xlnx_512x36_2clk.vhd | 2 | 5,890 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_xlnx_512x36_2clk.vhd when simulating
-- the core, fifo_xlnx_512x36_2clk. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_xlnx_512x36_2clk IS
port (
din: IN std_logic_VECTOR(35 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(35 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
rd_data_count: OUT std_logic_VECTOR(8 downto 0);
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
END fifo_xlnx_512x36_2clk;
ARCHITECTURE fifo_xlnx_512x36_2clk_a OF fifo_xlnx_512x36_2clk IS
-- synthesis translate_off
component wrapped_fifo_xlnx_512x36_2clk
port (
din: IN std_logic_VECTOR(35 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(35 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
rd_data_count: OUT std_logic_VECTOR(8 downto 0);
wr_data_count: OUT std_logic_VECTOR(8 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_xlnx_512x36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral)
generic map(
c_has_int_clk => 0,
c_rd_freq => 1,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 1,
c_din_width => 36,
c_has_wr_data_count => 1,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 0,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 0,
c_dout_width => 36,
c_msgon_val => 1,
c_rd_depth => 512,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 9,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 9,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 9,
c_enable_rlocs => 0,
c_wr_pntr_width => 9,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 9,
c_preload_regs => 1,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 510,
c_wr_depth => 512,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_thresh_assert_val => 4,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 511,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_xlnx_512x36_2clk
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count);
-- synthesis translate_on
END fifo_xlnx_512x36_2clk_a;
| gpl-2.0 | 076f45f5ddf38356014bae7efc280757 | 0.570628 | 3.359954 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/spike_filter/vhdl_source/spike_filter.vhd | 5 | 971 | library ieee;
use ieee.std_logic_1164.all;
entity spike_filter is
generic (
g_stable_time : integer := 8 );
port (
clock : in std_logic;
pin_in : in std_logic;
pin_out : out std_logic := '1' );
end spike_filter;
architecture gideon of spike_filter is
signal pin_c : std_logic;
signal cnt : integer range 0 to g_stable_time-1 := (g_stable_time-1) / 2;
begin
process(clock)
begin
if rising_edge(clock) then
pin_c <= pin_in;
if pin_c='0' then
if cnt = 0 then
pin_out <= '0';
else
cnt <= cnt - 1;
end if;
else
if cnt = g_stable_time-1 then
pin_out <= '1';
else
cnt <= cnt + 1;
end if;
end if;
end if;
end process;
end gideon;
| gpl-3.0 | 446aa51c19c1e72ed79398a2ba342342 | 0.429454 | 3.822835 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/iec_interface/vhdl_source/iec_interface_io.vhd | 5 | 14,603 | -------------------------------------------------------------------------------
-- Title : IEC Interface
-------------------------------------------------------------------------------
-- File : iec_interface.vhd
-- Created : 2008-01-17
-- Last update: 2008-01-17
-------------------------------------------------------------------------------
-- Description: This module implements a simple IEC transceiver.
-------------------------------------------------------------------------------
-- LUT/FF/S3S/BRAM: 238/ 85/126/0 (not programmable)
-- LUT/FF/S3S/BRAM: 279/104/148/0 (programmable)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity iec_interface_io is
generic (
g_state_readback : boolean := false;
programmable_timing : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
iec_atn_i : in std_logic;
iec_atn_o : out std_logic;
iec_clk_i : in std_logic;
iec_clk_o : out std_logic;
iec_data_i : in std_logic;
iec_data_o : out std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
-- debug
iec_state : out std_logic_vector(3 downto 0);
iec_dbg : out std_logic_vector(1 downto 0) );
-- end debug
end iec_interface_io;
architecture erno of iec_interface_io is
signal bit_cnt : integer range 0 to 8;
signal data_reg : std_logic_vector(7 downto 0);
signal send_data : std_logic_vector(7 downto 0);
signal delay : integer range 0 to 255;
signal clk_d : std_logic;
signal atn_d : std_logic;
constant c_div : integer := 250;
signal timer_div : integer range 0 to c_div-1 := 0;
signal timer_tick : std_logic := '0';
signal flag_eoi : std_logic;
signal flag_atn : std_logic;
signal flag_data_av : std_logic;
signal flag_clr2send : std_logic;
signal flag_byte_sent: std_logic;
signal ctrl_data_av : std_logic;
signal ctrl_nodata : std_logic;
signal ctrl_talker : std_logic;
signal ctrl_listener : std_logic;
signal ctrl_eoi : std_logic;
signal ctrl_swready : std_logic;
signal ctrl_swreset : std_logic;
signal ctrl_killed : std_logic;
signal ctrl_address : std_logic_vector(4 downto 0);
signal clk_edge_seen : std_logic;
signal clk_edge_d : std_logic := '1';
signal atn_edge_d : std_logic := '1';
type t_state is ( idle, prep_recv, reoi_chk, reoi_ack, recv, rack_wait4sw, prep_talk, turn_around,
wait4listener, teoi, teoi_ack, trans1, trans2, twait4ack, sw_byte, ack_byte, prep_atn);
signal state : t_state;
signal time1 : std_logic_vector(5 downto 0) := "010100";
signal time2 : std_logic_vector(5 downto 0) := "010100";
signal time3 : std_logic_vector(5 downto 0) := "010100";
signal time4 : std_logic_vector(5 downto 0) := "010100";
-- comment these two lines when done
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
signal encoded_state : std_logic_vector(3 downto 0) := X"0";
begin
process(clock)
procedure continue_next is
begin
if ctrl_talker = '1' and iec_atn_i = '1' and iec_clk_i = '1' then
iec_clk_o <= '0';
iec_data_o <= '1';
state <= prep_talk;
elsif iec_atn_i = '0' then
state <= prep_recv;
elsif ctrl_listener = '1' and flag_eoi='0' then
state <= prep_recv;
else
state <= idle;
end if;
end procedure continue_next;
begin
if rising_edge(clock) then
if timer_div = 0 then
timer_div <= c_div - 1;
timer_tick <= '1';
else
timer_div <= timer_div - 1;
timer_tick <= '0';
end if;
atn_d <= iec_atn_i;
clk_d <= iec_clk_i;
flag_clr2send <= '0';
if delay /= 0 and timer_tick = '1' then
delay <= delay - 1;
end if;
if iec_clk_i='1' and clk_d='0' then
clk_edge_seen <= '1';
end if;
case state is
when idle =>
iec_data_o <= '1';
iec_clk_o <= '1';
when prep_recv =>
if clk_edge_seen = '1' and ctrl_swready='1' then
iec_data_o <= '1';
delay <= 40;
bit_cnt <= 8;
flag_eoi <= '0';
state <= reoi_chk;
elsif ctrl_talker = '1' and iec_atn_i = '1' then
iec_data_o <= '1';
state <= turn_around;
elsif ctrl_talker = '0' and ctrl_listener = '0' and iec_atn_i = '1' then
state <= idle;
end if;
when reoi_chk =>
if iec_clk_i = '0' then
flag_atn <= not iec_atn_i;
state <= recv;
elsif delay = 0 then
iec_data_o <= '0';
delay <= 20;
flag_eoi <= '1';
state <= reoi_ack;
end if;
when reoi_ack =>
if iec_clk_i = '0' then
iec_data_o <= '1';
flag_atn <= not iec_atn_i;
state <= recv;
elsif delay = 0 then
iec_data_o <= '1';
end if;
when recv =>
if iec_clk_i='1' and clk_d='0' then
bit_cnt <= bit_cnt - 1;
data_reg <= iec_data_i & data_reg(7 downto 1);
end if;
if iec_clk_i='0' and bit_cnt = 0 then -- end of transfer
delay <= 20;
if flag_atn='1' then
if data_reg(7 downto 5)="001" then -- listen
ctrl_talker <= '0';
ctrl_listener <= '0';
if data_reg(4 downto 0) = ctrl_address then
ctrl_listener <= '1';
state <= ack_byte;
end if;
elsif data_reg(7 downto 5)="010" then -- talk
ctrl_talker <= '0';
ctrl_listener <= '0';
if data_reg(4 downto 0) = ctrl_address then
ctrl_talker <= '1';
state <= ack_byte;
end if;
elsif ctrl_talker='1' or ctrl_listener='1' then -- other atn byte
state <= sw_byte;
else
state <= idle;
end if;
else -- byte without atn.. we can only be here if we were listener!
state <= sw_byte;
end if;
end if;
when ack_byte =>
iec_data_o <= '0';
clk_edge_seen <= '0';
if delay=0 then
continue_next;
end if;
when sw_byte =>
iec_data_o <= '0';
flag_data_av <= '1';
ctrl_swready <= '0';
clk_edge_seen <= '0';
state <= rack_wait4sw;
when rack_wait4sw =>
if ctrl_swready = '1' then
continue_next;
end if;
when prep_talk =>
flag_clr2send <= '1';
if ctrl_data_av = '1' and delay = 0 then
data_reg <= send_data; -- copy
flag_byte_sent <= '0';
iec_clk_o <= '1';
bit_cnt <= 8;
state <= wait4listener;
end if;
when wait4listener =>
if iec_data_i = '1' then
if ctrl_eoi = '1' then
state <= teoi;
else
iec_clk_o <= '0';
iec_data_o <= data_reg(0);
delay <= to_integer(unsigned(time1));
state <= trans1;
end if;
end if;
when teoi =>
if iec_data_i = '0' then
state <= teoi_ack;
end if;
when teoi_ack =>
if ctrl_nodata = '1' then
state <= idle;
elsif iec_data_i = '1' then
iec_clk_o <= '0';
iec_data_o <= data_reg(0);
delay <= to_integer(unsigned(time1));
state <= trans1;
end if;
when trans1 =>
if delay = 0 then
iec_clk_o <= '1';
data_reg <= '1' & data_reg(7 downto 1);
delay <= to_integer(unsigned(time2));
state <= trans2;
end if;
when trans2 =>
if delay = 0 then
iec_data_o <= data_reg(0);
iec_clk_o <= '0';
if bit_cnt = 1 then
state <= twait4ack;
else
bit_cnt <= bit_cnt - 1;
delay <= to_integer(unsigned(time3));
state <= trans1;
end if;
end if;
when twait4ack =>
if iec_data_i = '0' and timer_tick='1' then
ctrl_data_av <= '0';
flag_byte_sent <= '1';
if ctrl_eoi = '0' then
state <= prep_talk;
else
state <= idle;
ctrl_talker <= '0';
end if;
end if;
when turn_around =>
if iec_clk_i='1' then
iec_clk_o <= '0';
delay <= 20;
state <= prep_talk;
end if;
when prep_atn =>
if timer_tick='1' then
clk_edge_seen <= '0';
state <= prep_recv;
end if;
when others =>
null;
end case;
if ctrl_killed = '0' then
if iec_atn_i = '0' and atn_d = '1' then -- falling edge attention
iec_data_o <= '0';
iec_clk_o <= '1';
ctrl_data_av <= '0';
clk_edge_seen <= '0';
if timer_tick='0' then
atn_d <= '1'; -- delay edge detection until clock is also seen high
else
state <= prep_atn;
end if;
end if;
end if;
-- BUS INTERFACE
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
if io_req.address(2)='0' then
case io_req.address(1 downto 0) is
when "00" =>
send_data <= io_req.data;
when "01" =>
if io_req.data(7)='1' then
flag_data_av <= '0';
end if;
ctrl_swready <= io_req.data(7);
ctrl_nodata <= io_req.data(6);
-- ctrl_talker <= io_req.data(5);
-- ctrl_listener <= io_req.data(4);
ctrl_data_av <= io_req.data(3);
ctrl_swreset <= io_req.data(2);
ctrl_killed <= io_req.data(1);
ctrl_eoi <= io_req.data(0);
when "10" =>
ctrl_address <= io_req.data(4 downto 0);
when others =>
null;
end case;
elsif programmable_timing then -- note: cpu_addr(2) = '1'
case io_req.address(1 downto 0) is
when "00" =>
time1 <= io_req.data(5 downto 0);
when "01" =>
time2 <= io_req.data(5 downto 0);
when "10" =>
time3 <= io_req.data(5 downto 0);
when "11" =>
time4 <= io_req.data(5 downto 0);
when others =>
null;
end case;
end if;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(1 downto 0) is
when "00" =>
io_resp.data <= data_reg;
when "01" =>
io_resp.data(7) <= flag_data_av;
io_resp.data(1) <= flag_atn;
io_resp.data(5) <= ctrl_talker;
io_resp.data(4) <= ctrl_listener;
io_resp.data(3) <= flag_clr2send;
io_resp.data(2) <= flag_byte_sent;
io_resp.data(0) <= flag_eoi;
when "11" =>
io_resp.data(3 downto 0) <= encoded_state;
when others =>
null;
end case;
end if;
if reset='1' or ctrl_swreset='1' then
state <= idle;
iec_data_o <= '1';
iec_clk_o <= '1';
clk_edge_seen <= '0';
flag_eoi <= '0';
flag_atn <= '0';
flag_data_av <= '0';
flag_clr2send <= '0';
flag_byte_sent <= '0';
ctrl_swreset <= '0';
ctrl_swready <= '0';
ctrl_data_av <= '0';
ctrl_nodata <= '0';
ctrl_talker <= '0';
ctrl_listener <= '0';
ctrl_eoi <= '0';
ctrl_killed <= '1';
ctrl_address <= "01001"; -- 9
end if;
end if;
end process;
r_state: if g_state_readback generate
with state select encoded_state <=
X"0" when idle,
X"1" when prep_recv,
X"2" when reoi_chk,
X"3" when reoi_ack,
X"4" when recv,
X"5" when rack_wait4sw,
X"6" when prep_talk,
X"7" when wait4listener,
X"8" when teoi,
X"9" when teoi_ack,
X"A" when trans1,
X"B" when trans2,
X"C" when twait4ack,
X"D" when sw_byte,
X"E" when ack_byte,
X"F" when others;
end generate;
iec_atn_o <= '1';
iec_state <= encoded_state;
iec_dbg(0) <= ctrl_data_av;
iec_dbg(1) <= ctrl_swready;
end erno;
| gpl-3.0 | 1b1d3786a355fb0adb7a776a56362761 | 0.405465 | 3.636205 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_source/pkg_6502_decode.vhd | 3 | 9,508 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean;
function is_illegal(inst: std_logic_vector(7 downto 0)) return boolean;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector;
constant c_stack_idx_brk : std_logic_vector(1 downto 0) := "00";
constant c_stack_idx_jsr : std_logic_vector(1 downto 0) := "01";
constant c_stack_idx_rti : std_logic_vector(1 downto 0) := "10";
constant c_stack_idx_rts : std_logic_vector(1 downto 0) := "11";
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean;
end;
package body pkg_6502_decode is
function is_absolute(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X11X | 1101
if inst(3 downto 2)="11" then
return true;
elsif inst(4 downto 2)="110" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(7 downto 6)="01" and inst(3 downto 0)=X"C";
end function;
function is_immediate(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210 = 1XX000X0
if inst(7)='1' and inst(4 downto 2)="000" and inst(0)='0' then
return true;
-- 76543210 = XXX010X1
elsif inst(4 downto 2)="010" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_implied(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 4320 = X100
return inst(3 downto 2)="10" and inst(0)='0';
end function;
function is_stack(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 76543210
-- 0xx0x000
return inst(7)='0' and inst(4)='0' and inst(2 downto 0)="000";
end function;
function is_push(inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- we already know it's a stack operation, so only the direction is important
return inst(5)='0';
end function;
function is_zeropage(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(3 downto 2)="01" then
return true;
elsif inst(3 downto 2)="00" and inst(0)='1' then
return true;
end if;
return false;
end function;
function is_indirect(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(3 downto 2)="00" and inst(0)='1');
end function;
function is_relative(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(4 downto 0)="10000");
end function;
function is_store(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst(7 downto 5)="100");
end function;
function is_shift(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7)='1' and inst(4 downto 2)="010" then
return false;
end if;
return (inst(1)='1');
end function;
function is_alu(inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(7)='0' and inst(4 downto 1)="0101" then
return false;
end if;
return (inst(0)='1');
end function;
function is_load(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return not is_store(inst) and not is_rmw(inst);
end function;
function is_rmw(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(1)='1' and inst(7 downto 6)/="10";
end function;
function is_abs_jump(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return is_jump(inst) and inst(5)='0';
end function;
function is_postindexed(inst: std_logic_vector(7 downto 0)) return boolean is
begin
return inst(4)='1';
end function;
function stack_idx(inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
return inst(6 downto 5);
end function;
function select_index_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
if inst(4)='1' and inst(2)='0' and inst(0)='1' then -- XXX1X0X1
return true;
elsif inst(7 downto 6)="10" and inst(2 downto 1)="11" then -- 10XXX11X
return true;
end if;
return false;
end function;
-- function flags_bit_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(2 downto 0)="100";
-- end function;
--
-- function flags_alu_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(1 downto 0)="01"; -- could also choose not to look at bit 1 (overlap)
-- end function;
--
-- function flags_shift_group (inst: std_logic_vector(7 downto 0)) return boolean is
-- begin
-- return inst(1 downto 0)="10"; -- could also choose not to look at bit 0 (overlap)
-- end function;
function load_a (inst: std_logic_vector(7 downto 0)) return boolean is
begin
return (inst = X"68");
end function;
function store_a_from_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 0XXXXXX1 or alu operations "lo"
-- 1X100001 or alu operations "hi" (except store and cmp)
-- 0XX01010 (implied)
return (inst(7)='0' and inst(4 downto 0)="01010") or
(inst(7)='0' and inst(0)='1') or
(inst(7)='1' and inst(0)='1' and inst(5)='1');
end function;
function load_x (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX1X or 1100101- (for SAX #)
if inst(7 downto 1)="1100101" then
return true;
end if;
return inst(7 downto 5)="101" and inst(1)='1' and not is_implied(inst);
end function;
function load_y (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 101XXX00
return inst(7 downto 5)="101" and inst(1 downto 0)="00" and not is_implied(inst);
end function;
function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
begin
-- 00 = none, 01 = memory, 10 = A, 11 = A & M
if inst(4 downto 2)="010" and inst(7)='0' then
return inst(1 downto 0);
end if;
return "01";
end function;
-- function shifter_in_select (inst: std_logic_vector(7 downto 0)) return std_logic_vector is
-- begin
-- -- 0=memory, 1=A
-- if inst(4 downto 1)="0101" and inst(7)='0' then
-- return "01";
-- end if;
-- return "10";
-- end function;
function is_illegal (inst: std_logic_vector(7 downto 0)) return boolean is
type t_my16bit_array is array(natural range <>) of std_logic_vector(15 downto 0);
constant c_illegal_map : t_my16bit_array(0 to 15) := (
X"989C", X"9C9C", X"888C", X"9C9C", X"889C", X"9C9C", X"889C", X"9C9C",
X"8A8D", X"D88C", X"8888", X"888C", X"888C", X"9C9C", X"888C", X"9C9C" );
variable row : std_logic_vector(15 downto 0);
begin
row := c_illegal_map(conv_integer(inst(7 downto 4)));
return (row(conv_integer(inst(3 downto 0))) = '1');
end function;
function x_to_alu (inst: std_logic_vector(7 downto 0)) return boolean is
begin
-- 1-00101- 8A,8B,CA,CB
return inst(5 downto 1)="00101" and inst(7)='1';
end function;
end;
| gpl-3.0 | 6ee9afd81ed6385e5914b1c153d38896 | 0.609487 | 3.508487 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_sim/tb_floppy.vhd | 5 | 5,528 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : tb_floppy_stream.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.floppy_emu_pkg.all;
use work.flat_memory_model.all;
entity tb_floppy is
end tb_floppy;
architecture tb of tb_floppy is
signal clock : std_logic := '0';
signal clock_en : std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
signal reset : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal track : std_logic_vector(6 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal read_data : std_logic_vector(7 downto 0);
signal write_data : std_logic_vector(7 downto 0) := X"55";
---
signal mem_clock : std_logic := '0';
signal mem_req : std_logic;
signal mem_rwn : std_logic;
signal mem_rack : std_logic := '0';
signal mem_dack : std_logic := '0';
signal mem_addr : std_logic_vector(31 downto 0) := (others => '0');
signal mem_wdata : std_logic_vector(7 downto 0);
signal mem_rdata : std_logic_vector(7 downto 0) := X"00";
type t_integer_array is array (natural range <>) of integer;
constant rate_table : t_integer_array(0 to 63) := (
3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
2, 2, 2, 2, 2, 2, 2,
1, 1, 1, 1, 1, 1,
0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 );
begin
clock <= not clock after 31.25 ns;
reset <= '1', '0' after 400 ns;
mem_clock <= not mem_clock after 100 ns; -- 5 Mhz
process
begin
wait until clock='1';
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
end process;
mut: entity work.floppy
port map (
drv_clock => clock,
drv_clock_en => clock_en, -- combi clk/cke that yields 4 MHz; eg. 16/4
drv_reset => reset,
motor_on => motor_on,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
soe => soe,
rate_ctrl => rate_ctrl,
write_data => write_data,
read_data => read_data,
track => track,
mem_clock => mem_clock,
mem_reset => reset,
mem_req => mem_req,
mem_rwn => mem_rwn,
mem_rack => mem_rack,
mem_dack => mem_dack,
mem_addr => mem_addr(19 downto 0), -- 1MB
mem_wdata => mem_wdata,
mem_rdata => mem_rdata );
test: process
begin
motor_on <= '1';
mode <= '1';
write_prot_n <= '1';
soe <= '1';
wait for 700 us;
wait until byte_ready='0';
wait for 10 us;
mode <= '0'; -- switch to write
for i in 0 to 255 loop
wait until byte_ready='0';
wait for 10 us;
write_data <= write_data + 1;
end loop;
wait until byte_ready='0';
mode <= '1';
wait;
end process;
move: process
begin
wait for 2 us;
for i in 0 to 100 loop
step <= step + 1;
wait for 2 us;
end loop;
wait for 2 us;
for i in 0 to 100 loop
step <= step - 1;
wait for 2 us;
end loop;
wait;
end process;
rate_ctrl <= conv_std_logic_vector(rate_table(conv_integer(track(6 downto 1))), 2);
memory: process
variable h : h_mem_object;
begin
register_mem_model("my memory", h);
for i in 0 to 15 loop
write_memory_32(h, conv_std_logic_vector(i*4, 32), X"FFFFFFFF");
end loop;
while true loop
wait until mem_clock='1';
if mem_req='1' then
wait until mem_clock='1';
wait until mem_clock='1';
wait until mem_clock='1';
if mem_rwn='0' then -- write
write_memory_8(h, mem_addr, mem_wdata);
mem_ack <= '1';
wait until mem_clock='1';
mem_ack <= '0';
else
mem_rdata <= read_memory_8(h, mem_addr);
mem_ack <= '1';
wait until mem_clock='1';
mem_ack <= '0';
mem_rdata <= X"00";
end if;
end if;
end loop;
end process;
end tb; | gpl-3.0 | 6ced50d1c509d7f20c6c79a1c59f5528 | 0.453871 | 3.571059 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb/vhdl_source/usb1_ulpi_tx.vhd | 2 | 8,747 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb1_ulpi_tx is
port (
clock : in std_logic;
reset : in std_logic;
-- Bus Interface
tx_start : out std_logic;
tx_last : out std_logic;
tx_valid : out std_logic;
tx_next : in std_logic;
tx_data : out std_logic_vector(7 downto 0);
-- Status
status : in std_logic_vector(7 downto 0);
speed : in std_logic_vector(1 downto 0);
busy : out std_logic;
tx_ack : out std_logic;
-- Interface to send tokens and handshakes
send_token : in std_logic;
send_handsh : in std_logic;
pid : in std_logic_vector(3 downto 0);
token : in std_logic_vector(10 downto 0);
-- Interface to send data packets
send_data : in std_logic;
no_data : in std_logic := '0';
user_data : in std_logic_vector(7 downto 0);
user_last : in std_logic;
user_next : out std_logic;
-- Interface to output reset packets
send_reset_data : in std_logic;
reset_last : in std_logic;
reset_data : in std_logic );
end usb1_ulpi_tx;
architecture gideon of usb1_ulpi_tx is
type t_state is (idle, crc_1, crc_2, token1, token2, token3,
reset_pkt, transmit,
wait4next, write_end, handshake, gap, gap2);
signal state : t_state;
-- type t_tx_type is (none, dat, hsh, tok);
-- signal tx_type : t_tx_type := none;
signal j_state : std_logic_vector(1 downto 0);
signal tx_data_i : std_logic_vector(7 downto 0);
signal tx_last_i : std_logic;
signal token_crc : std_logic_vector(4 downto 0);
signal crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
signal no_data_d : std_logic;
constant c_gap_val : integer := 15;
signal gap_count : integer range 0 to 15;
-- XILINX USB STICK:
-- On high speed, gap values 0x05 - 0x25 WORK.. (bigger than 0x25 doesn't, smaller than 0x05 doesn't..)
-- TRUST USB 2.0 Hub:
-- On high speed, gap values 0x07 - 0x1D WORK.. with the exception of 0x09.
-- Samsung DVD-Burner:
-- On high speed, gap values 0x00 - 0x23 WORK.. with the exception of 0x04.
-- Western Digital external HD:
-- On high speed, gap values 0x05 - 0x21 WORK.. with the exception of 0x06 and 0x09.
--
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "sequential";
begin
tx_ack <= (send_token or send_handsh or send_data) when
(state = idle) else '0';
j_state <= not speed(0) & speed(0);
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
tx_data_i <= X"00";
no_data_d <= no_data;
if send_token='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & pid;
state <= token1;
elsif send_handsh='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & pid;
tx_last_i <= '1';
state <= handshake;
elsif send_data='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & pid;
state <= wait4next;
elsif send_reset_data='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"40"; -- pidless
state <= reset_pkt;
end if;
when wait4next =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '1';
if no_data_d='1' then
state <= crc_1;
else
state <= transmit;
end if;
end if;
when handshake =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
state <= gap;
end if;
when write_end =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
state <= idle;
end if;
when crc_1 =>
if tx_next = '1' then
tx_last_i <= '1';
state <= crc_2;
end if;
when crc_2 =>
if tx_next = '1' then
tx_last_i <= '0';
tx_valid <= '0';
state <= gap;
end if;
when token1 =>
if tx_next = '1' then
tx_start <= '0';
tx_data_i <= token(7 downto 0);
state <= token2;
end if;
when token2 =>
if tx_next = '1' then
tx_data_i <= token_crc & token(10 downto 8);
tx_last_i <= '1';
state <= token3;
end if;
when token3 =>
if tx_next = '1' then
tx_last_i <= '0';
tx_valid <= '0';
state <= gap;
end if;
when gap =>
gap_count <= c_gap_val;
if speed(1)='0' then
if status(1 downto 0)="00" or status(1 downto 0)="11" then --<-- :-o SE1 in low speed?!
state <= gap2;
end if;
else -- high speed
state <= gap2;
end if;
when gap2 =>
if speed(1)='0' then
if status(1 downto 0) = j_state then
state <= idle;
end if;
else
if gap_count = 0 then
state <= idle;
else
gap_count <= gap_count - 1;
end if;
end if;
when transmit =>
if tx_next='1' and user_last='1' then
state <= crc_1;
end if;
when reset_pkt =>
tx_data_i <= (others => reset_data);
if reset_last='1' then
tx_last_i <= '1';
end if;
if tx_next='1' then
tx_start <= '0';
if tx_last_i='1' then
tx_valid <= '0';
tx_last_i <= '0';
state <= idle;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
crc_dvalid <= '1' when (state = transmit) and tx_next='1' else '0';
crc_sync <= '1' when (state = idle) else '0';
busy <= '0' when (state = idle) else '1'; -- or (state = gap) else '1';
i_token_crc: entity work.usb1_token_crc
port map (
clock => clock,
sync => '1',
token_in => token,
crc => token_crc );
i_data_crc: entity work.usb1_data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => user_data,
crc => data_crc );
with state select tx_data <=
user_data when transmit,
data_crc(7 downto 0) when crc_1,
data_crc(15 downto 8) when crc_2,
tx_data_i when others;
tx_last <= tx_last_i;
user_next <= tx_next when state=transmit else '0';
end gideon;
| gpl-3.0 | befc5245b47c432bcb8dbc8c57c06777 | 0.390077 | 4.127891 | false | false | false | false |
tirfil/VhdI2CSlave | vhdl/i2cslave.vhd | 1 | 6,479 | --###############################
--# Project Name : I2C slave
--# File : i2cslave.vhd
--# Project : i2c slave for FPGA
--# Engineer : Philippe THIRION
--# Modification History
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity I2CSLAVE is
generic(
DEVICE : std_logic_vector(7 downto 0) := x"38"
);
port(
MCLK : in std_logic;
nRST : in std_logic;
SDA_IN : in std_logic;
SCL_IN : in std_logic;
SDA_OUT : out std_logic;
SCL_OUT : out std_logic;
ADDRESS : out std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
WR : out std_logic;
RD : out std_logic;
READ_DONE : out std_logic
);
end I2CSLAVE;
architecture rtl of I2CSLAVE is
type tstate is ( S_IDLE, S_START, S_SHIFTIN, S_RW, S_SENDACK, S_SENDACK2, S_SENDNACK,
S_ADDRESS, S_WRITE, S_SHIFTOUT, S_READ, S_WAITACK
);
type toperation is (OP_READ, OP_WRITE);
signal state : tstate;
signal next_state : tstate;
signal operation : toperation;
signal rising_scl, falling_scl : std_logic;
signal address_i : std_logic_vector(7 downto 0);
signal next_address : std_logic_vector(7 downto 0);
signal counter : integer range 0 to 7;
signal start_cond : std_logic;
signal stop_cond : std_logic;
signal sda_q, sda_qq, sda_qqq : std_logic;
signal scl_q, scl_qq, scl_qqq : std_logic;
signal shiftreg : std_logic_vector(7 downto 0);
signal sda: std_logic;
signal address_incr : std_logic;
signal rd_d : std_logic;
signal read_data_done : std_logic;
begin
ADDRESS <= address_i;
next_address <= (others=>'0') when (address_i = x"FF") else
std_logic_vector(to_unsigned(to_integer(unsigned( address_i )) + 1, 8));
S_RSY: process(MCLK,nRST)
begin
if (nRST = '0') then
sda_q <= '1';
sda_qq <= '1';
sda_qqq <= '1';
scl_q <= '1';
scl_qq <= '1';
scl_qqq <= '1';
elsif (MCLK'event and MCLK='1') then
sda_q <= SDA_IN;
sda_qq <= sda_q;
sda_qqq <= sda_qq;
scl_q <= SCL_IN;
scl_qq <= scl_q;
scl_qqq <= scl_qq;
end if;
end process S_RSY;
rising_scl <= scl_qq and not scl_qqq;
falling_scl <= not scl_qq and scl_qqq;
START_BIT: process(MCLK,nRST)
begin
if (nRST = '0') then
start_cond <= '0';
elsif (MCLK'event and MCLK='1') then
if (sda_qqq = '1' and sda_qq = '0' and scl_qq = '1') then
start_cond <= '1';
else
start_cond <= '0';
end if;
end if;
end process START_BIT;
STOP_BIT: process(MCLK,nRST)
begin
if (nRST = '0') then
stop_cond <= '0';
elsif (MCLK'event and MCLK='1') then
if (sda_qqq = '0' and sda_qq = '1' and scl_qq = '1') then
stop_cond <= '1';
else
stop_cond <= '0';
end if;
end if;
end process STOP_BIT;
sda <= sda_qq;
RD_DELAY: process(MCLK, nRST)
begin
if (nRST = '0') then
RD <= '0';
elsif (MCLK'event and MCLK='1') then
RD <= rd_d;
end if;
end process RD_DELAY;
OTO: process(MCLK, nRST)
begin
if (nRST = '0') then
state <= S_IDLE;
SDA_OUT <= '1';
SCL_OUT <= '1';
WR <= '0';
rd_d <= '0';
address_i <= (others=>'0');
DATA_OUT <= (others=>'0');
shiftreg <= (others=>'0');
read_data_done <= '0';
elsif (MCLK'event and MCLK='1') then
if (stop_cond = '1') then
state <= S_IDLE;
SDA_OUT <= '1';
SCL_OUT <= '1';
operation <= OP_READ;
WR <= '0';
rd_d <= '0';
address_incr <= '0';
elsif(start_cond = '1') then
state <= S_START;
SDA_OUT <= '1';
SCL_OUT <= '1';
operation <= OP_READ;
WR <= '0';
rd_d <= '0';
address_incr <= '0';
elsif(state = S_IDLE) then
state <= S_IDLE;
SDA_OUT <= '1';
SCL_OUT <= '1';
operation <= OP_READ;
WR <= '0';
rd_d <= '0';
address_incr <= '0';
elsif(state = S_START) then
shiftreg <= (others=>'0');
state <= S_SHIFTIN;
next_state <= S_RW;
counter <= 6;
elsif(state = S_SHIFTIN) then
if (rising_scl = '1') then
shiftreg(7 downto 1) <= shiftreg(6 downto 0);
shiftreg(0) <= sda;
if (counter = 0) then
state <= next_state;
counter <= 7;
else
counter <= counter - 1;
end if;
end if;
elsif(state = S_RW) then
if (rising_scl = '1') then
if (shiftreg = DEVICE) then
state <= S_SENDACK;
if (sda = '1') then
operation <= OP_READ;
-- next_state <= S_READ; -- no needed
rd_d <= '1';
else
operation <= OP_WRITE;
next_state <= S_ADDRESS;
address_incr <= '0';
end if;
else
state <= S_SENDNACK;
end if;
end if;
elsif(state = S_SENDACK) then
WR <= '0';
rd_d <= '0';
if (falling_scl = '1') then
SDA_OUT <= '0';
counter <= 7;
if (operation= OP_WRITE) then
state <= S_SENDACK2;
else -- OP_READ
state <= S_SHIFTOUT;
shiftreg <= DATA_IN;
read_data_done <= '1';
end if;
end if;
elsif(state = S_SENDACK2) then
if (falling_scl = '1') then
SDA_OUT <= '1';
state <= S_SHIFTIN;
shiftreg <= (others=>'0');
if (address_incr = '1') then
address_i <= next_address;
end if;
end if;
elsif(state = S_SENDNACK) then
if (falling_scl = '1') then
SDA_OUT <= '1';
state <= S_IDLE;
end if;
elsif(state = S_ADDRESS) then
address_i <= shiftreg;
next_state <= S_WRITE;
state <= S_SENDACK;
address_incr <= '0';
elsif(state = S_WRITE) then
DATA_OUT <= shiftreg;
next_state <= S_WRITE;
state <= S_SENDACK;
WR <= '1';
address_incr <= '1';
elsif(state = S_SHIFTOUT) then
read_data_done <= '0';
if (falling_scl = '1') then
SDA_OUT <= shiftreg(7);
shiftreg(7 downto 1) <= shiftreg(6 downto 0);
shiftreg(0) <= '1';
if (counter = 0) then
state <= S_READ;
address_i <= next_address;
rd_d <= '1';
else
counter <= counter - 1;
end if;
end if;
elsif(state = S_READ) then
rd_d <= '0';
if (falling_scl = '1') then
SDA_OUT <= '1';
state <= S_WAITACK;
end if;
elsif(state = S_WAITACK) then
if (rising_scl = '1') then
if (sda = '0') then
state <= S_SHIFTOUT;
counter <= 7;
shiftreg <= DATA_IN;
read_data_done <= '1';
else
state <= S_IDLE;
end if;
end if;
end if;
end if;
end process OTO;
READ_DONE <= read_data_done;
end rtl;
| gpl-3.0 | 78da7ab24990d4cbb4f33465bfa7e8b8 | 0.537737 | 2.706349 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/ram/simulation/ram_synth.vhd | 1 | 7,846 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ram_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY ram_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE ram_synth_ARCH OF ram_synth IS
COMPONENT ram_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: ram_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | 3079e25879e6c9dc1c6a4a23e79e1847 | 0.563599 | 3.775746 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/command_interface/vhdl_source/command_protocol.vhd | 3 | 12,745 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.command_if_pkg.all;
entity command_protocol is
port (
clock : in std_logic;
reset : in std_logic;
-- io interface for local cpu
io_req : in t_io_req; -- we get a 2K range
io_resp : out t_io_resp;
-- C64 side interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
freeze : out std_logic;
-- block memory
address : out unsigned(10 downto 0);
rdata : in std_logic_vector(7 downto 0);
wdata : out std_logic_vector(7 downto 0);
en : out std_logic;
we : out std_logic );
end entity;
-- How does the protocol work?
-- The Ultimate software initializes the command and response buffers that the C64 can write to.
-- Each buffer has a start address, an end address, and a current read/write pointer as seen
-- from the C64 side.
-- The C64 can write into the command buffer and set a handshake flag. The 1541U software
-- triggers on the flag, and reads the write pointer, copies the command, and stores the
-- result and status in their respective buffers, and sets the respective handshake flags back
-- to the C64. The buffers on the ultimate side are direct mapped; on the C64 side, each
-- buffer has its own data register. One bidirectional register (on the C64 side) acts as
-- handshake register. Command queueing is not supported.
-- Protocol:
-- There are 4 states:
-- 00: Ultimate is ready and waiting for new command
-- 01: C64 has written data into the Ultimate command buffer, and the Ultimate is processing it
-- 11: Ultimate has processed the command and replied with data/status. This is not the last data.
-- 10: Ultimate has processed the command and replied with data/status. This is the last data.
-- The status register (seen by the C64) holds the following bits:
-- Bit 7: Response data available
-- Bit 6: Status data available
-- Bit 5..4: State
-- Bit 3: Error flag (write 1 to clear)
-- Bit 2: Abort flag set (cleared by Ultimate software)
-- Bit 1: Data accepted bit set (cleared by Ultimate software)
-- Bit 0: New command (set when new command is written, should NOT be used by C64)
architecture gideon of command_protocol is
signal enabled : std_logic;
signal slot_base : unsigned(6 downto 0);
signal do_write : std_logic;
signal command_pointer : unsigned(10 downto 0);
signal response_pointer : unsigned(10 downto 0);
signal status_pointer : unsigned(10 downto 0);
signal command_length : unsigned(10 downto 0);
signal response_length : unsigned(10 downto 0);
signal status_length : unsigned(10 downto 0);
-- signal response_valid : std_logic;
-- signal status_valid : std_logic;
signal rdata_resp : std_logic_vector(7 downto 0);
signal rdata_stat : std_logic_vector(7 downto 0);
signal slot_status : std_logic_vector(7 downto 0);
alias response_valid : std_logic is slot_status(7);
alias status_valid : std_logic is slot_status(6);
alias state : std_logic_vector(1 downto 0) is slot_status(5 downto 4);
alias error_busy : std_logic is slot_status(3);
alias handshake_in : std_logic_vector(2 downto 0) is slot_status(2 downto 0);
begin
-- assert false report integer'image(to_integer(c_cmd_if_command_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_response_buffer_end)) severity warning;
-- assert false report integer'image(to_integer(c_cmd_if_status_buffer_end)) severity warning;
--
command_length <= command_pointer - c_cmd_if_command_buffer_addr;
with slot_req.bus_address(1 downto 0) select slot_resp.data <=
slot_status when c_cif_slot_control,
X"C9" when c_cif_slot_command,
rdata_resp when c_cif_slot_response,
rdata_stat when others;
rdata_resp <= rdata when response_valid='1' else X"00";
rdata_stat <= rdata when status_valid='1' else X"00";
slot_resp.reg_output <= enabled when slot_req.bus_address(8 downto 2) = slot_base else '0';
slot_resp.irq <= '0';
-- signals to RAM
en <= enabled;
we <= do_write;
wdata <= slot_req.data;
address <= command_pointer when do_write='1' else
response_pointer when slot_req.bus_address(0)='0' else
status_pointer;
do_write <= '1' when slot_req.io_write='1' and slot_req.io_address(8 downto 0) = (slot_base & c_cif_slot_command) else '0';
p_control: process(clock)
procedure reset_response is
begin
response_pointer <= c_cmd_if_response_buffer_addr;
status_pointer <= c_cmd_if_status_buffer_addr;
response_length <= (others => '0');
status_length <= (others => '0');
end procedure;
begin
if rising_edge(clock) then
if (response_pointer - c_cmd_if_response_buffer_addr) < response_length then
response_valid <= '1';
else
response_valid <= '0';
end if;
if (status_pointer - c_cmd_if_status_buffer_addr) < status_length then
status_valid <= '1';
else
status_valid <= '0';
end if;
if (slot_req.io_address(8 downto 2) = slot_base) and (enabled = '1') then
if slot_req.io_write='1' then
case slot_req.io_address(1 downto 0) is
when c_cif_slot_command =>
if command_pointer /= c_cmd_if_command_buffer_end then
command_pointer <= command_pointer + 1;
end if;
when c_cif_slot_control =>
if slot_req.data(3)='1' then
error_busy <= '0';
end if;
if slot_req.data(0)='1' then
freeze <= slot_req.data(7);
if state = "00" then
reset_response;
state <= "01";
handshake_in(0) <= '1';
else
error_busy <= '1';
end if;
end if;
if slot_req.data(1)='1' and state(1) = '1' then -- data accept
handshake_in(1) <= '1'; -- data accepted, only ultimate can clear it
reset_response;
state(1) <= '0'; -- either goes to idle, or back to wait for software
end if;
if slot_req.data(2)='1' then
handshake_in(2) <= '1'; -- abort, only ultimate can clear it.
reset_response;
end if;
when others =>
null;
end case;
elsif slot_req.io_read='1' then
case slot_req.io_address(1 downto 0) is
when c_cif_slot_response =>
if response_pointer /= c_cmd_if_response_buffer_end then
response_pointer <= response_pointer + 1;
end if;
when c_cif_slot_status =>
if status_pointer /= c_cmd_if_status_buffer_end then
status_pointer <= status_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
slot_base <= unsigned(io_req.data(slot_base'range));
when c_cif_io_slot_enable =>
enabled <= io_req.data(0);
when c_cif_io_handshake_out =>
if io_req.data(0)='1' then -- reset
handshake_in(0) <= '0';
command_pointer <= c_cmd_if_command_buffer_addr;
end if;
if io_req.data(1)='1' then -- data seen
handshake_in(1) <= '0';
end if;
if io_req.data(2)='1' then -- abort bit
handshake_in(2) <= '0';
end if;
if io_req.data(4)='1' then -- validate data
freeze <= '0';
state(1) <= '1';
state(0) <= io_req.data(5); -- more bit
end if;
if io_req.data(7)='1' then
freeze <= '0';
reset_response;
state <= "00";
end if;
when c_cif_io_status_length =>
status_pointer <= c_cmd_if_status_buffer_addr;
status_length(7 downto 0) <= unsigned(io_req.data); -- FIXME
when c_cif_io_response_len_l =>
response_pointer <= c_cmd_if_response_buffer_addr;
response_length(7 downto 0) <= unsigned(io_req.data);
when c_cif_io_response_len_h =>
response_length(10 downto 8) <= unsigned(io_req.data(2 downto 0));
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cif_io_slot_base =>
io_resp.data(slot_base'range) <= std_logic_vector(slot_base);
when c_cif_io_slot_enable =>
io_resp.data(0) <= enabled;
when c_cif_io_handshake_out =>
io_resp.data(5 downto 4) <= state;
when c_cif_io_handshake_in =>
io_resp.data <= slot_status;
when c_cif_io_command_start =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_addr(10 downto 3));
when c_cif_io_command_end =>
io_resp.data <= std_logic_vector(c_cmd_if_command_buffer_end(10 downto 3));
when c_cif_io_response_start =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_addr(10 downto 3));
when c_cif_io_response_end =>
io_resp.data <= std_logic_vector(c_cmd_if_response_buffer_end(10 downto 3));
when c_cif_io_status_start =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_addr(10 downto 3));
when c_cif_io_status_end =>
io_resp.data <= std_logic_vector(c_cmd_if_status_buffer_end(10 downto 3));
when c_cif_io_status_length =>
io_resp.data <= std_logic_vector(status_length(7 downto 0)); -- fixme
when c_cif_io_response_len_l =>
io_resp.data <= std_logic_vector(response_length(7 downto 0));
when c_cif_io_response_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(response_length(10 downto 8));
when c_cif_io_command_len_l =>
io_resp.data <= std_logic_vector(command_length(7 downto 0));
when c_cif_io_command_len_h =>
io_resp.data(2 downto 0) <= std_logic_vector(command_length(10 downto 8));
when others =>
null;
end case;
end if;
if reset='1' then
command_pointer <= c_cmd_if_command_buffer_addr;
reset_response;
handshake_in <= "000";
state <= "00";
enabled <= '0';
error_busy <= '0';
slot_base <= (others => '0');
freeze <= '0';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | d2e132d4bd65a4da21e8187b919fc6d7 | 0.499804 | 4.056334 | false | false | false | false |
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