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daringer/schemmaker | testdata/new/circuit_bi1_0op944_4.vhdl | 1 | 4,147 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => out1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias3,
S => net3
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 099c6d7dc44630476d7b6ea090aaf68a | 0.587895 | 3.257659 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_source/ulpi_tx.vhd | 1 | 11,226 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_tx is
generic (
g_simulation : boolean := false;
g_support_split : boolean := true;
g_support_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
-- Bus Interface
tx_start : out std_logic;
tx_last : out std_logic;
tx_valid : out std_logic;
tx_next : in std_logic;
tx_data : out std_logic_vector(7 downto 0);
rx_busy : in std_logic;
-- CRC calculator
crc_sync : out std_logic;
crc_dvalid : out std_logic;
data_to_crc : out std_logic_vector(7 downto 0);
data_crc : in std_logic_vector(15 downto 0);
-- Status
status : in std_logic_vector(7 downto 0);
speed : in std_logic_vector(1 downto 0);
usb_tx_req : in t_usb_tx_req;
usb_tx_resp : out t_usb_tx_resp );
end ulpi_tx;
architecture gideon of ulpi_tx is
type t_state is (idle, crc_1, crc_2, token0, token1, token2, token3,
transmit, wait4next, write_end, handshake, gap, gap2);
signal state : t_state;
signal tx_data_i : std_logic_vector(7 downto 0);
signal tx_last_i : std_logic;
signal token_crc : std_logic_vector(4 downto 0) := "00000";
signal split_crc : std_logic_vector(4 downto 0) := "00000";
signal no_data_d : std_logic;
signal gap_count : integer range 0 to 2047;
signal rd_data : std_logic_vector(7 downto 0);
signal rd_last : std_logic;
signal rd_next : std_logic;
signal token_vector : std_logic_vector(18 downto 0);
signal long : boolean;
signal fifo_flush : std_logic;
signal busy : std_logic;
signal sending_sof : boolean;
signal tx_allowed : std_logic;
signal start_value : unsigned(10 downto 0);
signal start_timer : std_logic;
-- internal fifo is 3 bytes as it seems. 3 bytes is at max 40 bits incl. 1.5 SE0 EOP. at Full speed this is 40*5 = 200 clocks
-- at low speed this is 40*40 clocks = 1600
type t_int_array is array (natural range <>) of integer;
constant c_gap_values : t_int_array(0 to 3) := ( 1599, 199, 13, 13 );
-- XILINX USB STICK:
-- On high speed, gap values 0x05 - 0x25 WORK.. (bigger than 0x25 doesn't, smaller than 0x05 doesn't..)
-- TRUST USB 2.0 Hub:
-- On high speed, gap values 0x07 - 0x1D WORK.. with the exception of 0x09.
-- Samsung DVD-Burner:
-- On high speed, gap values 0x00 - 0x23 WORK.. with the exception of 0x04.
-- Western Digital external HD:
-- On high speed, gap values 0x05 - 0x21 WORK.. with the exception of 0x06 and 0x09.
--
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "sequential";
begin
usb_tx_resp.request_ack <= (usb_tx_req.send_token or usb_tx_req.send_handsh or usb_tx_req.send_packet or usb_tx_req.send_split)
when (state = idle) and (tx_allowed = '1') else '0';
usb_tx_resp.busy <= busy;
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
fifo_flush <= '0';
tx_data_i <= X"00";
no_data_d <= usb_tx_req.no_data;
long <= false;
sending_sof <= usb_tx_req.pid = c_pid_sof;
if tx_allowed = '1' then
if usb_tx_req.send_token='1' and g_support_token then
token_vector <= token_to_vector(usb_tx_req.token) & X"00";
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & usb_tx_req.pid;
state <= token1;
elsif usb_tx_req.send_split='1' and g_support_split then
token_vector <= split_token_to_vector(usb_tx_req.split_token);
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & usb_tx_req.pid;
long <= true;
state <= token0;
elsif usb_tx_req.send_handsh='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & usb_tx_req.pid;
tx_last_i <= '1';
state <= handshake;
elsif usb_tx_req.send_packet='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & usb_tx_req.pid;
state <= wait4next;
end if;
end if;
when wait4next =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '1';
if no_data_d='1' then
state <= crc_1;
else
state <= transmit;
end if;
end if;
when handshake =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
state <= gap;
end if;
when write_end =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
state <= idle;
end if;
when crc_1 =>
if tx_next = '1' then
tx_last_i <= '1';
fifo_flush <= '1';
state <= crc_2;
end if;
when crc_2 =>
if tx_next = '1' then
tx_last_i <= '0';
tx_valid <= '0';
state <= gap;
end if;
when token0 =>
if tx_next = '1' then
tx_start <= '0';
tx_data_i <= token_vector(7 downto 0);
state <= token1;
end if;
when token1 =>
if tx_next = '1' then
tx_start <= '0';
tx_data_i <= token_vector(15 downto 8);
state <= token2;
end if;
when token2 =>
if tx_next = '1' then
if long then
tx_data_i <= split_crc & token_vector(18 downto 16);
else
tx_data_i <= token_crc & token_vector(18 downto 16);
end if;
tx_last_i <= '1';
state <= token3;
end if;
when token3 =>
if tx_next = '1' then
tx_last_i <= '0';
tx_valid <= '0';
state <= gap;
end if;
when gap => -- pulse timer
state <= gap2;
when gap2 =>
if tx_allowed = '1' then
state <= idle;
end if;
when transmit =>
if tx_next='1' and rd_last='1' then
state <= crc_1;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
fifo_flush <= '0';
end if;
end if;
end process;
crc_dvalid <= '1' when (state = transmit) and tx_next='1' else '0';
--crc_sync <= '1' when (state = idle) else '0';
crc_sync <= usb_tx_req.send_packet;
busy <= '0' when (state = idle) else '1'; -- or (state = gap) else '1';
g_token: if g_support_token generate
i_token_crc: entity work.token_crc
port map (
clock => clock,
token_in => token_vector(18 downto 8),
crc => token_crc );
end generate;
g_split: if g_support_split generate
i_split_crc: entity work.token_crc_19
port map (
clock => clock,
token_in => token_vector(18 downto 0),
crc => split_crc );
end generate;
with state select tx_data <=
rd_data when transmit,
data_crc(7 downto 0) when crc_1,
data_crc(15 downto 8) when crc_2,
tx_data_i when others;
tx_last <= tx_last_i;
rd_next <= '1' when (tx_next = '1') and (state = transmit) else '0';
i_tx_fifo: entity work.srl_fifo
generic map (
Width => 9,
Threshold => 13 )
port map (
clock => clock,
reset => reset,
GetElement => rd_next,
PutElement => usb_tx_req.data_valid,
FlushFifo => fifo_flush,
DataIn(8) => usb_tx_req.data_last,
DataIn(7 downto 0) => usb_tx_req.data,
DataOut(8) => rd_last,
DataOut(7 downto 0) => rd_data,
SpaceInFifo => open,
AlmostFull => usb_tx_resp.data_wait,
DataInFifo => open );
data_to_crc <= rd_data;
start_timer <= '1' when state = gap else rx_busy; -- we start the tx_backoff timer when we are receiving, or when we finished transmitting
process(sending_sof, speed, status)
begin
if g_simulation then
start_value <= to_unsigned(15, start_value'length);
elsif rx_busy = '1' then
start_value <= to_unsigned(12, start_value'length);
elsif sending_sof and speed(1)='1' then
start_value <= to_unsigned(22, start_value'length);
else
case speed is
when "00" => start_value <= to_unsigned(c_gap_values(0), start_value'length);
when "01" => start_value <= to_unsigned(c_gap_values(1), start_value'length);
when others => start_value <= to_unsigned(c_gap_values(2), start_value'length);
end case;
end if;
end process;
i_timer: entity work.timer
generic map (
g_reset => '1',
g_width => 11 )
port map (
clock => clock,
reset => reset,
start => start_timer,
start_value => start_value,
timeout => tx_allowed );
end gideon;
| gpl-3.0 | fe40be166a2a4570a61451dee4b35f2a | 0.430429 | 4.004995 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_source/char_generator_rom.vhd | 5 | 1,371 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_rom.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator ROM
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.char_generator_rom_pkg.all;
entity char_generator_rom is
port (
clock : in std_logic;
enable : in std_logic := '1';
address : in unsigned(10 downto 0);
data : out std_logic_vector(7 downto 0) );
end entity;
architecture rom of char_generator_rom is
signal data_i : std_logic_vector(7 downto 0) := X"00";
begin
process(clock)
begin
if rising_edge(clock) then
if enable='1' then
data_i <= char_rom_array(to_integer(address));
end if;
end if;
end process;
data <= data_i;
end rom;
| gpl-3.0 | 9a7531f57a3d610b95159525dfe13119 | 0.417943 | 4.600671 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op328_4sk1_0.vhdl | 1 | 6,113 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4e-07,
W => Wdiff_0,
Wdiff_0init => 2.145e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4e-07,
W => Wdiff_0,
Wdiff_0init => 2.145e-05,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => W_0,
W_0init => 7.725e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => Wcasc_2,
Wcasc_2init => 8.2e-06,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => Wcasc_2,
Wcasc_2init => 8.2e-06,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias2,
S => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => Wcmcasc_1,
Wcmcasc_1init => 8.25e-06,
scope => Wprivate
)
port map(
D => net4,
G => vbias3,
S => net6
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.7e-06,
W => Wcm_1,
Wcm_1init => 1.425e-05,
scope => private
)
port map(
D => net6,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.7e-06,
W => Wcmout_1,
Wcmout_1init => 1.505e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => Wcmcasc_1,
Wcmcasc_1init => 8.25e-06,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => (pfak)*(WBias),
WBiasinit => 2.35e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6e-07,
W => (pfak)*(WBias),
WBiasinit => 2.35e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6e-07,
W => WBias,
WBiasinit => 2.35e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => WBias,
WBiasinit => 2.35e-06
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => WBias,
WBiasinit => 2.35e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6e-07,
W => WBias,
WBiasinit => 2.35e-06
)
port map(
D => net8,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net9,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net9,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net9,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 535b461fd642df509ec7ad087d5ae335 | 0.588909 | 2.992168 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op4.vhdl | 1 | 9,380 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.95e-06,
W => Wdiff_0,
Wdiff_0init => 6.12e-05,
scope => private
)
port map(
D => net5,
G => in1,
S => net3
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 5.95e-06,
W => Wdiff_0,
Wdiff_0init => 6.12e-05,
scope => private
)
port map(
D => net4,
G => in2,
S => net3
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => W_0,
W_0init => 6.385e-05
)
port map(
D => net3,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => Wcursrc_1,
Wcursrc_1init => 1.055e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => Wcursrc_1,
Wcursrc_1init => 1.055e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => L_2,
L_2init => 3.45e-06,
W => Wsrc_2,
Wsrc_2init => 6.895e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net1,
G => net4,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => L_3,
L_3init => 6.6e-06,
W => Wsrc_2,
Wsrc_2init => 6.895e-05,
scope => Wprivate,
symmetry_scope => sym_4
)
port map(
D => net2,
G => net5,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcm_3,
Wcm_3init => 4.5e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcmout_3,
Wcmout_3init => 7.285e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net1,
S => vdd
);
subnet0_subnet5_c1 : entity cap(behave)
generic map(
C => C_4,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net1
);
subnet0_subnet6_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcm_3,
Wcm_3init => 4.5e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet6_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcmout_3,
Wcmout_3init => 7.285e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out2,
G => net2,
S => vdd
);
subnet0_subnet6_c1 : entity cap(behave)
generic map(
C => C_5,
symmetry_scope => sym_5
)
port map(
P => out2,
N => net2
);
subnet0_subnet7_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => Wcursrc_4,
Wcursrc_4init => 3.685e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet8_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => Wcursrc_4,
Wcursrc_4init => 3.685e-05,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net6,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net6,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net9,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net8,
N => net6
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => W_1,
W_1init => 6.395e-05
)
port map(
D => net7,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 7.75e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 5.365e-05,
scope => private
)
port map(
D => net9,
G => vref,
S => net7
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 7.75e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 5.365e-05,
scope => private
)
port map(
D => net8,
G => net6,
S => net7
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 6.35e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 5e-07,
scope => private
)
port map(
D => net8,
G => net8,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 6.35e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 5e-07,
scope => private
)
port map(
D => net9,
G => net8,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 2.35e-06,
W => Wcmbias_0,
Wcmbias_0init => 7.2e-05,
scope => private
)
port map(
D => out1,
G => net9,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 2.35e-06,
W => Wcmbias_0,
Wcmbias_0init => 7.2e-05,
scope => private
)
port map(
D => out2,
G => net9,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => (pfak)*(WBias),
WBiasinit => 6.105e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6.15e-06,
W => (pfak)*(WBias),
WBiasinit => 6.105e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 6.15e-06,
W => WBias,
WBiasinit => 6.105e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => WBias,
WBiasinit => 6.105e-05
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => WBias,
WBiasinit => 6.105e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 6.15e-06,
W => WBias,
WBiasinit => 6.105e-05
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 9c87a87fb236dd1d75ac0eaee4201024 | 0.569616 | 2.855403 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/lib/global.vhd | 3 | 2,965 | ------------------------------------------------------------------------------------------------------------------------
-- Global package
--
-- Copyright (C) 2012 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2012-02-07 zelenkaj Derived from global package
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package Global is
constant cActivated : std_logic := '1';
constant cInactivated : std_logic := '0';
constant cnActivated : std_logic := '0';
constant cnInactivated : std_logic := '1';
function LogDualis(cNumber : natural) return natural;
end Global;
package body Global is
function LogDualis(cNumber : natural) return natural is
variable vClimbUp : natural := 1;
variable vResult : natural;
begin
while vClimbUp < cNumber loop
vClimbUp := vClimbUp * 2;
vResult := vResult+1;
end loop;
return vResult;
end LogDualis;
end Global; | gpl-2.0 | 35f9389bd21e5a5ba72c7240a023d309 | 0.584148 | 5.156522 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/altaccumulate1_inst.vhd | 1 | 193 | altaccumulate1_inst : altaccumulate1 PORT MAP (
aclr => aclr_sig,
clken => clken_sig,
clock => clock_sig,
data => data_sig,
overflow => overflow_sig,
result => result_sig
);
| gpl-2.0 | 94293af764befe08c4d3f773a1eb8af2 | 0.626943 | 2.880597 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_sim/tb_proc_control.vhd | 5 | 7,221 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.pkg_6502_defs.all;
use work.pkg_6502_decode.all;
use work.pkg_6502_opcodes.all;
entity tb_proc_control is
end tb_proc_control;
architecture tb of tb_proc_control is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal inst : std_logic_vector(7 downto 0);
signal force_sync : std_logic;
signal index_carry : std_logic := '1';
signal pc_carry : std_logic := '1';
signal branch_taken : boolean := true;
signal latch_dreg : std_logic;
signal reg_update : std_logic;
signal copy_d2p : std_logic;
signal dummy_cycle : std_logic;
signal sync : std_logic;
signal rwn : std_logic;
signal a_mux : t_amux;
signal pc_oper : t_pc_oper;
signal s_oper : t_sp_oper;
signal adl_oper : t_adl_oper;
signal adh_oper : t_adh_oper;
signal dout_mux : t_dout_mux;
signal opcode : string(1 to 13);
signal s_is_absolute : boolean;
signal s_is_abs_jump : boolean;
signal s_is_immediate : boolean;
signal s_is_implied : boolean;
signal s_is_stack : boolean;
signal s_is_push : boolean;
signal s_is_zeropage : boolean;
signal s_is_indirect : boolean;
signal s_is_relative : boolean;
signal s_is_load : boolean;
signal s_is_store : boolean;
signal s_is_rmw : boolean;
signal s_is_jump : boolean;
signal s_is_postindexed : boolean;
signal s_store_a_from_alu : boolean;
signal s_load_x : boolean;
signal s_load_y : boolean;
signal i_reg : std_logic_vector(7 downto 0);
signal adh, adl : std_logic_vector(7 downto 0) := X"00";
signal pch, pcl : std_logic_vector(7 downto 0) := X"11";
signal addr : std_logic_vector(15 downto 0);
signal sp : std_logic_vector(7 downto 0) := X"FF";
signal dreg : std_logic_vector(7 downto 0) := X"FF";
signal databus : std_logic_vector(7 downto 0);
signal dout : std_logic_vector(7 downto 0);
begin
s_is_absolute <= is_absolute(i_reg);
s_is_abs_jump <= is_abs_jump(i_reg);
s_is_immediate <= is_immediate(i_reg);
s_is_implied <= is_implied(i_reg);
s_is_stack <= is_stack(i_reg);
s_is_push <= is_push(i_reg);
s_is_zeropage <= is_zeropage(i_reg);
s_is_indirect <= is_indirect(i_reg);
s_is_relative <= is_relative(i_reg);
s_is_load <= is_load(i_reg);
s_is_store <= is_store(i_reg);
s_is_rmw <= is_rmw(i_reg);
s_is_jump <= is_jump(i_reg);
s_is_postindexed <= is_postindexed(i_reg);
s_store_a_from_alu <= store_a_from_alu(i_reg);
s_load_x <= load_x(i_reg);
s_load_y <= load_y(i_reg);
mut: entity work.proc_control
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
interrupt => '0',
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
sync => sync,
dummy_cycle => dummy_cycle,
latch_dreg => latch_dreg,
reg_update => reg_update,
copy_d2p => copy_d2p,
rwn => rwn,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper );
clock <= not clock after 50 ns;
clock_en <= '1';
reset <= '1', '0' after 500 ns;
test: process
begin
inst <= X"00";
force_sync <= '0';
wait until reset='0';
for i in 0 to 255 loop
inst <= conv_std_logic_vector(i, 8);
wait until sync='1' for 2 us;
if sync='0' then
wait until clock='1';
force_sync <= '1';
wait until clock='1';
force_sync <= '0';
else
wait until sync='0';
end if;
end loop;
wait;
end process;
opcode <= opcode_array(conv_integer(i_reg));
process(clock)
begin
if rising_edge(clock) and clock_en='1' then
if latch_dreg='1' then
dreg <= databus;
end if;
if sync='1' or force_sync='1' then
i_reg <= databus;
end if;
case pc_oper is
when increment =>
if pcl = X"FF" then
pch <= pch + 1;
end if;
pcl <= pcl + 1;
when copy =>
pcl <= dreg;
pch <= databus;
when from_alu =>
pcl <= pcl + 40;
when others =>
null;
end case;
case adl_oper is
when increment =>
adl <= adl + 1;
when add_idx =>
adl <= adl + 5;
when load_bus =>
adl <= databus;
when copy_dreg =>
adl <= dreg;
when others =>
null;
end case;
case adh_oper is
when increment =>
adh <= adh + 1;
when clear =>
adh <= (others => '0');
when load_bus =>
adh <= databus;
when others =>
null;
end case;
case s_oper is
when increment =>
sp <= sp + 1;
when decrement =>
sp <= sp - 1;
when others =>
null;
end case;
end if;
end process;
with a_mux select addr <=
X"FFFF" when 0,
adh & adl when 1,
X"01" & sp when 2,
pch & pcl when 3;
with dout_mux select dout <=
dreg when reg_d,
X"11" when reg_axy,
X"22" when reg_flags,
pcl when reg_pcl,
pch when reg_pch,
X"33" when shift_res,
X"FF" when others;
databus <= inst when (sync='1' or force_sync='1') else X"D" & addr(3 downto 0);
end tb;
| gpl-3.0 | 87fa545bb98921d5ccecbd8de1b43b5f | 0.423349 | 3.861497 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op989_8.vhdl | 1 | 6,153 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net8
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net8,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net9,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | ed063e6547f3bb6b65865eb4a5ce9f2e | 0.574516 | 3.088855 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/zpu_medium.vhdl | 5 | 50,197 | ------------------------------------------------------------------------------
---- ----
---- ZPU Medium ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the medium size version. ----
---- Supports external memories. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUMediumCore(Behave) (Entity and architecture) ----
---- File name: zpu_medium.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
--
-- write_en_o - set to '1' for a single cycle to send off a write request.
-- data_o is valid only while write_en_o='1'.
-- read_en_o - set to '1' for a single cycle to send off a read request.
-- mem_busy_i - It is illegal to send off a read/write request when
-- mem_busy_i='1'.
-- Set to '0' when data_i is valid after a read request.
-- If it goes to '1'(busy), it is on the cycle after read/
-- write_en_o is '1'.
-- addr_o - address for read/write request
-- data_i - read data. Valid only on the cycle after mem_busy_i='0'
-- after read_en_o='1' for a single cycle.
-- data_o - data to write
-- break_o - set to '1' when CPU hits break instruction
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library zpu;
use zpu.zpupkg.all;
entity ZPUMediumCore is
generic(
WORD_SIZE : integer:=32; -- 16/32 (2**wordPower)
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
MULT_PIPE : boolean:=false; -- Pipeline multiplication
BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
ENA_LSHR : boolean:=true; -- lshiftright
ENA_IDLE : boolean:=false; -- Enable the enable_i input
FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
port(
clk_i : in std_logic; -- CPU Clock
reset_i : in std_logic; -- Sync Reset
enable_i : in std_logic; -- Hold the CPU (after reset)
break_o : out std_logic; -- Break instruction executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- Memory interface
mem_busy_i : in std_logic; -- Memory is busy
data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
write_en_o : out std_logic; -- Memory write enable
read_en_o : out std_logic); -- Memory read enable
end entity ZPUMediumCore;
architecture Behave of ZPUMediumCore is
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
constant WORD_BYTES : integer:=WORD_SIZE/OPCODE_W;
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(ADDR_W-1 downto BYTE_BITS):=
SP_START_1(ADDR_W-1 downto BYTE_BITS);
-- Update [SP+1]. We hold it in b_r, this writes the value to memory.
procedure FlushB(signal we : out std_logic;
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal inc_sp : in unsigned(ADDR_W-1 downto BYTE_BITS);
signal data : out unsigned(WORD_SIZE-1 downto 0);
signal b : in unsigned(WORD_SIZE-1 downto 0)) is
begin
we <= '1';
addr <= inc_sp;
data <= b;
end procedure FlushB;
-- Do a simple stack push, it is performed in the internal cache registers,
-- not in the real memory.
procedure Push(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal a : in unsigned(WORD_SIZE-1 downto 0);
signal b : out unsigned(WORD_SIZE-1 downto 0)) is
begin
b <= a; -- Update cache [SP+1]=[SP]
sp <= sp-1;
end procedure Push;
-- Do a simple stack pop, it is performed in the internal cache registers,
-- not in the real memory.
procedure Pop(signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal a : out unsigned(WORD_SIZE-1 downto 0);
signal b : in unsigned(WORD_SIZE-1 downto 0)) is
begin
a <= b; -- Update cache [SP]=[SP+1]
sp <= sp+1;
end procedure Pop;
-- Expand a PC value to WORD_SIZE
function ExpandPC(v : unsigned(ADDR_W-1 downto 0)) return unsigned is
variable nv : unsigned(WORD_SIZE-1 downto 0);
begin
nv:=(others => '0');
nv(ADDR_W-1 downto 0):=v;
return nv;
end function ExpandPC;
-- Program counter
signal pc_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(ADDR_W-1 downto BYTE_BITS):=SP_START;
-- SP+1, SP+2 and SP-1 are very used, these are shortcuts
signal inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS);
signal inc_inc_sp : unsigned(ADDR_W-1 downto BYTE_BITS);
-- a_r is a cache for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_r : unsigned(WORD_SIZE-1 downto 0);
-- b_r is a cache for the next value in the stack [SP+1]
signal b_r : unsigned(WORD_SIZE-1 downto 0);
signal bin_op_res1_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal bin_op_res2_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal mult_res1_r : unsigned(WORD_SIZE-1 downto 0);
signal mult_res2_r : unsigned(WORD_SIZE-1 downto 0);
signal mult_res3_r : unsigned(WORD_SIZE-1 downto 0);
signal mult_a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal mult_b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
signal idim_r : std_logic;
signal write_en_r : std_logic;
signal read_en_r : std_logic;
signal addr_r : unsigned(ADDR_W-1 downto BYTE_BITS):=(others => '0');
signal fetched_w_r : unsigned(WORD_SIZE-1 downto 0);
type state_t is(st_load2, st_popped, st_load_sp2, st_load_sp3, st_add_sp2,
st_fetch, st_execute, st_decode, st_decode2, st_resync,
st_store_sp2, st_resync2, st_resync3, st_loadb2, st_storeb2,
st_mult2, st_mult3, st_mult5, st_mult4, st_binary_op_res2,
st_binary_op_res, st_idle);
signal state : state_t:=st_resync;
-- Go to st_fetch state or just do its work
procedure DoFetch(constant FAST : boolean;
signal state : out state_t;
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal pc : in unsigned(ADDR_W-1 downto 0);
signal re : out std_logic;
signal busy : in std_logic) is
begin
if FAST then
-- Equivalent to st_fetch
if busy='0' then
addr <= pc(ADDR_W-1 downto BYTE_BITS);
re <= '1';
state <= st_decode;
end if;
else
state <= st_fetch;
end if;
end procedure DoFetch;
-- Perform a "binary operation" (2 operands)
procedure DoBinOp(result : in unsigned(WORD_SIZE-1 downto 0);
signal state : out state_t;
signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal re : out std_logic;
signal dest : out unsigned(WORD_SIZE-1 downto 0);
signal dest_p : out unsigned(WORD_SIZE-1 downto 0);
constant DEPTH : natural) is
begin
if DEPTH=2 then
-- 2 clocks: st_binary_op_res+st_binary_op_res2
state <= st_binary_op_res;
dest_p <= result;
elsif DEPTH=1 then
-- 1 clock: st_binary_op_res2
state <= st_binary_op_res2;
dest_p <= result;
else -- 0 clocks
re <= '1';
addr <= sp+2;
sp <= sp+1;
dest <= result;
state <= st_popped;
end if;
end procedure DoBinOp;
-- Perform a boolean "binary operation" (2 operands)
procedure DoBinOpBool(result : in boolean;
signal state : out state_t;
signal sp : inout unsigned(ADDR_W-1 downto BYTE_BITS);
signal addr : out unsigned(ADDR_W-1 downto BYTE_BITS);
signal re : out std_logic;
signal dest : out unsigned(WORD_SIZE-1 downto 0);
signal dest_p : out unsigned(WORD_SIZE-1 downto 0);
constant DEPTH : natural) is
variable res : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
begin
if result then
res(0):='1';
end if;
DoBinOp(res,state,sp,addr,re,dest,dest_p,DEPTH);
end procedure DoBinOpBool;
type insn_t is (dec_add_top, dec_dup, dec_dup_stk_b, dec_pop, dec_add,
dec_or, dec_and, dec_store, dec_add_sp, dec_shift, dec_nop,
dec_im, dec_load_sp, dec_store_sp, dec_emulate, dec_load,
dec_push_sp, dec_pop_pc, dec_pop_pc_rel, dec_not, dec_flip,
dec_pop_sp, dec_neq_branch, dec_eq, dec_loadb, dec_mult,
dec_less_than, dec_less_than_or_equal, dec_lshr,
dec_u_less_than_or_equal, dec_u_less_than, dec_push_sp_add,
dec_call, dec_call_pc_rel, dec_sub, dec_break, dec_storeb,
dec_insn_fetch, dec_pop_down);
signal insn : insn_t;
type insn_array_t is array(0 to WORD_BYTES-1) of insn_t;
signal insns : insn_array_t;
type opcode_array_t is array(0 to WORD_BYTES-1) of unsigned(OPCODE_W-1 downto 0);
signal opcode_r : opcode_array_t;
begin
-- the memory subsystem will tell us one cycle later whether or
-- not it is busy
write_en_o <= write_en_r;
read_en_o <= read_en_r;
addr_o(ADDR_W-1 downto BYTE_BITS) <= addr_r;
addr_o(BYTE_BITS-1 downto 0) <= (others => '0');
-- SP+1 and +2
inc_sp <= sp_r+1;
inc_inc_sp <= sp_r+2;
opcode_control:
process (clk_i)
variable topcode : unsigned(OPCODE_W-1 downto 0);
variable ex_opcode : unsigned(OPCODE_W-1 downto 0);
variable sp_offset : unsigned(4 downto 0);
variable tsp_offset : unsigned(4 downto 0);
variable next_pc : unsigned(ADDR_W-1 downto 0);
variable tdecoded : insn_t;
variable tinsns : insn_array_t;
variable mult_res : unsigned(WORD_SIZE*2-1 downto 0);
variable ipc_low : integer range 0 to 3; -- Address inside a word (pc_r)
variable inpc_low : integer range 0 to 3; -- Address inside a word (next_pc)
variable h_bit : integer;
variable l_bit : integer;
variable not_lshr : std_logic:='1';
begin
if rising_edge(clk_i) then
break_o <= '0';
if reset_i='1' then
if ENA_IDLE then
state <= st_idle;
else
state <= st_resync;
end if;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
write_en_r <= '0';
read_en_r <= '0';
mult_a_r <= (others => '0');
mult_b_r <= (others => '0');
dbg_o.b_inst <= '0';
-- Reseting add_r here makes XST fail to use BRAMs ?!
else -- reset_i='1'
if MULT_PIPE then
-- We must multiply unconditionally to get pipelined multiplication
mult_res:=mult_a_r*mult_b_r;
mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
mult_res2_r <= mult_res1_r;
mult_res3_r <= mult_res2_r;
mult_a_r <= (others => D_CARE_VAL);
mult_b_r <= (others => D_CARE_VAL);
end if;
if BINOP_PIPE=2 then
bin_op_res2_r <= bin_op_res1_r; -- pipeline a bit.
end if;
read_en_r <='0';
write_en_r <='0';
-- Allow synthesis tools to load bogus values when we don't
-- care about the address and output data.
addr_r <= (others => D_CARE_VAL);
data_o <= (others => D_CARE_VAL);
if (write_en_r='1') and (read_en_r='1') then
report "read/write collision" severity failure;
end if;
ipc_low:=to_integer(pc_r(BYTE_BITS-1 downto 0));
sp_offset(4):=not opcode_r(ipc_low)(4);
sp_offset(3 downto 0):=opcode_r(ipc_low)(3 downto 0);
next_pc:=pc_r+1;
-- Prepare trace snapshot
dbg_o.opcode <= opcode_r(ipc_low);
dbg_o.pc <= resize(pc_r,32);
dbg_o.stk_a <= resize(a_r,32);
dbg_o.stk_b <= resize(b_r,32);
dbg_o.b_inst <= '0';
dbg_o.sp <= (others => '0');
dbg_o.sp(ADDR_W-1 downto BYTE_BITS) <= sp_r;
case state is
when st_idle =>
if enable_i='1' then
state <= st_resync;
end if;
-- Initial state of ZPU, fetch top of stack (A/B) + first instruction
when st_resync =>
if mem_busy_i='0' then
addr_r <= sp_r;
read_en_r <= '1';
state <= st_resync2;
end if;
when st_resync2 =>
if mem_busy_i='0' then
a_r <= data_i;
addr_r <= inc_sp;
read_en_r <= '1';
state <= st_resync3;
end if;
when st_resync3 =>
if mem_busy_i='0' then
b_r <= data_i;
addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
state <= st_decode;
end if;
when st_decode =>
if mem_busy_i='0' then
-- Here we latch the fetched word to give one full clock
-- cycle to the instruction decoder. This could be removed
-- if using BRAMs and the decoder delay isn't important.
fetched_w_r <= data_i;
state <= st_decode2;
end if;
when st_decode2 =>
-- decode 4 instructions in parallel
for i in 0 to WORD_BYTES-1 loop
topcode:=fetched_w_r((WORD_BYTES-1-i+1)*8-1 downto (WORD_BYTES-1-i)*8);
tsp_offset(4):=not topcode(4);
tsp_offset(3 downto 0):=topcode(3 downto 0);
opcode_r(i) <= topcode;
if topcode(7 downto 7)=OPCODE_IM then
tdecoded:=dec_im;
elsif topcode(7 downto 5)=OPCODE_STORESP then
if tsp_offset=0 then
-- Special case, we can avoid a write
tdecoded:=dec_pop;
elsif tsp_offset=1 then
-- Special case, collision
tdecoded:=dec_pop_down;
else
tdecoded:=dec_store_sp;
end if;
elsif topcode(7 downto 5)=OPCODE_LOADSP then
if tsp_offset=0 then
tdecoded:=dec_dup;
elsif tsp_offset=1 then
tdecoded:=dec_dup_stk_b;
else
tdecoded:=dec_load_sp;
end if;
elsif topcode(7 downto 5)=OPCODE_EMULATE then
tdecoded:=dec_emulate;
if ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_NEQBRANCH then
tdecoded:=dec_neq_branch;
elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_EQ then
tdecoded:=dec_eq;
elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_LOADB then
tdecoded:=dec_loadb;
elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_PUSHSPADD then
tdecoded:=dec_push_sp_add;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_LESSTHAN then
tdecoded:=dec_less_than;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_ULESSTHAN then
tdecoded:=dec_u_less_than;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_MULT then
tdecoded:=dec_mult;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_STOREB then
tdecoded:=dec_storeb;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_CALLPCREL then
tdecoded:=dec_call_pc_rel;
elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_SUB then
tdecoded:=dec_sub;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
tdecoded:=dec_less_than_or_equal;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
tdecoded:=dec_u_less_than_or_equal;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_CALL then
tdecoded:=dec_call;
elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_POPPCREL then
tdecoded:=dec_pop_pc_rel;
elsif ENA_LSHR and topcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
tdecoded:=dec_lshr;
end if;
elsif topcode(7 downto 4)=OPCODE_ADDSP then
if tsp_offset=0 then
tdecoded:=dec_shift;
elsif tsp_offset=1 then
tdecoded:=dec_add_top;
else
tdecoded:=dec_add_sp;
end if;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
tdecoded:=dec_break;
when OPCODE_PUSHSP =>
tdecoded:=dec_push_sp;
when OPCODE_POPPC =>
tdecoded:=dec_pop_pc;
when OPCODE_ADD =>
tdecoded:=dec_add;
when OPCODE_OR =>
tdecoded:=dec_or;
when OPCODE_AND =>
tdecoded:=dec_and;
when OPCODE_LOAD =>
tdecoded:=dec_load;
when OPCODE_NOT =>
tdecoded:=dec_not;
when OPCODE_FLIP =>
tdecoded:=dec_flip;
when OPCODE_STORE =>
tdecoded:=dec_store;
when OPCODE_POPSP =>
tdecoded:=dec_pop_sp;
when others => -- OPCODE_NOP and others
tdecoded:=dec_nop;
end case;
end if;
tinsns(i):=tdecoded;
end loop;
insn <= tinsns(ipc_low);
-- once we wrap, we need to fetch
tinsns(0):=dec_insn_fetch;
insns <= tinsns;
state <= st_execute;
-- Each instruction must:
--
-- 1. increase pc_r if applicable
-- 2. set next state if applicable
-- 3. do it's operation
when st_execute =>
-- Some shortcut to make the code readable:
inpc_low:=to_integer(next_pc(BYTE_BITS-1 downto 0));
ex_opcode:=opcode_r(ipc_low);
insn <= insns(inpc_low);
-- Defaults used by most instructions
if insn/=dec_insn_fetch and insn/=dec_im then
dbg_o.b_inst <= '1';
idim_r <= '0';
end if;
case insn is
when dec_insn_fetch =>
-- Not a real instruction, fetch new instructions
DoFetch(FAST_FETCH,state,addr_r,pc_r,read_en_r,mem_busy_i);
when dec_im =>
-- Push(immediate value), IDIM=1
-- if IDIM=0 Push(signed(opcode & 0x7F)) else
-- Push((Pop()<<7)|(opcode&0x7F))
if mem_busy_i='0' then
dbg_o.b_inst <= '1';
idim_r <= '1';
pc_r <= pc_r+1;
if idim_r='1' then
-- We already started an IM sequence
-- Shift left 7 bits
a_r(WORD_SIZE-1 downto 7) <= a_r(WORD_SIZE-8 downto 0);
-- Put the new value
a_r(6 downto 0) <= ex_opcode(6 downto 0);
else
-- First IM, push the value sign extended
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
a_r <= unsigned(resize(signed(ex_opcode(6 downto 0)),WORD_SIZE));
Push(sp_r,a_r,b_r);
end if;
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
if mem_busy_i='0' then
write_en_r <= '1';
addr_r <= sp_r+sp_offset;
data_o <= a_r;
Pop(sp_r,a_r,b_r);
-- We need to fetch B
state <= st_store_sp2;
end if;
when dec_load_sp =>
-- Push([SP+Offset])
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
Push(sp_r,a_r,b_r);
-- We are flushing B cache, so we need more time to
-- read the value.
state <= st_load_sp2;
end if;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_fetch;
a_r <= ExpandPC(pc_r+1);
Push(sp_r,a_r,b_r);
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= ex_opcode(4 downto 0);
end if;
when dec_call_pc_rel =>
-- t=Pop(), Push(PC+1), PC=PC+t
if mem_busy_i='0' and ENA_LEVEL1 then
state <= st_fetch;
a_r <= ExpandPC(pc_r+1);
pc_r <= pc_r+a_r(ADDR_W-1 downto 0);
end if;
when dec_call =>
-- t=Pop(), Push(PC+1), PC=t
if mem_busy_i='0' and ENA_LEVEL2 then
state <= st_fetch;
a_r <= ExpandPC(pc_r+1);
pc_r <= a_r(ADDR_W-1 downto 0);
end if;
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
if mem_busy_i='0' then
-- Read SP+Offset
state <= st_add_sp2;
read_en_r <= '1';
addr_r <= sp_r+sp_offset;
pc_r <= pc_r+1;
end if;
when dec_push_sp =>
-- Push(SP)
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
pc_r <= pc_r+1;
a_r <= (others => '0');
a_r(ADDR_W-1 downto BYTE_BITS) <= sp_r;
Push(sp_r,a_r,b_r);
end if;
when dec_pop_pc =>
-- PC=Pop() (return)
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_resync;
pc_r <= a_r(ADDR_W-1 downto 0);
sp_r <= inc_sp;
end if;
when dec_pop_pc_rel =>
-- PC=PC+Pop()
if mem_busy_i='0' and ENA_LEVEL2 then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_resync;
pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
sp_r <= inc_sp;
end if;
when dec_add =>
-- Push(Pop()+Pop()) [A=A+B, SP++, update B]
if mem_busy_i='0' then
state <= st_popped;
a_r <= a_r+b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
end if;
when dec_sub =>
-- a=Pop(), b=Pop(), Push(b-a)
if mem_busy_i='0' and ENA_LEVEL1 then
DoBinOp(b_r-a_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_pop =>
-- Pop()
if mem_busy_i='0' then
state <= st_popped;
addr_r <= inc_inc_sp;
read_en_r <= '1';
Pop(sp_r,a_r,b_r);
end if;
when dec_pop_down =>
-- t=Pop(), Pop(), Push(t)
if mem_busy_i='0' then
-- PopDown leaves top of stack unchanged
state <= st_popped;
addr_r <= inc_inc_sp;
read_en_r <= '1';
sp_r <= inc_sp;
end if;
when dec_or =>
-- Push(Pop() or Pop())
if mem_busy_i='0' then
state <= st_popped;
a_r <= a_r or b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
end if;
when dec_and =>
-- Push(Pop() and Pop())
if mem_busy_i='0' then
state <= st_popped;
a_r <= a_r and b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
end if;
when dec_eq =>
-- a=Pop(), b=Pop(), Push(a=b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL0 then
DoBinOpBool(a_r=b_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_u_less_than =>
-- a=Pop(), b=Pop(), Push(a<b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL1 then
DoBinOpBool(a_r<b_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_u_less_than_or_equal =>
-- a=Pop(), b=Pop(), Push(a<=b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL2 then
DoBinOpBool(a_r<=b_r,state,sp_r,addr_r,read_en_r,
a_r,bin_op_res1_r,BINOP_PIPE);
end if;
when dec_less_than =>
-- a=signed(Pop()), b=signed(Pop()), Push(a<b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL1 then
DoBinOpBool(signed(a_r)<signed(b_r),state,sp_r,
addr_r,read_en_r,a_r,bin_op_res1_r,
BINOP_PIPE);
end if;
when dec_less_than_or_equal =>
-- a=signed(Pop()), b=signed(Pop()), Push(a<=b ? 1 : 0)
if mem_busy_i='0' and ENA_LEVEL2 then
DoBinOpBool(signed(a_r)<=signed(b_r),state,sp_r,
addr_r,read_en_r,a_r,bin_op_res1_r,
BINOP_PIPE);
end if;
when dec_load =>
-- Push([Pop()])
if mem_busy_i='0' then
state <= st_load2;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
pc_r <= pc_r+1;
end if;
when dec_dup =>
-- t=Pop(), Push(t), Push(t)
if mem_busy_i='0' then
pc_r <= pc_r+1;
-- A is dupped, no change
Push(sp_r,a_r,b_r);
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
end if;
when dec_dup_stk_b =>
-- Pop(), t=Pop(), Push(t), Push(t), Push(t)
if mem_busy_i='0' then
pc_r <= pc_r+1;
a_r <= b_r;
-- B goes to A
Push(sp_r,a_r,b_r);
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
end if;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
if mem_busy_i='0' then
state <= st_resync;
pc_r <= pc_r+1;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
data_o <= b_r;
write_en_r <= '1';
sp_r <= inc_inc_sp;
end if;
when dec_pop_sp =>
-- SP=Pop()
if mem_busy_i='0' then
FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
state <= st_resync;
pc_r <= pc_r+1;
sp_r <= a_r(ADDR_W-1 downto BYTE_BITS);
end if;
when dec_nop =>
pc_r <= pc_r+1;
when dec_not =>
-- Push(not(Pop()))
pc_r <= pc_r+1;
a_r <= not a_r;
when dec_flip =>
-- Push(flip(Pop()))
pc_r <= pc_r+1;
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_r(WORD_SIZE-1-i);
end loop;
when dec_add_top =>
-- a=Pop(), b=Pop(), Push(b), Push(a+b)
pc_r <= pc_r+1;
a_r <= a_r+b_r;
when dec_shift =>
-- Push(Pop()<<1) [equivalent to a=Pop(), Push(a+a)]
pc_r <= pc_r+1;
a_r(WORD_SIZE-1 downto 1) <= a_r(WORD_SIZE-2 downto 0);
a_r(0) <= '0';
when dec_push_sp_add =>
-- Push(Pop()+SP)
if ENA_LEVEL0 then
pc_r <= pc_r+1;
a_r <= (others => '0');
a_r(ADDR_W-1 downto BYTE_BITS) <=
a_r(ADDR_W-1-BYTE_BITS downto 0)+sp_r;
end if;
when dec_neq_branch =>
-- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a
-- Branches are almost always taken as they form loops
if ENA_LEVEL0 then
sp_r <= inc_inc_sp;
-- Need to fetch stack again.
state <= st_resync;
if b_r/=0 then
pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
else
pc_r <= pc_r+1;
end if;
end if;
when dec_mult =>
-- Push(Pop()*Pop())
if ENA_LEVEL1 then
if MULT_PIPE then
mult_a_r <= a_r;
mult_b_r <= b_r;
state <= st_mult2;
else
mult_res:=a_r*b_r;
mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
state <= st_mult5;
end if;
end if;
when dec_break =>
-- Assert the break_o signal
--report "Break instruction encountered" severity failure;
break_o <= '1';
pc_r <= pc_r+1;
when dec_loadb =>
-- Push([Pop()] & 0xFF) (byte address)
if mem_busy_i='0' and ENA_LEVEL0 then
state <= st_loadb2;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
pc_r <= pc_r+1;
end if;
when dec_storeb =>
-- [Pop()]=Pop() & 0xFF (byte address)
if mem_busy_i='0' and ENA_LEVEL1 then
state <= st_storeb2;
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
pc_r <= pc_r+1;
end if;
when dec_lshr =>
-- a=Pop(), b=Pop(), Push(b>>(a&0x3F))
if ENA_LSHR then
-- This instruction takes more than one cycle.
-- We must avoid duplications in the trace log.
dbg_o.b_inst <= not_lshr;
not_lshr:='0';
if a_r(5 downto 0)=0 then -- Only 6 bits used
-- No more shifts
if mem_busy_i='0' then
state <= st_popped;
a_r <= b_r;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
not_lshr:='1';
end if;
else -- More shifts needed
b_r <= "0"&b_r(WORD_SIZE-1 downto 1);
a_r(5 downto 0) <= a_r(5 downto 0)-1;
insn <= insn;
end if;
end if;
when others =>
-- Undefined behavior, we shouldn't get here.
-- It only helps synthesis tools.
sp_r <= (others => D_CARE_VAL);
report "Illegal decode instruction?!" severity failure;
--break_o <= '1';
end case;
-- The followup of operations that takes more than one execution clock
when st_store_sp2 =>
if mem_busy_i='0' then
addr_r <= inc_sp;
read_en_r <= '1';
state <= st_popped;
end if;
when st_load_sp2 =>
if mem_busy_i='0' then
state <= st_load_sp3;
-- Now we can read SP+Offset (SP already decremented)
read_en_r <= '1';
addr_r <= sp_r+sp_offset+1;
end if;
when st_load_sp3 =>
if mem_busy_i='0' then
-- Note: We can't increment PC in the decode stage
-- because it will modify sp_offset.
pc_r <= pc_r+1;
-- Finally we have the result in A
state <= st_execute;
a_r <= data_i;
end if;
when st_add_sp2 =>
if mem_busy_i='0' then
state <= st_execute;
a_r <= a_r+data_i;
end if;
when st_load2 =>
if mem_busy_i='0' then
a_r <= data_i;
state <= st_execute;
end if;
when st_loadb2 =>
if mem_busy_i='0' then
a_r <= (others => '0');
-- Select the source bits using the less significant bits (byte address)
h_bit:=(WORD_BYTES-to_integer(a_r(BYTE_BITS-1 downto 0)))*8-1;
l_bit:=h_bit-7;
a_r(7 downto 0) <= data_i(h_bit downto l_bit);
state <= st_execute;
end if;
when st_storeb2 =>
if mem_busy_i='0' then
addr_r <= a_r(ADDR_W-1 downto BYTE_BITS);
data_o <= data_i;
-- Select the source bits using the less significant bits (byte address)
h_bit:=(WORD_BYTES-to_integer(a_r(BYTE_BITS-1 downto 0)))*8-1;
l_bit:=h_bit-7;
data_o(h_bit downto l_bit) <= b_r(7 downto 0);
write_en_r <= '1';
sp_r <= inc_inc_sp;
state <= st_resync;
end if;
when st_fetch =>
if mem_busy_i='0' then
addr_r <= pc_r(ADDR_W-1 downto BYTE_BITS);
read_en_r <= '1';
state <= st_decode;
end if;
-- The following states can be used to leave cycles free for
-- tools that can automagically decompose the multiplication
-- in various stages. Xilinx tools can do it to increase the
-- multipliers performance.
when st_mult2 =>
state <= st_mult3;
when st_mult3 =>
state <= st_mult4;
when st_mult4 =>
state <= st_mult5;
when st_mult5 =>
if mem_busy_i='0' then
if MULT_PIPE then
a_r <= mult_res3_r;
else
a_r <= mult_res1_r;
end if;
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
state <= st_popped;
end if;
when st_binary_op_res =>
-- BINOP_PIPE=2
state <= st_binary_op_res2;
when st_binary_op_res2 =>
-- BINOP_PIPE>=1
read_en_r <= '1';
addr_r <= inc_inc_sp;
sp_r <= inc_sp;
state <= st_popped;
if BINOP_PIPE=2 then
a_r <= bin_op_res2_r;
else -- 1
a_r <= bin_op_res1_r;
end if;
when st_popped =>
if mem_busy_i='0' then
-- Note: Moving this PC++ to the decoder seems to
-- consume more LUTs.
pc_r <= pc_r+1;
b_r <= data_i;
state <= st_execute;
end if;
when others =>
-- Undefined behavior, we shouldn't get here.
-- It only helps synthesis tools.
sp_r <= (others => D_CARE_VAL);
report "Illegal state?!" severity failure;
--break_o <= '1';
end case; -- state
end if; -- else reset_i='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
end architecture Behave; -- Entity: ZPUMediumCore
| gpl-3.0 | 31722287e545e5ade2cf8187d74e86e7 | 0.353985 | 4.612847 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/StateMachine.vhd | 1 | 1,565 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity StateMachine is
port (
clk : in std_logic;
nReset : in std_logic;
Dout : out std_logic_vector(7 downto 0); -- data read from ds1621
error : out std_logic; -- no correct ack received
SCL : inout std_logic;
SDA : inout std_logic
);
end entity StateMachine;
architecture structural of StateMachine is
---------------------------------------------------------------------------
YUVmachine: process (Hsync, Vsync, YUV_Cstate)
begin
case YUV_Cstate is
when "000" =>
YUV_Nstate <="001";
YUVclk<= '0';
Yclk<='0';
Uclk<='0';
Y1clk<='0';
Vclk<='0';
when "001" =>
YUV_Nstate <="010";
YUVclk<='1' ; --and Hsync;
Yclk<='1';
Uclk<='0';
Y1clk<='0';
Vclk<='0';
when "010" =>
YUV_Nstate <="011";
YUVclk<='0';
Yclk<='0';
Uclk<='1';
Y1clk<='0';
Vclk<='0';
when "011" =>
YUV_Nstate <="100";
YUVclk<='0';
Yclk<='0';
Uclk<='0';
Y1clk<='1';
Vclk<='0';
when "100" =>
YUV_Nstate <="001";
YUVclk<='0';
Yclk<='0';
Uclk<='0';
Y1clk<='0';
Vclk<='1';
when others =>
Yclk<='0';
Uclk<='0';
Y1clk<='0';
Vclk<='0';
YUV_Nstate <="001";
YUVclk<='0';
end case;
-- genregs
if (Hsync='0') then
YUV_Cstate <="000";
elsif (clk'event) and (clk = '0') then -- PC 04.08.06 was '1'
YUV_Cstate<=YUV_Nstate;
end if;
end process structural;
--------------------------------------------------------------------------- | gpl-2.0 | 237116d3bb19582b70488421c818ae87 | 0.478594 | 2.87156 | false | false | false | false |
KB777/1541UltimateII | fpga/cart_slot/vhdl_source/cart_slot_pkg.vhd | 1 | 2,740 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package cart_slot_pkg is
constant c_cart_c64_mode : unsigned(3 downto 0) := X"0";
constant c_cart_c64_stop : unsigned(3 downto 0) := X"1";
constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2";
constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3";
constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4";
constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5";
constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6";
constant c_cart_cartridge_active : unsigned(3 downto 0) := X"6";
constant c_cart_kernal_enable : unsigned(3 downto 0) := X"7";
constant c_cart_reu_enable : unsigned(3 downto 0) := X"8";
constant c_cart_reu_size : unsigned(3 downto 0) := X"9";
constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A";
constant c_cart_timing : unsigned(3 downto 0) := X"B";
constant c_cart_phi2_recover : unsigned(3 downto 0) := X"C";
constant c_cart_sampler_enable : unsigned(3 downto 0) := X"E";
constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F";
type t_cart_control is record
c64_reset : std_logic;
c64_nmi : std_logic;
c64_ultimax : std_logic;
c64_stop : std_logic;
c64_stop_mode : std_logic_vector(1 downto 0);
cartridge_type : std_logic_vector(3 downto 0);
cartridge_kill : std_logic;
kernal_enable : std_logic;
reu_enable : std_logic;
reu_size : std_logic_vector(2 downto 0);
eth_enable : std_logic;
sampler_enable : std_logic;
swap_buttons : std_logic;
timing_addr_valid : unsigned(2 downto 0);
phi2_edge_recover : std_logic;
tick_ntsc : std_logic;
end record;
type t_cart_status is record
c64_stopped : std_logic;
clock_detect : std_logic;
cart_active : std_logic;
end record;
constant c_cart_control_init : t_cart_control := (
c64_nmi => '0',
c64_reset => '0',
c64_ultimax => '0',
c64_stop => '0',
c64_stop_mode => "00",
cartridge_type => X"0",
cartridge_kill => '0',
kernal_enable => '0',
reu_enable => '0',
reu_size => "111",
eth_enable => '0',
sampler_enable => '0',
timing_addr_valid => "100",
phi2_edge_recover => '1',
swap_buttons => '1',
tick_ntsc => '0' );
end cart_slot_pkg;
| gpl-3.0 | 66920f906d2dc36e94956d92e2703c20 | 0.529927 | 3.120729 | false | false | false | false |
chriz2600/DreamcastHDMI | Core/source/adv7513/i2c_master.vhd | 1 | 14,369 | --------------------------------------------------------------------------------
--
-- FileName: i2c_master.vhd
-- Dependencies: none
-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
--
-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
--
-- Version History
-- Version 1.0 11/01/2012 Scott Larson
-- Initial Public Release
-- Version 2.0 06/20/2014 Scott Larson
-- Added ability to interface with different slaves in the same transaction
-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
-- Corrected timing of when ack_error signal clears
-- Version 2.1 10/21/2014 Scott Larson
-- Replaced gated clock with clock enable
-- Adjusted timing of SCL during start and stop conditions
-- Version 2.2 02/05/2015 Scott Larson
-- Corrected small SDA glitch introduced in version 2.1
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY i2c_master IS
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --active low reset
ena : IN STD_LOGIC; --latch in command
addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
rw : IN STD_LOGIC; --'0' is write, '1' is read
data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
busy : OUT STD_LOGIC; --indicates transaction in progress
data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
sda : INOUT STD_LOGIC; --serial data output of i2c bus
scl : INOUT STD_LOGIC; --serial clock output of i2c bus
divider : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
END i2c_master;
ARCHITECTURE logic OF i2c_master IS
TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
SIGNAL state : machine; --state machine
SIGNAL data_clk : STD_LOGIC; --data clock for sda
SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
BEGIN
--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
PROCESS(clk, reset_n)
VARIABLE count : INTEGER RANGE 0 TO 255; --timing for clock generation
BEGIN
IF(reset_n = '0') THEN --reset asserted
stretch <= '0';
count := 0;
ELSIF(clk'EVENT AND clk = '1') THEN
data_clk_prev <= data_clk; --store previous value of data clock
IF(count = divider(31 downto 24)-1) THEN --end of timing cycle
count := 0; --reset timer
ELSIF(stretch = '0') THEN --clock stretching from slave not detected
count := count + 1; --continue clock generation timing
END IF;
IF(count < divider(7 downto 0)) THEN
scl_clk <= '0';
data_clk <= '0';
ELSIF(count < divider(15 downto 8)) THEN
scl_clk <= '0';
data_clk <= '1';
ELSIF(count < divider(23 downto 16)) THEN
scl_clk <= '1'; --release scl
IF(scl = '0') THEN --detect if slave is stretching clock
stretch <= '1';
ELSE
stretch <= '0';
END IF;
data_clk <= '1';
ELSE
scl_clk <= '1';
data_clk <= '0';
END IF;
-- IF(count < div1) THEN
-- scl_clk <= '0';
-- data_clk <= '0';
-- ELSIF(count < div2) THEN
-- scl_clk <= '0';
-- data_clk <= '1';
-- ELSIF(count < div3) THEN
-- scl_clk <= '1'; --release scl
-- IF(scl = '0') THEN --detect if slave is stretching clock
-- stretch <= '1';
-- ELSE
-- stretch <= '0';
-- END IF;
-- data_clk <= '1';
-- ELSE
-- scl_clk <= '1';
-- data_clk <= '0';
-- END IF;
END IF;
END PROCESS;
--state machine and writing to sda during scl low (data_clk rising edge)
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --reset asserted
state <= ready; --return to initial state
busy <= '1'; --indicate not available
scl_ena <= '0'; --sets scl high impedance
sda_int <= '1'; --sets sda high impedance
ack_error <= '0'; --clear acknowledge error flag
bit_cnt <= 7; --restarts data bit counter
data_rd <= "00000000"; --clear data read port
ELSIF(clk'EVENT AND clk = '1') THEN
IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
CASE state IS
WHEN ready => --idle state
IF(ena = '1') THEN --transaction requested
busy <= '1'; --flag busy
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
state <= start; --go to start bit
ELSE --remain idle
busy <= '0'; --unflag busy
state <= ready; --remain idle
END IF;
WHEN start => --start bit of transaction
busy <= '1'; --resume busy if continuous mode
sda_int <= addr_rw(bit_cnt); --set first address bit to bus
state <= command; --go to command
WHEN command => --address and command byte of transaction
IF(bit_cnt = 0) THEN --command transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack1; --go to slave acknowledge (command)
ELSE --next clock cycle of command state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
state <= command; --continue with command
END IF;
WHEN slv_ack1 => --slave acknowledge bit (command)
IF(addr_rw(0) = '0') THEN --write command
sda_int <= data_tx(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --read command
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
END IF;
WHEN wr => --write byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --write byte transmit finished
sda_int <= '1'; --release sda for slave acknowledge
bit_cnt <= 7; --reset bit counter for "byte" states
state <= slv_ack2; --go to slave acknowledge (write)
ELSE --next clock cycle of write state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
sda_int <= data_tx(bit_cnt-1); --write next bit to bus
state <= wr; --continue writing
END IF;
WHEN rd => --read byte of transaction
busy <= '1'; --resume busy if continuous mode
IF(bit_cnt = 0) THEN --read byte receive finished
IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
sda_int <= '0'; --acknowledge the byte has been received
ELSE --stopping or continuing with a write
sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
END IF;
bit_cnt <= 7; --reset bit counter for "byte" states
data_rd <= data_rx; --output received data
state <= mstr_ack; --go to master acknowledge
ELSE --next clock cycle of read state
bit_cnt <= bit_cnt - 1; --keep track of transaction bits
state <= rd; --continue reading
END IF;
WHEN slv_ack2 => --slave acknowledge bit (write)
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another write
sda_int <= data_wr(bit_cnt); --write first bit of data
state <= wr; --go to write byte
ELSE --continue transaction with a read or new slave
state <= start; --go to repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN mstr_ack => --master acknowledge bit after a read
IF(ena = '1') THEN --continue transaction
busy <= '0'; --continue is accepted and data received is available on bus
addr_rw <= addr & rw; --collect requested slave address and command
data_tx <= data_wr; --collect requested data to write
IF(addr_rw = addr & rw) THEN --continue transaction with another read
sda_int <= '1'; --release sda from incoming data
state <= rd; --go to read byte
ELSE --continue transaction with a write or new slave
state <= start; --repeated start
END IF;
ELSE --complete transaction
state <= stop; --go to stop bit
END IF;
WHEN stop => --stop bit of transaction
busy <= '0'; --unflag busy
state <= ready; --go to idle state
END CASE;
ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
CASE state IS
WHEN start =>
IF(scl_ena = '0') THEN --starting new transaction
scl_ena <= '1'; --enable scl output
ack_error <= '0'; --reset acknowledge error output
END IF;
WHEN slv_ack1 => --receiving slave acknowledge (command)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN rd => --receiving slave data
data_rx(bit_cnt) <= sda; --receive current slave data bit
WHEN slv_ack2 => --receiving slave acknowledge (write)
IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
ack_error <= '1'; --set error output if no-acknowledge
END IF;
WHEN stop =>
scl_ena <= '0'; --disable scl
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END IF;
END PROCESS;
--set sda output
WITH state SELECT
sda_ena_n <= data_clk_prev WHEN start, --generate start condition
NOT data_clk_prev WHEN stop, --generate stop condition
sda_int WHEN OTHERS; --set to internal sda signal
--set scl and sda outputs
scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
END logic;
| mit | 33df74e6f3fe7cfc0c9a808549d080f0 | 0.482845 | 4.627697 | false | false | false | false |
Sourangsu/RAM-Arbiter-VHDL-Code | ARBITER_NEW.vhd | 1 | 12,781 | Library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------
-- Entity for ARBITER
-------------------------------------------------------------------------
entity ARBITER_NEW is
generic
(
-------------------------------------------------------------------------
-- Generics for scalability
-------------------------------------------------------------------------
G_ADDR_WIDTH: integer := 4;
G_DATA_WIDTH: integer := 8;
G_REGISTERED_DATA: integer :=0
-- G_ADDR_WIDTH = Number of bits required to address the ram
-- G_DATA_WIDTH = Number of bits in a data
-- G_REGISTERED_DATA =1 for registered data in output 0 for nonregistered
-------------------------------------------------------------------------
);
port
(
-------------------------------------------------------------------------
-- General Inputs And Output
-------------------------------------------------------------------------
RST_N: in std_logic;
CLOCK: in std_logic;
RST_DONE: out std_logic;
-------------------------------------------------------------------------
-- Inputs from --------client1--------------
-------------------------------------------------------------------------
RD_EN_C1: in std_logic; --read enb--
WR_EN_C1: in std_logic; --write enb--
RDADDR_C1: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--read addr---
WRADDR_C1: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--write addr--
WRDATA_C1: in std_logic_vector(G_DATA_WIDTH-1 downto 0);--data in----
-------------------------------------------------------------------------
-- Inputs from --------client2--------------
-------------------------------------------------------------------------
DATAIN_C2: in std_logic_vector(G_DATA_WIDTH-1 downto 0);--input data--
REQUEST_C2: in std_logic; --request to access memory--
RD_NOT_WRITE_C2: in std_logic; --if '0' then write or read--
ADDR_C2: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--addr for rd or wr--
-------------------------------------------------------------------------
--output from --------client1--------------
-------------------------------------------------------------------------
RDDATA_C1: out std_logic_vector(G_DATA_WIDTH-1 downto 0);--data out--
-------------------------------------------------------------------------
--output from --------client2--------------
-------------------------------------------------------------------------
DATAOUT_C2: out std_logic_vector(G_DATA_WIDTH-1 downto 0);--out data--
ACK_C2: out std_logic; --acknowlwdgement--
-------------------------------------------------------------------------
-- Others Input And Output
-------------------------------------------------------------------------
RD_EN: out std_logic;
WR_EN: out std_logic;
WR_ADDR: out std_logic_vector(G_ADDR_WIDTH-1 downto 0);
RD_ADDR: out std_logic_vector(G_ADDR_WIDTH-1 downto 0);
WR_DATA: out std_logic_vector(G_DATA_WIDTH-1 downto 0);
RD_DATA: in std_logic_vector(G_DATA_WIDTH-1 downto 0));
end ARBITER_NEW;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- Architecture for ARBITER
-------------------------------------------------------------------------
architecture RTL of ARBITER_NEW is
--------------Temporary registers-------------------
signal TEMP_RD_DATA: std_logic_vector(G_DATA_WIDTH-1 downto 0);
signal TEMP_RD_DATA1: std_logic_vector(G_DATA_WIDTH-1 downto 0);
signal TEMP_RD_DATA2: std_logic_vector(G_DATA_WIDTH-1 downto 0);
signal TEMP_RD_EN: std_logic;
signal TEMP_WR_EN: std_logic;
signal TEMP_WR_ADDR: std_logic_vector(G_ADDR_WIDTH-1 downto 0);
signal TEMP_RD_ADDR: std_logic_vector(G_ADDR_WIDTH-1 downto 0);
signal TEMP_WR_DATA: std_logic_vector(G_DATA_WIDTH-1 downto 0);
-------------Client type and state for FSM-----------
type client is (reset,idle,client1_read,client2_read,client1_write,client2_write);
signal pr_client_read: client; --present client read-
signal pr_client_write: client; --present client write-
signal nx_client_read: client; --next client read--
signal nx_client_write: client; --next client write--
-------------Acknowledgement reg for client2---------
signal TEMP_ACK: std_logic:='0';
signal TEMP_ACK1: std_logic;
signal TEMP_ACK2: std_logic;
signal TEMP_WR: std_logic:='0';
signal TEMP_WR1: std_logic;
------------Generic consideration-------------------------------
signal REGISTERED_DATA: integer range 0 to 1 :=0;
------------Reset done generation Counter & register-----------
signal RESET_DONE_REG: std_logic;
signal COUNT: integer range 0 to 2**G_ADDR_WIDTH-1:=0;
------------Address Clash check register-----------------------
signal ADDR_CLASHI: std_logic:='0';
signal ADDR_CLASH: std_logic:='0';
begin
-------------------------------------------------------------------------
--FSM for ARBITER
-------------------------------------------------------------------------
-------------------------------------------------
-------sequential section & reset condition- ----
-------------------------------------------------
p1:process(RST_N,CLOCK)
begin
if (RST_N='0') then
pr_client_read <= reset;
pr_client_write <= reset;
elsif (CLOCK'EVENT and CLOCK='1' ) then
pr_client_read <= nx_client_read;
pr_client_write <= nx_client_write;
end if;
end process;
---------------------------------------------------
--------Generate for registered data-------
---------------------------------------------------
g1: if (G_REGISTERED_DATA=1) generate
REGISTERED_DATA<=G_REGISTERED_DATA;
end generate g1;
---------------------------------------------------
---------combinational section & client state------
---------------------------------------------------
p2:process(pr_client_read,pr_client_write,clock)
begin
if(RST_N='1' and clock='1')then
if(nx_client_read=reset and nx_client_write=reset)then
if(count<(2**G_ADDR_WIDTH))then
RESET_DONE_REG <= '0';
count<=count+1;
else
nx_client_read <= idle;
nx_client_write <= idle;
RESET_DONE_REG <= '1';
count<=0;
end if;
end if;
elsif(RST_N='0') then
nx_client_read <= reset;
nx_client_write<=reset;
end if;
if(pr_client_read=idle)then ----when arbiter idle--
if(RD_EN_C1='0')then
if(REQUEST_C2='0')then
nx_client_read<= idle;
elsif(RD_NOT_WRITE_C2='1')then
nx_client_read<= client2_read;
elsif(RD_NOT_WRITE_C2='0')then
nx_client_write<= client2_write;
end if;
else
nx_client_read <=client1_read;
end if;
end if;
if(pr_client_write=idle)then
if( WR_EN_C1='0')then
if(REQUEST_C2='0')then
nx_client_write<= idle;
elsif(RD_NOT_WRITE_C2='0')then
nx_client_write<= client2_write;
elsif(RD_NOT_WRITE_C2='1')then
nx_client_read<= client2_read;
end if;
else
nx_client_write <=client1_write;
end if;
end if;----------------------------------------------------------
if(pr_client_read=client1_read)then -----when arbiter allow client 1---
if(RD_EN_C1='1')then
nx_client_read <=client1_read;
else
if(REQUEST_C2='0')then
nx_client_read<= idle;
elsif(RD_NOT_WRITE_C2='1')then
nx_client_read<= client2_read;
elsif(RD_NOT_WRITE_C2='0')then
nx_client_read<= idle;
end if;
end if;
end if;
if(pr_client_write=client1_write)then
if(WR_EN_C1='1')then
nx_client_write <=client1_write;
else
if(REQUEST_C2='0')then
nx_client_write<= idle;
elsif(RD_NOT_WRITE_C2='0')then
nx_client_write<= client2_write;
elsif(RD_NOT_WRITE_C2='1')then
nx_client_write<= idle;
end if;
end if;
end if;----------------------------------------------------------------------
if(pr_client_read=client2_read)then ------when arbiter allow client 2-----
if(RD_EN_C1='0')then
if(REQUEST_C2='1')then
if( RD_NOT_WRITE_C2='1')then
nx_client_read<= client2_read;
else
nx_client_read<=idle;
nx_client_write<= client2_write;
end if;
else
nx_client_read<=idle;
end if;
else
nx_client_read <=client1_read;
end if;
end if;
if(pr_client_write=client2_write)then
if(WR_EN_C1='0')then
if(REQUEST_C2='1')then
if( RD_NOT_WRITE_C2='0')then
nx_client_write<= client2_write;
else
nx_client_write<=idle;
nx_client_read<= client2_read;
end if;
else
nx_client_write<=idle;
end if;
else
nx_client_write <=client1_write;
end if;
end if;
-------------------------------------------------------------------------
end process;
-------------------------------------------------------------------------
--Assigning Temp Registers according to the client----------------
-------------------------------------------------------------------------
pram:process(CLOCK)
begin
---------------------------------------------------
----------------Read & Write operation ------------
---------------------------------------------------
if(RST_N = '0')then
TEMP_RD_DATA <= (others =>'0');
TEMP_RD_DATA1 <= (others =>'0');
TEMP_RD_DATA2 <= (others =>'0');
elsif(CLOCK'EVENT and CLOCK='1')then
if(nx_client_read = idle)then
TEMP_RD_EN<='0';
TEMP_RD_ADDR<=(others =>'0');
elsif (nx_client_read=client1_read)then
TEMP_RD_EN <= RD_EN_C1;
TEMP_RD_ADDR <= RDADDR_C1;
elsif(nx_client_read=client2_read)then
if(TEMP_ACK='0')then
TEMP_RD_EN <= '1';
TEMP_RD_ADDR<= ADDR_C2;
TEMP_ACK <= '1';
end if;
end if;
if(nx_client_write = idle)then
TEMP_WR_EN <= '0';
TEMP_WR_DATA <= (others =>'0');
TEMP_WR_ADDR <= (others =>'0');
elsif (nx_client_write=client1_write)then
TEMP_WR_EN <= WR_EN_C1;
TEMP_WR_DATA <= WRDATA_C1;
TEMP_WR_ADDR <= WRADDR_C1;
elsif(nx_client_write=client2_write)then
if(TEMP_WR='0')then
TEMP_WR_EN <= '1';
TEMP_WR_ADDR <= ADDR_C2;
TEMP_WR_DATA <= DATAIN_C2;
TEMP_WR <= '1';
end if;
end if;
-------------------------------------------
-----If Addr Clash occurs -------
-------------------------------------------
if (TEMP_RD_EN='1' and TEMP_WR_EN ='1') then
if(TEMP_WR_ADDR = TEMP_RD_ADDR )then
ADDR_CLASH <='1';
TEMP_RD_DATA<=TEMP_WR_DATA;
else
ADDR_CLASH <='0';
end if;
else
ADDR_CLASH <='0';
end if;
----------------------------------------------
if(TEMP_WR1='1')then ------For ACK generation during client2_Write------
TEMP_WR<='0';
end if;
TEMP_ACK1<=TEMP_ACK; ------For ACK generation during client2_Read------
if(TEMP_ACK1='1')then
TEMP_ACK1<='0';
TEMP_ACK<='0';
end if; -----------------------------------------------------
ADDR_CLASHI<=ADDR_CLASH;---One clock cycle delay in addr clash for Registered data-----
TEMP_RD_DATA1<=TEMP_RD_DATA;---One clock cycle delay in output for Registered data with addr clash -----
TEMP_RD_DATA2<=RD_DATA; ---One clock cycle delay in output for Registered data without addr clash -----
end if;
end process;
-------------------------------------------------------------------------
--------Data in out put from temp registers---------
-------------------------------------------------------------------------
RD_EN<= TEMP_RD_EN;
WR_EN<= TEMP_WR_EN;
WR_DATA<=TEMP_WR_DATA;
WR_ADDR<=TEMP_WR_ADDR;
RD_ADDR<=TEMP_RD_ADDR;
-------------------------------------------------------------------------
TEMP_WR1<=TEMP_WR;-----For ACK generation during client2_write--------
ACK_C2<='1' when (TEMP_ACK1='1' or TEMP_WR1='1') else '0';--output ACK generation during client2_write and read---
RST_DONE<=RESET_DONE_REG; ----------Indication for reset compleate----
-------------------------------------------------------------------------
-----------------Data out for client 2 ----------------
-------------------------------------------------------------------------
DATAOUT_C2<=RD_DATA when (ADDR_CLASH='0') else
TEMP_RD_DATA;
-------------------------------------------------------------------------
-----------------------Data out for client 1------- ---------
-------------------------------------------------------------------------
RDDATA_C1<=RD_DATA when (REGISTERED_DATA =0 and ADDR_CLASH='0' ) else
TEMP_RD_DATA when (REGISTERED_DATA =0 and ADDR_CLASH='1' ) else
TEMP_RD_DATA2 when (REGISTERED_DATA =1 and ADDR_CLASHI='0' ) else
TEMP_RD_DATA1 when (REGISTERED_DATA =1 and ADDR_CLASHI='1' );
end RTL;
| bsd-3-clause | 59b098a4f0ce419186db29b6004fb973 | 0.457789 | 3.852019 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_sim/char_generator_tb.vhd | 5 | 1,699 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity char_generator_tb is
end;
architecture tb of char_generator_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_req : t_io_req := c_io_req_init;
signal io_resp : t_io_resp;
signal h_sync : std_logic := '0';
signal v_sync : std_logic := '0';
signal pixel_active : std_logic;
signal pixel_data : std_logic;
begin
clock <= not clock after 35714 ps;
reset <= '1', '0' after 100 ns;
i_char_gen: entity work.char_generator
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
h_sync => h_sync,
v_sync => v_sync,
pixel_active => pixel_active,
pixel_data => pixel_data );
end tb;
| gpl-3.0 | 90e6d78095aa10830523ff9285727c9d | 0.390818 | 4.542781 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/SyncProcessor.vhd | 1 | 9,015 | --*****************************************
-- (c) Phil Culverhouse, 2006
--
-- All rights reserved
--
-- CHANGES:
-- 30.06.07 increased CoulumnCounter to 11 bits to avoid overflo during row
-- 30.06.07 added Hsync to AccumulateSignal to avoid accumulating pixels outside of Href
-- 02.07.07 fixed bug in YUV state machine allocated wrong timing to pixel enables
--
--********************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- not both this and below -- USE ieee.std_logic_arith.all;
--use IEEE.numeric_bit.all; -- for integer to bit_vector conversion
use IEEE.numeric_std.all; -- for integer to bit_vector conversion
-- VGA std format 640 by 480 pixels in a frame
-- register them, count line by line
--
ENTITY SyncProcessor IS
PORT
(
Clk : IN std_logic;
Vsync : IN std_logic;
Hsync : IN std_logic;
TrainFlag : IN std_logic; -- from debounced user switch input
Aclr : IN std_logic; -- hold decode of pixel colour 01==red, 10==green, 11==blue
YUV : out unsigned (2 downto 0); -- values R, G and B 4 pixels in a stream 000 is only set during Vsync
Row : out unsigned (8 downto 0); -- 480 == 256+128+64 ie. "111100000"
Column : out unsigned (10 downto 0); -- 640 == 512+128 ie. "1010000000"
AccumulateSIGNAL : out std_logic; -- is HIGH during hysnc's within a frame, reset by Vsync
CalculateSIGNAL : out std_logic; -- is HIGH during gap between last hysnc in a frame, reset by Vsync
FirstROW : out std_logic; -- true for first row in frame
LastROW : out std_logic; -- true for last row in frame
WindowROW : out std_logic; -- true for valid ROWs in specified processing window
WindowCOLUMN: out std_logic; -- true for valid COLUMNs in specified processing window
TrainFLAGsynced:out std_logic; -- the user input TrainFLAG now sync'd to one frame only
YUVclk: out std_logic;
Yclk: out std_logic;
Uclk: out std_logic;
Y1clk: out std_logic;
Vclk: out std_logic -- BGRG pixel seq.
);
END SyncProcessor;
-- first register the pixel stream
ARCHITECTURE SyncProcessor_v1 OF SyncProcessor IS
constant VGAmaxROW: natural := 480;
constant VGAmaxCOLUMN: natural := 640*2; -- 1280 pixels in a line (UY for pixel N and then VY for pixel N+1)
--##########################################################################################
-- processing window size
constant RwinSTARTc: natural := (VGAmaxROW/2)-3; -- was -50; -- for inverted connector, but upright camera --(240-25);
constant RwinENDc: natural := (VGAmaxROW/2)+3; --(240+25);
constant CwinSTARTc: natural := ((VGAmaxCOLUMN/2)-12);-- centre of FOV
constant CwinENDc: natural := ((VGAmaxCOLUMN/2)+12);
--##########################################################################################
shared variable FrameCounter: natural :=0; -- counts frames up to limit of integer range
signal YUV_Cstate, YUV_Nstate: unsigned (2 downto 0); -- natural range 0 to 3; -- was unsigned (2 downto 0);
signal RowCounter : natural range 0 to VGAmaxROW; --was unsigned (8 downto 0);
signal ColumnCounter: natural range 0 to VGAmaxCOLUMN; -- was unsigned (9 downto 0);
signal LastROWint: std_logic; -- true for last row in frame
signal RowCENTRE,ColumnCENTRE: std_logic;
signal INFrameFLAGint: std_logic; -- '1' for all Hsync rows in a frame
signal CalculateSIGNALint: std_logic;
signal STOP: std_logic :='1'; -- used to enable the counter, hence cleared to stop it.
signal TrainFLAGstart,resetFLAG: std_logic; -- sync's start of training with Vsync
signal TrainDELAYED, TrainDELAYEDmore: std_logic;
component dff port(d,clk,clrn,prn:in std_logic; q:out std_logic);end component;
BEGIN
Row <= to_unsigned(Rowcounter,9); -- was RowCounter ; -- WAS (to_unsigned(Rowcounter,9)); -- convert integer to bit_vector!
---PC 30.06.07 Column <= to_unsigned(Columncounter,10); -- was ColumnCounter; -- was (to_unsigned(Columncounter,10));
Column <= to_unsigned(Columncounter,11); -- was ColumnCounter; -- was (to_unsigned(Columncounter,10));
YUV <= YUV_Cstate; -- was to_unsigned(YUVcounter,3); --- was YUVcounter;
LastROW <= LastROWint and Hsync; -- ensure it does not stay true until next Vsync.
-- now the sequencer for generating the syncronised TrainFLAG to ensure TrainFLAG only lasts one frame
u1: dff port map('1',TrainFLAG,not(STOP),'1',TrainDELAYED);-- train for one frame only
u2: dff port map(TrainDELAYED,Vsync, not(STOP),'1',TrainDELAYEDmore);-- train for one frame only
u3: dff port map(TrainDELAYEDmore,Vsync, '1','1',STOP);-- train for one frame only
TrainFLAGsynced <= TrainDELAYEDmore; -- debug
--PC 30.06.07 AccumulateSIGNAL <= INFrameFLAGint and not(Vsync) and (not(CalculateSIGNALint)); -- (not(LastROWint and INFrameFLAGint)); -- ensure it does not stay true until next Vsync.
AccumulateSIGNAL <= INFrameFLAGint and not(Vsync) and (not(CalculateSIGNALint)) and Hsync; -- (not(LastROWint and INFrameFLAGint)); -- ensure it does not stay true until next Vsync.
u4: dff port map('1',LastROWint, INFrameFLAGint,'1',CalculateSIGNALint);-- train for one frame only
CalculateSIGNAL <= CalculateSIGNALint; -- LastROWint and INFrameFLAGint; -- ensure it does not stay true until next Vsync.
-- sequential processes belowand Hsync; -- (not(LastROWint and INFrameFLAGint)); --
---------------------------------------------------------------------------
SYNC: PROCESS (Clk, Hsync)
BEGIN
if (Clk'event) and (Clk = '1') then -- PC 04.08.06 was '1'
if (Hsync = '1') then
ColumnCounter <= ColumnCounter + 1;
elsif (Hsync = '0')then
ColumnCounter <= 0;
end if;
end if;
END PROCESS SYNC ;
---------------------------------------------------------------------------
HsyncCOUNT: process (Hsync, Vsync, Rowcounter)
begin
if (Hsync'event) and (Hsync = '1') then -- increment row counter every line
RowCounter <= RowCounter +1;
INframeFLAGint <= '1';
if RowCounter > VGAmaxROW then
RowCounter <= 0;
end if;
end if;
if (Vsync = '1') then
RowCounter <= 0; --"000000000";
INframeFLAGint <= '0';
FirstROW <= '0';
LastROWint <= '0';
end if;
case RowCounter is
when 1 =>
FirstROW <= '1';
LastROWint <= '0';
when VGAmaxROW =>
FirstROW <= '0';
LastROWint <= '1';
when others =>
FirstROW <= '0';
LastROWint <= '0';
end case;
end process HsyncCOUNT;
---------------------------------------------------------------------------
VsyncCOUNT: process (Vsync)
begin
if (Vsync'event) and (Vsync = '1') then -- increment row counter every line
Framecounter := Framecounter +1;
end if;
end process VsyncCOUNT;
---------------------------------------------------------------------------
-- used to output a centre of frame pulse FOR TRAINING
RowPULSE: process (RowCounter, Hsync)
begin
if (RowCounter >= RwinSTARTc)and (RowCounter <= RwinENDc) then --and (Hsync= '1') then --240
WindowROW <= '1';
else
WindowROW <= '0';
end if;
end process RowPULSE;
---------------------------------------------------------------------------
ColumnPULSE: process (ColumnCounter, Hsync)
begin
if (ColumnCounter >= CwinSTARTc) and (ColumnCounter <= CwinENDc) then -- was and (Hsync = '1') then --1
WindowCOLUMN <= '1';
else
WindowCOLUMN <= '0';
end if;
end process ColumnPULSE;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
YUVCLOCK: process (clk, Hsync, YUV_Nstate) -- clk pixels on 4th pixel, so they are stable for 4 pixel clks.
begin
if (Hsync='0') then
YUV_Cstate <="000";
elsif (clk'event) and (clk = '1') then -- PC 03.07.07 was '0', as pixels change on falling edge, but FSM must change with regstered pixels
YUV_Cstate<=YUV_Nstate;
end if;
end process YUVCLOCK;
---------------------------------------------------------------------------
YUVmachine: process (Vsync, YUV_Cstate) -- clk pixels on 4th pixel, so they are stable for 4 pixel clks.
begin -- 02.07.07 changed Yclk, Uclk, Vclk, Y1clk etc below to correctly reflect pixel data order in stream from camera.
case YUV_Cstate is
when "000" =>
YUV_Nstate <="001";
YUVclk<= '0';
Yclk<='0';
Uclk<='0';
Y1clk<='0';
Vclk<='0';
when "001" =>
YUV_Nstate <="010";
YUVclk<='1' ; --and Hsync;
Yclk<='0';
Uclk<='1';
Y1clk<='0';
Vclk<='0';
when "010" =>
YUV_Nstate <="011";
YUVclk<='0';
Yclk<='1';
Uclk<='0';
Y1clk<='0';
Vclk<='0';
when "011" =>
YUV_Nstate <="100";
YUVclk<='0';
Yclk<='0';
Uclk<='0';
Y1clk<='0';
Vclk<='1';
when "100" =>
YUV_Nstate <="001";
YUVclk<='0';
Yclk<='0';
Uclk<='0';
Y1clk<='1';
Vclk<='0';
when others =>
Yclk<='0';
Uclk<='0';
Y1clk<='0';
Vclk<='0';
YUV_Nstate <="001";
YUVclk<='0';
end case;
end process YUVmachine;
---------------------------------------------------------------------------
END SyncProcessor_v1; | gpl-2.0 | 762f55d29d7e8adae7942dce3560e8f7 | 0.597671 | 3.47265 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op338_10sk1_0.vhdl | 1 | 7,988 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.3e-06,
W => Wdiff_0,
Wdiff_0init => 5.5e-07,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.3e-06,
W => Wdiff_0,
Wdiff_0init => 5.5e-07,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => W_0,
W_0init => 4.7e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.3e-06,
W => Wdiff_0,
Wdiff_0init => 5.5e-07,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.3e-06,
W => Wdiff_0,
Wdiff_0init => 5.5e-07,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.35e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2.75e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.35e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2.75e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.35e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2.75e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.35e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2.75e-06,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 5.35e-06,
W => Wsrc_2,
Wsrc_2init => 7.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 5.35e-06,
W => Wsrc_2,
Wsrc_2init => 7.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 1.69e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias2,
S => net7
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.8e-06,
W => Wcm_1,
Wcm_1init => 1.015e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.8e-06,
W => Wcmout_1,
Wcmout_1init => 2.005e-05,
scope => private
)
port map(
D => net8,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 1.69e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => (pfak)*(WBias),
WBiasinit => 1.895e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 4.4e-06,
W => (pfak)*(WBias),
WBiasinit => 1.895e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 4.4e-06,
W => WBias,
WBiasinit => 1.895e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => WBias,
WBiasinit => 1.895e-05
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => WBias,
WBiasinit => 1.895e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.4e-06,
W => WBias,
WBiasinit => 1.895e-05
)
port map(
D => net9,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net10,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net10,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net10,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | e1f4b8a85a72214defb4c0191a31e893 | 0.581247 | 2.852857 | false | false | false | false |
KB777/1541UltimateII | fpga/io/command_interface/vhdl_source/command_interface.vhd | 1 | 3,368 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
entity command_interface is
port (
clock : in std_logic;
reset : in std_logic;
-- C64 side interface
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
freeze : out std_logic;
-- io interface for local cpu
io_req : in t_io_req; -- we get an 8K range
io_resp : out t_io_resp;
io_irq : out std_logic );
end entity;
architecture gideon of command_interface is
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp;
signal io_req_ram : t_io_req;
signal io_resp_ram : t_io_resp;
signal io_ram_en : std_logic;
signal io_ram_rdata : std_logic_vector(7 downto 0);
signal io_ram_ack : std_logic;
signal b_address : unsigned(10 downto 0);
signal b_rdata : std_logic_vector(7 downto 0);
signal b_wdata : std_logic_vector(7 downto 0);
signal b_en : std_logic;
signal b_we : std_logic;
begin
-- first we split our I/O bus in max 4 ranges, of 2K each.
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 11,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs,
reqs(1) => io_req_ram,
resps(0) => io_resp_regs,
resps(1) => io_resp_ram );
process(clock)
begin
if rising_edge(clock) then
io_ram_ack <= io_ram_en;
end if;
end process;
io_ram_en <= io_req_ram.read or io_req_ram.write;
io_resp_ram.data <= X"00" when io_ram_ack='0' else io_ram_rdata;
io_resp_ram.ack <= io_ram_ack;
i_ram: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => 11,
g_read_first_a => false,
g_read_first_b => false,
g_storage => "block" )
port map (
a_clock => clock,
a_address => io_req_ram.address(10 downto 0),
a_rdata => io_ram_rdata,
a_wdata => io_req_ram.data,
a_en => io_ram_en,
a_we => io_req_ram.write,
b_clock => clock,
b_address => b_address,
b_rdata => b_rdata,
b_wdata => b_wdata,
b_en => b_en,
b_we => b_we );
i_protocol: entity work.command_protocol
port map (
clock => clock,
reset => reset,
-- Local CPU side
io_req => io_req_regs,
io_resp => io_resp_regs,
io_irq => io_irq,
-- slot
slot_req => slot_req,
slot_resp => slot_resp,
freeze => freeze,
-- memory
address => b_address,
rdata => b_rdata,
wdata => b_wdata,
en => b_en,
we => b_we );
end architecture;
| gpl-3.0 | bb44713caff816dd4aa6803c91efa742 | 0.452494 | 3.472165 | false | false | false | false |
KB777/1541UltimateII | fpga/io/cs8900a/vhdl_source/cs8900a_bus.vhd | 1 | 7,546 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : CS8900A bus interface module
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the bus-behavior of the CS8900A chip.
-- It is based on a dual ported memory, which can be read/written
-- from the cartridge port, as well as from the other CPU as I/O
-- device. This allows the software to emulate the functionality
-- of the link, while this hardware block only implements how the
-- chip behaves as seen from the cartrige port.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity cs8900a_bus is
port (
clock : in std_logic;
reset : in std_logic;
bus_addr : in std_logic_vector(3 downto 0);
bus_write : in std_logic;
bus_read : in std_logic;
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
pp_addr : out unsigned(11 downto 0);
pp_write : out std_logic;
pp_read : out std_logic;
pp_tx_data : out std_logic; -- put
pp_rx_data : out std_logic; -- get
pp_wdata : out std_logic_vector(15 downto 0);
pp_rdata : in std_logic_vector(15 downto 0);
pp_new_rx_pkt : in std_logic );
end cs8900a_bus;
architecture gideon of cs8900a_bus is
-- The 8900A chip is accessed in WORDs, using alternately
-- even and odd bytes. Only PacketPage access in I/O mode
-- is supported.
constant c_rx_tx_data_0 : std_logic_vector(3 downto 1) := "000"; -- R/W
constant c_rx_tx_data_1 : std_logic_vector(3 downto 1) := "001"; -- R/W
constant c_tx_command : std_logic_vector(3 downto 1) := "010"; -- W
constant c_tx_length : std_logic_vector(3 downto 1) := "011"; -- W
constant c_isq : std_logic_vector(3 downto 1) := "100"; -- R
constant c_packet_page_pointer : std_logic_vector(3 downto 1) := "101"; -- R/W
constant c_packet_page_data_0 : std_logic_vector(3 downto 1) := "110"; -- R/W
constant c_packet_page_data_1 : std_logic_vector(3 downto 1) := "111"; -- R/W
constant c_lo_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0000"; -- R/W
constant c_hi_rx_tx_data_0 : std_logic_vector(3 downto 0) := "0001"; -- R/W
constant c_lo_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0010"; -- R/W
constant c_hi_rx_tx_data_1 : std_logic_vector(3 downto 0) := "0011"; -- R/W
constant c_lo_packet_page_pointer : std_logic_vector(3 downto 0) := "1010"; -- R/W
constant c_hi_packet_page_pointer : std_logic_vector(3 downto 0) := "1011"; -- R/W
constant c_lo_packet_page_data_0 : std_logic_vector(3 downto 0) := "1100"; -- R/W
constant c_hi_packet_page_data_0 : std_logic_vector(3 downto 0) := "1101"; -- R/W
constant c_lo_packet_page_data_1 : std_logic_vector(3 downto 0) := "1110"; -- R/W
constant c_hi_packet_page_data_1 : std_logic_vector(3 downto 0) := "1111"; -- R/W
signal packet_page_pointer : unsigned(11 downto 1);
signal packet_page_auto_inc : std_logic;
signal word_buffer : std_logic_vector(15 downto 0);
signal rx_count : integer range 0 to 2;
begin
pp_wdata <= word_buffer;
process(clock)
variable v_3bit_addr : std_logic_vector(3 downto 1);
begin
if rising_edge(clock) then
-- handle writes
pp_write <= '0';
pp_read <= '0';
pp_rx_data <= '0';
pp_tx_data <= '0';
pp_addr <= packet_page_pointer & '0';
v_3bit_addr := bus_addr(3 downto 1);
-- determine pp_addr for reads (default, will be overwritten by writes)
if bus_addr(3 downto 2)="00" then
case rx_count is
when 0 =>
pp_addr <= X"400";
when 1 =>
pp_addr <= X"402";
when others =>
pp_addr <= X"404";
end case;
if bus_read='1' and bus_addr(0)='1' then -- read from odd address
if rx_count /= 2 then
rx_count <= rx_count + 1;
pp_read <= '1';
else
pp_rx_data <= '1'; -- pop
end if;
end if;
end if;
if bus_write='1' then
if bus_addr(0)='0' then
word_buffer(7 downto 0) <= bus_wdata;
else
word_buffer(15 downto 8) <= bus_wdata;
case v_3bit_addr is
when c_rx_tx_data_0 | c_rx_tx_data_1 =>
pp_tx_data <= '1';
pp_write <= '1';
pp_addr <= X"A00";
when c_tx_command =>
pp_addr <= X"144";
pp_write <= '1';
when c_tx_length =>
pp_addr <= X"146";
pp_write <= '1';
when c_packet_page_pointer =>
packet_page_pointer <= unsigned(word_buffer(packet_page_pointer'range));
packet_page_auto_inc <= word_buffer(15);
when c_packet_page_data_0 | c_packet_page_data_1 =>
pp_write <= '1';
if packet_page_auto_inc='1' then
packet_page_pointer <= packet_page_pointer + 1;
end if;
when others =>
null;
end case;
end if;
end if;
if pp_new_tx_pkt='1' then
rx_count <= 0;
end if;
if reset='1' then
packet_page_pointer <= (others => '0');
packet_page_auto_inc <= '0';
end if;
end if;
end process;
-- determine output byte (combinatorial, since it's easy!)
with bus_addr select bus_rdata <=
pp_rdata(7 downto 0) when c_lo_rx_tx_data_0 | c_lo_rx_tx_data_1 | c_lo_packet_page_data_0 | c_lo_packet_page_data_1,
pp_rdata(15 downto 8) when c_hi_rx_tx_data_0 | c_hi_rx_tx_data_1 | c_hi_packet_page_data_0 | c_hi_packet_page_data_1,
std_logic_vector(packet_page_pointer(7 downto 1)) & '0' when c_lo_packet_page_pointer,
packet_page_auto_inc & "000" & std_logic_vector(packet_page_pointer(11 downto 8)) when c_hi_packet_page_pointer,
X"00" when others;
end;
| gpl-3.0 | f7dee3703c1bdb87111470a12bf7cd24 | 0.456798 | 3.83825 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ipcore_dir/ROM_GAUSS_COE/example_design/ROM_GAUSS_COE_prod_exdes.vhd | 1 | 5,570 |
--------------------------------------------------------------------------------
--
-- Distributed Memory Generator v6.3 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
--
-- Description:
-- This is the actual DMG core wrapper.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ROM_GAUSS_COE_exdes is
PORT (
A : IN STD_LOGIC_VECTOR(4-1-(4*0*boolean'pos(4>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0');
DPRA : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS => '0');
SPRA : IN STD_LOGIC_VECTOR(4-1 downto 0) := (OTHERS => '0');
CLK : IN STD_LOGIC := '0';
WE : IN STD_LOGIC := '0';
I_CE : IN STD_LOGIC := '1';
QSPO_CE : IN STD_LOGIC := '1';
QDPO_CE : IN STD_LOGIC := '1';
QDPO_CLK : IN STD_LOGIC := '0';
QSPO_RST : IN STD_LOGIC := '0';
QDPO_RST : IN STD_LOGIC := '0';
QSPO_SRST : IN STD_LOGIC := '0';
QDPO_SRST : IN STD_LOGIC := '0';
SPO : OUT STD_LOGIC_VECTOR(135-1 downto 0);
DPO : OUT STD_LOGIC_VECTOR(135-1 downto 0);
QSPO : OUT STD_LOGIC_VECTOR(135-1 downto 0);
QDPO : OUT STD_LOGIC_VECTOR(135-1 downto 0)
);
end ROM_GAUSS_COE_exdes;
architecture xilinx of ROM_GAUSS_COE_exdes is
SIGNAL CLK_i : std_logic;
component ROM_GAUSS_COE is
PORT (
CLK : IN STD_LOGIC;
WE : IN STD_LOGIC;
SPO : OUT STD_LOGIC_VECTOR(135-1 downto 0);
A : IN STD_LOGIC_VECTOR(4-1-(4*0*boolean'pos(4>4)) downto 0)
:= (OTHERS => '0');
D : IN STD_LOGIC_VECTOR(135-1 downto 0) := (OTHERS => '0')
);
end component;
begin
dmg0 : ROM_GAUSS_COE
port map (
CLK => CLK_i,
WE => WE,
SPO => SPO,
A => A,
D => D
);
clk_buf: bufg
PORT map(
i => CLK,
o => CLK_i
);
end xilinx;
| gpl-3.0 | b4f76e7a20a9fab42a5ac0b3fa15ae50 | 0.493178 | 4.645538 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/clocks/simulation/clocks_tb.vhd | 1 | 6,159 | -- file: clocks_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clocks_tb is
end clocks_tb;
architecture test of clocks_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.250 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(4 downto 1);
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(4 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clocks_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(4 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(4 downto 1)
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clocks_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
| mit | b61976ce7a475cd31be916f0323d05b7 | 0.639065 | 4.297976 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v2.vhd | 5 | 15,718 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : External Memory controller for SRAM / FLASH / SDRAM (no burst)
-------------------------------------------------------------------------------
-- File : ext_mem_ctrl.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity ext_mem_ctrl_v2 is
generic (
tag_width : integer := 2;
SRAM_Byte_Lanes : integer := 1;
SRAM_Data_Width : integer := 8;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
ETH_Acc_Time : integer := 9;
FLASH_ASU : integer := 0;
FLASH_Pulse : integer := 3;
FLASH_Hold : integer := 1; -- bus turn around
A_Width : integer := 23;
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in std_logic;
req_tag : in std_logic_vector(1 to tag_width) := (others => '0');
readwriten : in std_logic;
address : in std_logic_vector(25 downto 0); -- 64M Space
rack : out std_logic;
dack : out std_logic;
rack_tag : out std_logic_vector(1 to tag_width);
dack_tag : out std_logic_vector(1 to tag_width);
wdata : in std_logic_vector(SRAM_Data_Width-1 downto 0);
wdata_mask : in std_logic_vector(SRAM_Byte_Lanes-1 downto 0) := (others => '0');
rdata : out std_logic_vector(SRAM_Data_Width-1 downto 0);
slot_req : in std_logic := '0';
dma_addr : out std_logic_vector(15 downto 0);
dma_rdata : in std_logic_vector(7 downto 0);
dma_wdata : out std_logic_vector(7 downto 0);
dma_req : out std_logic;
dma_rwn : out std_logic;
dma_ack : in std_logic := '0';
enable_refr : in std_logic := '0';
enable_sdram: in std_logic := '0';
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
ETH_CSn : out std_logic := '1';
SRAM_CSn : out std_logic;
FLASH_CSn : out std_logic;
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_OEn : out std_logic;
MEM_WEn : out std_logic;
MEM_D : inout std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => 'Z');
MEM_BEn : out std_logic_vector(SRAM_Byte_Lanes-1 downto 0) );
end ext_mem_ctrl_v2;
-- ADDR: 25 24 23 ...
-- 0 0 0 ... SRAM
-- 0 0 1 ... C64 DMA
-- 0 1 0 ... Flash
-- 0 1 1 ... SDRAM command
-- 1 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v2 is
type t_state is (idle, setup, pulse, hold, dma_access, sd_cas, sd_wait, eth_pulse);
signal state : t_state;
signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sram_d_t : std_logic := '0';
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal tag : std_logic_vector(1 to tag_width);
signal memsel : std_logic_vector(1 downto 0);
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal reg_out : integer range 0 to 3 := 0;
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
signal dout_sel : std_logic := '0';
signal dma_rdata_c : std_logic_vector(7 downto 0) := (others => '0');
signal refr_delay : integer range 0 to 3;
signal suspend_dma : std_logic;
signal dma_tag : std_logic_vector(tag'range);
-- signal counter : std_logic_vector(7 downto 0) := X"00";
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
-- assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
assert FLASH_Pulse > 0 report "Flash cmd pulse time should be greater than 0." severity failure;
assert FLASH_Hold > 0 report "Flash hold time should be greater than 0." severity failure;
is_idle <= '1' when state = idle else '0';
rdata <= rdata_i when dout_sel='0' else dma_rdata_c;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
rack <= '1';
rack_tag <= req_tag;
tag <= req_tag;
rwn_i <= readwriten;
mem_a_i <= address(MEM_A'range);
memsel <= address(25 downto 24);
sram_d_t <= not readwriten;
sram_d_o <= wdata;
dma_wdata <= wdata;
SRAM_CSn <= address(25) or address(24) or address(23); -- should be all '0' for CSn to become active
FLASH_CSn <= address(25) or not address(24) or address(23) or address(22); -- '0' when A25..23 = 010
ETH_CSn <= address(25) or not address(24) or address(23) or not address(22); -- '1' when A25..22 = 0101
if address(25)='1' then
mem_a_i(12 downto 0) <= address(24 downto 12); -- 13 row bits
mem_a_i(17 downto 16) <= address(11 downto 10); -- 2 bank bits
col_addr <= address( 9 downto 0); -- 10 column bits
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
sram_d_t <= '0'; -- no data yet
delay <= 1;
state <= sd_cas;
elsif address(24 downto 22)="100" then -- Flash
if FLASH_ASU=0 then
state <= pulse;
delay <= FLASH_Pulse;
else
delay <= FLASH_ASU;
state <= setup;
end if;
if readwriten='0' then -- write
MEM_BEn <= not wdata_mask;
MEM_WEn <= '0';
MEM_OEn <= '1';
else -- read
MEM_BEn <= (others => '0');
MEM_OEn <= '0';
MEM_WEn <= '1';
end if;
elsif address(24 downto 22)="101" then -- Ethernet
delay <= ETH_Acc_Time;
state <= eth_pulse;
elsif address(24 downto 23)="11" then -- sdram command
SDRAM_CSn <= '0';
SDRAM_RASn <= address(13);
SDRAM_CASn <= address(14);
SDRAM_WEn <= address(15);
dack <= '1';
dack_tag <= req_tag;
state <= idle;
elsif address(24 downto 23)="01" then -- DMA
MEM_BEn <= (others => '1');
MEM_OEn <= '1';
MEM_WEn <= '1';
dma_req <= '1';
state <= dma_access;
else -- SRAM
if readwriten='0' then -- write
MEM_BEn <= not wdata_mask;
if SRAM_WR_ASU=0 then
state <= pulse;
MEM_WEn <= '0';
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
MEM_BEn <= (others => '0');
MEM_OEn <= '0';
if SRAM_RD_ASU=0 then
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
end if;
end procedure;
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
dout_sel <= '0';
dma_rdata_c <= dma_rdata;
inhibit_d <= inhibit;
rdata_i <= MEM_D; -- clock in
SDRAM_CSn <= '1';
SDRAM_CKE <= enable_sdram;
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
case state is
when idle =>
if suspend_dma='1' then
tag <= dma_tag;
state <= dma_access;
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
elsif do_refresh='1' and not (inhibit_d='1' and inhibit='0') then
send_refresh_cmd;
elsif inhibit='0' then
dma_req <= '0';
if req='1' and (refr_delay=0 or address(25)='0') then
accept_req;
end if;
end if;
when sd_cas =>
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
sram_d_t <= '1';
if delay = 0 then
-- read or write with auto precharge
SDRAM_CSn <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= rwn_i;
if rwn_i='0' then -- write
delay <= 2;
else
delay <= 1;
end if;
state <= sd_wait;
else
delay <= delay - 1;
end if;
when sd_wait =>
sram_d_t <= '0';
if delay=0 then
dack <= '1';
dack_tag <= tag;
state <= idle;
else
delay <= delay - 1;
end if;
when setup =>
if delay = 1 then
state <= pulse;
if memsel(0)='0' then -- SRAM
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
MEM_WEn <= '0';
else
delay <= SRAM_RD_Pulse;
MEM_OEn <= '0';
end if;
else
delay <= FLASH_Pulse;
if rwn_i='0' then
MEM_WEn <= '0';
else
MEM_OEn <= '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
MEM_OEn <= '1';
MEM_WEn <= '1';
dack <= '1';
dack_tag <= tag;
if memsel(0)='0' then -- SRAM
if rwn_i='0' and SRAM_WR_Hold > 0 then
delay <= SRAM_WR_Hold;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 0 then
state <= hold;
delay <= SRAM_RD_Hold;
else
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
end if;
else -- Flash
if rwn_i='0' and FLASH_Hold > 0 then -- for writes, add hold cycles
delay <= FLASH_Hold;
state <= hold;
else
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
end if;
end if;
else
delay <= delay - 1;
end if;
when eth_pulse =>
delay <= delay - 1;
case delay is
when 2 =>
dack <= '1';
dack_tag <= tag;
-- rdata_i <= counter;
-- counter <= counter + 1;
MEM_WEn <= '1';
MEM_OEn <= '1';
when 1 =>
sram_d_t <= '0';
ETH_CSn <= '1';
state <= idle;
when others =>
MEM_WEn <= rwn_i;
MEM_OEn <= not rwn_i;
end case;
when hold =>
if delay = 1 then
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
state <= idle;
else
delay <= delay - 1;
end if;
when dma_access =>
suspend_dma <= '0';
dma_tag <= tag;
if dma_ack='1' then
dma_req <= '0';
sram_d_t <= '0';
dack <= '1';
dack_tag <= tag;
dout_sel <= '1';
state <= idle;
elsif slot_req='1' then
suspend_dma <= '1';
accept_req; -- exits this state, does an access and returns to idle.
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= enable_refr;
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= idle;
dma_req <= '0';
ETH_CSn <= '1';
SRAM_CSn <= '1';
FLASH_CSn <= '1';
MEM_BEn <= (others => '1');
-- sram_d_o <= (others => '1');
sram_d_t <= '0';
MEM_OEn <= '1';
MEM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
do_refresh <= '0';
suspend_dma <= '0';
end if;
end if;
end process;
dma_rwn <= rwn_i;
MEM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
MEM_A <= mem_a_i;
dma_addr <= mem_a_i(15 downto 0);
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
end Gideon;
| gpl-3.0 | 04a215d461bef5f1180969f17d8f94a5 | 0.434597 | 3.669858 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb2/vhdl_source/usb_contoller.vhd | 3 | 12,041 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_controller is
generic (
g_tag : std_logic_vector(7 downto 0) := X"55" );
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- ULPI Interface
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- LED interface
usb_busy : out std_logic;
-- register interface bus
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_mem_req : out t_mem_req;
sys_mem_resp: in t_mem_resp;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp );
end usb_controller;
architecture wrap of usb_controller is
signal nano_addr : unsigned(7 downto 0);
signal nano_write : std_logic;
signal nano_read : std_logic;
signal nano_wdata : std_logic_vector(15 downto 0);
signal nano_rdata : std_logic_vector(15 downto 0);
signal stall : std_logic := '0';
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal rx_valid_token : std_logic := '0';
signal rx_valid_handsh : std_logic := '0';
signal rx_valid_packet : std_logic := '0';
signal rx_error : std_logic := '0';
signal rx_user_valid : std_logic := '0';
signal rx_user_start : std_logic := '0';
signal rx_user_data : std_logic_vector(7 downto 0) := X"12";
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal tx_send_token : std_logic;
signal tx_send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal tx_send_data : std_logic;
signal tx_no_data : std_logic;
signal tx_user_data : std_logic_vector(7 downto 0);
signal tx_user_last : std_logic;
signal tx_user_next : std_logic;
signal tx_length : unsigned(10 downto 0);
signal transferred : unsigned(10 downto 0);
-- cmd interface
signal cmd_addr : std_logic_vector(3 downto 0);
signal cmd_valid : std_logic;
signal cmd_write : std_logic;
signal cmd_wdata : std_logic_vector(15 downto 0);
signal cmd_ack : std_logic;
signal cmd_ready : std_logic;
signal sys_buf_addr : std_logic_vector(10 downto 0);
signal sys_buf_en : std_logic;
signal sys_buf_we : std_logic;
signal sys_buf_wdata : std_logic_vector(7 downto 0);
signal sys_buf_rdata : std_logic_vector(7 downto 0);
signal ulpi_buf_addr : std_logic_vector(10 downto 0);
signal ulpi_buf_en : std_logic;
signal ulpi_buf_we : std_logic;
signal ulpi_buf_wdata : std_logic_vector(7 downto 0);
signal ulpi_buf_rdata : std_logic_vector(7 downto 0);
-- low level
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal tx_chirp_start : std_logic;
signal tx_chirp_level : std_logic;
signal tx_chirp_end : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
signal reg_read : std_logic := '0';
signal reg_write : std_logic := '0';
signal reg_ack : std_logic;
signal reg_addr : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
signal speed : std_logic_vector(1 downto 0) := "10"; -- TODO!
begin
i_nano: entity work.nano
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- i/o interface
io_addr => nano_addr,
io_write => nano_write,
io_read => nano_read,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => stall,
-- system interface (to write code into the nano)
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => sys_io_req,
sys_io_resp => sys_io_resp );
i_regs: entity work.usb_io_bank
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- i/o interface
io_addr => nano_addr,
io_read => nano_read,
io_write => nano_write,
io_wdata => nano_wdata,
io_rdata => nano_rdata,
stall => stall,
-- memory controller
mem_ready => cmd_ready,
transferred => transferred,
-- Register access
reg_addr => reg_addr,
reg_read => reg_read,
reg_write => reg_write,
reg_ack => reg_ack,
reg_wdata => reg_wdata,
reg_rdata => rx_data,
status => status,
-- I/O pins from RX
rx_pid => rx_pid,
rx_token => rx_token,
rx_valid_token => rx_valid_token,
rx_valid_handsh => rx_valid_handsh,
rx_valid_packet => rx_valid_packet,
rx_error => rx_error,
-- I/O pins to TX
tx_pid => tx_pid,
tx_token => tx_token,
tx_send_token => tx_send_token,
tx_send_handsh => tx_send_handsh,
tx_send_data => tx_send_data,
tx_length => tx_length,
tx_no_data => tx_no_data,
tx_ack => tx_ack,
tx_chirp_start => tx_chirp_start,
tx_chirp_end => tx_chirp_end,
tx_chirp_level => tx_chirp_level );
i_bridge_to_mem_ctrl: entity work.bridge_to_mem_ctrl
port map (
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset,
nano_addr => nano_addr,
nano_write => nano_write,
nano_wdata => nano_wdata,
sys_clock => sys_clock,
sys_reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack );
i_memctrl: entity work.usb_memory_ctrl
generic map (
g_tag => g_tag )
port map (
clock => sys_clock,
reset => sys_reset,
-- cmd interface
cmd_addr => cmd_addr,
cmd_valid => cmd_valid,
cmd_write => cmd_write,
cmd_wdata => cmd_wdata,
cmd_ack => cmd_ack,
cmd_ready => cmd_ready,
-- BRAM interface
ram_addr => sys_buf_addr,
ram_en => sys_buf_en,
ram_we => sys_buf_we,
ram_wdata => sys_buf_wdata,
ram_rdata => sys_buf_rdata,
-- memory interface
mem_req => sys_mem_req,
mem_resp => sys_mem_resp );
i_buf_ram: RAMB16_S9_S9
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_buf_we,
ADDRA => sys_buf_addr,
DIA => sys_buf_wdata,
DIPA => "0",
DOA => sys_buf_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => ulpi_buf_en,
WEB => ulpi_buf_we,
ADDRB => ulpi_buf_addr,
DIB => ulpi_buf_wdata,
DIPB => "0",
DOB => ulpi_buf_rdata );
i_buf_ctrl: entity work.rxtx_to_buf
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- transferred length
transferred => transferred,
-- bram interface
ram_addr => ulpi_buf_addr,
ram_wdata => ulpi_buf_wdata,
ram_rdata => ulpi_buf_rdata,
ram_we => ulpi_buf_we,
ram_en => ulpi_buf_en,
-- Interface from RX
user_rx_valid => rx_user_valid,
user_rx_start => rx_user_start,
user_rx_data => rx_user_data,
user_rx_last => rx_last,
-- Interface to TX
send_data => tx_send_data,
last_addr => tx_length,
no_data => tx_no_data,
user_tx_data => tx_user_data,
user_tx_last => tx_user_last,
user_tx_next => tx_user_next );
i_tx: entity work.ulpi_tx
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
-- Status
speed => speed,
status => status,
busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens
send_token => tx_send_token,
send_handsh => tx_send_handsh,
pid => tx_pid,
token => tx_token,
-- Interface to send data packets
send_data => tx_send_data,
no_data => tx_no_data,
user_data => tx_user_data,
user_last => tx_user_last,
user_next => tx_user_next,
-- Interface to read/write registers and reset packets
send_reset_data => tx_chirp_start,
reset_data => tx_chirp_level,
reset_last => tx_chirp_end );
i_rx: entity work.ulpi_rx
generic map (
g_allow_token => false )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => rx_pid,
token => rx_token,
valid_token => rx_valid_token,
valid_handsh => rx_valid_handsh,
valid_packet => rx_valid_packet,
data_out => rx_user_data,
data_valid => rx_user_valid,
data_start => rx_user_start,
error => rx_error );
i_bus: entity work.ulpi_bus
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_addr,
reg_wdata => reg_wdata,
reg_ack => reg_ack,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
end wrap;
| gpl-3.0 | af27c6934561f8a4ea45ac56ba95662a | 0.471472 | 3.583631 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op330_3sk1_0.vhdl | 1 | 6,091 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 7.9e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 7.9e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 5e-07,
W => W_0,
W_0init => 1.265e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.55e-06,
W => Wcm_2,
Wcm_2init => 9e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.55e-06,
W => Wcmcout_2,
Wcmcout_2init => 4.965e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.55e-06,
W => Wcm_2,
Wcm_2init => 9e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.55e-06,
W => Wcmcout_2,
Wcmcout_2init => 4.965e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.5e-06,
W => Wcm_1,
Wcm_1init => 7.14e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.5e-06,
W => Wcmout_1,
Wcmout_1init => 2.51e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 5e-07,
W => (pfak)*(WBias),
WBiasinit => 2.1e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 5e-07,
W => (pfak)*(WBias),
WBiasinit => 2.1e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 5e-07,
W => WBias,
WBiasinit => 2.1e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5e-07,
W => WBias,
WBiasinit => 2.1e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5e-07,
W => WBias,
WBiasinit => 2.1e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5e-07,
W => WBias,
WBiasinit => 2.1e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 3945a1ab57a011995cc779c7efa8131e | 0.583812 | 2.958232 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ROM_PAIRS.vhd | 1 | 10,417 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:14:30 05/16/2014
-- Design Name:
-- Module Name: ROM_PAIRS - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.RetinaParameters.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ROM_PAIRS is
port(
clk : in std_logic;
addr : in std_logic_vector(4 downto 0);
points1 : out T_POINT_INDEX;
points2 : out T_POINT_INDEX
);
end ROM_PAIRS;
architecture Behavioral of ROM_PAIRS is
constant sROM_PAIRS : T_ROM_PAIRS :=
(
0 => (28,26), 1 => (29,25), 2 => (40,38), 3 => (32,15), 4 => (19,10), 5 => (10,7), 6 => (25,11), 7 => (42,13), 8 => (39,33), 9 => (33,15), 10 => (38,16), 11 => (21,20), 12 => (29,11), 13 => (20,15), 14 => (5,1), 15 => (33,32), 16 => (17,13), 17 => (23,12), 18 => (9,3), 19 => (25,6), 20 => (18,12), 21 => (41,37), 22 => (22,19), 23 => (4,2), 24 => (11,6), 25 => (6,0), 26 => (11,0), 27 => (38,14), 28 => (9,8), 29 => (29,6), 30 => (34,31), 31 => (16,14), 32 => (39,20), 33 => (37,29), 34 => (36,30), 35 => (40,2), 36 => (35,30), 37 => (31,22), 38 => (33,21), 39 => (32,20), 40 => (23,18), 41 => (36,35), 42 => (39,21), 43 => (28,14), 44 => (19,7), 45 => (40,16), 46 => (39,32), 47 => (8,3), 48 => (37,6), 49 => (41,25), 50 => (33,20), 51 => (40,14), 52 => (37,11), 53 => (36,24), 54 => (22,10), 55 => (41,11), 56 => (21,15), 57 => (22,7), 58 => (41,29), 59 => (13,5), 60 => (37,25), 61 => (31,19), 62 => (41,6), 63 => (38,4), 64 => (16,2), 65 => (32,21), 66 => (34,22), 67 => (38,28), 68 => (26,3), 69 => (26,14), 70 => (34,10), 71 => (31,10), 72 => (28,16), 73 => (31,7), 74 => (34,19), 75 => (28,3), 76 => (17,1), 77 => (14,2), 78 => (28,2), 79 => (26,2), 80 => (35,24), 81 => (38,26), 82 => (40,28), 83 => (21,8), 84 => (21,3), 85 => (30,24), 86 => (17,5), 87 => (40,26), 88 => (26,16), 89 => (14,4), 90 => (28,4), 91 => (34,7), 92 => (16,4), 93 => (39,9), 94 => (20,3), 95 => (39,8), 96 => (38,3), 97 => (41,23), 98 => (13,1), 99 => (20,9), 100 => (25,17), 101 => (26,4), 102 => (39,27), 103 => (20,8), 104 => (14,9), 105 => (31,1), 106 => (35,18), 107 => (13,0), 108 => (34,1), 109 => (40,3), 110 => (37,23), 111 => (17,0), 112 => (41,18), 113 => (14,3), 114 => (17,6), 115 => (18,11), 116 => (37,13), 117 => (21,9), 118 => (29,13), 119 => (27,15), 120 => (29,12), 121 => (29,17), 122 => (12,11), 123 => (13,11), 124 => (32,27), 125 => (23,6), 126 => (37,17), 127 => (25,12), 128 => (33,27), 129 => (6,5), 130 => (31,5), 131 => (37,18), 132 => (16,3), 133 => (30,23), 134 => (30,18), 135 => (41,13), 136 => (12,6), 137 => (15,8), 138 => (23,0), 139 => (15,3), 140 => (25,13), 141 => (7,4), 142 => (18,0), 143 => (36,18), 144 => (29,5), 145 => (35,12), 146 => (35,23), 147 => (16,8), 148 => (25,5), 149 => (22,1), 150 => (25,1), 151 => (13,6), 152 => (11,1), 153 => (23,11), 154 => (27,20), 155 => (10,1), 156 => (29,1), 157 => (27,9), 158 => (9,2), 159 => (14,8), 160 => (19,5), 161 => (38,7), 162 => (15,9), 163 => (34,17), 164 => (12,0), 165 => (27,21), 166 => (36,23), 167 => (16,9), 168 => (27,8), 169 => (29,18), 170 => (18,6), 171 => (41,1), 172 => (5,0), 173 => (25,23), 174 => (28,15), 175 => (3,2), 176 => (26,15), 177 => (42,30), 178 => (4,3), 179 => (40,10), 180 => (10,2), 181 => (1,0), 182 => (19,4), 183 => (26,21), 184 => (22,5), 185 => (7,5), 186 => (19,1), 187 => (17,11), 188 => (34,13), 189 => (34,0), 190 => (8,4), 191 => (24,18), 192 => (29,23), 193 => (38,21), 194 => (39,14), 195 => (28,20), 196 => (40,7), 197 => (24,12), 198 => (24,23), 199 => (39,28), 200 => (34,4), 201 => (39,26), 202 => (38,19), 203 => (39,16), 204 => (21,14), 205 => (31,0), 206 => (38,20), 207 => (32,2), 208 => (31,2), 209 => (22,4), 210 => (16,7), 211 => (40,22), 212 => (30,11), 213 => (22,2), 214 => (33,16), 215 => (31,17), 216 => (40,20), 217 => (25,18), 218 => (6,1), 219 => (33,4), 220 => (40,21), 221 => (30,6), 222 => (33,26), 223 => (19,2), 224 => (11,5), 225 => (33,2), 226 => (38,10), 227 => (31,4), 228 => (8,2), 229 => (21,2), 230 => (36,0), 231 => (42,38), 232 => (18,17), 233 => (23,13), 234 => (40,19), 235 => (13,10), 236 => (10,4), 237 => (32,16), 238 => (28,21), 239 => (7,2), 240 => (32,4), 241 => (15,2), 242 => (32,28), 243 => (13,12), 244 => (20,4), 245 => (17,7), 246 => (16,15), 247 => (20,2), 248 => (20,16), 249 => (26,20), 250 => (17,12), 251 => (12,5), 252 => (15,14), 253 => (14,10), 254 => (34,2), 255 => (42,9), 256 => (18,5), 257 => (23,1), 258 => (21,4), 259 => (24,0), 260 => (30,29), 261 => (26,7), 262 => (38,22), 263 => (19,17), 264 => (28,7), 265 => (7,3), 266 => (31,11), 267 => (9,4), 268 => (22,0), 269 => (35,25), 270 => (19,0), 271 => (23,5), 272 => (12,1), 273 => (15,4), 274 => (41,24), 275 => (22,13), 276 => (19,16), 277 => (28,10), 278 => (37,35), 279 => (37,24), 280 => (10,5), 281 => (4,1), 282 => (41,30), 283 => (31,14), 284 => (10,3), 285 => (32,26), 286 => (7,1), 287 => (18,1), 288 => (5,2), 289 => (36,29), 290 => (38,33), 291 => (36,25), 292 => (34,16), 293 => (38,34), 294 => (41,10), 295 => (40,31), 296 => (19,3), 297 => (7,0), 298 => (22,6), 299 => (26,10), 300 => (27,2), 301 => (22,3), 302 => (10,8), 303 => (23,17), 304 => (11,7), 305 => (19,11), 306 => (10,0), 307 => (19,6), 308 => (22,14), 309 => (40,32), 310 => (37,7), 311 => (27,4), 312 => (33,28), 313 => (35,17), 314 => (18,13), 315 => (20,14), 316 => (10,9), 317 => (22,17), 318 => (27,14), 319 => (21,16), 320 => (22,11), 321 => (30,17), 322 => (37,34), 323 => (37,19), 324 => (34,12), 325 => (5,4), 326 => (41,22), 327 => (31,16), 328 => (31,3), 329 => (40,1), 330 => (34,3), 331 => (29,10), 332 => (19,8), 333 => (28,27), 334 => (8,7), 335 => (40,39), 336 => (35,13), 337 => (35,29), 338 => (27,16), 339 => (14,7), 340 => (36,13), 341 => (30,13), 342 => (2,1), 343 => (30,25), 344 => (37,10), 345 => (30,5), 346 => (22,9), 347 => (16,10), 348 => (17,10), 349 => (19,13), 350 => (19,14), 351 => (29,24), 352 => (11,10), 353 => (40,27), 354 => (27,26), 355 => (13,4), 356 => (16,1), 357 => (38,5), 358 => (22,8), 359 => (25,10), 360 => (17,2), 361 => (35,1), 362 => (38,27), 363 => (34,14), 364 => (31,12), 365 => (41,31), 366 => (40,17), 367 => (22,16), 368 => (7,6), 369 => (13,7), 370 => (34,25), 371 => (25,7), 372 => (39,38), 373 => (26,1), 374 => (31,29), 375 => (41,36), 376 => (25,24), 377 => (41,7), 378 => (14,5), 379 => (39,7), 380 => (5,3), 381 => (28,19), 382 => (16,5), 383 => (37,22), 384 => (37,36), 385 => (14,1), 386 => (24,17), 387 => (38,13), 388 => (24,1), 389 => (17,4), 390 => (15,7), 391 => (3,1), 392 => (13,2), 393 => (41,35), 394 => (41,19), 395 => (2,0), 396 => (29,7), 397 => (26,22), 398 => (34,23), 399 => (31,28), 400 => (24,13), 401 => (37,30), 402 => (6,4), 403 => (39,10), 404 => (28,1), 405 => (12,10), 406 => (12,7), 407 => (15,10), 408 => (4,0), 409 => (34,29), 410 => (19,12), 411 => (38,31), 412 => (20,7), 413 => (31,18), 414 => (21,7), 415 => (26,19), 416 => (26,5), 417 => (28,22), 418 => (19,15), 419 => (22,12), 420 => (34,26), 421 => (21,10), 422 => (40,0), 423 => (20,10), 424 => (40,13), 425 => (22,15), 426 => (41,4), 427 => (9,5), 428 => (38,32), 429 => (34,18), 430 => (13,3), 431 => (38,0), 432 => (25,22), 433 => (39,19), 434 => (38,17), 435 => (17,3), 436 => (31,15), 437 => (31,25), 438 => (14,0), 439 => (40,34), 440 => (40,33), 441 => (18,10), 442 => (17,16), 443 => (31,23), 444 => (39,22), 445 => (23,10), 446 => (29,19), 447 => (29,4), 448 => (34,15), 449 => (16,0), 450 => (25,19), 451 => (37,2), 452 => (17,14), 453 => (18,7), 454 => (25,2), 455 => (31,26), 456 => (32,19), 457 => (23,7), 458 => (17,9), 459 => (29,22), 460 => (14,6), 461 => (22,20), 462 => (28,17), 463 => (23,19), 464 => (22,21), 465 => (6,3), 466 => (15,1), 467 => (27,7), 468 => (41,34), 469 => (31,20), 470 => (17,8), 471 => (33,22), 472 => (16,11), 473 => (16,13), 474 => (28,0), 475 => (12,2), 476 => (14,11), 477 => (14,13), 478 => (11,3), 479 => (27,10), 480 => (23,22), 481 => (20,19), 482 => (37,31), 483 => (34,21), 484 => (26,13), 485 => (39,1), 486 => (34,28), 487 => (26,0), 488 => (29,2), 489 => (21,19), 490 => (8,0), 491 => (25,4), 492 => (20,1), 493 => (19,18), 494 => (15,5), 495 => (16,6), 496 => (31,21), 497 => (21,1), 498 => (33,19), 499 => (33,5), 500 => (12,4), 501 => (21,5), 502 => (37,4), 503 => (22,18), 504 => (9,0), 505 => (34,20), 506 => (28,11), 507 => (35,10), 508 => (26,6), 509 => (32,22), 510 => (30,7), 511 => (41,2)
);
begin
rom: process(clk)
variable pointIndex1: integer range 0 to 42 := 0;
variable pointIndex2: integer range 0 to 42 := 0;
begin
if rising_edge(clk) then
for i in 0 to 15 loop
pointIndex1 := sROM_PAIRS(to_integer(resize(unsigned(addr)*16+i,9)))(0);
pointIndex2 := sROM_PAIRS(to_integer(resize(unsigned(addr)*16+i,9)))(1);
points1(i) <= std_logic_vector(to_unsigned(pointIndex1, points1(0)'length)) ;
points2(i) <= std_logic_vector(to_unsigned(pointIndex2, points2(0)'length)) ;
end loop;
end if;
--sROM_PAIRS(to_integer(resize(unsigned(addr)*16+i,9)))(0);
end process rom;
end Behavioral;
| gpl-3.0 | 49802262c837516ab431feb68ae198f2 | 0.474801 | 2.400784 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_source/slot_bus_pkg.vhd | 4 | 1,974 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package slot_bus_pkg is
type t_slot_req is record
bus_address : unsigned(15 downto 0); -- for async reads and direct bus writes
bus_write : std_logic;
io_address : unsigned(15 downto 0); -- for late reads/writes
io_read : std_logic;
io_read_early : std_logic;
io_write : std_logic;
late_write : std_logic;
data : std_logic_vector(7 downto 0);
end record;
type t_slot_resp is record
data : std_logic_vector(7 downto 0);
reg_output : std_logic;
irq : std_logic;
end record;
constant c_slot_req_init : t_slot_req := (
bus_address => X"0000",
bus_write => '0',
io_read_early => '0',
io_address => X"0000",
io_read => '0',
io_write => '0',
late_write => '0',
data => X"00" );
constant c_slot_resp_init : t_slot_resp := (
data => X"00",
reg_output => '0',
irq => '0' );
type t_slot_req_array is array(natural range <>) of t_slot_req;
type t_slot_resp_array is array(natural range <>) of t_slot_resp;
function or_reduce(ar: t_slot_resp_array) return t_slot_resp;
end package;
package body slot_bus_pkg is
function or_reduce(ar: t_slot_resp_array) return t_slot_resp is
variable ret : t_slot_resp;
begin
ret := c_slot_resp_init;
for i in ar'range loop
ret.reg_output := ret.reg_output or ar(i).reg_output;
if ar(i).reg_output='1' then
ret.data := ret.data or ar(i).data;
end if;
ret.irq := ret.irq or ar(i).irq;
end loop;
return ret;
end function or_reduce;
end package body;
| gpl-3.0 | 46d6fb43e79e626a05a05a488826b984 | 0.50152 | 3.543986 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_bfm/io_bus_bfm_pkg.vhd | 4 | 3,912 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.io_bus_pkg.all;
package io_bus_bfm_pkg is
type t_io_bus_bfm_object;
type p_io_bus_bfm_object is access t_io_bus_bfm_object;
type t_io_bfm_command is ( e_io_none, e_io_read, e_io_write );
type t_io_bus_bfm_object is record
next_bfm : p_io_bus_bfm_object;
name : string(1 to 256);
command : t_io_bfm_command;
address : unsigned(19 downto 0);
data : std_logic_vector(7 downto 0);
end record;
------------------------------------------------------------------------------------
shared variable io_bus_bfms : p_io_bus_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
------------------------------------------------------------------------------------
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
end io_bus_bfm_pkg;
package body io_bus_bfm_pkg is
procedure register_io_bus_bfm(named : string;
variable pntr : inout p_io_bus_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_io_bus_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
-- add this pointer to the head of the linked list
if io_bus_bfms = null then -- first entry
io_bus_bfms := pntr;
else -- insert new entry
pntr.next_bfm := io_bus_bfms;
io_bus_bfms := pntr;
end if;
end register_io_bus_bfm;
procedure bind_io_bus_bfm(named : string;
variable pntr : inout p_io_bus_bfm_object) is
variable p : p_io_bus_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := io_bus_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_io_bus_bfm;
------------------------------------------------------------------------------
procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(19 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
io.address := a_i;
io.command := e_io_read;
while io.command /= e_io_none loop
wait for 10 ns;
end loop;
data := io.data;
end procedure;
procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(19 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
io.address := a_i;
io.command := e_io_write;
io.data := data;
while io.command /= e_io_none loop
wait for 10 ns;
end loop;
end procedure;
end;
------------------------------------------------------------------------------
| gpl-3.0 | 67c80523b8e360bacf50cecf242c6709 | 0.476994 | 3.971574 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_sim/ulpi_phy_bfm.vhd | 3 | 6,972 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_phy_bfm is
generic (
g_rx_interval : integer := 100 );
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : out std_logic;
ULPI_NXT : out std_logic;
ULPI_STP : in std_logic );
end ulpi_phy_bfm;
architecture gideon of ulpi_phy_bfm is
type t_state is (idle, sending, receiving, read_reg, read_reg2, read_reg3, write_reg, status_update);
signal state : t_state;
signal pattern : std_logic_vector(0 to 19);
signal do_send : std_logic;
signal counter : unsigned(7 downto 0) := X"01";
signal status_in : std_logic_vector(7 downto 0) := X"00";
signal status_d : std_logic_vector(7 downto 0) := X"00";
signal ulpi_nxt_i : std_logic;
signal ulpi_dir_i : std_logic;
alias ulpi_cmd : std_logic_vector(1 downto 0) is ULPI_DATA(7 downto 6);
constant c_transmit : std_logic_vector(1 downto 0) := "01";
constant c_write_reg : std_logic_vector(1 downto 0) := "10";
constant c_read_reg : std_logic_vector(1 downto 0) := "11";
begin
process(clock)
variable byte_count : integer := 0;
variable rx_interval : integer := g_rx_interval;
variable address : std_logic_vector(5 downto 0);
procedure set_reg(addr: std_logic_vector(5 downto 0);
data: std_logic_vector(7 downto 0) ) is
begin
if addr = "001010" then
if data(5)='1' or data(6)='1' then-- poweron
report "Power On";
if status_in(3)='0' then
status_in(3 downto 2) <= transport "00",
"01" after 10 us,
"10" after 20 us,
"11" after 30 us;
end if;
else -- power off
report "Power Off";
status_in(3 downto 2) <= transport "11",
"10" after 1 us,
"01" after 2 us,
"00" after 3 us;
end if;
end if;
if addr = "000100" then
case data(2 downto 0) is
when "000" => -- host chirp
status_in(1 downto 0) <= transport "00", "10" after 10 us, "00" after 15 us;
when "001"|"011" => -- powerup
status_in(1 downto 0) <= "11";
when "010" => -- unknown
status_in(1 downto 0) <= "00";
when "100" => -- peripheral chirp
status_in(1 downto 0) <= "10";
when "101"|"111" => -- peripheral FS
status_in(1 downto 0) <= "01";
when "110" => -- peripheral LS
status_in(1 downto 0) <= "10";
when others =>
null;
end case;
end if;
end procedure;
begin
if rising_edge(clock) then
if rx_interval = 0 then
do_send <= '0'; -- autonomous send disabled
rx_interval := g_rx_interval;
else
rx_interval := rx_interval - 1;
end if;
ulpi_nxt_i <= '0';
case state is
when idle =>
status_d <= status_in;
ulpi_dir_i <= '0';
ULPI_DATA <= (others => 'Z');
if do_send = '1' then
do_send <= '0';
ulpi_dir_i <= '1';
ulpi_nxt_i <= '1';
pattern <= "01111101111011101101";
state <= sending;
byte_count := 20;
elsif ulpi_dir_i = '0' then
if ulpi_cmd = c_transmit then
pattern <= "11111111100111011010";
state <= receiving;
elsif ulpi_cmd = c_write_reg then
address := ULPI_DATA(5 downto 0);
byte_count := 2;
state <= write_reg;
elsif ulpi_cmd = c_read_reg then
state <= read_reg;
elsif status_in /= status_d then
ulpi_dir_i <= '1';
state <= status_update;
end if;
end if;
when status_update =>
ULPI_DATA <= status_d;
state <= idle;
when sending =>
pattern <= pattern(1 to 19) & '0';
if pattern(0)='1' then
ULPI_DATA <= std_logic_vector(counter);
ulpi_nxt_i <= '1';
counter <= counter + 1;
else
ULPI_DATA <= status_in;
ulpi_nxt_i <= '0';
end if;
byte_count := byte_count - 1;
if byte_count = 0 then
state <= idle;
end if;
when receiving =>
if ULPI_STP = '1' then
ulpi_nxt_i <= '0';
state <= idle;
else
ulpi_nxt_i <= pattern(0);
pattern <= pattern(1 to 19) & '1';
end if;
when write_reg =>
if byte_count = 0 then
ulpi_nxt_i <= '0';
set_reg(address, ULPI_DATA);
else
ulpi_nxt_i <= '1';
end if;
byte_count := byte_count - 1;
if ULPI_STP = '1' then
state <= idle;
end if;
when read_reg =>
ulpi_nxt_i <= '1';
state <= read_reg2;
when read_reg2 =>
ulpi_dir_i <= '1';
state <= read_reg3;
when read_reg3 =>
ULPI_DATA <= X"AA";
state <= idle;
when others =>
state <= idle;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
ULPI_NXT <= ulpi_nxt_i;
ULPI_DIR <= ulpi_dir_i;
end gideon;
| gpl-3.0 | 9fb4999b4611515a2c36ca17ca83412f | 0.379088 | 4.589862 | false | false | false | false |
nick1au/Home-Sec-SYS | output_files/halfSecDelay.vhd | 2 | 818 | Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Entity halfSecDelay is
Port (load, clock: in std_logic;
TC: out std_logic);
End Entity halfSecDelay;
Architecture csa of halfSecDelay is
Type StateName is (idle, hold, count);
signal Prest, NxtSt, idlenxt, holdnxt, countnxt: StateName;
signal decrement_str, decrement: unsigned(1 downto 0);
begin
idlenxt <= hold when load ='1' else idle;
holdnxt <= count when load ='0' else hold;
countnxt <= idle when decrement_str = "00" ELSE count;
NxtSt <= idlenxt when prest = idle else holdnxt when prest = hold else countnxt;
Prest <= NxtSt when rising_edge (clock);
decrement <= "11" when prest /= count else decrement_str - 1;
decrement_str <= decrement when rising_edge(clock);
TC <= '1' when prest = hold and nxtSt= count else '0';
end csa; | gpl-3.0 | 1c88c9fee96745766f9ecb3cda767064 | 0.723716 | 3.170543 | false | false | false | false |
KB777/1541UltimateII | fpga/ip/srl_fifo/vhdl_source/srl_fifo.vhd | 2 | 3,787 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Fifo Using SRL16
-------------------------------------------------------------------------------
-- File : srl_fifo.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This implementation makes use of the SRL16 properties,
-- implementing a 16-deep synchronous fifo in only one LUT per
-- bit. It is a fall-through fifo.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity srl_fifo is
generic (Width : integer := 32;
Depth : integer := 15; -- 15 is the maximum
Threshold : integer := 13);
port (
clock : in std_logic;
reset : in std_logic;
GetElement : in std_logic;
PutElement : in std_logic;
FlushFifo : in std_logic;
DataIn : in std_logic_vector(Width-1 downto 0);
DataOut : out std_logic_vector(Width-1 downto 0);
SpaceInFifo : out std_logic;
AlmostFull : out std_logic;
DataInFifo : out std_logic);
end srl_fifo;
architecture Gideon of srl_fifo is
signal NumElements : std_logic_vector(3 downto 0);
signal FilteredGet : std_logic;
signal FilteredPut : std_logic;
signal DataInFifo_i : std_logic;
signal SpaceInFifo_i : std_logic;
constant Depth_std : std_logic_vector(3 downto 0) := conv_std_logic_vector(Depth-1, 4);
begin
FilteredGet <= DataInFifo_i and GetElement;
FilteredPut <= SpaceInFifo_i and PutElement;
DataInFifo <= DataInFifo_i;
SpaceInFifo <= SpaceInFifo_i;
process(clock)
variable NewCnt : std_logic_vector(3 downto 0);--integer range 0 to Depth;
begin
if rising_edge(clock) then
if FlushFifo='1' then
NewCnt := "1111"; --0;
elsif (FilteredGet='1') and (FilteredPut='0') then
NewCnt := NumElements - 1;
elsif (FilteredGet='0') and (FilteredPut='1') then
NewCnt := NumElements + 1;
else
NewCnt := NumElements;
end if;
NumElements <= NewCnt;
if (NewCnt > Threshold) and (NewCnt /= "1111") then
AlmostFull <= '1';
else
AlmostFull <= '0';
end if;
if (NewCnt = "1111") then
DataInFifo_i <= '0';
else
DataInFifo_i <= '1';
end if;
if (NewCnt /= Depth_std) then
SpaceInFifo_i <= '1';
else
SpaceInFifo_i <= '0';
end if;
if Reset='1' then
NumElements <= "1111";
SpaceInFifo_i <= '1';
DataInFifo_i <= '0';
AlmostFull <= '0';
end if;
end if;
end process;
SRLs : for srl2 in 0 to Width-1 generate
i_SRL : SRL16E
port map (
CLK => clock,
CE => FilteredPut,
D => DataIn(srl2),
A3 => NumElements(3),
A2 => NumElements(2),
A1 => NumElements(1),
A0 => NumElements(0),
Q => DataOut(srl2) );
end generate;
end Gideon;
| gpl-3.0 | 0975e830d1b7614808fc14e709dde5c5 | 0.460259 | 4.293651 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ImagePatchReader.vhd | 1 | 6,892 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_XMTEyY
-- /___/ /\ Timestamp : 04/06/2014 00:33:38
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity ImagePatchReader is
port ( addr : in std_logic_vector (31 downto 0);
kptScale : in std_logic_vector(KPT_SCALE_BW-1 downto 0);--keypoint's scale
busy_in : in std_logic;
clk : in std_logic;
memData : in std_logic_vector (PIXEL_BW-1 downto 0);
rst : in std_logic;
addrKernel : out std_logic_vector (N_GAUSS_KERNEL_BW-1 downto 0);
en_out : out std_logic;
memAddr : out std_logic_vector (31 downto 0);
patchColumn : out T_INPUT_VERTICAL_CONVOLUTION;
readMem : out std_logic;
request_out : out std_logic
);
end ImagePatchReader;
architecture BEHAVIORAL of ImagePatchReader is
signal s_column_array: T_INPUT_VERTICAL_CONVOLUTION;
type consumer_FSM_states is (INIT, REQ, WAITING, READY);
signal s_consumerState: consumer_FSM_states;
type reading_mem_states is (INIT, READING, READY, END_READ);
signal s_readingMemState: reading_mem_states;
signal s_mem_addr: std_logic_vector(31 downto 0);
signal row_counter: integer range 0 to KERNEL_SIZE;
signal col_counter: integer range 0 to KERNEL_SIZE;
signal pointCounterA: integer range 0 to N_POINTS-1;--total number of points
signal pointCounterB: integer range 0 to 6;--number of points on each concentric circle
signal sAddrKernel: std_logic_vector (N_GAUSS_KERNEL_BW-1 downto 0);
begin
consumer_proc: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_consumerState <= INIT;
else
case s_consumerState is
when INIT =>
if busy_in = '0' then
request_out <= '1';
s_consumerState <= REQ;
end if;
when REQ =>
if busy_in = '1' then
request_out <= '0';
s_consumerState <= WAITING;
end if;
when WAITING =>
if busy_in = '0' then
s_consumerState <= READY;
end if;
when READY =>
if s_readingMemState = END_READ then
s_consumerState <= INIT;
end if;
end case;
end if;
end if;
end process;
patch_reading_proc: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_readingMemState <= INIT;
s_column_array <= (others => (others => '0'));
en_out <= '0';
readMem <= '0';
elsif s_consumerState = READY then
case s_readingMemState is
when INIT =>
s_mem_addr <= std_logic_vector(to_unsigned(to_integer(unsigned(addr)) +
(KERNEL_SIZE_ROM-1)*(1-IMAGE_WIDTH)
, s_mem_addr'length));
readMem <= '1';
s_readingMemState <= READING;
row_counter <= 0;
col_counter <= 0;
en_out <= '0';
when READING =>
readMem <= '0';
s_readingMemState <= READY;
en_out <= '0';
when READY =>
s_column_array(0) <= memData;
for i in 1 to KERNEL_SIZE-1 loop
s_column_array(i) <= s_column_array(i-1);
end loop;
--read the next pixel
if row_counter = KERNEL_SIZE-1 then
row_counter <= 0;
if col_counter = KERNEL_SIZE-1 then
s_readingMemState <= END_READ;
col_counter <= 0;
readMem <= '0';
else
s_mem_addr <= std_logic_vector(to_unsigned(
to_integer(unsigned(s_mem_addr))
- (IMAGE_WIDTH*(KERNEL_SIZE-1)+1)
, s_mem_addr'length)); --first row, previous column
col_counter <= col_counter + 1;
readMem <= '1';
s_readingMemState <= READING;
end if;
en_out <= '1';
else
s_mem_addr <= std_logic_vector(to_unsigned(to_integer(
unsigned(s_mem_addr)) +IMAGE_WIDTH
, s_mem_addr'length));--next row, same column
row_counter <= row_counter + 1;
en_out <= '0';
readMem <= '1';
s_readingMemState <= READING;
end if;
when END_READ =>
en_out <= '0';
s_readingMemState <= INIT;
end case;
else
en_out <= '0';
end if;
end if;
end process;
selectGaussKernel: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
pointCounterA <= 0;
pointCounterB <= 0;
sAddrKernel <= (others => '0');
elsif s_readingMemState = END_READ then
if pointCounterA = N_POINTS-1 then
pointCounterA <= 0;
sAddrKernel <= (others => '0');
else
pointCounterA <= pointCounterA + 1;
end if;
if pointCounterA /= N_POINTS-2 then
if pointCounterB = 5 then
pointCounterB <= 0;
sAddrKernel <= std_logic_vector(resize(unsigned(sAddrKernel) + 1 , sAddrKernel'length));
else
pointCounterB <= pointCounterB + 1;
end if;
end if;
end if;
end if;
end process;
memAddr <= s_mem_addr;
patchColumn <= s_column_array;
addrKernel <= std_logic_vector(resize(unsigned(sAddrKernel) + unsigned(kptScale)*NKERNEL_BY_SCALES, sAddrKernel'length));
end BEHAVIORAL;
| gpl-3.0 | 9337d2c40c8d79a7c198bcc1f9bac1f2 | 0.548172 | 3.600836 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-full-a.vhd | 2 | 6,062 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Chip toplevel design with full feature set
--
-- $Id: chip-full-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture full of chip is
component spi_boot
generic (
width_set_sel_g : integer := 4;
width_bit_cnt_g : integer := 6;
width_img_cnt_g : integer := 2;
num_bits_per_img_g : integer := 18;
sd_init_g : integer := 0;
mmc_compat_clk_div_g : integer := 0;
width_mmc_clk_div_g : integer := 0;
reset_level_g : integer := 0
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0);
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
spi_en_outs_o : out std_logic;
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end component;
signal spi_clk_s : std_logic;
signal spi_cs_n_s : std_logic;
signal spi_data_out_s : std_logic;
signal spi_en_outs_s : std_logic;
signal set_sel_s : std_logic_vector(3 downto 0);
begin
set_sel_s <= not set_sel_n_i;
spi_boot_b : spi_boot
generic map (
width_set_sel_g => 4, -- 16 sets
width_bit_cnt_g => 12, -- 512 bytes per block
width_img_cnt_g => 2, -- 4 images
num_bits_per_img_g => 18, -- 256 kByte per image
sd_init_g => 1, -- use SD specific initialization
mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2)
width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider
)
port map (
clk_i => clk_i,
reset_i => reset_i,
set_sel_i => set_sel_s,
spi_clk_o => spi_clk_s,
spi_cs_n_o => spi_cs_n_s,
spi_data_in_i => spi_data_in_i,
spi_data_out_o => spi_data_out_s,
spi_en_outs_o => spi_en_outs_s,
start_i => start_i,
mode_i => mode_i,
config_n_o => config_n_o,
detached_o => detached_o,
cfg_init_n_i => cfg_init_n_i,
cfg_done_i => cfg_done_i,
dat_done_i => dat_done_i,
cfg_clk_o => cfg_clk_o,
cfg_dat_o => cfg_dat_o
);
-----------------------------------------------------------------------------
-- Three state drivers for SPI outputs.
-----------------------------------------------------------------------------
spi_clk_o <= spi_clk_s
when spi_en_outs_s = '1' else
'Z';
spi_cs_n_o <= spi_cs_n_s
when spi_en_outs_s = '1' else
'Z';
spi_data_out_o <= spi_data_out_s
when spi_en_outs_s = '1' else
'Z';
end full;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: chip-full-a.vhd,v $
-- Revision 1.6 2005/04/07 20:44:23 arniml
-- add new port detached_o
--
-- Revision 1.5 2005/03/09 19:48:34 arniml
-- invert level of set_sel input
--
-- Revision 1.4 2005/03/08 22:07:12 arniml
-- added set selection
--
-- Revision 1.3 2005/02/18 06:42:11 arniml
-- clarify wording for images
--
-- Revision 1.2 2005/02/16 18:54:37 arniml
-- added tri-state drivers for spi outputs
--
-- Revision 1.1 2005/02/08 20:41:31 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 72b7ffc3b368e33fd5e08655b9cdc7a9 | 0.539591 | 3.632115 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_syn/usb_host.vhd | 3 | 11,187 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_host is
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- ULPI Interface
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- register interface bus
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_address : in std_logic_vector(12 downto 0); -- 8K block
sys_write : in std_logic;
sys_request : in std_logic;
sys_wdata : in std_logic_vector(7 downto 0);
sys_rdata : out std_logic_vector(7 downto 0);
sys_rack : out std_logic;
sys_dack : out std_logic );
-- -- Interface to read/write registers
-- read_reg : in std_logic;
-- write_reg : in std_logic;
-- reg_ack : out std_logic;
-- address : in std_logic_vector(5 downto 0);
-- write_data : in std_logic_vector(7 downto 0);
-- read_data : out std_logic_vector(7 downto 0) );
--
end usb_host;
architecture wrap of usb_host is
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(11 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal send_token : std_logic;
signal send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal send_data : std_logic;
signal no_data : std_logic;
signal user_data : std_logic_vector(7 downto 0);
signal user_last : std_logic;
signal user_valid : std_logic;
signal user_next : std_logic;
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal valid_token : std_logic := '0';
signal valid_handsh : std_logic := '0';
signal valid_packet : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_start : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := X"12";
signal rx_error : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
signal read_reg : std_logic := '0';
signal write_reg : std_logic;
signal reg_ack : std_logic;
signal address : std_logic_vector(5 downto 0);
signal write_data : std_logic_vector(7 downto 0);
signal read_data : std_logic_vector(7 downto 0);
signal reset_pkt : std_logic;
signal reset_valid : std_logic;
signal reset_last : std_logic;
signal reset_data : std_logic_vector(7 downto 0);
signal power_en : std_logic;
signal do_reset : std_logic;
signal reset_done : std_logic;
signal speed : std_logic_vector(1 downto 0);
signal sys_buf_en : std_logic;
signal sys_descr_en : std_logic;
signal sys_sel_d : std_logic;
signal sys_buf_rdata : std_logic_vector(7 downto 0);
signal sys_descr_rdata : std_logic_vector(7 downto 0);
begin
i_host: entity work.ulpi_host
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
-- Interface to bus reset unit
power_en => power_en,
do_reset => do_reset,
reset_done => reset_done,
speed => speed,
reset_pkt => reset_pkt,
reset_data => reset_data,
reset_last => reset_last,
reset_valid => reset_valid,
-- Interface to read/write registers
-- read_reg => read_reg,
-- write_reg => write_reg,
-- address => address,
-- write_data => write_data,
-- read_data => X"55", -- read_data
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
i_descr_ram: RAMB16_S9_S36
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_descr_en,
WEA => sys_write,
ADDRA => sys_address(10 downto 0),
DIA => sys_wdata,
DIPA => "0",
DOA => sys_descr_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => descr_en,
WEB => descr_we,
ADDRB => descr_addr,
DIB => descr_wdata,
DIPB => X"0",
DOB => descr_rdata );
i_buf_ram: RAMB16_S9_S9
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_write,
ADDRA => sys_address(10 downto 0),
DIA => sys_wdata,
DIPA => "0",
DOA => sys_buf_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => buf_addr(10 downto 0),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata );
sys_buf_en <= sys_request and sys_address(12);
sys_descr_en <= sys_request and not sys_address(12);
sys_rack <= sys_request;
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_dack <= sys_request;
sys_sel_d <= sys_address(12);
end if;
end process;
sys_rdata <= sys_buf_rdata when sys_sel_d='1' else sys_descr_rdata;
i_tx: entity work.ulpi_tx
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
rx_register => rx_register,
rx_data => rx_data,
-- Status
busy => tx_busy,
tx_ack => tx_ack,
reg_ack => reg_ack,
-- Interface to send tokens
send_token => send_token,
send_handsh => send_handsh,
pid => tx_pid,
token => tx_token,
-- Interface to send data packets
send_data => send_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
-- Interface to read/write registers
read_reg => read_reg,
write_reg => write_reg,
address => address,
write_data => write_data,
read_data => read_data );
i_rx: entity work.ulpi_rx
generic map (
g_allow_token => false )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => rx_pid,
token => rx_token,
valid_token => valid_token,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => rx_error );
i_bus: entity work.ulpi_bus
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_reset: entity work.bus_reset
port map (
clock => ulpi_clock,
reset => ulpi_reset,
do_reset => do_reset,
power_en => power_en,
reset_done => reset_done,
speed => speed,
-- status
status => status,
-- register interface
write_reg => write_reg,
write_data => write_data,
address => address,
reg_ack => reg_ack,
send_packet => reset_pkt,
user_data => reset_data,
user_last => reset_last,
user_valid => reset_valid );
end wrap;
| gpl-3.0 | d37d60792bd46b5ab74337e0f24a4052 | 0.475641 | 3.640417 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_source/char_generator_peripheral.vhd | 4 | 5,893 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_peripheral.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator top
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator_peripheral is
generic (
g_color_ram : boolean := false;
g_screen_size : natural := 11 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '0');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '0');
pix_clock : in std_logic;
pix_reset : in std_logic;
h_count : in unsigned(11 downto 0);
v_count : in unsigned(11 downto 0);
pixel_active : out std_logic;
pixel_opaque : out std_logic;
pixel_data : out unsigned(3 downto 0) );
end entity;
architecture structural of char_generator_peripheral is
signal control : t_chargen_control;
signal screen_addr : unsigned(g_screen_size-1 downto 0);
signal screen_data : std_logic_vector(7 downto 0);
signal color_data : std_logic_vector(7 downto 0) := X"0F";
signal char_addr : unsigned(10 downto 0);
signal char_data : std_logic_vector(7 downto 0);
signal io_req_regs : t_io_req := c_io_req_init;
signal io_req_scr : t_io_req := c_io_req_init;
signal io_req_color : t_io_req := c_io_req_init;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_resp_scr : t_io_resp := c_io_resp_init;
signal io_resp_color : t_io_resp := c_io_resp_init;
begin
overlay_on <= control.overlay_on;
-- allocate 32K for character memory
-- allocate 32K for color memory
-- allocate another space for registers
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => g_screen_size,
g_range_hi => g_screen_size+1,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_regs, -- size=15: xxx0000, size=11: xxx0000
reqs(1) => io_req_scr, -- size=15: xxx8000, size=11: xxx0800
reqs(2) => io_req_color, -- size=15: xx10000, size=11: xxx1000
resps(0) => io_resp_regs,
resps(1) => io_resp_scr,
resps(2) => io_resp_color );
i_regs: entity work.char_generator_regs
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
keyb_row => keyb_row,
keyb_col => keyb_col,
control => control );
i_timing: entity work.char_generator_slave
generic map (
g_screen_size => g_screen_size )
port map (
clock => pix_clock,
reset => pix_reset,
h_count => h_count,
v_count => v_count,
control => control,
screen_addr => screen_addr,
screen_data => screen_data,
color_data => color_data,
char_addr => char_addr,
char_data => char_data,
pixel_active => pixel_active,
pixel_opaque => pixel_opaque,
pixel_data => pixel_data );
i_rom: entity work.char_generator_rom
port map (
clock => pix_clock,
enable => '1',
address => char_addr,
data => char_data );
-- process(pix_clock)
-- begin
-- if rising_edge(pix_clock) then
-- screen_data <= std_logic_vector(screen_addr(7 downto 0));
-- color_data <= std_logic_vector(screen_addr(10 downto 3));
-- end if;
-- end process;
i_screen: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"20",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => screen_Data,
b_clock => clock,
b_req => io_req_scr,
b_resp => io_resp_scr );
r_color: if g_color_ram generate
i_color: entity work.dpram_io
generic map (
g_depth_bits => g_screen_size, -- max = 15 for 1920x1080
g_default => X"0F",
g_storage => "block" )
port map (
a_clock => pix_clock,
a_address => screen_addr,
a_rdata => color_data,
b_clock => clock,
b_req => io_req_color,
b_resp => io_resp_color );
end generate;
end structural;
| gpl-3.0 | 81f39653fe6da32012389e0a0336246d | 0.445104 | 3.787275 | false | false | false | false |
multiple1902/xjtu_comp-org-lab | modules/fourstep/fourstep.vhdl | 1 | 744 | -- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fourstep is
port (
clk : in std_logic;
step : out std_logic_vector(3 downto 0) -- no semicolon here!
);
end fourstep;
architecture behv of fourstep is
signal state, nstate: std_logic_vector(3 downto 0) := "0001";
begin
process(clk)
begin
-- if clk='1' then
step(3 downto 0) <= "1111";
nstate(2 downto 0)<=state(3 downto 1);
nstate(3) <= state(0);
state(3 downto 0)<=nstate(3 downto 0);
step(3 downto 0) <= nstate(3 downto 0);
-- end if;
end process;
end behv;
| gpl-3.0 | af9bac876548078179157a563fcbb8a9 | 0.580645 | 3.412844 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/srl_fifo/vhdl_source/srl_fifo.vhd | 3 | 3,787 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Fifo Using SRL16
-------------------------------------------------------------------------------
-- File : srl_fifo.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This implementation makes use of the SRL16 properties,
-- implementing a 16-deep synchronous fifo in only one LUT per
-- bit. It is a fall-through fifo.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity srl_fifo is
generic (Width : integer := 32;
Depth : integer := 15; -- 15 is the maximum
Threshold : integer := 13);
port (
clock : in std_logic;
reset : in std_logic;
GetElement : in std_logic;
PutElement : in std_logic;
FlushFifo : in std_logic;
DataIn : in std_logic_vector(Width-1 downto 0);
DataOut : out std_logic_vector(Width-1 downto 0);
SpaceInFifo : out std_logic;
AlmostFull : out std_logic;
DataInFifo : out std_logic);
end SRL_fifo;
architecture Gideon of srl_fifo is
signal NumElements : std_logic_vector(3 downto 0);
signal FilteredGet : std_logic;
signal FilteredPut : std_logic;
signal DataInFifo_i : std_logic;
signal SpaceInFifo_i : std_logic;
constant Depth_std : std_logic_vector(3 downto 0) := conv_std_logic_vector(Depth-1, 4);
begin
FilteredGet <= DataInFifo_i and GetElement;
FilteredPut <= SpaceInFifo_i and PutElement;
DataInFifo <= DataInFifo_i;
SpaceInFifo <= SpaceInFifo_i;
process(clock)
variable NewCnt : std_logic_vector(3 downto 0);--integer range 0 to Depth;
begin
if rising_edge(clock) then
if FlushFifo='1' then
NewCnt := "1111"; --0;
elsif (FilteredGet='1') and (FilteredPut='0') then
NewCnt := NumElements - 1;
elsif (FilteredGet='0') and (FilteredPut='1') then
NewCnt := NumElements + 1;
else
NewCnt := NumElements;
end if;
NumElements <= NewCnt;
if (NewCnt > Threshold) and (NewCnt /= "1111") then
AlmostFull <= '1';
else
AlmostFull <= '0';
end if;
if (NewCnt = "1111") then
DataInFifo_i <= '0';
else
DataInFifo_i <= '1';
end if;
if (NewCnt /= Depth_std) then
SpaceInFifo_i <= '1';
else
SpaceInFifo_i <= '0';
end if;
if Reset='1' then
NumElements <= "1111";
SpaceInFifo_i <= '1';
DataInFifo_i <= '0';
AlmostFull <= '0';
end if;
end if;
end process;
SRLs : for srl2 in 0 to Width-1 generate
i_SRL : SRL16E
port map (
CLK => clock,
CE => FilteredPut,
D => DataIn(srl2),
A3 => NumElements(3),
A2 => NumElements(2),
A1 => NumElements(1),
A0 => NumElements(0),
Q => DataOut(srl2) );
end generate;
end Gideon;
| gpl-3.0 | 89f964c5fcf762528a84269b917a5f14 | 0.460259 | 4.293651 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cpu_unit/vhdl_source/mem32k.vhd | 5 | 2,193 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem32k is
generic (
simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
address : in std_logic_vector(26 downto 0);
request : in std_logic;
mwrite : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
rack : out std_logic;
dack : out std_logic;
claimed : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of mem32k : entity is "yes";
end mem32k;
architecture gideon of mem32k is
subtype t_byte is std_logic_vector(7 downto 0);
type t_byte_array is array(natural range <>) of t_byte;
signal my_mem : t_byte_array(0 to 32767);
signal claimed_i : std_logic;
signal do_write : std_logic;
attribute ram_style : string;
attribute ram_style of my_mem : signal is "block";
begin
claimed_i <= '1' when address(26 downto 15) = "000000000000"
else '0';
claimed <= claimed_i;
rack <= claimed_i and request;
do_write <= claimed_i and request and mwrite;
-- synthesis translate_off
model: if simulation generate
mram: entity work.bram_model_8sp
generic map("intram", 15) -- 32k
port map (
CLK => clock,
SSR => reset,
EN => request,
WE => do_write,
ADDR => address(14 downto 0),
DI => wdata,
DO => rdata );
end generate;
-- synthesis translate_on
process(clock)
begin
if rising_edge(clock) then
if not simulation then
rdata <= my_mem(to_integer(unsigned(address(14 downto 0))));
else
rdata <= (others => 'Z');
end if;
dack <= claimed_i and request;
if do_write='1' then
my_mem(to_integer(unsigned(address(14 downto 0)))) <= wdata;
end if;
end if;
end process;
end gideon;
| gpl-3.0 | 58b71ce039c1e83ddcf54c7728c0e58f | 0.532148 | 3.716949 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/zpupkg.vhd | 5 | 14,617 | ------------------------------------------------------------------------------
---- ----
---- ZPU Package ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the package. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpupkg, UART (Package) ----
---- File name: zpu_medium.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: Spartan 3 (XC3S400-4-FT256) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package zpupkg is
constant c_opcode_width : integer:=8;
-- Debug structure, currently only for the trace module
type zpu_dbgo_t is record
b_inst : std_logic;
opcode : unsigned(c_opcode_width-1 downto 0);
pc : unsigned(31 downto 0);
sp : unsigned(31 downto 0);
stk_a : unsigned(31 downto 0);
stk_b : unsigned(31 downto 0);
end record;
component Trace is
generic(
LOG_FILE : string:="trace.txt"; -- Name of the trace file
ADDR_W : integer:=16; -- Address width
WORD_SIZE : integer:=32); -- 16/32
port(
clk_i : in std_logic;
dbg_i : in zpu_dbgo_t;
stop_i : in std_logic;
busy_i : in std_logic
);
end component Trace;
component ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end component ZPUSmallCore;
component ZPUMediumCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
MULT_PIPE : boolean:=false; -- Pipeline multiplication
BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
ENA_LEVEL2 : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
ENA_LSHR : boolean:=true; -- lshiftright
ENA_IDLE : boolean:=false; -- Enable the enable_i input
FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
port(
clk_i : in std_logic; -- CPU Clock
reset_i : in std_logic; -- Sync Reset
enable_i : in std_logic; -- Hold the CPU (after reset)
break_o : out std_logic; -- Break instruction executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- Memory interface
mem_busy_i : in std_logic; -- Memory is busy
data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
write_en_o : out std_logic; -- Memory write enable
read_en_o : out std_logic); -- Memory read enable
end component ZPUMediumCore;
component Timer is
port(
clk_i : in std_logic;
reset_i : in std_logic;
we_i : in std_logic;
data_i : in unsigned(31 downto 0);
addr_i : in unsigned(0 downto 0);
data_o : out unsigned(31 downto 0));
end component Timer;
component ZPUPhiIO is
generic(
BRDIVISOR : positive:=1; -- Baud rate divisor i.e. br_clk/9600/4
ENA_LOG : boolean:=true; -- Enable log
LOG_FILE : string:="log.txt"); -- Name for the log file
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
busy_o : out std_logic; -- I/O is busy
we_i : in std_logic; -- Write Enable
re_i : in std_logic; -- Read Enable
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
addr_i : in unsigned(2 downto 0); -- Address bits 4-2
rs232_rx_i : in std_logic; -- UART Rx input
rs232_tx_o : out std_logic; -- UART Tx output
br_clk_i : in std_logic); -- UART base clock (enable)
end component ZPUPhiIO;
-- Opcode decode constants
-- Note: these are the basic opcodes, always implemented using hardware.
constant OPCODE_IM : unsigned(7 downto 7):="1";
constant OPCODE_STORESP : unsigned(7 downto 5):="010";
constant OPCODE_LOADSP : unsigned(7 downto 5):="011";
constant OPCODE_EMULATE : unsigned(7 downto 5):="001";
constant OPCODE_ADDSP : unsigned(7 downto 4):="0001";
constant OPCODE_SHORT : unsigned(7 downto 4):="0000";
constant OPCODE_BREAK : unsigned(3 downto 0):="0000";
constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001";
constant OPCODE_PUSHSP : unsigned(3 downto 0):="0010";
constant OPCODE_PUSHINT : unsigned(3 downto 0):="0011";
constant OPCODE_POPPC : unsigned(3 downto 0):="0100";
constant OPCODE_ADD : unsigned(3 downto 0):="0101";
constant OPCODE_AND : unsigned(3 downto 0):="0110";
constant OPCODE_OR : unsigned(3 downto 0):="0111";
constant OPCODE_LOAD : unsigned(3 downto 0):="1000";
constant OPCODE_NOT : unsigned(3 downto 0):="1001";
constant OPCODE_FLIP : unsigned(3 downto 0):="1010";
constant OPCODE_NOP : unsigned(3 downto 0):="1011";
constant OPCODE_STORE : unsigned(3 downto 0):="1100";
constant OPCODE_POPSP : unsigned(3 downto 0):="1101";
constant OPCODE_COMPARE : unsigned(3 downto 0):="1110";
constant OPCODE_POPINT : unsigned(3 downto 0):="1111";
-- The following instructions are emulated in the small version and
-- implemented as hardware in the full version.
-- The constants correpond to the "emulated" instruction number.
-- Enabled by the ENA_LEVEL0 generic:
constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6);
constant OPCODE_LOADB : unsigned(5 downto 0):=to_unsigned(51,6);
constant OPCODE_NEQBRANCH : unsigned(5 downto 0):=to_unsigned(56,6);
constant OPCODE_PUSHSPADD : unsigned(5 downto 0):=to_unsigned(61,6);
-- Enabled by the ENA_LEVEL1 generic:
constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6);
constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6);
constant OPCODE_MULT : unsigned(5 downto 0):=to_unsigned(41,6);
constant OPCODE_STOREB : unsigned(5 downto 0):=to_unsigned(52,6);
constant OPCODE_CALLPCREL : unsigned(5 downto 0):=to_unsigned(63,6);
constant OPCODE_SUB : unsigned(5 downto 0):=to_unsigned(49,6);
-- Enabled by the ENA_LEVEL2 generic:
constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6);
constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6);
constant OPCODE_CALL : unsigned(5 downto 0):=to_unsigned(45,6);
constant OPCODE_POPPCREL : unsigned(5 downto 0):=to_unsigned(57,6);
-- Enabled by the ENA_LSHR generic:
constant OPCODE_LSHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(42,6);
-- The following opcodes are always emulated.
constant OPCODE_LOADH : unsigned(5 downto 0):=to_unsigned(34,6);
constant OPCODE_STOREH : unsigned(5 downto 0):=to_unsigned(35,6);
constant OPCODE_ASHIFTLEFT : unsigned(5 downto 0):=to_unsigned(43,6);
constant OPCODE_ASHIFTRIGHT : unsigned(5 downto 0):=to_unsigned(44,6);
constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6);
constant OPCODE_NEG : unsigned(5 downto 0):=to_unsigned(48,6);
constant OPCODE_XOR : unsigned(5 downto 0):=to_unsigned(50,6);
constant OPCODE_DIV : unsigned(5 downto 0):=to_unsigned(53,6);
constant OPCODE_MOD : unsigned(5 downto 0):=to_unsigned(54,6);
constant OPCODE_EQBRANCH : unsigned(5 downto 0):=to_unsigned(55,6);
constant OPCODE_CONFIG : unsigned(5 downto 0):=to_unsigned(58,6);
constant OPCODE_PUSHPC : unsigned(5 downto 0):=to_unsigned(59,6);
end package zpupkg;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package UART is
----------------------
-- Very simple UART --
----------------------
component RxUnit is
port(
clk_i : in std_logic; -- System clock signal
reset_i : in std_logic; -- Reset input (sync)
enable_i : in std_logic; -- Enable input (rate*4)
read_i : in std_logic; -- Received Byte Read
rxd_i : in std_logic; -- RS-232 data input
rxav_o : out std_logic; -- Byte available
datao_o : out std_logic_vector(7 downto 0)); -- Byte received
end component RxUnit;
component TxUnit is
port (
clk_i : in std_logic; -- Clock signal
reset_i : in std_logic; -- Reset input
enable_i : in std_logic; -- Enable input
load_i : in std_logic; -- Load input
txd_o : out std_logic; -- RS-232 data output
busy_o : out std_logic; -- Tx Busy
datai_i : in std_logic_vector(7 downto 0)); -- Byte to transmit
end component TxUnit;
component BRGen is
generic(
COUNT : integer range 0 to 65535);-- Count revolution
port (
clk_i : in std_logic; -- Clock
reset_i : in std_logic; -- Reset input
ce_i : in std_logic; -- Chip Enable
o_o : out std_logic); -- Output
end component BRGen;
end package UART;
| gpl-3.0 | 680002e93331d9d5d1348071decd49c2 | 0.480126 | 4.1256 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_source/usb_host_io.vhd | 3 | 15,325 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb_host_io is
generic (
g_simulation : boolean := false );
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- ULPI Interface
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- LED interface
usb_busy : out std_logic;
-- register interface bus
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp );
end usb_host_io;
architecture wrap of usb_host_io is
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(10 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal send_token : std_logic;
signal send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal send_data : std_logic;
signal no_data : std_logic;
signal user_data : std_logic_vector(7 downto 0);
signal user_last : std_logic;
signal user_next : std_logic;
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal valid_token : std_logic := '0';
signal valid_handsh : std_logic := '0';
signal valid_packet : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_start : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := X"12";
signal rx_error : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
signal reg_read : std_logic := '0';
signal reg_write : std_logic;
signal reg_ack : std_logic;
signal reg_addr : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
-- signal reset_pkt : std_logic;
-- signal reset_valid : std_logic;
-- signal reset_last : std_logic;
-- signal reset_data : std_logic_vector(7 downto 0);
signal send_reset_data : std_logic;
signal reset_last : std_logic;
signal reset_data : std_logic_vector(7 downto 0);
signal reset_done : std_logic;
signal sof_enable : std_logic;
signal scan_enable : std_logic;
signal speed : std_logic_vector(1 downto 0);
signal abort : std_logic;
signal sys_addr_i : std_logic_vector(sys_io_req.address'range);
signal sys_buf_en : std_logic;
signal sys_descr_en : std_logic;
signal sys_sel_d : std_logic_vector(2 downto 0);
signal sys_buf_rdata : std_logic_vector(7 downto 0);
signal sys_descr_rdata : std_logic_vector(7 downto 0);
signal sys_cmd_read : std_logic;
signal sys_cmd_write : std_logic;
signal sys_cmd_rdata : std_logic_vector(7 downto 0);
signal sys_cmd_full : std_logic;
signal sys_cmd_count : std_logic_vector(2 downto 0);
signal sys_resp_get : std_logic;
signal sys_resp_data : std_logic_vector(8 downto 0);
signal sys_resp_empty : std_logic;
signal cmd_get : std_logic;
signal cmd_empty : std_logic;
signal cmd_data : std_logic_vector(7 downto 0);
signal resp_put : std_logic;
signal resp_full : std_logic;
signal resp_data : std_logic_vector(8 downto 0);
begin
i_host: entity work.ulpi_host
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_next => user_next,
-- Interface to bus reset unit
reset_done => reset_done,
sof_enable => sof_enable,
scan_enable => scan_enable,
speed => speed,
abort => abort,
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
i_descr_ram: RAMB16_S9_S36
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_descr_en,
WEA => sys_io_req.write,
ADDRA => sys_addr_i(10 downto 0),
DIA => sys_io_req.data,
DIPA => "0",
DOA => sys_descr_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => descr_en,
WEB => descr_we,
ADDRB => descr_addr,
DIB => descr_wdata,
DIPB => X"0",
DOB => descr_rdata );
i_buf_ram: RAMB16_S9_S9
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_io_req.write,
ADDRA => sys_addr_i(10 downto 0),
DIA => sys_io_req.data,
DIPA => "0",
DOA => sys_buf_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => buf_addr(10 downto 0),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata );
i_tx: entity work.ulpi_tx
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
-- Status
speed => speed,
status => status,
busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens
send_token => send_token,
send_handsh => send_handsh,
pid => tx_pid,
token => tx_token,
-- Interface to send data packets
send_data => send_data,
user_data => user_data,
user_last => user_last,
user_next => user_next,
-- Interface to read/write registers and reset packets
send_reset_data => send_reset_data,
reset_data => reset_data(0),
reset_last => reset_last );
i_rx: entity work.ulpi_rx
generic map (
g_allow_token => false )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => rx_pid,
token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => rx_error );
i_bus: entity work.ulpi_bus
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_addr,
reg_wdata => reg_wdata,
reg_ack => reg_ack,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_reset: entity work.bus_reset
generic map (
g_simulation => g_simulation )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
reset_done => reset_done,
sof_enable => sof_enable,
scan_enable => scan_enable,
speed => speed,
abort => abort,
-- Command / response interface
cmd_get => cmd_get,
cmd_empty => cmd_empty,
cmd_data => cmd_data,
resp_put => resp_put,
resp_full => resp_full,
resp_data => resp_data,
-- status
status => status,
usb_busy => usb_busy,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_rdata => rx_data,
reg_wdata => reg_wdata,
reg_address => reg_addr,
reg_ack => reg_ack,
-- interface to packet transmitter
send_packet => send_reset_data,
user_data => reset_data,
user_last => reset_last,
user_valid => open );
i_cmd_fifo: entity work.async_fifo
generic map (
g_data_width => 8,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 3,
g_storage => "distributed" )
port map (
-- write port signals (synchronized to write clock)
wr_clock => sys_clock,
wr_reset => sys_reset,
wr_en => sys_cmd_write,
wr_din => sys_io_req.data,
wr_flush => '0',
wr_count => sys_cmd_count,
wr_full => open,
wr_almost_full => sys_cmd_full,
wr_error => open,
wr_inhibit => open,
-- read port signals (synchronized to read clock)
rd_clock => ulpi_clock,
rd_reset => ulpi_reset,
rd_en => cmd_get,
rd_dout => cmd_data,
rd_count => open,
rd_empty => cmd_empty,
rd_almost_empty => open,
rd_error => open );
i_resp_fifo: entity work.async_fifo
generic map (
g_data_width => 9,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 3,
g_storage => "distributed" )
port map (
-- write port signals (synchronized to write clock)
wr_clock => ulpi_clock,
wr_reset => ulpi_reset,
wr_en => resp_put,
wr_din => resp_data,
wr_flush => '0',
wr_count => open,
wr_full => resp_full,
wr_almost_full => open,
wr_error => open,
wr_inhibit => open,
-- read port signals (synchronized to read clock)
rd_clock => sys_clock,
rd_reset => sys_reset,
rd_en => sys_resp_get,
rd_dout => sys_resp_data,
rd_count => open,
rd_empty => sys_resp_empty,
rd_almost_empty => open,
rd_error => open );
-- BUS INTERFACE --
-- command / response output word generator
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_resp_get <= '0';
case sys_io_req.address(1 downto 0) is
when "00" =>
sys_cmd_rdata <= sys_resp_data(7 downto 0);
when "01" =>
sys_cmd_rdata <= not sys_resp_empty & "000000" & sys_resp_data(8);
when "10" =>
sys_cmd_rdata <= sys_cmd_full & "0000" & sys_cmd_count;
when "11" =>
sys_cmd_rdata <= X"00";
sys_resp_get <= sys_cmd_read; -- if reading, we'll pull one
when others =>
null;
end case;
end if;
end process;
sys_addr_i(sys_addr_i'high downto 0) <= std_logic_vector(sys_io_req.address(sys_addr_i'range));
sys_buf_en <= (sys_io_req.read or sys_io_req.write) and sys_io_req.address(12);
sys_descr_en <= (sys_io_req.read or sys_io_req.write) and not sys_io_req.address(12) and not sys_io_req.address(11);
sys_cmd_read <= sys_io_req.read and not sys_io_req.address(12) and sys_io_req.address(11);
sys_cmd_write <= sys_io_req.write and not sys_io_req.address(12) and sys_io_req.address(11);
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_io_resp.ack <= sys_io_req.read or sys_io_req.write;
sys_sel_d <= sys_io_req.read & std_logic_vector(sys_io_req.address(12 downto 11));
end if;
end process;
with sys_sel_d select sys_io_resp.data <=
sys_buf_rdata when "110" | "111",
sys_descr_rdata when "100",
sys_cmd_rdata when "101",
X"00" when others;
end wrap;
| gpl-3.0 | 78ca9e08bd575eba02b0d115e8cbf571 | 0.477912 | 3.633239 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op981_5.vhdl | 1 | 6,383 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net7
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net7,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net9
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net10
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | bc0d07893767638bd6a0747b398d1a2e | 0.573398 | 3.09704 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op952_17.vhdl | 1 | 5,941 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias2,
S => net5
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net5,
G => net1,
S => vdd
);
subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net6,
G => net1,
S => vdd
);
subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net6
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias2,
S => net7
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net2,
S => vdd
);
subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net2,
S => vdd
);
subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net3,
G => vbias3,
S => net9
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net10,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net10
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | f408935b73c30b6180ac4e704edf2e07 | 0.578017 | 3.125197 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op6.vhdl | 1 | 10,299 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.85e-06,
W => Wdiff_0,
Wdiff_0init => 4.38e-05,
scope => private
)
port map(
D => net2,
G => in1,
S => net5
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.85e-06,
W => Wdiff_0,
Wdiff_0init => 4.38e-05,
scope => private
)
port map(
D => net1,
G => in2,
S => net5
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => W_0,
W_0init => 3.105e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.85e-06,
W => Wdiff_0,
Wdiff_0init => 4.38e-05,
scope => private
)
port map(
D => net6,
G => in1,
S => net5
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.85e-06,
W => Wdiff_0,
Wdiff_0init => 4.38e-05,
scope => private
)
port map(
D => net6,
G => in2,
S => net5
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.23e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.36e-05,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.23e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.36e-05,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.23e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.36e-05,
scope => private
)
port map(
D => net1,
G => net6,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.23e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.36e-05,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => L_2,
L_2init => 5.75e-06,
W => Wsrc_1,
Wsrc_1init => 6.765e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => L_3,
L_3init => 5.4e-06,
W => Wsrc_1,
Wsrc_1init => 6.765e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcm_2,
Wcm_2init => 1.855e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcmout_2,
Wcmout_2init => 7.73e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => C_4,
symmetry_scope => sym_4
)
port map(
P => out1,
N => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcm_2,
Wcm_2init => 1.855e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcmout_2,
Wcmout_2init => 7.73e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => out2,
G => net4,
S => vdd
);
subnet0_subnet4_c1 : entity cap(behave)
generic map(
C => C_5,
symmetry_scope => sym_4
)
port map(
P => out2,
N => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => Wcursrc_3,
Wcursrc_3init => 5.115e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet6_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => Wcursrc_3,
Wcursrc_3init => 5.115e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net7,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net10,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net9,
N => net7
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => W_1,
W_1init => 1.785e-05
)
port map(
D => net8,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 7.7e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 7.935e-05,
scope => private
)
port map(
D => net10,
G => vref,
S => net8
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 7.7e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 7.935e-05,
scope => private
)
port map(
D => net9,
G => net7,
S => net8
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 7.15e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 6e-07,
scope => private
)
port map(
D => net9,
G => net9,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 7.15e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 6e-07,
scope => private
)
port map(
D => net10,
G => net9,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 1.05e-06,
W => Wcmbias_0,
Wcmbias_0init => 7.435e-05,
scope => private
)
port map(
D => out1,
G => net10,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 1.05e-06,
W => Wcmbias_0,
Wcmbias_0init => 7.435e-05,
scope => private
)
port map(
D => out2,
G => net10,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => (pfak)*(WBias),
WBiasinit => 5.7e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 9.5e-07,
W => (pfak)*(WBias),
WBiasinit => 5.7e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 9.5e-07,
W => WBias,
WBiasinit => 5.7e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => WBias,
WBiasinit => 5.7e-06
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => WBias,
WBiasinit => 5.7e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => WBias,
WBiasinit => 5.7e-06
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 49f853e3c3b7015d02b50d15f08426b9 | 0.566948 | 2.804739 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/copper/vhdl_source/copper_engine.vhd | 5 | 10,510 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.dma_bus_pkg.all;
use work.copper_pkg.all;
entity copper_engine is
generic (
g_copper_size : natural := 12 );
port (
clock : in std_logic;
reset : in std_logic;
irq_n : in std_logic;
phi2_tick : in std_logic;
ram_address : out unsigned(g_copper_size-1 downto 0);
ram_rdata : in std_logic_vector(7 downto 0);
ram_wdata : out std_logic_vector(7 downto 0);
ram_en : out std_logic;
ram_we : out std_logic;
trigger_1 : out std_logic;
trigger_2 : out std_logic;
dma_req : out t_dma_req;
dma_resp : in t_dma_resp;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
control : in t_copper_control;
status : out t_copper_status );
end copper_engine;
architecture gideon of copper_engine is
signal irq_c : std_logic;
signal irq_d : std_logic;
signal opcode : std_logic_vector(7 downto 0);
signal sync : std_logic;
signal timer : unsigned(15 downto 0);
signal match : unsigned(15 downto 0);
signal addr_i : unsigned(ram_address'range);
type t_state is (idle, fetch, decode, fetch2, decode2, fetch3, decode3, wait_irq, wait_sync, wait_until, wait_dma,
record_start, recording, record_end);
signal state : t_state;
signal store_word : std_logic_vector(31 downto 0) := (others => '0');
signal store_trig : std_logic := '0';
signal fifo_dout : std_logic_vector(31 downto 0) := (others => '0');
signal fifo_dav : std_logic;
signal fifo_pop : std_logic;
signal ram_we_i : std_logic;
begin
p_fsm: process(clock)
procedure process_fifo_data is
begin
if fifo_dav='1' then
addr_i <= addr_i + 1;
end if;
end procedure;
begin
if rising_edge(clock) then
irq_c <= not irq_n;
irq_d <= irq_c;
trigger_1 <= '0';
trigger_2 <= '0';
store_trig <= '0';
slot_resp <= c_slot_resp_init;
sync <= '0';
if timer = control.frame_length then
timer <= (others => '0');
sync <= '1';
elsif phi2_tick='1' then
timer <= timer + 1;
end if;
case state is
when idle =>
addr_i <= (others => '0');
case control.command is
when c_copper_cmd_play =>
state <= fetch;
status.running <= '1';
when c_copper_cmd_record =>
state <= record_start;
status.running <= '1';
when others =>
null;
end case;
when fetch =>
addr_i <= addr_i + 1;
state <= decode;
when decode =>
opcode <= ram_rdata;
if ram_rdata(7 downto 6) = c_copcode_write_reg(7 downto 6) then
state <= fetch2;
elsif ram_rdata(7 downto 6) = c_copcode_read_reg(7 downto 6) then
dma_req.request <= '1';
dma_req.read_writen <= '1';
dma_req.address <= X"D0" & "00" & unsigned(ram_rdata(5 downto 0));
state <= wait_dma;
else
case ram_rdata is
when c_copcode_wait_irq => -- waits until falling edge of IRQn
state <= wait_irq;
when c_copcode_wait_sync => -- waits until sync pulse from timer
state <= wait_sync;
when c_copcode_timer_clr => -- clears timer
timer <= (others => '0');
state <= fetch;
when c_copcode_capture => -- copies timer to measure register
status.measured_time <= timer;
state <= fetch;
when c_copcode_wait_for => -- takes a 1 byte argument
state <= fetch2;
when c_copcode_wait_until => -- takes 2 bytes argument (wait until timer match)
state <= fetch2;
when c_copcode_repeat => -- restart at program address 0.
addr_i <= (others => '0');
state <= fetch;
when c_copcode_end => -- ends operation and return to idle
state <= idle;
status.running <= '0';
when c_copcode_trigger_1 =>
trigger_1 <= '1';
state <= fetch;
when c_copcode_trigger_2 =>
trigger_2 <= '1';
state <= fetch;
when others =>
state <= fetch;
end case;
end if;
when wait_irq =>
if irq_c='1' and irq_d='0' then
state <= fetch;
end if;
when wait_sync =>
if sync='1' then
state <= fetch;
end if;
when fetch2 =>
addr_i <= addr_i + 1;
state <= decode2;
when decode2 =>
if opcode(7 downto 6) = c_copcode_write_reg(7 downto 6) then
dma_req.request <= '1';
dma_req.read_writen <= '0';
dma_req.address <= X"D0" & "00" & unsigned(opcode(5 downto 0));
dma_req.data <= ram_rdata;
state <= wait_dma;
else
case opcode is
when c_copcode_wait_for => -- takes a 1 byte argument
match <= timer + unsigned(ram_rdata);
state <= wait_until;
when c_copcode_wait_until => -- takes 2 bytes argument (wait until timer match)
match(7 downto 0) <= unsigned(ram_rdata);
state <= fetch3;
when others =>
state <= fetch; -- illegal opcode
end case;
end if;
when fetch3 =>
addr_i <= addr_i + 1;
state <= decode3;
when decode3 =>
-- the only opcode at this point requiring two bytes of opcode is the wait until..
match(15 downto 8) <= unsigned(ram_rdata);
state <= wait_until;
when wait_until =>
if timer = match then
state <= fetch;
end if;
when wait_dma =>
if dma_resp.rack='1' then
dma_req.request <= '0';
state <= fetch;
end if;
when record_start =>
if sync='1' then
state <= recording;
end if;
when recording =>
process_fifo_data;
if slot_req.bus_write='1' and slot_req.bus_address(15 downto 10)="110100" then
store_word(23 downto 16) <= std_logic_vector(slot_req.bus_address(7 downto 0));
store_word(31 downto 24) <= slot_req.data;
store_word(15 downto 0) <= std_logic_vector(timer);
store_trig <= '1';
end if;
if sync='1' then
store_word <= (others => '1');
store_trig <= '1';
state <= record_end;
end if;
when record_end =>
process_fifo_data;
if fifo_dav='0' and store_trig='0' then
state <= idle;
status.running <= '0';
end if;
when others =>
null;
end case;
if control.stop='1' then
state <= idle;
status.running <= '0';
dma_req.request <= '0';
end if;
if reset='1' then
state <= idle;
timer <= (others => '0');
match <= (others => '0');
status <= c_copper_status_init;
dma_req <= c_dma_req_init;
end if;
end if;
end process;
i_store_fifo: entity work.srl_fifo
generic map (
Width => 32,
Depth => 15,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => fifo_pop,
PutElement => store_trig,
FlushFifo => '0',
DataIn => store_word,
DataOut => fifo_dout,
SpaceInFifo => open,
AlmostFull => open,
DataInFifo => fifo_dav );
ram_we_i <= fifo_dav; -- whenever there is data, write!
fifo_pop <= '1' when addr_i(1 downto 0)="11" and ram_we_i='1' else '0'; -- pop data when we're writing the last byte of the word
with addr_i(1 downto 0) select
ram_wdata <=
fifo_dout(7 downto 0) when "00",
fifo_dout(15 downto 8) when "01",
fifo_dout(23 downto 16) when "10",
fifo_dout(31 downto 24) when others;
ram_address <= addr_i;
ram_we <= ram_we_i;
ram_en <= '1' when (state = fetch) or (state = fetch2) or (state = fetch3) or (ram_we_i='1') else '0';
end architecture;
| gpl-3.0 | 21eaf4a23e48b5dc5177abbfec5f60a5 | 0.427783 | 4.37188 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op980_4.vhdl | 1 | 6,383 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net7
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net7,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net8
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net9
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net10
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 46bfee1d7b98548f7695fd1cb4356233 | 0.573398 | 3.09704 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op992_21.vhdl | 1 | 7,074 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net9
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias2,
S => net10
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => vdd
);
subnet0_subnet4_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net11,
G => net4,
S => vdd
);
subnet0_subnet4_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net11
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net12
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net12,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | baa72e65bbe115fe99d1452aa147642d | 0.570823 | 3.054404 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb2/vhdl_source/mem_remain_counter.vhd | 3 | 1,395 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_remain_counter is
port (
clock : in std_logic;
load_value : in unsigned(10 downto 0);
do_load : in std_logic;
do_dec : in std_logic;
dec_by_4 : in std_logic;
remain : out unsigned(10 downto 0);
remain_is_0 : out std_logic;
remain_less4: out std_logic );
end mem_remain_counter;
architecture test of mem_remain_counter is
signal rem_i : unsigned(remain'range) := (others => '0');
signal small : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
if do_load='1' then
rem_i <= load_value;
-- elsif do_dec='1' then
-- rem_i <= rem_i - 1;
-- elsif dec_by_4='1' then
-- rem_i <= rem_i - 4;
-- end if;
elsif do_dec='1' then
if dec_by_4='1' then
rem_i <= rem_i - 4;
else
rem_i <= rem_i - 1;
end if;
end if;
end if;
end process;
remain <= rem_i;
small <= '1' when (rem_i(rem_i'high downto 2) = 0) else '0';
remain_is_0 <= small when (rem_i(1 downto 0) = 0) else '0';
remain_less4 <= small;
end architecture;
| gpl-3.0 | c0a06f7983473589673bb7e6c8ad963c | 0.472401 | 3.329356 | false | false | false | false |
Sourangsu/RAM-Arbiter-VHDL-Code | RAM_NEW.vhd | 1 | 2,849 | -------------------------------------------------------------------------
-- Entity for RAM
-------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RAM is
generic
(
-------------------------------------------------------------------------
-- Generics for scalability
-------------------------------------------------------------------------
G_ADDR_WIDTH: integer := 4;
G_DATA_WIDTH: integer := 8
-- G_ADDR_WIDTH = Number of bits required to address the ram
-- G_DATA_WIDTH = Number of bits in a data
-------------------------------------------------------------------------
);
port
(
-------------------------------------------------------------------------
-- RAM Inputs
-------------------------------------------------------------------------
CLOCK: in std_logic;
RST_N: in std_logic;
RD_EN: in std_logic; --read enb--
WR_EN: in std_logic; --write enb--
RD_ADDR: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--read addr---
WR_ADDR: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--write addr--
WR_DATA: in std_logic_vector(G_DATA_WIDTH-1 downto 0);--data input----
RD_DATA: out std_logic_vector(G_DATA_WIDTH-1 downto 0) --data output--
);
end RAM;
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-- Architecture for RAM
-------------------------------------------------------------------------
architecture RTL of RAM is
constant RAM_DEPTH: integer := 2**G_ADDR_WIDTH;
type MEMORY_ARRAY is array(0 to RAM_DEPTH-1) of std_logic_vector(G_DATA_WIDTH-1 downto 0);--ram type--
signal MEMORY: MEMORY_ARRAY;
signal count: integer:=0;
signal reset_done: std_logic;
begin
memorypr:process(CLOCK)
begin
if (RST_N='0')then
reset_done<='1';
elsif(CLOCK'EVENT and CLOCK='1')then
if(count <(2**G_ADDR_WIDTH) and reset_done='1' )then
MEMORY(conv_integer(count))<=(others =>'0');
count<=count+1;
else
count<=0;
reset_done<='0';
end if;
if(reset_done='0')then
-------------------------------------------------------------------
-----WRITING PROCESS IN RAM
-------------------------------------------------------------------
if(WR_EN='1')then
MEMORY(conv_integer(WR_ADDR))<= WR_DATA;
end if;
-------------------------------------------------------------------
-----READING PROCESS IN RAM
-------------------------------------------------------------------
if(RD_EN='1')then
RD_DATA<=MEMORY(conv_integer(RD_ADDR));
end if;
end if;
end if;
end process;
end RTL;
-------------------------------------------------------------------------
| bsd-3-clause | 30912422ee526d6f62d999371fd41f33 | 0.384345 | 4.573034 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_sim/tb_cpu_part_1541.vhd | 5 | 3,636 | library ieee;
use ieee.std_logic_1164.all;
library work;
use work.iec_bus_bfm_pkg.all;
entity tb_cpu_part_1541 is
end tb_cpu_part_1541;
architecture tb of tb_cpu_part_1541 is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal atn_o : std_logic; -- open drain
signal atn_i : std_logic := '1';
signal clk_o : std_logic; -- open drain
signal clk_i : std_logic := '1';
signal data_o : std_logic; -- open drain
signal data_i : std_logic := '1';
signal motor_on : std_logic;
signal mode : std_logic;
signal write_prot_n : std_logic := '1';
signal step : std_logic_vector(1 downto 0);
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic := '1';
signal sync : std_logic := '1';
signal drv_rdata : std_logic_vector(7 downto 0) := X"FF";
signal drv_wdata : std_logic_vector(7 downto 0);
signal act_led : std_logic;
signal iec_clock : std_logic;
signal iec_data : std_logic;
signal iec_atn : std_logic;
begin
clock <= not clock after 125 ns;
reset <= '1', '0' after 2 us;
ce: process
begin
clock_en <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
clock_en <= '1';
wait until clock='1';
end process;
mut: entity work.cpu_part_1541
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- drive pins
power => '1',
drive_select => "00",
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
drv_rdata => drv_rdata,
drv_wdata => drv_wdata,
-- other
act_led => act_led );
-- open collector logic
clk_i <= iec_clock and '1';
data_i <= iec_data and '1';
atn_i <= iec_atn and '1';
iec_clock <= '0' when clk_o='0' else 'H';
iec_data <= '0' when data_o='0' else 'H';
iec_atn <= '0' when atn_o='0' else 'H';
iec_bfm: entity work.iec_bus_bfm
port map (
iec_clock => iec_clock,
iec_data => iec_data,
iec_atn => iec_atn );
test: process
variable bfm : p_iec_bus_bfm_object;
variable msg : t_iec_message;
begin
bind_iec_bus_bfm(":tb_cpu_part_1541:iec_bfm:", bfm);
-- wait for 1250 ms; -- unpatched ROM
wait for 30 ms; -- patched ROM
iec_send_atn(bfm, X"48"); -- Drive 8, Talk, I will listen
iec_send_atn(bfm, X"6F"); -- Open channel 15
iec_turnaround(bfm); -- start to listen
iec_get_message(bfm, msg);
iec_print_message(msg);
wait;
end process;
end tb;
| gpl-3.0 | 33f2cf95f723ce54d91436b5fcdc6b42 | 0.456821 | 3.571709 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/iec_interface/vhdl_source/iec_processor.vhd | 4 | 9,993 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity iec_processor is
generic (
g_mhz : natural := 50);
port (
clock : in std_logic;
reset : in std_logic;
-- instruction ram interface
instr_addr : out unsigned(8 downto 0);
instr_en : out std_logic;
instr_data : in std_logic_vector(29 downto 0);
-- software fifo interface
up_fifo_full : in std_logic;
up_fifo_put : out std_logic;
up_fifo_din : out std_logic_vector(8 downto 0);
down_fifo_empty : in std_logic;
down_fifo_get : out std_logic;
down_fifo_flush : out std_logic;
down_fifo_dout : in std_logic_vector(8 downto 0);
irq_event : out std_logic;
clk_o : out std_logic;
clk_i : in std_logic;
data_o : out std_logic;
data_i : in std_logic;
atn_o : out std_logic;
atn_i : in std_logic;
srq_o : out std_logic;
srq_i : in std_logic );
attribute opt_mode : string;
attribute opt_mode of iec_processor: entity is "area";
end iec_processor;
architecture mixed of iec_processor is
constant c_opc_load : std_logic_vector(3 downto 0) := X"0";
constant c_opc_pop : std_logic_vector(3 downto 0) := X"1";
constant c_opc_pushc : std_logic_vector(3 downto 0) := X"2";
constant c_opc_pushd : std_logic_vector(3 downto 0) := X"3";
constant c_opc_sub : std_logic_vector(3 downto 0) := X"4";
constant c_opc_copy_bit : std_logic_vector(3 downto 0) := X"5";
constant c_opc_irq : std_logic_vector(3 downto 0) := X"6";
constant c_opc_ret : std_logic_vector(3 downto 0) := X"7";
constant c_opc_if : std_logic_vector(3 downto 0) := X"8";
constant c_opc_clrstack : std_logic_vector(3 downto 0) := X"9";
constant c_opc_reset_st : std_logic_vector(3 downto 0) := X"D";
constant c_opc_reset_drv: std_logic_vector(3 downto 0) := X"E";
constant c_opc_wait : std_logic_vector(3 downto 0) := X"C";
signal inputs : std_logic_vector(3 downto 0);
signal inputs_raw : std_logic_vector(3 downto 0);
signal timer : unsigned(11 downto 0);
signal pc : unsigned(instr_addr'range);
signal pc_ret_std : std_logic_vector(instr_addr'range);
signal pop, push : std_logic;
signal presc : integer range 0 to g_mhz;
signal timer_done : std_logic;
signal atn_i_d : std_logic;
signal valid_reg : std_logic := '0';
signal ctrl_reg : std_logic := '0';
signal timeout_reg : std_logic := '0';
signal flush_stack : std_logic;
type t_state is (idle, get_inst, decode, wait_true);
signal state : t_state;
signal instruction : std_logic_vector(29 downto 0);
alias a_invert : std_logic is instruction(29);
alias a_select : std_logic_vector( 4 downto 0) is instruction(28 downto 24);
alias a_opcode : std_logic_vector( 3 downto 0) is instruction(23 downto 20);
alias a_operand : std_logic_vector(11 downto 0) is instruction(19 downto 8);
alias a_mask : std_logic_vector( 3 downto 0) is instruction(7 downto 4);
alias a_value : std_logic_vector( 3 downto 0) is instruction(3 downto 0);
alias a_databyte : std_logic_vector( 7 downto 0) is instruction(7 downto 0);
signal input_vector : std_logic_vector(31 downto 0);
signal selected_bit : std_logic;
signal out_vector : std_logic_vector(19 downto 0);
alias a_drivers : std_logic_vector(3 downto 0) is out_vector(19 downto 16);
alias a_irq_enable : std_logic is out_vector(8);
alias a_status : std_logic_vector(7 downto 0) is out_vector(15 downto 8);
alias a_data_reg : std_logic_vector(7 downto 0) is out_vector(7 downto 0);
begin
clk_o <= a_drivers(0);
data_o <= a_drivers(1);
atn_o <= a_drivers(2);
srq_o <= a_drivers(3);
inputs_raw <= srq_i & atn_i & data_i & clk_i;
inputs <= std_logic_vector(to_01(unsigned(inputs_raw)));
input_vector(31 downto 30) <= "10";
input_vector(29) <= ctrl_reg;
input_vector(28) <= valid_reg;
input_vector(27) <= timeout_reg;
input_vector(26) <= up_fifo_full;
input_vector(25) <= '1' when (inputs and a_mask) = a_value else '0';
input_vector(24) <= '1' when (a_data_reg = a_databyte) else '0';
input_vector(23 downto 20) <= inputs;
input_vector(19 downto 16) <= a_drivers;
input_vector(15 downto 8) <= a_status;
input_vector(7 downto 0) <= a_data_reg;
selected_bit <= input_vector(to_integer(unsigned(a_select))) xor a_invert;
instr_addr <= pc;
instr_en <= '1' when (state = get_inst) else '0';
instruction <= instr_data;
process(clock)
variable v_bit : std_logic;
begin
if rising_edge(clock) then
up_fifo_put <= '0';
down_fifo_get <= '0';
down_fifo_flush <= '0';
irq_event <= '0';
flush_stack <= '0';
if presc = 0 then
if timer = 1 then
timer_done <= '1';
end if;
if timer /= 0 then
timer <= timer - 1;
end if;
presc <= g_mhz-1;
else
presc <= presc - 1;
end if;
case state is
when idle =>
null;
when get_inst =>
pc <= pc + 1;
state <= decode;
when decode =>
timer_done <= '0';
timer <= unsigned(a_operand);
-- presc <= 0;
state <= get_inst;
case a_opcode is
when c_opc_load =>
a_data_reg <= a_databyte;
when c_opc_reset_st =>
a_status <= X"01";
when c_opc_reset_drv =>
a_drivers <= "1111";
when c_opc_irq =>
irq_event <= '1';
when c_opc_pushc =>
if up_fifo_full='0' then
up_fifo_din <= '1' & a_data_reg;
up_fifo_put <= '1';
else
state <= decode;
end if;
when c_opc_pushd =>
if up_fifo_full='0' then
up_fifo_din <= '0' & a_data_reg;
up_fifo_put <= '1';
else
state <= decode;
end if;
when c_opc_pop =>
a_data_reg <= down_fifo_dout(7 downto 0);
ctrl_reg <= down_fifo_dout(8);
valid_reg <= not down_fifo_empty;
if down_fifo_empty='0' then
down_fifo_get <= '1';
elsif a_databyte(0)='0' then -- empty and non-block bit not set
state <= decode;
end if;
when c_opc_copy_bit =>
out_vector(to_integer(unsigned(a_databyte(4 downto 0)))) <= selected_bit;
when c_opc_if =>
if selected_bit='1' then
pc <= unsigned(a_operand(pc'range));
end if;
when c_opc_wait =>
timeout_reg <= '0';
state <= wait_true;
when c_opc_sub =>
-- pc_ret <= pc; (will be pushed)
pc <= unsigned(a_operand(pc'range));
when c_opc_ret =>
pc <= unsigned(pc_ret_std);
when c_opc_clrstack =>
flush_stack <= '1';
when others =>
null;
end case;
when wait_true =>
if timer_done='1' then
state <= get_inst;
timeout_reg <= '1';
elsif selected_bit='1' then
state <= get_inst;
end if;
when others =>
null;
end case;
atn_i_d <= atn_i;
if atn_i='0' and atn_i_d/='0' and a_irq_enable='1' then
down_fifo_flush <= '1';
pc <= to_unsigned(1, pc'length);
state <= get_inst;
end if;
if reset='1' then
state <= get_inst;
pc <= (others => '0');
out_vector <= X"F0000";
end if;
end if;
end process;
push <= '1' when (state = decode) and (a_opcode = c_opc_sub) else '0';
pop <= '1' when (state = decode) and (a_opcode = c_opc_ret) else '0';
i_stack: entity work.distributed_stack
generic map (
width => pc'length,
simultaneous_pushpop => false )
port map (
clock => clock,
reset => reset,
pop => pop,
push => push,
flush => flush_stack,
data_in => std_logic_vector(pc),
data_out => pc_ret_std,
full => open,
data_valid => open );
end mixed;
| gpl-3.0 | 74c0e9070f4071388f4e86eeafd8e9ba | 0.450015 | 3.858301 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/slot_slave.vhd | 4 | 13,915 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity slot_slave is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
ROMLn : in std_logic;
ROMHn : in std_logic;
BA : in std_logic;
GAMEn : in std_logic;
EXROMn : in std_logic;
RWn : in std_logic;
ADDRESS : in std_logic_vector(15 downto 0);
DATA_in : in std_logic_vector(7 downto 0);
DATA_out : out std_logic_vector(7 downto 0) := (others => '0');
DATA_tri : out std_logic;
-- interface with memory controller
mem_req : out std_logic; -- our memory request to serve slot
mem_size : out unsigned(1 downto 0);
mem_rwn : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_count : in unsigned(1 downto 0);
mem_rdata : in std_logic_vector(7 downto 0);
mem_wdata : out std_logic_vector(7 downto 0);
-- mem_addr comes from cartridge logic
reset_out : out std_logic;
-- timing inputs
phi2_tick : in std_logic;
do_sample_addr : in std_logic;
do_probe_end : in std_logic;
do_sample_io : in std_logic;
do_io_event : in std_logic;
-- interface with freezer (cartridge) logic
allow_serve : in std_logic := '0'; -- from timing unit (modified version of serve_enable)
serve_rom : in std_logic := '0'; -- ROML or ROMH
serve_io1 : in std_logic := '0'; -- IO1n
serve_io2 : in std_logic := '0'; -- IO2n
allow_write : in std_logic := '0';
kernal_enable : in std_logic := '0';
kernal_probe : out std_logic := '0';
kernal_area : out std_logic := '0';
force_ultimax : out std_logic := '0';
do_reg_output : in std_logic := '0';
epyx_timeout : out std_logic; -- '0' => epyx is on, '1' epyx is off
cpu_write : out std_logic; -- for freezer
slot_req : out t_slot_req;
slot_resp : in t_slot_resp;
-- interface with hardware
BUFFER_ENn : out std_logic );
end slot_slave;
architecture gideon of slot_slave is
signal address_c : std_logic_vector(15 downto 0) := (others => '0');
signal data_c : std_logic_vector(7 downto 0) := X"FF";
signal io1n_c : std_logic := '1';
signal io2n_c : std_logic := '1';
signal rwn_c : std_logic := '1';
signal romhn_c : std_logic := '1';
signal romln_c : std_logic := '1';
signal ba_c : std_logic := '0';
signal dav : std_logic := '0';
signal addr_is_io : boolean;
signal addr_is_kernal : std_logic;
signal mem_req_ff : std_logic;
signal mem_size_i : unsigned(1 downto 0);
signal servicable : std_logic;
signal io_out : boolean := false;
signal io_read_cond : std_logic;
signal io_write_cond: std_logic;
signal late_write_cond : std_logic;
signal ultimax : std_logic;
signal ultimax_d : std_logic := '0';
signal ultimax_d2 : std_logic := '0';
signal last_rwn : std_logic;
signal mem_wdata_i : std_logic_vector(7 downto 0);
signal kernal_probe_i : std_logic;
signal kernal_area_i : std_logic;
signal mem_data_0 : std_logic_vector(7 downto 0) := X"00";
signal mem_data_1 : std_logic_vector(7 downto 0) := X"00";
signal data_mux : std_logic;
attribute register_duplication : string;
attribute register_duplication of rwn_c : signal is "no";
attribute register_duplication of io1n_c : signal is "no";
attribute register_duplication of io2n_c : signal is "no";
attribute register_duplication of romln_c : signal is "no";
attribute register_duplication of romhn_c : signal is "no";
attribute register_duplication of reset_out : signal is "no";
type t_state is (idle, mem_access, wait_end, reg_out);
attribute iob : string;
attribute iob of data_c : signal is "true";
signal state : t_state;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
signal epyx_timer : unsigned(6 downto 0) := (others => '0');
signal epyx_reset : std_logic := '0';
begin
slot_req.io_write <= do_io_event and io_write_cond;
slot_req.io_read <= do_io_event and io_read_cond;
slot_req.late_write <= do_io_event and late_write_cond;
slot_req.io_read_early <= '1' when (addr_is_io and rwn_c='1' and do_sample_addr='1') else '0';
process(clock)
begin
if rising_edge(clock) then
-- synchronization
if mem_req_ff='0' then -- don't change while an access is taking place
rwn_c <= RWn;
address_c <= ADDRESS;
end if;
reset_out <= reset or not RSTn;
ba_c <= BA;
io1n_c <= IO1n;
io2n_c <= IO2n;
romln_c <= ROMLn;
romhn_c <= ROMHn;
data_c <= DATA_in;
ultimax <= not GAMEn and EXROMn;
ultimax_d <= ultimax;
ultimax_d2 <= ultimax_d;
if epyx_reset='1' then
epyx_timer <= (others => '1');
epyx_timeout <= '0';
elsif phi2_tick='1' then
if epyx_timer = "0000000" then
epyx_timeout <= '1';
else
epyx_timer <= epyx_timer - 1;
end if;
end if;
slot_req.bus_write <= '0';
if do_sample_io='1' then
cpu_write <= not RWn;
slot_req.bus_write <= not RWn;
slot_req.io_address <= unsigned(address_c);
mem_wdata_i <= data_c;
late_write_cond <= not rwn_c;
io_write_cond <= not rwn_c and (not io2n_c or not io1n_c);
io_read_cond <= rwn_c and (not io2n_c or not io1n_c);
epyx_reset <= not io2n_c or not io1n_c or not romln_c or not RSTn;
end if;
if do_probe_end='1' then
data_mux <= kernal_probe_i and not romhn_c;
force_ultimax <= kernal_probe_i;
kernal_probe_i <= '0';
elsif do_io_event='1' then
force_ultimax <= '0';
end if;
case state is
when idle =>
mem_size_i <= "00";
if do_sample_addr='1' then
-- register output
if slot_resp.reg_output='1' and addr_is_io and rwn_c='1' then -- read register
mem_data_0 <= slot_resp.data;
io_out <= true;
dav <= '1';
state <= reg_out;
elsif allow_serve='1' and servicable='1' and rwn_c='1' then
io_out <= false;
-- memory read
if kernal_enable='1' and ultimax='0' and addr_is_kernal='1' and ba_c='1' then
kernal_probe_i <= '1';
kernal_area_i <= '1';
mem_size_i <= "01";
end if;
if addr_is_io then
if ba_c='1' then -- only serve IO when BA='1' (Fix for Ethernet)
mem_req_ff <= '1';
state <= mem_access;
end if;
if address_c(8)='0' and serve_io1='1' then
io_out <= (rwn_c='1');
elsif address_c(8)='1' and serve_io2='1' then
io_out <= (rwn_c='1');
end if;
else -- non-IO, always serve
mem_req_ff <= '1';
state <= mem_access;
end if;
end if;
elsif do_sample_io='1' and rwn_c='0' then
if allow_write='1' then
-- memory write
if address_c(14)='1' then -- IO range
if io2n_c='0' or io1n_c='0' then
mem_req_ff <= '1';
state <= mem_access;
end if;
else
mem_req_ff <= '1';
state <= mem_access;
end if;
elsif kernal_enable='1' and addr_is_kernal='1' then
-- do mirror to kernal write address
mem_req_ff <= '1';
state <= mem_access;
kernal_area_i <= '1';
end if;
end if;
when mem_access =>
if mem_rack='1' then
mem_req_ff <= '0'; -- clear request
if rwn_c='0' then -- if write, we're done.
kernal_area_i <= '0';
state <= idle;
else -- if read, then we need to wait for the data
state <= wait_end;
end if;
end if;
-- this will never happen, because we have latency from RAM.
-- if mem_dack='1' then -- in case the data comes immediately
-- DATA_out <= mem_rdata;
-- dav <= '1';
-- end if;
when wait_end =>
if mem_dack='1' then -- the data is available, put it on the bus!
if mem_count="00" then
mem_data_0 <= mem_rdata;
else
mem_data_1 <= mem_rdata;
end if;
dav <= '1';
end if;
if phi2_tick='1' or do_io_event='1' then -- around the clock edges
kernal_area_i <= '0';
state <= idle;
io_out <= false;
dav <= '0';
end if;
when reg_out =>
mem_data_0 <= slot_resp.data;
if phi2_tick='1' or do_io_event='1' then -- around the clock edges
state <= idle;
io_out <= false;
dav <= '0';
end if;
when others =>
null;
end case;
if (kernal_area_i='1') then
DATA_tri <= not romhn_c and ultimax_d2 and rwn_c;
elsif (io_out and (io1n_c='0' or io2n_c='0')) or
((romln_c='0' or romhn_c='0') and (rwn_c='1')) then
DATA_tri <= mem_dack or dav;
else
DATA_tri <= '0';
end if;
if reset='1' then
data_mux <= '0';
last_rwn <= '1';
dav <= '0';
state <= idle;
mem_req_ff <= '0';
mem_size_i <= "00";
io_out <= false;
io_read_cond <= '0';
io_write_cond <= '0';
late_write_cond <= '0';
slot_req.io_address <= (others => '0');
cpu_write <= '0';
epyx_reset <= '1';
kernal_probe_i <= '0';
kernal_area_i <= '0';
force_ultimax <= '0';
end if;
end if;
end process;
-- combinatoric
addr_is_io <= (address_c(15 downto 9)="1101111"); -- DE/DF
addr_is_kernal <= '1' when (address_c(15 downto 13)="111") else '0';
process(rwn_c, address_c, addr_is_io, romln_c, romhn_c, serve_rom, serve_io1, serve_io2, ultimax, kernal_enable, ba_c)
begin
servicable <= '0';
if rwn_c='1' then
if addr_is_io and (serve_io1='1' or serve_io2='1') then
servicable <= '1';
end if;
-- if (romln_c='0' or romhn_c='0') and (serve_rom='1') then -- our decode is faster!
if address_c(15 downto 14)="10" and (serve_rom='1') then -- 8000-BFFF
servicable <= '1';
end if;
if address_c(15 downto 13)="111" and (serve_rom='1') and (ultimax='1') then
servicable <= '1';
end if;
if address_c(15 downto 13)="111" and (kernal_enable='1') and (ba_c='1') then
servicable <= '1';
end if;
end if;
end process;
mem_req <= mem_req_ff;
mem_rwn <= rwn_c;
mem_wdata <= mem_wdata_i;
mem_size <= mem_size_i;
BUFFER_ENn <= '0';
DATA_out <= mem_data_0 when data_mux='0' else mem_data_1;
slot_req.data <= mem_wdata_i;
slot_req.bus_address <= unsigned(address_c(15 downto 0));
kernal_probe <= kernal_probe_i;
kernal_area <= kernal_area_i;
end gideon;
| gpl-3.0 | d7224e092ae8372e22618f48178fc640 | 0.431477 | 3.734568 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/iec_interface/vhdl_source/iec_processor_io.vhd | 3 | 12,997 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 260/111/136/1
library work;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity iec_processor_io is
generic (
g_mhz : natural := 50);
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
clk_o : out std_logic;
clk_i : in std_logic;
data_o : out std_logic;
data_i : in std_logic;
atn_o : out std_logic;
atn_i : in std_logic;
srq_o : out std_logic;
srq_i : in std_logic );
end iec_processor_io;
architecture structural of iec_processor_io is
signal proc_reset : std_logic;
signal enable : std_logic;
-- irq
signal irq_event : std_logic;
signal irq_enable : std_logic;
signal irq_status : std_logic;
-- instruction ram interface
signal instr_addr : unsigned(8 downto 0);
signal instr_en : std_logic;
signal instr_data : std_logic_vector(31 downto 0);
-- software fifo interface
signal up_fifo_get : std_logic;
signal up_fifo_put : std_logic;
signal up_fifo_din : std_logic_vector(8 downto 0);
signal up_fifo_dout : std_logic_vector(8 downto 0);
signal up_fifo_empty : std_logic;
signal up_fifo_full : std_logic;
signal up_dav : std_logic;
signal up_space : std_logic;
signal down_fifo_flush : std_logic;
signal down_fifo_empty : std_logic;
signal down_fifo_full : std_logic;
signal down_fifo_get : std_logic;
signal down_fifo_put : std_logic;
signal down_fifo_din : std_logic_vector(8 downto 0);
signal down_fifo_dout : std_logic_vector(8 downto 0);
signal down_dav : std_logic;
signal down_space : std_logic;
signal ram_en : std_logic;
signal ram_rdata : std_logic_vector(7 downto 0);
signal ram_sel : std_logic;
signal reg_rdata : std_logic_vector(7 downto 0);
begin
i_proc: entity work.iec_processor
generic map (
g_mhz => g_mhz )
port map (
clock => clock,
reset => proc_reset,
-- instruction ram interface
instr_addr => instr_addr,
instr_en => instr_en,
instr_data => instr_data(29 downto 0),
-- software fifo interface
up_fifo_put => up_fifo_put,
up_fifo_din => up_fifo_din,
up_fifo_full => up_fifo_full,
down_fifo_empty => down_fifo_empty,
down_fifo_get => down_fifo_get,
down_fifo_dout => down_fifo_dout,
down_fifo_flush => down_fifo_flush,
irq_event => irq_event,
clk_o => clk_o,
clk_i => clk_i,
data_o => data_o,
data_i => data_i,
atn_o => atn_o,
atn_i => atn_i,
srq_o => srq_o,
srq_i => srq_i );
-- i_inst_ram: entity work.dpram
-- generic map (
-- g_width_bits => 32,
-- g_depth_bits => 11,
-- g_read_first_a => false,
-- g_read_first_b => false,
-- g_storage => "block" )
-- port map (
-- a_clock => clock,
-- a_address => instr_addr,
-- a_rdata => instr_data,
-- a_wdata => X"00",
-- a_en => instr_en,
-- a_we => '0',
--
-- b_clock => clock,
-- b_address => req.address(10 downto 0),
-- b_rdata => ram_rdata,
-- b_wdata => req.data,
-- b_en => ram_en,
-- b_we => req.write );
i_ram: RAMB16_S9_S36
generic map (
INIT_00 => X"00406F0019C00011002000000000004119C000101E5000111F5000101F80B200",
INIT_01 => X"098012000A8012000040A10000409C002A800D001F800D0000409C0029800B00",
INIT_02 => X"2A80690009801E0000200000000000423680060039C000501F50001119C04601",
INIT_03 => X"1B80AF0019C0C8111F80690019C046012C80180000409C0000406F0019C00011",
INIT_04 => X"004029001E50000C00200000000000431E50000C19C050011F5000111E500010",
INIT_05 => X"2C80290000403100001000001F50000C188030103D802E00001000001F806900",
INIT_06 => X"1E5000101B80AF0019C3E82019C064012C80390019C000221F50001000700000",
INIT_07 => X"1E50001019C050011F50001019C05001005000111E50001019C0280119C00022",
INIT_08 => X"1F50001019C05001025000111E50001019C050011F50001019C0500101500011",
INIT_09 => X"045000111E50001019C050011F50001019C05001035000111E50001019C05001",
INIT_0A => X"19C050011F50001019C05001055000111E50001019C050011F50001019C05001",
INIT_0B => X"19C05001075000111E50001019C050011F50001019C05001065000111E500010",
INIT_0C => X"19C05A011B80AF0019C3E82019C002011E5000101F50001119C050011F500010",
INIT_0D => X"1A806F001F80B2001F5000111F5000101F50001200200000000000DD00700000",
INIT_0E => X"19C3E8101F50001119C046011E5000112C8079001B50000C19C0C8101F500011",
INIT_0F => X"1B80AF001550000119C0C81119C0C8101B80AF001550000019C0C8111B80AF00",
INIT_10 => X"1B80AF001550000319C0C81119C0C8101B80AF001550000219C0C81119C0C810",
INIT_11 => X"1B80AF001550000519C0C81119C0C8101B80AF001550000419C0C81119C0C810",
INIT_12 => X"1B80AF001550000719C0C81119C0C8101B80AF001550000619C0C81119C0C810",
INIT_13 => X"00200000000000452C80A00000300000007000001E50001119C0140119C0C810",
INIT_14 => X"007000001E50000A1F5000093880A84A007000001E5000093880A45F00700000",
INIT_15 => X"000000EE007000001E5000091F50000A3880AE2A007000001E50000A3880AB3F",
INIT_16 => X"1880B94D1880D7573D80B200001000001F500008009000001F80690000200000",
INIT_17 => X"1B80D40019C3E82019C014011F5000111E5000101E5000121E5000081F80B200",
INIT_18 => X"1880694B1880CB4C1880B94D1F80C000004031001E50000C1D80C50000100000",
INIT_19 => X"1F5000121F80C00019C06401004029001F50001200200000000000E51880CF4A",
INIT_1A => X"002000001F80690000200000000000E61F80180019C005011F50001019C01E01",
INIT_1B => X"00300000000000550010000000200000000000DA3480EE0039C000331E500008",
INIT_1C => X"0040F900004120000040F900004120000040F9001F50001019C000221E500010",
INIT_1D => X"00200000000000DE1F80D7000060000019C0003300200000000000AD00412500",
INIT_1E => X"2780B2000060000019C00033004102000040F9001F50001119C000111E500011",
INIT_1F => X"0060000000200000000000AE0070000019C0040119C3E83019C000331F80D700",
INIT_20 => X"1F50001319C0080135500001345000031E50001319C015011F80B20019C00033",
INIT_21 => X"355000043450000619C00801355000053450000719C008013550000034500002",
INIT_22 => X"0041120000700000004102000041020000410200004102000070000000300000",
INIT_23 => X"0070000000411200004112000041120000411200004112000041120000411200",
INIT_24 => X"0041120000411700004117000070000000411700004117000041170000411700",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000700000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST" )
port map (
DOA => ram_rdata,
ADDRA => std_logic_vector(req.address(10 downto 0)),
CLKA => clock,
DIA => req.data,
DIPA => "0",
ENA => ram_en,
SSRA => '0',
WEA => req.write,
DOB => instr_data,
ADDRB => std_logic_vector(instr_addr),
CLKB => clock,
DIB => X"00000000",
DIPB => X"0",
ENB => instr_en,
SSRB => '0',
WEB => '0' );
-- i_up_fifo: entity work.srl_fifo
-- generic map (
-- Width => 9,
-- Depth => 15, -- 15 is the maximum
-- Threshold => 13 )
-- port map (
-- clock => clock,
-- reset => reset,
-- GetElement => up_fifo_get,
-- PutElement => up_fifo_put,
-- FlushFifo => '0',
-- DataIn => up_fifo_din,
-- DataOut => up_fifo_dout,
-- SpaceInFifo => up_space,
-- AlmostFull => open,
-- DataInFifo => up_dav);
--
-- up_fifo_empty <= not up_dav;
-- up_fifo_full <= not up_space;
i_up_fifo: entity work.sync_fifo
generic map (
g_depth => 2048,
g_data_width => 9,
g_threshold => 500,
g_storage => "blockram", -- can also be "blockram" or "distributed"
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => up_fifo_get,
wr_en => up_fifo_put,
din => up_fifo_din,
dout => up_fifo_dout,
flush => '0',
full => up_fifo_full,
almost_full => open,
empty => up_fifo_empty,
count => open );
i_down_fifo: entity work.srl_fifo
generic map (
Width => 9,
Depth => 15, -- 15 is the maximum
Threshold => 13 )
port map (
clock => clock,
reset => reset,
GetElement => down_fifo_get,
PutElement => down_fifo_put,
FlushFifo => down_fifo_flush,
DataIn => down_fifo_din,
DataOut => down_fifo_dout,
SpaceInFifo => down_space,
AlmostFull => open,
DataInFifo => down_dav);
down_fifo_empty <= not down_dav;
down_fifo_full <= not down_space;
process(clock)
begin
if rising_edge(clock) then
ram_sel <= '0';
reg_rdata <= (others => '0');
proc_reset <= not enable;
resp.ack <= '0';
if req.read='1' then
resp.ack <= '1'; -- data handled outside clocked process if ram
ram_sel <= req.address(11);
case req.address(3 downto 0) is
when X"0" =>
reg_rdata <= X"23"; -- version
when X"1" =>
reg_rdata(0) <= down_fifo_empty;
reg_rdata(1) <= down_fifo_full;
when X"2" =>
reg_rdata(0) <= up_fifo_empty;
reg_rdata(1) <= up_fifo_full;
reg_rdata(7) <= up_fifo_dout(8);
when X"6"|X"8"|X"9"|X"A"|X"B" =>
reg_rdata <= up_fifo_dout(7 downto 0);
when X"7" =>
reg_rdata <= "0000000" & up_fifo_dout(8);
when X"C" =>
reg_rdata <= "0000000" & irq_status;
when others => null;
end case;
elsif req.write='1' then
resp.ack <= '1'; -- data handled outside clocked process if ram
if req.address(11)='0' then
case req.address(3 downto 0) is
when X"3" =>
proc_reset <= '1';
enable <= req.data(0);
when X"C" =>
irq_status <= '0';
irq_enable <= req.data(0);
when others =>
null;
end case;
end if;
end if;
if irq_event='1' then
irq_status <= '1';
end if;
resp.irq <= irq_enable and irq_status;
if reset='1' then
proc_reset <= '1';
enable <= '0';
end if;
end if;
end process;
resp.data <= ram_rdata when ram_sel='1' else reg_rdata;
down_fifo_put <= '1' when req.write='1' and req.address(11)='0' and req.address(3 downto 1) = "10" else '0';
up_fifo_get <= '1' when req.read='1' and req.address(11)='0' and ((req.address(3 downto 0) = "0110") or (req.address(3 downto 2) = "10")) else '0';
down_fifo_din <= req.address(0) & req.data;
ram_en <= (req.write or req.read) and req.address(11);
end structural;
| gpl-3.0 | 7609889d0c6f870d98363c0625674301 | 0.51835 | 3.463096 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/gcr_decoder.vhd | 5 | 2,043 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity gcr_decoder is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp );
end gcr_decoder;
architecture regmap of gcr_decoder is
signal shift_reg : std_logic_vector(0 to 39);
signal decoded : std_logic_vector(0 to 31);
signal errors : std_logic_vector(0 to 7);
begin
process(clock)
begin
if rising_edge(clock) then
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
shift_reg <= shift_reg(8 to 39) & req.data;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data <= decoded(0 to 7);
when X"1" =>
resp.data <= decoded(8 to 15);
when X"2" =>
resp.data <= decoded(16 to 23);
when X"3" =>
resp.data <= decoded(24 to 31);
when X"7" =>
resp.data <= decoded(0 to 7);
when X"6" =>
resp.data <= decoded(8 to 15);
when X"5" =>
resp.data <= decoded(16 to 23);
when X"4" =>
resp.data <= decoded(24 to 31);
when others =>
resp.data <= errors;
end case;
end if;
if reset='1' then
shift_reg <= X"5555555555";
end if;
end if;
end process;
r_decoders: for i in 0 to 7 generate
i_gcr2bin: entity work.gcr2bin
port map (
d_in => shift_reg(5*i to 4+5*i),
d_out => decoded(4*i to 3+4*i),
error => errors(i) );
end generate;
end;
| gpl-3.0 | 82320d703b54a644cb52e5904f7a560a | 0.428292 | 3.818692 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/nano_cpu/vhdl_sim/nano_tb.vhd | 5 | 807 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity nano_tb is
end entity;
architecture tb of nano_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_addr : unsigned(7 downto 0);
signal io_write : std_logic;
signal io_wdata : std_logic_vector(15 downto 0);
signal io_rdata : std_logic_vector(15 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_cpu: entity work.nano
port map (
clock => clock,
reset => reset,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_wdata => io_wdata,
io_rdata => io_rdata );
end architecture;
| gpl-3.0 | 4bbf5677003c455f8c7d9b6b313cc1d8 | 0.531599 | 3.493506 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op975_1.vhdl | 1 | 4,110 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net3,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_3,
scope => Wprivate
)
port map(
D => out1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net4,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | dbd0867c29f1c351ce524e7c9b045487 | 0.585888 | 3.256735 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_sim/tb_sid.vhd | 5 | 5,253 | -------------------------------------------------------------------------------
-- Date $Date: 2005/04/12 19:09:27 $
-- Author $Author: Gideon $
-- Revision $Revision: 1.1 $
-- Log $Log: oscillator.vhd,v $
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_sid is
end tb_sid;
architecture tb of tb_sid is
signal clock : std_logic := '0';
signal reset : std_logic;
signal addr : unsigned(6 downto 0) := (others => '0');
signal wren : std_logic := '0';
signal wdata : std_logic_vector(7 downto 0) := (others => '0');
signal rdata : std_logic_vector(7 downto 0) := (others => '0');
signal start_iter : std_logic := '0';
signal sid_pwm : std_logic := '0';
signal sample_out : signed(17 downto 0);
signal stop_clock : boolean := false;
signal vc : real := 0.0;
constant R : real := 2200.0;
constant C : real := 0.000000022;
begin
clock <= not clock after 10 ns when not stop_clock; -- 50 MHz
reset <= '1', '0' after 1 us;
sid: entity work.sid_top
generic map (
g_num_voices => 7 )
port map (
clock => clock,
reset => reset,
addr => addr,
wren => wren,
wdata => wdata,
rdata => rdata,
start_iter => start_iter,
sample_out => sample_out );
i_pdm_sid: entity work.sigma_delta_dac
generic map (
g_left_shift => 0,
g_width => sample_out'length )
port map (
clock => clock,
reset => reset,
dac_in => sample_out,
dac_out => sid_pwm );
filter: process(clock)
variable v_dac : real;
variable i_r : real;
variable q_c : real;
begin
if rising_edge(clock) then
if sid_pwm='0' then
v_dac := -1.2;
else
v_dac := 1.2;
end if;
i_r := (v_dac - vc) / R;
q_c := i_r * 20.0e-9; -- 20 ns;
vc <= vc + (q_c / C);
end if;
end process;
test: process
procedure do_write(a : natural; d : std_logic_vector(7 downto 0)) is
begin
wait until clock='1';
addr <= to_unsigned(a, 7);
wdata <= d;
wren <= '1';
wait until clock='1';
wren <= '0';
end procedure;
begin
wait until reset='0';
wait until clock='1';
do_write(24, X"0F"); -- volume = 15
-- voice 1
do_write(0, X"8A"); -- freq = 1000 Hz
do_write(1, X"41");
do_write(2, X"55"); -- pulse_width = 1/3 (4095 / 3)
do_write(3, X"05");
do_write(5, X"01"); -- attack = 0, release = 1
do_write(6, X"F1"); -- sustain = 8, decay = 1
do_write(4, X"11"); -- triangle, gate = 1, with sync
wait for 4 ms;
do_write(4, X"19"); -- triangle with test
wait for 50 us;
do_write(4, X"11"); -- reset test bit
wait for 50 us;
do_write(4, X"01"); -- waveform 0
wait for 100 us;
do_write(4, X"19"); -- triangle with test
wait for 1 us;
do_write(4, X"11"); -- reset test bit
wait for 20 us;
do_write(4, X"01"); -- waveform 0
-- voice 3
do_write(14+0, X"FC"); -- freq = 900 Hz
do_write(14+1, X"3A");
do_write(14+1, X"FF"); -- max for ring mod view in wave
do_write(14+2, X"55"); -- pulse_width = 1/3 (4095 / 3)
do_write(14+3, X"05");
do_write(14+5, X"11"); -- attack = 1, release = 1
do_write(14+6, X"81"); -- sustain = 8, decay = 1
-- do_write(22, X"20"); -- low frequency filter
-- do_write(23, X"41"); -- a bit of resonance for voice1
-- do_write(24, X"1F"); -- full volume, with LP
-- wait for 20 ms;
-- do_write(24, X"0C"); -- volume = 12
--
-- do_write( 7, X"22");
-- do_write( 8, X"39");
-- do_write(12, X"11");
-- do_write(13, X"F1");
-- do_write(11, X"11"); -- saw
--
-- wait for 20 ms;
--
-- -- voice 3 oscillator on
-- do_write(14, X"E1"); -- freq = 1234 Hz
-- do_write(15, X"50");
-- do_write(19, X"22"); -- attack = 2, release = 2
-- do_write(20, X"A2"); -- sustain = 10, decay = 2
-- do_write(18, X"11"); -- select triangle, to see it on the output register
wait for 50 ms;
do_write(4, X"20"); -- gate off
do_write(18, X"10"); -- gate off
wait for 70 ms;
stop_clock <= true;
wait;
end process test;
process
begin
wait for 980 ns;
start_iter <= '1';
wait for 20 ns;
start_iter <= '0';
if stop_clock then
wait;
end if;
end process;
end tb;
| gpl-3.0 | 914d4cbdcb0cebbf321bf5e832b85755 | 0.431944 | 3.384665 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_sim/tb_ulpi_bus.vhd | 3 | 3,037 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_bus is
end entity;
architecture tb of tb_ulpi_bus is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_mut: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_bfm: entity work.ulpi_phy_bfm
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
p_test: process
procedure tx_packet(invec : t_std_logic_8_vector; last : boolean) is
begin
wait until clock='1';
tx_start <= '1';
for i in invec'range loop
tx_data <= invec(i);
tx_valid <= '1';
if i = invec'right and last then
tx_last <= '1';
else
tx_last <= '0';
end if;
wait until clock='1';
tx_start <= '0';
while tx_next = '0' loop
wait until clock='1';
end loop;
end loop;
tx_valid <= '0';
end procedure;
begin
wait for 500 ns;
tx_packet((X"40", X"01", X"02", X"03", X"04"), true);
wait for 300 ns;
tx_packet((X"81", X"15"), true);
wait for 300 ns;
tx_packet((0 => X"C2"), false);
wait;
end process;
end tb;
| gpl-3.0 | 6076f2ce77b9448e7a1f0506c23ed035 | 0.459006 | 3.690158 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op330_9.vhdl | 1 | 4,730 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net3
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | c467c4e150927430f00eb88e5a80f62c | 0.580127 | 3.187332 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op337_9sk1_0.vhdl | 1 | 7,641 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.95e-06,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.95e-06,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => W_0,
W_0init => 9.05e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.95e-06,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.95e-06,
W => Wdiff_0,
Wdiff_0init => 3.5e-07,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.85e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.85e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.85e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 8.75e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 6.85e-06,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 7.3e-06,
W => Wsrc_2,
Wsrc_2init => 7.85e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 7.3e-06,
W => Wsrc_2,
Wsrc_2init => 7.85e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net3,
S => vdd
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 3.78e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias3,
S => net7
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.7e-06,
W => Wcm_1,
Wcm_1init => 1.54e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.7e-06,
W => Wcmout_1,
Wcmout_1init => 1.045e-05,
scope => private
)
port map(
D => net8,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 3.78e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => (pfak)*(WBias),
WBiasinit => 2.15e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.15e-06,
W => (pfak)*(WBias),
WBiasinit => 2.15e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.15e-06,
W => WBias,
WBiasinit => 2.15e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => WBias,
WBiasinit => 2.15e-05
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => WBias,
WBiasinit => 2.15e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.15e-06,
W => WBias,
WBiasinit => 2.15e-05
)
port map(
D => net9,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net10,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net10,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net10,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 9bb965e9e3950038099b11b4a1535ac7 | 0.582123 | 2.861798 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op962_5.vhdl | 1 | 4,520 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias4: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias3,
S => net3
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net4
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_3,
scope => Wprivate
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | b4437b5c697cb516f3213ad29d06f01d | 0.584071 | 3.214794 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ipcore_dir/ROM_GAUSS_COE/simulation/ROM_GAUSS_COE_tb.vhd | 1 | 4,249 | --------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ROM_GAUSS_COE_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ROM_GAUSS_COE_tb IS
END ENTITY;
ARCHITECTURE ROM_GAUSS_COE_tb_ARCH OF ROM_GAUSS_COE_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ROM_GAUSS_COE_tb_synth_inst:ENTITY work.ROM_GAUSS_COE_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-3.0 | d1482ad22e6bc582b7f6e612c69d955d | 0.624382 | 4.529851 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/old/mk7_pla.vhd | 5 | 6,665 |
library ieee;
use ieee.std_logic_1164.all;
entity mk7_pla is
port (
A : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(4 downto 1) );
end mk7_pla;
architecture table of mk7_pla is
begin
process(A)
begin
Q <= X"F";
if A(7)='0' then
Q <= "101" & not A(3);
else
case A(6 downto 0) is
when "0000000" => Q <= "0110";
when "0000001" => Q <= "0111";
when "0000010" => Q <= "1111";
when "0000011" => Q <= "1111";
when "0000100" => Q <= "0010";
when "0000101" => Q <= "0011";
when "0000110" => Q <= "1010";
when "0000111" => Q <= "1011";
when "0001000" => Q <= "0110";
when "0001001" => Q <= "0111";
when "0001010" => Q <= "1111";
when "0001011" => Q <= "1111";
when "0001100" => Q <= "0010";
when "0001101" => Q <= "0011";
when "0001110" => Q <= "1010";
when "0001111" => Q <= "1011";
when "0010000" => Q <= "0110";
when "0010001" => Q <= "0111";
when "0010010" => Q <= "1111";
when "0010011" => Q <= "1111";
when "0010100" => Q <= "0010";
when "0010101" => Q <= "0011";
when "0010110" => Q <= "1010";
when "0010111" => Q <= "1011";
when "0011000" => Q <= "0110";
when "0011001" => Q <= "0111";
when "0011010" => Q <= "1111";
when "0011011" => Q <= "1111";
when "0011100" => Q <= "0010";
when "0011101" => Q <= "0011";
when "0011110" => Q <= "1010";
when "0011111" => Q <= "1011";
when "0100000" => Q <= "0110";
when "0100001" => Q <= "0111";
when "0100010" => Q <= "1111";
when "0100011" => Q <= "1111";
when "0100100" => Q <= "0010";
when "0100101" => Q <= "0011";
when "0100110" => Q <= "1010";
when "0100111" => Q <= "1011";
when "0101000" => Q <= "0110";
when "0101001" => Q <= "0101";
when "0101010" => Q <= "1111";
when "0101011" => Q <= "1101";
when "0101100" => Q <= "0011";
when "0101101" => Q <= "0001";
when "0101110" => Q <= "1010";
when "0101111" => Q <= "1001";
when "0110000" => Q <= "0111";
when "0110001" => Q <= "0111";
when "0110010" => Q <= "1111";
when "0110011" => Q <= "1111";
when "0110100" => Q <= "0011";
when "0110101" => Q <= "0011";
when "0110110" => Q <= "1010";
when "0110111" => Q <= "1010";
when "0111000" => Q <= "0111";
when "0111001" => Q <= "0111";
when "0111010" => Q <= "1111";
when "0111011" => Q <= "1111";
when "0111100" => Q <= "0010";
when "0111101" => Q <= "0010";
when "0111110" => Q <= "1011";
when "0111111" => Q <= "1010";
when "1000000" => Q <= "0110";
when "1000001" => Q <= "0111";
when "1000010" => Q <= "1111";
when "1000011" => Q <= "1111";
when "1000100" => Q <= "0010";
when "1000101" => Q <= "0011";
when "1000110" => Q <= "1010";
when "1000111" => Q <= "1011";
when "1001000" => Q <= "0110";
when "1001001" => Q <= "0111";
when "1001010" => Q <= "1111";
when "1001011" => Q <= "1111";
when "1001100" => Q <= "0010";
when "1001101" => Q <= "0011";
when "1001110" => Q <= "1010";
when "1001111" => Q <= "1011";
when "1010000" => Q <= "0110";
when "1010001" => Q <= "0111";
when "1010010" => Q <= "1111";
when "1010011" => Q <= "1111";
when "1010100" => Q <= "0010";
when "1010101" => Q <= "0011";
when "1010110" => Q <= "1010";
when "1010111" => Q <= "1011";
when "1011000" => Q <= "0110";
when "1011001" => Q <= "0111";
when "1011010" => Q <= "1111";
when "1011011" => Q <= "1111";
when "1011100" => Q <= "0010";
when "1011101" => Q <= "0011";
when "1011110" => Q <= "1010";
when "1011111" => Q <= "1011";
when "1100000" => Q <= "0110";
when "1100001" => Q <= "0101";
when "1100010" => Q <= "1110";
when "1100011" => Q <= "1101";
when "1100100" => Q <= "0011";
when "1100101" => Q <= "0001";
when "1100110" => Q <= "1011";
when "1100111" => Q <= "1001";
when "1101000" => Q <= "0111";
when "1101001" => Q <= "0111";
when "1101010" => Q <= "1111";
when "1101011" => Q <= "1111";
when "1101100" => Q <= "0011";
when "1101101" => Q <= "0011";
when "1101110" => Q <= "1011";
when "1101111" => Q <= "1011";
when "1110000" => Q <= "0111";
when "1110001" => Q <= "0111";
when "1110010" => Q <= "1111";
when "1110011" => Q <= "1111";
when "1110100" => Q <= "0011";
when "1110101" => Q <= "0011";
when "1110110" => Q <= "1010";
when "1110111" => Q <= "1010";
when "1111000" => Q <= "0111";
when "1111001" => Q <= "0111";
when "1111010" => Q <= "1111";
when "1111011" => Q <= "1111";
when "1111100" => Q <= "0011";
when "1111101" => Q <= "0011";
when "1111110" => Q <= "1010";
when "1111111" => Q <= "1010";
when others => Q <= "1111";
end case;
end if;
end process;
end table;
| gpl-3.0 | 4941617dde0e95b0abef88e84b32d91e | 0.343436 | 4.258786 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_source/boot_400a.vhd | 4 | 9,830 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity boot_400a is
generic (
g_version : unsigned(7 downto 0) := X"AB" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end boot_400a;
architecture structural of boot_400a is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_fpga_type => 1,
g_boot_rom => true,
g_icap => true,
g_uart => true,
g_drive_1541 => false,
g_drive_1541_2 => false,
g_hardware_gcr => false,
g_ram_expansion => false,
g_extended_reu => false,
g_stereo_sid => false,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => false,
g_c2n_recorder => false,
g_cartridge => true,
g_command_intf => false,
g_drive_sound => false,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => false,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
| gpl-3.0 | ce2172c07105a54d1ba35a4b11e0527e | 0.475687 | 3.378007 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/i2c/rtl/vhdl/tst_ds1621.vhd | 4 | 6,959 | --
--
-- State machine for reading data from Dallas 1621
--
-- Testsystem for i2c controller
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.i2c.all;
entity DS1621_interface is
port (
clk : in std_logic;
nReset : in std_logic;
Dout : out std_logic_vector(7 downto 0); -- data read from ds1621
error : out std_logic; -- no correct ack received
SCL : inout std_logic;
SDA : inout std_logic
);
end entity DS1621_interface;
architecture structural of DS1621_interface is
constant SLAVE_ADDR : std_logic_vector(6 downto 0) := "1001000";
constant CLK_CNT : unsigned(7 downto 0) := conv_unsigned(20, 8);
signal cmd_ack : std_logic;
signal D : std_logic_vector(7 downto 0);
signal lack, store_dout : std_logic;
signal start, read, write, ack, stop : std_logic;
signal i2c_dout : std_logic_vector(7 downto 0);
begin
-- hookup I2C controller
u1: simple_i2c port map (clk => clk, ena => '1', clk_cnt => clk_cnt, nReset => nReset,
read => read, write => write, start => start, stop => stop, ack_in => ack, cmd_ack => cmd_ack,
Din => D, Dout => i2c_dout, ack_out => lack, SCL => SCL, SDA => SDA);
init_statemachine : block
type states is (i1, i2, i3, i4, i5, t1, t2, t3, t4, t5);
signal state : states;
begin
nxt_state_decoder: process(clk, nReset, state)
variable nxt_state : states;
variable iD : std_logic_vector(7 downto 0);
variable ierr : std_logic;
variable istart, iread, iwrite, iack, istop : std_logic;
variable istore_dout : std_logic;
begin
nxt_state := state;
ierr := '0';
istore_dout := '0';
istart := start;
iread := read;
iwrite := write;
iack := ack;
istop := stop;
iD := D;
case (state) is
-- init DS1621
-- 1) send start condition
-- 2) send slave address + write
-- 3) check ack
-- 4) send "access config" command (0xAC)
-- 5) check ack
-- 6) send config register data (0x00)
-- 7) check ack
-- 8) send stop condition
-- 9) send start condition
-- 10) send slave address + write
-- 11) check ack
-- 12) send "start conversion" command (0xEE)
-- 13) check ack
-- 14) send stop condition
when i1 => -- send start condition, sent slave address + write
nxt_state := i2;
istart := '1';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := (slave_addr & '0'); -- write to slave (R/W = '0')
when i2 => -- send "access config" command
if (cmd_ack = '1') then
nxt_state := i3;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no acknowledge received from last command, expected ACK
end if;
istart := '0';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := x"AC";
end if;
when i3 => -- send config register data, sent stop condition
if (cmd_ack = '1') then
nxt_state := i4;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no acknowledge received from last command, expected ACK
end if;
istart := '0';
iread := '0';
iwrite := '1';
iack := '0';
istop := '1';
iD := x"00";
end if;
when i4 => -- send start condition, sent slave address + write
if (cmd_ack = '1') then
nxt_state := i5;
istart := '1';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := (slave_addr & '0'); -- write to slave (R/W = '0')
end if;
when i5 => -- send "start conversion" command + stop condition
if (cmd_ack = '1') then
nxt_state := t1;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no acknowledge received from last command, expected ACK
end if;
istart := '0';
iread := '0';
iwrite := '1';
iack := '0';
istop := '1';
iD := x"EE";
end if;
-- read temperature
-- 1) sent start condition
-- 2) sent slave address + write
-- 3) check ack
-- 4) sent "read temperature" command (0xAA)
-- 5) check ack
-- 6) sent start condition
-- 7) sent slave address + read
-- 8) check ack
-- 9) read msb
-- 10) send ack
-- 11) read lsb
-- 12) send nack
-- 13) send stop condition
when t1 => -- send start condition, sent slave address + write
if (cmd_ack = '1') then
nxt_state := t2;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no acknowledge received from last command, expected ACK
end if;
istart := '1';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := (slave_addr & '0'); -- write to slave (R/W = '0')
end if;
when t2 => -- send read temperature command
if (cmd_ack = '1') then
nxt_state := t3;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no acknowledge received from last command, expected ACK
end if;
istart := '0';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := x"AA";
end if;
when t3 => -- send (repeated) start condition, send slave address + read
if (cmd_ack = '1') then
nxt_state := t4;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no acknowledge received, expected ACK
end if;
istart := '1';
iread := '0';
iwrite := '1';
iack := '0';
istop := '0';
iD := (slave_addr & '1'); -- read from slave (R/W = '1')
end if;
when t4 => -- read MSB (hi-byte), send acknowledge
if (cmd_ack = '1') then
nxt_state := t5;
-- check aknowledge bit
if (lack = '1') then
ierr := '1'; -- no acknowledge received from last command, expected ACK
end if;
istart := '0';
iread := '1';
iwrite := '0';
iack := '0'; --ACK
istop := '0';
end if;
when t5 => -- read LSB (lo-byte), send acknowledge, sent stop
if (cmd_ack = '1') then
nxt_state := t1;
istart := '0';
iread := '1';
iwrite := '0';
iack := '1'; --NACK
istop := '1';
istore_dout := '1';
end if;
end case;
-- genregs
if (nReset = '0') then
state <= i1;
error <= '0';
store_dout <= '0';
start <= '0';
read <= '0';
write <= '0';
ack <= '0';
stop <= '0';
D <= (others => '0');
elsif (clk'event and clk = '1') then
state <= nxt_state;
error <= ierr;
store_dout <= istore_dout;
start <= istart;
read <= iread;
write <= iwrite;
ack <= iack;
stop <= istop;
D <= iD;
end if;
end process nxt_state_decoder;
end block init_statemachine;
-- store temp
gen_dout : process(clk)
begin
if (clk'event and clk = '1') then
if (store_dout = '1') then
Dout <= i2c_dout;
end if;
end if;
end process gen_dout;
end architecture structural;
| gpl-2.0 | 5781c6ca6fe6d97b41ecb398b0db9010 | 0.531973 | 3.019089 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op326_0sk1_0.vhdl | 1 | 4,988 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 4.25e-06,
scope => private
)
port map(
D => net2,
G => net1,
S => net3
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.05e-06,
W => Wdiff_0,
Wdiff_0init => 4.25e-06,
scope => private
)
port map(
D => out1,
G => out1,
S => net3
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => W_0,
W_0init => 3.52e-05
)
port map(
D => net3,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.1e-06,
W => Wcm_1,
Wcm_1init => 1.25e-06,
scope => private
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.1e-06,
W => Wcmout_1,
Wcmout_1init => 6.28e-05,
scope => private
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.5e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => (pfak)*(WBias),
WBiasinit => 2.5e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7e-07,
W => WBias,
WBiasinit => 2.5e-06
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net5,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net5,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net5,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | cd524b3dfc12cbf412499a53bfdf9b52 | 0.592021 | 3.054501 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op338_6sk1_0.vhdl | 1 | 7,571 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.35e-06,
W => Wdiff_0,
Wdiff_0init => 1.45e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.35e-06,
W => Wdiff_0,
Wdiff_0init => 1.45e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => W_0,
W_0init => 5.72e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.35e-06,
W => Wdiff_0,
Wdiff_0init => 1.45e-06,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.35e-06,
W => Wdiff_0,
Wdiff_0init => 1.45e-06,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 2.5e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 2.5e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 2.5e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 2.5e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 2e-06,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 2.6e-06,
W => Wsrc_2,
Wsrc_2init => 1.15e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 2.6e-06,
W => Wsrc_2,
Wsrc_2init => 1.15e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.4e-06,
W => Wcm_1,
Wcm_1init => 2.91e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.4e-06,
W => Wcmout_1,
Wcmout_1init => 5.95e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => (pfak)*(WBias),
WBiasinit => 7.9e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.3e-06,
W => (pfak)*(WBias),
WBiasinit => 7.9e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.3e-06,
W => WBias,
WBiasinit => 7.9e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => WBias,
WBiasinit => 7.9e-06
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => WBias,
WBiasinit => 7.9e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.3e-06,
W => WBias,
WBiasinit => 7.9e-06
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net8,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net8,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net8,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 1e9ddb49ea581cd7ca2677622031b9c1 | 0.580901 | 2.865632 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_sim/token_crc_tb.vhd | 3 | 1,522 | -------------------------------------------------------------------------------
-- Title : token_crc.vhd
-------------------------------------------------------------------------------
-- File : token_crc.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This file is used to calculate the CRC over a USB token
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity token_crc_tb is
end token_crc_tb;
architecture tb of token_crc_tb is
signal clock : std_logic := '0';
signal token_in : std_logic_vector(10 downto 0);
signal crc : std_logic_vector(4 downto 0);
signal total : std_logic_vector(15 downto 0);
begin
i_mut: entity work.token_crc
port map (
clock => clock,
sync => '1',
token_in => token_in,
crc => crc );
clock <= not clock after 10 ns;
p_test: process
begin
token_in <= "0001" & "0000001"; -- EP=1 / ADDR=1
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "111" & X"FB";
wait until clock='1';
wait until clock='1';
wait until clock='1';
token_in <= "000" & X"01";
wait;
end process;
total <= crc & token_in;
end tb;
| gpl-3.0 | 0eee27537f1d9b7e5032a19f3baaeafb | 0.411958 | 4.398844 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/nano_cpu/vhdl_source/nano_alu.vhd | 3 | 1,551 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
entity nano_alu is
port (
clock : in std_logic;
reset : in std_logic;
value_in : in unsigned(15 downto 0);
ext_in : in unsigned(15 downto 0);
alu_oper : in std_logic_vector(15 downto 13);
update_accu : in std_logic;
update_flag : in std_logic;
accu : out unsigned(15 downto 0);
z : out boolean;
n : out boolean );
end entity;
architecture gideon of nano_alu is
signal accu_i : unsigned(15 downto 0) := (others => '0');
signal alu_out : unsigned(15 downto 0);
signal alu_z : boolean;
signal alu_n : boolean;
begin
with alu_oper select alu_out <=
value_in when c_alu_load,
value_in or accu_i when c_alu_or,
value_in and accu_i when c_alu_and,
value_in xor accu_i when c_alu_xor,
accu_i + value_in when c_alu_add,
accu_i - value_in when c_alu_sub,
ext_in when others;
alu_z <= (alu_out = 0);
alu_n <= (alu_out(alu_out'high)='1');
process(clock)
begin
if rising_edge(clock) then
if update_accu='1' then
accu_i <= alu_out;
end if;
if update_flag='1' then
z <= alu_z;
n <= alu_n;
end if;
end if;
end process;
accu <= accu_i;
end architecture;
| gpl-3.0 | c3e2ab9e3ee64d101c7508db5239d81b | 0.506125 | 3.379085 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_source/io_bus_splitter.vhd | 5 | 1,731 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity io_bus_splitter is
generic (
g_range_lo : natural := 16;
g_range_hi : natural := 19;
g_ports : positive := 3 );
port (
clock : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
reqs : out t_io_req_array(0 to g_ports-1);
resps : in t_io_resp_array(0 to g_ports-1) );
end io_bus_splitter;
architecture rtl of io_bus_splitter is
constant c_max_ports : integer := 2 ** (1 + g_range_hi - g_range_lo);
signal dummy_resp : t_io_resp;
begin
-- sanity check
assert g_ports <= c_max_ports
report "Number of ports exceeds decoding capacity of address vector."
severity failure;
-- combinatioral decode
process(req)
begin
for i in reqs'range loop
reqs(i) <= req;
if to_integer(req.address(g_range_hi downto g_range_lo)) = i then
reqs(i).write <= req.write;
reqs(i).read <= req.read;
else
reqs(i).write <= '0';
reqs(i).read <= '0';
end if;
end loop;
end process;
-- prevent hangup from incomplete decode
process(clock)
begin
if rising_edge(clock) then
dummy_resp <= c_io_resp_init;
if to_integer(req.address(g_range_hi downto g_range_lo)) >= g_ports then
dummy_resp.ack <= req.write or req.read;
end if;
end if;
end process;
-- combine responses to one, back to master.
resp <= or_reduce(resps & dummy_resp);
end rtl;
| gpl-3.0 | 5daf242fcf49d6d9194e141794ca25cc | 0.530329 | 3.414201 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_source/mem_bus_arbiter_pri.vhd | 5 | 1,531 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity mem_bus_arbiter_pri is
generic (
g_registered: boolean := true;
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_mem_req_array(0 to g_ports-1);
resps : out t_mem_resp_array(0 to g_ports-1);
req : out t_mem_req;
resp : in t_mem_resp );
end entity;
architecture rtl of mem_bus_arbiter_pri is
signal req_i : t_mem_req;
signal req_c : t_mem_req;
begin
-- prioritize the first request found onto output
process(reqs)
begin
req_i <= c_mem_req_init;
for i in reqs'range loop
if reqs(i).request='1' then
req_i <= reqs(i);
exit;
end if;
end loop;
end process;
-- send the reply to everyone (including tag)
process(resp)
begin
for i in resps'range loop
resps(i) <= resp;
end loop;
end process;
-- output register (will be eliminated when not used)
process(clock)
begin
if rising_edge(clock) then
req_c <= req_i;
if resp.rack = '1' and (resp.rack_tag = req_c.tag) then
req_c.request <= '0';
end if;
end if;
end process;
req <= req_c when g_registered else req_i;
end architecture;
| gpl-3.0 | 80f070fbc556beca45ebe5687f4e176b | 0.519268 | 3.448198 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op330_1sk1_0.vhdl | 1 | 6,475 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.35e-05,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.35e-05,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => W_0,
W_0init => 1.74e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.35e-06,
W => Wcm_2,
Wcm_2init => 4e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.35e-06,
W => Wcmcout_2,
Wcmcout_2init => 4.605e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.35e-06,
W => Wcm_2,
Wcm_2init => 4e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 2.35e-06,
W => Wcmcout_2,
Wcmcout_2init => 4.605e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.85e-06,
W => Wcm_1,
Wcm_1init => 4.475e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.85e-06,
W => Wcmout_1,
Wcmout_1init => 5.84e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.415e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 9.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.415e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 9.5e-07,
W => WBias,
WBiasinit => 1.415e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => WBias,
WBiasinit => 1.415e-05
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => WBias,
WBiasinit => 1.415e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9.5e-07,
W => WBias,
WBiasinit => 1.415e-05
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | f0ad43e5fa630484e661088ecc293fd9 | 0.584556 | 2.94452 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op994_0.vhdl | 1 | 5,740 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net3
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 4368efbd8ab4323b11769bc603493e2a | 0.574913 | 3.106061 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/testmem/simulation/testmem_synth.vhd | 1 | 7,870 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: testmem_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY testmem_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE testmem_synth_ARCH OF testmem_synth IS
COMPONENT testmem_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: testmem_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| mit | 0332e27c7fdbaaf0e90be781e5bc4958 | 0.56493 | 3.776392 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_source/mem_addr_counter.vhd | 2 | 767 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem_addr_counter is
port (
clock : in std_logic;
load_value : in unsigned(25 downto 2);
do_load : in std_logic;
do_inc : in std_logic;
address : out unsigned(25 downto 2) );
end mem_addr_counter;
architecture test of mem_addr_counter is
signal addr_i : unsigned(address'range) := (others => '0');
begin
process(clock)
begin
if rising_edge(clock) then
if do_load='1' then
addr_i <= load_value;
elsif do_inc='1' then
addr_i <= addr_i + 1;
end if;
end if;
end process;
address <= addr_i;
end architecture;
| gpl-3.0 | df7afedfa70a5e64f9b562130b106223 | 0.537158 | 3.454955 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb2/vhdl_source/bridge_to_mem_ctrl.vhd | 4 | 2,777 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bridge_to_mem_ctrl is
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
nano_addr : in unsigned(7 downto 0);
nano_write : in std_logic;
nano_wdata : in std_logic_vector(15 downto 0);
-- cmd interface
sys_clock : in std_logic;
sys_reset : in std_logic;
cmd_addr : out std_logic_vector(3 downto 0);
cmd_valid : out std_logic;
cmd_write : out std_logic;
cmd_wdata : out std_logic_vector(15 downto 0);
cmd_ack : in std_logic );
end entity;
architecture gideon of bridge_to_mem_ctrl is
signal fifo_data_in : std_logic_vector(19 downto 0);
signal fifo_data_out : std_logic_vector(19 downto 0);
signal fifo_get : std_logic;
signal fifo_empty : std_logic;
signal fifo_write : std_logic;
signal cmd_data_out : std_logic_vector(19 downto 0);
begin
fifo_data_in <= std_logic_vector(nano_addr(3 downto 0)) & nano_wdata;
fifo_write <= '1' when (nano_addr(7 downto 4)=X"7" and nano_write='1') else '0';
i_cmd_fifo: entity work.async_fifo
generic map (
g_data_width => 20,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 3,
g_storage => "distributed" )
port map (
-- write port signals (synchronized to write clock)
wr_clock => ulpi_clock,
wr_reset => ulpi_reset,
wr_en => fifo_write,
wr_din => fifo_data_in,
wr_flush => '0',
wr_count => open,
wr_full => open,
wr_almost_full => open,
wr_error => open,
wr_inhibit => open,
-- read port signals (synchronized to read clock)
rd_clock => sys_clock,
rd_reset => sys_reset,
rd_en => fifo_get,
rd_dout => fifo_data_out,
rd_count => open,
rd_empty => fifo_empty,
rd_almost_empty => open,
rd_error => open );
i_ft: entity work.fall_through_add_on
generic map (
g_data_width => 20)
port map (
clock => sys_clock,
reset => sys_reset,
-- fifo side
rd_dout => fifo_data_out,
rd_empty => fifo_empty,
rd_en => fifo_get,
-- consumer side
data_out => cmd_data_out,
data_valid => cmd_valid,
data_next => cmd_ack );
cmd_addr <= cmd_data_out(19 downto 16);
cmd_wdata <= cmd_data_out(15 downto 0);
cmd_write <= '1'; -- we don't support reads yet
end architecture;
| gpl-3.0 | 0f88b246a950fe2bf3924aa059cce6fd | 0.512423 | 3.428395 | false | false | false | false |
KB777/1541UltimateII | fpga/cpu_unit/vhdl_source/cached_mblite.vhd | 1 | 2,656 | library ieee;
use ieee.std_logic_1164.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
library work;
entity cached_mblite is
port (
clock : in std_logic;
reset : in std_logic;
invalidate : in std_logic := '0';
inv_addr : in std_logic_vector(31 downto 0);
dmem_o : out dmem_out_type;
dmem_i : in dmem_in_type;
imem_o : out dmem_out_type;
imem_i : in dmem_in_type;
irq_i : in std_logic;
irq_o : out std_logic );
end entity;
architecture structural of cached_mblite is
-- signals from processor to cache
signal cimem_o : imem_out_type;
signal cimem_i : imem_in_type;
signal cdmem_o : dmem_out_type;
signal cdmem_i : dmem_in_type;
BEGIN
core0 : core
port map (
imem_o => cimem_o,
imem_i => cimem_i,
dmem_o => cdmem_o,
dmem_i => cdmem_i,
int_i => irq_i,
int_o => irq_o,
rst_i => reset,
clk_i => clock );
i_cache: entity work.dm_simple
generic map (
g_data_register => true,
g_mem_direct => true )
port map (
clock => clock,
reset => reset,
dmem_i.adr_o => cimem_o.adr_o,
dmem_i.ena_o => cimem_o.ena_o,
dmem_i.sel_o => "0000",
dmem_i.we_o => '0',
dmem_i.dat_o => (others => '0'),
dmem_o.ena_i => cimem_i.ena_i,
dmem_o.dat_i => cimem_i.dat_i,
mem_o => imem_o,
mem_i => imem_i );
d_cache: entity work.dm_with_invalidate
-- generic map (
-- g_address_swap => X"00010000"
port map (
clock => clock,
reset => reset,
invalidate => invalidate,
inv_addr => inv_addr,
dmem_i => cdmem_o,
dmem_o => cdmem_i,
mem_o => dmem_o,
mem_i => dmem_i );
-- arb: entity work.dmem_arbiter
-- port map (
-- clock => clock,
-- reset => reset,
-- imem_i => imem_o,
-- imem_o => imem_i,
-- dmem_i => dmem_o,
-- dmem_o => dmem_i,
-- mmem_o => mmem_o,
-- mmem_i => mmem_i );
--
-- process(clock)
-- begin
-- if rising_edge(clock) then
-- if cdmem_i.ena_i='1' and cimem_i.ena_i='1' then
-- stuck <= '0';
-- stuck_cnt <= 0;
-- elsif stuck_cnt = 31 then
-- stuck <= '1';
-- else
-- stuck_cnt <= stuck_cnt + 1;
-- end if;
-- end if;
-- end process;
end architecture;
| gpl-3.0 | b3a50866ddddfba4e63314afe1d2990f | 0.470633 | 3.021615 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate2_cached.vhd | 4 | 9,293 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate2_cached is
generic (
g_version : unsigned(7 downto 0) := X"A8" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate2_cached;
architecture structural of ultimate2_cached is
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of LB_DATA: signal is "0";
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal mem_req_cached : t_mem_burst_req;
signal mem_resp_cached : t_mem_burst_resp;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3e_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_shifted => sys_shifted,
-- sys_clock_2x => sys_clock_2x,
eth_clock => open );
i_logic: entity work.ultimate_logic
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Buttons
BUTTON => button_i );
i_cache: entity work.dm_cache
port map (
clock => sys_clock,
reset => sys_reset,
client_req => mem_req,
client_resp => mem_resp,
mem_req => mem_req_cached,
mem_resp => mem_resp_cached );
i_memctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => false,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req_cached,
resp => mem_resp_cached,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
-- tie offs
SDRAM_DQM <= '0';
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
| gpl-3.0 | ce90d3129c3acc627f9ddea4e29bd01f | 0.479824 | 3.44568 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_source/ulpi_tx.vhd | 3 | 8,722 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ulpi_tx is
port (
clock : in std_logic;
reset : in std_logic;
-- Bus Interface
tx_start : out std_logic;
tx_last : out std_logic;
tx_valid : out std_logic;
tx_next : in std_logic;
tx_data : out std_logic_vector(7 downto 0);
-- Status
status : in std_logic_vector(7 downto 0);
speed : in std_logic_vector(1 downto 0);
busy : out std_logic;
tx_ack : out std_logic;
-- Interface to send tokens and handshakes
send_token : in std_logic;
send_handsh : in std_logic;
pid : in std_logic_vector(3 downto 0);
token : in std_logic_vector(10 downto 0);
-- Interface to send data packets
send_data : in std_logic;
no_data : in std_logic := '0';
user_data : in std_logic_vector(7 downto 0);
user_last : in std_logic;
user_next : out std_logic;
-- Interface to output reset packets
send_reset_data : in std_logic;
reset_last : in std_logic;
reset_data : in std_logic );
end ulpi_tx;
architecture gideon of ulpi_tx is
type t_state is (idle, crc_1, crc_2, token1, token2, token3,
reset_pkt, transmit,
wait4next, write_end, handshake, gap, gap2);
signal state : t_state;
-- type t_tx_type is (none, dat, hsh, tok);
-- signal tx_type : t_tx_type := none;
signal j_state : std_logic_vector(1 downto 0);
signal tx_data_i : std_logic_vector(7 downto 0);
signal tx_last_i : std_logic;
signal token_crc : std_logic_vector(4 downto 0);
signal crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
signal no_data_d : std_logic;
constant c_gap_val : integer := 15;
signal gap_count : integer range 0 to 15;
-- XILINX USB STICK:
-- On high speed, gap values 0x05 - 0x25 WORK.. (bigger than 0x25 doesn't, smaller than 0x05 doesn't..)
-- TRUST USB 2.0 Hub:
-- On high speed, gap values 0x07 - 0x1D WORK.. with the exception of 0x09.
-- Samsung DVD-Burner:
-- On high speed, gap values 0x00 - 0x23 WORK.. with the exception of 0x04.
-- Western Digital external HD:
-- On high speed, gap values 0x05 - 0x21 WORK.. with the exception of 0x06 and 0x09.
--
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "sequential";
begin
tx_ack <= (send_token or send_handsh or send_data) when
(state = idle) else '0';
j_state <= not speed(0) & speed(0);
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
tx_data_i <= X"00";
no_data_d <= no_data;
if send_token='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & pid;
state <= token1;
elsif send_handsh='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & pid;
tx_last_i <= '1';
state <= handshake;
elsif send_data='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"4" & pid;
state <= wait4next;
elsif send_reset_data='1' then
tx_start <= '1';
tx_valid <= '1';
tx_data_i <= X"40"; -- pidless
state <= reset_pkt;
end if;
when wait4next =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '1';
if no_data_d='1' then
state <= crc_1;
else
state <= transmit;
end if;
end if;
when handshake =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
state <= gap;
end if;
when write_end =>
if tx_next='1' then
tx_start <= '0';
tx_valid <= '0';
tx_last_i <= '0';
state <= idle;
end if;
when crc_1 =>
if tx_next = '1' then
tx_last_i <= '1';
state <= crc_2;
end if;
when crc_2 =>
if tx_next = '1' then
tx_last_i <= '0';
tx_valid <= '0';
state <= gap;
end if;
when token1 =>
if tx_next = '1' then
tx_start <= '0';
tx_data_i <= token(7 downto 0);
state <= token2;
end if;
when token2 =>
if tx_next = '1' then
tx_data_i <= token_crc & token(10 downto 8);
tx_last_i <= '1';
state <= token3;
end if;
when token3 =>
if tx_next = '1' then
tx_last_i <= '0';
tx_valid <= '0';
state <= gap;
end if;
when gap =>
gap_count <= c_gap_val;
if speed(1)='0' then
if status(1 downto 0)="00" or status(1 downto 0)="11" then --<-- :-o SE1 in low speed?!
state <= gap2;
end if;
else -- high speed
state <= gap2;
end if;
when gap2 =>
if speed(1)='0' then
if status(1 downto 0) = j_state then
state <= idle;
end if;
else
if gap_count = 0 then
state <= idle;
else
gap_count <= gap_count - 1;
end if;
end if;
when transmit =>
if tx_next='1' and user_last='1' then
state <= crc_1;
end if;
when reset_pkt =>
tx_data_i <= (others => reset_data);
if reset_last='1' then
tx_last_i <= '1';
end if;
if tx_next='1' then
tx_start <= '0';
if tx_last_i='1' then
tx_valid <= '0';
tx_last_i <= '0';
state <= idle;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
end if;
end if;
end process;
crc_dvalid <= '1' when (state = transmit) and tx_next='1' else '0';
crc_sync <= '1' when (state = idle) else '0';
busy <= '0' when (state = idle) else '1'; -- or (state = gap) else '1';
i_token_crc: entity work.token_crc
port map (
clock => clock,
sync => '1',
token_in => token,
crc => token_crc );
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => user_data,
crc => data_crc );
with state select tx_data <=
user_data when transmit,
data_crc(7 downto 0) when crc_1,
data_crc(15 downto 8) when crc_2,
tx_data_i when others;
tx_last <= tx_last_i;
user_next <= tx_next when state=transmit else '0';
end gideon;
| gpl-3.0 | d0a5db4f8b58ce2d5730cf0f15186198 | 0.388902 | 4.151356 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_sim/tb_data_oper.vhd | 5 | 4,942 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
library work;
use work.pkg_6502_opcodes.all;
use work.pkg_6502_decode.all;
use work.File_IO_pkg.all;
entity tb_data_oper is
end tb_data_oper;
architecture tb of tb_data_oper is
signal inst : std_logic_vector(7 downto 0);
signal n_in : std_logic := 'Z';
signal v_in : std_logic;
signal z_in : std_logic;
signal c_in : std_logic := 'U';
signal d_in : std_logic := 'U';
signal i_in : std_logic;
signal data_in : std_logic_vector(7 downto 0) := X"55";
signal a_reg : std_logic_vector(7 downto 0) := X"33";
signal x_reg : std_logic_vector(7 downto 0) := X"AB";
signal y_reg : std_logic_vector(7 downto 0) := X"CD";
signal s_reg : std_logic_vector(7 downto 0) := X"EF";
signal alu_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal opcode : string(1 to 13);
begin
mut: entity work.data_oper
generic map (
support_bcd => true )
port map (
inst => inst,
n_in => n_in,
v_in => v_in,
z_in => z_in,
c_in => c_in,
d_in => d_in,
i_in => i_in,
data_in => data_in,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
process
procedure write_str(variable L : inout line; s : string) is
begin
write(L, s);
end procedure;
variable L : line;
begin
for i in 0 to 255 loop
c_in <= 'U';
d_in <= 'U';
inst <= conv_std_logic_vector(i, 8);
opcode <= opcode_array(i);
wait for 1 us;
write(L, VecToHex(inst, 2));
write(L, ' ');
write(L, opcode_array(i));
write(L, ':');
if(n_out /= 'Z') then write(L, 'N'); else write(L, '-'); end if;
if(v_out /= 'U') then write(L, 'V'); else write(L, '-'); end if;
if(z_out /= 'U') then write(L, 'Z'); else write(L, '-'); end if;
if(c_out /= 'U') then write(L, 'C'); else write(L, '-'); end if;
if(d_out /= 'U') then write(L, 'D'); else write(L, '-'); end if;
if(i_out /= 'U') then write(L, 'I'); else write(L, '-'); end if;
c_in <= '0';
d_in <= '0';
wait for 1 us;
write(L, ' ');
if store_a_from_alu(inst) then
write_str(L, "Store ALU in A ");
end if;
if load_x(inst) then
write_str(L, "Store ALU in X ");
end if;
if load_y(inst) then
write_str(L, "Store ALU in Y ");
end if;
if(set_a='1') then
write_str(L, "A:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_x='1') then
write_str(L, "X:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_y='1') then
write_str(L, "Y:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
if(set_s='1') then
write_str(L, "SP:=");
write(L, VecToHex(impl_out, 2));
write_str(L, " ");
end if;
write_str(L, " ALU: " & VecToHex(alu_out, 2));
write_str(L, "; MEM: " & VecToHex(alu_out, 2));
writeline(output, L);
end loop;
wait;
end process;
end tb;
| gpl-3.0 | 0490e0b8258cd78c23d92efb9afa4c7a | 0.408539 | 3.387252 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_sim/harness_v2_mk1.vhd | 5 | 10,827 |
library work;
use work.tl_flat_memory_model_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity harness_v2_mk1 is
end harness_v2_mk1;
architecture tb of harness_v2_mk1 is
constant c_uart_divisor : natural := 434;
signal PHI2 : std_logic := '0';
signal RSTn : std_logic := '1';
signal DOTCLK : std_logic := '1';
signal BUFFER_ENn : std_logic := '1';
signal LB_ADDR : std_logic_vector(21 downto 0);
signal LB_DATA : std_logic_vector(7 downto 0) := X"00";
signal BA : std_logic := '0';
signal DMAn : std_logic := '1';
signal EXROMn : std_logic;
signal GAMEn : std_logic;
signal ROMHn : std_logic := '1';
signal ROMLn : std_logic := '1';
signal IO1n : std_logic := '1';
signal IO2n : std_logic := '1';
signal IRQn : std_logic := '1';
signal NMIn : std_logic := '1';
signal MEM_WEn : std_logic;
signal MEM_OEn : std_logic;
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_DQM : std_logic;
signal PWM_OUT : std_logic_vector(1 downto 0);
signal IEC_ATN : std_logic := '1';
signal IEC_DATA : std_logic := '1';
signal IEC_CLOCK : std_logic := '1';
signal IEC_RESET : std_logic := '1';
signal IEC_SRQ_IN : std_logic := '1';
signal DISK_ACTn : std_logic; -- activity LED
signal CART_LEDn : std_logic;
signal SDACT_LEDn : std_logic;
signal MOTOR_LEDn : std_logic;
signal UART_TXD : std_logic;
signal UART_RXD : std_logic := '1';
signal SD_SSn : std_logic;
signal SD_CLK : std_logic;
signal SD_MOSI : std_logic;
signal SD_MISO : std_logic := '1';
signal SD_WP : std_logic := '1';
signal SD_CARDDETn : std_logic := '1';
signal BUTTON : std_logic_vector(2 downto 0) := "111";
signal SLOT_ADDR : std_logic_vector(15 downto 0);
signal SLOT_DATA : std_logic_vector(7 downto 0);
signal RWn : std_logic := '1';
signal CAS_MOTOR : std_logic := '1';
signal CAS_SENSE : std_logic := '0';
signal CAS_READ : std_logic := '0';
signal CAS_WRITE : std_logic := '0';
signal ETH_CLK : std_logic;
signal ETH_RST : std_logic;
signal ETH_CSn : std_logic;
signal ETH_CS : std_logic;
signal FLASH_CSn : std_logic;
signal SRAM_CSn : std_logic;
signal ONE_WIRE : std_logic := 'H';
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic := '0';
signal rx_char : std_logic_vector(7 downto 0);
signal rx_char_d : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal tx_char : std_logic_vector(7 downto 0) := X"00";
signal tx_done : std_logic;
signal do_tx : std_logic := '0';
shared variable dram : h_mem_object;
shared variable ram : h_mem_object;
shared variable sram : h_mem_object;
-- shared variable bram : h_mem_object;
begin
mut: entity work.ultimate_1541_250e
generic map (
g_simulation => true )
port map (
CLOCK => sys_clock,
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
LB_ADDR => LB_ADDR,
LB_DATA => LB_DATA,
FLASH_CSn => FLASH_CSn,
SRAM_CSn => SRAM_CSn,
MEM_WEn => MEM_WEn,
MEM_OEn => MEM_OEn,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
SDRAM_DQM => SDRAM_DQM,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- USB
USB_IOP => open,
USB_ION => open,
USB_SEP => '1',
USB_SEN => '0',
USB_DET => open,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_WP => '0',
SD_CARDDETn => SD_CARDDETn,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- Ethernet Interface
ETH_CLK => ETH_CLK,
ETH_IRQ => '0',
ETH_CSn => ETH_CSn,
ETH_CS => ETH_CS,
ETH_RST => ETH_RST,
ONE_WIRE => ONE_WIRE,
-- Buttons
BUTTON => BUTTON );
sys_clock <= not sys_clock after 10 ns; -- 50 MHz
sys_reset <= '1', '0' after 100 ns;
PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz
RSTn <= '0', '1' after 6 us;
process
begin
bind_mem_model("intram", ram);
bind_mem_model("dram", dram);
bind_mem_model("sram", sram);
load_memory("../../software/1st_boot/result/1st_boot.bin", ram, X"00000000");
load_memory("../../software/ultimate/result/ultimate_V1.bin", sram, X"00030000");
wait;
end process;
SLOT_DATA <= (others => 'H');
ROMHn <= '1';
ROMLn <= not PHI2 after 50 ns;
IO1n <= '1';
IO2n <= '1';
process
begin
SLOT_ADDR <= X"7FF0";
RWn <= '1';
while true loop
wait until PHI2 = '0';
--SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1);
SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1);
RWn <= '1';
wait until PHI2 = '0';
RWn <= '0';
end loop;
end process;
process
begin
BA <= '1';
for i in 0 to 100 loop
wait until PHI2='0';
end loop;
BA <= '0';
for i in 0 to 10 loop
wait until PHI2='0';
end loop;
end process;
sram_bfm: entity work.sram_model_8
generic map("sram", 19, 10 ns)
port map (LB_ADDR(18 downto 0), LB_DATA, SRAM_CSn, MEM_OEn, MEM_WEn);
flash_bfm: entity work.sram_model_8
generic map("flash", 21, 70 ns)
port map (LB_ADDR(20 downto 0), LB_DATA, FLASH_CSn, MEM_OEn, '1');
dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 1,
g_burst_len_w => 1,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => LB_ADDR(12 downto 0),
BA => LB_ADDR(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => LB_DATA);
-- assert not (ADDRESS(18 downto 16)="011" and ADDRESS(15 downto 0)=X"86A0" and SRAM_CSn='0' and MEM_WEn='0')
-- report "writing to jump address."
-- severity failure;
-- sram: entity work.sram_model_8
-- generic map("sram", 19, 10 ns)
-- port map (LB_ADDR(18 downto 0), LB_DATA, SRAM_CSn, MEM_OEn, MEM_WEn);
--
-- flash: entity work.sram_model_8
-- generic map("flash", 21, 70 ns)
-- port map (LB_ADDR(20 downto 0), LB_DATA, FLASH_CSn, MEM_OEn, '1');
-- process(ETH_CS, ETH_CSn, LB_ADDR)
-- begin
-- if ETH_CS='1' and ETH_CSn='0' then
-- LB_DATA <= not LB_ADDR(7 downto 0) after 135 ns;
-- else
-- LB_DATA <= (others => 'Z') after 50 ns;
-- end if;
-- end process;
i_rx: entity work.rx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
rxd => UART_TXD,
rxchar => rx_char,
rx_ack => rx_ack );
i_tx: entity work.tx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
dotx => do_tx,
txchar => tx_char,
done => tx_done,
txd => UART_RXD );
process(sys_clock)
begin
if rising_edge(sys_clock) then
if rx_ack='1' then
rx_char_d <= rx_char;
end if;
end if;
end process;
process
procedure send_char(i: std_logic_vector(7 downto 0)) is
begin
if tx_done /= '1' then
wait until tx_done = '1';
end if;
wait until sys_clock='1';
tx_char <= i;
do_tx <= '1';
wait until tx_done = '0';
wait until sys_clock='1';
do_tx <= '0';
end procedure;
procedure send_string(i : string) is
variable b : std_logic_vector(7 downto 0);
begin
for n in i'range loop
b := std_logic_vector(to_unsigned(character'pos(i(n)), 8));
send_char(b);
end loop;
send_char(X"0d");
send_char(X"0a");
end procedure;
begin
wait for 2 ms;
--send_string("wd 4005000 12345678");
send_string("run");
-- send_string("m 100000");
-- send_string("w 400000F 4");
wait;
end process;
-- check timing data
process(PHI2)
begin
if falling_edge(PHI2) then
assert SLOT_DATA'last_event >= 189 ns
report "Timing error on C64 bus."
severity error;
end if;
end process;
end tb;
| gpl-3.0 | 16b5a952cb38569c3589a19981044652 | 0.478526 | 3.376052 | false | false | false | false |
chrismasters/fpga-notes | sdramcontroller/ipcore_dir/clks/simulation/timing/clks_tb.vhd | 1 | 6,283 | -- file: clks_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clks_tb is
end clks_tb;
architecture test of clks_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.250 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(2 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clks_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1)
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clks_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
| mit | 5c92f34055c06c8e2cb7f6d7f61089e9 | 0.643323 | 4.256775 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op993_21.vhdl | 1 | 7,074 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net9
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias2,
S => net10
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => vdd
);
subnet0_subnet4_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net11,
G => net4,
S => vdd
);
subnet0_subnet4_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net11
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net12
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net12,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 1936bb9f9954a01e7c3da94bd4f64e35 | 0.570823 | 3.054404 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/via6522.vhd | 1 | 21,899 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity via6522 is
port (
clock : in std_logic;
clock_en : in std_logic; -- for counters and stuff
reset : in std_logic;
addr : in std_logic_vector(3 downto 0);
wen : in std_logic;
ren : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
-- pio --
port_a_o : out std_logic_vector(7 downto 0);
port_a_t : out std_logic_vector(7 downto 0);
port_a_i : in std_logic_vector(7 downto 0);
port_b_o : out std_logic_vector(7 downto 0);
port_b_t : out std_logic_vector(7 downto 0);
port_b_i : in std_logic_vector(7 downto 0);
-- handshake pins
ca1_i : in std_logic;
ca2_o : out std_logic;
ca2_i : in std_logic;
ca2_t : out std_logic;
cb1_o : out std_logic;
cb1_i : in std_logic;
cb1_t : out std_logic;
cb2_o : out std_logic;
cb2_i : in std_logic;
cb2_t : out std_logic;
irq : out std_logic );
end via6522;
architecture Gideon of via6522 is
type pio_t is
record
pra : std_logic_vector(7 downto 0);
ddra : std_logic_vector(7 downto 0);
prb : std_logic_vector(7 downto 0);
ddrb : std_logic_vector(7 downto 0);
end record;
constant pio_default : pio_t := (others => (others => '0'));
signal pio_i : pio_t;
signal irq_mask : std_logic_vector(6 downto 0) := (others => '0');
signal irq_flags : std_logic_vector(6 downto 0) := (others => '0');
signal irq_events : std_logic_vector(6 downto 0) := (others => '0');
signal irq_out : std_logic;
signal timer_a_latch : std_logic_vector(15 downto 0);
signal timer_b_latch : std_logic_vector(7 downto 0);
signal timer_a_count : std_logic_vector(15 downto 0) := X"0000";
signal timer_b_count : std_logic_vector(15 downto 0) := X"0000";
signal timer_a_out : std_logic;
signal timer_b_tick : std_logic;
signal acr, pcr : std_logic_vector(7 downto 0) := X"00";
signal shift_reg : std_logic_vector(7 downto 0) := X"00";
signal serport_en : std_logic;
signal ser_cb2_o : std_logic;
signal hs_cb2_o : std_logic;
alias ca2_event : std_logic is irq_events(0);
alias ca1_event : std_logic is irq_events(1);
alias serial_event : std_logic is irq_events(2);
alias cb2_event : std_logic is irq_events(3);
alias cb1_event : std_logic is irq_events(4);
alias timer_b_event : std_logic is irq_events(5);
alias timer_a_event : std_logic is irq_events(6);
alias ca2_flag : std_logic is irq_flags(0);
alias ca1_flag : std_logic is irq_flags(1);
alias serial_flag : std_logic is irq_flags(2);
alias cb2_flag : std_logic is irq_flags(3);
alias cb1_flag : std_logic is irq_flags(4);
alias timer_b_flag : std_logic is irq_flags(5);
alias timer_a_flag : std_logic is irq_flags(6);
alias tmr_a_output_en : std_logic is acr(7);
alias tmr_a_freerun : std_logic is acr(6);
alias tmr_b_count_mode : std_logic is acr(5);
alias shift_dir : std_logic is acr(4);
alias shift_clk_sel : std_logic_vector(1 downto 0) is acr(3 downto 2);
alias pb_latch_en : std_logic is acr(1);
alias pa_latch_en : std_logic is acr(0);
alias cb2_is_output : std_logic is pcr(7);
alias cb2_edge_select : std_logic is pcr(6); -- for when CB2 is input
alias cb2_no_irq_clr : std_logic is pcr(5); -- for when CB2 is input
alias cb2_out_mode : std_logic_vector(1 downto 0) is pcr(6 downto 5);
alias cb1_edge_select : std_logic is pcr(4);
alias ca2_is_output : std_logic is pcr(3);
alias ca2_edge_select : std_logic is pcr(2); -- for when CA2 is input
alias ca2_no_irq_clr : std_logic is pcr(1); -- for when CA2 is input
alias ca2_out_mode : std_logic_vector(1 downto 0) is pcr(2 downto 1);
alias ca1_edge_select : std_logic is pcr(0);
signal ira, irb : std_logic_vector(7 downto 0) := (others => '0');
signal write_t1c_h : std_logic;
signal write_t2c_h : std_logic;
signal ca1_c, ca2_c : std_logic;
signal cb1_c, cb2_c : std_logic;
signal ca1_d, ca2_d : std_logic;
signal cb1_d, cb2_d : std_logic;
signal set_ca2_low : std_logic;
signal set_cb2_low : std_logic;
begin
irq <= irq_out;
irq_out <= '0' when (irq_flags and irq_mask) = "0000000" else '1';
write_t1c_h <= '1' when addr = X"5" and wen='1' else '0';
write_t2c_h <= '1' when addr = X"9" and wen='1' else '0';
-- input latches
-- ira <= port_a_i when (ca1_flag='0') or (pa_latch_en='0'); -- latch
-- moved to clocked process
irb <= port_b_i;-- when (ca1_flag='0') or (pb_latch_en='0'); -- latch. Port doesn't have a latch!
ca1_event <= (ca1_c xor ca1_d) and (ca1_d xor ca1_edge_select);
ca2_event <= (ca2_c xor ca2_d) and (ca2_d xor ca2_edge_select);
cb1_event <= (cb1_c xor cb1_d) and (cb1_d xor cb1_edge_select);
cb2_event <= (cb2_c xor cb2_d) and (cb2_d xor cb2_edge_select);
ca2_t <= ca2_is_output;
cb2_t <= cb2_is_output when serport_en='0' else shift_dir;
cb2_o <= hs_cb2_o when serport_en='0' else ser_cb2_o;
process(clock)
begin
if rising_edge(clock) then
-- CA1/CA2/CB1/CB2 edge detect flipflops
ca1_c <= To_X01(ca1_i);
ca2_c <= To_X01(ca2_i);
cb1_c <= To_X01(cb1_i);
cb2_c <= To_X01(cb2_i);
ca1_d <= ca1_c;
ca2_d <= ca2_c;
cb1_d <= cb1_c;
cb2_d <= cb2_c;
-- input latch for port a
if ca1_flag='0' or pa_latch_en='0' then
ira <= port_a_i;
end if;
-- CA2 output logic
case ca2_out_mode is
when "00" =>
if ca1_event='1' then
ca2_o <= '1';
elsif (ren='1' or wen='1') and addr=X"1" then
ca2_o <= '0';
end if;
when "01" =>
if clock_en='1' then
ca2_o <= not set_ca2_low;
set_ca2_low <= '0';
end if;
if (ren='1' or wen='1') and addr=X"1" then
if clock_en='1' then
ca2_o <= '0';
else
set_ca2_low <= '1';
end if;
end if;
when "10" =>
ca2_o <= '0';
when "11" =>
ca2_o <= '1';
when others =>
null;
end case;
-- CB2 output logic
case cb2_out_mode is
when "00" =>
if cb1_event='1' then
hs_cb2_o <= '1';
elsif (ren='1' or wen='1') and addr=X"0" then
hs_cb2_o <= '0';
end if;
when "01" =>
if clock_en='1' then
hs_cb2_o <= not set_cb2_low;
set_cb2_low <= '0';
end if;
if (ren='1' or wen='1') and addr=X"0" then
if clock_en='1' then
hs_cb2_o <= '0';
else
set_cb2_low <= '1';
end if;
end if;
when "10" =>
hs_cb2_o <= '0';
when "11" =>
hs_cb2_o <= '1';
when others =>
null;
end case;
-- Interrupt logic
irq_flags <= irq_flags or irq_events;
-- Writes --
if wen='1' then
case addr is
when X"0" => -- ORB
pio_i.prb <= data_in;
if cb2_no_irq_clr='0' then
cb2_flag <= '0';
end if;
cb1_flag <= '0';
when X"1" => -- ORA
pio_i.pra <= data_in;
if ca2_no_irq_clr='0' then
ca2_flag <= '0';
end if;
ca1_flag <= '0';
when X"2" => -- DDRB
pio_i.ddrb <= data_in;
when X"3" => -- DDRA
pio_i.ddra <= data_in;
when X"4" => -- TA LO counter (write=latch)
timer_a_latch(7 downto 0) <= data_in;
when X"5" => -- TA HI counter
timer_a_latch(15 downto 8) <= data_in;
timer_a_flag <= '0';
when X"6" => -- TA LO latch
timer_a_latch(7 downto 0) <= data_in;
when X"7" => -- TA HI latch
timer_a_latch(15 downto 8) <= data_in;
timer_a_flag <= '0';
when X"8" => -- TB LO latch
timer_b_latch(7 downto 0) <= data_in;
when X"9" => -- TB HI counter
timer_b_flag <= '0';
when X"A" => -- Serial port
serial_flag <= '0';
when X"B" => -- ACR (Auxiliary Control Register)
acr <= data_in;
when X"C" => -- PCR (Peripheral Control Register)
pcr <= data_in;
when X"D" => -- IFR
irq_flags <= irq_flags and not data_in(6 downto 0);
when X"E" => -- IER
if data_in(7)='1' then -- set
irq_mask <= irq_mask or data_in(6 downto 0);
else -- clear
irq_mask <= irq_mask and not data_in(6 downto 0);
end if;
when X"F" => -- ORA no handshake
pio_i.pra <= data_in;
when others =>
null;
end case;
end if;
-- Reads --
case addr is
when X"0" => -- ORB
data_out <= irb;
if cb2_no_irq_clr='0' and ren='1' then
cb2_flag <= '0';
end if;
if ren='1' then
cb1_flag <= '0';
end if;
when X"1" => -- ORA
data_out <= ira;
if ca2_no_irq_clr='0' and ren='1' then
ca2_flag <= '0';
end if;
if ren='1' then
ca1_flag <= '0';
end if;
when X"2" => -- DDRB
data_out <= pio_i.ddrb;
when X"3" => -- DDRA
data_out <= pio_i.ddrb;
when X"4" => -- TA LO counter
data_out <= timer_a_count(7 downto 0);
if ren='1' then
timer_a_flag <= '0';
end if;
when X"5" => -- TA HI counter
data_out <= timer_a_count(15 downto 8);
when X"6" => -- TA LO latch
data_out <= timer_a_latch(7 downto 0);
when X"7" => -- TA HI latch
data_out <= timer_a_latch(15 downto 8);
when X"8" => -- TA LO counter
data_out <= timer_b_count(7 downto 0);
if ren='1' then
timer_b_flag <= '0';
end if;
when X"9" => -- TA HI counter
data_out <= timer_b_count(15 downto 8);
when X"A" => -- SR
data_out <= shift_reg;
if ren='1' then
serial_flag <= '0';
end if;
when X"B" => -- ACR
data_out <= acr;
when X"C" => -- PCR
data_out <= pcr;
when X"D" => -- IFR
data_out <= irq_out & irq_flags;
when X"E" => -- IER
data_out <= '0' & irq_mask;
when X"F" => -- ORA
data_out <= port_a_i;
when others =>
null;
end case;
if reset='1' then
pio_i <= pio_default;
irq_mask <= (others => '0');
irq_flags <= (others => '0');
timer_a_latch <= (others => '0');
timer_b_latch <= (others => '0');
acr <= (others => '0');
pcr <= (others => '0');
ca2_o <= '1';
hs_cb2_o <= '1';
set_ca2_low <= '0';
set_cb2_low <= '0';
end if;
end if;
end process;
-- PIO Out select --
port_a_o <= pio_i.pra;
port_b_o(6 downto 0) <= pio_i.prb(6 downto 0);
port_b_o(7) <= pio_i.prb(7) when tmr_a_output_en='0' else timer_a_out;
port_a_t <= pio_i.ddra;
port_b_t(6 downto 0) <= pio_i.ddrb(6 downto 0);
port_b_t(7) <= pio_i.ddrb(7) or tmr_a_output_en;
-- Timer A
tmr_a: block
signal timer_a_reload : std_logic;
signal timer_a_run : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
timer_a_event <= '0';
if clock_en='1' then
-- always count, or load
if timer_a_reload = '1' then
timer_a_count <= timer_a_latch;
timer_a_reload <= '0';
else
timer_a_count <= timer_a_count - 1;
end if;
if timer_a_count = 0 then
-- generate an event if we were triggered
timer_a_event <= timer_a_run;
-- continue to be triggered in free running mode
timer_a_run <= tmr_a_freerun;
-- toggle output
timer_a_out <= not timer_a_out;
-- if in free running mode, set a flag to reload
timer_a_reload <= tmr_a_freerun;
end if;
end if;
if write_t1c_h = '1' then
timer_a_out <= '0';
timer_a_count <= data_in & timer_a_latch(7 downto 0);
timer_a_run <= '1';
end if;
if reset='1' then
timer_a_count <= (others => '0');
timer_a_out <= '1';
timer_a_reload <= '0';
timer_a_run <= '0';
end if;
end if;
end process;
end block tmr_a;
-- Timer B
tmr_b: block
signal timer_b_trig : std_logic;
signal pb6_c, pb6_d : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
timer_b_event <= '0';
timer_b_tick <= '0';
pb6_c <= port_b_i(6);
if timer_b_count = X"0000" and timer_b_trig='1' then
timer_b_event <= '1';
timer_b_trig <= '0';
end if;
if clock_en='1' then
pb6_d <= pb6_c;
if tmr_b_count_mode = '1' then
if (pb6_d='0' and pb6_c='1') then
timer_b_count <= timer_b_count - 1;
end if;
else -- one shot or used for shirt register
if timer_b_count = X"0000" then
timer_b_count <= X"00" & timer_b_latch(7 downto 0);
timer_b_tick <= '1';
else
timer_b_count <= timer_b_count - 1;
end if;
end if;
end if;
if write_t2c_h = '1' then
timer_b_count <= data_in & timer_b_latch(7 downto 0);
timer_b_trig <= '1';
end if;
if reset='1' then
timer_b_count <= (others => '0');
timer_b_trig <= '0';
end if;
end if;
end process;
end block tmr_b;
ser: block
signal shift_clock_d : std_logic;
signal shift_clock : std_logic;
signal shift_tick_r : std_logic;
signal shift_tick_f : std_logic;
signal cb1_c, cb2_c : std_logic;
signal mpu_write : std_logic;
signal mpu_read : std_logic;
signal bit_cnt : integer range 0 to 7;
signal shift_active : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
case shift_clk_sel is
when "10" =>
if shift_active='0' then
shift_clock <= '1';
elsif clock_en='1' then
shift_clock <= not shift_clock;
end if;
when "00"|"01" =>
if shift_active='0' then
shift_clock <= '1';
elsif timer_b_tick='1' then
shift_clock <= not shift_clock;
end if;
when others => -- "11"
shift_clock <= To_X01(cb1_i);
end case;
shift_clock_d <= shift_clock;
end if;
end process;
shift_tick_r <= not shift_clock_d and shift_clock;
shift_tick_f <= shift_clock_d and not shift_clock;
cb1_t <= '0' when shift_clk_sel="11" else serport_en;
cb1_o <= shift_clock;
mpu_write <= wen when addr=X"A" else '0';
mpu_read <= ren when addr=X"A" else '0';
serport_en <= shift_dir or shift_clk_sel(1) or shift_clk_sel(0);
process(clock)
begin
if rising_edge(clock) then
cb1_c <= To_X01(cb1_i);
cb2_c <= To_X01(cb2_i);
if shift_clk_sel = "00" then
bit_cnt <= 7;
if shift_dir='0' then -- disabled mode
shift_active <= '0';
end if;
end if;
if mpu_read='1' or mpu_write='1' then
bit_cnt <= 7;
shift_active <= '1';
if mpu_write='1' then
shift_reg <= data_in;
end if;
end if;
serial_event <= '0';
if shift_active='1' then
if shift_tick_f='1' then
ser_cb2_o <= shift_reg(7);
end if;
if shift_tick_r='1' then
if shift_dir='1' then -- output
shift_reg <= shift_reg(6 downto 0) & shift_reg(7);
else
shift_reg <= shift_reg(6 downto 0) & cb2_c;
end if;
if bit_cnt=0 then
serial_event <= '1';
shift_active <= '0';
else
bit_cnt <= bit_cnt - 1;
end if;
end if;
end if;
if reset='1' then
shift_reg <= (others => '1');
shift_active <= '0';
bit_cnt <= 0;
ser_cb2_o <= '1';
end if;
end if;
end process;
end block ser;
end Gideon;
| gpl-3.0 | 5e56f3c49619e7eaa9e8601e4ac303bf | 0.380109 | 3.934423 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op990_9.vhdl | 1 | 7,073 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net9
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net10
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net11,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net11
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net12
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net12,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 0d144b133320a8076bad0db7dcd9d78a | 0.570762 | 3.053972 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/audio_select/vhdl_source/audio_select.vhd | 4 | 2,232 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity audio_select is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
drive0 : in std_logic;
drive1 : in std_logic;
cas_read : in std_logic;
cas_write : in std_logic;
sid_left : in std_logic;
sid_right : in std_logic;
samp_left : in std_logic;
samp_right : in std_logic;
pwm_out : out std_logic_vector(1 downto 0) );
end audio_select;
architecture gideon of audio_select is
signal left_select : std_logic_vector(2 downto 0);
signal right_select : std_logic_vector(2 downto 0);
signal in_vec : std_logic_vector(0 to 7);
begin
in_vec <= drive0 & drive1 & cas_read & cas_write & sid_left & sid_right & samp_left & samp_right;
process(clock)
begin
if rising_edge(clock) then
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
left_select <= req.data(2 downto 0);
when X"1" =>
right_select <= req.data(2 downto 0);
when others =>
null;
end case;
elsif req.read='1' then
resp.ack <= '1';
case req.address(3 downto 0) is
when X"0" =>
resp.data(2 downto 0) <= left_select;
when X"1" =>
resp.data(2 downto 0) <= right_select;
when others =>
null;
end case;
end if;
pwm_out(0) <= in_vec(to_integer(unsigned(left_select)));
pwm_out(1) <= in_vec(to_integer(unsigned(right_select)));
if reset='1' then
left_select <= "000";
right_select <= "000";
end if;
end if;
end process;
end gideon;
| gpl-3.0 | 620a927096c88dc00c8c48dfc8e49f43 | 0.473118 | 3.647059 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op336_0sk1_0.vhdl | 1 | 7,230 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.6e-06,
W => Wdiff_0,
Wdiff_0init => 3.45e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.6e-06,
W => Wdiff_0,
Wdiff_0init => 3.45e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.2e-06,
W => W_0,
W_0init => 5.84e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.6e-06,
W => Wdiff_0,
Wdiff_0init => 3.45e-06,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.6e-06,
W => Wdiff_0,
Wdiff_0init => 3.45e-06,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.26e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.2e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.26e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.2e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.26e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.2e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.26e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.2e-06,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 5.55e-06,
W => Wsrc_2,
Wsrc_2init => 8e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
Lsrcinit => 5.55e-06,
W => Wsrc_2,
Wsrc_2init => 8e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 3.95e-06,
W => Wcm_1,
Wcm_1init => 4.36e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 3.95e-06,
W => Wcmcout_1,
Wcmcout_1init => 5.6e-06,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 5.2e-06,
W => (pfak)*(WBias),
WBiasinit => 1.87e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 5.2e-06,
W => (pfak)*(WBias),
WBiasinit => 1.87e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 5.2e-06,
W => WBias,
WBiasinit => 1.87e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.2e-06,
W => WBias,
WBiasinit => 1.87e-05
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.2e-06,
W => WBias,
WBiasinit => 1.87e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.2e-06,
W => WBias,
WBiasinit => 1.87e-05
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net8,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net8,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net8,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 6c0e5e7a9af306fdd5bbc7bab462da5b | 0.581881 | 2.873609 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/slot_master_v4.vhd | 4 | 8,791 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
entity slot_master_v4 is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
DMAn : out std_logic := '1';
BA : in std_logic := '0';
RWn_in : in std_logic;
RWn_out : out std_logic;
RWn_tri : out std_logic;
ADDRESS_out : out std_logic_vector(15 downto 0);
ADDRESS_tri_h : out std_logic;
ADDRESS_tri_l : out std_logic;
DATA_in : in std_logic_vector(7 downto 0);
DATA_out : out std_logic_vector(7 downto 0) := (others => '1');
DATA_tri : out std_logic;
-- timing inputs
vic_cycle : in std_logic;
phi2_recovered : in std_logic;
phi2_tick : in std_logic;
do_sample_addr : in std_logic;
do_sample_io : in std_logic;
do_io_event : in std_logic;
reu_dma_n : in std_logic := '1';
cmd_if_freeze : in std_logic := '0';
-- request from the memory controller to do a cycle on the cart bus
dma_req : in t_dma_req;
dma_resp : out t_dma_resp;
-- system control
stop_cond : in std_logic_vector(1 downto 0);
c64_stop : in std_logic; -- condition to start looking for a stop moment
c64_stopped : out std_logic ); -- indicates that stopping has succeeded
end slot_master_v4;
architecture gideon of slot_master_v4 is
signal ba_c : std_logic;
signal rwn_c : std_logic := '1';
signal dma_n_i : std_logic := '1';
signal data_c : std_logic_vector(7 downto 0) := (others => '1');
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
signal data_d : t_byte_array(0 to 7);
signal addr_out : std_logic_vector(15 downto 0) := (others => '1');
signal drive_ah : std_logic;
signal drive_al : std_logic;
signal dma_ack_i : std_logic;
signal rwn_out_i : std_logic;
signal phi2_dly : std_logic_vector(6 downto 0) := (others => '0');
signal reu_active : std_logic;
signal cmd_if_active: std_logic;
constant match_ptrn : std_logic_vector(1 downto 0) := "01"; -- read from left to right
signal rwn_hist : std_logic_vector(3 downto 0);
signal ba_count : integer range 0 to 15;
attribute register_duplication : string;
attribute register_duplication of rwn_c : signal is "no";
attribute register_duplication of ba_c : signal is "no";
attribute keep : string;
attribute keep of rwn_hist : signal is "true";
type t_state is (idle, stopped, do_dma );
signal state : t_state;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
signal dma_rack : std_logic;
begin
process(clock)
variable stop : boolean;
begin
if rising_edge(clock) then
ba_c <= BA;
rwn_c <= RWn_in;
data_c <= DATA_in;
data_d(0) <= data_c;
data_d(1 to 7) <= data_d(0 to 6);
dma_rack <= '0';
phi2_dly <= phi2_dly(phi2_dly'high-1 downto 0) & phi2_recovered;
-- consecutive write counter (match counter)
if do_sample_addr='1' and phi2_recovered='1' then -- count CPU cycles only (sample might become true for VIC cycles)
-- the following statement detects a bad line. VIC wants bus. We just wait in line until VIC is done,
-- by pulling DMA low halfway the bad line. This is the safest method.
if ba_c='0' then
if ba_count /= 15 then
ba_count <= ba_count + 1;
end if;
else
ba_count <= 0;
end if;
-- the following statement detects a rw/n pattern, that indicates that it's safe to pull dma low
rwn_hist <= rwn_hist(rwn_hist'high-1 downto 0) & rwn_c;
end if;
case stop_cond is
when "00" => stop := (ba_count = 14);
when "01" => stop := (rwn_hist(match_ptrn'range) = match_ptrn);
when others => stop := true;
end case;
case state is
when idle =>
dma_ack_i <= dma_req.request and dma_req.read_writen; -- do not serve DMA requests when machine is not stopped
dma_rack <= dma_req.request;
dma_n_i <= '1';
reu_active <= '0';
cmd_if_active <= '0';
if reu_dma_n='0' then -- for software assited REU-debugging
reu_active <= '1';
dma_n_i <= '0';
c64_stopped <= '1';
state <= stopped;
elsif cmd_if_freeze='1' then
cmd_if_active <= '1';
dma_n_i <= '0';
c64_stopped <= '1';
state <= stopped;
elsif c64_stop='1' and do_io_event='1' then
if stop then
dma_n_i <= '0';
state <= stopped;
c64_stopped <= '1';
end if;
end if;
when stopped =>
dma_ack_i <= '0';
rwn_out_i <= '1';
addr_out(15 downto 14) <= "00"; -- always in a safe area
-- is the dma request active and are we at the right time?
if dma_req.request='1' and dma_ack_i='0' and phi2_tick='1' and ba_c='1' then
dma_rack <= '1';
DATA_out <= dma_req.data;
addr_out <= std_logic_vector(dma_req.address);
rwn_out_i <= dma_req.read_writen;
state <= do_dma;
elsif reu_active='1' and reu_dma_n='1' and do_io_event='1' then
c64_stopped <= '0';
dma_n_i <= '1';
state <= idle;
elsif cmd_if_active='1' and cmd_if_freeze='0' and do_io_event='1' then
c64_stopped <= '0';
dma_n_i <= '1';
state <= idle;
elsif reu_active='0' and c64_stop = '0' and do_io_event='1' then
if stop then
c64_stopped <= '0';
dma_n_i <= '1';
state <= idle;
end if;
end if;
when do_dma =>
if phi2_recovered='0' then -- end of CPU cycle
--if do_io_event='1' then
dma_ack_i <= '1';
state <= stopped;
end if;
when others =>
null;
end case;
drive_ah <= drive_al; -- one cycle later on (SSO)
if (dma_n_i='0' and phi2_recovered='1' and vic_cycle='0') then
drive_al <= '1';
else
drive_al <= '0';
drive_ah <= '0'; -- off at the same time
end if;
if reset='1' then
state <= idle;
dma_n_i <= '1';
c64_stopped <= '0';
rwn_out_i <= '1';
addr_out <= (others => '1');
end if;
end if;
end process;
dma_resp.dack <= dma_ack_i and rwn_out_i; -- only data-acknowledge reads
dma_resp.rack <= dma_rack;
dma_resp.data <= data_d(3) when dma_ack_i='1' and rwn_out_i='1' else X"00";
-- by shifting the phi2 and anding it with the original, we make the write enable narrower,
-- starting only halfway through the cycle. We should not be too fast!
DATA_tri <= '1' when (dma_n_i='0' and phi2_recovered='1' and phi2_dly(phi2_dly'high)='1' and
vic_cycle='0' and rwn_out_i='0') else '0';
RWn_tri <= drive_al; --'1' when (dma_n_i='0' and phi2_recovered='1' and ba_c='1') else '0';
ADDRESS_out <= addr_out;
ADDRESS_tri_h <= drive_ah;
ADDRESS_tri_l <= drive_al;
RWn_out <= rwn_out_i;
DMAn <= dma_n_i;
end gideon;
| gpl-3.0 | 1c0866321c6e718f3815aef2fa3fadbd | 0.456035 | 3.752027 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/memory/vhdl_source/pseudo_dpram.vhd | 4 | 1,915 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pseudo_dpram is
generic (
g_width_bits : positive := 16;
g_depth_bits : positive := 9;
g_read_first : boolean := false;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
rd_address : in unsigned(g_depth_bits-1 downto 0);
rd_data : out std_logic_vector(g_width_bits-1 downto 0);
rd_en : in std_logic := '1';
wr_address : in unsigned(g_depth_bits-1 downto 0);
wr_data : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
wr_en : in std_logic := '0' );
attribute keep_hierarchy : string;
attribute keep_hierarchy of pseudo_dpram : entity is "yes";
end entity;
architecture xilinx of pseudo_dpram is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
shared variable ram : t_ram := (others => (others => '0'));
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
process(clock)
begin
if rising_edge(clock) then
if g_read_first then
if rd_en='1' then
rd_data <= ram(to_integer(rd_address));
end if;
end if;
if wr_en='1' then
ram(to_integer(wr_address)) := wr_data;
end if;
if not g_read_first then
if rd_en='1' then
rd_data <= ram(to_integer(rd_address));
end if;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 435b4d8b377a725d3b7007361ada99ea | 0.493473 | 3.860887 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op332_1sk1_0.vhdl | 1 | 6,261 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.85e-06,
W => Wdiff_0,
Wdiff_0init => 1.65e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.85e-06,
W => Wdiff_0,
Wdiff_0init => 1.65e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.6e-06,
W => W_0,
W_0init => 4.5e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.1e-06,
W => Wcm_2,
Wcm_2init => 8e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.1e-06,
W => Wcmout_2,
Wcmout_2init => 7.49e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.1e-06,
W => Wcm_2,
Wcm_2init => 8e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.1e-06,
W => Wcmout_2,
Wcmout_2init => 7.49e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.25e-06,
W => Wcm_1,
Wcm_1init => 6.45e-06,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.25e-06,
W => Wcmcout_1,
Wcmcout_1init => 6.48e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 5.6e-06,
W => (pfak)*(WBias),
WBiasinit => 2.025e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 5.6e-06,
W => (pfak)*(WBias),
WBiasinit => 2.025e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 5.6e-06,
W => WBias,
WBiasinit => 2.025e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.6e-06,
W => WBias,
WBiasinit => 2.025e-05
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.6e-06,
W => WBias,
WBiasinit => 2.025e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.6e-06,
W => WBias,
WBiasinit => 2.025e-05
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | b23a694e98aa4d92fa191fbc5b243646 | 0.584092 | 2.943583 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/tb_PatchReader.vhd | 1 | 6,029 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:05:32 12/21/2013
-- Design Name:
-- Module Name: /media/DATA42/Projects/ComputerVision/RetinaDescriptors/tb_PatchReader.vhd
-- Project Name: RetinaDescriptors
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: PatchReader
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.RetinaParameters.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_PatchReader IS
END tb_PatchReader;
ARCHITECTURE behavior OF tb_PatchReader IS
-- Component Declaration for the Unit Under Test (UUT)
component ImagePatchReader
port ( addr : in std_logic_vector (31 downto 0);
busy_in : in std_logic;
clk : in std_logic;
memData : in std_logic_vector (PIXEL_BW-1 downto 0);
rst : in std_logic;
addrKernel : out std_logic_vector (N_GAUSS_KERNEL_BW-1 downto 0);
en_out : out std_logic;
memAddr : out std_logic_vector (31 downto 0);
patchColumn : out T_INPUT_VERTICAL_CONVOLUTION;
readMem : out std_logic;
request_out : out std_logic);
end component;
COMPONENT RAM
PORT(
clk: IN std_logic;
address: IN std_logic_vector(31 downto 0);
read_en: IN std_logic;
data_out: OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--signals of PathReader component
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal busy_in : std_logic := '0';
signal mem_data : std_logic_vector(7 downto 0) := (others => '0');
signal mem_addr_in : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal req_out : std_logic;
signal enable_out : std_logic;
signal mem_addr_out : std_logic_vector(31 downto 0);
signal read_mem : std_logic;
signal patch_column : input_vert_conv_type;
signal addrKernel: std_logic_vector (N_GAUSS_KERNEL_BW-1 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
--control signals for FSM producer of addresses
type producer_FSM_states is (INIT, REQ, READY);
signal s_producerState: producer_FSM_states;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ImagePatchReader PORT MAP (
clk => clk,
rst => rst,
busy_in => busy_in,
request_out => req_out,
en_out => enable_out,
memAddr => mem_addr_out,
readMem => read_mem,
memData => mem_data,
addr => mem_addr_in,
patchColumn => patch_column,
addrKernel => addrKernel
);
comp_ram: RAM PORT MAP(
clk => clk,
address => mem_addr_out,
read_en => read_mem,
data_out => mem_data
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
-- wait for clk_period*100;
-- insert stimulus here
wait;
end process;
--simulate the AddressGenerator's producer
stim_proc: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
mem_addr_in <= std_logic_vector(to_unsigned(480, mem_addr_in'length));
busy_in <= '0';
s_producerState <= INIT;
else
case s_producerState is
when INIT =>
if req_out = '1' then
busy_in <= '1';
s_producerState <= REQ;
end if;
when REQ =>
busy_in <= '0';
s_producerState <= READY;
when READY =>
busy_in <= '1';
end case;
end if;
end if;
end process;
END;
| gpl-3.0 | 6a9eb97ebadb5b7dd09e9444af345186 | 0.547023 | 4.095788 | false | false | false | false |
KB777/1541UltimateII | fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_mb_700a.vhd | 1 | 9,995 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_mb_700a is
generic (
g_version : unsigned(7 downto 0) := X"04" );
port (
CLOCK : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- memory
SDRAM_A : out std_logic_vector(12 downto 0); -- DRAM A
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- LED Interface
LED_CLK : out std_logic;
LED_DATA : out std_logic;
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end entity;
architecture structural of ultimate_mb_700a is
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic;
signal sys_reset : std_logic;
signal sys_clock_2x : std_logic;
-- signal sys_shifted : std_logic;
signal button_i : std_logic_vector(2 downto 0);
-- miscellaneous interconnect
signal ulpi_reset_i : std_logic;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
-- IEC open drain
signal iec_atn_o : std_logic;
signal iec_data_o : std_logic;
signal iec_clock_o : std_logic;
signal iec_srq_o : std_logic;
-- debug
signal scale_cnt : unsigned(11 downto 0) := X"000";
attribute iob : string;
attribute iob of scale_cnt : signal is "false";
begin
reset_in <= '1' when BUTTON="000" else '0'; -- all 3 buttons pressed
button_i <= not BUTTON;
i_clkgen: entity work.s3a_clockgen
port map (
clk_50 => CLOCK,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 50 MHz
sys_reset => sys_reset,
sys_clock_2x => sys_clock_2x );
i_logic: entity work.ultimate_logic_32
generic map (
g_version => g_version,
g_simulation => false,
g_clock_freq => 50_000_000,
g_baud_rate => 115_200,
g_timer_rate => 200_000,
g_icap => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => false,
g_hardware_gcr => true,
g_ram_expansion => true,
g_extended_reu => false,
g_stereo_sid => true,
g_hardware_iec => true,
g_iec_prog_tim => false,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_cartridge => true,
g_command_intf => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => false,
g_usb_host => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_video_overlay => false,
g_sampler => true,
g_analyzer => false,
g_profiler => true )
port map (
-- globals
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset_i,
-- slot side
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => open,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
-- LED interface
LED_CLK => LED_CLK,
LED_DATA => LED_DATA,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
vid_clock => sys_clock,
vid_reset => sys_reset,
vid_h_count => X"000",
vid_v_count => X"000",
vid_active => open,
vid_opaque => open,
vid_data => open,
-- Buttons
BUTTON => button_i );
IEC_ATN <= '0' when iec_atn_o = '0' else 'Z';
IEC_DATA <= '0' when iec_data_o = '0' else 'Z';
IEC_CLOCK <= '0' when iec_clock_o = '0' else 'Z';
IEC_SRQ_IN <= '0' when iec_srq_o = '0' else 'Z';
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => false )
port map (
clock => sys_clock,
clk_2x => sys_clock_2x,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
process(ulpi_clock, reset_in)
begin
if rising_edge(ulpi_clock) then
ulpi_reset_i <= sys_reset;
end if;
if reset_in='1' then
ulpi_reset_i <= '1';
end if;
end process;
process(ulpi_clock)
begin
if rising_edge(ulpi_clock) then
scale_cnt <= scale_cnt + 1;
end if;
end process;
ULPI_RESET <= ulpi_reset_i;
end structural;
| gpl-3.0 | eedb1c1e166fa749b0fc64a1af2ca402 | 0.472536 | 3.382403 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/synchroniser/vhdl_source/input_synchronizer.vhd | 5 | 3,069 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2008, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Input synchronizer block
-------------------------------------------------------------------------------
-- Description: The input synchronizer block synchronizes an asynchronous
-- input to the clock of the receiving module. Two flip-flops are
-- used to avoid metastability of the synchronized signal.
--
--
-- Please read Ran Ginosars paper "Fourteen ways to fool your
-- synchronizer" before considering modifications to this module!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity input_synchronizer is
generic (
g_width : positive := 1;
g_reset_val : std_logic := '0'
);
port (
-- Clock signal
clock : in std_logic;
-- Asynchronous input
reset : in std_logic;
-- Asynchronous input
input : in std_logic;
-- Synchronized input
input_c : out std_logic
);
---------------------------------------------------------------------------
-- Synthesis attributes to prevent duplication and balancing.
---------------------------------------------------------------------------
-- Xilinx attributes
attribute register_duplication : string;
attribute register_duplication of input_synchronizer : entity is "no";
attribute register_balancing : string;
attribute register_balancing of input_synchronizer : entity is "no";
-- Altera attributes
attribute dont_replicate : boolean;
attribute dont_replicate of input_synchronizer : entity is true;
attribute dont_retime : boolean;
attribute dont_retime of input_synchronizer : entity is true;
---------------------------------------------------------------------------
end input_synchronizer;
architecture rtl of input_synchronizer is
signal sync1 : std_logic;
signal sync2 : std_logic;
-- Xilinx attributes
attribute iob : string;
attribute iob of sync1 : signal is "true";
-- Altera attributes
-- Add FAST_INPUT_REGISTER to qsf file to force the sync1 register into an iob
begin
p_input_synchronization : process(clock)
begin
if rising_edge(clock) then
sync1 <= input;
sync2 <= sync1;
if reset = '1' then
sync1 <= g_reset_val;
sync2 <= g_reset_val;
end if;
end if;
end process;
input_c <= sync2;
end rtl;
| gpl-3.0 | 470008f09e2b5ea53c8a295a0295a64c | 0.446074 | 5.631193 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_bfm/mem_bus_master_bfm_pkg.vhd | 5 | 4,335 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.mem_bus_pkg.all;
package mem_bus_master_bfm_pkg is
type t_mem_bus_master_bfm_object;
type p_mem_bus_master_bfm_object is access t_mem_bus_master_bfm_object;
type t_mem_bus_bfm_command is ( e_mem_none, e_mem_read, e_mem_write );
type t_mem_bus_master_bfm_object is record
next_bfm : p_mem_bus_master_bfm_object;
name : string(1 to 256);
command : t_mem_bus_bfm_command;
poll_time : time;
tag : std_logic_vector(7 downto 0);
address : unsigned(25 downto 0);
data : std_logic_vector(7 downto 0);
end record;
------------------------------------------------------------------------------------
shared variable mem_bus_master_bfms : p_mem_bus_master_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_mem_bus_master_bfm(named : string; variable pntr: inout p_mem_bus_master_bfm_object);
procedure bind_mem_bus_master_bfm(named : string; variable pntr: inout p_mem_bus_master_bfm_object);
------------------------------------------------------------------------------------
procedure mem_read(variable m : inout p_mem_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure mem_write(variable m : inout p_mem_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
end mem_bus_master_bfm_pkg;
package body mem_bus_master_bfm_pkg is
procedure register_mem_bus_master_bfm(named : string;
variable pntr : inout p_mem_bus_master_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_mem_bus_master_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
-- add this pointer to the head of the linked list
if mem_bus_master_bfms = null then -- first entry
mem_bus_master_bfms := pntr;
else -- insert new entry
pntr.next_bfm := mem_bus_master_bfms;
mem_bus_master_bfms := pntr;
end if;
pntr.tag := X"01";
pntr.poll_time := 2 ns;
end register_mem_bus_master_bfm;
procedure bind_mem_bus_master_bfm(named : string;
variable pntr : inout p_mem_bus_master_bfm_object) is
variable p : p_mem_bus_master_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := mem_bus_master_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_mem_bus_master_bfm;
------------------------------------------------------------------------------
procedure mem_read(variable m : inout p_mem_bus_master_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(25 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_mem_read;
while m.command /= e_mem_none loop
wait for m.poll_time;
end loop;
data := m.data;
end procedure;
procedure mem_write(variable m : inout p_mem_bus_master_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(25 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_mem_write;
m.data := data;
while m.command /= e_mem_none loop
wait for m.poll_time;
end loop;
end procedure;
end;
------------------------------------------------------------------------------
| gpl-3.0 | de1e49f6b287d0b6211373187049a2b4 | 0.498962 | 3.948087 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/ram/simulation/ram_tb.vhd | 1 | 4,292 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ram_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ram_tb IS
END ENTITY;
ARCHITECTURE ram_tb_ARCH OF ram_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ram_synth_inst:ENTITY work.ram_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | a303804dbe18590ba08a355f53000490 | 0.617894 | 4.675381 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/lpm_add_sub0.vhd | 1 | 4,439 | -- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: lpm_add_sub0.vhd
-- Megafunction Name(s):
-- lpm_add_sub
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_add_sub0 IS
PORT
(
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END lpm_add_sub0;
ARCHITECTURE SYN OF lpm_add_sub0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1_bv : BIT_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1_bv(31 DOWNTO 0) <= "00000000000000000000000000010100";
sub_wire1 <= To_stdlogicvector(sub_wire1_bv);
result <= sub_wire0(31 DOWNTO 0);
lpm_add_sub_component : lpm_add_sub
GENERIC MAP (
lpm_direction => "SUB",
lpm_hint => "ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO",
lpm_type => "LPM_ADD_SUB",
lpm_width => 32
)
PORT MAP (
dataa => sub_wire1,
datab => datab,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "20"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: Function NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "1"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "1"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "SUB"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL datab[31..0]
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: CONNECT: @dataa 0 0 32 0 20 0 0 0 0
-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0_inst.vhd TRUE
| gpl-2.0 | 972b366cdda69f6e957decaaf82b2a41 | 0.656229 | 3.600162 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_sim/ext_mem_test_v6_tb.vhd | 5 | 7,362 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.vital_timing.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_test_v6_tb is
end ext_mem_test_v6_tb;
architecture tb of ext_mem_test_v6_tb is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp : t_mem_burst_16_resp;
signal okay : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal logic_A : std_logic_vector(12 downto 0);
signal logic_BA : std_logic_vector(1 downto 0);
signal dummy_data : std_logic_vector(15 downto 0) := (others => 'H');
signal dummy_dqm : std_logic_vector(1 downto 0) := (others => 'H');
constant c_wire_delay : VitalDelayType01 := ( 2 ns, 3 ns );
begin
clock <= not clock after 10.2 ns;
clk_2x <= not clk_2x after 5.1 ns;
reset <= '1', '0' after 100 ns;
i_checker: entity work.ext_mem_test_v6
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
okay => okay );
i_mut: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => true )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
SDRAM_BA => logic_BA,
SDRAM_A => logic_A,
SDRAM_DQ => MEM_D );
i_sdram : entity work.mt48lc16m16a2
generic map(
tipd_BA0 => c_wire_delay,
tipd_BA1 => c_wire_delay,
tipd_DQMH => c_wire_delay,
tipd_DQML => c_wire_delay,
tipd_DQ0 => c_wire_delay,
tipd_DQ1 => c_wire_delay,
tipd_DQ2 => c_wire_delay,
tipd_DQ3 => c_wire_delay,
tipd_DQ4 => c_wire_delay,
tipd_DQ5 => c_wire_delay,
tipd_DQ6 => c_wire_delay,
tipd_DQ7 => c_wire_delay,
tipd_DQ8 => c_wire_delay,
tipd_DQ9 => c_wire_delay,
tipd_DQ10 => c_wire_delay,
tipd_DQ11 => c_wire_delay,
tipd_DQ12 => c_wire_delay,
tipd_DQ13 => c_wire_delay,
tipd_DQ14 => c_wire_delay,
tipd_DQ15 => c_wire_delay,
tipd_CLK => c_wire_delay,
tipd_CKE => c_wire_delay,
tipd_A0 => c_wire_delay,
tipd_A1 => c_wire_delay,
tipd_A2 => c_wire_delay,
tipd_A3 => c_wire_delay,
tipd_A4 => c_wire_delay,
tipd_A5 => c_wire_delay,
tipd_A6 => c_wire_delay,
tipd_A7 => c_wire_delay,
tipd_A8 => c_wire_delay,
tipd_A9 => c_wire_delay,
tipd_A10 => c_wire_delay,
tipd_A11 => c_wire_delay,
tipd_A12 => c_wire_delay,
tipd_WENeg => c_wire_delay,
tipd_RASNeg => c_wire_delay,
tipd_CSNeg => c_wire_delay,
tipd_CASNeg => c_wire_delay,
-- tpd delays
tpd_CLK_DQ2 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
tpd_CLK_DQ3 => ( 4 ns, 4 ns, 4 ns, 4 ns, 4 ns, 4 ns ),
-- -- tpw values: pulse widths
-- tpw_CLK_posedge : VitalDelayType := UnitDelay;
-- tpw_CLK_negedge : VitalDelayType := UnitDelay;
-- -- tsetup values: setup times
-- tsetup_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- thold values: hold times
-- thold_DQ0_CLK : VitalDelayType := UnitDelay;
-- -- tperiod_min: minimum clock period = 1/max freq
-- tperiod_CLK_posedge : VitalDelayType := UnitDelay;
--
mem_file_name => "none",
tpowerup => 100 ns )
port map(
BA0 => logic_BA(0),
BA1 => logic_BA(1),
DQMH => dummy_dqm(1),
DQML => logic_DQM,
DQ0 => MEM_D(0),
DQ1 => MEM_D(1),
DQ2 => MEM_D(2),
DQ3 => MEM_D(3),
DQ4 => MEM_D(4),
DQ5 => MEM_D(5),
DQ6 => MEM_D(6),
DQ7 => MEM_D(7),
DQ8 => dummy_data(8),
DQ9 => dummy_data(9),
DQ10 => dummy_data(10),
DQ11 => dummy_data(11),
DQ12 => dummy_data(12),
DQ13 => dummy_data(13),
DQ14 => dummy_data(14),
DQ15 => dummy_data(15),
CLK => logic_CLK,
CKE => logic_CKE,
A0 => logic_A(0),
A1 => logic_A(1),
A2 => logic_A(2),
A3 => logic_A(3),
A4 => logic_A(4),
A5 => logic_A(5),
A6 => logic_A(6),
A7 => logic_A(7),
A8 => logic_A(8),
A9 => logic_A(9),
A10 => logic_A(10),
A11 => logic_A(11),
A12 => logic_A(12),
WENeg => logic_WEn,
RASNeg => logic_RASn,
CSNeg => logic_CSn,
CASNeg => logic_CASn );
end;
| gpl-3.0 | d823bedc4c5d81169d152e31e2cb8236 | 0.420266 | 3.556522 | false | false | false | false |
KB777/1541UltimateII | fpga/cart_slot/vhdl_source/cart_slot_registers.vhd | 1 | 5,320 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.cart_slot_pkg.all;
entity cart_slot_registers is
generic (
g_rom_base : unsigned(27 downto 0) := X"0F80000";
g_ram_base : unsigned(27 downto 0) := X"0F70000";
g_ram_expansion : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_cart_control;
status : in t_cart_status );
end entity;
architecture rtl of cart_slot_registers is
signal control_i : t_cart_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
control_i.cartridge_kill <= '0';
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
if io_req.data(2)='1' then
control_i.c64_reset <= '1';
elsif io_req.data(3)='1' then
control_i.c64_reset <= '0';
else
control_i.c64_ultimax <= io_req.data(1);
control_i.c64_nmi <= io_req.data(4);
end if;
when c_cart_c64_stop =>
control_i.c64_stop <= io_req.data(0);
when c_cart_c64_stop_mode =>
control_i.c64_stop_mode <= io_req.data(1 downto 0);
when c_cart_cartridge_type =>
control_i.cartridge_type <= io_req.data(3 downto 0);
when c_cart_cartridge_kill =>
control_i.cartridge_kill <= '1';
when c_cart_kernal_enable =>
control_i.kernal_enable <= io_req.data(0);
when c_cart_reu_enable =>
control_i.reu_enable <= io_req.data(0);
when c_cart_reu_size =>
control_i.reu_size <= io_req.data(2 downto 0);
when c_cart_ethernet_enable =>
control_i.eth_enable <= io_req.data(0);
when c_cart_timing =>
control_i.timing_addr_valid <= unsigned(io_req.data(2 downto 0));
when c_cart_phi2_recover =>
control_i.phi2_edge_recover <= io_req.data(0);
control_i.tick_ntsc <= io_req.data(1);
when c_cart_swap_buttons =>
control_i.swap_buttons <= io_req.data(0);
when c_cart_sampler_enable =>
control_i.sampler_enable <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
io_resp.data(1) <= control_i.c64_ultimax;
io_resp.data(2) <= control_i.c64_reset;
io_resp.data(4) <= control_i.c64_nmi;
when c_cart_c64_stop =>
io_resp.data(0) <= control_i.c64_stop;
io_resp.data(1) <= status.c64_stopped;
when c_cart_c64_stop_mode =>
io_resp.data(1 downto 0) <= control_i.c64_stop_mode;
when c_cart_c64_clock_detect =>
io_resp.data(0) <= status.clock_detect;
when c_cart_cartridge_rom_base =>
io_resp.data <= std_logic_vector(g_rom_base(23 downto 16));
when c_cart_cartridge_type =>
io_resp.data(3 downto 0) <= control_i.cartridge_type;
when c_cart_cartridge_active =>
io_resp.data(0) <= status.cart_active;
when c_cart_kernal_enable =>
io_resp.data(0) <= control_i.kernal_enable;
when c_cart_reu_enable =>
io_resp.data(0) <= control_i.reu_enable;
when c_cart_reu_size =>
io_resp.data(2 downto 0) <= control_i.reu_size;
when c_cart_ethernet_enable =>
io_resp.data(0) <= control_i.eth_enable;
when c_cart_sampler_enable =>
io_resp.data(0) <= control_i.sampler_enable;
when c_cart_timing =>
io_resp.data(2 downto 0) <= std_logic_vector(control_i.timing_addr_valid);
when c_cart_phi2_recover =>
io_resp.data(0) <= control_i.phi2_edge_recover;
io_resp.data(1) <= control_i.tick_ntsc;
when c_cart_swap_buttons =>
io_resp.data(0) <= control_i.swap_buttons;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_cart_control_init;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 75ffe524f57c72f2426cd5443449c8be | 0.454887 | 3.60678 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_source/hf_noise.vhd | 3 | 3,289 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hf_noise is
generic (
g_hp_filter : boolean := true );
port (
clock : in std_logic;
enable : in std_logic;
reset : in std_logic;
q : out signed(15 downto 0) );
end entity;
architecture structural of hf_noise is
-- constant c_type : string := "Galois";
-- constant c_polynom : std_logic_vector := X"5D6DCB";
constant c_type : string := "Fibonacci";
constant c_polynom : std_logic_vector := X"E10000";
constant c_seed : std_logic_vector := X"000001";
signal raw_lfsr : std_logic_vector(c_polynom'length-1 downto 0);
signal noise : signed(15 downto 0);
signal hp : signed(15 downto 0);
begin
i_lfsr: entity work.noise_generator
generic map (
g_type => c_type,
g_polynom => c_polynom,
g_seed => c_seed )
port map (
clock => clock,
enable => enable,
reset => reset,
q => raw_lfsr );
-- Reordering the bits somehow randomly,
-- gives a better spectral distribution
-- in case of Galois (flat!)! In face of Fibonacci,
-- this reordering gives ~20dB dips at odd
-- locations, depending on the reorder choice.
noise(15) <= raw_lfsr(1);
noise(14) <= raw_lfsr(4);
noise(13) <= raw_lfsr(7);
noise(12) <= raw_lfsr(10);
noise(11) <= raw_lfsr(13);
noise(10) <= raw_lfsr(16);
noise(09) <= raw_lfsr(19);
noise(08) <= raw_lfsr(22);
noise(07) <= raw_lfsr(20);
noise(06) <= raw_lfsr(17);
noise(05) <= raw_lfsr(14);
noise(04) <= raw_lfsr(11);
noise(03) <= raw_lfsr(8);
noise(02) <= raw_lfsr(5);
noise(01) <= raw_lfsr(2);
noise(00) <= raw_lfsr(18);
-- taking an up-range or down range gives a reasonably
-- flat frequency response, but lacks low frequencies (~20 dB)
-- In case of our high-freq noise that we need, this is not
-- a bad thing, as our filter doesn't need to be so sharp.
-- Fibonacci gives less low frequency noise than Galois!
-- differences seen with 1st order filter below were 5-10dB in
-- our band of interest.
-- noise <= signed(raw_lfsr(20 downto 5));
r_hp: if g_hp_filter generate
signal hp_a : signed(15 downto 0);
begin
i_hp: entity work.high_pass
generic map (
g_width => 15 )
port map (
clock => clock,
enable => enable,
reset => reset,
x => noise(14 downto 0),
-- q => hp_a );
-- i_hp_b: entity work.high_pass
-- generic map (
-- g_width => 16 )
-- port map (
-- clock => clock,
-- reset => reset,
--
-- x => hp_a,
q => hp );
end generate;
q <= hp(15 downto 0) when g_hp_filter else noise;
end structural;
| gpl-3.0 | 20720e685c1370293dbbea8b28394654 | 0.48647 | 3.638274 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_source/io_to_dma_bridge.vhd | 4 | 1,937 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.dma_bus_pkg.all;
entity io_to_dma_bridge is
port (
clock : in std_logic;
reset : in std_logic;
c64_stopped : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
dma_req : out t_dma_req;
dma_resp : in t_dma_resp );
end entity;
architecture rtl of io_to_dma_bridge is
signal dma_rwn_i : std_logic;
begin
dma_req.address <= io_req.address(15 downto 0);
dma_req.read_writen <= dma_rwn_i;
dma_req.data <= io_req.data;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if dma_resp.rack='1' then
dma_req.request <= '0';
if dma_rwn_i='0' then -- was write
io_resp.ack <= '1';
end if;
end if;
if dma_resp.dack='1' then
io_resp.data <= dma_resp.data;
io_resp.ack <= '1';
end if;
if io_req.write='1' then
if c64_stopped='1' then
dma_req.request <= '1';
dma_rwn_i <= '0';
else
io_resp.ack <= '1';
end if;
elsif io_req.read='1' then
if c64_stopped='1' then
dma_req.request <= '1';
dma_rwn_i <= '1';
else
io_resp.ack <= '1';
end if;
end if;
if reset='1' then
dma_req.request <= '0';
dma_rwn_i <= '1';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 5095a5c0725f20a83e5db15e971a6d52 | 0.409912 | 3.661626 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op994_8.vhdl | 1 | 6,153 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net3
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net8
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net8,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net9,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net9
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 4faf1495fb8c9136bc97cf53bc7e0990 | 0.574516 | 3.088855 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/uart_lite/vhdl_sim/tb_tx.vhd | 5 | 2,109 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Testbench for Serial Transmitter: 115200/8N1
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-- Created : Wed Apr 28, 2004
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_tx is
end tb_tx;
architecture tb of tb_tx is
component tx is
port (
clk : in std_logic;
reset : in std_logic;
dotx : in std_logic;
txchar : in std_logic_vector(7 downto 0);
txd : out std_logic;
done : out std_logic );
end component;
signal clk : std_logic;
signal reset : std_logic;
signal dotx : std_logic;
signal txchar : character;
signal txd : std_logic;
signal done : std_logic;
constant teststring : string := "Gideon is gek";
begin
ck: process
begin
clk <= '0'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
end process;
test: process
begin
reset <= '1';
dotx <= '0';
txchar <= NUL; --StdToChar("00000000");
wait for 80 ns;
reset <= '0';
wait until clk='1';
for i in teststring'range loop
txchar <= teststring(i);
dotx <= '1';
wait until clk='1';
dotx <= '0';
wait until clk='1';
while done='0' loop
wait until clk='1';
end loop;
end loop;
wait;
end process;
my_tx: tx port map (
clk => clk,
reset => reset,
dotx => dotx,
txchar => txchar,
txd => txd,
done => done );
end tb;
| gpl-3.0 | f7e8a727a54cea7f7d1178a4d92430ce | 0.396871 | 4.44 | false | true | false | false |
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