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daringer/schemmaker | testdata/new/circuit_bi1_0op968_15.vhdl | 1 | 5,465 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net3
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net4
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net7
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net7,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net8,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 536be3d8f7bbf2db7f7516b7e37ce9ee | 0.578225 | 3.146229 | false | false | false | false |
KB777/1541UltimateII | fpga/cpu_unit/mblite/hw/core/fetch.vhd | 1 | 2,738 | ----------------------------------------------------------------------------------------------
--
-- Input file : fetch.vhd
-- Design name : fetch
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : Instruction Fetch Stage inserts instruction into the pipeline. It
-- uses a single port Random Access Memory component which holds
-- the instructions. The next instruction is computed in the decode
-- stage.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity fetch is port
(
fetch_o : out fetch_out_type;
imem_o : out imem_out_type;
fetch_i : in fetch_in_type;
imem_i : in imem_in_type;
rst_i : in std_logic;
ena_i : in std_logic;
clk_i : in std_logic
);
end fetch;
architecture arch of fetch is
signal r, rin : fetch_out_type;
signal rst_d : std_logic;
signal ena_o : std_logic;
signal possibly_valid : std_logic;
begin
fetch_o.program_counter <= r.program_counter;
fetch_o.instruction <= imem_i.dat_i;
fetch_o.inst_valid <= possibly_valid and imem_i.ena_i;
ena_o <= ena_i and imem_i.ena_i;
imem_o.adr_o <= rin.program_counter;
imem_o.ena_o <= ena_o;
fetch_comb: process(fetch_i, imem_i, r, rst_d)
variable v : fetch_out_type;
begin
v := r;
if rst_d = '1' then
v.program_counter := (OTHERS => '0');
elsif fetch_i.hazard = '1' or imem_i.ena_i = '0' then
v.program_counter := r.program_counter;
elsif fetch_i.branch = '1' then
v.program_counter := fetch_i.branch_target;
else
v.program_counter := increment(r.program_counter(CFG_IMEM_SIZE - 1 downto 2)) & "00";
end if;
rin <= v;
end process;
fetch_seq: process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
r.program_counter <= (others => '0');
rst_d <= '1';
possibly_valid <= '0';
elsif ena_i = '1' then
r <= rin;
rst_d <= '0';
if imem_i.ena_i = '1' then
possibly_valid <= ena_o;
end if;
end if;
end if;
end process;
end arch; | gpl-3.0 | 35652a7ff99abcc26860e3ea7a2973c2 | 0.489774 | 3.792244 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cpu_unit/vhdl_source/mem4k.vhd | 5 | 2,199 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem4k is
generic (
simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
address : in std_logic_vector(26 downto 0);
request : in std_logic;
mwrite : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
rack : out std_logic;
dack : out std_logic;
claimed : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of mem4k : entity is "yes";
end mem4k;
architecture gideon of mem4k is
subtype t_byte is std_logic_vector(7 downto 0);
type t_byte_array is array(natural range <>) of t_byte;
shared variable my_mem : t_byte_array(0 to 4095);
signal claimed_i : std_logic;
signal do_write : std_logic;
-- attribute ram_style : string;
-- attribute ram_style of my_mem : signal is "block";
begin
claimed_i <= '1' when address(26 downto 12) = "000000000000000"
else '0';
claimed <= claimed_i;
rack <= claimed_i and request;
do_write <= claimed_i and request and mwrite;
-- synthesis translate_off
model: if simulation generate
mram: entity work.bram_model_8sp
generic map("intram", 12) -- 4k
port map (
CLK => clock,
SSR => reset,
EN => request,
WE => do_write,
ADDR => address(11 downto 0),
DI => wdata,
DO => rdata );
end generate;
-- synthesis translate_on
process(clock)
begin
if rising_edge(clock) then
if do_write='1' then
my_mem(to_integer(unsigned(address(11 downto 0)))) := wdata;
end if;
if not simulation then
rdata <= my_mem(to_integer(unsigned(address(11 downto 0))));
else
rdata <= (others => 'Z');
end if;
dack <= claimed_i and request;
end if;
end process;
end gideon;
| gpl-3.0 | f766057d2879ca63e695daec7cc80293 | 0.53297 | 3.689597 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_sim/noise_generator_tb.vhd | 5 | 4,260 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.tl_string_util_pkg.all;
entity noise_generator_tb is
end;
architecture tb of noise_generator_tb is
constant c_type : string := "Fibonacci";
-- constant c_polynom : std_logic_vector := X"E10000";
constant c_polynom : std_logic_vector := "11100100000000000000000";
signal polynom : std_logic_vector(22 downto 0) := c_polynom;
-- constant c_type : string := "Galois";
-- constant c_polynom : std_logic_vector := X"5D6DCB";
-- constant c_seed : std_logic_vector := X"000001";
constant c_seed : std_logic_vector := "11111111111111111111111";
signal clock : std_logic := '0';
signal reset : std_logic;
signal q : std_logic_vector(c_polynom'length-1 downto 0);
signal selected_bits : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
--reset <= '1', '0' after 100 ns;
i_lfsr: entity work.noise_generator
generic map (
g_type => c_type,
g_polynom => c_polynom,
g_fixed_polynom => false,
g_seed => c_seed )
port map (
clock => clock,
reset => reset,
enable => '1',
polynom => polynom,
q => q );
selected_bits(7) <= q(22);
selected_bits(6) <= q(20);
selected_bits(5) <= q(16);
selected_bits(4) <= q(13);
selected_bits(3) <= q(11);
selected_bits(2) <= q(7);
selected_bits(1) <= q(4);
selected_bits(0) <= q(2);
p_test: process
variable poly : std_logic_vector(7 downto 0);
variable count : integer;
function count_bits(p : std_logic_vector) return integer is
variable c : integer;
begin
c := 0;
for i in p'range loop
if p(i)='1' then
c := c + 1;
end if;
end loop;
return c;
end function;
procedure perform_test is
begin
reset <= '1';
wait until clock='1';
wait until clock='1';
wait until clock='1';
reset <= '0';
wait until clock='1';
wait until clock='1';
count := 1;
while q /= c_seed loop
wait until clock='1';
count := count + 1;
end loop;
report "Polynom = " & hstr(polynom) & ". Length of LFSR = " & integer'image(count) severity note;
end procedure;
begin
reset <= '0';
for i in 0 to 255 loop -- test 256 different polynoms, at least; ones that result in an even number of bits set
poly := std_logic_vector(to_unsigned(i, 8));
if(count_bits(poly) mod 2) = 1 then
polynom <= "1" & poly & "00000000000000";
perform_test;
end if;
end loop;
wait;
end process;
-- assert count=0 or q/=c_seed
-- report "Length of LFSR = " & integer'image(count)
-- severity failure;
-- count := count + 1;
-- end if;
-- end if;
-- end process;
--
end tb;
-- FF 11111111111111111111111
-- FF 11111111111111111111110
-- FF 11111111111111111111100
-- FE 11111111111111111111000 2
-- FE 11111111111111111110000
-- FC 11111111111111111100000 4
-- FC 11111111111111111000000
-- FC 11111111111111110000000
-- F8 11111111111111100000000 7
-- F8 11111111111111000000000
-- F8 11111111111110000000000
-- F8 11111111111100000000000
-- F0 11111111111000000000000 11
-- F0 11111111110000000000000
-- E0 11111111100000000000000 13
-- E0 11111111000000000000000
-- E0 11111110000000000000000
-- C0 11111100000000000000000 16
-- C0 1111100000000000000000-
-- C0 11110000000000000000001
-- C0 1110000000000000000001-
-- 81 110000000000000000001-- 20
-- 81 10000000000000000001---
-- 03 000000000000000000----- 22
-- 03
-- 06
-- 06
-- 06
--
--
-- | gpl-3.0 | 97278a97683675ca9dda80538447d194 | 0.527465 | 3.824057 | false | false | false | false |
multiple1902/xjtu_comp-org-lab | brainfuck-machine/implementation/bfp_tb.vhdl | 1 | 9,152 | -- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use std.textio.all;
entity bfp_tb is
end bfp_tb;
architecture behav of bfp_tb is
subtype bfp_instruction is std_logic_vector(2 downto 0);
subtype bfp_data is std_logic_vector(7 downto 0);
component bfp
port (ins_in : in bfp_instruction;
data_in : in bfp_data;
clk : in std_logic;
data_out: out bfp_data;
halt : out std_logic -- no semicolon here!
);
end component;
for bfp_0: bfp use entity work.bfp;
signal ins_in : bfp_instruction;
signal data_in : bfp_data;
signal clk : std_logic;
signal data_out: bfp_data;
signal halt : std_logic;
begin
bfp_0: bfp port map (ins_in => ins_in,
data_in => data_in,
clk => clk,
data_out => data_out,
halt => halt
);
process
variable l: line;
variable counter: integer := 0;
type op_array is array (natural range <>) of bfp_instruction;
constant ops : op_array :=
(
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"100",
"000",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"000",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"000",
"010",
"010",
"010",
"000",
"010",
"001",
"001",
"001",
"001",
"011",
"101",
"000",
"010",
"010",
"110",
"000",
"010",
"110",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"110",
"110",
"010",
"010",
"010",
"110",
"000",
"010",
"010",
"110",
"001",
"001",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"010",
"110",
"000",
"110",
"010",
"010",
"010",
"110",
"011",
"011",
"011",
"011",
"011",
"011",
"110",
"011",
"011",
"011",
"011",
"011",
"011",
"011",
"011",
"110",
"000",
"010",
"110",
"000",
"110"
);
begin
for i in ops'range loop
-- write(l, String'("loop"));
-- writeline(output, l);
clk <= '0';
wait for 1 ns;
ins_in <= ops(i);
clk <= '1';
wait for 10 ms;
end loop;
clk <= '0';
wait for 1 ns;
ins_in <= "ZZZ";
clk <= '1';
wait for 10 ms;
while halt='0' loop
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 10 ms;
if ieee.std_logic_1164."/="(data_out,"ZZZZZZZZ") then
case conv_integer(data_out) is
when 97=>
write(l, string'("a"));
when 98=>
write(l, string'("b"));
when 99=>
write(l, string'("c"));
when 100=>
write(l, string'("d"));
when 101=>
write(l, string'("e"));
when 102=>
write(l, string'("f"));
when 103=>
write(l, string'("g"));
when 104=>
write(l, string'("h"));
when 105=>
write(l, string'("i"));
when 106=>
write(l, string'("j"));
when 107=>
write(l, string'("k"));
when 108=>
write(l, string'("l"));
when 109=>
write(l, string'("m"));
when 110=>
write(l, string'("n"));
when 111=>
write(l, string'("o"));
when 112=>
write(l, string'("p"));
when 113=>
write(l, string'("q"));
when 114=>
write(l, string'("r"));
when 115=>
write(l, string'("s"));
when 116=>
write(l, string'("t"));
when 117=>
write(l, string'("u"));
when 118=>
write(l, string'("v"));
when 119=>
write(l, string'("w"));
when 120=>
write(l, string'("x"));
when 121=>
write(l, string'("y"));
when 122=>
write(l, string'("z"));
when 65=>
write(l, string'("A"));
when 66=>
write(l, string'("B"));
when 67=>
write(l, string'("C"));
when 68=>
write(l, string'("D"));
when 69=>
write(l, string'("E"));
when 70=>
write(l, string'("F"));
when 71=>
write(l, string'("G"));
when 72=>
write(l, string'("H"));
when 73=>
write(l, string'("I"));
when 74=>
write(l, string'("J"));
when 75=>
write(l, string'("K"));
when 76=>
write(l, string'("L"));
when 77=>
write(l, string'("M"));
when 78=>
write(l, string'("N"));
when 79=>
write(l, string'("O"));
when 80=>
write(l, string'("P"));
when 81=>
write(l, string'("Q"));
when 82=>
write(l, string'("R"));
when 83=>
write(l, string'("S"));
when 84=>
write(l, string'("T"));
when 85=>
write(l, string'("U"));
when 86=>
write(l, string'("V"));
when 87=>
write(l, string'("W"));
when 88=>
write(l, string'("X"));
when 89=>
write(l, string'("Y"));
when 90=>
write(l, string'("Z"));
when 48=>
write(l, string'("0"));
when 49=>
write(l, string'("1"));
when 50=>
write(l, string'("2"));
when 51=>
write(l, string'("3"));
when 52=>
write(l, string'("4"));
when 53=>
write(l, string'("5"));
when 54=>
write(l, string'("6"));
when 55=>
write(l, string'("7"));
when 56=>
write(l, string'("8"));
when 57=>
write(l, string'("9"));
when others =>
write(l, string'(" "));
end case;
end if;
end loop;
writeline(output, l);
wait;
end process;
end behav;
| gpl-3.0 | 303b437d995137f523a902bb84e55561 | 0.282452 | 5.017544 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op952_7.vhdl | 2 | 4,590 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 1a718f745d50c1f0f2b162f56b9cdc72 | 0.58061 | 3.20307 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/zpu/core/zpu_core.vhd | 2 | 26,231 |
-- Company: ZPU4 generic memory interface CPU
-- Engineer: Øyvind Harboe
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_arith.ALL;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
entity zpu_core is
Port ( clk : in std_logic;
areset : in std_logic;
enable : in std_logic;
mem_req : out std_logic;
mem_we : out std_logic;
mem_ack : in std_logic;
mem_read : in std_logic_vector(wordSize-1 downto 0);
mem_write : out std_logic_vector(wordSize-1 downto 0);
out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
interrupt : in std_logic;
break : out std_logic;
zpu_status : out std_logic_vector(63 downto 0));
end zpu_core;
architecture behave of zpu_core is
type InsnType is
(
State_AddTop,
State_Dup,
State_DupStackB,
State_Pop,
State_Popdown,
State_Add,
State_Or,
State_And,
State_Store,
State_AddSP,
State_Shift,
State_Nop,
State_Im,
State_LoadSP,
State_StoreSP,
State_Emulate,
State_Load,
State_PushPC,
State_PushSP,
State_PopPC,
State_PopPCRel,
State_Not,
State_Flip,
State_PopSP,
State_Neqbranch,
State_Eq,
State_Loadb,
State_Mult,
State_Lessthan,
State_Lessthanorequal,
State_Ulessthanorequal,
State_Ulessthan,
State_Pushspadd,
State_Call,
State_Callpcrel,
State_Sub,
State_Break,
State_Storeb,
State_Interrupt,
State_InsnFetch
);
type StateType is
(
State_Idle, -- using first state first on the list out of paranoia
State_Load2,
State_Popped,
State_LoadSP2,
State_LoadSP3,
State_AddSP2,
State_Fetch,
State_Execute,
State_Decode,
State_Decode2,
State_Resync,
State_StoreSP2,
State_Resync2,
State_Resync3,
State_Loadb2,
State_Storeb2,
State_Mult2,
State_Mult3,
State_Mult5,
State_Mult6,
State_Mult4,
State_BinaryOpResult
);
signal pc : std_logic_vector(maxAddrBitIncIO downto 0);
signal sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal incSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal incIncSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal decSp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal stackA : std_logic_vector(wordSize-1 downto 0);
signal binaryOpResult : std_logic_vector(wordSize-1 downto 0);
signal multResult2 : std_logic_vector(wordSize-1 downto 0);
signal multResult3 : std_logic_vector(wordSize-1 downto 0);
signal multResult : std_logic_vector(wordSize-1 downto 0);
signal multA : std_logic_vector(wordSize-1 downto 0);
signal multB : std_logic_vector(wordSize-1 downto 0);
signal stackB : std_logic_vector(wordSize-1 downto 0);
signal idim_flag : std_logic;
signal busy : std_logic;
signal mem_readEnable : std_logic;
signal mem_addr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal mem_delayAddr : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal mem_delayReadEnable : std_logic;
signal mem_busy : std_logic;
signal decodeWord : std_logic_vector(wordSize-1 downto 0);
signal state : StateType;
signal insn : InsnType;
type InsnArray is array(0 to wordBytes-1) of InsnType;
signal decodedOpcode : InsnArray;
type OpcodeArray is array(0 to wordBytes-1) of std_logic_vector(7 downto 0);
signal opcode : OpcodeArray;
signal begin_inst : std_logic;
signal trace_opcode : std_logic_vector(7 downto 0);
signal trace_pc : std_logic_vector(maxAddrBitIncIO downto 0);
signal trace_sp : std_logic_vector(maxAddrBitIncIO downto minAddrBit);
signal trace_topOfStack : std_logic_vector(wordSize-1 downto 0);
signal trace_topOfStackB : std_logic_vector(wordSize-1 downto 0);
signal out_mem_req : std_logic;
signal inInterrupt : std_logic;
-- state machine.
begin
zpu_status(maxAddrBitIncIO downto 0) <= trace_pc;
zpu_status(31) <= '1';
zpu_status(39 downto 32) <= trace_opcode;
zpu_status(40) <= '1' when (state = State_Idle) else '0';
zpu_status(62) <= '1';
traceFileGenerate:
if Generate_Trace generate
trace_file: trace port map (
clk => clk,
begin_inst => begin_inst,
pc => trace_pc,
opcode => trace_opcode,
sp => trace_sp,
memA => trace_topOfStack,
memB => trace_topOfStackB,
busy => busy,
intsp => (others => 'U')
);
end generate;
-- the memory subsystem will tell us one cycle later whether or
-- not it is busy
out_mem_addr(maxAddrBitIncIO downto minAddrBit) <= mem_addr;
out_mem_addr(minAddrBit-1 downto 0) <= (others => '0');
mem_req <= out_mem_req;
incSp <= sp + 1;
incIncSp <= sp + 2;
decSp <= sp - 1;
mem_busy <= out_mem_req and not mem_ack; -- '1' when the memory is busy
opcodeControl:
process(clk, areset)
variable tOpcode : std_logic_vector(OpCode_Size-1 downto 0);
variable spOffset : std_logic_vector(4 downto 0);
variable tSpOffset : std_logic_vector(4 downto 0);
variable nextPC : std_logic_vector(maxAddrBitIncIO downto 0);
variable tNextState : InsnType;
variable tDecodedOpcode : InsnArray;
variable tMultResult : std_logic_vector(wordSize*2-1 downto 0);
begin
if areset = '1' then
state <= State_Idle;
break <= '0';
sp <= spStart(maxAddrBitIncIO downto minAddrBit);
pc <= (others => '0');
idim_flag <= '0';
begin_inst <= '0';
mem_we <= '0';
multA <= (others => '0');
multB <= (others => '0');
mem_writeMask <= (others => '1');
out_mem_req <= '0';
mem_addr <= (others => DontCareValue);
mem_write <= (others => DontCareValue);
inInterrupt <= '0';
elsif (clk'event and clk = '1') then
-- we must multiply unconditionally to get pipelined multiplication
tMultResult := multA * multB;
multResult3 <= multResult2;
multResult2 <= multResult;
multResult <= tMultResult(wordSize-1 downto 0);
spOffset(4):=not opcode(conv_integer(pc(byteBits-1 downto 0)))(4);
spOffset(3 downto 0):=opcode(conv_integer(pc(byteBits-1 downto 0)))(3 downto 0);
nextPC := pc + 1;
-- prepare trace snapshot
trace_opcode <= opcode(conv_integer(pc(byteBits-1 downto 0)));
trace_pc <= pc;
trace_sp <= sp;
trace_topOfStack <= stackA;
trace_topOfStackB <= stackB;
begin_inst <= '0';
-- we terminate the requeset as soon as we get acknowledge
if mem_ack = '1' then
out_mem_req <= '0';
mem_we <= '0';
end if;
if interrupt='0' then
inInterrupt <= '0'; -- no longer in an interrupt
end if;
case state is
when State_Idle =>
if enable='1' then
state <= State_Resync;
end if;
-- Initial state of ZPU, fetch top of stack + first instruction
when State_Resync =>
if mem_busy='0' then
mem_addr <= sp;
out_mem_req <= '1';
state <= State_Resync2;
end if;
when State_Resync2 =>
if mem_busy='0' then
stackA <= mem_read;
mem_addr <= incSp;
out_mem_req <= '1';
state <= State_Resync3;
end if;
when State_Resync3 =>
if mem_busy='0' then
stackB <= mem_read;
mem_addr <= pc(maxAddrBitIncIO downto minAddrBit);
out_mem_req <= '1';
state <= State_Decode;
end if;
when State_Decode =>
if mem_busy='0' then
decodeWord <= mem_read;
state <= State_Decode2;
end if;
when State_Decode2 =>
-- decode 4 instructions in parallel
for i in 0 to wordBytes-1 loop
tOpcode := decodeWord((wordBytes-1-i+1)*8-1 downto (wordBytes-1-i)*8);
tSpOffset(4):=not tOpcode(4);
tSpOffset(3 downto 0):=tOpcode(3 downto 0);
opcode(i) <= tOpcode;
if (tOpcode(7 downto 7)=OpCode_Im) then
tNextState:=State_Im;
elsif (tOpcode(7 downto 5)=OpCode_StoreSP) then
if tSpOffset = 0 then
tNextState := State_Pop;
elsif tSpOffset=1 then
tNextState := State_PopDown;
else
tNextState :=State_StoreSP;
end if;
elsif (tOpcode(7 downto 5)=OpCode_LoadSP) then
if tSpOffset = 0 then
tNextState :=State_Dup;
elsif tSpOffset = 1 then
tNextState :=State_DupStackB;
else
tNextState :=State_LoadSP;
end if;
elsif (tOpcode(7 downto 5)=OpCode_Emulate) then
tNextState :=State_Emulate;
if tOpcode(5 downto 0)=OpCode_Neqbranch then
tNextState :=State_Neqbranch;
elsif tOpcode(5 downto 0)=OpCode_Eq then
tNextState :=State_Eq;
elsif tOpcode(5 downto 0)=OpCode_Lessthan then
tNextState :=State_Lessthan;
elsif tOpcode(5 downto 0)=OpCode_Lessthanorequal then
--tNextState :=State_Lessthanorequal;
elsif tOpcode(5 downto 0)=OpCode_Ulessthan then
tNextState :=State_Ulessthan;
elsif tOpcode(5 downto 0)=OpCode_Ulessthanorequal then
--tNextState :=State_Ulessthanorequal;
elsif tOpcode(5 downto 0)=OpCode_Loadb then
tNextState :=State_Loadb;
elsif tOpcode(5 downto 0)=OpCode_Mult then
tNextState :=State_Mult;
elsif tOpcode(5 downto 0)=OpCode_Storeb then
tNextState :=State_Storeb;
elsif tOpcode(5 downto 0)=OpCode_Pushspadd then
tNextState :=State_Pushspadd;
elsif tOpcode(5 downto 0)=OpCode_Callpcrel then
tNextState :=State_Callpcrel;
elsif tOpcode(5 downto 0)=OpCode_Call then
--tNextState :=State_Call;
elsif tOpcode(5 downto 0)=OpCode_Sub then
tNextState :=State_Sub;
elsif tOpcode(5 downto 0)=OpCode_PopPCRel then
--tNextState :=State_PopPCRel;
end if;
elsif (tOpcode(7 downto 4)=OpCode_AddSP) then
if tSpOffset = 0 then
tNextState := State_Shift;
elsif tSpOffset = 1 then
tNextState := State_AddTop;
else
tNextState :=State_AddSP;
end if;
else
case tOpcode(3 downto 0) is
when OpCode_Nop =>
tNextState :=State_Nop;
when OpCode_PushSP =>
tNextState :=State_PushSP;
when OpCode_PopPC =>
tNextState :=State_PopPC;
when OpCode_Add =>
tNextState :=State_Add;
when OpCode_Or =>
tNextState :=State_Or;
when OpCode_And =>
tNextState :=State_And;
when OpCode_Load =>
tNextState :=State_Load;
when OpCode_Not =>
tNextState :=State_Not;
when OpCode_Flip =>
tNextState :=State_Flip;
when OpCode_Store =>
tNextState :=State_Store;
when OpCode_PopSP =>
tNextState :=State_PopSP;
when others =>
tNextState := State_Break;
end case;
end if;
tDecodedOpcode(i) := tNextState;
end loop;
insn <= tDecodedOpcode(conv_integer(pc(byteBits-1 downto 0)));
-- once we wrap, we need to fetch
tDecodedOpcode(0) := State_InsnFetch;
decodedOpcode <= tDecodedOpcode;
state <= State_Execute;
-- Each instruction must:
--
-- 1. set idim_flag
-- 2. increase pc if applicable
-- 3. set next state if appliable
-- 4. do it's operation
when State_Execute =>
insn <= decodedOpcode(conv_integer(nextPC(byteBits-1 downto 0)));
case insn is
when State_InsnFetch =>
state <= State_Fetch;
when State_Im =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '1';
pc <= pc + 1;
if idim_flag='1' then
stackA(wordSize-1 downto 7) <= stackA(wordSize-8 downto 0);
stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0);
else
out_mem_req <= '1';
mem_we <= '1';
mem_addr <= incSp;
mem_write <= stackB;
stackB <= stackA;
sp <= decSp;
for i in wordSize-1 downto 7 loop
stackA(i) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6);
end loop;
stackA(6 downto 0) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(6 downto 0);
end if;
else
insn <= insn;
end if;
when State_StoreSP =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
state <= State_StoreSP2;
out_mem_req <= '1';
mem_we <= '1';
mem_addr <= sp+spOffset;
mem_write <= stackA;
stackA <= stackB;
sp <= incSp;
else
insn <= insn;
end if;
when State_LoadSP =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
state <= State_LoadSP2;
sp <= decSp;
out_mem_req <= '1';
mem_we <= '1';
mem_addr <= incSp;
mem_write <= stackB;
else
insn <= insn;
end if;
when State_Emulate =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
sp <= decSp;
out_mem_req <= '1';
mem_we <= '1';
mem_addr <= incSp;
mem_write <= stackB;
stackA <= (others => DontCareValue);
stackA(maxAddrBitIncIO downto 0) <= pc + 1;
stackB <= stackA;
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc <= (others => '0');
pc(9 downto 5) <= opcode(conv_integer(pc(byteBits-1 downto 0)))(4 downto 0);
state <= State_Fetch;
else
insn <= insn;
end if;
when State_Callpcrel =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
stackA <= (others => DontCareValue);
stackA(maxAddrBitIncIO downto 0) <= pc + 1;
pc <= pc + stackA(maxAddrBitIncIO downto 0);
state <= State_Fetch;
else
insn <= insn;
end if;
when State_Call =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
stackA <= (others => DontCareValue);
stackA(maxAddrBitIncIO downto 0) <= pc + 1;
pc <= stackA(maxAddrBitIncIO downto 0);
state <= State_Fetch;
else
insn <= insn;
end if;
when State_AddSP =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
state <= State_AddSP2;
out_mem_req <= '1';
mem_addr <= sp+spOffset;
else
insn <= insn;
end if;
when State_PushSP =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
pc <= pc + 1;
sp <= decSp;
stackA <= (others => '0');
stackA(maxAddrBitIncIO downto minAddrBit) <= sp;
stackB <= stackA;
out_mem_req <= '1';
mem_we <= '1';
mem_addr <= incSp;
mem_write <= stackB;
else
insn <= insn;
end if;
when State_PopPC =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
pc <= stackA(maxAddrBitIncIO downto 0);
sp <= incSp;
out_mem_req <= '1';
mem_we <= '1';
mem_addr <= incSp;
mem_write <= stackB;
state <= State_Resync;
else
insn <= insn;
end if;
when State_PopPCRel =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
pc <= stackA(maxAddrBitIncIO downto 0) + pc;
sp <= incSp;
out_mem_req <= '1';
mem_we <= '1';
mem_addr <= incSp;
mem_write <= stackB;
state <= State_Resync;
else
insn <= insn;
end if;
when State_Add =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
stackA <= stackA + stackB;
out_mem_req <= '1';
mem_addr <= incIncSp;
sp <= incSp;
state <= State_Popped;
else
insn <= insn;
end if;
when State_Sub =>
begin_inst <= '1';
idim_flag <= '0';
binaryOpResult <= stackB - stackA;
state <= State_BinaryOpResult;
when State_Pop =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
mem_addr <= incIncSp;
out_mem_req <= '1';
sp <= incSp;
stackA <= stackB;
state <= State_Popped;
else
insn <= insn;
end if;
when State_PopDown =>
if mem_busy='0' then
-- PopDown leaves top of stack unchanged
begin_inst <= '1';
idim_flag <= '0';
mem_addr <= incIncSp;
out_mem_req <= '1';
sp <= incSp;
state <= State_Popped;
else
insn <= insn;
end if;
when State_Or =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
stackA <= stackA or stackB;
out_mem_req <= '1';
mem_addr <= incIncSp;
sp <= incSp;
state <= State_Popped;
else
insn <= insn;
end if;
when State_And =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
stackA <= stackA and stackB;
out_mem_req <= '1';
mem_addr <= incIncSp;
sp <= incSp;
state <= State_Popped;
else
insn <= insn;
end if;
when State_Eq =>
begin_inst <= '1';
idim_flag <= '0';
binaryOpResult <= (others => '0');
if (stackA=stackB) then
binaryOpResult(0) <= '1';
end if;
state <= State_BinaryOpResult;
when State_Ulessthan =>
begin_inst <= '1';
idim_flag <= '0';
binaryOpResult <= (others => '0');
if (stackA<stackB) then
binaryOpResult(0) <= '1';
end if;
state <= State_BinaryOpResult;
when State_Ulessthanorequal =>
begin_inst <= '1';
idim_flag <= '0';
binaryOpResult <= (others => '0');
if (stackA<=stackB) then
binaryOpResult(0) <= '1';
end if;
state <= State_BinaryOpResult;
when State_Lessthan =>
begin_inst <= '1';
idim_flag <= '0';
binaryOpResult <= (others => '0');
if (signed(stackA)<signed(stackB)) then
binaryOpResult(0) <= '1';
end if;
state <= State_BinaryOpResult;
when State_Lessthanorequal =>
begin_inst <= '1';
idim_flag <= '0';
binaryOpResult <= (others => '0');
if (signed(stackA)<=signed(stackB)) then
binaryOpResult(0) <= '1';
end if;
state <= State_BinaryOpResult;
when State_Load =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
state <= State_Load2;
mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
out_mem_req <= '1';
else
insn <= insn;
end if;
when State_Dup =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
pc <= pc + 1;
sp <= decSp;
stackB <= stackA;
mem_write <= stackB;
mem_addr <= incSp;
out_mem_req <= '1';
mem_we <= '1';
else
insn <= insn;
end if;
when State_DupStackB =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
pc <= pc + 1;
sp <= decSp;
stackA <= stackB;
stackB <= stackA;
mem_write <= stackB;
mem_addr <= incSp;
out_mem_req <= '1';
mem_we <= '1';
else
insn <= insn;
end if;
when State_Store =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
pc <= pc + 1;
mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
mem_write <= stackB;
out_mem_req <= '1';
mem_we <= '1';
sp <= incIncSp;
state <= State_Resync;
else
insn <= insn;
end if;
when State_PopSP =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
pc <= pc + 1;
mem_write <= stackB;
mem_addr <= incSp;
out_mem_req <= '1';
mem_we <= '1';
sp <= stackA(maxAddrBitIncIO downto minAddrBit);
state <= State_Resync;
else
insn <= insn;
end if;
when State_Nop =>
begin_inst <= '1';
idim_flag <= '0';
pc <= pc + 1;
when State_Not =>
begin_inst <= '1';
idim_flag <= '0';
pc <= pc + 1;
stackA <= not stackA;
when State_Flip =>
begin_inst <= '1';
idim_flag <= '0';
pc <= pc + 1;
for i in 0 to wordSize-1 loop
stackA(i) <= stackA(wordSize-1-i);
end loop;
when State_AddTop =>
begin_inst <= '1';
idim_flag <= '0';
pc <= pc + 1;
stackA <= stackA + stackB;
when State_Shift =>
begin_inst <= '1';
idim_flag <= '0';
pc <= pc + 1;
stackA(wordSize-1 downto 1) <= stackA(wordSize-2 downto 0);
stackA(0) <= '0';
when State_Pushspadd =>
begin_inst <= '1';
idim_flag <= '0';
pc <= pc + 1;
stackA <= (others => '0');
stackA(maxAddrBitIncIO downto minAddrBit) <= stackA(maxAddrBitIncIO-minAddrBit downto 0)+sp;
when State_Neqbranch =>
-- branches are almost always taken as they form loops
begin_inst <= '1';
idim_flag <= '0';
sp <= incIncSp;
if (stackB/=0) then
pc <= stackA(maxAddrBitIncIO downto 0) + pc;
else
pc <= pc + 1;
end if;
-- need to fetch stack again.
state <= State_Resync;
when State_Mult =>
begin_inst <= '1';
idim_flag <= '0';
multA <= stackA;
multB <= stackB;
state <= State_Mult2;
when State_Break =>
report "Break instruction encountered" severity failure;
break <= '1';
when State_Loadb =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
state <= State_Loadb2;
mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
out_mem_req <= '1';
else
insn <= insn;
end if;
when State_Storeb =>
if mem_busy='0' then
begin_inst <= '1';
idim_flag <= '0';
state <= State_Storeb2;
mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
out_mem_req <= '1';
else
insn <= insn;
end if;
when others =>
-- sp <= (others => DontCareValue);
report "Illegal instruction" severity failure;
break <= '1';
end case;
when State_StoreSP2 =>
if mem_busy='0' then
mem_addr <= incSp;
out_mem_req <= '1';
state <= State_Popped;
end if;
when State_LoadSP2 =>
if mem_busy='0' then
state <= State_LoadSP3;
out_mem_req <= '1';
mem_addr <= sp+spOffset+1;
end if;
when State_LoadSP3 =>
if mem_busy='0' then
pc <= pc + 1;
state <= State_Execute;
stackB <= stackA;
stackA <= mem_read;
end if;
when State_AddSP2 =>
if mem_busy='0' then
pc <= pc + 1;
state <= State_Execute;
stackA <= stackA + mem_read;
end if;
when State_Load2 =>
if mem_busy='0' then
stackA <= mem_read;
pc <= pc + 1;
state <= State_Execute;
end if;
when State_Loadb2 =>
if mem_busy='0' then
stackA <= (others => '0');
stackA(7 downto 0) <= mem_read(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8);
pc <= pc + 1;
state <= State_Execute;
end if;
when State_Storeb2 =>
if mem_busy='0' then
mem_addr <= stackA(maxAddrBitIncIO downto minAddrBit);
mem_write <= mem_read;
mem_write(((wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8+7) downto (wordBytes-1-conv_integer(stackA(byteBits-1 downto 0)))*8) <= stackB(7 downto 0) ;
out_mem_req <= '1';
mem_we <= '1';
pc <= pc + 1;
sp <= incIncSp;
state <= State_Resync;
end if;
when State_Fetch =>
if mem_busy='0' then
if interrupt='1' and inInterrupt='0' and idim_flag='0' then
-- We got an interrupt
inInterrupt <= '1';
sp <= decSp;
out_mem_req <= '1';
mem_we <= '1';
mem_addr <= incSp;
mem_write <= stackB;
stackA <= (others => DontCareValue);
stackA(maxAddrBitIncIO downto 0) <= pc;
stackB <= stackA;
pc <= conv_std_logic_vector(32, maxAddrBitIncIo+1); -- interrupt address
report "ZPU jumped to interrupt!" severity note;
else
mem_addr <= pc(maxAddrBitIncIO downto minAddrBit);
out_mem_req <= '1';
state <= State_Decode;
end if;
end if;
when State_Mult2 =>
state <= State_Mult3;
when State_Mult3 =>
state <= State_Mult4;
when State_Mult4 =>
state <= State_Mult5;
when State_Mult5 =>
stackA <= multResult3;
state <= State_Mult6;
when State_Mult6 =>
if mem_busy='0' then
out_mem_req <= '1';
mem_addr <= incIncSp;
sp <= incSp;
state <= State_Popped;
end if;
when State_BinaryOpResult =>
if mem_busy='0' then
-- NB!!!! we know that the memory isn't busy at this point!!!!
out_mem_req <= '1';
mem_addr <= incIncSp;
sp <= incSp;
stackA <= binaryOpResult;
state <= State_Popped;
end if;
when State_Popped =>
if mem_busy='0' then
pc <= pc + 1;
stackB <= mem_read;
state <= State_Execute;
end if;
when others =>
-- sp <= (others => DontCareValue);
report "Illegal state" severity failure;
break <= '1';
end case;
end if;
end process;
end behave;
| gpl-2.0 | 8965fabbb0846053df56668849921f57 | 0.539667 | 3.158839 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb2/vhdl_source/rxtx_to_buf.vhd | 5 | 3,347 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rxtx_to_buf is
port (
clock : in std_logic;
reset : in std_logic;
-- bram interface
ram_addr : out std_logic_vector(10 downto 0);
ram_wdata : out std_logic_vector(7 downto 0);
ram_rdata : in std_logic_vector(7 downto 0);
ram_we : out std_logic;
ram_en : out std_logic;
transferred : out unsigned(10 downto 0);
-- Interface from RX
user_rx_valid : in std_logic;
user_rx_start : in std_logic;
user_rx_data : in std_logic_vector(7 downto 0);
user_rx_last : in std_logic;
-- Interface to TX
send_data : in std_logic;
last_addr : in unsigned(10 downto 0);
no_data : in std_logic := '0';
user_tx_data : out std_logic_vector(7 downto 0);
user_tx_last : out std_logic;
user_tx_next : in std_logic );
end entity;
architecture gideon of rxtx_to_buf is
signal ram_addr_i : unsigned(10 downto 0);
signal ram_en_r : std_logic;
type t_state is (idle, tx_1, tx_2, tx_3, rx);
signal state : t_state;
signal trx_end : std_logic;
begin
ram_en <= ram_en_r or user_rx_valid or user_tx_next;
ram_we <= user_rx_valid;
ram_wdata <= user_rx_data;
user_tx_data <= ram_rdata;
ram_addr <= std_logic_vector(ram_addr_i);
process(clock)
begin
if rising_edge(clock) then
ram_en_r <= '0';
trx_end <= '0';
if trx_end = '1' then
transferred <= ram_addr_i;
end if;
case state is
when idle =>
ram_addr_i <= (others => '0');
if send_data='1' and no_data='0' then
ram_en_r <= '1';
state <= tx_1;
elsif user_rx_start='1' then
if user_rx_valid='1' then
ram_addr_i <= ram_addr_i + 1;
end if;
state <= rx;
end if;
when tx_1 =>
ram_addr_i <= ram_addr_i + 1;
state <= tx_2;
when tx_2 =>
if user_tx_next='1' then
ram_addr_i <= ram_addr_i + 1;
if ram_addr_i = last_addr then
user_tx_last <= '1';
state <= tx_3;
end if;
end if;
when tx_3 =>
if user_tx_next='1' then
trx_end <= '1';
state <= idle;
user_tx_last <= '0';
end if;
when rx =>
if user_rx_valid='1' then
ram_addr_i <= ram_addr_i + 1;
end if;
if user_rx_last='1' then
trx_end <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
user_tx_last <= '0';
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 185ac28a662c8090bdab20690db3a61c | 0.419779 | 3.773393 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op332_3sk1_0.vhdl | 1 | 6,618 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.35e-06,
W => Wdiff_0,
Wdiff_0init => 4.25e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.35e-06,
W => Wdiff_0,
Wdiff_0init => 4.25e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.85e-06,
W => W_0,
W_0init => 2.95e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8.5e-07,
W => Wcm_2,
Wcm_2init => 5.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8.5e-07,
W => Wcmout_2,
Wcmout_2init => 6.095e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8.5e-07,
W => Wcm_2,
Wcm_2init => 5.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8.5e-07,
W => Wcmout_2,
Wcmout_2init => 6.095e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.45e-06,
W => Wcm_1,
Wcm_1init => 1.135e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.45e-06,
W => Wcmcout_1,
Wcmcout_1init => 1.15e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 2.85e-06,
W => (pfak)*(WBias),
WBiasinit => 2.6e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.85e-06,
W => (pfak)*(WBias),
WBiasinit => 2.6e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.85e-06,
W => WBias,
WBiasinit => 2.6e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.85e-06,
W => WBias,
WBiasinit => 2.6e-05
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.85e-06,
W => WBias,
WBiasinit => 2.6e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.85e-06,
W => WBias,
WBiasinit => 2.6e-05
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | d2bcfa013285612010f0e966ded398fa | 0.583862 | 2.932211 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op330_11sk1_0.vhdl | 1 | 7,470 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 2.8e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 2.8e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.55e-06,
W => W_0,
W_0init => 3.085e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.55e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 7.945e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net2,
G => vbias3,
S => net6
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.5e-06,
W => Wcm_2,
Wcm_2init => 9e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.5e-06,
W => Wcmout_2,
Wcmout_2init => 4.935e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net7,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.55e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 7.945e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias3,
S => net7
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.55e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 7.945e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.5e-06,
W => Wcm_2,
Wcm_2init => 9e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 1.5e-06,
W => Wcmout_2,
Wcmout_2init => 4.935e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.55e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 7.945e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.1e-06,
W => Wcm_1,
Wcm_1init => 7.965e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.1e-06,
W => Wcmout_1,
Wcmout_1init => 5.36e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.55e-06,
W => (pfak)*(WBias),
WBiasinit => 5.45e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.55e-06,
W => (pfak)*(WBias),
WBiasinit => 5.45e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.55e-06,
W => WBias,
WBiasinit => 5.45e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.55e-06,
W => WBias,
WBiasinit => 5.45e-06
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.55e-06,
W => WBias,
WBiasinit => 5.45e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.55e-06,
W => WBias,
WBiasinit => 5.45e-06
)
port map(
D => net10,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net11,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net11,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net11,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 51ae7f691d67647bdeaf5e0b1a4bea85 | 0.5834 | 2.905484 | false | false | false | false |
chrismasters/fpga-notes | vga_test/ipcore_dir/vga_clk/simulation/timing/vga_clk_tb.vhd | 1 | 6,260 | -- file: vga_clk_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity vga_clk_tb is
end vga_clk_tb;
architecture test of vga_clk_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component vga_clk_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : vga_clk_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
| mit | 2dfe0eaf1855eac54b1827ad71f905b9 | 0.642652 | 4.244068 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/clocks/example_design/clocks_exdes.vhd | 1 | 6,680 | -- file: clocks_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocks_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(4 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(4 downto 1)
);
end clocks_exdes;
architecture xilinx of clocks_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 4;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal clk_n : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component clocks is
port
(-- Clock in ports
clkin : in std_logic;
-- Clock out ports
clk10mhz : out std_logic;
clk133mhz : out std_logic;
clk133mhzinv : out std_logic;
clk25mhz : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : clocks
port map
(-- Clock in ports
clkin => CLK_IN1,
-- Clock out ports
clk10mhz => clk_int(1),
clk133mhz => clk_int(2),
clk133mhzinv => clk_int(3),
clk25mhz => clk_int(4));
gen_outclk_oddr:
for clk_out_pins in 1 to NUM_C generate
begin
clk_n(clk_out_pins) <= not clk(clk_out_pins);
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(clk_out_pins),
C0 => clk(clk_out_pins),
C1 => clk_n(clk_out_pins),
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate;
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
clk(3) <= clk_int(3);
clk(4) <= clk_int(4);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
| mit | ad89b62fa306bb5fa69319cf5a13b69f | 0.620359 | 3.82808 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/fpga_mem_test_v7.vhd | 5 | 2,933 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity fpga_mem_test_v7 is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(14 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
MOTOR_LEDn : out std_logic;
ACT_LEDn : out std_logic );
end fpga_mem_test_v7;
architecture tb of fpga_mem_test_v7 is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp : t_mem_burst_32_resp;
signal okay : std_logic;
begin
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
okay => ACT_LEDn );
i_mem_ctrl: entity work.ext_mem_ctrl_v7
generic map (
q_tcko_data => 5 ns,
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_A(14 downto 13),
SDRAM_A => SDRAM_A(12 downto 0),
SDRAM_DQ => SDRAM_DQ );
MOTOR_LEDn <= 'Z';
end;
| gpl-3.0 | 2ab34886113f37a33e384eacd253c982 | 0.437777 | 3.68005 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_source/s3a_clockgen.vhd | 3 | 4,920 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity s3a_clockgen is
port (
clk_50 : in std_logic;
reset_in : in std_logic;
dcm_lock : out std_logic;
sys_clock : out std_logic; -- 50 MHz
sys_reset : out std_logic;
sys_clock_2x : out std_logic;
sys_clock_4x : out std_logic;
drive_stop : in std_logic := '0';
drv_clock_en : out std_logic; -- 1/12.5 (4 MHz)
cpu_clock_en : out std_logic; -- 1/50 (1 MHz)
eth_clock : out std_logic; -- / 2.5 (20 MHz)
iec_reset_n : in std_logic := '1';
iec_reset_o : out std_logic );
end s3a_clockgen;
architecture Gideon of s3a_clockgen is
signal clk_in_buf : std_logic;
signal sys_clk_buf : std_logic;
signal reset_dcm : std_logic;
signal reset_cnt : integer range 0 to 63 := 0;
signal dcm1_locked : std_logic := '1';
signal sys_clk_i : std_logic := '0';
signal sys_reset_i : std_logic := '1';
signal sys_reset_p : std_logic := '1';
signal div_cnt : std_logic_vector(3 downto 0) := "0000";
signal pre_cnt : std_logic_vector(1 downto 0) := "00";
signal cpu_cke_i : std_logic := '0';
signal toggle : std_logic := '0';
signal reset_c : std_logic;
signal reset_out : std_logic := '1';
signal sysrst_cnt : integer range 0 to 63;
signal iec_reset_sh : std_logic_vector(0 to 2) := "000";
-- signal reset_sample_cnt : integer range 0 to 127 := 0;
-- signal reset_float : std_logic := '1';
attribute register_duplication : string;
attribute register_duplication of sys_reset_i : signal is "no";
signal clk_0_pre : std_logic;
signal clk_2x_pre : std_logic;
signal clk_4x_pre : std_logic;
begin
dcm_lock <= dcm1_locked;
bufg_in : BUFG port map (I => clk_50, O => clk_in_buf);
process(clk_in_buf)
begin
if rising_edge(clk_in_buf) then
if reset_cnt = 63 then
reset_dcm <= '0';
else
reset_cnt <= reset_cnt + 1;
reset_dcm <= '1';
end if;
end if;
if reset_in='1' then
reset_dcm <= '1';
reset_cnt <= 0;
end if;
end process;
dcm_shft: DCM
generic map
(
CLKIN_PERIOD => 20.0,
-- CLKOUT_PHASE_SHIFT => "FIXED",
CLK_FEEDBACK => "1X",
-- PHASE_SHIFT => -20,
CLKDV_DIVIDE => 2.5,
CLKFX_MULTIPLY => 4,
CLKFX_DIVIDE => 1,
STARTUP_WAIT => true
)
port map
(
CLKIN => clk_in_buf,
CLKFB => sys_clk_buf,
CLK0 => clk_0_pre,
CLK2X => clk_2x_pre,
CLKFX => clk_4x_pre,
CLKDV => eth_clock,
LOCKED => dcm1_locked,
RST => reset_dcm
);
bufg_sys: BUFG port map (I => clk_0_pre, O => sys_clk_buf);
bufg_sys2x: BUFG port map (I => clk_2x_pre, O => sys_clock_2x);
bufg_sys4x: BUFG port map (I => clk_4x_pre, O => sys_clock_4x);
sys_clk_i <= sys_clk_buf;
sys_clock <= sys_clk_buf;
process(sys_clk_i, dcm1_locked)
begin
if rising_edge(sys_clk_i) then
if sysrst_cnt = 63 then
sys_reset_i <= '0';
else
sysrst_cnt <= sysrst_cnt + 1;
end if;
sys_reset_p <= sys_reset_i;
drv_clock_en <= '0';
cpu_cke_i <= '0';
if drive_stop='0' then
if (div_cnt = X"B" and toggle='0') or
(div_cnt = X"C" and toggle='1') then
div_cnt <= X"0";
drv_clock_en <= '1';
toggle <= not toggle;
pre_cnt <= pre_cnt + 1;
if pre_cnt = "11" then
cpu_cke_i <= '1';
else
cpu_cke_i <= '0';
end if;
else
div_cnt <= div_cnt + 1;
end if;
end if;
if cpu_cke_i = '1' then
iec_reset_sh(0) <= not iec_reset_n;
iec_reset_sh(1 to 2) <= iec_reset_sh(0 to 1);
end if;
if sys_reset_p='1' then
toggle <= '0';
pre_cnt <= (others => '0');
div_cnt <= (others => '0');
end if;
end if;
if dcm1_locked='0' then
sysrst_cnt <= 0;
sys_reset_i <= '1';
sys_reset_p <= '1';
end if;
end process;
sys_reset <= sys_reset_p;
cpu_clock_en <= cpu_cke_i;
iec_reset_o <= '1' when iec_reset_sh="111" else '0';
end Gideon; | gpl-3.0 | d8a472c9e169bc0871f6a3e5c1d9f726 | 0.465041 | 3.163987 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op990_33.vhdl | 1 | 7,489 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
terminal net14: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net9
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net10
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net11,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net11
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net12
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net12,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net13,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net13
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net14
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net14,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 293a721301ef2b537410177922591394 | 0.570837 | 3.044309 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op328_2sk1_0.vhdl | 1 | 5,594 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.78e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 3.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.78e-05,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => W_0,
W_0init => 6.505e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcasc_2,
Wcasc_2init => 8e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => Wcasc_2,
Wcasc_2init => 8e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias2,
S => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.15e-06,
W => Wcm_1,
Wcm_1init => 4.25e-06,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.15e-06,
W => Wcmcout_1,
Wcmcout_1init => 4.5e-06,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.45e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => (pfak)*(WBias),
WBiasinit => 1.45e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 3.5e-07,
W => WBias,
WBiasinit => 1.45e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 5b6b7aa95a0bb781d984dda19e9fa64f | 0.589918 | 3.005911 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/vram/simulation/bmg_stim_gen.vhd | 1 | 15,688 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(8,8);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(8,8);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(7168,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(12 DOWNTO 0) <= WRITE_ADDR_A(12 DOWNTO 0);
READ_ADDR_INT_A(12 DOWNTO 0) <= READ_ADDR_A(12 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(12 DOWNTO 0) <= WRITE_ADDR_B(12 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(12 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(12 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 7168,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>7168 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 7168 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 7168 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>8,
DOUT_WIDTH => 8,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>8,
DOUT_WIDTH =>8 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
WEA(0) <= IF_THEN_ELSE(DO_WRITE_A='1','1','0') ;
WEB(0) <= IF_THEN_ELSE(DO_WRITE_B='1','1','0') ;
END ARCHITECTURE;
| mit | ff1ed3ffc5b5506e28e3bd30cc905236 | 0.575025 | 3.209493 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/mem_16to32.vhd | 5 | 3,562 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module converts a 16 bit burst into 32 bits for reads,
-- and vice versa for writes
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity mem_16to32 is
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
req_16 : out t_mem_burst_16_req;
resp_16 : in t_mem_burst_16_resp;
req_32 : in t_mem_burst_32_req;
resp_32 : out t_mem_burst_32_resp );
end entity;
architecture gideon of mem_16to32 is
signal rtoggle : std_logic;
-- signal rbuf : std_logic_vector(15 downto 0);
signal wtoggle : std_logic;
signal pass_wdata : std_logic;
signal get_wdata : std_logic;
signal wdata_av : std_logic;
signal fifo_wdata : std_logic_vector(31 downto 0);
signal fifo_byte_en : std_logic_vector(3 downto 0);
begin
req_16.request <= req_32.request;
req_16.request_tag <= req_32.request_tag;
req_16.address <= req_32.address;
req_16.read_writen <= req_32.read_writen;
resp_32.ready <= resp_16.ready;
process(clock)
begin
if rising_edge(clock) then
-- handle reads
resp_32.rdata_av <= '0';
if resp_16.rdata_av='1' then
rtoggle <= not rtoggle;
-- rbuf <= resp_16.data;
if rtoggle='1' then
resp_32.data(31 downto 16) <= resp_16.data;
resp_32.data_tag <= resp_16.data_tag;
resp_32.rdata_av <= '1';
else
resp_32.data(15 downto 0) <= resp_16.data;
end if;
end if;
-- handle writes
if pass_wdata='1' then
wtoggle <= not wtoggle;
end if;
-- reset
if reset='1' then
wtoggle <= '0';
rtoggle <= '0';
-- rbuf <= (others => '0');
resp_32.data <= (others => '0');
resp_32.data_tag <= (others => '0');
end if;
end if;
end process;
pass_wdata <= wdata_av and not resp_16.wdata_full;
req_16.data <= fifo_wdata(15 downto 0) when wtoggle='0' else fifo_wdata(31 downto 16);
req_16.byte_en <= fifo_byte_en(1 downto 0) when wtoggle='0' else fifo_byte_en(3 downto 2);
req_16.data_push <= pass_wdata;
get_wdata <= pass_wdata and wtoggle;
i_write_fifo: entity work.SRL_fifo
generic map (
Width => 36,
Depth => 15,
Threshold => 6 )
port map (
clock => clock,
reset => reset,
GetElement => get_wdata,
PutElement => req_32.data_push,
FlushFifo => '0',
DataIn(35 downto 32) => req_32.byte_en,
DataIn(31 downto 0) => req_32.data,
DataOut(35 downto 32) => fifo_byte_en,
DataOut(31 downto 0) => fifo_wdata,
SpaceInFifo => open,
AlmostFull => resp_32.wdata_full,
DataInFifo => wdata_av );
end architecture;
| gpl-3.0 | 825192c677b84f9d6c952e5e6bcd8ec1 | 0.463504 | 3.801494 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_sim/usb_harness.vhd | 2 | 2,204 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_harness
-- Date:2015-01-27
-- Author: Gideon
-- Description: Harness for USB Host Controller
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
entity usb_harness is
port (
clocks_stopped : in boolean := false );
end entity;
architecture arch of usb_harness is
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic;
signal clock : std_logic := '0';
signal reset : std_logic;
signal sys_io_req : t_io_req;
signal sys_io_resp : t_io_resp;
signal ulpi_nxt : std_logic;
signal ulpi_stp : std_logic;
signal ulpi_dir : std_logic;
signal ulpi_data : std_logic_vector(7 downto 0);
begin
sys_clock <= not sys_clock after 10 ns when not clocks_stopped;
sys_reset <= '1', '0' after 50 ns;
clock <= not clock after 8 ns when not clocks_stopped;
reset <= '1', '0' after 250 ns;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io" )
port map (
clock => sys_clock,
req => sys_io_req,
resp => sys_io_resp );
i_host: entity work.usb_host_controller
generic map (
g_simulation => true )
port map (
clock => clock,
reset => reset,
ulpi_nxt => ulpi_nxt,
ulpi_dir => ulpi_dir,
ulpi_stp => ulpi_stp,
ulpi_data => ulpi_data,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_io_req => sys_io_req,
sys_io_resp => sys_io_resp );
i_ulpi_phy: entity work.ulpi_master_bfm
generic map (
g_given_name => "device" )
port map (
clock => clock,
reset => reset,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_dir => ulpi_dir,
ulpi_data => ulpi_data );
i_device: entity work.usb_device_model;
end arch;
| gpl-3.0 | adcef6c74b5139a91619582845b19e2a | 0.501815 | 3.642975 | false | false | false | false |
gauravks/i210dummy | Examples/altera_nios2/ipcore/powerlink/src/tbOpenMAC_16to32conv.vhd | 1 | 10,027 | -------------------------------------------------------------------------------
-- Entity : No Title
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use global.all;
entity tbOpenMAC_16to32conv is
end tbOpenMAC_16to32conv;
architecture bhv of tbOpenMAC_16to32conv is
---- Component declarations -----
component busMaster
generic(
gAddrWidth : integer := 32;
gDataWidth : integer := 32;
gStimuliFile : string := "name_TB_stim.txt"
);
port (
iAck : in std_logic;
iClk : in std_logic;
iEnable : in std_logic;
iReaddata : in std_logic_vector(gDataWidth-1 downto 0);
iRst : in std_logic;
oAddress : out std_logic_vector(gAddrWidth-1 downto 0);
oByteenable : out std_logic_vector(gDataWidth/8-1 downto 0);
oDone : out std_logic;
oRead : out std_logic;
oSelect : out std_logic;
oWrite : out std_logic;
oWritedata : out std_logic_vector(gDataWidth-1 downto 0)
);
end component;
component clkgen
generic(
gPeriod : time := 20 ns
);
port (
iDone : in std_logic;
oClk : out std_logic
);
end component;
component Dpr_16_16
generic(
Simulate : boolean
);
port (
AddrA : in std_logic_vector(7 downto 0);
AddrB : in std_logic_vector(7 downto 0);
BeA : in std_logic_vector(1 downto 0) := "11";
BeB : in std_logic_vector(1 downto 0) := "11";
ClkA : in std_logic;
ClkB : in std_logic;
DiA : in std_logic_vector(15 downto 0) := (others => '0');
DiB : in std_logic_vector(15 downto 0) := (others => '0');
EnA : in std_logic := '1';
EnB : in std_logic := '1';
WeA : in std_logic := '0';
WeB : in std_logic := '0';
DoA : out std_logic_vector(15 downto 0);
DoB : out std_logic_vector(15 downto 0)
);
end component;
component enableGen
generic(
gEnableDelay : time := 100 ns
);
port (
iReset : in std_logic;
oEnable : out std_logic;
onEnable : out std_logic
);
end component;
component openMAC_16to32conv
generic(
bus_address_width : integer := 10
);
port (
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_byteenable : in std_logic_vector(3 downto 0);
bus_read : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_writedata : in std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_waitrequest : in std_logic;
bus_ack_rd : out std_logic;
bus_ack_wr : out std_logic;
bus_readdata : out std_logic_vector(31 downto 0);
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_chipselect : out std_logic;
s_read : out std_logic;
s_write : out std_logic;
s_writedata : out std_logic_vector(15 downto 0)
);
end component;
component req_ack
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port (
clk : in std_logic;
enable : in std_logic;
rst : in std_logic;
ack : out std_logic
);
end component;
---- Architecture declarations -----
-- Click here to add additional declarations --
constant cAddrwidth : integer := 32;
constant cDatawidth : integer := 32;
---- Constants -----
constant DANGLING_INPUT_CONSTANT : std_logic := 'Z';
constant GND_CONSTANT : std_logic := '0';
---- Signal declarations used on the diagram ----
signal ack : std_logic;
signal busMasterDone : std_logic;
signal clk50 : std_logic;
signal done : std_logic := '1';
signal enable : std_logic;
signal GND : std_logic;
signal NET1416 : std_logic;
signal NET1425 : std_logic;
signal NET928 : std_logic;
signal NET932 : std_logic;
signal read : std_logic;
signal reset : std_logic;
signal sel : std_logic;
signal s_chipselect : std_logic;
signal s_read : std_logic;
signal s_waitrequest : std_logic;
signal s_write : std_logic;
signal write : std_logic;
signal address : std_logic_vector (cAddrwidth-1 downto 0);
signal byteenable : std_logic_vector (cDatawidth/8-1 downto 0);
signal readdata : std_logic_vector (cDatawidth-1 downto 0);
signal s_address : std_logic_vector (cAddrwidth-1 downto 0);
signal s_byteenable : std_logic_vector (1 downto 0);
signal s_readdata : std_logic_vector (15 downto 0);
signal s_writedata : std_logic_vector (15 downto 0);
signal writedata : std_logic_vector (cDatawidth-1 downto 0);
---- Declaration for Dangling input ----
signal Dangling_Input_Signal : STD_LOGIC;
begin
---- User Signal Assignments ----
--generate done signal
done <= busMasterDone;
---- Component instantiations ----
DUT : openMAC_16to32conv
generic map (
bus_address_width => cAddrwidth
)
port map(
bus_byteenable(0) => byteenable(0),
bus_byteenable(1) => byteenable(1),
bus_byteenable(2) => byteenable(2),
bus_byteenable(3) => byteenable(3),
bus_ack_rd => NET928,
bus_ack_wr => NET932,
bus_address => address( cAddrwidth-1 downto 0 ),
bus_read => read,
bus_readdata => readdata( cDatawidth-1 downto 0 ),
bus_select => sel,
bus_write => write,
bus_writedata => writedata( cDatawidth-1 downto 0 ),
clk => clk50,
rst => reset,
s_address => s_address( cAddrwidth-1 downto 0 ),
s_byteenable => s_byteenable,
s_chipselect => s_chipselect,
s_read => s_read,
s_readdata => s_readdata,
s_waitrequest => s_waitrequest,
s_write => s_write,
s_writedata => s_writedata
);
U1 : clkgen
generic map (
gPeriod => 20 ns
)
port map(
iDone => done,
oClk => clk50
);
U2 : enableGen
generic map (
gEnableDelay => 50 ns
)
port map(
iReset => GND,
onEnable => reset
);
U3 : enableGen
generic map (
gEnableDelay => 50 ns
)
port map(
iReset => reset,
oEnable => enable
);
U4 : busMaster
generic map (
gAddrWidth => cAddrwidth,
gDataWidth => cDatawidth,
gStimuliFile => "openMAC/tb/tbOpenMAC_16to32conv_stim.txt"
)
port map(
iAck => ack,
iClk => clk50,
iEnable => enable,
iReaddata => readdata( cDatawidth-1 downto 0 ),
iRst => reset,
oAddress => address( cAddrwidth-1 downto 0 ),
oByteenable => byteenable( cDatawidth/8-1 downto 0 ),
oDone => busMasterDone,
oRead => read,
oSelect => sel,
oWrite => write,
oWritedata => writedata( cDatawidth-1 downto 0 )
);
U5 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => NET1425,
clk => clk50,
enable => s_write,
rst => reset
);
U6 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => NET1416,
clk => clk50,
enable => s_read,
rst => reset
);
ack <= NET928 or NET932;
s_waitrequest <= not(NET1416 or NET1425);
U9 : Dpr_16_16
generic map (
Simulate => false
)
port map(
AddrA(0) => s_address(0),
AddrA(1) => s_address(1),
AddrA(2) => s_address(2),
AddrA(3) => s_address(3),
AddrA(4) => s_address(4),
AddrA(5) => s_address(5),
AddrA(6) => s_address(6),
AddrA(7) => s_address(7),
AddrB(0) => Dangling_Input_Signal,
AddrB(1) => Dangling_Input_Signal,
AddrB(2) => Dangling_Input_Signal,
AddrB(3) => Dangling_Input_Signal,
AddrB(4) => Dangling_Input_Signal,
AddrB(5) => Dangling_Input_Signal,
AddrB(6) => Dangling_Input_Signal,
AddrB(7) => Dangling_Input_Signal,
BeA => s_byteenable,
ClkA => clk50,
ClkB => clk50,
DiA => s_writedata,
DoA => s_readdata,
EnA => s_chipselect,
EnB => GND,
WeA => s_write,
WeB => GND
);
---- Power , ground assignment ----
GND <= GND_CONSTANT;
---- Dangling input signal assignment ----
Dangling_Input_Signal <= DANGLING_INPUT_CONSTANT;
end bhv;
| gpl-2.0 | 9d818463e4ad963b28ac7b32baa3e189 | 0.600578 | 3.643532 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op336_6sk1_0.vhdl | 1 | 7,438 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9e-07,
W => Wdiff_0,
Wdiff_0init => 5.15e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9e-07,
W => Wdiff_0,
Wdiff_0init => 5.15e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.1e-06,
W => W_0,
W_0init => 3.55e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9e-07,
W => Wdiff_0,
Wdiff_0init => 5.15e-06,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9e-07,
W => Wdiff_0,
Wdiff_0init => 5.15e-06,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.45e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.245e-05,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.45e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.245e-05,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.45e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.245e-05,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.45e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 3.245e-05,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 8.1e-06,
W => Wsrc_2,
Wsrc_2init => 1.45e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 8.1e-06,
W => Wsrc_2,
Wsrc_2init => 1.45e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.8e-06,
W => Wcm_1,
Wcm_1init => 3.5e-07,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.8e-06,
W => Wcmcout_1,
Wcmcout_1init => 6.15e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.1e-06,
W => (pfak)*(WBias),
WBiasinit => 3.65e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.1e-06,
W => (pfak)*(WBias),
WBiasinit => 3.65e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.1e-06,
W => WBias,
WBiasinit => 3.65e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.1e-06,
W => WBias,
WBiasinit => 3.65e-06
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.1e-06,
W => WBias,
WBiasinit => 3.65e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.1e-06,
W => WBias,
WBiasinit => 3.65e-06
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net8,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net8,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net8,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 5738ab5227889523e731f4914fca2f84 | 0.581742 | 2.874034 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/zpu_small.vhdl | 5 | 23,125 | ------------------------------------------------------------------------------
---- ----
---- ZPU Small ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is the small size version. ----
---- It doesn't support external memories, needs a dual ported memory. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: ZPUSmallCore(Behave) (Entity and architecture) ----
---- File name: zpu_small.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- zpu.zpupkg ----
---- Target FPGA: Spartan 3 (XC3S1500-4-FG456) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 9.2.03i - xst J.39 ----
---- Simulation tools: GHDL [Sokcho edition] (0.2x) ----
---- Text editor: SETEdit 0.5.x ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.numeric_std.all;
library work;
use work.zpupkg.all;
entity ZPUSmallCore is
generic(
WORD_SIZE : integer:=32; -- Data width 16/32
ADDR_W : integer:=16; -- Total address space width (incl. I/O)
MEM_W : integer:=15; -- Memory (prog+data+stack) width
D_CARE_VAL : std_logic:='X'); -- Value used to fill the unsused bits
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (text, data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
a_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
b_o : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(WORD_SIZE-1 downto 0);
data_o : out unsigned(WORD_SIZE-1 downto 0);
addr_o : out unsigned(ADDR_W-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity ZPUSmallCore;
architecture Behave of ZPUSmallCore is
constant MAX_ADDR_BIT : integer:=ADDR_W-2;
constant BYTE_BITS : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
constant SP_START : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=
SP_START_1(MAX_ADDR_BIT downto BYTE_BITS);
constant IO_BIT : integer:=ADDR_W-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(MAX_ADDR_BIT downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal a_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
-- We also use the B port to fetch instructions.
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(MAX_ADDR_BIT downto BYTE_BITS):=(others => '0');
signal b_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_io, st_write_io, st_fetch_next,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(ADDR_W-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(MEM_W-1 downto BYTE_BITS);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(MEM_W-1 downto BYTE_BITS);
b_o <= b_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use Port B memory to fetch the opcodes.
decode_control:
process(b_i, pc_r)
variable topcode : unsigned(c_opcode_width-1 downto 0);
begin
-- Select the addressed byte inside the fetched word
case (to_integer(pc_r(BYTE_BITS-1 downto 0))) is
when 0 =>
topcode:=b_i(31 downto 24);
when 1 =>
topcode:=b_i(23 downto 16);
when 2 =>
topcode:=b_i(15 downto 8);
when others => -- 3
topcode:=b_i(7 downto 0);
end case;
opcode <= topcode;
if (topcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (topcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (topcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (topcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (topcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case topcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
dbg_o.b_inst <= '0';
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
a_r <= (others => D_CARE_VAL);
b_r <= (others => D_CARE_VAL);
sp_offset:=(others => D_CARE_VAL);
a_addr_r <= (others => D_CARE_VAL);
b_addr_r <= (others => D_CARE_VAL);
addr_r <= a_i(ADDR_W-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(MAX_ADDR_BIT downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32,MAX_ADDR_BIT+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),WORD_SIZE));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(WORD_SIZE-1 downto 7) <= a_i(WORD_SIZE-8 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(MAX_ADDR_BIT downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => D_CARE_VAL);
a_r(31) <= '1'; -- for easy comparison with my own version of ZPU
a_r(MAX_ADDR_BIT downto BYTE_BITS) <= sp_r;
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(MAX_ADDR_BIT downto 0);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
if a_i(IO_BIT)='1' then
addr_r <= a_i(ADDR_W-1 downto 0);
read_en_o <= '1';
state <= st_read_io;
else
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r(MAX_ADDR_BIT downto BYTE_BITS);
a_we_r <= '1';
for i in 0 to WORD_SIZE-1 loop
a_r(i) <= a_i(WORD_SIZE-1-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
b_addr_r <= sp_r+1;
sp_r <= sp_r+1;
if a_i(IO_BIT)='1' then
state <= st_write_io;
else
state <= st_store;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_read_io =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
a_r <= data_i;
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(ADDR_W-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During the *next* cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute the cycle after
-- next
b_addr_r <= pc_r(MAX_ADDR_BIT downto BYTE_BITS);
state <= st_fetch_next;
when st_fetch_next =>
-- At this point a_i contains the value that is either
-- from the top of stack or should be copied to the top of the stack
a_we_r <= '1';
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(MAX_ADDR_BIT downto BYTE_BITS);
a_r <= b_i;
state <= st_resync;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: ZPUSmallCore
| gpl-3.0 | 9c6bf111182390577bb91ed2b3e9c710 | 0.349059 | 4.46601 | false | false | false | false |
chrismasters/fpga-notes | sdramcontroller/ipcore_dir/clks/example_design/clks_exdes.vhd | 1 | 6,458 | -- file: clks_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clks_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1)
);
end clks_exdes;
architecture xilinx of clks_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Number of counters
constant NUM_C : integer := 2;
-- Array typedef
type ctrarr is array (1 to NUM_C) of std_logic_vector(C_W-1 downto 0);
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counters
signal clk : std_logic_vector(NUM_C downto 1);
signal clk_int : std_logic_vector(NUM_C downto 1);
signal clk_n : std_logic_vector(NUM_C downto 1);
signal counter : ctrarr := (( others => (others => '0')));
signal rst_sync : std_logic_vector(NUM_C downto 1);
signal rst_sync_int : std_logic_vector(NUM_C downto 1);
signal rst_sync_int1 : std_logic_vector(NUM_C downto 1);
signal rst_sync_int2 : std_logic_vector(NUM_C downto 1);
component clks is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
counters_1: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), reset_int) begin
if (reset_int = '1') then
rst_sync(count_gen) <= '1';
rst_sync_int(count_gen) <= '1';
rst_sync_int1(count_gen) <= '1';
rst_sync_int2(count_gen) <= '1';
elsif (clk(count_gen) 'event and clk(count_gen)='1') then
rst_sync(count_gen) <= '0';
rst_sync_int(count_gen) <= rst_sync(count_gen);
rst_sync_int1(count_gen) <= rst_sync_int(count_gen);
rst_sync_int2(count_gen) <= rst_sync_int1(count_gen);
end if;
end process;
end generate counters_1;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : clks
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int(1),
CLK_OUT2 => clk_int(2));
gen_outclk_oddr:
for clk_out_pins in 1 to NUM_C generate
begin
clk_n(clk_out_pins) <= not clk(clk_out_pins);
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(clk_out_pins),
C0 => clk(clk_out_pins),
C1 => clk_n(clk_out_pins),
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate;
-- Connect the output clocks to the design
-------------------------------------------
clk(1) <= clk_int(1);
clk(2) <= clk_int(2);
-- Output clock sampling
-------------------------------------
counters: for count_gen in 1 to NUM_C generate begin
process (clk(count_gen), rst_sync_int2(count_gen)) begin
if (rst_sync_int2(count_gen) = '1') then
counter(count_gen) <= (others => '0') after TCQ;
elsif (rising_edge (clk(count_gen))) then
counter(count_gen) <= counter(count_gen) + 1 after TCQ;
end if;
end process;
-- alias the high bit of each counter to the corresponding
-- bit in the output bus
COUNT(count_gen) <= counter(count_gen)(C_W-1);
end generate counters;
end xilinx;
| mit | b85cf6dcfe8370b79f03ddb2fa56a182 | 0.624032 | 3.841761 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op332_9sk1_0.vhdl | 1 | 6,468 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.7e-06,
W => Wdiff_0,
Wdiff_0init => 1.165e-05,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.7e-06,
W => Wdiff_0,
Wdiff_0init => 1.165e-05,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.3e-06,
W => W_0,
W_0init => 3.4e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 9.5e-07,
W => Wcm_2,
Wcm_2init => 1.05e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 9.5e-07,
W => Wcmout_2,
Wcmout_2init => 6.84e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 9.5e-07,
W => Wcm_2,
Wcm_2init => 1.05e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 9.5e-07,
W => Wcmout_2,
Wcmout_2init => 6.84e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.05e-06,
W => Wcm_1,
Wcm_1init => 2.58e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.05e-06,
W => Wcmcout_1,
Wcmcout_1init => 2.535e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4.3e-06,
W => (pfak)*(WBias),
WBiasinit => 1.49e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 4.3e-06,
W => (pfak)*(WBias),
WBiasinit => 1.49e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 4.3e-06,
W => WBias,
WBiasinit => 1.49e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.3e-06,
W => WBias,
WBiasinit => 1.49e-05
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.3e-06,
W => WBias,
WBiasinit => 1.49e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.3e-06,
W => WBias,
WBiasinit => 1.49e-05
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 285e0cdee8758a8ad9f80bed06485e29 | 0.583797 | 2.935996 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sampler/vhdl_source/sampler.vhd | 4 | 9,000 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.sampler_pkg.all;
entity sampler is
generic (
g_num_voices : positive := 8 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
irq : out std_logic;
sample_L : out signed(17 downto 0);
sample_R : out signed(17 downto 0);
new_sample : out std_logic );
end entity;
architecture gideon of sampler is
signal voice_state : t_voice_state_array(0 to g_num_voices-1) := (others => c_voice_state_init);
signal voice_sample_reg_h : t_sample_byte_array(0 to g_num_voices-1) := (others => (others => '0'));
signal voice_sample_reg_l : t_sample_byte_array(0 to g_num_voices-1) := (others => (others => '0'));
signal voice_i : integer range 0 to g_num_voices-1;
signal fetch_en : std_logic;
signal fetch_addr : unsigned(25 downto 0);
signal fetch_tag : std_logic_vector(7 downto 0);
signal interrupt : std_logic_vector(g_num_voices-1 downto 0);
signal interrupt_clr : std_logic_vector(g_num_voices-1 downto 0);
signal current_control : t_voice_control;
signal first_chan : std_logic;
signal cur_sam : signed(15 downto 0);
signal cur_vol : unsigned(5 downto 0);
signal cur_pan : unsigned(3 downto 0);
begin
i_regs: entity work.sampler_regs
generic map (
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
rd_addr => voice_i,
control => current_control,
irq_status => interrupt,
irq_clear => interrupt_clr );
irq <= '1' when unsigned(interrupt) /= 0 else '0';
process(clock)
variable current_state : t_voice_state;
variable next_state : t_voice_state;
variable sample_reg : signed(15 downto 0);
variable v : integer range 0 to 15;
begin
if rising_edge(clock) then
if voice_i = g_num_voices-1 then
voice_i <= 0;
else
voice_i <= voice_i + 1;
end if;
for i in interrupt'range loop
if interrupt_clr(i)='1' then
interrupt(i) <= '0';
end if;
end loop;
fetch_en <= '0';
current_state := voice_state(0);
sample_reg := voice_sample_reg_h(voice_i) & voice_sample_reg_l(voice_i);
next_state := current_state;
case current_state.state is
when idle =>
if current_control.enable then
next_state.state := fetch1;
next_state.position := (others => '0');
next_state.divider := current_control.rate;
next_state.sample_out := (others => '0');
end if;
when playing =>
if current_state.divider = 0 then
next_state.divider := current_control.rate;
next_state.sample_out := sample_reg;
next_state.state := fetch1;
if (current_state.position = current_control.repeat_b) then
if current_control.enable and current_control.repeat then
next_state.position := current_control.repeat_a;
end if;
elsif current_state.position = current_control.length then
next_state.state := finished;
if current_control.interrupt then
interrupt(voice_i) <= '1';
end if;
end if;
else
next_state.divider := current_state.divider - 1;
end if;
if not current_control.enable and not current_control.repeat then
next_state.state := idle;
end if;
when finished =>
if not current_control.enable then
next_state.state := idle;
end if;
when fetch1 =>
fetch_en <= '1';
fetch_addr <= current_control.start_addr + current_state.position;
if current_control.mode = mono8 then
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '1'; -- high
next_state.state := playing;
if current_control.interleave then
next_state.position := current_state.position + 2; -- this and the next byte
else
next_state.position := current_state.position + 1; -- this byte only
end if;
else
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '0'; -- low
next_state.position := current_state.position + 1; -- go to the next byte
next_state.state := fetch2;
end if;
when fetch2 =>
fetch_en <= '1';
fetch_addr <= current_control.start_addr + current_state.position;
fetch_tag <= "110" & std_logic_vector(to_unsigned(voice_i, 4)) & '1'; -- high
next_state.state := playing;
if current_control.interleave then
next_state.position := current_state.position + 3; -- this and the two next bytes
else
next_state.position := current_state.position + 1; -- this byte only
end if;
when others =>
null;
end case;
cur_sam <= current_state.sample_out;
cur_vol <= current_control.volume;
cur_pan <= current_control.pan;
if voice_i=0 then
first_chan <= '1';
else
first_chan <= '0';
end if;
-- write port - state --
voice_state <= voice_state(1 to g_num_voices-1) & next_state;
-- write port - sample data --
if mem_resp.dack_tag(7 downto 5) = "110" then
v := to_integer(unsigned(mem_resp.dack_tag(4 downto 1)));
if mem_resp.dack_tag(0)='1' then
voice_sample_reg_h(v) <= signed(mem_resp.data);
else
voice_sample_reg_l(v) <= signed(mem_resp.data);
end if;
end if;
if reset='1' then
voice_i <= 0;
next_state.state := idle; -- shifted into the voice state vector automatically.
interrupt <= (others => '0');
end if;
end if;
end process;
b_mem_fifo: block
signal rack : std_logic;
signal fifo_din : std_logic_vector(33 downto 0);
signal fifo_dout : std_logic_vector(33 downto 0);
begin
fifo_din <= fetch_tag & std_logic_vector(fetch_addr);
i_fifo: entity work.srl_fifo
generic map (
Width => 34,
Depth => 15,
Threshold => 10 )
port map (
clock => clock,
reset => reset,
GetElement => rack,
PutElement => fetch_en,
FlushFifo => '0',
DataIn => fifo_din,
DataOut => fifo_dout,
SpaceInFifo => open,
DataInFifo => mem_req.request );
mem_req.read_writen <= '1';
mem_req.address <= unsigned(fifo_dout(25 downto 0));
mem_req.tag <= fifo_dout(33 downto 26);
mem_req.data <= X"00";
mem_req.size <= "00"; -- 1 byte at a time (can be optimized!)
rack <= '1' when (mem_resp.rack='1' and mem_resp.rack_tag(7 downto 5)="110") else '0';
end block;
i_accu: entity work.sampler_accu
port map (
clock => clock,
reset => reset,
first_chan => first_chan,
sample_in => cur_sam,
volume_in => cur_vol,
pan_in => cur_pan,
sample_L => sample_L,
sample_R => sample_R,
new_sample => new_sample );
end gideon;
| gpl-3.0 | c2da0502c2792d0007c68d08e529edbf | 0.464444 | 4.193849 | false | false | false | false |
multiple1902/xjtu_comp-org-lab | modules/memory/memory.vhdl | 1 | 1,620 | -- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.numeric_std.all;
entity memory is
port (
cs : in std_logic; -- Chip select
re, we : in std_logic; -- Read / Write Enable
clk : in std_logic;
addr_h, addr_l
: in std_logic_vector(4 downto 0);
data_in : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0) -- no semicolon here!
);
end memory;
architecture behv of memory is
type core_type is array(1023 downto 0) of std_logic_vector(15 downto 0);
signal core: core_type;
signal addr: std_logic_vector(9 downto 0);
begin
process(clk,cs,re,we,addr_h,addr_l)
begin
if clk='1' and cs='1' and re='1' then
addr(9 downto 5)<= addr_h(4 downto 0);
addr(4 downto 0)<= addr_l(4 downto 0);
data_out <= core(conv_integer(std_logic_vector(addr)));
elsif clk='1' and cs='1' and we='1' then
addr(9 downto 5)<= addr_h(4 downto 0);
addr(4 downto 0)<= addr_l(4 downto 0);
-- core(to_integer(unsigned(addr)))<= data_in;
-- core(to_integer(unsigned(addr)))<= data_in;
core(conv_integer(std_logic_vector(addr)))<= data_in;
data_out <= core(to_integer(unsigned(addr)));
assert false report "hello" severity note;
-- data_out <= "ZZZZZZZZZZZZZZZZ";
--else
-- data_out <= "ZZZZZZZZZZZZZZZZ";
end if;
end process;
end behv;
| gpl-3.0 | 74e805819ee5938e1037b282807500e8 | 0.575926 | 3.375 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_sim/tb_sid_from_file.vhd | 4 | 5,053 | -------------------------------------------------------------------------------
-- Date $Date: 2005/04/12 19:09:27 $
-- Author $Author: Gideon $
-- Revision $Revision: 1.1 $
-- Log $Log: oscillator.vhd,v $
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.wave_pkg.all;
entity tb_sid_from_file is
end tb_sid_from_file;
architecture tb of tb_sid_from_file is
signal clock : std_logic := '0';
signal reset : std_logic;
signal addr : unsigned(6 downto 0) := (others => '0');
signal wren : std_logic := '0';
signal wdata : std_logic_vector(7 downto 0) := (others => '0');
signal rdata : std_logic_vector(7 downto 0) := (others => '0');
signal start_iter : std_logic := '0';
signal sid_pwm : std_logic := '0';
signal sample_out : signed(17 downto 0);
signal stop_clock : boolean := false;
signal vc : real := 0.0;
constant R : real := 2200.0;
constant C : real := 0.000000022;
constant c_cpu_period : time := 1014973 ps;
constant c_half_clock : time := c_cpu_period / 8;
constant c_clock : time := c_half_clock * 2;
begin
clock <= not clock after c_half_clock when not stop_clock; -- 5 MHz
reset <= '1', '0' after 1 us;
sid: entity work.sid_top
generic map (
g_filter_div => 20, -- 194 for 50 MHz;
g_num_voices => 3 )
port map (
clock => clock,
reset => reset,
addr => addr,
wren => wren,
wdata => wdata,
rdata => rdata,
start_iter => start_iter,
sample_out => sample_out );
-- i_pdm_sid: entity work.sigma_delta_dac
-- generic map (
-- g_left_shift => 0,
-- g_width => sample_out'length )
-- port map (
-- clock => clock,
-- reset => reset,
--
-- dac_in => sample_out,
--
-- dac_out => sid_pwm );
--
-- filter: process(clock)
-- variable v_dac : real;
-- variable i_r : real;
-- variable q_c : real;
-- begin
-- if rising_edge(clock) then
-- if sid_pwm='0' then
-- v_dac := -1.2;
-- else
-- v_dac := 1.2;
-- end if;
-- i_r := (v_dac - vc) / R;
-- q_c := i_r * 200.0e-9; -- 200 ns;
-- vc <= vc + (q_c / C);
-- end if;
-- end process;
--
test: process
variable trace_in : h_mem_object;
variable addr_i : integer := 0;
variable delay : time := 1 ns;
variable t : unsigned(23 downto 0);
variable b : std_logic_vector(7 downto 0);
begin
register_mem_model(tb_sid_from_file'path_name, "trace", trace_in);
load_memory("sidtrace.555", trace_in, X"00000000");
wait until reset='0';
wait until clock='1';
L1: while now < 5000 ms loop
b := read_memory_8(trace_in, std_logic_vector(to_unsigned(addr_i, 32)));
addr <= unsigned(b(6 downto 0));
wdata <= read_memory_8(trace_in, std_logic_vector(to_unsigned(addr_i+1, 32)));
t(23 downto 16) := unsigned(read_memory_8(trace_in, std_logic_vector(to_unsigned(addr_i+2, 32))));
t(15 downto 8) := unsigned(read_memory_8(trace_in, std_logic_vector(to_unsigned(addr_i+3, 32))));
t( 7 downto 0) := unsigned(read_memory_8(trace_in, std_logic_vector(to_unsigned(addr_i+4, 32))));
addr_i := addr_i + 5;
if t = 0 then
exit L1;
end if;
delay := (1 us) * (to_integer(t)-1);
wait for delay;
wren <= '1';
wait for 1 * c_clock;
wren <= '0';
wait for 3 * c_clock;
end loop;
stop_clock <= true;
wait;
end process test;
process
begin
wait for 3 * c_clock;
start_iter <= '1';
wait for 1 * c_clock;
start_iter <= '0';
if stop_clock then
wait;
end if;
end process;
-- this clock is a little faster (1 Mhz instead of 985250 Hz, thus we need to adjust our sample rate by the same amount
-- which means we need to sample at 48718 Hz instead of 48kHz. Sample period =
process
variable chan : t_wave_channel;
begin
open_channel(chan);
while not stop_clock loop
wait for 20833 ns; -- 20526 ns;
push_sample(chan, to_integer(sample_out(17 downto 2)));
end loop;
write_wave("sid_wave.wav", 48000, (0 => chan));
wait;
end process;
end tb;
| gpl-3.0 | 617344402309be5675383545f493ba5a | 0.470216 | 3.518802 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_sim/tb_clockgen.vhd | 5 | 1,105 | library ieee;
use ieee.std_logic_1164.all;
entity tb_clockgen is
end;
architecture tb of tb_clockgen is
signal clk_50 : std_logic := '0';
signal reset_in : std_logic;
signal dcm_lock : std_logic;
signal sys_clock : std_logic; -- 48 MHz
signal sys_reset : std_logic;
signal drv_clock_en : std_logic; -- 1/12 (4 MHz)
signal cpu_clock_en : std_logic; -- 1/48 (1 MHz)
begin
clk_50 <= not clk_50 after 10 ns;
reset_in <= '1', '0' after 100 ns;
gen: entity work.s3e_clockgen
generic map ( false )
port map (
clk_50 => clk_50,
reset_in => reset_in,
dcm_lock => dcm_lock,
sys_clock => sys_clock, -- 48 MHz
sys_reset => sys_reset,
drv_clock_en => drv_clock_en, -- 1/12 (4 MHz)
cpu_clock_en => cpu_clock_en, -- 1/48 (1 MHz)
cpu_speed => '0', -- 0 = 1 MHz, 1 = max.
mem_ready => '1' );
end tb;
| gpl-3.0 | 79b084431431369be322d6e41375073d | 0.459729 | 3.4 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/RAM_MEMORY.vhd | 1 | 2,560 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_F9LRRL
-- /___/ /\ Timestamp : 04/06/2014 00:33:54
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity RAM_MEMORY is
port (
clk : IN std_logic;
address : IN std_logic_vector(31 downto 0);
read_en : IN std_logic;
data_out: OUT std_logic_vector(7 downto 0)
);
end RAM_MEMORY;
architecture BEHAVIORAL of PointBuffer is
signal sPointSet: T_POINT_SET := others => (others => '0'));
signal enables: std_logic_vector(N_POINTS-2 downto 0);
signal counter1: integer range 0 to N_POINTS*NUMBER_OF_SCALES-1 = 0;
signal counter2: integer range 0 to NUMBER_OF_SCALES-1 := 0;
component PointFifo
port ( clk : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
rst : in std_logic;
enableOut : out std_logic;
outputValue: out std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0)
);
end component;
begin
pointFifo0: PointFifo
port map(
clk => clk,
enableIn => enableIn,
inputValue => inputValue,
rst => rst,
enableOut => enables(0),
outputValue => sPointSet(1)
);
genPointBuffer: for i in 1 to N_POINTS-2 generate
pointFifoX: PointFifo
port map(
clk => clk,
enableIn => enables(i-1),
inputValue => sPointSet(i),
rst => rst,
enableOut => enables(i),
outputValue => sPointSet(i+1)
);
end generate genPointBuffer;
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
counter1 <= 0;
counter2 <= 0;
enableOut <= '0';
else
if enableIn = '1' then
sPointSet(0) <= inputValue;
if counter1 = N_POINTS*NUMBER_OF_SCALES-1 then
if counter2 = NUMBER_OF_SCALES-1 then
counter2 <= 0;
counter1 <= 0;
else
counter2 <= counter2+1;
end if;
enableOut <= '1';
else
counter1 <= counter1+1;
enableOut <= '0';
end if;
else
enableOut <= '0';
end if;
end if;
end if;
end process;
pointSet <= sPointSet;
end BEHAVIORAL;
| gpl-3.0 | 2e84b8cd64a9ed7638fddd79926b1afc | 0.552344 | 3.047619 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openFILTER.vhd | 3 | 11,093 | ------------------------------------------------------------------------------------------------------------------------
-- OpenFILTER
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: RxDv and RxDat have to be synchron to Clk
-- The following Conditions are checked:
-- RxDV >163.64µsec HIGH -> invalid
-- RxDV <0.64µsec LOW -> invalid
-- RxDV 4x <5.12µsec HIGH -> invalid
-- RxDV >5.12µsec HIGH -> valid
-- RxErr HIGH -> invalid
-- if invalid deactivation of port, until RxDv and RxErr > 10.24µsec low
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted from V1.1 to first official version.
-- 2011-07-23 V0.10 zelenkaj Consideration of RX Error signal and jitter (converted from V2.3)
-- 2011-08-03 V0.11 zelenkaj translated comments
-- 2011-11-18 V0.12 zelenkaj bypass filter by generic
-- 2011-11-28 V0.13 zelenkaj Changed reset level to high-active
-- 2012-04-19 V0.20 zelenkaj Redesign with fsm, Preamble-check improvement
-- 2012-05-21 V0.21 muelhausens changed timeout of fs_FRMnopre to 660ns
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
ENTITY openFILTER is
Generic (
bypassFilter : boolean := false
);
Port ( Rst : in std_logic;
Clk : in std_logic;
nCheckShortFrames : in std_logic := '0'; -- Rx Port von Hub;
RxDvIn : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
RxDatOut : out std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
TxDatIn : in std_logic_vector(1 downto 0);
TxEnOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
RxErr : in std_logic := '0'
);
END ENTITY openFILTER;
ARCHITECTURE rtl OF openFILTER IS
type aRxSet is record
RxDv : std_logic;
RxDat: std_logic_vector(1 downto 0);
end record;
type aRxSetArr is array (3 downto 0) of aRxSet;
type aFiltState is (fs_init, fs_GAP2short, fs_GAPext, fs_GAPok, fs_FRMnopre,
fs_FRMpre2short, fs_FRMpreOk, fs_FRM2short, fs_FRMok, fs_FRM2long, fs_BlockAll);
signal FiltState : aFiltState;
signal RxDel : aRxSetArr;
signal FrameShift : std_logic;
signal LastFrameNOK : std_logic;
signal StCnt : std_logic_vector(13 downto 0);
signal BlockRxPort : std_logic;
BEGIN
disFilter : if bypassFilter generate
begin
RxDvOut <= RxDvIn;
RxDatOut <= RxDatIn;
TxEnOut <= TxEnIn;
TxDatOut <= TxDatIn;
end generate;
enFilter : if not bypassFilter generate
begin
-- IN --
RxDel(0).RxDv <= RxDvIn;
RxDel(0).RxDat <= RxDatIn;
BlockRxPort <= '1' when FiltState = fs_FRMnopre or FiltState = fs_BlockAll or LastFrameNOK = '1' else '0';
-- OUTPUT MUX --
RxDvOut <= '0' when BlockRxPort = '1' else
RxDel(3).RxDv when FrameShift = '1' else
RxDel(1).RxDv;
RxDatOut <= "00" when BlockRxPort = '1' else
RxDel(3).RxDat when FrameShift = '1' else
RxDel(1).RxDat;
TxEnOut <= TxEnIn;
TxDatOut <= TxDatIn;
fsm: PROCESS(Rst, Clk)
VARIABLE RstStCnt : std_logic;
begin
if Rst = '1' then
StCnt <= (others => '0');
FiltState <= fs_init;
FrameShift <= '0';
RxDel(3 downto 1) <= (others => ('0',"00"));
LastFrameNOK <= '0';
elsif rising_edge(Clk) then
RxDel(3 downto 1) <= RxDel(2 downto 0);
-- DEFAULT --
RstStCnt := '0';
case FiltState is
-------------------------------- INIT ---------------------------------------
when fs_init =>
FiltState <= fs_GAP2short; RstStCnt := '1';
-------------------------------- GAP 2 SHORT --------------------------------
when fs_GAP2short =>
FrameShift <= '0';
IF StCnt(4) = '1' then FiltState <= fs_GAPext; END IF; -- 360ns
IF RxDel(0).RxDv = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- Gap < 360 ns -> too short -> Block Filter
-------------------------------- GAP EXTEND ---------------------------------
when fs_GAPext =>
IF StCnt(5 downto 0) = "101110" then FiltState <= fs_GAPok; END IF;
IF RxDel(0).RxDv = '1' then -- GAP [360ns .. 960ns] -> short, but ok -> Start Frame
RstStCnt := '1';
FrameShift <= '1';
IF RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; -- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
ELSE FiltState <= fs_FRMnopre; -- GAP > 960ns -> OK -> Start Frame and wait of preamble
END IF;
END IF;
-------------------------------- GAP OK -------------------------------------
when fs_GAPok =>
IF RxDel(0).RxDv = '1' then
RstStCnt := '1';
IF RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; -- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
ELSE FiltState <= fs_FRMnopre; -- GAP > 960ns -> OK -> Start Frame and wait of preamble
END IF;
END IF;
-------------------------------- FRAME, BUT STILL NO PREAMBLE ---------------
when fs_FRMnopre =>
IF StCnt(5) = '1' or -- no preamble for >=660 ns -> Block Filter
RxDel(0).RxDat = "11" or RxDel(0).RxDat = "10" or -- preamble wrong -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1';
elsif RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; RstStCnt := '1'; -- preamble starts -> Check Preamble
END IF;
-------------------------------- FRAME CHECK PREAMBLE TOO SHORT --------------
when fs_FRMpre2short =>
IF RxDel(0).RxDat /= "01" or -- preamble wrong -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1';
ELSIF StCnt(3) = '1' then FiltState <= fs_FRMpreOk; END IF; -- preamble ok for 180 ns -> Preamble OK
-------------------------------- FRAME CHECK PREAMBLE OK ---------------
when fs_FRMpreOk =>
IF RxDel(0).RxDat /= "01" then FiltState <= fs_FRMok; END IF; -- preamble done -> Start Frame
IF (StCnt(5) = '1' and StCnt(2) = '1') or -- preamble to long for 740 ns -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF;
LastFrameNOK <= '0'; -- preamble is OK
-------------------------------- FRAME OK -----------------------------------
when fs_FRMok =>
IF StCnt(13) = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- FRAME > 163,842 us -> too long -> Block Filter
IF RxDel(0).RxDv = '0' and
RxDel(1).RxDv = '0' then FiltState <= fs_GAP2short; RstStCnt := '1'; END IF; -- FRAME [163,842 us] -> OK -> Start GAP
-------------------------------- Block Filter -------------------------------
when fs_BlockAll =>
IF StCnt(2) = '1' then FiltState <= fs_GAP2short; RstStCnt := '1'; END IF; -- Block for 100 nsec
IF RxDel(0).RxDv = '1' then RstStCnt := '1'; END IF; -- RxDv != '0' -> Reset Wait Period
LastFrameNOK <= '1'; -- block next rx frame (until receive a valid preamble)
when others =>
FiltState <= fs_init;
end case;
IF RxErr = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- RxErr -> Block Filter
-- State Counter --
StCnt <= StCnt + 1;
if RstStCnt = '1' then StCnt <= (others => '0'); end if;
end if;
end process;
end generate;
END rtl;
| gpl-2.0 | da3435586c2f0aa0c98bf768479e9a80 | 0.475705 | 4.492912 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/ram/example_design/ram_exdes.vhd | 1 | 4,577 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ram_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END ram_exdes;
ARCHITECTURE xilinx OF ram_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT ram IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : ram
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| mit | ff40b2ef19d748196a501835a0b5a082 | 0.564999 | 4.752856 | false | false | false | false |
chrismasters/fpga-notes | sdramcontroller/sdramcontroller.vhd | 2 | 6,417 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sdramcontroller is
port (
clk : in STD_LOGIC;
addr : in STD_LOGIC_VECTOR (15 downto 0);
dataIn : in STD_LOGIC_VECTOR (7 downto 0);
dataOut : out STD_LOGIC_VECTOR (7 downto 0);
cmd : in STD_LOGIC_VECTOR (1 downto 0);
ready : out STD_LOGIC;
--chipClk : out STD_LOGIC;
--chipCke : out STD_LOGIC;
chipCS : out STD_LOGIC;
chipWE : out STD_LOGIC;
chipCAS : out STD_LOGIC;
chipRAS: out STD_LOGIC;
chipDQML : out STD_LOGIC;
chipDQMH : out STD_LOGIC;
chipBA : out STD_LOGIC_VECTOR (1 downto 0);
chipADDR : out STD_LOGIC_VECTOR (11 downto 0);
chipDATA : inout STD_LOGIC_VECTOR (15 downto 0));
end sdramcontroller;
architecture Behavioral of sdramcontroller is
type stateType is
(
init0, init1, init2, init3, init4, init5, init6, init7, init8,
idle, decoding,
read1, read2, read3, read4, read5, read6,
write1, write2, write3, write4, write5, write6
);
signal currentState : stateType := init0;
signal writeBuffer : STD_LOGIC_VECTOR (7 downto 0) := (others => '0');
constant cmdCommandInhibit : std_logic_vector (3 downto 0) := "1000";
constant cmdNOP : std_logic_vector (3 downto 0) := "0111";
constant cmdActive : std_logic_vector (3 downto 0) := "0011";
constant cmdRead : std_logic_vector (3 downto 0) := "0101";
constant cmdWrite : std_logic_vector (3 downto 0) := "0100";
constant cmdBurstTerminate : std_logic_vector (3 downto 0) := "0110";
constant cmdPrecharge : std_logic_vector (3 downto 0) := "0010";
constant cmdAutoRefresh : std_logic_vector (3 downto 0) := "0001";
constant cmdLoadMoadReg : std_logic_vector (3 downto 0) := "0000";
signal chipCmd : std_logic_vector (3 downto 0) := "UUUU";
signal waitCounter : std_logic_vector (31 downto 0) := (others => '0');
signal writeChipDataEnable : std_logic := '0';
begin
--chipClk <= clk;
--chipCke <= '1';
chipCS <= chipCmd(3);
chipRAS <= chipCmd(2);
chipCAS <= chipCmd(1);
chipWE <= chipCmd(0);
chipDATA <= "00000000" & writeBuffer when (writeChipDataEnable = '1') else (others => 'Z');
mainproc:
process (clk)
begin
if (falling_edge(clk) and currentState = read5) then
-- put the lower bits of data on the bus (we store 8 bit words in 16 bits)
dataOut <= chipDATA(7 downto 0);
end if;
if (rising_edge(clk)) then
case (currentState) is
when init0 =>
ready <= '0';
-- wait 100 ms and send NOP then init1
--if (waitCounter = 10) then
if (waitCounter = 14000000) then
-- set once since the address bus is only 16 bits, so we are only ever using one bank of memory
chipCmd <= cmdNOP;
currentState <= init1;
waitCounter <= (others => '0');
else
waitCounter <= waitCounter + 1;
end if;
when init1 =>
-- send PRECHARGE ALL
chipBA <= "00";
chipCmd <= cmdPrecharge;
chipADDR <= "010000000000";
currentState <= init2;
when init2 =>
-- wait tRP while sending NOP
if (waitCounter = 3) then
currentState <= init3;
waitCounter <= (others => '0');
else
chipCmd <= cmdNOP;
waitCounter <= waitCounter + 1;
end if;
when init3 =>
-- send AUTO REFRESH
chipCmd <= cmdAutoRefresh;
currentState <= init4;
when init4 =>
-- wait tRFC sending NOP
if (waitCounter = 8) then -- 66ns
currentState <= init5;
waitCounter <= (others => '0');
else
chipCmd <= cmdNOP;
waitCounter <= waitCounter + 1;
end if;
when init5 =>
-- send AUTO REFRESH
chipCmd <= cmdAutoRefresh;
currentState <= init6;
when init6 =>
-- wait tRFC sending NOP
if (waitCounter = 9) then -- 66ns
currentState <= init7;
waitCounter <= (others => '0');
else
chipCmd <= cmdNOP;
waitCounter <= waitCounter + 1;
end if;
when init7 =>
-- send LOAD MODE REGISTER
chipADDR <= "001000100000";
chipCmd <= cmdLoadMoadReg;
currentState <= init8;
when init8 =>
-- wait tMRD sending NOP, then we're ready!
if (waitCounter = 15) then -- 2 * tCK
currentState <= idle;
waitCounter <= (others => '0');
else
chipCmd <= cmdNOP;
waitCounter <= waitCounter + 1;
end if;
when idle =>
ready <= '1';
writeChipDataEnable <= '0';
currentState <= idle;
if (cmd /= "00") then
ready <= '0';
currentState <= decoding;
end if;
when decoding =>
-- send active
chipCmd <= cmdActive;
-- set row in a0 - a11
chipADDR(11 downto 8) <= "0000";
chipADDR(7 downto 0) <= addr(15 downto 8);
-- set bank in BA0/1 (already done once)
case (cmd) is
when "01" => -- read
currentState <= read1;
when "11" => -- write
currentState <= write1;
when others =>
chipCmd <= cmdNOP;
currentState <= idle;
end case;
when read1 =>
chipCmd <= cmdNOP;
chipDQMH <= '0';
chipDQML <= '0';
currentState <= read2;
when read2 =>
chipCmd <= cmdRead;
-- set column in a0 - a7
chipADDR(7 downto 0) <= addr(7 downto 0);
-- set a10 low (no auto precharge)
chipADDR(10) <= '0';
currentState <= read3;
when read3 =>
chipCmd <= cmdNOP;
currentState <= read4;
when read4 =>
currentState <= read5;
when read5 =>
-- send precharge
chipCmd <= cmdPrecharge;
chipADDR <= "001000000000";
currentState <= read6;
when read6 =>
-- one more NOP
chipCmd <= cmdNOP;
-- go idle
currentState <= idle;
when write1 =>
chipCmd <= cmdNOP;
writeBuffer(7 downto 0) <= dataIn;
writeChipDataEnable <= '1';
currentState <= write2;
chipDQMH <= '0';
chipDQML <= '0';
-- set column in a0 - a7
chipADDR(7 downto 0) <= addr(7 downto 0);
-- set a10 low (no auto precharge)
chipADDR(10) <= '0';
when write2 =>
chipCmd <= cmdWrite;
currentState <= write3;
when write3 =>
chipCmd <= cmdNOP;
currentState <= write4;
when write4 =>
chipCmd <= cmdNOP;
currentState <= write5;
when write5 =>
-- send precharge
chipCmd <= cmdPrecharge;
chipADDR <= "001000000000";
currentState <= write6;
when write6 =>
-- one more NOP
chipCmd <= cmdNOP;
-- go idle
currentState <= idle;
end case;
end if;
end process mainproc;
end Behavioral;
| mit | 4ca20a04535d33678484f9f167768fc5 | 0.602151 | 3.259015 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/rom.vhd | 1 | 5,331 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file rom.vhd when simulating
-- the core, rom. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY rom IS
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END rom;
ARCHITECTURE rom_a OF rom IS
-- synthesis translate_off
COMPONENT wrapped_rom
PORT (
clka : IN STD_LOGIC;
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_rom USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 13,
c_addrb_width => 13,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "rom.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 3,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 8192,
c_read_depth_b => 8192,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 8192,
c_write_depth_b => 8192,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_rom
PORT MAP (
clka => clka,
addra => addra,
douta => douta
);
-- synthesis translate_on
END rom_a;
| mit | 037da7565ccb39f00808d9880c90efaa | 0.525417 | 4.002252 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_sim/usb_test_nano2.vhd | 1 | 5,337 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2015-01-27
-- Author: Gideon
-- Description: Testcase 2 for USB host
-- This testcase initializes a repeated IN transfer in Circular Mem Buffer mode
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_bfm_pkg.all;
use work.tl_sctb_pkg.all;
use work.usb_cmd_pkg.all;
use work.tl_string_util_pkg.all;
entity usb_test_nano2 is
end entity;
architecture arch of usb_test_nano2 is
signal clocks_stopped : boolean := false;
constant Pipe_Command : unsigned(19 downto 0) := X"005F0"; -- 2F8 * 2 (pipe 3)
constant Pipe_DevEP : unsigned(19 downto 0) := X"005F2";
constant Pipe_Length : unsigned(19 downto 0) := X"005F4";
constant Pipe_MaxTrans : unsigned(19 downto 0) := X"005F6";
constant Pipe_Interval : unsigned(19 downto 0) := X"005F8";
constant Pipe_IntCount : unsigned(19 downto 0) := X"005FA";
constant Pipe_SplitCtl : unsigned(19 downto 0) := X"005FC";
constant Pipe_Result : unsigned(19 downto 0) := X"005FE";
constant Attr_Fifo_Base : unsigned(19 downto 0) := X"00640"; -- 320 * 2
constant Attr_Fifo_Tail_Address : unsigned(19 downto 0) := X"007F0"; -- 3f8 * 2
constant Attr_Fifo_Head_Address : unsigned(19 downto 0) := X"007F2"; -- 3f9 * 2
constant Circ_MemAddr_Start_High : unsigned(19 downto 0) := X"007C0"; -- 3e0
constant Circ_MemAddr_Start_Low : unsigned(19 downto 0) := X"007C2";
constant Circ_Size : unsigned(19 downto 0) := X"007C4";
constant Circ_Offset : unsigned(19 downto 0) := X"007C6";
constant MemBlock_Base_High : unsigned(19 downto 0) := X"007C8";
constant MemBlock_Base_Low : unsigned(19 downto 0) := X"007CA";
begin
i_harness: entity work.usb_harness_nano
port map (
clocks_stopped => clocks_stopped );
process
variable io : p_io_bus_bfm_object;
variable data : std_logic_vector(15 downto 0);
variable res : std_logic_vector(7 downto 0);
variable attr_fifo_tail : integer := 0;
variable attr_fifo_head : integer := 0;
procedure io_write_word(addr : unsigned(19 downto 0); word : std_logic_vector(15 downto 0)) is
begin
io_write(io => io, addr => addr, data => word(7 downto 0));
io_write(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure io_read_word(addr : unsigned(19 downto 0); variable word : out std_logic_vector(15 downto 0)) is
begin
io_read(io => io, addr => addr, data => word(7 downto 0));
io_read(io => io, addr => (addr + 1), data => word(15 downto 8));
end procedure;
procedure read_attr_fifo(result : out std_logic_vector(15 downto 0)) is
variable data : std_logic_vector(15 downto 0);
begin
L1: while true loop
io_read_word(addr => Attr_Fifo_Head_Address, word => data);
attr_fifo_head := to_integer(unsigned(data));
if (attr_fifo_head /= attr_fifo_tail) then
exit L1;
end if;
end loop;
io_read_word(addr => (Attr_Fifo_Base + attr_fifo_tail*2), word => result);
attr_fifo_tail := attr_fifo_tail + 1;
if attr_fifo_tail = 128 then
attr_fifo_tail := 0;
end if;
end procedure;
-- procedure wait_command_done is
-- begin
-- L1: while true loop
-- io_read(io => io, addr => Command, data => res);
-- if res = X"00" then
-- exit L1;
-- end if;
-- end loop;
-- end procedure;
begin
bind_io_bus_bfm("io", io);
sctb_open_simulation("path::path", "usb_test_nano2.tcr");
sctb_open_region("Testing Setup request", 0);
sctb_set_log_level(c_log_level_trace);
wait for 70 ns;
io_write(io => io, addr => X"007fe", data => X"01" ); -- set nano to simulation mode
io_write(io => io, addr => X"007fc", data => X"02" ); -- set bus speed to HS
io_write(io => io, addr => X"00800", data => X"01" ); -- enable nano
wait for 4 us;
io_write_word(Circ_Size, X"0040"); -- 64 bytes, only 4 entries and then we will wrap (test)
io_write_word(Circ_MemAddr_Start_High, X"0012");
io_write_word(Circ_MemAddr_Start_Low, X"6460"); -- 126460 is base :)
io_write_word(Pipe_DevEP, X"0007"); -- EP7: NAK NAK DATA0 NAK NAK DATA1 NAK STALL
io_write_word(Pipe_MaxTrans, X"0010");
io_write_word(Pipe_Interval, X"0002"); -- every other microframe
io_write_word(Pipe_Length, X"0010");
io_write_word(Pipe_Command, X"5042"); -- in with mem write, using cercular buffer
for i in 1 to 16 loop
read_attr_fifo(data);
sctb_trace("Fifo read: " & hstr(data));
end loop;
wait for 1 ms;
sctb_close_region;
clocks_stopped <= true;
wait;
end process;
end arch;
| gpl-3.0 | e459fca06f5e6e8bf659063f4a5a4ab1 | 0.557055 | 3.508876 | false | true | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/IntermediateFifoConv.vhd | 1 | 1,967 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_F8MKfI
-- /___/ /\ Timestamp : 04/05/2014 20:58:17
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use work.RetinaParameters.ALL;
entity IntermediateFifoConv is
port ( clk : in std_logic;
rst : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_VERT_CONV_BW-1 downto 0);
enableOut : out std_logic;
outputData : out std_logic_vector (OUT_VERT_CONV_BW-1 downto 0)
);
end IntermediateFifoConv;
architecture BEHAVIORAL of IntermediateFifoConv is
type T_SCALE_VALUES_FIFO is array (NUMBER_OF_SCALES-1 downto 0) of std_logic_vector(OUT_VERT_CONV_BW-1 downto 0);
signal intermediate_fifo: T_SCALE_VALUES_FIFO := (others => (others => '0'));
signal counter: integer range 0 to NUMBER_OF_SCALES-1 := 0;
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
intermediate_fifo <= (others => (others => '0'));
enableOut <= '0';
counter <= 0;
else
if enableIn = '1' then
-------WORKS ONLY FOR NUMBER_OF_SCALES > 2 ??????
intermediate_fifo(0) <= inputValue;
for i in 1 to NUMBER_OF_SCALES-1 loop
intermediate_fifo(i) <= intermediate_fifo(i-1);
end loop;
if counter = NUMBER_OF_SCALES-1 then
enableOut <= '1';
counter <= 0;
else
counter <= counter +1;
enableOut <= '0';
end if;
else
enableOut <= '0';
end if;
end if;
end if;
end process;
outputData <= intermediate_fifo(NUMBER_OF_SCALES-1);
end BEHAVIORAL;
| gpl-3.0 | 9121a30715ba44baa04fdbf888dba55b | 0.541942 | 3.208809 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/blahram.vhd | 5 | 2,526 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dpram is
generic (
g_ram_size : natural := 13 );
port (
clock_a : in std_logic;
enable_a : in std_logic;
write_a : in std_logic;
address_a : in unsigned(g_ram_size-1 downto 2);
din_a : in unsigned(31 downto 0);
dout_a : out unsigned(31 downto 0);
clock_b : in std_logic;
enable_b : in std_logic;
write_b : in std_logic;
address_b : in unsigned(g_ram_size-1 downto 2);
din_b : in unsigned(31 downto 0);
dout_b : out unsigned(31 downto 0) );
attribute keep_hierarchy : string;
attribute keep_hierarchy of dpram : entity is "yes";
end dpram;
architecture rtl of dpram is
constant c_num_words : integer := 2 ** (g_ram_size - 2);
type t_ram is array (0 to c_num_words-1) of unsigned(31 downto 0);
shared variable ram: t_ram := (others => X"00000000");
attribute ram_style : string;
attribute ram_style of ram : variable is "block";
begin
p_port_a: process (clock_a)
begin
if rising_edge(clock_a) then
if enable_a = '1' then
if write_a = '1' then
ram(to_integer(address_a)) := din_a;
-- synthesis translate_off
for i in din_a'range loop
assert din_a(i) = '0' or din_a(i) = '1'
report "Bit " & integer'image(i) & " is not 0 or 1."
severity failure;
end loop;
-- synthesis translate_on
end if;
dout_a <= ram(to_integer(address_a));
end if;
end if;
end process;
p_port_b: process (clock_b)
begin
if rising_edge(clock_b) then
if enable_b = '1' then
if write_b = '1' then
ram(to_integer(address_b)) := din_b;
-- synthesis translate_off
for i in din_b'range loop
assert din_b(i) = '0' or din_b(i) = '1'
report "Bit " & integer'image(i) & " is not 0 or 1, writing B."
severity failure;
end loop;
-- synthesis translate_on
end if;
dout_b <= ram(to_integer(address_b));
end if;
end if;
end process;
end architecture;
| gpl-3.0 | ef91ff3fac2e4c95be41d00f7e835239 | 0.483373 | 3.645022 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/spi/vhdl_sim/tb_spi.vhd | 5 | 2,700 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_spi is
end tb_spi;
architecture tb of tb_spi is
signal clock : std_logic := '0';
signal reset : std_logic;
signal do_send : std_logic;
signal force_ss : std_logic := '0';
signal level_ss : std_logic := '0';
signal busy : std_logic;
signal rate : std_logic_vector(7 downto 0) := X"01";
signal cpol : std_logic := '0';
signal cpha : std_logic := '0';
signal wdata : std_logic_vector(7 downto 0);
signal rdata : std_logic_vector(7 downto 0);
signal SPI_SSn : std_logic;
signal SPI_CLK : std_logic;
signal SPI_MOSI : std_logic;
--signal SPI_MISO : std_logic;
signal stop_clock : boolean := false;
signal clear_crc : std_logic := '0';
begin
clock <= not clock after 10 ns when not stop_clock;
reset <= '1', '0' after 100 ns;
mut: entity work.spi
port map (
clock => clock,
reset => reset,
do_send => do_send,
clear_crc => clear_crc,
force_ss => force_ss,
level_ss => level_ss,
busy => busy,
rate(8) => rate(7),
rate(7 downto 0) => rate,
cpol => cpol,
cpha => cpha,
wdata => wdata,
rdata => rdata,
SPI_SSn => SPI_SSn,
SPI_CLK => SPI_CLK,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MOSI );
test: process
procedure send_byte(byte: std_logic_vector) is
begin
wdata <= byte;
wait until clock='1';
if busy='1' then
wait until busy='0';
end if;
do_send <= '1';
wait until clock='1';
do_send <= '0';
end procedure;
begin
cpol <= '0';
cpha <= '0';
do_send <= '0';
wdata <= X"00";
wait until reset='0';
wait for 200 ns;
wait until clock='1';
clear_crc <= '1';
wait until clock='1';
clear_crc <= '0';
send_byte(X"40");
send_byte(X"00");
send_byte(X"00");
send_byte(X"00");
send_byte(X"00");
send_byte(X"95");
wait until busy='0';
wait for 200 ns;
stop_clock <= true;
wait;
end process;
end tb;
| gpl-3.0 | 39544e9be739beda569071fb69bfc1dd | 0.435556 | 3.835227 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/floppy.vhd | 4 | 4,957 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2006, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Floppy Emulator
-------------------------------------------------------------------------------
-- File : floppy.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements the emulator of the floppy drive.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity floppy is
generic (
g_tag : std_logic_vector(7 downto 0) := X"01" );
port (
sys_clock : in std_logic;
drv_clock_en : in std_logic; -- combi clk/cke that yields 4 MHz; eg. 16/4
drv_reset : in std_logic;
-- signals from MOS 6522 VIA
motor_on : in std_logic;
mode : in std_logic;
write_prot_n : in std_logic;
step : in std_logic_vector(1 downto 0);
soe : in std_logic;
rate_ctrl : in std_logic_vector(1 downto 0);
byte_ready : out std_logic;
sync : out std_logic;
read_data : out std_logic_vector(7 downto 0);
write_data : in std_logic_vector(7 downto 0);
track : out std_logic_vector(6 downto 0);
track_is_0 : out std_logic;
-- signals connected to sd-cpu
cpu_write : in std_logic;
cpu_ram_en : in std_logic;
cpu_addr : in std_logic_vector(10 downto 0);
cpu_wdata : in std_logic_vector(7 downto 0);
cpu_rdata : out std_logic_vector(7 downto 0);
---
floppy_inserted : in std_logic := '0';
do_head_bang : out std_logic;
do_track_out : out std_logic;
do_track_in : out std_logic;
en_hum : out std_logic;
en_slip : out std_logic;
---
mem_req : out t_mem_req;
mem_resp : in t_mem_resp );
end floppy;
architecture structural of floppy is
signal drv_rdata : std_logic_vector(7 downto 0);
signal do_read : std_logic;
signal do_write : std_logic;
signal do_advance : std_logic;
signal track_start : std_logic_vector(25 downto 0);
signal max_offset : std_logic_vector(13 downto 0);
signal track_i : std_logic_vector(6 downto 0);
signal bit_time : unsigned(8 downto 0);
begin
en_hum <= motor_on and not floppy_inserted;
en_slip <= motor_on and floppy_inserted;
track <= track_i;
stream: entity work.floppy_stream
port map (
clock => sys_clock,
clock_en => drv_clock_en, -- combi clk/cke that yields 4 MHz; eg. 16/4
reset => drv_reset,
drv_rdata => drv_rdata, -- from memory
do_read => do_read,
do_write => do_write,
do_advance => do_advance,
floppy_inserted => floppy_inserted,
track => track_i,
track_is_0 => track_is_0,
do_head_bang => do_head_bang,
do_track_in => do_track_in,
do_track_out => do_track_out,
motor_on => motor_on,
sync => sync,
mode => mode,
write_prot_n => write_prot_n,
step => step,
byte_ready => byte_ready,
soe => soe,
rate_ctrl => rate_ctrl,
bit_time => bit_time,
read_data => read_data );
params: entity work.floppy_param_mem
port map (
clock => sys_clock,
reset => drv_reset,
cpu_write => cpu_write,
cpu_ram_en => cpu_ram_en,
cpu_addr => cpu_addr,
cpu_wdata => cpu_wdata,
cpu_rdata => cpu_rdata,
track => track_i,
track_start => track_start,
max_offset => max_offset,
bit_time => bit_time );
fetch_wb: entity work.floppy_mem
generic map (
g_tag => g_tag )
port map (
clock => sys_clock,
reset => drv_reset,
drv_rdata => drv_rdata,
drv_wdata => write_data,
do_read => do_read,
do_write => do_write,
do_advance => do_advance,
track_start => track_start,
max_offset => max_offset,
mem_req => mem_req,
mem_resp => mem_resp );
end structural;
| gpl-3.0 | 04988bc6e136d36626d5dbb37f6b6fad | 0.446439 | 3.842636 | false | false | false | false |
KB777/1541UltimateII | fpga/io/c2n_record/vhdl_source/c2n_record.vhd | 1 | 8,230 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity c2n_record is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
irq : out std_logic;
phi2_tick : in std_logic;
c64_stopped : in std_logic;
pull_sense : out std_logic;
c2n_motor : in std_logic;
c2n_sense : in std_logic;
c2n_read : in std_logic;
c2n_write : in std_logic );
end c2n_record;
architecture gideon of c2n_record is
signal stream_en : std_logic;
signal mode : std_logic_vector(1 downto 0);
signal sel : std_logic;
signal read_s : std_logic;
signal read_c : std_logic;
signal read_d : std_logic;
signal read_event : std_logic;
signal enabled : std_logic;
signal counter : unsigned(23 downto 0);
signal diff : unsigned(23 downto 0);
signal remain : unsigned(2 downto 0);
signal error : std_logic;
signal irq_en : std_logic;
signal status : std_logic_vector(7 downto 0);
signal fifo_din : std_logic_vector(7 downto 0);
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal fifo_flush : std_logic;
signal fifo_write : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 63;
type t_state is (idle, listen, encode, multi1, multi2, multi3);
signal state : t_state;
signal state_enc : std_logic_vector(1 downto 0);
attribute register_duplication : string;
attribute register_duplication of stream_en : signal is "no";
attribute register_duplication of read_c : signal is "no";
begin
pull_sense <= sel and enabled;
filt: entity work.spike_filter generic map (10) port map(clock, read_s, read_c);
process(clock)
variable v_diff : unsigned(10 downto 0);
begin
if rising_edge(clock) then
if fifo_full='1' and enabled='1' then
error <= '1';
end if;
-- signal capture
stream_en <= c2n_sense and enabled and c2n_motor;
read_s <= (c2n_read and not sel) or (c2n_write and sel);
read_d <= read_c;
case mode is
when "00" =>
read_event <= read_c and not read_d; -- rising edge
when "01" =>
read_event <= not read_c and read_d; -- falling edge
when others =>
read_event <= read_c xor read_d; -- both edges
end case;
-- filter for false pulses
-- if counter(23 downto 4) = X"00000" then
-- read_event <= '0';
-- end if;
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1'; -- ack for fifo write as well.
if req.address(11)='0' then
enabled <= req.data(0);
if req.data(0)='0' and enabled='1' then -- getting disabled
read_event <= '1'; -- why??
end if;
if req.data(1)='1' then
error <= '0';
end if;
fifo_flush <= req.data(2);
mode <= req.data(5 downto 4);
sel <= req.data(6);
irq_en <= req.data(7);
end if;
elsif req.read='1' then
resp.ack <= '1';
if req.address(11)='0' then
resp.data <= status;
else
resp.data <= fifo_dout;
end if;
end if;
irq <= irq_en and fifo_almostfull;
-- listening process
if stream_en='1' then
if phi2_tick='1' then
counter <= counter + 1;
end if;
else
counter <= (others => '0');
end if;
fifo_write <= '0';
case state is
when idle =>
if stream_en='1' then
state <= listen;
end if;
when listen =>
if read_event='1' then
diff <= counter;
if phi2_tick='1' then
counter <= to_unsigned(1, counter'length);
else
counter <= to_unsigned(0, counter'length);
end if;
state <= encode;
elsif enabled='0' then
state <= idle;
end if;
when encode =>
fifo_write <= '1';
if diff > 2040 then
fifo_din <= X"00";
state <= multi1;
else
v_diff := diff(10 downto 0) + remain;
if v_diff(10 downto 3) = X"00" then
fifo_din <= X"01";
else
fifo_din <= std_logic_vector(v_diff(10 downto 3));
end if;
remain <= v_diff(2 downto 0);
state <= listen;
end if;
when multi1 =>
fifo_din <= std_logic_vector(diff(7 downto 0));
fifo_write <= '1';
state <= multi2;
when multi2 =>
fifo_din <= std_logic_vector(diff(15 downto 8));
fifo_write <= '1';
state <= multi3;
when multi3 =>
fifo_din <= std_logic_vector(diff(23 downto 16));
fifo_write <= '1';
state <= listen;
when others =>
null;
end case;
if reset='1' then
fifo_din <= (others => '0');
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
mode <= "00";
sel <= '0';
remain <= "000";
irq_en <= '0';
end if;
end if;
end process;
fifo_read <= '1' when req.read='1' and req.address(11)='1' else '0';
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 512,
g_storage => "block",
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => fifo_din,
dout => fifo_dout,
flush => fifo_flush,
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= state_enc(0);
status(5) <= state_enc(1);
status(6) <= stream_en;
status(7) <= not fifo_empty;
with state select state_enc <=
"00" when idle,
"01" when multi1,
"01" when multi2,
"01" when multi3,
"10" when listen,
"11" when others;
end gideon;
| gpl-3.0 | dc7049c5c5266a6140149988d0979e0e | 0.412515 | 4.275325 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_source/mash.vhd | 5 | 2,882 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mash is
generic (
g_order : positive := 2;
g_width : positive := 16 );
port (
clock : in std_logic;
enable : in std_logic := '1';
reset : in std_logic;
dac_in : in unsigned(g_width-1 downto 0);
dac_out : out integer range 0 to (2**g_order)-1);
end entity;
architecture gideon of mash is
type t_accu_array is array(natural range <>) of unsigned(g_width-1 downto 0);
signal accu : t_accu_array(0 to g_order-1);
signal carry : std_logic_vector(0 to g_order-1);
signal sum : t_accu_array(0 to g_order-1);
subtype t_delta_range is integer range -(2**(g_order-1)) to (2**(g_order-1));
type t_int_array is array(natural range <>) of t_delta_range;
signal delta : t_int_array(0 to g_order-1) := (others => 0);
signal delta_d : t_int_array(0 to g_order-1) := (others => 0);
procedure sum_with_carry(a, b : unsigned; y : out unsigned; c : out std_logic ) is
variable a_ext : unsigned(a'length downto 0);
variable b_ext : unsigned(a'length downto 0);
variable summed : unsigned(a'length downto 0);
begin
a_ext := '0' & a;
b_ext := '0' & b;
summed := a_ext + b_ext;
c := summed(summed'left);
y := summed(a'length-1 downto 0);
end procedure;
function count_deltas(a : std_logic; b : t_delta_range; c : t_delta_range) return t_delta_range is
begin
if a = '1' then
return 1 + b - c;
end if;
return b - c;
end function;
begin
process(accu, dac_in, carry, delta, delta_d, sum)
variable a : unsigned(dac_in'range);
variable y : unsigned(dac_in'range);
variable c : std_logic;
begin
for i in 0 to g_order-1 loop
if i=0 then
a := dac_in;
else
a := sum(i-1);
end if;
sum_with_carry(a, accu(i), y, c);
sum(i) <= y;
carry(i) <= c;
if i = g_order-1 then
delta(i) <= count_deltas(carry(i), 0, 0);
else
delta(i) <= count_deltas(carry(i), delta(i+1), delta_d(i+1));
end if;
end loop;
end process;
dac_out <= delta_d(0) + (2 ** (g_order-1) - 1);
process(clock)
begin
if rising_edge(clock) then
if enable='1' then
accu <= sum;
delta_d <= delta;
end if;
if reset='1' then
accu <= (others => (others => '0'));
delta_d <= (others => 0);
end if;
end if;
end process;
end gideon;
| gpl-3.0 | d28a94d9bfdd432fe5472b0e13cf74d7 | 0.48508 | 3.426873 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/uart_lite/vhdl_source/uart_peripheral_io.vhd | 3 | 5,157 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity uart_peripheral_io is
generic (
g_tx_fifo : boolean := true;
g_divisor : natural := 417 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
txd : out std_logic;
rxd : in std_logic := '1';
rts : out std_logic;
cts : in std_logic := '1' );
end uart_peripheral_io;
architecture gideon of uart_peripheral_io is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxfifo_get : std_logic;
signal rxfifo_dout : std_logic_vector(7 downto 0);
signal rxfifo_full : std_logic;
signal rxfifo_dav : std_logic;
signal overflow : std_logic;
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(7 downto 6);
signal rdata_mux : std_logic_vector(7 downto 0);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
constant c_uart_data : unsigned(1 downto 0) := "00";
constant c_uart_get : unsigned(1 downto 0) := "01";
constant c_uart_flags : unsigned(1 downto 0) := "10";
constant c_uart_imask : unsigned(1 downto 0) := "11";
begin
my_tx: entity work.tx
generic map (g_divisor)
port map (
clk => clock,
reset => reset,
dotx => dotx,
txchar => txchar,
cts => cts,
txd => txd,
done => done );
my_rx: entity work.rx
generic map (g_divisor)
port map (
clk => clock,
reset => reset,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
my_rxfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => rxfifo_get,
PutElement => rx_ack,
FlushFifo => '0',
DataIn => rxchar,
DataOut => rxfifo_dout,
SpaceInFifo => open,
AlmostFull => rxfifo_full,
DataInFifo => rxfifo_dav );
gentx: if g_tx_fifo generate
my_txfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => txfifo_get,
PutElement => txfifo_put,
FlushFifo => '0',
DataIn => io_req.data,
DataOut => txfifo_dout,
SpaceInFifo => open,
AlmostFull => txfifo_full,
DataInFifo => txfifo_dav );
end generate;
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
io_resp <= c_io_resp_init;
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
txfifo_put <= '0';
if g_tx_fifo then
dotx <= txfifo_dav and done and not dotx;
txchar <= txfifo_dout;
else
dotx <= '0'; -- default, overridden with write
end if;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(1 downto 0) is
when c_uart_data => -- dout
if not g_tx_fifo then
txchar <= io_req.data;
dotx <= '1';
else -- there is a fifo
txfifo_put <= '1';
end if;
when c_uart_get => -- din
rxfifo_get <= '1';
when c_uart_flags => -- clear flags
overflow <= overflow and not io_req.data(0);
when c_uart_imask => -- interrupt control
imask <= io_req.data(7 downto 6);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
io_resp.data <= rdata_mux;
end if;
if (flags(7 downto 6) and imask) /= "00" then
io_resp.irq <= '1';
else
io_resp.irq <= '0';
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= '0';
flags(3) <= '0';
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
rts <= not rxfifo_full;
with io_req.address(1 downto 0) select rdata_mux <=
rxfifo_dout when c_uart_data,
flags when c_uart_flags,
imask & "000000" when c_uart_imask,
X"00" when others;
end gideon;
| gpl-3.0 | 9fb389a98af5485ee99e6a3e21318ef7 | 0.492728 | 3.379423 | false | false | false | false |
pemb/siphash | sipround.vhd | 1 | 1,073 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.siphash_package.all;
entity sipround is
port (
v0_in, v1_in, v2_in, v3_in : in std_logic_vector(V_WIDTH-1 downto 0);
v0_out, v1_out, v2_out, v3_out : out std_logic_vector(V_WIDTH-1 downto 0)
);
end entity;
architecture rtl of sipround is
begin
process(v0_in, v1_in, v2_in, v3_in)
variable v0, v1, v2, v3 : unsigned(V_WIDTH-1 downto 0);
begin
v0 := unsigned(v0_in);
v1 := unsigned(v1_in);
v2 := unsigned(v2_in);
v3 := unsigned(v3_in);
v0 := v0 + v1;
v2 := v2 + v3;
v1 := rotate_left(v1, 13);
v3 := rotate_left(v3, 16);
v1 := v1 xor v0;
v3 := v3 xor v2;
v0 := rotate_left(v0, 32);
v0 := v0 + v3;
v2 := v2 + v1;
v1 := rotate_left(v1, 17);
v3 := rotate_left(v3, 21);
v1 := v1 xor v2;
v3 := v3 xor v0;
v2 := rotate_left(v2, 32);
v0_out <= std_logic_vector(v0);
v1_out <= std_logic_vector(v1);
v2_out <= std_logic_vector(v2);
v3_out <= std_logic_vector(v3);
end process;
end;
| gpl-3.0 | 9c37ca738e81d89063e44f68d3689763 | 0.5685 | 2.358242 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op961_17.vhdl | 1 | 6,411 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net7
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net7,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net9
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net10
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net11
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net11,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net12,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net12
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 87ff228ecce795c43eeb8584e9398fd2 | 0.577445 | 3.110626 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op970_5.vhdl | 1 | 4,600 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net4,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net3,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias4,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 42c7fb7afb9afd38ab17b3dd979c32ff | 0.582391 | 3.214535 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_source/data_oper.vhd | 3 | 5,855 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.pkg_6502_decode.all;
-- this module puts the alu, shifter and bit/compare unit together
entity data_oper is
generic (
support_bcd : boolean := true );
port (
inst : in std_logic_vector(7 downto 0);
n_in : in std_logic;
v_in : in std_logic;
z_in : in std_logic;
c_in : in std_logic;
d_in : in std_logic;
i_in : in std_logic;
data_in : in std_logic_vector(7 downto 0);
a_reg : in std_logic_vector(7 downto 0);
x_reg : in std_logic_vector(7 downto 0);
y_reg : in std_logic_vector(7 downto 0);
s_reg : in std_logic_vector(7 downto 0);
alu_out : out std_logic_vector(7 downto 0);
mem_out : out std_logic_vector(7 downto 0);
impl_out : out std_logic_vector(7 downto 0);
set_a : out std_logic;
set_x : out std_logic;
set_y : out std_logic;
set_s : out std_logic;
n_out : out std_logic;
v_out : out std_logic;
z_out : out std_logic;
c_out : out std_logic;
d_out : out std_logic;
i_out : out std_logic );
end data_oper;
architecture gideon of data_oper is
signal shift_sel : std_logic_vector(1 downto 0) := "00";
signal shift_din : std_logic_vector(7 downto 0) := X"00";
signal shift_dout: std_logic_vector(7 downto 0) := X"00";
signal alu_data_a: std_logic_vector(7 downto 0) := X"00";
signal row0_n : std_logic;
signal row0_v : std_logic;
signal row0_z : std_logic;
signal row0_c : std_logic;
signal shft_n : std_logic;
signal shft_z : std_logic;
signal shft_c : std_logic;
signal alu_n : std_logic;
signal alu_v : std_logic;
signal alu_z : std_logic;
signal alu_c : std_logic;
signal impl_n : std_logic;
signal impl_z : std_logic;
signal impl_c : std_logic;
signal impl_v : std_logic;
signal impl_i : std_logic;
signal impl_d : std_logic;
signal shift_en : std_logic;
signal alu_en : std_logic;
signal impl_en : std_logic;
signal impl_flags: boolean;
begin
shift_sel <= shifter_in_select(inst);
with shift_sel select shift_din <=
data_in when "01",
a_reg when "10",
data_in and a_reg when "11",
X"FF" when others;
shift_en <= '1' when is_shift(inst) else '0';
alu_en <= '1' when is_alu(inst) else '0';
row0: entity work.bit_cpx_cpy
port map (
operation => inst(7 downto 5),
enable => '1',
n_in => n_in,
v_in => v_in,
z_in => z_in,
c_in => c_in,
data_in => data_in,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
n_out => row0_n,
v_out => row0_v,
z_out => row0_z,
c_out => row0_c );
shft: entity work.shifter
port map (
operation => inst(7 downto 5),
enable => shift_en,
c_in => c_in,
n_in => n_in,
z_in => z_in,
data_in => shift_din,
c_out => shft_c,
n_out => shft_n,
z_out => shft_z,
data_out => shift_dout );
alu_data_a <= a_reg and x_reg when x_to_alu(inst) else a_reg;
alu1: entity work.alu
generic map (
support_bcd => support_bcd )
port map (
operation => inst(7 downto 5),
enable => alu_en,
n_in => shft_n,
v_in => v_in,
z_in => shft_z,
c_in => shft_c,
d_in => d_in,
data_a => alu_data_a,
data_b => shift_dout,
n_out => alu_n,
v_out => alu_v,
z_out => alu_z,
c_out => alu_c,
data_out => alu_out );
mem_out <= shift_dout;
impl_en <= '1' when is_implied(inst) else '0';
impl_flags <= is_implied(inst) and (inst(4)='1' or inst(7)='1');
impl: entity work.implied
port map (
inst => inst,
enable => impl_en,
c_in => c_in,
i_in => i_in,
n_in => n_in,
z_in => z_in,
d_in => d_in,
v_in => v_in,
reg_a => a_reg,
reg_x => x_reg,
reg_y => y_reg,
reg_s => s_reg,
i_out => impl_i,
d_out => impl_d,
c_out => impl_c,
n_out => impl_n,
z_out => impl_z,
v_out => impl_v,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
data_out => impl_out );
n_out <= impl_n when impl_flags else row0_n when inst(1 downto 0)="00" else alu_n;
v_out <= impl_v when impl_flags else row0_v when inst(1 downto 0)="00" else alu_v;
z_out <= impl_z when impl_flags else row0_z when inst(1 downto 0)="00" else alu_z;
c_out <= impl_c when impl_flags else row0_c when inst(1 downto 0)="00" else alu_c;
i_out <= impl_i when impl_flags else i_in;
d_out <= impl_d when impl_flags else d_in;
end gideon;
| gpl-3.0 | b35b6dcfe8fc4f567aae28c911f1dff7 | 0.438429 | 3.281951 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/spi_boot.vhd | 2 | 30,114 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: spi_boot.vhd,v 1.9 2007/02/25 18:24:12 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity spi_boot is
generic (
-- width of set selection
width_set_sel_g : integer := 4;
-- width of bit counter: minimum 6, maximum 12
width_bit_cnt_g : integer := 6;
-- width of image counter: minimum 0, maximum n
width_img_cnt_g : integer := 2;
-- number of bits required to address one image
num_bits_per_img_g : integer := 18;
-- SD specific initialization
sd_init_g : integer := 0;
-- clock divider to reach 400 kHz for MMC compatibility
mmc_compat_clk_div_g : integer := 0;
width_mmc_clk_div_g : integer := 0;
-- active level of reset_i
reset_level_g : integer := 0
);
port (
-- System Interface -------------------------------------------------------
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0);
-- Card Interface ---------------------------------------------------------
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
spi_en_outs_o : out std_logic;
-- FPGA Configuration Interface -------------------------------------------
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end spi_boot;
library ieee;
use ieee.numeric_std.all;
use work.spi_boot_pack.all;
architecture rtl of spi_boot is
component spi_counter
generic (
cnt_width_g : integer := 4;
cnt_max_g : integer := 15
);
port (
clk_i : in std_logic;
reset_i : in boolean;
cnt_en_i : in boolean;
cnt_o : out std_logic_vector(cnt_width_g-1 downto 0);
cnt_ovfl_o : out boolean
);
end component;
-----------------------------------------------------------------------------
-- States of the controller FSM
--
type ctrl_states_t is (POWER_UP1, POWER_UP2,
CMD0,
CMD1,
CMD55, ACMD41,
CMD16,
WAIT_START,
WAIT_INIT_LOW, WAIT_INIT_HIGH,
CMD18, CMD18_DATA,
CMD12,
INC_IMG_CNT);
--
signal ctrl_fsm_q,
ctrl_fsm_s : ctrl_states_t;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- States of the command FSM
--
type cmd_states_t is (CMD, START, R1, PAUSE);
--
signal cmd_fsm_q,
cmd_fsm_s : cmd_states_t;
--
-----------------------------------------------------------------------------
subtype op_r is integer range 5 downto 0;
type res_bc_t is (NONE, RES_MAX, RES_47, RES_15, RES_7);
signal bit_cnt_q : unsigned(width_bit_cnt_g-1 downto 0);
signal res_bc_s : res_bc_t;
signal upper_bitcnt_zero_s : boolean;
signal cfg_dat_q : std_logic;
signal spi_clk_q : std_logic;
signal spi_clk_rising_q : boolean;
signal spi_clk_falling_q : boolean;
signal spi_dat_q,
spi_dat_s : std_logic;
signal spi_cs_n_q,
spi_cs_n_s : std_logic;
signal cfg_clk_q : std_logic;
signal start_q : std_logic;
signal img_cnt_s : std_logic_vector(width_img_cnt_g downto 0);
signal cnt_en_img_s : boolean;
signal mmc_cnt_ovfl_s : boolean;
signal mmc_compat_s : boolean;
signal cmd_finished_s : boolean;
signal r1_result_q : std_logic;
signal done_q,
send_cmd12_q : boolean;
signal en_outs_s,
en_outs_q : boolean;
signal reset_s : boolean;
signal true_s : boolean;
begin
true_s <= true;
reset_s <= true
when (reset_level_g = 1 and reset_i = '1') or
(reset_level_g = 0 and reset_i = '0') else
false;
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements several sequential elements.
--
seq: process (clk_i, reset_s)
variable bit_cnt_v : unsigned(1 downto 0);
begin
if reset_s then
-- reset bit counter to 63 for power up
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "111111";
spi_dat_q <= '1';
spi_cs_n_q <= '1';
cfg_dat_q <= '1';
start_q <= '0';
done_q <= false;
send_cmd12_q <= false;
ctrl_fsm_q <= POWER_UP1;
cmd_fsm_q <= CMD;
r1_result_q <= '0';
en_outs_q <= false;
elsif clk_i'event and clk_i = '1' then
-- bit counter control
if spi_clk_rising_q then
case res_bc_s is
when NONE =>
bit_cnt_q <= bit_cnt_q - 1;
when RES_MAX =>
bit_cnt_q <= (others => '1');
when RES_47 =>
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "101111";
when RES_15 =>
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "001111";
when RES_7 =>
bit_cnt_q <= (others => '0');
bit_cnt_q(op_r) <= "000111";
when others =>
bit_cnt_q <= (others => '0');
end case;
end if;
-- Card data output register
-- spi_clk_falling_q acts as enable during MMC clock compatibility mode.
-- As soon as this mode is left, the register must start latching.
-- There is no explicit relation to spi_clk_q anymore in normal mode.
-- Instead, spi_dat_s is operated by bit_cnt_q above which changes its
-- value after the rising edge of spi_clk_q.
-- -> spi_dat_q changes upon falling edge of spi_clk_q
if spi_clk_falling_q or not mmc_compat_s then
spi_dat_q <= spi_dat_s;
end if;
-- config data output register
-- a new value is loaded when config clock is high,
-- i.e. input data is sampled with rising spi_clk
-- while output value changes on falling edge of cfg_clk
if cfg_clk_q = '1' and spi_clk_rising_q then
cfg_dat_q <= spi_data_in_i;
end if;
-- Controller FSM state
ctrl_fsm_q <= ctrl_fsm_s;
-- Command FSM state
cmd_fsm_q <= cmd_fsm_s;
-- CS signal for SPI card
if spi_clk_q = '1' then
spi_cs_n_q <= spi_cs_n_s;
end if;
-- Extract flags from R1 response
if cmd_fsm_q = R1 then
bit_cnt_v := bit_cnt_q(1 downto 0);
case bit_cnt_v(1 downto 0) is
when "10" =>
-- always save "Illegal Command" flag
r1_result_q <= to_X01(spi_data_in_i);
when "00" =>
-- overwrite with "Idle State" flag when not in CMD55
if ctrl_fsm_q /= CMD55 then
r1_result_q <= to_X01(spi_data_in_i);
end if;
when others =>
null;
end case;
end if;
-- Start trigger register for rising edge detection
-- the reset value is '0' thus a rising edge will always be detected
-- after reset even though start_i is tied to '1'
if start_i = '0' then
start_q <= '0';
elsif ctrl_fsm_q = WAIT_START and cmd_finished_s then
start_q <= start_i;
end if;
-- Marker for cfg_done and dat_done
if ctrl_fsm_q = CMD18_DATA then
if cfg_done_i = '1' and dat_done_i = '1' then
done_q <= true;
end if;
if done_q and
(not upper_bitcnt_zero_s or cmd_fsm_q = START) then
-- activate sending of CMD12 when it is safe:
-- * upper bits of bit counter are not zero
-- -> transmission of CMD12 is not running
-- * cmd FSM is in START state
-- -> also no transmission running
send_cmd12_q <= true;
end if;
elsif ctrl_fsm_q = WAIT_START then
-- reset done_q when WAIT_START has been reached
-- this is necessary to let the stop transmission process come to
-- an end without interruption or generation of unwanted cfg_clk_q
done_q <= false;
send_cmd12_q <= false;
end if;
-- output enable
if spi_clk_rising_q then
en_outs_q <= en_outs_s;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process upper_bits
--
-- Purpose:
-- Detects that the upper bits of the bit counter are zero.
-- Upper bits = n downto 6, i.e. the optional part that is not required for
-- commands but for extension of data blocks.
--
upper_bits: process (bit_cnt_q)
variable zero_v : boolean;
begin
zero_v := true;
for i in bit_cnt_q'high downto 6 loop
if bit_cnt_q(i) = '1' then
zero_v := false;
end if;
end loop;
upper_bitcnt_zero_s <= zero_v;
end process upper_bits;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process clk_gen
--
-- Purpose:
-- Generates clocks for card and FPGA configuration.
-- The card clock is free running with a divide by two of clk_i.
-- The clock for FPGA config has an enable and is stopped on high level.
-- There is a phase shift of half a period between spi_clk and cfg_clk.
--
clk_gen: process (clk_i, reset_s)
begin
if reset_s then
spi_clk_q <= '0';
cfg_clk_q <= '1';
elsif clk_i'event and clk_i = '1' then
-- spi_clk_q rises according to the flag
-- it falls with overflow indication
-- the resulting duty cycle is not exactly 50:50,
-- high time is a bit longer
if mmc_compat_s then
-- MMC clock compatibility mode:
-- spi_clk_q rises when flagged by spi_clk_rising_q
if spi_clk_rising_q then
spi_clk_q <= '1';
elsif mmc_cnt_ovfl_s then
-- upon counter overflow spi_clk_q falls in case it does not rise
spi_clk_q <= '0';
end if;
else
-- normal mode
-- spi_clk_q follows spi_clk_rising_q
if spi_clk_rising_q then
spi_clk_q <= '1';
else
spi_clk_q <= '0';
end if;
end if;
-- clock for FPGA config must be enabled and follows spi_clk
if ctrl_fsm_q = CMD18_DATA and cmd_fsm_q = CMD and
not done_q then
cfg_clk_q <= spi_clk_q;
else
cfg_clk_q <= '1';
end if;
end if;
end process clk_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Indication flags for rising and falling spi_clk_q.
-- Essential for MMC clock compatibility mode.
-----------------------------------------------------------------------------
mmc_comap: if mmc_compat_clk_div_g > 0 generate
mmc_compat_sig: process (clk_i, reset_s)
begin
if reset_s then
spi_clk_rising_q <= false;
spi_clk_falling_q <= false;
elsif clk_i'event and clk_i = '1' then
if mmc_compat_s then
-- MMC clock compatibility mode:
-- spi_clk_rising_q is an impulse right before rising edge of spi_clk_q
-- spi_clk_falling_q is an impulse right before falling edge of spi_clk_q
if mmc_cnt_ovfl_s then
spi_clk_rising_q <= spi_clk_q = '0';
spi_clk_falling_q <= spi_clk_q = '1';
else
spi_clk_rising_q <= false;
spi_clk_falling_q <= false;
end if;
else
-- normal mode
spi_clk_rising_q <= not spi_clk_rising_q;
spi_clk_falling_q <= true;
end if;
end if;
end process mmc_compat_sig;
end generate;
no_mmc_compat: if mmc_compat_clk_div_g = 0 generate
-- SPI clock rising whenever spi_clk_q is '0'
spi_clk_rising_q <= spi_clk_q = '0';
-- SPI clock falling whenever spi_clk_q is '1'
spi_clk_falling_q <= spi_clk_q = '1';
end generate;
-----------------------------------------------------------------------------
-- Process ctrl_fsm
--
-- Purpose:
-- Implements the controller FSM.
--
ctrl_fsm: process (ctrl_fsm_q,
cmd_finished_s, r1_result_q,
start_i, start_q, mode_i,
cfg_init_n_i)
variable mmc_compat_v : boolean;
begin
-- default assignments
ctrl_fsm_s <= POWER_UP1;
config_n_o <= '1';
cnt_en_img_s <= false;
spi_cs_n_s <= '0';
mmc_compat_v := false;
en_outs_s <= true;
case ctrl_fsm_q is
-- Let card finish power up, step 1 -------------------------------------
when POWER_UP1 =>
mmc_compat_v := true;
spi_cs_n_s <= '1';
if cmd_finished_s then
ctrl_fsm_s <= POWER_UP2;
else
ctrl_fsm_s <= POWER_UP1;
end if;
-- Let card finish power up, step 2 -------------------------------------
when POWER_UP2 =>
mmc_compat_v := true;
if cmd_finished_s then
ctrl_fsm_s <= CMD0;
else
spi_cs_n_s <= '1';
ctrl_fsm_s <= POWER_UP2;
end if;
-- Issue CMD0: GO_IDLE_STATE --------------------------------------------
when CMD0 =>
mmc_compat_v := true;
if cmd_finished_s then
if sd_init_g = 1 then
ctrl_fsm_s <= CMD55;
else
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= CMD0;
end if;
-- Issue CMD55: APP_CMD -------------------------------------------------
when CMD55 =>
if sd_init_g = 1 then
mmc_compat_v := true;
if cmd_finished_s then
if r1_result_q = '0' then
-- command accepted, it's an SD card
ctrl_fsm_s <= ACMD41;
else
-- command rejected, it's an MMC card
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= CMD55;
end if;
end if;
-- Issue ACMD41: SEND_OP_COND -------------------------------------------
when ACMD41 =>
if sd_init_g = 1 then
mmc_compat_v := true;
if cmd_finished_s then
if r1_result_q = '0' then
ctrl_fsm_s <= CMD16;
else
ctrl_fsm_s <= CMD55;
end if;
else
ctrl_fsm_s <= ACMD41;
end if;
end if;
-- Issue CMD1: SEND_OP_COND ---------------------------------------------
when CMD1 =>
mmc_compat_v := true;
if cmd_finished_s then
if r1_result_q = '0' then
ctrl_fsm_s <= CMD16;
else
ctrl_fsm_s <= CMD1;
end if;
else
ctrl_fsm_s <= CMD1;
end if;
-- Issue CMD16: SET_BLOCKLEN --------------------------------------------
when CMD16 =>
if cmd_finished_s then
ctrl_fsm_s <= WAIT_START;
else
ctrl_fsm_s <= CMD16;
end if;
-- Wait for configuration start request ---------------------------------
when WAIT_START =>
spi_cs_n_s <= '1';
-- detect rising edge of start_i
if start_i = '1' and start_q = '0' then
-- decide which mode is requested
if cmd_finished_s then
if mode_i = '0' then
ctrl_fsm_s <= CMD18;
else
ctrl_fsm_s <= WAIT_INIT_LOW;
end if;
else
en_outs_s <= false;
ctrl_fsm_s <= WAIT_START;
end if;
else
en_outs_s <= false;
ctrl_fsm_s <= WAIT_START;
end if;
-- Wait for INIT to become low ------------------------------------------
when WAIT_INIT_LOW =>
spi_cs_n_s <= '1';
-- activate FPGA configuration
config_n_o <= '0';
if cfg_init_n_i = '0' then
ctrl_fsm_s <= WAIT_INIT_HIGH;
else
ctrl_fsm_s <= WAIT_INIT_LOW;
end if;
-- Wait for INIT to become high -----------------------------------------
when WAIT_INIT_HIGH =>
spi_cs_n_s <= '1';
if cfg_init_n_i = '1' and cmd_finished_s then
ctrl_fsm_s <= CMD18;
else
ctrl_fsm_s <= WAIT_INIT_HIGH;
end if;
-- Issue CMD18: READ_MULTIPLE_BLOCKS ------------------------------------
when CMD18 =>
if cmd_finished_s then
ctrl_fsm_s <= CMD18_DATA;
else
ctrl_fsm_s <= CMD18;
end if;
--
-- receive a data block
when CMD18_DATA =>
if cmd_finished_s then
ctrl_fsm_s <= CMD12;
else
ctrl_fsm_s <= CMD18_DATA;
end if;
-- Issued CMD12: STOP_TRANSMISSION --------------------------------------
when CMD12 =>
if cmd_finished_s then
ctrl_fsm_s <= INC_IMG_CNT;
else
ctrl_fsm_s <= CMD12;
end if;
-- Increment Image Counter ----------------------------------------------
when INC_IMG_CNT =>
spi_cs_n_s <= '1';
ctrl_fsm_s <= WAIT_START;
cnt_en_img_s <= true;
when others =>
null;
end case;
-- mmc_compat_s is suppressed if MMC clock compatibility is not required
if mmc_compat_clk_div_g > 0 then
mmc_compat_s <= mmc_compat_v;
else
mmc_compat_s <= false;
end if;
end process ctrl_fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process cmd_fsm
--
-- Purpose:
-- Implements the command FSM.
--
cmd_fsm: process (spi_clk_rising_q,
spi_data_in_i,
bit_cnt_q,
ctrl_fsm_q,
cmd_fsm_q,
send_cmd12_q)
variable cnt_zero_v : boolean;
variable spi_data_low_v : boolean;
variable no_startbit_v : boolean;
begin
-- default assignments
cmd_finished_s <= false;
cmd_fsm_s <= CMD;
res_bc_s <= NONE;
cnt_zero_v := spi_clk_rising_q and bit_cnt_q = 0;
spi_data_low_v := spi_clk_rising_q and spi_data_in_i = '0';
-- these are no real commands thus there will be no startbit
case ctrl_fsm_q is
when POWER_UP1 | POWER_UP2 |
WAIT_START | WAIT_INIT_HIGH | WAIT_INIT_LOW =>
no_startbit_v := true;
when others =>
no_startbit_v := false;
end case;
case cmd_fsm_q is
-- Send the command -----------------------------------------------------
when CMD =>
if cnt_zero_v then
if ctrl_fsm_q /= CMD18_DATA then
-- normal commands including CMD12 require startbit of R1 response
cmd_fsm_s <= START;
else
if not send_cmd12_q then
-- CMD18_DATA needs to read CRC
cmd_fsm_s <= R1;
res_bc_s <= RES_15;
else
-- CMD18_DATA finished, scan for startbit of response
cmd_finished_s <= true;
cmd_fsm_s <= START;
end if;
end if;
else
cmd_fsm_s <= CMD;
end if;
-- Wait for startbit of response ----------------------------------------
when START =>
-- startbit detection or skip of this check
if no_startbit_v and spi_clk_rising_q then
cmd_fsm_s <= R1;
res_bc_s <= RES_7;
elsif spi_data_low_v then
if ctrl_fsm_q /= CMD18_DATA then
cmd_fsm_s <= R1;
else
-- CMD18_DATA startbit detected, read payload
cmd_fsm_s <= CMD;
res_bc_s <= RES_MAX;
end if;
else
cmd_fsm_s <= START;
res_bc_s <= RES_7;
end if;
-- Read R1 response -----------------------------------------------------
when R1 =>
if cnt_zero_v then
res_bc_s <= RES_7;
if not (ctrl_fsm_q = CMD18 or ctrl_fsm_q = CMD18_DATA) then
cmd_fsm_s <= PAUSE;
else
-- CMD18 needs another startbit detection for the data token.
-- CMD18_DATA needs a startbit after having received the CRC, either
-- * next data token
-- * R1 response of CMD12
cmd_fsm_s <= START;
if ctrl_fsm_q = CMD18 then
-- CMD18 response received -> advance to CMD18_DATA
cmd_finished_s <= true;
end if;
end if;
else
cmd_fsm_s <= R1;
end if;
-- PAUSE state -> required for Nrc, card response to host command -------
when PAUSE =>
if cnt_zero_v then
cmd_fsm_s <= CMD;
res_bc_s <= RES_47;
cmd_finished_s <= true;
else
cmd_fsm_s <= PAUSE;
end if;
when others =>
null;
end case;
end process cmd_fsm;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process transmit
--
-- Purpose:
-- Generates the serial data output values based on the current FSM state
--
-- The local variable cmd_v is 64 bits wide in contrast to an SPI command
-- with 48 bits. There are two reasons for this:
-- * During "overlaid" sending of CMD12 in FSM state CMD18_DATA, the bit
-- counter will start from 3F on its lowest 6 bits. Therefore, it is
-- necessary to provide all 64 positions in cmd_v.
-- * Reduces logic.
--
transmit: process (ctrl_fsm_q,
cmd_fsm_q,
bit_cnt_q,
img_cnt_s,
send_cmd12_q,
set_sel_i,
upper_bitcnt_zero_s)
subtype cmd_r is natural range 47 downto 0;
subtype cmd_t is std_logic_vector(cmd_r);
subtype ext_cmd_t is std_logic_vector(63 downto 0);
-- STCCCCCCAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAcccccccS
constant cmd0_c : cmd_t := "010000000000000000000000000000000000000010010101";
constant cmd1_c : cmd_t := "0100000100000000000000000000000000000000-------1";
constant cmd12_c : cmd_t := "0100110000000000000000000000000000000000-------1";
constant cmd16_c : cmd_t := "0101000000000000000000000000000000000000-------1";
constant cmd18_c : cmd_t := "0101001000000000000000000000000000000000-------1";
constant cmd55_c : cmd_t := "0111011100000000000000000000000000000000-------1";
constant acmd41_c : cmd_t := "0110100100000000000000000000000000000000-------1";
variable cmd_v : ext_cmd_t;
variable tx_v : boolean;
begin
-- default assignments
spi_dat_s <= '1';
cmd_v := (others => '1');
tx_v := false;
if cmd_fsm_q = CMD then
case ctrl_fsm_q is
when CMD0 =>
cmd_v(cmd_r) := cmd0_c;
tx_v := true;
when CMD1 =>
cmd_v(cmd_r) := cmd1_c;
tx_v := true;
when CMD16 =>
cmd_v(cmd_r) := cmd16_c;
cmd_v(8 + width_bit_cnt_g-3) := '1';
tx_v := true;
when CMD18 =>
cmd_v(cmd_r) := cmd18_c;
-- insert image counter
cmd_v(8 + num_bits_per_img_g + width_img_cnt_g
downto 8 + num_bits_per_img_g) := img_cnt_s;
-- insert set selection
cmd_v(8 + num_bits_per_img_g + width_img_cnt_g + width_set_sel_g-1
downto 8 + num_bits_per_img_g + width_img_cnt_g) := set_sel_i;
tx_v := true;
when CMD18_DATA =>
cmd_v(cmd_r) := cmd12_c;
if send_cmd12_q and upper_bitcnt_zero_s then
tx_v := true;
end if;
when CMD55 =>
cmd_v(cmd_r) := cmd55_c;
tx_v := true;
when ACMD41 =>
cmd_v(cmd_r) := acmd41_c;
tx_v := true;
when others =>
null;
end case;
end if;
if tx_v then
spi_dat_s <= cmd_v(to_integer(bit_cnt_q(5 downto 0)));
end if;
end process transmit;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Optional Image Counter
-----------------------------------------------------------------------------
img_cnt: if width_img_cnt_g > 0 generate
img_cnt_b : spi_counter
generic map (
cnt_width_g => width_img_cnt_g,
cnt_max_g => 2**width_img_cnt_g - 1
)
port map (
clk_i => clk_i,
reset_i => reset_s,
cnt_en_i => cnt_en_img_s,
cnt_o => img_cnt_s(width_img_cnt_g-1 downto 0),
cnt_ovfl_o => open
);
img_cnt_s(width_img_cnt_g) <= '0';
end generate;
no_img_cnt: if width_img_cnt_g = 0 generate
img_cnt_s <= (others => '0');
end generate;
-----------------------------------------------------------------------------
-- Optional MMC compatibility counter
-----------------------------------------------------------------------------
mmc_cnt: if mmc_compat_clk_div_g > 0 generate
mmc_cnt_b : spi_counter
generic map (
cnt_width_g => width_mmc_clk_div_g,
cnt_max_g => mmc_compat_clk_div_g
)
port map (
clk_i => clk_i,
reset_i => reset_s,
cnt_en_i => true_s,
cnt_o => open,
cnt_ovfl_o => mmc_cnt_ovfl_s
);
end generate;
no_mmc_cnt: if mmc_compat_clk_div_g = 0 generate
mmc_cnt_ovfl_s <= true;
end generate;
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
spi_clk_o <= spi_clk_q;
spi_cs_n_o <= spi_cs_n_q;
spi_data_out_o <= spi_dat_q;
spi_en_outs_o <= '1'
when en_outs_q else
'0';
cfg_clk_o <= cfg_clk_q;
cfg_dat_o <= cfg_dat_q;
detached_o <= '0'
when en_outs_q else
'1';
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: spi_boot.vhd,v $
-- Revision 1.9 2007/02/25 18:24:12 arniml
-- fix type handling of resets
--
-- Revision 1.8 2006/09/11 23:03:36 arniml
-- disable outputs with reset
--
-- Revision 1.7 2005/04/07 20:44:23 arniml
-- add new port detached_o
--
-- Revision 1.6 2005/03/09 19:48:34 arniml
-- invert level of set_sel input
--
-- Revision 1.5 2005/03/08 22:07:12 arniml
-- added set selection
--
-- Revision 1.4 2005/02/18 06:42:08 arniml
-- clarify wording for images
--
-- Revision 1.3 2005/02/16 18:59:10 arniml
-- include output enable control for SPI outputs
--
-- Revision 1.2 2005/02/13 17:25:51 arniml
-- major update to fix several problems
-- configuration/data download of multiple sets works now
--
-- Revision 1.1 2005/02/08 20:41:33 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | dbb2e13d52f369edef36935433007a7d | 0.477419 | 3.855826 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/old/retro_logic.vhd | 5 | 5,927 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity retro_logic is
generic (
rom_base : std_logic_vector(27 downto 0) := X"1040000";
ram_base : std_logic_vector(27 downto 0) := X"0052000" );
port (
clock : in std_logic;
reset : in std_logic;
RSTn_in : in std_logic;
freeze_trig : in std_logic; -- goes '1' when the button has been pressed and we're waiting to enter the freezer
freeze_act : in std_logic; -- goes '1' when we need to switch in the cartridge for freeze mode
unfreeze : out std_logic; -- indicates the freeze logic to switch back to non-freeze mode.
cart_kill : in std_logic;
io_write : in std_logic;
io_addr : in std_logic_vector(8 downto 0);
io_data : in std_logic_vector(7 downto 0);
serve_enable : out std_logic; -- enables fetching bus address PHI2=1
serve_vic : out std_logic; -- enables doing so for PHI2=0
serve_rom : out std_logic; -- ROML or ROMH
serve_io1 : out std_logic; -- IO1n
serve_io2 : out std_logic; -- IO2n
allow_write : out std_logic;
reg_output : out std_logic;
reg_rdata : out std_logic_vector(7 downto 0);
slot_addr : in std_logic_vector(15 downto 0);
mem_addr : out std_logic_vector(25 downto 0);
-- debug
cart_mode : out std_logic_vector(7 downto 0);
irq_n : out std_logic;
nmi_n : out std_logic;
exrom_n : out std_logic;
game_n : out std_logic;
CART_LEDn : out std_logic );
end retro_logic;
architecture gideon of retro_logic is
signal reset_in : std_logic;
signal cart_ctrl : std_logic_vector(7 downto 0);
signal freeze_act_d : std_logic;
signal mode : std_logic_vector(2 downto 0);
signal cart_en : std_logic;
signal do_io2 : std_logic;
signal allow_bank : std_logic;
constant c_serve_rom : std_logic_vector(0 to 7) := "11011111";
constant c_serve_io1 : std_logic_vector(0 to 7) := "10101111";
begin
unfreeze <= cart_ctrl(6);
serve_enable <= cart_en;
process(clock)
begin
if rising_edge(clock) then
reset_in <= reset or not RSTn_in;
freeze_act_d <= freeze_act;
-- control register
if reset_in='1' then -- either reset or freeze
cart_ctrl <= (others => '0');
do_io2 <= '1';
allow_bank <= '0';
elsif freeze_act='1' and freeze_act_d='0' then
cart_ctrl <= (others => '0');
do_io2 <= '1';
allow_bank <= '0';
elsif io_write='1' and io_addr(8 downto 1) = X"00" and cart_en='1' then -- IO1
if io_addr(0)='0' then
cart_ctrl <= io_data;
else
do_io2 <= not io_data(6);
allow_bank <= io_data(1);
end if;
end if;
-- Generate the cartridge mode
-- determine whether to serve io requests
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
serve_rom <= '1';
serve_io1 <= '0';
serve_io2 <= '0';
else
game_n <= not mode(0);
exrom_n <= mode(1);
serve_io1 <= c_serve_io1(conv_integer(mode));
serve_io2 <= c_serve_io1(conv_integer(mode)) and do_io2;
serve_rom <= c_serve_rom(conv_integer(mode));
end if;
if cart_kill='1' then
cart_ctrl(2) <= '1';
end if;
end if;
end process;
mode <= cart_ctrl(5) & cart_ctrl(1) & cart_ctrl(0);
cart_en <= not cart_ctrl(2);
CART_LEDn <= cart_ctrl(2);
irq_n <= not (freeze_trig or freeze_act);
nmi_n <= not (freeze_trig or freeze_act);
-- determine address
process(slot_addr, mode, cart_ctrl, do_io2)
begin
allow_write <= '0';
if mode(2)='1' then
if slot_addr(13)='0' then
if allow_bank='1' then
mem_addr <= ram_base(25 downto 15) & cart_ctrl(4 downto 3) & slot_addr(12 downto 0);
else
mem_addr <= ram_base(25 downto 15) & "00" & slot_addr(12 downto 0);
end if;
else
mem_addr <= rom_base(25 downto 16) & cart_ctrl(7) & cart_ctrl(4 downto 3) & slot_addr(12 downto 0);
end if;
if slot_addr(15 downto 13)="100" and cart_ctrl(1 downto 0)="11" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DE" and slot_addr(7 downto 1)/="0000000" then
allow_write <= '1';
end if;
if slot_addr(15 downto 8)=X"DF" and do_io2='1' then
allow_write <= '1';
end if;
else
mem_addr <= rom_base(25 downto 16) & cart_ctrl(7) & cart_ctrl(4 downto 3) & slot_addr(12 downto 0);
end if;
end process;
cart_mode <= cart_ctrl;
serve_vic <= '0';
reg_rdata(7) <= cart_ctrl(7);
reg_rdata(6) <= '1';
reg_rdata(5) <= '0';
reg_rdata(4) <= cart_ctrl(4);
reg_rdata(3) <= cart_ctrl(3);
reg_rdata(2) <= '0'; -- freeze button pressed
reg_rdata(1) <= allow_bank; -- '1'; -- allow bank bit stuck at '1' for 1541U
reg_rdata(0) <= '0';
reg_output <= '1' when slot_addr(15 downto 1)="110111100000000" else '0';
end gideon;
| gpl-3.0 | d2eb0480b36daf9776affb4f0c4cf692 | 0.487768 | 3.530077 | false | false | false | false |
andygill/kansas-lava | Prelude/VHDL/Modelsim.vhd | 3 | 4,845 | library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
entity tb_env is
generic (
clk_period : time := 10 ns; -- 100MHz
cycle_count : integer := 1000
);
port (
clk : out std_logic;
clk_en : out std_logic;
rst : out std_logic
);
end entity;
-- This is the vhdl/modelsim version of shallowEnv.
architecture Behavioral of tb_env is
begin
runenv: process is
variable counter : integer := cycle_count;
begin
clk <= '0';
clk_en <= '1';
rst <= '0';
wait for clk_period / 2;
-- Use these three if you *need* reset.
-- rst <= '1';
-- wait for clk_period / 2;
-- rst <= '0';
while counter > 0 loop
if (counter mod 100 = 0) then
report("cycle: " & integer'image(cycle_count - counter));
end if;
counter := counter - 1;
wait for clk_period / 2;
clk <= '1'; -- rising edge
wait for clk_period / 2;
clk <= '0'; -- falling edge
end loop;
report "End of simulation." severity note;
wait;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
-- A 'src' generator is a Master or Writer, the consumer is a Slave or Reader.
entity lava_src_pipe is
generic (
src_file_name : string
);
port (
M_VALID : out std_logic;
M_DATA : out std_logic_vector(7 downto 0);
M_READY : in std_logic;
clk : in std_logic;
clk_en : in std_logic := '1';
rst : in std_logic := '0'
);
end entity;
architecture Behavioral of lava_src_pipe is
begin
runtest: process is
type char_file is file of character;
file my_file : char_file;
variable my_char_v : character;
variable my_byte : std_logic_vector(7 downto 0);
variable buf_empty : boolean := true; -- 1 element FIFO
function str(b: boolean) return string is
begin
if b then
return "true";
else
return "false";
end if;
end str;
begin
M_DATA <= (others => 'X');
M_VALID <= '0';
buf_empty := true;
file_open(my_file, src_file_name, read_mode);
report("FILE: " & str(endfile(my_file)));
-- while (not endfile (my_file)) or (not buf_empty) loop
while true loop
-- Considerations are made on the rising edge
wait until rising_edge(clk);
-- if the previous packet was accepted, then empty the buffer token
if M_READY = '1' then
buf_empty := true;
end if;
-- if the buffer is empty, then fill it
if buf_empty and not endfile(my_file) then
report("READING");
read(my_file, my_char_v);
report("READ: " & my_char_v);
my_byte := std_logic_vector(to_unsigned(character'pos(my_char_v),8));
buf_empty := false;
end if;
if buf_empty then
M_DATA <= (others => 'X');
M_VALID <= '0';
else
-- The buffer is now full, so send it
M_DATA <= my_byte;
M_VALID <= '1';
end if;
end loop;
-- wait until rising_edge(clk);
-- -- The buffer is now empty
-- M_DATA <= (others => 'X');
-- M_VALID <= '0';
wait;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
entity lava_sink_pipe is
generic (
sink_file_name : string
);
port (
S_VALID : in std_logic;
S_DATA : in std_logic_vector(7 downto 0);
S_READY : out std_logic;
clk : in std_logic;
clk_en : in std_logic := '1';
rst : in std_logic := '0'
);
end entity;
architecture Behavioral of lava_sink_pipe is
begin
runtest: process is
type char_file is file of character;
file my_file : char_file;
variable my_char_v : character;
variable my_byte : std_logic_vector(7 downto 0);
variable buf_empty : boolean := true; -- 1 element FIFO
begin
S_READY <= '1'; -- Always ready
while true loop
-- Considerations are made on the rising edge
wait until rising_edge(clk);
-- if there is a value, then write it
-- Very hacky, because ModelSim does not block if writing to a full pipe,
-- we so need to open and close each time.
if S_VALID = '1' then
file_open(my_file, sink_file_name, append_mode);
my_char_v := character'val(to_integer(unsigned(S_DATA)));
write(my_file, my_char_v);
file_close(my_file);
report("WROTE: " & my_char_v);
end if;
end loop;
end process;
end architecture;
| bsd-3-clause | 458a39bec679248657910a8af62af31a | 0.594221 | 3.304911 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/ram.vhd | 1 | 5,548 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file ram.vhd when simulating
-- the core, ram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY ram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ram;
ARCHITECTURE ram_a OF ram IS
-- synthesis translate_off
COMPONENT wrapped_ram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_ram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 10,
c_addrb_width => 10,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 1024,
c_read_depth_b => 1024,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 1024,
c_write_depth_b => 1024,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_ram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END ram_a;
| mit | a1dfe5756f7d5363472eb9c170454088 | 0.528479 | 3.957204 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op991_28.vhdl | 1 | 6,543 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net8
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net8,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net9,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net9
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | d86a5f475d20e22739b2f09144a8af49 | 0.570533 | 3.063202 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/itu/vhdl_source/itu.vhd | 3 | 10,344 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.itu_pkg.all;
entity itu is
generic (
g_version : unsigned(7 downto 0) := X"FE";
g_uart : boolean := true;
g_frequency : integer := 50_000_000;
g_edge_init : std_logic_vector(7 downto 0) := "00000001";
g_capabilities : std_logic_vector(31 downto 0) := X"5555AAAA";
g_edge_write : boolean := true;
g_baudrate : integer := 115_200;
g_timer_rate : integer := 200_000 ); -- 5µs (should not result in more than 8 bits div)
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
irq_timer_tick : in std_logic := '0';
irq_in : in std_logic_vector(7 downto 2);
uart_txd : out std_logic;
uart_rxd : in std_logic := '1';
uart_rts : out std_logic;
uart_cts : in std_logic := '1' );
end itu;
architecture gideon of itu is
constant c_timer_div : integer := g_frequency / g_timer_rate;
constant c_baud_div : integer := g_frequency / g_baudrate;
constant c_ms_div : integer := g_timer_rate / 1000;
signal imask : std_logic_vector(7 downto 0);
signal iedge : std_logic_vector(7 downto 0) := g_edge_init;
signal timer : unsigned(7 downto 0);
signal timer_tick : std_logic;
signal timer_div : integer range 0 to c_timer_div - 1;
signal irq_timer_val : unsigned(15 downto 0);
signal irq_timer_cnt : unsigned(23 downto 0);
signal irq_timer_en : std_logic;
signal irq_timer_select : std_logic;
signal irq_en : std_logic;
signal irq_c : std_logic_vector(7 downto 0);
signal irq_d : std_logic_vector(7 downto 0);
signal irq_edge_flag : std_logic_vector(7 downto 0);
signal irq_active : std_logic_vector(7 downto 0);
signal uart_irq : std_logic := '0';
signal io_req_it : t_io_req;
signal io_resp_it : t_io_resp;
signal io_req_uart : t_io_req;
signal io_resp_uart : t_io_resp;
signal io_req_ms : t_io_req;
signal io_resp_ms : t_io_resp;
signal ms_timer_presc : integer range 0 to c_ms_div-1 := 0;
signal ms_timer : unsigned(15 downto 0) := (others => '0');
begin
process(clock)
variable new_irq_edge_flag : std_logic_vector(irq_edge_flag'range);
begin
if rising_edge(clock) then
if timer_div = 0 then
timer_div <= c_timer_div - 1;
timer_tick <= '1';
else
timer_div <= timer_div - 1;
timer_tick <= '0';
end if;
if timer_tick='1' then
if timer /= X"00" then
timer <= timer - 1;
end if;
if ms_timer_presc = 0 then
ms_timer <= ms_timer + 1;
ms_timer_presc <= c_ms_div - 1;
else
ms_timer_presc <= ms_timer_presc - 1;
end if;
end if;
irq_c(7 downto 2) <= irq_in(7 downto 2);
irq_c(1) <= uart_irq;
irq_c(0) <= '0';
if irq_timer_en='1' then
if irq_timer_cnt = 0 then
irq_c(0) <= '1';
if irq_timer_select='1' then
irq_timer_cnt <= X"00" & irq_timer_val;
else
irq_timer_cnt <= irq_timer_val & X"FF";
end if;
elsif irq_timer_select='0' or irq_timer_tick='1' then
irq_timer_cnt <= irq_timer_cnt - 1;
end if;
end if;
irq_d <= irq_c;
io_resp_it <= c_io_resp_init;
new_irq_edge_flag := irq_edge_flag;
if io_req_it.write='1' then
io_resp_it.ack <= '1';
case io_req_it.address(3 downto 0) is
when c_itu_irq_global =>
irq_en <= io_req_it.data(0);
when c_itu_irq_enable =>
imask <= imask or io_req_it.data;
when c_itu_irq_disable =>
imask <= imask and not io_req_it.data;
when c_itu_irq_edge =>
if g_edge_write then
iedge <= io_req_it.data;
end if;
when c_itu_irq_clear =>
new_irq_edge_flag := new_irq_edge_flag and not io_req_it.data;
when c_itu_timer =>
timer <= unsigned(io_req_it.data);
when c_itu_irq_timer_en =>
irq_timer_en <= io_req_it.data(0);
irq_timer_select <= io_req_it.data(1);
if irq_timer_en='0' then
irq_timer_cnt <= irq_timer_val & X"FF";
end if;
when c_itu_irq_timer_lo =>
irq_timer_val(7 downto 0) <= unsigned(io_req_it.data);
when c_itu_irq_timer_hi =>
irq_timer_val(15 downto 8) <= unsigned(io_req_it.data);
when others =>
null;
end case;
elsif io_req_it.read='1' then
io_resp_it.ack <= '1';
case io_req_it.address(3 downto 0) is
when c_itu_irq_global =>
io_resp_it.data(0) <= irq_en;
when c_itu_irq_enable =>
io_resp_it.data <= imask;
when c_itu_irq_edge =>
io_resp_it.data <= iedge;
when c_itu_irq_active =>
io_resp_it.data <= irq_active;
when c_itu_timer =>
io_resp_it.data <= std_logic_vector(timer);
when c_itu_irq_timer_en =>
io_resp_it.data(0) <= irq_timer_en;
io_resp_it.data(1) <= irq_timer_select;
when c_itu_irq_timer_lo =>
io_resp_it.data <= std_logic_vector(irq_timer_cnt(7 downto 0));
when c_itu_irq_timer_hi =>
io_resp_it.data <= std_logic_vector(irq_timer_cnt(15 downto 8));
when c_itu_fpga_version =>
io_resp_it.data <= std_logic_vector(g_version);
when c_itu_capabilities0 =>
io_resp_it.data <= g_capabilities(31 downto 24);
when c_itu_capabilities1 =>
io_resp_it.data <= g_capabilities(23 downto 16);
when c_itu_capabilities2 =>
io_resp_it.data <= g_capabilities(15 downto 8);
when c_itu_capabilities3 =>
io_resp_it.data <= g_capabilities( 7 downto 0);
when others =>
null;
end case;
end if;
io_resp_ms <= c_io_resp_init;
if io_req_ms.write='1' then
io_resp_ms.ack <= '1';
elsif io_req_ms.read='1' then
io_resp_ms.ack <= '1';
case io_req_ms.address(3 downto 0) is
when c_itu_ms_timer_lo =>
io_resp_ms.data <= std_logic_vector(ms_timer(7 downto 0));
when c_itu_ms_timer_hi =>
io_resp_ms.data <= std_logic_vector(ms_timer(15 downto 8));
when others =>
null;
end case;
end if;
for i in 0 to 7 loop
if iedge(i)='1' then
if irq_c(i)='1' and irq_d(i)='0' then
new_irq_edge_flag(i) := '1';
end if;
end if;
end loop;
irq_edge_flag <= new_irq_edge_flag;
io_resp_it.irq <= '0';
if irq_en = '1' then
if (irq_active and imask) /= X"00" then
io_resp_it.irq <= '1';
end if;
end if;
if reset='1' then
irq_en <= '1';
imask <= (others => '0');
iedge <= g_edge_init;
timer <= (others => '0');
irq_timer_en <= '0';
irq_timer_val <= X"8000";
irq_timer_cnt <= (others => '0');
ms_timer <= (others => '0');
end if;
end if;
end process;
irq_active <= irq_edge_flag or (irq_c and not iedge);
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 4,
g_range_hi => 5,
g_ports => 3 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_it,
reqs(1) => io_req_uart,
reqs(2) => io_req_ms,
resps(0) => io_resp_it,
resps(1) => io_resp_uart,
resps(2) => io_resp_ms );
r_uart: if g_uart generate
uart: entity work.uart_peripheral_io
generic map (
g_divisor => c_baud_div )
port map (
clock => clock,
reset => reset,
io_req => io_req_uart,
io_resp => io_resp_uart,
rts => uart_rts,
cts => uart_cts,
txd => uart_txd,
rxd => uart_rxd );
end generate;
no_uart: if not g_uart generate
process(clock)
begin
if rising_edge(clock) then
io_resp_uart <= c_io_resp_init;
io_resp_uart.ack <= io_req_uart.read or io_req_uart.write;
end if;
end process;
end generate;
end architecture;
| gpl-3.0 | 2e7f24631c1b3755400284ed3c5a3a15 | 0.427784 | 3.771054 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cpu_unit/vhdl_source/mem16k.vhd | 5 | 2,201 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mem16k is
generic (
simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
address : in std_logic_vector(26 downto 0);
request : in std_logic;
mwrite : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
rack : out std_logic;
dack : out std_logic;
claimed : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of mem16k : entity is "yes";
end mem16k;
architecture gideon of mem16k is
subtype t_byte is std_logic_vector(7 downto 0);
type t_byte_array is array(natural range <>) of t_byte;
shared variable my_mem : t_byte_array(0 to 16383);
signal claimed_i : std_logic;
signal do_write : std_logic;
-- attribute ram_style : string;
-- attribute ram_style of my_mem : signal is "block";
begin
claimed_i <= '1' when address(26 downto 14) = "0000000000000"
else '0';
claimed <= claimed_i;
rack <= claimed_i and request;
do_write <= claimed_i and request and mwrite;
-- synthesis translate_off
model: if simulation generate
mram: entity work.bram_model_8sp
generic map("intram", 14) -- 16k
port map (
CLK => clock,
SSR => reset,
EN => request,
WE => do_write,
ADDR => address(13 downto 0),
DI => wdata,
DO => rdata );
end generate;
-- synthesis translate_on
process(clock)
begin
if rising_edge(clock) then
if do_write='1' then
my_mem(to_integer(unsigned(address(13 downto 0)))) := wdata;
end if;
if not simulation then
rdata <= my_mem(to_integer(unsigned(address(13 downto 0))));
else
rdata <= (others => 'Z');
end if;
dack <= claimed_i and request;
end if;
end process;
end gideon;
| gpl-3.0 | 783bdb2d449a59a4b68699f8713b8c66 | 0.534303 | 3.692953 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_source/ulpi_rx.vhd | 1 | 8,524 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_rx is
generic (
g_support_split : boolean := true;
g_support_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_last : in std_logic;
rx_valid : in std_logic;
rx_store : in std_logic;
crc_sync : out std_logic;
crc_dvalid : out std_logic;
data_crc : in std_logic_vector(15 downto 0);
status : in std_logic_vector(7 downto 0);
usb_rx : out t_usb_rx );
end ulpi_rx;
architecture gideon of ulpi_rx is
type t_state is (idle, token0, token1, token2, check_token, resync,
data, data_check, handshake );
signal state : t_state;
signal token_i : std_logic_vector(18 downto 0) := (others => '0');
signal token_crc : std_logic_vector(4 downto 0) := (others => '0');
signal crc_tvalid : std_logic;
signal crc_sync_i : std_logic;
signal rx_valid_d : std_logic;
signal pid : std_logic_vector(3 downto 0);
signal valid_token : std_logic;
signal valid_split : std_logic;
signal valid_handsh : std_logic;
signal valid_packet : std_logic;
signal data_valid : std_logic;
signal data_start : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal error : std_logic;
signal rx_data_d1 : std_logic_vector(7 downto 0);
signal rx_data_d2 : std_logic_vector(7 downto 0);
signal rx_valid_d1 : std_logic;
signal rx_valid_d2 : std_logic;
signal recv_d : std_logic_vector(1 to 3);
--signal ipd_counter : unsigned(tx_holdoff_delay'range) := (others => '0'); -- interpacket delay
begin
usb_rx.token <= vector_to_token(token_i(18 downto 8));
usb_rx.split_token <= vector_to_split_token(token_i(18 downto 0));
usb_rx.pid <= pid;
usb_rx.valid_token <= valid_token;
usb_rx.valid_split <= valid_split;
usb_rx.valid_handsh <= valid_handsh;
usb_rx.valid_packet <= valid_packet;
usb_rx.data_valid <= data_valid and rx_valid_d2;
usb_rx.data_start <= data_start;
usb_rx.data <= data_out;
usb_rx.error <= error;
usb_rx.receiving <= rx_store or recv_d(1) or recv_d(2) or recv_d(3) or status(4);
process(clock)
begin
if rising_edge(clock) then
error <= '0';
data_start <= '0';
valid_token <= '0';
valid_split <= '0';
valid_packet <= '0';
valid_handsh <= '0';
-- if rx_store = '1' then -- reset interpacket delay counter for transmit
-- tx_holdoff <= '1';
-- ipd_counter <= tx_holdoff_delay;
-- else
-- if ipd_counter = 0 then
-- tx_holdoff <= '0';
-- else
-- ipd_counter <= ipd_counter - 1;
-- end if;
-- end if;
recv_d <= rx_store & recv_d(1 to 2);
rx_data_d1 <= rx_data;
if data_valid='1' then
rx_data_d2 <= rx_data_d1;
data_out <= rx_data_d2;
rx_valid_d1 <= '1';
rx_valid_d2 <= rx_valid_d1;
end if;
data_valid <= '0';
rx_valid_d <= rx_valid;
case state is
when idle =>
rx_valid_d1 <= '0';
rx_valid_d2 <= '0';
if rx_valid='1' and rx_store='1' then -- wait for first byte
if rx_data(7 downto 4) = not rx_data(3 downto 0) then
pid <= rx_data(3 downto 0);
if is_handshake(rx_data(3 downto 0)) then
if rx_last = '1' then
valid_handsh <= '1';
else
state <= handshake;
end if;
elsif is_token(rx_data(3 downto 0)) then
if g_support_token then
state <= token1;
else
error <= '1';
end if;
elsif is_split(rx_data(3 downto 0)) then
if g_support_split then
state <= token0;
else
error <= '1';
end if;
else
data_start <= '1';
state <= data;
end if;
else -- error in PID
error <= '1';
end if;
end if;
when handshake =>
if rx_store='1' then -- more data? error
error <= '1';
state <= resync;
elsif rx_last = '1' then
valid_handsh <= '1';
state <= idle;
end if;
when token0 =>
if rx_store='1' then
token_i(7 downto 0) <= rx_data;
state <= token1;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= resync;
end if;
when token1 =>
if rx_store='1' then
token_i(15 downto 8) <= rx_data;
state <= token2;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= resync;
end if;
when token2 =>
if rx_store='1' then
token_i(18 downto 16) <= rx_data(2 downto 0);
state <= check_token;
end if;
when data =>
data_valid <= rx_store;
if rx_last='1' then
state <= data_check;
end if;
when data_check =>
if data_crc = X"4FFE" then
valid_packet <= '1';
else
error <= '1';
end if;
state <= idle;
when check_token =>
if token_crc = "11001" then
if is_split(pid) then
valid_split <= '1';
else
valid_token <= '1';
end if;
else
error <= '1';
end if;
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
else
state <= resync;
end if;
when resync =>
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
pid <= X"0";
-- tx_holdoff <= '0';
end if;
end if;
end process;
r_token: if g_support_token or g_support_split generate
i_token_crc: entity work.token_crc_check
port map (
clock => clock,
sync => crc_sync_i,
valid => crc_tvalid,
data_in => rx_data,
crc => token_crc );
end generate;
crc_sync_i <= (rx_valid and rx_store) when state = idle else '0';
crc_dvalid <= rx_store when state = data else '0';
crc_tvalid <= rx_store when (state = token0) or (state = token1) or (state = token2) else '0';
crc_sync <= crc_sync_i;
end gideon;
| gpl-3.0 | 1237bf02da56de483266b6d229f6a307 | 0.399108 | 4.203156 | false | false | false | false |
KB777/1541UltimateII | fpga/ip/busses/vhdl_source/align_read_to_bram.vhd | 1 | 4,775 | --------------------------------------------------------------------------------
-- Entity: align_read_to_bram
-- Date:2015-03-14
-- Author: Gideon
--
-- Description: This module aligns 32 bit reads from memory to writes to BRAM
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity align_read_to_bram is
port (
clock : in std_logic;
rdata : in std_logic_vector(31 downto 0);
rdata_valid : in std_logic;
first_word : in std_logic;
last_word : in std_logic;
offset : in unsigned(1 downto 0);
wdata : out std_logic_vector(31 downto 0);
wmask : out std_logic_vector(3 downto 0);
wnext : out std_logic );
end align_read_to_bram;
-- two possibilities.
-- 1) read from memory with lower address bits on zero. word from memory is aligned.
-- first byte in the word that needs to be written to BRAM depends on the offset,
-- so the word itself needs to be rotated, to get the right byte at the right 'lane'.
--
-- 2) read from memory with lower address set to the actual offset. Depending on the
-- burst size of the memory, the bytes in the word are actually shifted. Example:
-- Read from 0001 => 01.02.03.00 MSB first in this example.
-- ** ** ** -- Write these bytes to BRAM address 0
-- Read from 0005 => 05.06.07.04 MSB first
-- ** Write these bytes to BRAM address 0
-- ** ** ** -- Write these bytes to BRAM address 1
-- Read from 0009 => 09.0A.0B.09
-- ** Write these bytes to BRAM address 1
-- ** ** ** -- Write these bytes to BRAM address 2
-- ...
-- Read from 00FD => FD.FE.FF.FC
-- ** Write these bytes to BRAM address 62
-- ** ** ** -- Write these bytes to BRAM address 63
-- Read from 0101 => 01.02.03.00
-- ** Write these bytes to BRAM address 63
-- END.
-- So in this way we only need to generate the correct write strobes and address advance.
--
-- Note on count generation:
-- Bytes Offset | Words
-- 1 x | 1
-- 2 0 | 1
-- 2 1 | 1
-- 2 2 | 1
-- 2 3 | 2
-- 3 0 | 1
-- 3 1 | 1
-- 3 2 | 2
-- 3 3 | 2
-- 4 0 | 1
-- 4 1 | 2
-- 4 2 | 2
-- 4 3 | 2
-- (bytes + 3 + offset) and ~3
--
architecture arch of align_read_to_bram is
signal need_second : std_logic;
signal second_cycle : std_logic;
signal byte_en : std_logic_vector(3 downto 0);
signal advance : std_logic;
begin
process(offset, rdata_valid, first_word, last_word, second_cycle)
begin
need_second <= '0';
advance <= '0';
byte_en <= "0000";
if rdata_valid='1' then
case offset is
when "00" => -- direct fit
byte_en <= "1111";
advance <= '1';
when "01" =>
if first_word='1' then
byte_en <= "0111";
else
byte_en <= "1000";
advance <= '1';
need_second <= '1';
end if;
when "10" =>
if first_word='1' then
byte_en <= "0011";
else
byte_en <= "1100";
advance <= '1';
need_second <= '1';
end if;
when "11" =>
if first_word='1' then
byte_en <= "0001";
else
byte_en <= "1110";
advance <= '1';
need_second <= '1';
end if;
when others =>
null;
end case;
if last_word='1' then
need_second <= '0';
end if;
elsif second_cycle='1' then
case offset is
when "01" =>
byte_en <= "0111";
when "10" =>
byte_en <= "0011";
when "11" =>
byte_en <= "0001";
when others =>
null;
end case;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
second_cycle <= need_second;
if rdata_valid = '1' then
wdata <= rdata;
end if;
wmask <= byte_en;
wnext <= advance;
end if;
end process;
end arch;
| gpl-3.0 | 59c820b74023faa7608e6e8dff315076 | 0.434136 | 4.05348 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/ipcore_dir/ROM_GAUSS_COE/simulation/ROM_GAUSS_COE_tb_checker.vhd | 1 | 5,575 |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Checker
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ROM_GAUSS_COE_tb_checker.vhd
--
-- Description:
-- Checker
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ROM_GAUSS_COE_TB_PKG.ALL;
ENTITY ROM_GAUSS_COE_TB_CHECKER IS
GENERIC (
WRITE_WIDTH : INTEGER :=32;
READ_WIDTH : INTEGER :=32
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END ROM_GAUSS_COE_TB_CHECKER;
ARCHITECTURE CHECKER_ARCH OF ROM_GAUSS_COE_TB_CHECKER IS
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0);
SIGNAL EN_R : STD_LOGIC := '0';
SIGNAL EN_2R : STD_LOGIC := '0';
--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT
--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH)
--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8)
CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH);
CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH);
SIGNAL ERR_HOLD : STD_LOGIC :='0';
SIGNAL ERR_DET : STD_LOGIC :='0';
BEGIN
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST= '1') THEN
EN_R <= '0';
EN_2R <= '0';
DATA_IN_R <= (OTHERS=>'0');
ELSE
EN_R <= EN;
EN_2R <= EN_R;
DATA_IN_R <= DATA_IN;
END IF;
END IF;
END PROCESS;
EXPECTED_DGEN_INST:ENTITY work.ROM_GAUSS_COE_TB_DGEN
GENERIC MAP (
DATA_GEN_WIDTH =>MAX_WIDTH,
DOUT_WIDTH => READ_WIDTH,
DATA_PART_CNT => DATA_PART_CNT,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => EN_2R,
DATA_OUT => EXPECTED_DATA
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(EN_2R='1') THEN
IF(EXPECTED_DATA = DATA_IN_R) THEN
ERR_DET<='0';
ELSE
ERR_DET<= '1';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF(RST='1') THEN
ERR_HOLD <= '0';
ELSIF(RISING_EDGE(CLK)) THEN
ERR_HOLD <= ERR_HOLD OR ERR_DET ;
END IF;
END PROCESS;
STATUS <= ERR_HOLD;
END ARCHITECTURE;
| gpl-3.0 | 45edc31bb171009dbec6195f263a013a | 0.604126 | 4.099265 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/slot_server_v4.vhd | 3 | 27,534 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.dma_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.cart_slot_pkg.all;
entity slot_server_v4 is
generic (
g_tag_slot : std_logic_vector(7 downto 0) := X"08";
g_tag_reu : std_logic_vector(7 downto 0) := X"10";
g_ram_base_reu : unsigned(27 downto 0) := X"1000000"; -- should be on 16M boundary, or should be limited in size
g_ram_base_cart : unsigned(27 downto 0) := X"0F70000"; -- should be on a 64K boundary
g_rom_base_cart : unsigned(27 downto 0) := X"0F80000"; -- should be on a 512K boundary
g_control_read : boolean := true;
g_command_intf : boolean := true;
g_ram_expansion : boolean := true;
g_extended_reu : boolean := false;
g_sampler : boolean := false;
g_implement_sid : boolean := true;
g_sid_voices : natural := 3;
g_vic_copper : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : inout std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
PHI2 : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
DMAn : out std_logic := '1';
BA : in std_logic := '0';
ROMLn : in std_logic;
ROMHn : in std_logic;
GAMEn : inout std_logic;
EXROMn : inout std_logic;
RWn : inout std_logic;
ADDRESS : inout std_logic_vector(15 downto 0);
DATA : inout std_logic_vector(7 downto 0);
-- other hardware pins
BUFFER_ENn : out std_logic;
buttons : in std_logic_vector(2 downto 0);
cart_led_n : out std_logic;
trigger_1 : out std_logic;
trigger_2 : out std_logic;
-- debug
freezer_state : out std_logic_vector(1 downto 0);
-- audio output
sid_pwm_left : out std_logic := '0';
sid_pwm_right : out std_logic := '0';
samp_pwm_left : out std_logic := '0';
samp_pwm_right : out std_logic := '0';
-- timing output
phi2_tick : out std_logic;
c64_stopped : out std_logic;
-- master on memory bus
memctrl_inhibit : out std_logic;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- slave on io bus
io_req : in t_io_req;
io_resp : out t_io_resp );
end slot_server_v4;
architecture structural of slot_server_v4 is
signal phi2_tick_i : std_logic;
signal phi2_recovered : std_logic;
signal vic_cycle : std_logic;
signal do_sample_addr : std_logic;
signal do_sample_io : std_logic;
signal do_io_event : std_logic;
signal do_probe_end : std_logic;
signal timing_inhibit : std_logic;
signal slave_dout : std_logic_vector(7 downto 0);
signal slave_dtri : std_logic := '0';
signal master_dout : std_logic_vector(7 downto 0);
signal master_dtri : std_logic := '0';
signal address_tri_l : std_logic;
signal address_tri_h : std_logic;
signal address_out : std_logic_vector(15 downto 0);
signal rwn_tri : std_logic;
signal rwn_out : std_logic;
signal control : t_cart_control;
signal status : t_cart_status;
signal allow_serve : std_logic;
-- interface with freezer (cartridge) logic
signal serve_enable : std_logic := '0'; -- from cartridge emulation logic
signal serve_vic : std_logic := '0';
signal serve_rom : std_logic := '0'; -- ROML or ROMH
signal serve_io1 : std_logic := '0'; -- IO1n
signal serve_io2 : std_logic := '0'; -- IO2n
signal allow_write : std_logic := '0';
-- kernal replacement logic
signal kernal_area : std_logic := '0';
signal kernal_probe : std_logic := '0';
signal kernal_addr_out : std_logic := '0';
signal force_ultimax : std_logic := '0';
signal cpu_write : std_logic;
signal epyx_timeout : std_logic;
signal reu_dma_n : std_logic := '1'; -- direct from REC
signal cmd_if_freeze : std_logic := '0'; -- same function as reu_dma_n, but then from CI
signal mask_buttons : std_logic := '0';
signal reset_button : std_logic;
signal freeze_button : std_logic;
signal actual_c64_reset : std_logic;
signal dma_n : std_logic := '1';
signal nmi_n : std_logic := '1';
signal irq_n : std_logic := '1';
signal exrom_n : std_logic := '1';
signal game_n : std_logic := '1';
signal irq_oc, nmi_oc, rst_oc, dma_oc, exrom_oc, game_oc : std_logic;
signal unfreeze : std_logic;
signal freeze_trig : std_logic;
signal freeze_act : std_logic;
signal io_req_dma : t_io_req;
signal io_resp_dma : t_io_resp := c_io_resp_init;
signal io_req_peri : t_io_req;
signal io_resp_peri : t_io_resp := c_io_resp_init;
signal io_req_sid : t_io_req;
signal io_resp_sid : t_io_resp := c_io_resp_init;
signal io_req_regs : t_io_req;
signal io_resp_regs : t_io_resp := c_io_resp_init;
signal io_req_cmd : t_io_req;
signal io_resp_cmd : t_io_resp := c_io_resp_init;
signal io_req_copper : t_io_req;
signal io_resp_copper : t_io_resp := c_io_resp_init;
signal io_req_samp_cpu : t_io_req;
signal io_resp_samp_cpu : t_io_resp := c_io_resp_init;
signal dma_req_io : t_dma_req;
signal dma_resp_io : t_dma_resp := c_dma_resp_init;
signal dma_req_reu : t_dma_req;
signal dma_resp_reu : t_dma_resp := c_dma_resp_init;
signal dma_req_copper : t_dma_req;
signal dma_resp_copper : t_dma_resp := c_dma_resp_init;
signal dma_req : t_dma_req;
signal dma_resp : t_dma_resp := c_dma_resp_init;
signal slot_req : t_slot_req;
signal slot_resp : t_slot_resp := c_slot_resp_init;
signal slot_resp_reu : t_slot_resp := c_slot_resp_init;
signal slot_resp_cart : t_slot_resp := c_slot_resp_init;
signal slot_resp_sid : t_slot_resp := c_slot_resp_init;
signal slot_resp_cmd : t_slot_resp := c_slot_resp_init;
signal slot_resp_samp : t_slot_resp := c_slot_resp_init;
signal mem_req_slot : t_mem_req := c_mem_req_init;
signal mem_resp_slot : t_mem_resp := c_mem_resp_init;
signal mem_req_reu : t_mem_req := c_mem_req_init;
signal mem_resp_reu : t_mem_resp := c_mem_resp_init;
signal mem_req_samp : t_mem_req := c_mem_req_init;
signal mem_resp_samp : t_mem_resp := c_mem_resp_init;
-- signal mem_req_trace : t_mem_req;
-- signal mem_resp_trace : t_mem_resp;
signal mem_rack_slot : std_logic;
signal mem_dack_slot : std_logic;
signal sid_sample_left : signed(17 downto 0);
signal sid_sample_right : signed(17 downto 0);
signal sample_L : signed(17 downto 0);
signal sample_R : signed(17 downto 0);
begin
reset_button <= buttons(0) when control.swap_buttons='0' else buttons(2);
freeze_button <= buttons(2) when control.swap_buttons='0' else buttons(0);
i_split_64K: entity work.io_bus_splitter
generic map (
g_range_lo => 16,
g_range_hi => 16,
g_ports => 2 )
port map (
clock => clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_peri, -- 4040000
reqs(1) => io_req_dma, -- 4050000
resps(0) => io_resp_peri,
resps(1) => io_resp_dma );
i_bridge: entity work.io_to_dma_bridge
port map (
clock => clock,
reset => reset,
c64_stopped => status.c64_stopped,
io_req => io_req_dma,
io_resp => io_resp_dma,
dma_req => dma_req_io,
dma_resp => dma_resp_io );
i_split_8K: entity work.io_bus_splitter
generic map (
g_range_lo => 13,
g_range_hi => 15,
g_ports => 5 )
port map (
clock => clock,
req => io_req_peri,
resp => io_resp_peri,
reqs(0) => io_req_regs, -- 4040000
reqs(1) => io_req_sid, -- 4042000
reqs(2) => io_req_cmd, -- 4044000
reqs(3) => io_req_copper, -- 4046000
reqs(4) => io_req_samp_cpu, -- 4048000
resps(0) => io_resp_regs,
resps(1) => io_resp_sid,
resps(2) => io_resp_cmd,
resps(3) => io_resp_copper,
resps(4) => io_resp_samp_cpu );
i_registers: entity work.cart_slot_registers
generic map (
g_rom_base => g_rom_base_cart,
g_ram_base => g_ram_base_cart,
-- g_control_read => g_control_read,
g_ram_expansion => g_ram_expansion )
port map (
clock => clock,
reset => reset,
io_req => io_req_regs,
io_resp => io_resp_regs,
control => control,
status => status );
i_timing: entity work.slot_timing
port map (
clock => clock,
reset => reset,
-- Cartridge pins
PHI2 => PHI2,
BA => BA,
serve_vic => serve_vic,
serve_enable => serve_enable,
serve_inhibit => status.c64_stopped,
allow_serve => allow_serve,
timing_addr => control.timing_addr_valid,
edge_recover => control.phi2_edge_recover,
phi2_tick => phi2_tick_i,
phi2_recovered => phi2_recovered,
clock_det => status.clock_detect,
vic_cycle => vic_cycle,
inhibit => timing_inhibit,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_probe_end => do_probe_end,
do_io_event => do_io_event );
mem_req_slot.tag <= g_tag_slot;
mem_rack_slot <= '1' when mem_resp_slot.rack_tag = g_tag_slot else '0';
mem_dack_slot <= '1' when mem_resp_slot.dack_tag = g_tag_slot else '0';
i_slave: entity work.slot_slave
port map (
clock => clock,
reset => reset,
-- Cartridge pins
RSTn => RSTn,
IO1n => IO1n,
IO2n => IO2n,
ROMLn => ROMLn,
ROMHn => ROMHn,
GAMEn => GAMEn,
EXROMn => EXROMn,
RWn => RWn,
BA => BA,
ADDRESS => ADDRESS,
DATA_in => DATA,
DATA_out => slave_dout,
DATA_tri => slave_dtri,
-- interface with memory controller
mem_req => mem_req_slot.request,
mem_rwn => mem_req_slot.read_writen,
mem_wdata => mem_req_slot.data,
mem_size => mem_req_slot.size,
mem_rack => mem_rack_slot,
mem_dack => mem_dack_slot,
mem_rdata => mem_resp_slot.data,
mem_count => mem_resp.count,
-- mem_addr comes from cartridge logic
-- synchronized outputs
reset_out => actual_c64_reset,
-- timing inputs
phi2_tick => phi2_tick_i,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_io_event => do_io_event,
do_probe_end => do_probe_end,
-- interface with freezer (cartridge) logic
allow_serve => allow_serve,
serve_rom => serve_rom, -- ROML or ROMH
serve_io1 => serve_io1, -- IO1n
serve_io2 => serve_io2, -- IO2n
allow_write => allow_write,
-- kernal emulation
kernal_enable => control.kernal_enable,
kernal_probe => kernal_probe,
kernal_area => kernal_area,
force_ultimax => force_ultimax,
cpu_write => cpu_write,
epyx_timeout => epyx_timeout,
slot_req => slot_req,
slot_resp => slot_resp,
-- interface with hardware
BUFFER_ENn => BUFFER_ENn );
i_master: entity work.slot_master_v4
port map (
clock => clock,
reset => reset,
-- Cartridge pins
DMAn => dma_n,
BA => BA,
RWn_in => RWn,
RWn_out => rwn_out,
RWn_tri => rwn_tri,
ADDRESS_out => address_out,
ADDRESS_tri_h => address_tri_h,
ADDRESS_tri_l => address_tri_l,
DATA_in => DATA,
DATA_out => master_dout,
DATA_tri => master_dtri,
-- timing inputs
vic_cycle => vic_cycle,
phi2_recovered => phi2_recovered,
phi2_tick => phi2_tick_i,
do_sample_addr => do_sample_addr,
do_sample_io => do_sample_io,
do_io_event => do_io_event,
reu_dma_n => reu_dma_n,
cmd_if_freeze => cmd_if_freeze,
-- request from the cpu to do a cycle on the cart bus
dma_req => dma_req,
dma_resp => dma_resp,
-- system control
stop_cond => control.c64_stop_mode,
c64_stop => control.c64_stop,
c64_stopped => status.c64_stopped );
i_freeze: entity work.freezer
port map (
clock => clock,
reset => reset,
RST_in => reset_button,
button_freeze => freeze_button,
cpu_cycle_done => do_io_event,
cpu_write => cpu_write,
freezer_state => freezer_state,
unfreeze => unfreeze,
freeze_trig => freeze_trig,
freeze_act => freeze_act );
i_cart_logic: entity work.all_carts_v4
generic map (
g_rom_base => std_logic_vector(g_rom_base_cart),
g_ram_base => std_logic_vector(g_ram_base_cart) )
port map (
clock => clock,
reset => reset,
RST_in => reset_button,
c64_reset => control.c64_reset,
ethernet_enable => control.eth_enable,
freeze_trig => freeze_trig,
freeze_act => freeze_act,
unfreeze => unfreeze,
cart_logic => control.cartridge_type,
cart_kill => control.cartridge_kill,
epyx_timeout => epyx_timeout,
slot_req => slot_req,
slot_resp => slot_resp_cart,
mem_addr => mem_req_slot.address,
serve_enable => serve_enable,
serve_vic => serve_vic,
serve_rom => serve_rom, -- ROML or ROMH
serve_io1 => serve_io1, -- IO1n
serve_io2 => serve_io2, -- IO2n
allow_write => allow_write,
kernal_area => kernal_area,
kernal_enable => control.kernal_enable,
irq_n => irq_n,
nmi_n => nmi_n,
exrom_n => exrom_n,
game_n => game_n,
CART_LEDn => cart_led_n );
r_sid: if g_implement_sid generate
begin
-- i_trce: entity work.sid_trace
-- generic map (
-- g_mem_tag => X"CE" )
-- port map (
-- clock => clock,
-- reset => actual_c64_reset,
--
-- addr => unsigned(slot_addr(6 downto 0)),
-- wren => sid_write,
-- wdata => io_wdata,
--
-- phi2_tick => phi2_tick_i,
--
-- io_req => io_req_trace,
-- io_resp => io_resp_trace,
--
-- mem_req => mem_req_trace,
-- mem_resp => mem_resp_trace );
i_sid: entity work.sid_peripheral
generic map (
g_num_voices => g_sid_voices )
port map (
clock => clock,
reset => reset,
io_req => io_req_sid,
io_resp => io_resp_sid,
slot_req => slot_req,
slot_resp => slot_resp_sid,
start_iter => phi2_tick_i,
sample_left => sid_sample_left,
sample_right => sid_sample_right );
i_pdm_sid_L: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => sid_sample_left'length )
port map (
clock => clock,
reset => reset,
dac_in => sid_sample_left,
dac_out => sid_pwm_left );
i_pdm_sid_R: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => sid_sample_right'length )
port map (
clock => clock,
reset => reset,
dac_in => sid_sample_right,
dac_out => sid_pwm_right );
end generate;
g_cmd: if g_command_intf generate
i_cmd: entity work.command_interface
port map (
clock => clock,
reset => reset,
-- C64 side interface
slot_req => slot_req,
slot_resp => slot_resp_cmd,
freeze => cmd_if_freeze,
-- io interface for local cpu
io_req => io_req_cmd, -- we get an 8K range
io_resp => io_resp_cmd );
end generate;
g_reu: if g_ram_expansion generate
begin
i_reu: entity work.reu
generic map (
g_extended => g_extended_reu,
g_ram_base => g_ram_base_reu,
g_ram_tag => g_tag_reu )
port map (
clock => clock,
reset => actual_c64_reset,
-- register interface
slot_req => slot_req,
slot_resp => slot_resp_reu,
-- system interface
phi2_tick => do_io_event,
reu_dma_n => reu_dma_n,
size_ctrl => control.reu_size,
enable => control.reu_enable,
-- memory interface
mem_req => mem_req_reu,
mem_resp => mem_resp_reu,
dma_req => dma_req_reu,
dma_resp => dma_resp_reu );
end generate;
r_copper: if g_vic_copper generate
i_copper: entity work.copper
port map (
clock => clock,
reset => reset,
irq_n => IRQn,
phi2_tick => phi2_tick_i,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
io_req => io_req_copper,
io_resp => io_resp_copper,
dma_req => dma_req_copper,
dma_resp => dma_resp_copper,
slot_req => slot_req,
slot_resp => open ); -- never required, just snoop!
end generate;
r_sampler: if g_sampler generate
signal local_io_req : t_io_req := c_io_req_init;
signal local_io_resp : t_io_resp;
signal io_req_samp : t_io_req;
signal io_resp_samp : t_io_resp;
signal irq_samp : std_logic;
begin
i_io_bridge: entity work.slot_to_io_bridge
generic map (
g_io_base => X"48000", -- dont care in this context
g_slot_start => "100100000",
g_slot_stop => "111111111" )
port map (
clock => clock,
reset => reset,
enable => control.sampler_enable,
irq_in => irq_samp,
slot_req => slot_req,
slot_resp => slot_resp_samp,
io_req => local_io_req,
io_resp => local_io_resp );
i_io_arb_sampler: entity work.io_bus_arbiter_pri
generic map (
g_ports => 2 )
port map (
clock => clock,
reset => reset,
reqs(0) => io_req_samp_cpu,
reqs(1) => local_io_req,
resps(0) => io_resp_samp_cpu,
resps(1) => local_io_resp,
req => io_req_samp,
resp => io_resp_samp );
i_sampler: entity work.sampler
generic map (
g_num_voices => 8 )
port map (
clock => clock,
reset => actual_c64_reset,
io_req => io_req_samp,
io_resp => io_resp_samp,
mem_req => mem_req_samp,
mem_resp => mem_resp_samp,
irq => irq_samp,
sample_L => sample_L,
sample_R => sample_R,
new_sample => open );
i_pdm_samp_L: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => 18 )
port map (
clock => clock,
reset => reset,
dac_in => sample_L,
dac_out => samp_pwm_left );
i_pdm_samp_R: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 0,
g_invert => true,
g_use_mid_only => false,
g_width => 18 )
port map (
clock => clock,
reset => reset,
dac_in => sample_R,
dac_out => samp_pwm_right );
end generate;
slot_resp <= or_reduce(slot_resp_reu & slot_resp_cart & slot_resp_sid & slot_resp_cmd & slot_resp_samp);
p_probe_address_delay: process(clock)
variable kernal_probe_d : std_logic_vector(2 downto 0) := (others => '0');
begin
if rising_edge(clock) then
kernal_addr_out <= kernal_probe_d(0);
kernal_probe_d := kernal_probe & kernal_probe_d(kernal_probe_d'high downto 1);
end if;
end process;
ADDRESS(7 downto 0) <= address_out(7 downto 0) when address_tri_l='1' else (others => 'Z');
ADDRESS(12 downto 8) <= address_out(12 downto 8) when address_tri_h='1' else (others => 'Z');
ADDRESS(15 downto 13) <= "101" when (kernal_addr_out='1' and kernal_probe='1') else
address_out(15 downto 13) when address_tri_h='1' else (others => 'Z');
RWn <= rwn_out when rwn_tri='1' else 'Z';
DATA <= slave_dout when (slave_dtri='1') else
master_dout when (master_dtri='1') else (others => 'Z');
-- open drain outputs
irq_oc <= '0' when irq_n='0' or slot_resp.irq='1' else '1';
nmi_oc <= '0' when (control.c64_nmi='1') or (nmi_n='0') else '1';
rst_oc <= '0' when (reset_button='1' and status.c64_stopped='0' and mask_buttons='0') or
(control.c64_reset='1') else '1';
dma_oc <= '0' when (dma_n='0' or kernal_probe='1') else '1';
-- dma_oc <= '0' when (dma_n='0') else '1';
process(control, serve_enable, exrom_n, game_n, force_ultimax, kernal_probe)
begin
exrom_oc <= '1';
game_oc <= '1';
if (force_ultimax = '1') or (control.c64_ultimax = '1') then
game_oc <= '0';
elsif kernal_probe = '1' then
game_oc <= '0';
exrom_oc <= '0';
else
if (serve_enable='1' and exrom_n='0') then
exrom_oc <= '0';
end if;
if (serve_enable='1' and game_n='0') then
game_oc <= '0';
end if;
end if;
end process;
irq_push: entity work.oc_pusher port map(clock => clock, sig_in => irq_oc, oc_out => IRQn);
nmi_push: entity work.oc_pusher port map(clock => clock, sig_in => nmi_oc, oc_out => NMIn);
rst_push: entity work.oc_pusher port map(clock => clock, sig_in => rst_oc, oc_out => RSTn);
dma_push: entity work.oc_pusher port map(clock => clock, sig_in => dma_oc, oc_out => DMAn);
exr_push: entity work.oc_pusher port map(clock => clock, sig_in => exrom_oc, oc_out => EXROMn);
gam_push: entity work.oc_pusher port map(clock => clock, sig_in => game_oc, oc_out => GAMEn);
-- arbitration
i_dma_arb: entity work.dma_bus_arbiter_pri
generic map (
g_ports => 3 )
port map (
clock => clock,
reset => reset,
reqs(0) => dma_req_io,
reqs(1) => dma_req_reu,
reqs(2) => dma_req_copper,
resps(0) => dma_resp_io,
resps(1) => dma_resp_reu,
resps(2) => dma_resp_copper,
req => dma_req,
resp => dma_resp );
i_mem_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 3 )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_slot,
reqs(1) => mem_req_reu,
reqs(2) => mem_req_samp,
-- reqs(3) => mem_req_trace,
resps(0) => mem_resp_slot,
resps(1) => mem_resp_reu,
resps(2) => mem_resp_samp,
-- resps(3) => mem_resp_trace,
req => mem_req,
resp => mem_resp );
-- Delay the inhibit one clock cycle, because our
-- arbited introduces one clock cycle delay as well.
process(clock)
begin
if rising_edge(clock) then
memctrl_inhibit <= timing_inhibit;
end if;
end process;
phi2_tick <= phi2_tick_i;
c64_stopped <= status.c64_stopped;
end structural;
| gpl-3.0 | 4d479a6df0d88f33d0f272ecd90de7f6 | 0.463391 | 3.511542 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_sim/reu_tc_1.vhd | 5 | 6,290 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
use work.tl_string_util_pkg.all;
use work.tl_flat_memory_model_pkg.all;
use work.reu_pkg.all;
entity reu_tc_1 is
end reu_tc_1;
architecture testcase of reu_tc_1 is
shared variable errors : integer := 0;
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant c_reu_base : unsigned := X"DF00";
constant c_read_after_reset : t_byte_array(0 to 15) := (
X"10", -- status: version 0, no irq pending, done flag not set, no verify error, 256K or bigger.
X"10", -- command: only ff00 flag set
X"00", X"00", -- c64 base / addr
X"00", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"FF", X"FF", -- trans length
X"1F", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_1 : t_byte_array(0 to 15) := (
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask (all 3 bits set, other bits unused, thus 1)
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_verify_2 : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"B0", -- status: version 0, irq pending, done flag NOT set, verify error, 256K or bigger.
X"13", -- command: ff00 flag set, mode is verify
X"10", X"30", -- c64 base / addr
X"55", X"23", X"F9", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"10", X"00", -- trans length = 0x10 (error after 16 bytes, 16 to go)
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
constant c_read_after_swap : t_byte_array(0 to 15) := (
-- IRQ | DONE | ERR | SIZE | VERSION
X"D0", -- status: version 0, irq pending, done flag set, no verify error, 256K or bigger.
X"12", -- command: ff00 flag set, mode is swap
X"A0", X"30", -- c64 base / addr 3080+20
X"20", X"00", X"F8", -- reu base / addr (19 bits; upper 5 bits unused and thus 1)
X"01", X"00", -- trans length = 1
X"FF", -- irq mask
X"3F", -- control
X"FF", X"FF", X"FF", X"FF", X"FF" ); -- no register
procedure check(a,b : std_logic_vector; d: unsigned; s : string) is
begin
if a /= b then
print("ERROR: " & s & ": " & hstr(a) & "/=" & hstr(b) & " on addr " & hstr(d));
errors := errors + 1;
end if;
-- assert a = b report s severity error;
end procedure;
begin
i_harness: entity work.harness_reu
;
p_test: process
variable slot : p_slot_bus_master_bfm_object;
variable data : std_logic_vector(7 downto 0);
variable addr : unsigned(15 downto 0);
variable c64_mem : h_mem_object;
variable reu_mem : h_mem_object;
--variable datas : t_byte_array(0 to 15);
procedure reu_operation(op : std_logic_vector;
c64_addr : unsigned(15 downto 0);
reu_addr : unsigned(23 downto 0);
len : unsigned(15 downto 0) ) is
variable cmd : std_logic_vector(7 downto 0);
begin
cmd := X"90";
cmd(op'length-1 downto 0) := op;
slot_io_write(slot, c_reu_base + c_c64base_l, std_logic_vector(c64_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_c64base_h, std_logic_vector(c64_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_l, std_logic_vector(reu_addr( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_reubase_m, std_logic_vector(reu_addr(15 downto 8)));
slot_io_write(slot, c_reu_base + c_reubase_h, std_logic_vector(reu_addr(23 downto 16)));
slot_io_write(slot, c_reu_base + c_translen_l, std_logic_vector(len( 7 downto 0)));
slot_io_write(slot, c_reu_base + c_translen_h, std_logic_vector(len(15 downto 8)));
slot_io_write(slot, c_reu_base + c_command, cmd);
end procedure;
begin
wait for 150 ns;
bind_slot_bus_master_bfm("slot master", slot);
bind_mem_model("c64_memory", c64_mem);
bind_mem_model("reu_memory", reu_mem);
for i in c_read_after_reset'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_reset(i), addr, "Register read after reset not as expected.");
end loop;
for i in 0 to 255 loop
write_memory_8(c64_mem, std_logic_vector(to_unsigned(16#3000# + i, 32)),
std_logic_vector(to_unsigned(99+i*37, 8)));
end loop;
-- enable IRQ on done (and verify error for later), so that we can wait for it
slot_io_write(slot, c_reu_base + c_irqmask, X"E0");
-- try to copy something (16 bytes) from c64 to reu
reu_operation(c_mode_toreu, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
slot_io_read(slot, c_reu_base + c_status, data);
-- Verify the copied data
reu_operation(c_mode_verify, X"3000", X"012345", X"0010");
slot_wait_irq(slot);
for i in c_read_after_verify_1'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_1(i), addr, "Register read after verify 1 not as expected.");
end loop;
-- Verify operation 2: verify 32 bytes, of course this will fail, since we only copied 16 bytes
reu_operation(c_mode_verify, X"3000", X"012345", X"0020");
slot_wait_irq(slot);
for i in c_read_after_verify_2'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_verify_2(i), addr, "Register read after verify 2 not as expected.");
end loop;
-- Swap operation
reu_operation(c_mode_swap, X"3080", X"000000", X"0020");
slot_wait_irq(slot);
for i in c_read_after_swap'range loop
addr := c_reu_base + i;
slot_io_read(slot, addr, data);
check(data, c_read_after_swap(i), addr, "Register read after swap not as expected.");
end loop;
assert errors = 0 report "Errors encounted" severity failure;
wait;
end process;
end testcase;
| gpl-3.0 | 8393973c91b36a5d995bc9a43433deeb | 0.617011 | 2.684592 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/rom_coe.vhd | 1 | 3,818 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Company: LCR
-- Engineer: Emmanuel Bello
--
-- Create Date: 16:44:33 10/24/2013
-- Design Name:
-- Module Name: rom_coe - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.RetinaParameters.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rom_coe is
port(
clk: in std_logic;
address: in std_logic_vector(N_GAUSS_KERNEL_BW-1 downto 0);
data_out: out std_logic_vector(KERNEL_ROM_BW-1 downto 0)
);
end rom_coe;
architecture Behavioral of rom_coe is
type rom_coe_type is array (NUMBER_OF_KERNELS-1 downto 0) of std_logic_vector (KERNEL_ROM_BW-1 downto 0);
constant rom_coe_data : rom_coe_type :=
(
0 => ("0000101001000001010010000010100010000101000000001001110"),
1 => ("0000111011000001110110000011101000000111000000001101011"),
2 => ("0001001100100010011000000100100100001000101000000000000"),
3 => ("0001101011100011010010000110000110000000000000000000000"),
4 => ("0010110000000101010000000000000000000000000000000000000"),
5 => ("0010110110000101001010000000000000000000000000000000000"),
6 => ("1000000000000000000000000000000000000000000000000000000"),
7 => ("0000111010000001110100000011100110000111000100001101111"),
8 => ("0001001011000010010101000100100100001000111000000000000"),
9 => ("0001101001000011001111000110010000000000000000000000000"),
10 => ("0010101101100101010011000000000000000000000000000000000"),
11 => ("0010110000000101010000000000000000000000000000000000000"),
12 => ("0010110110000101001010000000000000000000000000000000000"),
13 => ("1000000000000000000000000000000000000000000000000000000"),
14 => ("0001001010000010010100000100100100001001000000000000000"),
15 => ("0001001011000010010101000100100100001000111000000000000"),
16 => ("0001101001000011001111000110010000000000000000000000000"),
17 => ("0010101101100101010011000000000000000000000000000000000"),
18 => ("0010110000000101010000000000000000000000000000000000000"),
19 => ("1000000000000000000000000000000000000000000000000000000"),
20 => ("1000000000000000000000000000000000000000000000000000000")
);
begin
rom: process(clk)
begin
if rising_edge(clk) then
data_out <=rom_coe_data(to_integer(resize(unsigned(address),N_GAUSS_KERNEL_BW)));
-- data_out <=rom_coe_data(0);
end if;
end process rom;
end architecture Behavioral;
| gpl-3.0 | eec487a9724628e77a08a395fce45528 | 0.730225 | 4.368421 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/testmem/example_design/testmem_prod.vhd | 1 | 10,062 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: testmem_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 64
-- C_READ_DEPTH_A : 64
-- C_ADDRA_WIDTH : 6
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 64
-- C_READ_DEPTH_B : 64
-- C_ADDRB_WIDTH : 6
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY testmem_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END testmem_prod;
ARCHITECTURE xilinx OF testmem_prod IS
COMPONENT testmem_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : testmem_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | abc980a4da4a718d3474f6eb1c7738e2 | 0.492447 | 3.827311 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op990_29.vhdl | 1 | 6,543 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmcout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net8
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net8,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net9,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net9
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 4ba797ac71091c4d82dc32241bc29d85 | 0.570533 | 3.063202 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/lpm_dff0_inst.vhd | 1 | 144 | lpm_dff0_inst : lpm_dff0 PORT MAP (
aclr => aclr_sig,
clock => clock_sig,
data => data_sig,
enable => enable_sig,
q => q_sig
);
| gpl-2.0 | 8a36892f3c67fce3647e7f35b7714543 | 0.555556 | 2.322581 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/vram/simulation/vram_tb.vhd | 1 | 4,493 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: vram_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY vram_tb IS
END ENTITY;
ARCHITECTURE vram_tb_ARCH OF vram_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
vram_synth_inst:ENTITY work.vram_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| mit | de93babaeda2e20cd251545108154662 | 0.614511 | 4.612936 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/old/ss5_logic.vhd | 5 | 5,060 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ss5_logic is
generic (
ram_base : std_logic_vector(27 downto 0) := X"0052000";
rom_base : std_logic_vector(27 downto 0) := X"1030000" );
port (
clock : in std_logic;
reset : in std_logic;
RSTn_in : in std_logic;
cart_kill : in std_logic := '0';
freeze_trig : in std_logic;
freeze_act : in std_logic;
unfreeze : out std_logic;
io_write : in std_logic;
io_addr : in std_logic_vector(8 downto 0);
io_data : in std_logic_vector(7 downto 0);
serve_enable : out std_logic; -- enables fetching bus address PHI2=1
serve_vic : out std_logic; -- enables doing so for PHI2=0
serve_rom : out std_logic; -- ROML or ROMH
serve_io1 : out std_logic; -- IO1n
serve_io2 : out std_logic; -- IO2n
allow_write : out std_logic;
slot_addr : in std_logic_vector(15 downto 0);
mem_addr : out std_logic_vector(25 downto 0);
irq_n : out std_logic;
nmi_n : out std_logic;
exrom_n : out std_logic;
game_n : out std_logic;
CART_LEDn : out std_logic );
end ss5_logic;
architecture gideon of ss5_logic is
signal cart_ctrl : std_logic_vector(7 downto 0);
signal reset_in : std_logic;
signal cart_en : std_logic;
signal freeze_act_d: std_logic;
alias rom_enable_n : std_logic is cart_ctrl(3);
alias ram_enable_n : std_logic is cart_ctrl(1);
alias game_ctrl_n : std_logic is cart_ctrl(0);
alias exrom_ctrl : std_logic is cart_ctrl(1);
signal bank_reg : std_logic_vector(1 downto 0);
signal mode : std_logic_vector(2 downto 0);
constant c_serve_en : std_logic_vector(0 to 7) := "11111000";
-- Bit 0 controls the GAME line: 0 pulls it low, 1 leaves it high
-- Bit 1 enables Ram: 0= enabled, 1=disabled
-- this bit also controls the Exrom line: 0: Exrom=1, 1:Exrom=0 (inverted!)
-- Bit 2 banking address line 14
-- Bit 3 enables Rom: 0=enabled, 1=disabled. Caution: Disabling rom also
-- disables this register, so make sure that Ram is enabled in order to
-- release the Exrom line!
-- Bit 4 banking address line 15
-- Bit 5 banking address line 16
begin
mode <= cart_ctrl(3) & cart_ctrl(1) & cart_ctrl(0);
bank_reg <= cart_ctrl(4) & cart_ctrl(2);
exrom_n <= not exrom_ctrl;
game_n <= game_ctrl_n;
unfreeze <= not game_ctrl_n; -- game goes low, unfreeze goes high
process(clock)
begin
if rising_edge(clock) then
reset_in <= not RSTn_in or reset;
freeze_act_d <= freeze_act;
-- flipflops
if io_write='1' and io_addr(8) = '0' and rom_enable_n='0' then
cart_ctrl <= io_data;
end if;
if cart_kill='1' then
rom_enable_n <= '1';
ram_enable_n <= '1';
game_ctrl_n <= '1';
exrom_ctrl <= '0';
end if;
-- reset
if reset_in='1' or (freeze_act='1' and freeze_act_d='0') then
cart_ctrl <= X"00";
end if;
end if;
end process;
-- open drains
irq_n <= not(freeze_trig or freeze_act);
nmi_n <= not(freeze_trig or freeze_act);
-- determine address
process(slot_addr, mode, cart_ctrl)
begin
allow_write <= '0';
if mode(1 downto 0)="00" then
if slot_addr(15 downto 13)="100" then
allow_write <= '1';
mem_addr <= ram_base(25 downto 13) & slot_addr(12 downto 0);
else
mem_addr <= rom_base(25 downto 16) & bank_reg & slot_addr(13 downto 0);
end if;
else
mem_addr <= rom_base(25 downto 16) & bank_reg & slot_addr(13 downto 0);
end if;
end process;
CART_LEDn <= rom_enable_n;
serve_vic <= '0';
serve_rom <= not rom_enable_n;
serve_io1 <= not rom_enable_n;
serve_io2 <= not rom_enable_n;
-- cart_ctrl(7 downto 6) is unused
serve_enable <= c_serve_en(to_integer(unsigned(mode)));
end gideon;
-- %xxxx0x00: game=0, exrom=1. 8000=RAM E000=ROM IO=ROM (ultimax) RAM ROM
-- %xxxx0x01: game=1, exrom=1. 8000=--- A000=--- IO=ROM [RAM] ROM
-- %xxxx0x10: game=0, exrom=0. 8000=ROM A000=ROM IO=ROM ROM
-- %xxxx0x11: game=1, exrom=0. 8000=ROM A000=--- IO=ROM ROM
-- %xxxx1x00: game=0, exrom=1. 8000=RAM E000=--- IO=--- (ultimax) RAM
-- %xxxx1x01: game=1, exrom=1. 8000=--- A000=--- IO=--- [RAM]
-- %xxxx1x10: game=0, exrom=0. 8000=XXX A000=XXX IO=---
-- %xxxx1x11: game=1, exrom=0. 8000=XXX A000=--- IO=---
| gpl-3.0 | 1f370aed317d262894d5d2df535aacf6 | 0.524506 | 3.224984 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op14.vhdl | 1 | 9,997 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9.45e-06,
W => Wdiff_0,
Wdiff_0init => 1.545e-05,
scope => private
)
port map(
D => net2,
G => in1,
S => net5
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9.45e-06,
W => Wdiff_0,
Wdiff_0init => 1.545e-05,
scope => private
)
port map(
D => net1,
G => in2,
S => net5
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => W_0,
W_0init => 1.25e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9.45e-06,
W => Wdiff_0,
Wdiff_0init => 1.545e-05,
scope => private
)
port map(
D => net6,
G => in1,
S => net5
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 9.45e-06,
W => Wdiff_0,
Wdiff_0init => 1.545e-05,
scope => private
)
port map(
D => net6,
G => in2,
S => net5
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.29e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.15e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.29e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.15e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.29e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.15e-06,
scope => private
)
port map(
D => net1,
G => net6,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 1.29e-05,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1.15e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => L_2,
L_2init => 3e-06,
W => Wsrc_1,
Wsrc_1init => 1.6e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => L_3,
L_3init => 6.75e-06,
W => Wsrc_1,
Wsrc_1init => 1.6e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcm_2,
Wcm_2init => 7.75e-06,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcmout_2,
Wcmout_2init => 6.215e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcm_2,
Wcm_2init => 7.75e-06,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcmout_2,
Wcmout_2init => 6.215e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => out2,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => Wcursrc_3,
Wcursrc_3init => 7.135e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet6_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => Wcursrc_3,
Wcursrc_3init => 7.135e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net7,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net10,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net9,
N => net7
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => W_1,
W_1init => 1.82e-05
)
port map(
D => net8,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 8.35e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 7.035e-05,
scope => private
)
port map(
D => net10,
G => vref,
S => net8
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 8.35e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 7.035e-05,
scope => private
)
port map(
D => net9,
G => net7,
S => net8
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 8.85e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1.4e-06,
scope => private
)
port map(
D => net9,
G => net9,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 8.85e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1.4e-06,
scope => private
)
port map(
D => net10,
G => net9,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 9.5e-07,
W => Wcmbias_0,
Wcmbias_0init => 7.285e-05,
scope => private
)
port map(
D => out1,
G => net10,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 9.5e-07,
W => Wcmbias_0,
Wcmbias_0init => 7.285e-05,
scope => private
)
port map(
D => out2,
G => net10,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => (pfak)*(WBias),
WBiasinit => 4.3e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 9e-07,
W => (pfak)*(WBias),
WBiasinit => 4.3e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 9e-07,
W => WBias,
WBiasinit => 4.3e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => WBias,
WBiasinit => 4.3e-06
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => WBias,
WBiasinit => 4.3e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 9e-07,
W => WBias,
WBiasinit => 4.3e-06
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 6c8bd39fc119f22a943fbbd3faff5f6c | 0.56737 | 2.817644 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/HorizontalConvolution.vhd | 1 | 4,647 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_dFUlzF
-- /___/ /\ Timestamp : 04/05/2014 20:58:24
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use work.RetinaParameters.ALL;
entity HorizontalConvolution is
port ( clk : in std_logic;
rst : in std_logic;
enableIn : in std_logic;
gaussianKernel : in std_logic_vector (KERNEL_ROM_BW-1 downto 0);
inputData : in T_INPUT_HORIZONTAL_CONVOLUTION;
enableOut : out std_logic;
outputData : out std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0)
);
end HorizontalConvolution;
architecture BEHAVIORAL of HorizontalConvolution is
signal s1_horiz_conv_array : T_S1_HORIZ_CONV;
signal s1_horiz_enable: std_logic;
signal s2_horiz_conv_array : T_S2_HORIZ_CONV;
signal s2_horiz_enable: std_logic;
signal s3_horiz_conv: std_logic_vector(S3_HORIZ_CONV_BW-1 downto 0);
begin
filtrar: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s1_horiz_conv_array <= (others =>(others => '0'));
s1_horiz_enable <= '0';
s2_horiz_conv_array <= (others =>(others => '0'));
s2_horiz_enable <= '0';
s3_horiz_conv <= (others => '0');
else
if enableIn = '1' then
--step 1
loop1: for i in 0 to (KERNEL_SIZE_ROM-1)-1 loop
s1_horiz_conv_array((KERNEL_SIZE_ROM-1)-i) <= std_logic_vector(resize(unsigned(inputData(i)) +
unsigned(inputData(KERNEL_SIZE-1-i)),
s1_horiz_conv_array(0)'length));
end loop loop1;
s1_horiz_conv_array(0) <= std_logic_vector(resize(unsigned(inputData(KERNEL_SIZE_ROM-1)),
s1_horiz_conv_array(0)'length));
end if;
s1_horiz_enable <= enableIn;
if s1_horiz_enable = '1' then
--step 2
loop2: for j in 0 to (KERNEL_SIZE_ROM-1) loop
s2_horiz_conv_array(j) <=
std_logic_vector(resize(unsigned(s1_horiz_conv_array(j)) *
unsigned(gaussianKernel(
GAUSSIAN_COE_BW*(KERNEL_SIZE_ROM-j) -1
downto
GAUSSIAN_COE_BW*(KERNEL_SIZE_ROM -j) -GAUSSIAN_COE_BW
)), s2_horiz_conv_array(0)'length));
end loop loop2;
end if;
s2_horiz_enable <= s1_horiz_enable;
if s2_horiz_enable = '1' then
--step 3
s3_horiz_conv <= std_logic_vector(resize(
((unsigned(s2_horiz_conv_array(0)) + unsigned(s2_horiz_conv_array(1)))+
(unsigned(s2_horiz_conv_array(2)) + unsigned(s2_horiz_conv_array(3))))
+
(unsigned(s2_horiz_conv_array(4)))--+
--(unsigned(s2_horiz_conv_array(6)) + unsigned(s2_horiz_conv_array(7))))
--+
--((unsigned(s2_horiz_conv_array(8)) + unsigned(s2_horiz_conv_array(9)))+
--(unsigned(s2_horiz_conv_array(10)) + unsigned(s2_horiz_conv_array(11))))
--+
--((unsigned(s2_horiz_conv_array(12)) + unsigned(s2_horiz_conv_array(13)))+
--(unsigned(s2_horiz_conv_array(14))))
, s3_horiz_conv'length));
end if;
enableOut <= s2_horiz_enable;
end if;
end if;
end process filtrar;
outputData <= s3_horiz_conv(S3_HORIZ_CONV_BW-1 downto SCALE_FACTOR_SH);
end BEHAVIORAL;
| gpl-3.0 | 133bf18e3926e2b53c1bb59bfa045c46 | 0.570476 | 3.265636 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_sim/tb_alu.vhd | 5 | 4,474 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.file_io_pkg.all;
library std;
use std.textio.all;
entity tb_alu is
end tb_alu;
architecture tb of tb_alu is
signal c_in : std_logic := '0';
signal data_a : std_logic_vector(7 downto 0) := X"00";
signal data_b : std_logic_vector(7 downto 0) := X"00";
signal n_out : std_logic;
signal v_out : std_logic;
signal z_out : std_logic;
signal c_out : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal p_out : std_logic_vector(7 downto 0);
signal operation : std_logic_vector(2 downto 0) := "011"; -- ADC
signal p_reference : std_logic_vector(7 downto 0);
signal n_ref : std_logic;
signal v_ref : std_logic;
signal z_ref : std_logic;
signal c_ref : std_logic;
begin
p_out <= n_out & v_out & "111" & '0' & z_out & c_out;
ref_sum: process -- taken from real 6510
begin
wait for 1 ps;
if operation(2)='0' then -- adc
p_reference <= X"3A"; wait for 1 us;
p_reference <= X"38"; wait for 121 us;
p_reference <= X"F8"; wait for 6 us;
p_reference <= X"B8"; wait for 26 us;
p_reference <= X"B9"; wait for 96 us;
p_reference <= X"39"; wait for 6 us;
-- 01
p_reference <= X"38"; wait for 121 us;
p_reference <= X"F8"; wait for 7 us;
p_reference <= X"B8"; wait for 25 us;
p_reference <= X"B9"; wait for 96 us;
p_reference <= X"39"; wait for 6 us;
p_reference <= X"3B"; wait for 1 us;
else
p_reference <= X"3B"; wait for 1 us;
p_reference <= X"B8"; wait for 127 us;
p_reference <= X"F8"; wait for 1 us;
p_reference <= X"38"; wait for 127 us;
-- 01
p_reference <= X"39"; wait for 1 us;
p_reference <= X"3B"; wait for 1 us;
p_reference <= X"B8"; wait for 126 us;
p_reference <= X"F8"; wait for 2 us;
p_reference <= X"38"; wait for 126 us;
end if;
p_reference <= (others => 'U');
wait;
end process;
n_ref <= p_reference(7);
v_ref <= p_reference(6);
z_ref <= p_reference(1);
c_ref <= p_reference(0);
test: process
variable L : line;
begin
for i in 0 to 3 loop
-- data_a <= conv_std_logic_vector((i mod 10) + (i/10)*16,8);
data_a <= conv_std_logic_vector(i,8);
for j in 0 to 255 loop
data_b <= conv_std_logic_vector(j,8);
c_in <= operation(2);
wait for 500 ns;
-- check flags
assert c_out = c_ref or c_ref = 'U' report "Error in C-flag!" severity error;
assert z_out = z_ref or z_ref = 'U' report "Error in Z-flag!" severity error;
assert v_out = v_ref or v_ref = 'U' report "Error in V-flag!" severity error;
assert n_out = n_ref or n_ref = 'U' report "Error in N-flag!" severity error;
wait for 500 ns;
-- write(L, VecToHex(data_out, 2));
-- write(L, VecToHex(p_out, 2));
-- write(L, ',');
-- c_in <= '1';
-- wait for 1 us;
end loop;
-- writeline(output, L);
end loop;
wait;
end process;
mut: entity work.alu
generic map (true)
port map (
operation => operation,
enable => '1',
n_in => 'U',
v_in => 'U',
z_in => 'U',
c_in => c_in,
d_in => '1',
data_a => data_a,
data_b => data_b,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
data_out => data_out );
end tb; | gpl-3.0 | 68003b922bbf90d12af408d031a9e82c | 0.428923 | 3.556439 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/c1541_timing.vhd | 4 | 2,249 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity c1541_timing is
port (
clock : in std_logic;
reset : in std_logic;
use_c64_reset : in std_logic;
c64_reset_n : in std_logic;
iec_reset_n : in std_logic;
iec_reset_o : out std_logic;
drive_stop : in std_logic;
drv_clock_en : out std_logic; -- 1/12.5 (4 MHz)
cpu_clock_en : out std_logic ); -- 1/50 (1 MHz)
end c1541_timing;
architecture Gideon of c1541_timing is
signal div_cnt : unsigned(3 downto 0) := "0000";
signal pre_cnt : unsigned(1 downto 0) := "00";
signal cpu_clock_en_i : std_logic := '0';
signal toggle : std_logic := '0';
signal iec_reset_sh : std_logic_vector(0 to 2) := "000";
signal c64_reset_sh : std_logic_vector(0 to 2) := "000";
begin
process(clock)
begin
if rising_edge(clock) then
drv_clock_en <= '0';
cpu_clock_en_i <= '0';
if drive_stop='0' then
if (div_cnt = X"B" and toggle='0') or
(div_cnt = X"C" and toggle='1') then
div_cnt <= X"0";
drv_clock_en <= '1';
toggle <= not toggle;
pre_cnt <= pre_cnt + 1;
if pre_cnt = "11" then
cpu_clock_en_i <= '1';
end if;
else
div_cnt <= div_cnt + 1;
end if;
end if;
if cpu_clock_en_i = '1' then
iec_reset_sh(0) <= not iec_reset_n;
iec_reset_sh(1 to 2) <= iec_reset_sh(0 to 1);
c64_reset_sh(0) <= use_c64_reset and not c64_reset_n;
c64_reset_sh(1 to 2) <= c64_reset_sh(0 to 1);
end if;
if reset='1' then
toggle <= '0';
pre_cnt <= (others => '0');
div_cnt <= (others => '0');
end if;
end if;
end process;
cpu_clock_en <= cpu_clock_en_i;
iec_reset_o <= '1' when (iec_reset_sh="111") or (c64_reset_sh="111") else '0';
end Gideon;
| gpl-3.0 | d1dec5e49c4665fad2e2782ce537ab69 | 0.445976 | 3.181047 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/TOP_DESIGN.vhd | 1 | 5,188 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 00:09:09 06/06/2014
-- Design Name:
-- Module Name: TOP_DESIGN - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.RetinaParameters.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity TOP_DESIGN is
port (
CLK : in std_logic;
RST : in std_logic;
ENABLE_IN : in std_logic;
DATA_IN : in std_logic_vector (7 downto 0);
DATA_OUT : OUT std_logic_vector (7 downto 0);
ENABLE_OUT : OUT std_logic
);
end TOP_DESIGN;
architecture Behavioral of TOP_DESIGN is
signal ENABLE : std_logic;
signal IMG_BASE_ADDR : std_logic_vector (31 downto 0);
signal KPTS_ADDR : std_logic_vector (31 downto 0);
signal KPT_DATA : std_logic_vector (31 downto 0);
signal PIXEL_DATA : std_logic_vector (PIXEL_BW-1 downto 0);
signal KPT_ADDR_MEM : std_logic_vector (31 downto 0);
signal PIXEL_ADDR_MEM: std_logic_vector (31 downto 0);
signal DESCRIPTOR : std_logic_vector (DESCRIPTOR_SIZE-1 downto 0);
signal ENABLEOUT : std_logic;
signal KPT_READ_MEM : std_logic;
signal PIXEL_READ_MEM : std_logic;
component RetinaDescriptorGenerator is
port ( CLK : in std_logic;
ENABLE : in std_logic;
IMG_BASE_ADDR : in std_logic_vector (31 downto 0);
KPTS_ADDR : in std_logic_vector (31 downto 0);
KPT_DATA : in std_logic_vector (31 downto 0);
PIXEL_DATA : in std_logic_vector (PIXEL_BW-1 downto 0);
RST : in std_logic;
KPT_ADDR_MEM : out std_logic_vector (31 downto 0);
PIXEL_ADDR_MEM: out std_logic_vector (31 downto 0);
DESCRIPTOR : out std_logic_vector (DESCRIPTOR_SIZE-1 downto 0);
ENABLEOUT : out std_logic;
KPT_READ_MEM : out std_logic;
PIXEL_READ_MEM : out std_logic
);
end component;
begin
retina: RetinaDescriptorGenerator
port map(
CLK => CLK,
ENABLE => ENABLE,
IMG_BASE_ADDR => IMG_BASE_ADDR,
KPTS_ADDR => KPTS_ADDR,
KPT_DATA => KPT_DATA,
PIXEL_DATA => PIXEL_DATA,
RST => RST,
KPT_ADDR_MEM => KPT_ADDR_MEM,
PIXEL_ADDR_MEM => PIXEL_ADDR_MEM,
DESCRIPTOR => DESCRIPTOR,
ENABLEOUT => ENABLEOUT,
KPT_READ_MEM => KPT_READ_MEM,
PIXEL_READ_MEM => PIXEL_READ_MEM
);
process(clk)
begin
if rising_edge(clk)then
if rst = '1' then
ENABLE <= '0';
IMG_BASE_ADDR<= (others => '0');
KPTS_ADDR <= (others => '0');
KPT_DATA <= (others => '0');
PIXEL_DATA <= (others => '0');
elsif ENABLE_IN = '1' then
case DATA_IN is
when "00000001" => --cargar registro IMG_BASE_ADDR
IMG_BASE_ADDR <= "00000000000000000000000000100000";
when "00000010" => -- cargar registro KPTS_ADDR
KPTS_ADDR <= "00000000000000000000000000000000";
when "00000011" => -- cargar registro KPTS_ADDR
KPT_DATA <= "00000000001000000001000000100000";
when "00000100" => -- cargar registro KPTS_ADDR
PIXEL_DATA <= "00100100";
when "00000101" => -- RUN!
ENABLE <= '1';
end case;
if
end if;
end if;
end process;
end Behavioral;
| gpl-3.0 | 5a659b39d4405360c552be6e9e9d9c0c | 0.555898 | 3.921391 | false | false | false | false |
KB777/1541UltimateII | fpga/io/debug/vhdl_source/logic_analyzer_32.vhd | 1 | 5,028 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.endianness_pkg.all;
entity logic_analyzer_32 is
generic (
g_timer_div : positive := 50 );
port (
clock : in std_logic;
reset : in std_logic;
ev_dav : in std_logic;
ev_data : in std_logic_vector(7 downto 0);
---
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
io_req : in t_io_req;
io_resp : out t_io_resp );
end logic_analyzer_32;
architecture gideon of logic_analyzer_32 is
signal enable_log : std_logic;
signal ev_timer : integer range 0 to g_timer_div-1;
signal ev_tick : std_logic;
signal ev_data_c : std_logic_vector(15 downto 0);
signal ev_data_d : std_logic_vector(15 downto 0);
signal ev_wdata : std_logic_vector(31 downto 0);
signal ev_addr : unsigned(23 downto 0);
signal stamp : unsigned(14 downto 0);
type t_state is (idle, writing);
signal state : t_state;
signal sub, task : std_logic_vector(3 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
if ev_timer = 0 then
ev_tick <= '1';
ev_timer <= g_timer_div - 1;
else
ev_tick <= '0';
ev_timer <= ev_timer - 1;
end if;
if ev_tick = '1' then
if stamp /= 32766 then
stamp <= stamp + 1;
end if;
end if;
ev_data_c <= sub & task & ev_data;
case state is
when idle =>
if enable_log = '1' then
if ev_dav='1' or ev_tick='1' then
if (ev_data_c /= ev_data_d) or (ev_dav = '1') then
ev_wdata <= ev_data_c & ev_dav & std_logic_vector(stamp);
ev_data_d <= ev_data_c;
stamp <= (others => '0');
state <= writing;
end if;
end if;
end if;
when writing =>
mem_req.data <= byte_swap(ev_wdata);
mem_req.request <= '1';
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 4;
mem_req.request <= '0';
state <= idle;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "011" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "000" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= X"0" & sub;
when "101" =>
io_resp.data <= X"0" & task;
when others =>
null;
end case;
elsif io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "111" =>
ev_addr <= (others => '0');
ev_data_d <= (others => '0'); -- to trigger first entry
stamp <= (others => '0');
enable_log <= '1';
when "110" =>
enable_log <= '0';
when "101" =>
task <= io_req.data(3 downto 0);
when "100" =>
sub <= io_req.data(3 downto 0);
when others =>
null;
end case;
end if;
if reset='1' then
state <= idle;
sub <= X"0";
task <= X"0";
enable_log <= '0';
ev_timer <= 0;
mem_req.request <= '0';
mem_req.data <= (others => '0');
ev_addr <= (others => '0');
stamp <= (others => '0');
ev_data_c <= (others => '0');
ev_data_d <= (others => '0');
end if;
end if;
end process;
mem_req.tag <= X"F0";
mem_req.address <= "01" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.byte_en <= "1111";
end gideon;
| gpl-3.0 | a1ab2e8d66c8e3245289dd9a7dcc4e99 | 0.392601 | 3.9653 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/AddressGenerator.vhd | 1 | 8,901 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_A26CnV
-- /___/ /\ Timestamp : 04/06/2014 00:33:30
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use work.RetinaParameters.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
entity AddressGenerator is
port ( busy_in : in std_logic;
clk : in std_logic;
imgBaseAddr : in std_logic_vector (31 downto 0);
kptCoordX : in std_logic_vector (KPT_COORD_BW-1 downto 0);--keypoint's column possition
kptCoordY : in std_logic_vector (KPT_COORD_BW-1 downto 0); --keypoint's row possition
kptScale : in std_logic_vector(KPT_SCALE_BW-1 downto 0);--keypoint's scale
kptOctave : in std_logic_vector(KPT_OCTAVE_BW-1 downto 0);--keypoint's octave
request_in : in std_logic;
rst : in std_logic;
kptScaleOut : out std_logic_vector(KPT_SCALE_BW-1 downto 0);--keypoint's scale
addr : out std_logic_vector (31 downto 0);
busy_out : out std_logic;
request_out : out std_logic
);
end AddressGenerator;
architecture BEHAVIORAL of AddressGenerator is
type points_coord_type is array(11 downto 0) of integer range -23 to 23;
type rom_coord_type is array (20 downto 0) of points_coord_type;
--coordinates of each point on the retina pattern, from OUTER to INNER
constant rom_coord_data : rom_coord_type :=
(
0 => (23,0,12,20,-12,20,-23,0,-12,-20,12,-20),
1 => (15,9,0,17,-15,9,-15,-9,0,-17,15,-9),
2 => (13,0,6,11,-6,11,-13,0,-6,-11,6,-11),
3 => (8,4,0,9,-8,4,-8,-4,0,-9,8,-4),
4 => (6,0,3,5,-3,5,-6,0,-3,-5,3,-5),
5 => (3,2,0,4,-3,2,-3,-2,0,-4,3,-2),
6 => (3,0,1,3,-1,3,-3,0,-1,-3,1,-3),
7 => (18,0,9,16,-9,16,-18,0,-9,-16,9,-16),
8 => (12,7,0,14,-12,7,-12,-7,0,-14,12,-7),
9 => (10,0,5,9,-5,9,-10,0,-5,-9,5,-9),
10 => (6,3,0,7,-6,3,-6,-3,0,-7,6,-3),
11 => (5,0,2,4,-2,4,-5,0,-2,-4,2,-4),
12 => (3,2,0,3,-3,2,-3,-2,0,-3,3,-2),
13 => (2,0,1,2,-1,2,-2,0,-1,-2,1,-2),
14 => (15,0,7,13,-7,13,-15,0,-7,-13,7,-13),
15 => (10,5,0,11,-10,6,-10,-5,0,-11,10,-5),
16 => (8,0,4,7,-4,7,-8,0,-4,-7,4,-7),
17 => (5,3,0,6,-5,3,-5,-3,0,-6,5,-3),
18 => (4,0,2,3,-2,3,-4,0,-2,-3,2,-3),
19 => (2,1,0,2,-2,1,-2,-1,0,-2,2,-1),
20 => (2,0,1,2,-1,2,-2,0,-1,-2,1,-2)
);
signal point_set_id: integer range 0 to 7;--describes each point set included the center of the retina pattern(the keypoint's possition)
signal point_addr: std_logic_vector(31 downto 0);
signal select_pair: integer range 0 to 5;
type consumer_FSM_states is (INIT, REQ, WAITING, READY);
signal s_consumerState: consumer_FSM_states;
type producer_FSM_states is (INIT, REQ);
signal s_producerState: producer_FSM_states;
begin
consumer_proc: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_consumerState <= INIT;
request_out <= '0';
else
case s_consumerState is
when INIT =>
if busy_in = '0' then
request_out <= '1';
s_consumerState <= REQ;
end if;
when REQ =>
if busy_in = '1' then
request_out <= '0';
s_consumerState <= WAITING;
end if;
when WAITING =>
if busy_in = '0' then
s_consumerState <= READY;
end if;
when READY =>
if select_pair = 5 and point_set_id = 7 then
s_consumerState <= INIT;
end if;
end case;
end if;
end if;
end process;
producer_proc: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_producerState <= INIT;
busy_out <= '0';
else
case s_producerState is
when INIT =>
if request_in = '1' then
busy_out <= '1';
s_producerState <= REQ;
end if;
when REQ =>
if s_consumerState = READY then
busy_out <= '0';
s_producerState <= INIT;
end if;
end case;
end if;
end if;
end process;
addr_generation_proc: process(clk)
--variable tmp1: integer range -1023 to 1023;
--variable tmp2: integer range -1023*IMAGE_WIDTH to 1023*IMAGE_WIDTH;
variable coordArray: points_coord_type;
begin
if rising_edge(clk) then
if rst = '1' then
point_set_id <= 0;
select_pair <= 5;
point_addr <= (others => '0');
kptScaleOut <= (others => '0');
elsif s_consumerState = READY and s_producerState = REQ then
if point_set_id = 7 then
point_addr <= std_logic_vector(
to_unsigned(
to_integer(unsigned(imgBaseAddr)) +
to_integer(unsigned(kptOctave))*IMAGE_WIDTH*IMAGE_HEIGHT +
to_integer(unsigned(kptCoordX)) +
(to_integer(unsigned(kptCoordY)))*IMAGE_WIDTH
, point_addr'length)
);
else
coordArray := rom_coord_data(point_set_id + 7*to_integer(unsigned(kptScale)));
point_addr <= std_logic_vector(
to_unsigned(
to_integer(unsigned(imgBaseAddr)) +
to_integer(unsigned(kptOctave))*IMAGE_WIDTH*IMAGE_HEIGHT +
to_integer(unsigned(kptCoordX)) + coordArray(select_pair*2+1) +
(to_integer(unsigned(kptCoordY)) + coordArray(select_pair*2))*IMAGE_WIDTH
, point_addr'length)
);
end if;
-- if point_set_id = 7 then
-- tmp1 := to_integer(unsigned(kptCoordX));
-- tmp2 := (to_integer(unsigned(kptCoordY)))*IMAGE_WIDTH;
-- else
-- coordArray := rom_coord_data(point_set_id + 7*to_integer(unsigned(kptScale)));
-- tmp1 := to_integer(unsigned(kptCoordX)) + coordArray(select_pair*2+1);--column possition offset
-- tmp2 := (to_integer(unsigned(kptCoordY)) + coordArray(select_pair*2))*IMAGE_WIDTH;--row possition offset
-- end if;
-- point_addr <= std_logic_vector(
-- to_unsigned(
-- to_integer(unsigned(imgBaseAddr)) +
-- to_integer(unsigned(kptOctave))*IMAGE_WIDTH*IMAGE_HEIGHT +
--
-- tmp1 + tmp2
--
--
-- , point_addr'length)
-- );
kptScaleOut <= kptScale;
if point_set_id = 7 then
point_set_id <= 0;
select_pair <= 5;
elsif select_pair = 0 then
select_pair <= 5;
point_set_id <= point_set_id + 1;
else
select_pair <= select_pair -1;
end if;
end if;
end if;--rising_edge(clk)
end process;
addr <= point_addr;
end BEHAVIORAL;
| gpl-3.0 | 13b3d26b3d21add36e86f865a2aa6a41 | 0.489271 | 3.418203 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op330_7.vhdl | 1 | 5,068 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net2,
G => net2,
S => gnd
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmcout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => out1,
N => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net3
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 9ef7d565c0aaca9b9ba513d98f980ec9 | 0.579321 | 3.159601 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_sim/tb_sram8bit32.vhd | 5 | 2,584 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_sram_8bit32 is
end tb_sram_8bit32;
architecture tb of tb_sram_8bit32 is
signal clock : std_logic := '0';
signal reset : std_logic := '0';
signal req : std_logic := '0';
signal readwriten : std_logic := '1';
signal address : std_logic_vector(19 downto 0) := (others => '0');
signal rack : std_logic;
signal dack : std_logic;
signal wdata : std_logic_vector(7 downto 0) := X"12";
signal rdata : std_logic_vector(7 downto 0);
signal SRAM_A : std_logic_vector(17 downto 0);
signal SRAM_OEn : std_logic;
signal SRAM_WEn : std_logic;
signal SRAM_CSn : std_logic;
signal SRAM_D : std_logic_vector(31 downto 0) := (others => 'Z');
signal SRAM_BEn : std_logic_vector(3 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
mut: entity work.sram_8bit32
generic map (
SRAM_WR_ASU => 0,
SRAM_WR_Pulse => 1,
SRAM_WR_Hold => 1,
SRAM_RD_ASU => 0,
SRAM_RD_Pulse => 1,
SRAM_RD_Hold => 1 ) -- recovery time (bus turnaround)
port map (
clock => clock,
reset => reset,
req => req,
readwriten => readwriten,
address => address,
rack => rack,
dack => dack,
wdata => wdata,
rdata => rdata,
--
SRAM_A => SRAM_A,
SRAM_OEn => SRAM_OEn,
SRAM_WEn => SRAM_WEn,
SRAM_CSn => SRAM_CSn,
SRAM_D => SRAM_D,
SRAM_BEn => SRAM_BEn );
SRAM_D <= "LLLLLLLHLLLLLLHLLLLLLLHHLLLLLHLL"; -- 01020304
test: process
procedure do_access(a : std_logic_vector; rw : std_logic; d : std_logic_vector) is
begin
req <= '1';
readwriten <= rw;
address <= a;
wdata <= d;
wait until clock='1';
while rack='0' loop
wait until clock='1';
end loop;
req <= '0';
-- while dack='0' loop
-- wait until clock='1';
-- end loop;
end do_access;
begin
wait until reset='0';
wait until clock='1';
do_access(X"01111", '1', X"00");
do_access(X"02233", '1', X"00");
do_access(X"04440", '0', X"55");
do_access(X"04441", '0', X"56");
do_access(X"04442", '0', X"57");
do_access(X"04443", '0', X"58");
do_access(X"05678", '0', X"12");
do_access(X"09999", '1', X"00");
wait;
end process;
end tb;
| gpl-3.0 | 10e53bfed65f7eb42445af6ac6a46d7a | 0.521672 | 2.936364 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/Debouncer.vhd | 1 | 2,160 | LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
use IEEE.numeric_std.all; -- for integer to bit_vector conversion
ENTITY debouncer IS
PORT (
Clk : IN STD_LOGIC;
SW : IN STD_LOGIC; -- sw input
Vsync : in std_logic;
SWout : OUT STD_LOGIC;
Aclr : out std_logic
);
END debouncer;
ARCHITECTURE clean_pulse OF debouncer IS
signal cnt : natural range 0 to 6;
signal cnt1 : natural range 0 to 6; -- makes switch momentary action for about 2 seconds
signal reset : std_logic:='0';
signal reset1 : std_logic:='0';
signal q: std_logic;
signal qout: std_logic;
signal carry: std_logic;
signal carry1: std_logic :='1'; -- ovflo from count1 for monostable action on switch input
signal clr3: std_logic;
signal SWbar: std_logic;
component dff port(d,clk,clrn,prn:in std_logic; q:out std_logic);end component;
BEGIN
u1: reset <= SWbar xnor q;
u2: dff port map(SWbar,carry,'1','1',q);
u3: dff port map('1',reset1,clr3,'1',qout);
SWbar <= not SW;
Swout <= qout; -- was not q;
reset1 <= not q; -- enable 2nd counter
clr3<= carry1 ; -- assume Trained pulse is always longer than a FRAME period*******
---------------------------------------------------------------
CLOCK: PROCESS (Clk, reset)
BEGIN
if reset = '1' then
cnt <= 0;
elsif (clk'EVENT and Clk = '1') then
cnt <= cnt + 1;
end if;
end process CLOCK;
---------------------------------------------------------------
AclrPULSE: process (cnt,q)
begin
if (cnt = 1) and (q='1') then
Aclr <= '1';
else
Aclr <='0';
end if;
end process AclrPULSE;
---------------------------------------------------------------
carryPULSE: process (cnt)
begin
if (cnt = 3) then
carry <= '1';
else
carry <='0';
end if;
end process carryPULSE;
---------------------------------------------------------------
CLOCK1: PROCESS (Clk, reset1)
BEGIN
if (reset1='0') then
cnt1 <= 0;
elsif (clk'EVENT and Clk = '1') then
cnt1 <= cnt1 + 1;
if cnt1 = 4 then
carry1 <='0';
else
carry1 <='1';
end if;
end if;
end process CLOCK1;
---------------------------------------------------------------
END clean_pulse; | gpl-2.0 | 6e828b458ef9425eec0055744255ee66 | 0.536574 | 3.396226 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op974_1.vhdl | 1 | 4,110 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net3,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_3,
scope => Wprivate
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net4
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net4,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | a865e7deb6d001a60caf8940f43961dc | 0.585888 | 3.256735 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/sid_filter.vhd | 4 | 13,333 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity sid_filter is
generic (
g_divider : natural := 221 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req := c_io_req_init;
io_resp : out t_io_resp;
filt_co : in unsigned(10 downto 0);
filt_res : in unsigned(3 downto 0);
valid_in : in std_logic := '0';
error_out : out std_logic;
input : in signed(17 downto 0);
high_pass : out signed(17 downto 0);
band_pass : out signed(17 downto 0);
low_pass : out signed(17 downto 0);
valid_out : out std_logic );
end sid_filter;
architecture dsvf of sid_filter is
signal filter_q : signed(17 downto 0);
signal filter_f : signed(17 downto 0);
signal input_sc : signed(17 downto 0);
signal filt_ram : std_logic_vector(15 downto 0);
signal xa : signed(17 downto 0);
signal xb : signed(17 downto 0);
signal sum_b : signed(17 downto 0);
signal sub_a : signed(17 downto 0);
signal sub_b : signed(17 downto 0);
signal x_reg : signed(17 downto 0) := (others => '0');
signal bp_reg : signed(17 downto 0);
signal hp_reg : signed(17 downto 0);
signal lp_reg : signed(17 downto 0);
signal temp_reg : signed(17 downto 0);
signal error : std_logic := '0';
signal divider : integer range 0 to g_divider-1;
signal instruction : std_logic_vector(7 downto 0);
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
constant c_program : t_byte_array := (X"80", X"12", X"81", X"4C", X"82", X"20");
alias xa_select : std_logic is instruction(0);
alias xb_select : std_logic is instruction(1);
alias sub_a_sel : std_logic is instruction(2);
alias sub_b_sel : std_logic is instruction(3);
alias sum_to_lp : std_logic is instruction(4);
alias sum_to_bp : std_logic is instruction(5);
alias sub_to_hp : std_logic is instruction(6);
alias mult_enable : std_logic is instruction(7);
begin
-- Derive the actual 'f' and 'q' parameters
i_q_table: entity work.Q_table
port map (
Q_reg => filt_res,
filter_q => filter_q ); -- 2.16 format
-- I prefer to infer ram than to instantiate a vendor specific
-- block, but this is the fastest, as the sizes of the ports differ.
-- Secondly, a nice init value can be given, for as long as we don't connect
-- the IO bus.
i_filt_coef: RAMB16_S9_S18
generic map (
INIT_00 => X"0329032803280327032703260326032503240324032303230322032203210320",
INIT_01 => X"03320332033103300330032f032f032e032e032d032c032c032b032b032a032a",
INIT_02 => X"033b033b033a033a033903380338033703370336033603350334033403330333",
INIT_03 => X"034403440343034303420341034103400340033f033f033e033e033d033c033c",
INIT_04 => X"035603550354035303510350034f034e034d034c034b03490348034703460345",
INIT_05 => X"03680367036603650364036203610360035f035e035d035c035b035903580357",
INIT_06 => X"037a037903780377037603750374037203710370036f036e036d036c036a0369",
INIT_07 => X"038d038b038a038903880387038603850383038203810380037f037e037d037c",
INIT_08 => X"03b803b603b303b003ad03aa03a703a403a2039f039c0399039603930391038e",
INIT_09 => X"03e603e303e003dd03db03d803d503d203cf03cc03c903c703c403c103be03bb",
INIT_0A => X"04130411040e040b04080405040203ff03fd03fa03f703f403f103ee03ec03e9",
INIT_0B => X"0441043e043b0438043604330430042d042a042704240422041f041c04190416",
INIT_0C => X"04aa04a3049d0496048f04880481047a0474046d0466045f04580451044b0444",
INIT_0D => X"05170511050a050304fc04f504ee04e804e104da04d304cc04c504bf04b804b1",
INIT_0E => X"0585057e0577057005690562055c0555054e05470540053a0533052c0525051e",
INIT_0F => X"05f205eb05e405dd05d705d005c905c205bb05b405ae05a705a005990592058b",
INIT_10 => X"072c0717070306ee06da06c506b1069d06880674065f064b06360622060d05f9",
INIT_11 => X"0874085f084b08360822080d07f907e407d007bb07a70792077e076907550740",
INIT_12 => X"09bb09a70992097e096909550940092c0917090308ee08da08c508b1089c0888",
INIT_13 => X"0b030aee0ada0ac50ab10a9c0a880a740a5f0a4b0a360a220a0d09f909e409d0",
INIT_14 => X"0dd30da40d760d470d190cea0cbb0c8d0c5e0c2f0c010bd20ba30b750b460b17",
INIT_15 => X"10bd108f1060103210030fd40fa60f770f480f1a0eeb0ebc0e8e0e5f0e300e02",
INIT_16 => X"13a81379134b131c12ed12bf129012611233120411d511a711781149111b10ec",
INIT_17 => X"169216641635160615d815a9157a154c151d14ee14c0149114621434140513d7",
INIT_18 => X"1b6c1b1c1acc1a7d1a2d19dd198e193e18ee189f184f17ff17b01760171116c1",
INIT_19 => X"206620161fc71f771f271ed81e881e381de91d991d491cfa1caa1c5a1c0b1bbb",
INIT_1A => X"26b5264f25e92582251c24b5244f23e92382231c22b5224f21e92182211c20b5",
INIT_1B => X"2d1c2cb52c4f2be92b822b1c2ab52a4f29e92982291c28b5284f27e92782271c",
INIT_1C => X"34d8345a33dd336032e3326631e9316b30ee30712ff42f772efa2e7d2dff2d82",
INIT_1D => X"3caa3c2d3bb03b333ab53a3839bb393e38c1384437c7374936cc364f35d23555",
INIT_1E => X"467d45dd453e449f43ff436042c14222418240e340443fa43f053e663dc63d27",
INIT_1F => X"54b95381524851104fff4eee4ddd4ccc4c164b604aaa49f4493e488847d2471c",
INIT_20 => X"4ac84a3149994901486a47d2473a46a2460b457344db4444438e42d84222416b",
INIT_21 => X"54b55416537752d85238519950fa505a4fbb4f1c4e7d4ddd4d3e4c9f4bff4b60",
INIT_22 => X"5d555ccc5c445bbb5b335aaa5a2159995910588857ff577756ee566655dd5555",
INIT_23 => X"65dd655564cc644463bb633362aa62216199611060885fff5f775eee5e665ddd",
INIT_24 => X"6e106d8e6d0b6c886c056b826aff6a7c69fa697768f4687167ee676b66e96666",
INIT_25 => X"763e75bb753874b5743273b0732d72aa722771a47121709f701c6f996f166e93",
INIT_26 => X"7e6b7de87d667ce37c607bdd7b5a7ad77a5579d2794f78cc784977c6774476c1",
INIT_27 => X"8699861685938510848d840b83888305828281ff817c80fa80777ff47f717eee",
INIT_28 => X"8f718ee38e558dc68d388caa8c1c8b8d8aff8a7189e3895588c6883887aa871c",
INIT_29 => X"985597c6973896aa961c958d94ff947193e3935592c6923891aa911c908d8fff",
INIT_2A => X"a138a0aaa01c9f8d9eff9e719de39d559cc69c389baa9b1c9a8d99ff997198e3",
INIT_2B => X"aa1ca98da8ffa871a7e3a755a6c6a638a5aaa51ca48da3ffa371a2e3a255a1c6",
INIT_2C => X"b2ffb271b1e3b154b0c6b038afaaaf1cae8dadffad71ace3ac54abc6ab38aaaa",
INIT_2D => X"bbe3bb54bac6ba38b9aab91cb88db7ffb771b6e3b654b5c6b538b4aab41cb38d",
INIT_2E => X"c4c6c438c3aac31cc28dc1ffc171c0e3c054bfc6bf38beaabe1cbd8dbcffbc71",
INIT_2F => X"cdaacd1ccc8dcbffcb71cae3ca54c9c6c938c8aac81cc78dc6ffc671c5e3c554",
INIT_30 => X"d338d2e3d28dd238d1e3d18dd138d0e3d08dd038cfe3cf8dcf38cee3ce8dce38",
INIT_31 => X"d88dd838d7e3d78dd738d6e3d68dd638d5e3d58dd538d4e3d48dd438d3e3d38d",
INIT_32 => X"dde3dd8ddd38dce3dc8ddc38dbe3db8ddb38dae3da8dda38d9e3d98dd938d8e3",
INIT_33 => X"e338e2e3e28de238e1e3e18de138e0e3e08de038dfe3df8ddf38dee3de8dde38",
INIT_34 => X"e738e6f9e6bbe67ce63ee5ffe5c0e582e543e505e4c6e488e449e40ae3cce38d",
INIT_35 => X"eb21eae3eaa4ea65ea27e9e8e9aae96be92de8eee8afe871e832e7f4e7b5e777",
INIT_36 => X"ef0aeeccee8dee4fee10edd2ed93ed54ed16ecd7ec99ec5aec1bebddeb9eeb60",
INIT_37 => X"f2f4f2b5f276f238f1f9f1bbf17cf13ef0fff0c0f082f043f005efc6ef88ef49",
INIT_38 => X"f532f510f4eef4ccf4aaf488f465f443f421f3fff3ddf3bbf399f376f354f332",
INIT_39 => X"f754f732f710f6eef6ccf6aaf688f665f643f621f5fff5ddf5bbf599f576f554",
INIT_3A => X"f976f954f932f910f8eef8ccf8aaf888f865f843f821f7fff7ddf7bbf799f776",
INIT_3B => X"fb99fb76fb54fb32fb10faeefaccfaaafa88fa65fa43fa21f9fff9ddf9bbf999",
INIT_3C => X"fcbdfcacfc9afc89fc78fc67fc56fc44fc33fc22fc11fc00fbeefbddfbccfbbb",
INIT_3D => X"fdd0fdbffdaefd9cfd8bfd7afd69fd58fd46fd35fd24fd13fd02fcf0fcdffcce",
INIT_3E => X"fee3fed2fec1feb0fe9efe8dfe7cfe6bfe5afe48fe37fe26fe15fe04fdf2fde1",
INIT_3F => X"fff6ffe5ffd4ffc3ffb2ffa0ff8fff7eff6dff5cff4aff39ff28ff17ff06fef4" )
port map (
DOA => open,
DOPA => open,
ADDRA => std_logic_vector(io_req.address(10 downto 0)),
CLKA => clock,
DIA => io_req.data,
DIPA => "0",
ENA => io_req.write,
SSRA => '0',
WEA => io_req.write,
DOB => filt_ram,
DOPB => open,
ADDRB => std_logic_vector(filt_co(10 downto 1)),
CLKB => clock,
DIB => X"0000",
DIPB => "00",
ENB => '1',
SSRB => '0',
WEB => '0' );
process(clock)
variable filt_f : signed(17 downto 3);
begin
if rising_edge(clock) then
filter_f <= "00" & signed(filt_ram(15 downto 0));
io_resp <= c_io_resp_init;
io_resp.ack <= io_req.read or io_req.write;
end if;
end process;
-- process(clock)
-- variable filt_f : signed(17 downto 3);
-- begin
-- if rising_edge(clock) then
-- filt_f := "000" & signed(filt_co) & "0";
-- filter_f <= '0' & (filt_f + 2) & "00";
-- end if;
-- end process;
--input_sc <= input;
input_sc <= shift_right(input, 1);
-- operations to execute the filter:
-- bp_f = f * bp_reg
-- q_contrib = q * bp_reg
-- lp = bp_f + lp_reg
-- temp = input - lp
-- hp = temp - q_contrib
-- hp_f = f * hp
-- bp = hp_f + bp_reg
-- bp_reg = bp
-- lp_reg = lp
-- x_reg = f * bp_reg -- 10000000 -- 80
-- lp_reg = x_reg + lp_reg -- 00010010 -- 12
-- q_contrib = q * bp_reg -- 10000001 -- 81
-- temp = input - lp -- 00000000 -- 00 (can be merged with previous!)
-- hp_reg = temp - q_contrib -- 01001100 -- 4C
-- x_reg = f * hp_reg -- 10000010 -- 82
-- bp_reg = x_reg + bp_reg -- 00100000 -- 20
-- now perform the arithmetic
xa <= filter_f when xa_select='0' else filter_q;
xb <= bp_reg when xb_select='0' else hp_reg;
sum_b <= bp_reg when xb_select='0' else lp_reg;
sub_a <= input_sc when sub_a_sel='0' else temp_reg;
sub_b <= lp_reg when sub_b_sel='0' else x_reg;
process(clock)
variable x_result : signed(35 downto 0);
variable sum_result : signed(17 downto 0);
variable sub_result : signed(17 downto 0);
begin
if rising_edge(clock) then
x_result := xa * xb;
if mult_enable='1' then
x_reg <= x_result(33 downto 16);
if (x_result(35 downto 33) /= "000") and (x_result(35 downto 33) /= "111") then
error <= not error;
end if;
end if;
sum_result := sum_limit(x_reg, sum_b);
temp_reg <= sum_result;
if sum_to_lp='1' then
lp_reg <= sum_result;
end if;
if sum_to_bp='1' then
bp_reg <= sum_result;
end if;
sub_result := sub_limit(sub_a, sub_b);
temp_reg <= sub_result;
if sub_to_hp='1' then
hp_reg <= sub_result;
end if;
-- control part
instruction <= (others => '0');
if reset='1' then
hp_reg <= (others => '0');
lp_reg <= (others => '0');
bp_reg <= (others => '0');
divider <= 0;
elsif divider = g_divider-1 then
divider <= 0;
else
divider <= divider + 1;
if divider < c_program'length then
instruction <= c_program(divider);
end if;
end if;
if divider = c_program'length then
valid_out <= '1';
else
valid_out <= '0';
end if;
end if;
end process;
high_pass <= hp_reg;
band_pass <= bp_reg;
low_pass <= lp_reg;
error_out <= error;
end dsvf;
| gpl-3.0 | 60abbd301db0a2fad03dc1881f193018 | 0.61014 | 2.863617 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/vram/example_design/vram_exdes.vhd | 1 | 5,367 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: vram_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY vram_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END vram_exdes;
ARCHITECTURE xilinx OF vram_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT vram IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : vram
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| mit | 5f4a1271c1288ddbfc489eeeb370a5bc | 0.549096 | 4.587179 | false | false | false | false |
KB777/1541UltimateII | fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate_logic_32.vhd | 1 | 39,453 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity ultimate_logic_32 is
generic (
g_version : unsigned(7 downto 0) := X"FF";
g_simulation : boolean := true;
g_clock_freq : natural := 50_000_000;
g_baud_rate : natural := 115_200;
g_timer_rate : natural := 200_000;
g_fpga_type : natural := 0;
g_boot_rom : boolean := false;
g_video_overlay : boolean := false;
g_icap : boolean := false;
g_uart : boolean := false;
g_drive_1541 : boolean := false;
g_drive_1541_2 : boolean := false;
g_hardware_gcr : boolean := false;
g_cartridge : boolean := false;
g_command_intf : boolean := false;
g_stereo_sid : boolean := false;
g_ram_expansion : boolean := false;
g_extended_reu : boolean := false;
g_hardware_iec : boolean := false;
g_iec_prog_tim : boolean := false;
g_c2n_streamer : boolean := false;
g_c2n_recorder : boolean := false;
g_drive_sound : boolean := false;
g_rtc_chip : boolean := false;
g_rtc_timer : boolean := false;
g_usb_host : boolean := false;
g_usb_host2 : boolean := false;
g_spi_flash : boolean := false;
g_vic_copper : boolean := false;
g_sampler : boolean := false;
g_profiler : boolean := false;
g_analyzer : boolean := false );
port (
-- globals
sys_clock : in std_logic;
sys_reset : in std_logic;
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- slot side
PHI2 : in std_logic;
DOTCLK : in std_logic;
RSTn : inout std_logic := '1';
BUFFER_ENn : out std_logic := '1';
SLOT_ADDR : inout std_logic_vector(15 downto 0);
SLOT_DATA : inout std_logic_vector(7 downto 0);
RWn : inout std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : inout std_logic;
GAMEn : inout std_logic;
ROMHn : in std_logic;
ROMLn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
IRQn : inout std_logic;
NMIn : inout std_logic;
-- local bus side
mem_inhibit : out std_logic;
mem_req : out t_mem_req_32;
mem_resp : in t_mem_resp_32;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
-- actual levels of the pins --
iec_reset_i : in std_logic;
iec_atn_i : in std_logic;
iec_data_i : in std_logic;
iec_clock_i : in std_logic;
iec_srq_i : in std_logic;
iec_reset_o : out std_logic := '1';
iec_atn_o : out std_logic;
iec_data_o : out std_logic;
iec_clock_o : out std_logic;
iec_srq_o : out std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1) := "ZZ";
-- LED interface
LED_CLK : out std_logic;
LED_DATA : out std_logic;
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0) := "ZZZZZZZZ";
-- Cassette Interface
CAS_MOTOR : in std_logic := '0';
CAS_SENSE : inout std_logic := 'Z';
CAS_READ : inout std_logic := 'Z';
CAS_WRITE : inout std_logic := 'Z';
-- Interface to other graphical output (Full HD of course and in 3D!) ;-)
vid_clock : in std_logic := '0';
vid_reset : in std_logic := '0';
vid_h_count : in unsigned(11 downto 0) := (others => '0');
vid_v_count : in unsigned(11 downto 0) := (others => '0');
vid_active : out std_logic;
vid_opaque : out std_logic;
vid_data : out unsigned(3 downto 0);
overlay_on : out std_logic;
keyb_row : in std_logic_vector(7 downto 0) := (others => '0');
keyb_col : inout std_logic_vector(7 downto 0) := (others => '0');
-- Buttons
button : in std_logic_vector(2 downto 0);
-- Simulation port
sim_io_req : in t_io_req := c_io_req_init;
sim_io_resp : out t_io_resp );
end ultimate_logic_32;
architecture logic of ultimate_logic_32 is
function to_std(b : boolean) return std_logic is
begin
if b then
return '1';
end if;
return '0';
end function;
impure function create_capabilities return std_logic_vector is
variable cap : std_logic_vector(31 downto 0) := (others => '0');
begin
cap(00) := to_std(g_uart);
cap(01) := to_std(g_drive_1541);
cap(02) := to_std(g_drive_1541_2);
cap(03) := to_std(g_drive_sound);
cap(04) := to_std(g_hardware_gcr);
cap(05) := to_std(g_hardware_iec);
cap(06) := to_std(g_iec_prog_tim);
cap(07) := to_std(g_c2n_streamer);
cap(08) := to_std(g_c2n_recorder);
cap(09) := to_std(g_cartridge);
cap(10) := to_std(g_ram_expansion);
cap(11) := to_std(g_usb_host);
cap(12) := to_std(g_rtc_chip);
cap(13) := to_std(g_rtc_timer);
cap(14) := to_std(g_spi_flash);
cap(15) := to_std(g_icap);
cap(16) := to_std(g_extended_reu);
cap(17) := to_std(g_stereo_sid);
cap(18) := to_std(g_command_intf);
cap(19) := to_std(g_vic_copper);
cap(20) := to_std(g_video_overlay);
cap(21) := to_std(g_sampler);
cap(22) := to_std(g_analyzer) or to_std(g_profiler);
cap(23) := to_std(g_usb_host2);
cap(29 downto 28) := std_logic_vector(to_unsigned(g_fpga_type, 2));
cap(30) := to_std(g_boot_rom);
cap(31) := to_std(g_simulation);
return cap;
end function;
constant c_capabilities : std_logic_vector(31 downto 0) := create_capabilities;
constant c_tag_1541_cpu_1 : std_logic_vector(7 downto 0) := X"01";
constant c_tag_1541_floppy_1 : std_logic_vector(7 downto 0) := X"02";
constant c_tag_1541_audio_1 : std_logic_vector(7 downto 0) := X"03";
constant c_tag_1541_cpu_2 : std_logic_vector(7 downto 0) := X"04";
constant c_tag_1541_floppy_2 : std_logic_vector(7 downto 0) := X"05";
constant c_tag_1541_audio_2 : std_logic_vector(7 downto 0) := X"06";
constant c_tag_slot : std_logic_vector(7 downto 0) := X"07";
constant c_tag_reu : std_logic_vector(7 downto 0) := X"08";
constant c_tag_usb2 : std_logic_vector(7 downto 0) := X"09";
constant c_tag_cpu_i : std_logic_vector(7 downto 0) := X"0A";
constant c_tag_cpu_d : std_logic_vector(7 downto 0) := X"0B";
-- Memory interface
signal mem_req_32_cpu : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_cpu : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req_1541 : t_mem_req := c_mem_req_init;
signal mem_resp_1541 : t_mem_resp := c_mem_resp_init;
signal mem_req_1541_2 : t_mem_req := c_mem_req_init;
signal mem_resp_1541_2 : t_mem_resp := c_mem_resp_init;
signal mem_req_cart : t_mem_req := c_mem_req_init;
signal mem_resp_cart : t_mem_resp := c_mem_resp_init;
signal mem_req_debug : t_mem_req := c_mem_req_init;
signal mem_resp_debug : t_mem_resp := c_mem_resp_init;
-- converted to 32 bits
signal mem_req_32_1541 : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_1541 : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req_32_1541_2 : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_1541_2 : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req_32_cart : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_cart : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req_32_debug : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_debug : t_mem_resp_32 := c_mem_resp_32_init;
signal mem_req_32_usb : t_mem_req_32 := c_mem_req_32_init;
signal mem_resp_32_usb : t_mem_resp_32 := c_mem_resp_32_init;
-- IO Bus
signal cpu_io_req : t_io_req;
signal cpu_io_resp : t_io_resp := c_io_resp_init;
signal io_req : t_io_req;
signal io_resp : t_io_resp := c_io_resp_init;
signal io_req_1541 : t_io_req;
signal io_resp_1541 : t_io_resp := c_io_resp_init;
signal io_req_1541_1 : t_io_req;
signal io_resp_1541_1 : t_io_resp := c_io_resp_init;
signal io_req_1541_2 : t_io_req;
signal io_resp_1541_2 : t_io_resp := c_io_resp_init;
signal io_req_itu : t_io_req;
signal io_resp_itu : t_io_resp := c_io_resp_init;
signal io_req_cart : t_io_req;
signal io_resp_cart : t_io_resp := c_io_resp_init;
signal io_req_io : t_io_req;
signal io_resp_io : t_io_resp := c_io_resp_init;
signal io_req_big_io : t_io_req;
signal io_resp_big_io : t_io_resp := c_io_resp_init;
signal io_req_sd : t_io_req;
signal io_resp_sd : t_io_resp := c_io_resp_init;
signal io_req_rtc : t_io_req;
signal io_resp_rtc : t_io_resp := c_io_resp_init;
signal io_req_rtc_tmr : t_io_req;
signal io_resp_rtc_tmr : t_io_resp := c_io_resp_init;
signal io_req_gcr_dec : t_io_req;
signal io_resp_gcr_dec : t_io_resp := c_io_resp_init;
signal io_req_flash : t_io_req;
signal io_resp_flash : t_io_resp := c_io_resp_init;
signal io_req_iec : t_io_req;
signal io_resp_iec : t_io_resp := c_io_resp_init;
signal io_req_usb : t_io_req;
signal io_resp_usb : t_io_resp := c_io_resp_init;
signal io_req_c2n : t_io_req;
signal io_resp_c2n : t_io_resp := c_io_resp_init;
signal io_req_c2n_rec : t_io_req;
signal io_resp_c2n_rec : t_io_resp := c_io_resp_init;
signal io_req_icap : t_io_req;
signal io_resp_icap : t_io_resp := c_io_resp_init;
signal io_req_aud_sel : t_io_req;
signal io_resp_aud_sel : t_io_resp := c_io_resp_init;
signal io_req_debug : t_io_req;
signal io_resp_debug : t_io_resp := c_io_resp_init;
signal io_req_led : t_io_req;
signal io_resp_led : t_io_resp := c_io_resp_init;
signal io_irq : std_logic;
-- Audio routing
signal pwm : std_logic;
signal pwm_2 : std_logic := '0';
signal drive_sample : signed(12 downto 0);
signal drive_sample_2 : signed(12 downto 0);
-- IEC signal routing
signal atn_o, atn_i : std_logic := '1';
signal clk_o, clk_i : std_logic := '1';
signal data_o, data_i : std_logic := '1';
signal srq_i : std_logic := '1';
signal atn_o_2 : std_logic := '1';
signal clk_o_2 : std_logic := '1';
signal data_o_2 : std_logic := '1';
signal hw_atn_o : std_logic := '1';
signal hw_clk_o : std_logic := '1';
signal hw_data_o : std_logic := '1';
signal hw_srq_o : std_logic := '1';
-- miscellaneous interconnect
signal c64_irq_n : std_logic;
signal c64_irq : std_logic;
signal phi2_tick : std_logic;
signal c64_stopped : std_logic;
signal c2n_sense : std_logic := '0';
signal c2n_sense_in : std_logic := '0';
signal c2n_out_r : std_logic := '1';
signal c2n_out_w : std_logic := '1';
signal busy_led : std_logic;
signal sd_busy : std_logic;
signal sd_act_stretched : std_logic;
signal error : std_logic;
signal act_led_n : std_logic := '1';
signal motor_led_n : std_logic := '1';
signal cart_led_n : std_logic := '1';
signal c2n_pull_sense : std_logic := '0';
signal freezer_state : std_logic_vector(1 downto 0);
signal dirty_led_1_n : std_logic := '1';
signal dirty_led_2_n : std_logic := '1';
signal sid_pwm_left : std_logic;
signal sid_pwm_right : std_logic;
signal samp_pwm_left : std_logic;
signal samp_pwm_right : std_logic;
signal trigger_1 : std_logic;
signal trigger_2 : std_logic;
signal sys_irq_usb : std_logic := '0';
signal sys_irq_tape : std_logic := '0';
signal sys_irq_iec : std_logic := '0';
signal sys_irq_cmdif : std_logic := '0';
signal invalidate : std_logic;
signal inv_addr : std_logic_vector(31 downto 0);
signal stuck : std_logic;
signal misc_io : std_logic_vector(7 downto 0);
signal profiler_irq_flags : std_logic_vector(7 downto 0);
begin
i_cpu: entity work.mblite_wrapper
generic map (
g_tag_i => c_tag_cpu_i,
g_tag_d => c_tag_cpu_d )
port map (
clock => sys_clock,
reset => sys_reset,
irq_i => io_irq,
invalidate => invalidate,
inv_addr => inv_addr,
-- memory interface
mem_req => mem_req_32_cpu,
mem_resp => mem_resp_32_cpu,
io_req => cpu_io_req,
io_resp => cpu_io_resp );
invalidate <= misc_io(0) when (mem_resp_32_usb.rack_tag(5 downto 0) = c_tag_usb2(5 downto 0)) and (mem_req_32_usb.read_writen = '0') else '0';
inv_addr(31 downto 26) <= (others => '0');
inv_addr(25 downto 0) <= std_logic_vector(mem_req_32_usb.address);
i_io_arb: entity work.io_bus_arbiter_pri
generic map (
g_ports => 2 )
port map (
clock => sys_clock,
reset => sys_reset,
reqs(0) => sim_io_req,
reqs(1) => cpu_io_req,
resps(0) => sim_io_resp,
resps(1) => cpu_io_resp,
req => io_req,
resp => io_resp );
i_itu: entity work.itu
generic map (
g_version => g_version,
g_capabilities => c_capabilities,
g_uart => g_uart,
g_frequency => g_clock_freq,
g_edge_init => "00000101",
g_edge_write => false,
g_baudrate => g_baud_rate,
g_timer_rate => g_timer_rate)
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_itu,
io_resp => io_resp_itu,
irq_in(7) => button(2),
irq_in(6) => button(1),
irq_in(5) => button(0),
irq_in(4) => sys_irq_cmdif,
irq_in(3) => sys_irq_tape,
irq_in(2) => sys_irq_usb,
irq_out => io_irq,
irq_flags => profiler_irq_flags,
busy_led => busy_led,
misc_io => misc_io,
uart_txd => UART_TXD,
uart_rxd => UART_RXD );
r_drive: if g_drive_1541 generate
begin
i_drive: entity work.c1541_drive
generic map (
g_cpu_tag => c_tag_1541_cpu_1,
g_floppy_tag => c_tag_1541_floppy_1,
g_audio_tag => c_tag_1541_audio_1,
g_audio => g_drive_sound,
g_audio_div => (g_clock_freq / 22500),
g_audio_base => X"0EC0000",
g_ram_base => X"0EE0000" )
port map (
clock => sys_clock,
reset => sys_reset,
drive_stop => c64_stopped,
-- slave port on io bus
io_req => io_req_1541_1,
io_resp => io_resp_1541_1,
-- master port on memory bus
mem_req => mem_req_1541,
mem_resp => mem_resp_1541,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
iec_reset_n => iec_reset_i,
c64_reset_n => RSTn,
-- LED
act_led_n => act_led_n,
motor_led_n => motor_led_n,
dirty_led_n => dirty_led_1_n,
-- audio out
audio_sample => drive_sample );
r_pwm: if g_drive_sound generate
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 2,
g_width => drive_sample'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => drive_sample,
dac_out => pwm );
end generate;
end generate;
r_drive_2: if g_drive_1541_2 generate
begin
i_drive: entity work.c1541_drive
generic map (
g_cpu_tag => c_tag_1541_cpu_2,
g_floppy_tag => c_tag_1541_floppy_2,
g_audio_tag => c_tag_1541_audio_2,
g_audio => g_drive_sound,
g_audio_div => (g_clock_freq / 22500),
g_audio_base => X"0EC0000",
g_ram_base => X"0ED0000" )
port map (
clock => sys_clock,
reset => sys_reset,
drive_stop => c64_stopped,
-- slave port on io bus
io_req => io_req_1541_2,
io_resp => io_resp_1541_2,
-- master port on memory bus
mem_req => mem_req_1541_2,
mem_resp => mem_resp_1541_2,
-- serial bus pins
atn_o => atn_o_2, -- open drain
atn_i => atn_i,
clk_o => clk_o_2, -- open drain
clk_i => clk_i,
data_o => data_o_2, -- open drain
data_i => data_i,
iec_reset_n => iec_reset_i,
c64_reset_n => RSTn,
-- LED
act_led_n => open, --DISK_ACTn,
motor_led_n => open, --MOTOR_LEDn,
dirty_led_n => dirty_led_2_n,
-- audio out
audio_sample => drive_sample_2 );
r_pwm: if g_drive_sound generate
i_pwm0: entity work.sigma_delta_dac --delta_sigma_2to5
generic map (
g_left_shift => 2,
g_width => drive_sample_2'length )
port map (
clock => sys_clock,
reset => sys_reset,
dac_in => drive_sample_2,
dac_out => pwm_2 );
end generate;
end generate;
r_cart: if g_cartridge generate
i_slot_srv: entity work.slot_server_v4
generic map (
g_tag_slot => c_tag_slot,
g_tag_reu => c_tag_reu,
g_ram_base_reu => X"1000000", -- should be on 16M boundary, or should be limited in size
g_rom_base_cart => X"0F00000", -- should be on a 1M boundary
g_ram_base_cart => X"0EF0000", -- should be on a 64K boundary
g_control_read => true,
g_ram_expansion => g_ram_expansion,
g_extended_reu => g_extended_reu,
g_command_intf => g_command_intf,
g_sampler => g_sampler,
g_implement_sid => g_stereo_sid,
g_sid_voices => 16,
g_vic_copper => g_vic_copper )
port map (
clock => sys_clock,
reset => sys_reset,
-- Cartridge pins
RSTn => RSTn,
IRQn => IRQn,
NMIn => NMIn,
PHI2 => PHI2,
IO1n => IO1n,
IO2n => IO2n,
DMAn => DMAn,
BA => BA,
ROMLn => ROMLn,
ROMHn => ROMHn,
GAMEn => GAMEn,
EXROMn => EXROMn,
RWn => RWn,
ADDRESS => SLOT_ADDR,
DATA => SLOT_DATA,
-- other hardware pins
BUFFER_ENn => BUFFER_ENn,
buttons => BUTTON,
cart_led_n => cart_led_n,
-- audio
sid_pwm_left => sid_pwm_left,
sid_pwm_right => sid_pwm_right,
samp_pwm_left => samp_pwm_left,
samp_pwm_right => samp_pwm_right,
-- debug
freezer_state => freezer_state,
trigger_1 => trigger_1,
trigger_2 => trigger_2,
-- timing output
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
-- master on memory bus
memctrl_inhibit => mem_inhibit,
mem_req => mem_req_cart,
mem_resp => mem_resp_cart,
-- slave on io bus
io_req => io_req_cart,
io_resp => io_resp_cart,
io_irq_cmd => sys_irq_cmdif );
end generate;
i_split1: entity work.io_bus_splitter
generic map (
g_range_lo => 17,
g_range_hi => 19,
g_ports => 8 )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp,
reqs(0) => io_req_itu, -- 4000000 ( 16 ... 400000F)
reqs(1) => io_req_1541, -- 4020000 ( 8K... 4021FFF) & 4024000 for drive B
reqs(2) => io_req_cart, -- 4040000 (128K... 405FFFF)
reqs(3) => io_req_io, -- 4060000 ( 2K... 4060FFF)
reqs(4) => io_req_usb, -- 4080000 ( 8K... 4081FFF)
reqs(5) => io_req_c2n, -- 40A0000 ( 4K... 40A0FFF)
reqs(6) => io_req_c2n_rec, -- 40C0000 ( 4K... 40C0FFF)
reqs(7) => io_req_big_io, -- 40E0000 (128K... 40FFFFF)
resps(0) => io_resp_itu,
resps(1) => io_resp_1541,
resps(2) => io_resp_cart,
resps(3) => io_resp_io,
resps(4) => io_resp_usb,
resps(5) => io_resp_c2n,
resps(6) => io_resp_c2n_rec,
resps(7) => io_resp_big_io );
i_split2: entity work.io_bus_splitter
generic map (
g_range_lo => 14,
g_range_hi => 15,
g_ports => 4 )
port map (
clock => sys_clock,
req => io_req_1541,
resp => io_resp_1541,
reqs(0) => io_req_1541_1, -- 4020000
reqs(1) => io_req_1541_2, -- 4024000
reqs(2) => io_req_iec, -- 4028000
reqs(3) => io_req_led, -- 402C000
resps(0) => io_resp_1541_1,
resps(1) => io_resp_1541_2,
resps(2) => io_resp_iec,
resps(3) => io_resp_led );
i_split3: entity work.io_bus_splitter
generic map (
g_range_lo => 8,
g_range_hi => 11,
g_ports => 8 )
port map (
clock => sys_clock,
req => io_req_io,
resp => io_resp_io,
reqs(0) => io_req_sd, -- 4060000
reqs(1) => io_req_rtc, -- 4060100
reqs(2) => io_req_flash, -- 4060200
reqs(3) => io_req_debug, -- 4060300
reqs(4) => io_req_rtc_tmr, -- 4060400
reqs(5) => io_req_gcr_dec, -- 4060500
reqs(6) => io_req_icap, -- 4060600
reqs(7) => io_req_aud_sel, -- 4060700
resps(0) => io_resp_sd,
resps(1) => io_resp_rtc,
resps(2) => io_resp_flash,
resps(3) => io_resp_debug,
resps(4) => io_resp_rtc_tmr,
resps(5) => io_resp_gcr_dec,
resps(6) => io_resp_icap,
resps(7) => io_resp_aud_sel );
-- r_usb: if g_usb_host generate
-- i_usb: entity work.usb_host_io
-- generic map (
-- g_simulation => g_simulation )
-- port map (
-- ulpi_clock => ULPI_CLOCK,
-- ulpi_reset => ulpi_reset,
--
-- -- ULPI Interface
-- ULPI_DATA => ULPI_DATA,
-- ULPI_DIR => ULPI_DIR,
-- ULPI_NXT => ULPI_NXT,
-- ULPI_STP => ULPI_STP,
--
-- usb_busy => usb_busy, -- LED interface
--
-- -- register interface bus
-- sys_clock => sys_clock,
-- sys_reset => sys_reset,
--
-- sys_io_req => io_req_usb,
-- sys_io_resp => io_resp_usb );
-- end generate;
--
r_usb2: if g_usb_host2 generate
i_usb2: entity work.usb_host_nano
generic map (
g_tag => c_tag_usb2,
g_simulation => g_simulation )
port map (
clock => ULPI_CLOCK,
reset => ulpi_reset,
ulpi_nxt => ulpi_nxt,
ulpi_dir => ulpi_dir,
ulpi_stp => ulpi_stp,
ulpi_data => ulpi_data,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_mem_req => mem_req_32_usb,
sys_mem_resp => mem_resp_32_usb,
sys_io_req => io_req_usb,
sys_io_resp => io_resp_usb,
sys_irq => sys_irq_usb );
end generate;
i_sd: entity work.spi_peripheral_io
generic map (
g_fixed_rate => false,
g_init_rate => 500,
g_crc => true )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_sd,
io_resp => io_resp_sd,
busy => sd_busy,
SD_DETECTn => SD_CARDDETn,
SD_WRPROTn => '1', --SD_WRPROTn,
SPI_SSn => SD_SSn,
SPI_CLK => SD_CLK,
SPI_MOSI => SD_MOSI,
SPI_MISO => SD_MISO );
-- -- playing around
-- i_led: entity work.spi_peripheral_io
-- generic map (
-- g_fixed_rate => true,
-- g_init_rate => 40,
-- g_crc => false )
-- port map (
-- clock => sys_clock,
-- reset => sys_reset,
--
-- io_req => io_req_led,
-- io_resp => io_resp_led,
--
-- busy => open,
--
-- SD_DETECTn => '0',
-- SD_WRPROTn => '1',
-- SPI_SSn => open,
-- SPI_CLK => LED_CLK,
-- SPI_MOSI => LED_DATA,
-- SPI_MISO => '1' );
LED_CLK <= 'Z';
LED_DATA <= 'Z';
i_stretch: entity work.pulse_stretch
generic map ( g_clock_freq / 200) -- 5 ms
port map (
clock => sys_clock,
reset => sys_reset,
pulse_in => sd_busy,
pulse_out => sd_act_stretched );
r_spi_flash: if g_spi_flash generate
i_spi_flash: entity work.spi_peripheral_io
generic map (
g_fixed_rate => true,
g_init_rate => 0,
g_crc => false )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_flash,
io_resp => io_resp_flash,
SD_DETECTn => '0',
SD_WRPROTn => '1',
SPI_SSn => FLASH_CSn,
SPI_CLK => FLASH_SCK,
SPI_MOSI => FLASH_MOSI,
SPI_MISO => FLASH_MISO );
end generate;
r_no_spi_flash: if not g_spi_flash generate
i_flash_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_flash,
io_resp => io_resp_flash );
end generate;
r_rtc: if g_rtc_chip generate
signal spi_ss_n : std_logic;
begin
i_spi_rtc: entity work.spi_peripheral_io
generic map (
g_fixed_rate => true,
g_init_rate => 31,
g_crc => false )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_rtc,
io_resp => io_resp_rtc,
SD_DETECTn => '0',
SD_WRPROTn => '1',
SPI_SSn => spi_ss_n,
SPI_CLK => RTC_SCK,
SPI_MOSI => RTC_MOSI,
SPI_MISO => RTC_MISO );
RTC_CS <= not spi_ss_n;
end generate;
r_no_rtc: if not g_rtc_chip generate
i_rtc_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_rtc,
io_resp => io_resp_rtc );
end generate;
r_rtc_timer: if g_rtc_timer generate
i_rtc_timer: entity work.real_time_clock
generic map (
g_freq => g_clock_freq )
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_rtc_tmr,
resp => io_resp_rtc_tmr );
end generate;
r_no_rtc_timer: if not g_rtc_chip generate
i_rtc_timer_dummy: entity work.io_dummy
port map (
clock => sys_clock,
io_req => io_req_rtc_tmr,
io_resp => io_resp_rtc_tmr );
end generate;
r_gcr_codec: if g_hardware_gcr generate
i_gcr_codec: entity work.gcr_codec
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_gcr_dec,
resp => io_resp_gcr_dec );
end generate;
r_iec: if g_hardware_iec generate
i_iec: entity work.iec_processor_io
port map (
clock => sys_clock,
reset => sys_reset,
srq_i => srq_i,
srq_o => hw_srq_o,
atn_i => atn_i,
atn_o => hw_atn_o,
clk_i => clk_i,
clk_o => hw_clk_o,
data_i => data_i,
data_o => hw_data_o,
irq => sys_irq_iec, -- TODO: is not connected anywhere
req => io_req_iec,
resp => io_resp_iec );
end generate;
r_c2n: if g_c2n_streamer generate
i_c2n: entity work.c2n_playback_io
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_c2n,
resp => io_resp_c2n,
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
c2n_sense => c2n_sense,
c2n_motor => CAS_MOTOR,
c2n_out_r => c2n_out_r,
c2n_out_w => c2n_out_w );
end generate;
r_c2n_rec: if g_c2n_recorder generate
i_c2n: entity work.c2n_record
port map (
clock => sys_clock,
reset => sys_reset,
irq => sys_irq_tape,
req => io_req_c2n_rec,
resp => io_resp_c2n_rec,
c64_stopped => c64_stopped,
phi2_tick => phi2_tick,
pull_sense => c2n_pull_sense,
c2n_sense => c2n_sense_in,
c2n_motor => CAS_MOTOR,
c2n_write => CAS_WRITE,
c2n_read => CAS_READ );
end generate;
r_icap: if g_icap generate
i_icap: entity work.icap
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_icap,
io_resp => io_resp_icap );
end generate;
r_overlay: if g_video_overlay generate
i_overlay: entity work.char_generator_peripheral
generic map (
g_screen_size => 11,
g_color_ram => true )
port map (
clock => sys_clock,
reset => sys_reset,
io_req => io_req_big_io, -- to be split later
io_resp => io_resp_big_io,
keyb_col => keyb_col,
keyb_row => keyb_row,
overlay_on => overlay_on,
pix_clock => vid_clock,
pix_reset => vid_reset,
h_count => vid_h_count,
v_count => vid_v_count,
pixel_active => vid_active,
pixel_opaque => vid_opaque,
pixel_data => vid_data );
end generate;
CAS_SENSE <= '0' when (c2n_sense='1') or (c2n_pull_sense='1') else 'Z';
CAS_READ <= '0' when c2n_out_r='0' else 'Z';
CAS_WRITE <= '0' when c2n_out_w='0' else 'Z';
-- CAS_READ <= trigger_1;
-- CAS_WRITE <= trigger_2;
c2n_sense_in <= '1' when CAS_SENSE='0' else '0';
i_conv32_cart: entity work.mem_to_mem32(route_through)
port map(
clock => sys_clock,
reset => sys_reset,
mem_req_8 => mem_req_cart,
mem_resp_8 => mem_resp_cart,
mem_req_32 => mem_req_32_cart,
mem_resp_32 => mem_resp_32_cart );
i_conv32_1541: entity work.mem_to_mem32(route_through)
port map(
clock => sys_clock,
reset => sys_reset,
mem_req_8 => mem_req_1541,
mem_resp_8 => mem_resp_1541,
mem_req_32 => mem_req_32_1541,
mem_resp_32 => mem_resp_32_1541 );
i_conv32_1541_2: entity work.mem_to_mem32(route_through)
port map(
clock => sys_clock,
reset => sys_reset,
mem_req_8 => mem_req_1541_2,
mem_resp_8 => mem_resp_1541_2,
mem_req_32 => mem_req_32_1541_2,
mem_resp_32 => mem_resp_32_1541_2 );
i_mem_arb: entity work.mem_bus_arbiter_pri_32
generic map (
g_ports => 6,
g_registered => false )
port map (
clock => sys_clock,
reset => sys_reset,
reqs(0) => mem_req_32_cart,
reqs(1) => mem_req_32_1541,
reqs(2) => mem_req_32_1541_2,
reqs(3) => mem_req_32_debug,
reqs(4) => mem_req_32_cpu,
reqs(5) => mem_req_32_usb,
resps(0) => mem_resp_32_cart,
resps(1) => mem_resp_32_1541,
resps(2) => mem_resp_32_1541_2,
resps(3) => mem_resp_32_debug,
resps(4) => mem_resp_32_cpu,
resps(5) => mem_resp_32_usb,
req => mem_req,
resp => mem_resp );
i_aud_select: entity work.audio_select
port map (
clock => sys_clock,
reset => sys_reset,
req => io_req_aud_sel,
resp => io_resp_aud_sel,
drive0 => pwm,
drive1 => pwm_2,
cas_read => CAS_READ,
cas_write => CAS_WRITE,
sid_left => sid_pwm_left,
sid_right => sid_pwm_right,
samp_left => samp_pwm_left,
samp_right => samp_pwm_right,
pwm_out => PWM_OUT );
iec_atn_o <= '0' when atn_o='0' or atn_o_2='0' or hw_atn_o='0' else '1';
iec_clock_o <= '0' when clk_o='0' or clk_o_2='0' or hw_clk_o='0' else '1';
iec_data_o <= '0' when data_o='0' or data_o_2='0' or hw_data_o='0' else '1';
iec_srq_o <= hw_srq_o; -- only source
error <= sys_reset;
DISK_ACTn <= act_led_n xor stuck;
MOTOR_LEDn <= motor_led_n xor error;
CART_LEDn <= cart_led_n xor error;
SDACT_LEDn <= (dirty_led_1_n and dirty_led_2_n and not (sd_act_stretched or busy_led)) xor error;
-- DISK_ACTn <= not freezer_state(1);
-- MOTOR_LEDn <= not freezer_state(0);
-- CART_LEDn <= IRQn;
-- SDACT_LEDn <= NMIn;
filt1: entity work.spike_filter generic map (10) port map(sys_clock, iec_atn_i, atn_i);
filt2: entity work.spike_filter generic map (10) port map(sys_clock, iec_clock_i, clk_i);
filt3: entity work.spike_filter generic map (10) port map(sys_clock, iec_data_i, data_i);
filt4: entity work.spike_filter generic map (10) port map(sys_clock, iec_srq_i, srq_i);
filt5: entity work.spike_filter port map(sys_clock, IRQn, c64_irq_n);
c64_irq <= not c64_irq_n;
-- dummy
SD_DATA <= "ZZ";
g_ela: if g_analyzer generate
signal ev_data : std_logic_vector(15 downto 0);
begin
i_ela: entity work.logic_analyzer
generic map (
g_timer_div => 50,
g_change_width => 16,
g_data_length => 2 )
port map (
clock => sys_clock,
reset => sys_reset,
ev_dav => '0',
ev_data => ev_data,
---
mem_req => mem_req_debug,
mem_resp => mem_resp_debug,
io_req => io_req_debug,
io_resp => io_resp_debug );
i_conv32_debug: entity work.mem_to_mem32(route_through)
port map(
clock => sys_clock,
reset => sys_reset,
mem_req_8 => mem_req_debug,
mem_resp_8 => mem_resp_debug,
mem_req_32 => mem_req_32_debug,
mem_resp_32 => mem_resp_32_debug );
ev_data <= srq_i & atn_i & data_i & clk_i & '1' & atn_o_2 & data_o_2 & clk_o_2 &
'0' & atn_o & data_o & clk_o & hw_srq_o & hw_atn_o & hw_data_o & hw_clk_o;
end generate;
g_ela32: if g_profiler generate
signal ev_data : std_logic_vector(7 downto 0);
begin
i_ela: entity work.logic_analyzer_32
generic map (
g_timer_div => 25 )
port map (
clock => sys_clock,
reset => sys_reset,
ev_dav => '0',
ev_data => ev_data,
---
mem_req => mem_req_32_debug,
mem_resp => mem_resp_32_debug,
io_req => io_req_debug,
io_resp => io_resp_debug );
ev_data <= profiler_irq_flags;
end generate;
end logic;
| gpl-3.0 | 17375f211d61d5b8cef216075bd80420 | 0.464223 | 3.175036 | false | false | false | false |
KB777/1541UltimateII | fpga/fpga_top/ultimate_fpga/vhdl_source/ultimate2_test.vhd | 1 | 5,017 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ultimate2_test is
port (
CLOCK : in std_logic;
-- slot side
PHI2 : out std_logic;
DOTCLK : out std_logic;
RSTn : out std_logic;
BUFFER_ENn : out std_logic;
SLOT_ADDR : out std_logic_vector(15 downto 0);
SLOT_DATA : out std_logic_vector(7 downto 0);
RWn : out std_logic;
BA : in std_logic;
DMAn : out std_logic;
EXROMn : out std_logic;
GAMEn : out std_logic;
ROMHn : out std_logic;
ROMLn : out std_logic;
IO1n : in std_logic;
IO2n : out std_logic;
IRQn : out std_logic;
NMIn : out std_logic;
-- local bus side
LB_ADDR : out std_logic_vector(14 downto 0); -- DRAM A
LB_DATA : inout std_logic_vector(7 downto 0);
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SDRAM_DQM : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CLK : out std_logic;
-- PWM outputs (for audio)
PWM_OUT : out std_logic_vector(1 downto 0) := "11";
-- IEC bus
IEC_ATN : inout std_logic;
IEC_DATA : inout std_logic;
IEC_CLOCK : inout std_logic;
IEC_RESET : in std_logic;
IEC_SRQ_IN : inout std_logic;
DISK_ACTn : out std_logic; -- activity LED
CART_LEDn : out std_logic;
SDACT_LEDn : out std_logic;
MOTOR_LEDn : out std_logic;
-- Debug UART
UART_TXD : out std_logic;
UART_RXD : in std_logic;
-- SD Card Interface
SD_SSn : out std_logic;
SD_CLK : out std_logic;
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_CARDDETn : in std_logic;
SD_DATA : inout std_logic_vector(2 downto 1);
-- RTC Interface
RTC_CS : out std_logic;
RTC_SCK : out std_logic;
RTC_MOSI : out std_logic;
RTC_MISO : in std_logic;
-- Flash Interface
FLASH_CSn : out std_logic;
FLASH_SCK : out std_logic;
FLASH_MOSI : out std_logic;
FLASH_MISO : in std_logic;
-- USB Interface (ULPI)
ULPI_RESET : out std_logic;
ULPI_CLOCK : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
ULPI_DIR : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
-- Cassette Interface
CAS_MOTOR : out std_logic := '0';
CAS_SENSE : out std_logic := 'Z';
CAS_READ : out std_logic := 'Z';
CAS_WRITE : out std_logic := 'Z';
-- Buttons
BUTTON : in std_logic_vector(2 downto 0));
end ultimate2_test;
architecture structural of ultimate2_test is
signal counter : unsigned(23 downto 0) := (others => '0');
signal pulses : unsigned(23 downto 1) := (others => '0');
begin
process(CLOCK)
begin
if rising_edge(CLOCK) then
counter <= counter + 1;
pulses <= counter(23 downto 1) and counter(22 downto 0);
end if;
end process;
-- slot side
BUFFER_ENn <= '0';
SLOT_ADDR <= std_logic_vector(counter(23 downto 8));
SLOT_DATA <= std_logic_vector(counter(7 downto 0));
-- top
DMAn <= pulses(1);
--BA <= pulses(2);
ROMLn <= pulses(3);
IO2n <= pulses(4);
EXROMn <= pulses(5);
GAMEn <= pulses(6);
--IO1n <= pulses(7);
DOTCLK <= pulses(8);
RWn <= pulses(9);
IRQn <= pulses(10);
PHI2 <= pulses(11);
NMIn <= pulses(12);
RSTn <= pulses(13);
ROMHn <= pulses(14);
-- Cassette Interface
CAS_SENSE <= pulses(16);
CAS_READ <= pulses(17);
CAS_WRITE <= pulses(18);
CAS_MOTOR <= pulses(19);
-- local bus side
LB_ADDR <= (others => 'Z');
LB_DATA <= (others => 'Z');
SDRAM_CSn <= 'Z';
SDRAM_RASn <= 'Z';
SDRAM_CASn <= 'Z';
SDRAM_WEn <= 'Z';
SDRAM_DQM <= 'Z';
SDRAM_CKE <= 'Z';
SDRAM_CLK <= 'Z';
-- PWM outputs (for audio)
PWM_OUT <= "ZZ";
-- IEC bus
IEC_ATN <= 'Z';
IEC_DATA <= 'Z';
IEC_CLOCK <= 'Z';
IEC_SRQ_IN <= 'Z';
DISK_ACTn <= '0';
CART_LEDn <= '1';
SDACT_LEDn <= '0';
MOTOR_LEDn <= '1';
-- Debug UART
UART_TXD <= '1';
-- SD Card Interface
SD_SSn <= 'Z';
SD_CLK <= 'Z';
SD_MOSI <= 'Z';
SD_DATA <= "ZZ";
-- RTC Interface
RTC_CS <= '0';
RTC_SCK <= '0';
RTC_MOSI <= '0';
-- Flash Interface
FLASH_CSn <= '1';
FLASH_SCK <= '1';
FLASH_MOSI <= '1';
-- USB Interface (ULPI)
ULPI_RESET <= '0';
ULPI_STP <= '0';
ULPI_DATA <= (others => 'Z');
end structural;
| gpl-3.0 | 51d5a2c789f91068d2359e6f857f1eb2 | 0.491927 | 3.173308 | false | false | false | false |
KB777/1541UltimateII | fpga/1541/vhdl_source/via6522.vhd | 1 | 24,664 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity via6522 is
port (
clock : in std_logic;
clock_en : in std_logic; -- for counters and stuff
reset : in std_logic;
addr : in std_logic_vector(3 downto 0);
wen : in std_logic;
ren : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
-- pio --
port_a_o : out std_logic_vector(7 downto 0);
port_a_t : out std_logic_vector(7 downto 0);
port_a_i : in std_logic_vector(7 downto 0);
port_b_o : out std_logic_vector(7 downto 0);
port_b_t : out std_logic_vector(7 downto 0);
port_b_i : in std_logic_vector(7 downto 0);
-- handshake pins
ca1_i : in std_logic;
ca2_o : out std_logic;
ca2_i : in std_logic;
ca2_t : out std_logic;
cb1_o : out std_logic;
cb1_i : in std_logic;
cb1_t : out std_logic;
cb2_o : out std_logic;
cb2_i : in std_logic;
cb2_t : out std_logic;
irq : out std_logic );
end via6522;
architecture Gideon of via6522 is
type pio_t is
record
pra : std_logic_vector(7 downto 0);
ddra : std_logic_vector(7 downto 0);
prb : std_logic_vector(7 downto 0);
ddrb : std_logic_vector(7 downto 0);
end record;
constant pio_default : pio_t := (others => (others => '0'));
constant latch_reset_pattern : std_logic_vector(15 downto 0) := X"01AA";
signal pio_i : pio_t;
signal irq_mask : std_logic_vector(6 downto 0) := (others => '0');
signal irq_flags : std_logic_vector(6 downto 0) := (others => '0');
signal irq_events : std_logic_vector(6 downto 0) := (others => '0');
signal irq_out : std_logic;
signal timer_a_latch : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_b_latch : std_logic_vector(7 downto 0) := latch_reset_pattern(7 downto 0);
signal timer_a_count : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_b_count : std_logic_vector(15 downto 0) := latch_reset_pattern;
signal timer_a_out : std_logic;
signal timer_b_tick : std_logic;
signal acr, pcr : std_logic_vector(7 downto 0) := X"00";
signal shift_reg : std_logic_vector(7 downto 0) := X"00";
signal serport_en : std_logic;
signal ser_cb2_o : std_logic;
signal hs_cb2_o : std_logic;
alias ca2_event : std_logic is irq_events(0);
alias ca1_event : std_logic is irq_events(1);
alias serial_event : std_logic is irq_events(2);
alias cb2_event : std_logic is irq_events(3);
alias cb1_event : std_logic is irq_events(4);
alias timer_b_event : std_logic is irq_events(5);
alias timer_a_event : std_logic is irq_events(6);
alias ca2_flag : std_logic is irq_flags(0);
alias ca1_flag : std_logic is irq_flags(1);
alias serial_flag : std_logic is irq_flags(2);
alias cb2_flag : std_logic is irq_flags(3);
alias cb1_flag : std_logic is irq_flags(4);
alias timer_b_flag : std_logic is irq_flags(5);
alias timer_a_flag : std_logic is irq_flags(6);
alias tmr_a_output_en : std_logic is acr(7);
alias tmr_a_freerun : std_logic is acr(6);
alias tmr_b_count_mode : std_logic is acr(5);
alias shift_dir : std_logic is acr(4);
alias shift_clk_sel : std_logic_vector(1 downto 0) is acr(3 downto 2);
alias shift_mode_control : std_logic_vector(2 downto 0) is acr(4 downto 2);
alias pb_latch_en : std_logic is acr(1);
alias pa_latch_en : std_logic is acr(0);
alias cb2_is_output : std_logic is pcr(7);
alias cb2_edge_select : std_logic is pcr(6); -- for when CB2 is input
alias cb2_no_irq_clr : std_logic is pcr(5); -- for when CB2 is input
alias cb2_out_mode : std_logic_vector(1 downto 0) is pcr(6 downto 5);
alias cb1_edge_select : std_logic is pcr(4);
alias ca2_is_output : std_logic is pcr(3);
alias ca2_edge_select : std_logic is pcr(2); -- for when CA2 is input
alias ca2_no_irq_clr : std_logic is pcr(1); -- for when CA2 is input
alias ca2_out_mode : std_logic_vector(1 downto 0) is pcr(2 downto 1);
alias ca1_edge_select : std_logic is pcr(0);
signal ira, irb : std_logic_vector(7 downto 0) := (others => '0');
signal pb_latch_ready : std_logic := '0';
signal pa_latch_ready : std_logic := '0';
signal write_t1c_h : std_logic;
signal write_t2c_h : std_logic;
signal ca1_c, ca2_c : std_logic;
signal cb1_c, cb2_c : std_logic;
signal ca1_d, ca2_d : std_logic;
signal cb1_d, cb2_d : std_logic;
signal set_ca2_low : std_logic;
signal set_cb2_low : std_logic;
begin
irq <= irq_out;
irq_out <= '0' when (irq_flags and irq_mask) = "0000000" else '1';
write_t1c_h <= '1' when addr = X"5" and wen='1' else '0';
write_t2c_h <= '1' when addr = X"9" and wen='1' else '0';
-- input latches
ira <= port_a_i when pa_latch_ready='0';
irb <= port_b_i when pb_latch_ready='0';
pa_latch_ready <= '1' when (ca1_event='1') and (pa_latch_en='1') and (pa_latch_ready='0') else
'0' when (pa_latch_en='0') or (ren='1' and addr=X"1");
pb_latch_ready <= '1' when (cb1_event='1') and (pb_latch_en='1') and (pb_latch_ready='0') else
'0' when (pb_latch_en='0') or (ren='1' and addr=X"0");
ca1_event <= (ca1_c xor ca1_d) and (ca1_d xor ca1_edge_select);
ca2_event <= (ca2_c xor ca2_d) and (ca2_d xor ca2_edge_select);
cb1_event <= (cb1_c xor cb1_d) and (cb1_d xor cb1_edge_select);
cb2_event <= (cb2_c xor cb2_d) and (cb2_d xor cb2_edge_select);
ca2_t <= ca2_is_output;
cb2_t <= cb2_is_output when serport_en='0' else shift_dir;
cb2_o <= hs_cb2_o when serport_en='0' else ser_cb2_o;
process(clock)
begin
if rising_edge(clock) then
-- CA1/CA2/CB1/CB2 edge detect flipflops
ca1_c <= To_X01(ca1_i);
ca2_c <= To_X01(ca2_i);
cb1_c <= To_X01(cb1_i);
cb2_c <= To_X01(cb2_i);
ca1_d <= ca1_c;
ca2_d <= ca2_c;
cb1_d <= cb1_c;
cb2_d <= cb2_c;
-- CA2 output logic
case ca2_out_mode is
when "00" =>
if ca1_event='1' then
ca2_o <= '1';
elsif (ren='1' or wen='1') and addr=X"1" then
ca2_o <= '0';
end if;
when "01" =>
if clock_en='1' then
ca2_o <= not set_ca2_low;
set_ca2_low <= '0';
end if;
if (ren='1' or wen='1') and addr=X"1" then
if clock_en='1' then
ca2_o <= '0';
else
set_ca2_low <= '1';
end if;
end if;
when "10" =>
ca2_o <= '0';
when "11" =>
ca2_o <= '1';
when others =>
null;
end case;
-- CB2 output logic
case cb2_out_mode is
when "00" =>
if cb1_event='1' then
hs_cb2_o <= '1';
elsif (ren='1' or wen='1') and addr=X"0" then
hs_cb2_o <= '0';
end if;
when "01" =>
if clock_en='1' then
hs_cb2_o <= not set_cb2_low;
set_cb2_low <= '0';
end if;
if (ren='1' or wen='1') and addr=X"0" then
if clock_en='1' then
hs_cb2_o <= '0';
else
set_cb2_low <= '1';
end if;
end if;
when "10" =>
hs_cb2_o <= '0';
when "11" =>
hs_cb2_o <= '1';
when others =>
null;
end case;
-- Interrupt logic
irq_flags <= irq_flags or irq_events;
-- Writes --
if wen='1' then
case addr is
when X"0" => -- ORB
pio_i.prb <= data_in;
if cb2_no_irq_clr='0' then
cb2_flag <= '0';
end if;
cb1_flag <= '0';
when X"1" => -- ORA
pio_i.pra <= data_in;
if ca2_no_irq_clr='0' then
ca2_flag <= '0';
end if;
ca1_flag <= '0';
when X"2" => -- DDRB
pio_i.ddrb <= data_in;
when X"3" => -- DDRA
pio_i.ddra <= data_in;
when X"4" => -- TA LO counter (write=latch)
timer_a_latch(7 downto 0) <= data_in;
when X"5" => -- TA HI counter
timer_a_latch(15 downto 8) <= data_in;
timer_a_flag <= '0';
when X"6" => -- TA LO latch
timer_a_latch(7 downto 0) <= data_in;
when X"7" => -- TA HI latch
timer_a_latch(15 downto 8) <= data_in;
when X"8" => -- TB LO latch
timer_b_latch(7 downto 0) <= data_in;
when X"9" => -- TB HI counter
timer_b_flag <= '0';
when X"A" => -- Serial port
serial_flag <= '0';
when X"B" => -- ACR (Auxiliary Control Register)
acr <= data_in;
when X"C" => -- PCR (Peripheral Control Register)
pcr <= data_in;
when X"D" => -- IFR
irq_flags <= irq_flags and not data_in(6 downto 0);
when X"E" => -- IER
if data_in(7)='1' then -- set
irq_mask <= irq_mask or data_in(6 downto 0);
else -- clear
irq_mask <= irq_mask and not data_in(6 downto 0);
end if;
when X"F" => -- ORA no handshake
pio_i.pra <= data_in;
when others =>
null;
end case;
end if;
-- Reads --
case addr is
when X"0" => -- ORB
--Port B reads its own output register for pins set to output.
data_out(0) <= (pio_i.prb(0) and pio_i.ddrb(0)) or (irb(0) and not pio_i.ddrb(0));
data_out(1) <= (pio_i.prb(1) and pio_i.ddrb(1)) or (irb(1) and not pio_i.ddrb(1));
data_out(2) <= (pio_i.prb(2) and pio_i.ddrb(2)) or (irb(2) and not pio_i.ddrb(2));
data_out(3) <= (pio_i.prb(3) and pio_i.ddrb(3)) or (irb(3) and not pio_i.ddrb(3));
data_out(4) <= (pio_i.prb(4) and pio_i.ddrb(4)) or (irb(4) and not pio_i.ddrb(4));
data_out(5) <= (pio_i.prb(5) and pio_i.ddrb(5)) or (irb(5) and not pio_i.ddrb(5));
data_out(6) <= (pio_i.prb(6) and pio_i.ddrb(6)) or (irb(6) and not pio_i.ddrb(6));
data_out(7) <= (pio_i.prb(7) and (pio_i.ddrb(7) or tmr_a_output_en)) or (irb(7) and not (pio_i.ddrb(7) or tmr_a_output_en));
if cb2_no_irq_clr='0' and ren='1' then
cb2_flag <= '0';
end if;
if ren='1' then
cb1_flag <= '0';
end if;
when X"1" => -- ORA
data_out <= ira;
if ca2_no_irq_clr='0' and ren='1' then
ca2_flag <= '0';
end if;
if ren='1' then
ca1_flag <= '0';
end if;
when X"2" => -- DDRB
data_out <= pio_i.ddrb;
when X"3" => -- DDRA
data_out <= pio_i.ddrb;
when X"4" => -- TA LO counter
data_out <= timer_a_count(7 downto 0);
if ren='1' then
timer_a_flag <= '0';
end if;
when X"5" => -- TA HI counter
data_out <= timer_a_count(15 downto 8);
when X"6" => -- TA LO latch
data_out <= timer_a_latch(7 downto 0);
when X"7" => -- TA HI latch
data_out <= timer_a_latch(15 downto 8);
when X"8" => -- TA LO counter
data_out <= timer_b_count(7 downto 0);
if ren='1' then
timer_b_flag <= '0';
end if;
when X"9" => -- TA HI counter
data_out <= timer_b_count(15 downto 8);
when X"A" => -- SR
data_out <= shift_reg;
if ren='1' then
serial_flag <= '0';
end if;
when X"B" => -- ACR
data_out <= acr;
when X"C" => -- PCR
data_out <= pcr;
when X"D" => -- IFR
data_out <= irq_out & irq_flags;
when X"E" => -- IER
data_out <= '0' & irq_mask;
when X"F" => -- ORA
data_out <= ira;
when others =>
null;
end case;
if reset='1' then
pio_i <= pio_default;
irq_mask <= (others => '0');
irq_flags <= (others => '0');
acr <= (others => '0');
pcr <= (others => '0');
ca2_o <= '1';
hs_cb2_o <= '1';
set_ca2_low <= '0';
set_cb2_low <= '0';
timer_a_latch <= latch_reset_pattern;
timer_b_latch <= latch_reset_pattern(7 downto 0);
end if;
end if;
end process;
-- PIO Out select --
port_a_o <= pio_i.pra;
port_b_o(6 downto 0) <= pio_i.prb(6 downto 0);
port_b_o(7) <= pio_i.prb(7) when tmr_a_output_en='0' else timer_a_out;
port_a_t <= pio_i.ddra;
port_b_t(6 downto 0) <= pio_i.ddrb(6 downto 0);
port_b_t(7) <= pio_i.ddrb(7) or tmr_a_output_en;
-- Timer A
tmr_a: block
signal timer_a_reload : std_logic;
signal timer_a_post_oneshot : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
timer_a_event <= '0';
if clock_en='1' then
-- always count, or load
if timer_a_reload = '1' then
timer_a_count <= timer_a_latch;
timer_a_reload <= '0';
else
if timer_a_count = X"0000" then
-- generate an event if we were triggered
if tmr_a_freerun = '1' then
timer_a_event <= '1';
-- if in free running mode, set a flag to reload
timer_a_reload <= tmr_a_freerun;
else
if (timer_a_post_oneshot = '0') then
timer_a_post_oneshot <= '1';
timer_a_event <= '1';
end if;
end if;
-- toggle output
timer_a_out <= not timer_a_out;
end if;
--Timer coutinues to count in both free run and one shot.
timer_a_count <= timer_a_count - X"0001";
end if;
end if;
if write_t1c_h = '1' then
timer_a_out <= '0';
timer_a_count <= data_in & timer_a_latch(7 downto 0);
timer_a_reload <= '0';
timer_a_post_oneshot <= '0';
end if;
if reset='1' then
timer_a_out <= '1';
timer_a_count <= latch_reset_pattern;
timer_a_reload <= '0';
timer_a_post_oneshot <= '0';
end if;
end if;
end process;
end block tmr_a;
-- Timer B
tmr_b: block
signal timer_b_reload : std_logic;
signal timer_b_post_oneshot : std_logic;
signal pb6_c, pb6_d : std_logic;
begin
process(clock)
variable timer_b_decrement : std_logic;
begin
if rising_edge(clock) then
timer_b_event <= '0';
timer_b_tick <= '0';
pb6_c <= port_b_i(6);
timer_b_decrement := '0';
if clock_en='1' then
pb6_d <= pb6_c;
if timer_b_reload = '1' then
timer_b_count <= X"00" & timer_b_latch(7 downto 0);
timer_b_reload <= '0';
else
if tmr_b_count_mode = '1' then
if (pb6_d='0' and pb6_c='1') then
timer_b_decrement := '1';
end if;
else -- one shot or used for shirt register
timer_b_decrement := '1';
end if;
if timer_b_decrement = '1' then
if timer_b_count = X"0000" then
if (timer_b_post_oneshot = '0') then
timer_b_post_oneshot <= '1';
timer_b_event <= '1';
end if;
timer_b_tick <= '1';
case shift_mode_control is
when "001" | "101" | "100" =>
timer_b_reload <= '1';
when others =>
null;
end case;
end if;
timer_b_count <= timer_b_count - X"0001";
end if;
end if;
end if;
if write_t2c_h = '1' then
timer_b_count <= data_in & timer_b_latch(7 downto 0);
timer_b_reload <= '0';
timer_b_post_oneshot <= '0';
end if;
if reset='1' then
timer_b_count <= latch_reset_pattern;
timer_b_reload <= '0';
timer_b_post_oneshot <= '0';
end if;
end if;
end process;
end block tmr_b;
ser: block
signal shift_clock_d : std_logic;
signal shift_clock : std_logic;
signal shift_tick_r : std_logic;
signal shift_tick_f : std_logic;
signal cb1_c, cb2_c : std_logic;
signal mpu_write : std_logic;
signal mpu_read : std_logic;
signal bit_cnt : integer range 0 to 7;
signal shift_active : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
case shift_clk_sel is
when "10" =>
if shift_active='0' then
shift_clock <= '1';
elsif clock_en='1' then
shift_clock <= not shift_clock;
end if;
when "00"|"01" =>
if shift_active='0' then
shift_clock <= '1';
elsif timer_b_tick='1' then
shift_clock <= not shift_clock;
end if;
when others => -- "11"
shift_clock <= To_X01(cb1_i);
end case;
shift_clock_d <= shift_clock;
end if;
end process;
shift_tick_r <= not shift_clock_d and shift_clock;
shift_tick_f <= shift_clock_d and not shift_clock;
cb1_t <= '0' when shift_clk_sel="11" else serport_en;
cb1_o <= shift_clock;
mpu_write <= wen when addr=X"A" else '0';
mpu_read <= ren when addr=X"A" else '0';
serport_en <= shift_dir or shift_clk_sel(1) or shift_clk_sel(0);
process(clock)
begin
if rising_edge(clock) then
cb1_c <= To_X01(cb1_i);
cb2_c <= To_X01(cb2_i);
if shift_clk_sel = "00" then
bit_cnt <= 7;
if shift_dir='0' then -- disabled mode
shift_active <= '0';
end if;
end if;
if mpu_read='1' or mpu_write='1' then
bit_cnt <= 7;
shift_active <= '1';
if mpu_write='1' then
shift_reg <= data_in;
end if;
end if;
serial_event <= '0';
if shift_active='1' then
if shift_tick_f='1' then
ser_cb2_o <= shift_reg(7);
end if;
if shift_tick_r='1' then
if shift_dir='1' then -- output
shift_reg <= shift_reg(6 downto 0) & shift_reg(7);
else
shift_reg <= shift_reg(6 downto 0) & cb2_c;
end if;
if bit_cnt=0 then
serial_event <= '1';
shift_active <= '0';
else
bit_cnt <= bit_cnt - 1;
end if;
end if;
end if;
if reset='1' then
shift_reg <= (others => '1');
shift_active <= '0';
bit_cnt <= 0;
ser_cb2_o <= '1';
end if;
end if;
end process;
end block ser;
end Gideon;
| gpl-3.0 | 10c286f63c7774fa9074d6ff0a23096e | 0.38396 | 3.910576 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/adsr_multi.vhd | 5 | 8,478 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.sid_debug_pkg.all;
-- LUT: 195, FF:68
entity adsr_multi is
generic (
g_num_voices : integer := 8 );
port (
clock : in std_logic;
reset : in std_logic;
voice_i : in unsigned(3 downto 0);
enable_i : in std_logic;
voice_o : out unsigned(3 downto 0);
enable_o : out std_logic;
gate : in std_logic;
attack : in std_logic_vector(3 downto 0);
decay : in std_logic_vector(3 downto 0);
sustain : in std_logic_vector(3 downto 0);
release : in std_logic_vector(3 downto 0);
env_state: out std_logic_vector(1 downto 0); -- for testing only
env_out : out unsigned(7 downto 0) );
end adsr_multi;
-- 158 1 62 .. FF
-- 45 2 35 .. 61
-- 26 4 1C .. 34
-- 13 8 0D .. 1B
-- 6 16 07 .. 0C
-- 7 30 00 .. 06
architecture gideon of adsr_multi is
type presc_array_t is array(natural range <>) of unsigned(15 downto 0);
constant prescalers : presc_array_t(0 to 15) := (
X"0008", X"001F", X"003E", X"005E",
X"0094", X"00DB", X"010A", X"0138",
X"0187", X"03D0", X"07A1", X"0C35",
X"0F42", X"2DC7", X"4C4B", X"7A12" );
signal enveloppe : unsigned(7 downto 0) := (others => '0');
signal state : unsigned(1 downto 0) := (others => '0');
constant st_release : unsigned(1 downto 0) := "00";
constant st_attack : unsigned(1 downto 0) := "01";
constant st_decay : unsigned(1 downto 0) := "11";
type state_array_t is array(natural range <>) of unsigned(29 downto 0);
signal state_array : state_array_t(0 to g_num_voices-1) := (others => (others => '0'));
signal voice_dbg : t_voice_debug_array(0 to g_num_voices-1);
begin
env_out <= enveloppe;
env_state <= std_logic_vector(state);
-- FF-5E 01
-- 5D-37 02
-- 36-1B 04
-- 1A-0F 08
-- 0E-07 10
-- 06-01 1E
process(clock)
function logarithmic(lev: unsigned(7 downto 0)) return unsigned is
variable res : unsigned(4 downto 0);
begin
if lev = X"00" then
res := "00000"; -- prescaler off
elsif lev < X"07" then
res := "11101"; -- 1E-1
elsif lev < X"0F" then
res := "01111"; -- 10-1
elsif lev < X"1B" then
res := "00111"; -- 08-1
elsif lev < X"37" then
res := "00011"; -- 04-1
elsif lev < X"5E" then
res := "00001"; -- 02-1
else
res := "00000"; -- 01-1
end if;
return res;
end function logarithmic;
variable presc_select : integer range 0 to 15;
variable cur_state : unsigned(1 downto 0);
variable cur_env : unsigned(7 downto 0);
variable cur_pre15 : unsigned(14 downto 0);
variable cur_pre5 : unsigned(4 downto 0);
variable next_state : unsigned(1 downto 0);
variable next_env : unsigned(7 downto 0);
variable next_pre15 : unsigned(14 downto 0);
variable next_pre5 : unsigned(4 downto 0);
variable presc_val : unsigned(14 downto 0);
variable log_div : unsigned(4 downto 0);
variable do_count_15 : std_logic;
variable do_count_5 : std_logic;
variable voice_x : integer;
begin
if rising_edge(clock) then
cur_state := state_array(0)(1 downto 0);
cur_env := state_array(0)(9 downto 2);
cur_pre15 := state_array(0)(24 downto 10);
cur_pre5 := state_array(0)(29 downto 25);
voice_o <= voice_i;
enable_o <= enable_i;
next_state := cur_state;
next_env := cur_env;
next_pre15 := cur_pre15;
next_pre5 := cur_pre5;
-- PRESCALER LOGIC, output: do_count --
-- 15 bit prescaler select --
case cur_state is
when st_attack =>
presc_select := to_integer(unsigned(attack));
when st_decay =>
presc_select := to_integer(unsigned(decay));
when others => -- includes release and idle
presc_select := to_integer(unsigned(release));
end case;
presc_val := prescalers(presc_select)(14 downto 0);
-- 15 bit prescaler counter --
do_count_15 := '0';
if cur_pre15 = presc_val then
next_pre15 := (others => '0');
do_count_15 := '1';
else
next_pre15 := cur_pre15 + 1;
end if;
-- 5 bit prescaler --
log_div := logarithmic(cur_env);
do_count_5 := '0';
if do_count_15='1' then
if (cur_state = st_attack) or cur_pre5 = log_div then
next_pre5 := "00000";
do_count_5 := '1';
else
next_pre5 := cur_pre5 + 1;
end if;
end if;
-- END PRESCALER LOGIC --
case cur_state is
when st_attack =>
if gate = '0' then
next_state := st_release;
elsif cur_env = X"FF" then
next_state := st_decay;
end if;
if do_count_15='1' then
next_env := cur_env + 1;
-- if cur_env = X"FE" or cur_env = X"FF" then -- result could be FF, but also 00!!
-- next_state := st_decay;
-- end if;
end if;
when st_decay =>
if gate = '0' then
next_state := st_release;
end if;
if do_count_15='1' and do_count_5='1' and
std_logic_vector(cur_env) /= (sustain & sustain) and
cur_env /= X"00" then
next_env := cur_env - 1;
end if;
when st_release =>
if gate = '1' then
next_state := st_attack;
end if;
if do_count_15='1' and do_count_5='1' and
cur_env /= X"00" then
next_env := cur_env - 1;
end if;
when others =>
next_state := st_release;
end case;
if enable_i='1' then
state_array(0 to g_num_voices-2) <= state_array(1 to g_num_voices-1);
state_array(g_num_voices-1) <= next_pre5 & next_pre15 & next_env & next_state;
enveloppe <= next_env;
state <= next_state;
voice_x := to_integer(voice_i);
voice_dbg(voice_x).state <= next_state;
voice_dbg(voice_x).enveloppe <= next_env;
voice_dbg(voice_x).pre15 <= next_pre15;
voice_dbg(voice_x).pre5 <= next_pre5;
voice_dbg(voice_x).presc <= presc_val;
voice_dbg(voice_x).gate <= gate;
voice_dbg(voice_x).attack <= attack;
voice_dbg(voice_x).decay <= decay;
voice_dbg(voice_x).sustain <= sustain;
voice_dbg(voice_x).release <= release;
end if;
if reset='1' then
state <= "00";
enveloppe <= (others => '0');
enable_o <= '0';
end if;
end if;
end process;
end gideon;
| gpl-3.0 | d9399b9c0743a8a53cc9eec28f4cc79e | 0.446921 | 3.903315 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_DMAmaster.vhd | 3 | 21,895 | -------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the toplevel of the openMAC DMA master component.
-- It introduces a generic master device applying burst transfers for
-- RX and TX packet data transfers via a common bus.
--
-------------------------------------------------------------------------------
--
-- 2011-08-03 V0.01 zelenkaj First version
-- 2011-10-13 V0.02 zelenkaj changed names of instances
-- 2011-11-28 V0.03 zelenkaj Added DMA observer
-- 2011-11-29 V0.04 zelenkaj Changed clkXing of Dma Addr
-- 2011-11-30 V0.05 zelenkaj Added generic for DMA observer
-- 2011-12-02 V0.06 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.07 zelenkaj Reduced Dma Req overflow
-- 2012-03-21 V0.10 zelenkaj Fixed 32 bit FIFO to support openMAC endian
-- 2012-04-17 V0.11 zelenkaj Added forwarding of DMA read length
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
entity openMAC_DMAmaster is
generic(
simulate : boolean := false;
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
gen_rx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
tx_fifo_word_size_g : integer := 32;
rx_fifo_word_size_g : integer := 32;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end openMAC_DMAmaster;
architecture strct of openMAC_DMAmaster is
---- Component declarations -----
component dma_handler
generic(
dma_highadr_g : integer := 31;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_wr_clk : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_full : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_rd_clk : in std_logic;
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_rd : out std_logic;
dma_new_addr_wr : out std_logic;
dma_new_len : out std_logic;
dma_rd_err : out std_logic;
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_wr_err : out std_logic;
rx_aclr : out std_logic;
rx_wr_req : out std_logic;
tx_rd_req : out std_logic
);
end component;
component master_handler
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burst_wr_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_rd : in std_logic;
dma_new_addr_wr : in std_logic;
dma_new_len_rd : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
rx_rd_req : out std_logic;
tx_aclr : out std_logic;
tx_wr_req : out std_logic
);
end component;
component OpenMAC_DMAFifo
generic(
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port (
aclr : in std_logic;
rd_clk : in std_logic;
rd_req : in std_logic;
wr_clk : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end component;
component slow2fastSync
generic(
doSync_g : boolean := TRUE
);
port (
clkDst : in std_logic;
clkSrc : in std_logic;
dataSrc : in std_logic;
rstDst : in std_logic;
rstSrc : in std_logic;
dataDst : out std_logic
);
end component;
---- Architecture declarations -----
--constants
constant tx_fifo_word_size_c : natural := natural(tx_fifo_word_size_g);
constant tx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(tx_fifo_word_size_c))));
constant rx_fifo_word_size_c : natural := natural(rx_fifo_word_size_g);
constant rx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(rx_fifo_word_size_c))));
---- Signal declarations used on the diagram ----
signal dma_new_addr_rd : std_logic;
signal dma_new_addr_wr : std_logic;
signal dma_new_rd_len : std_logic;
signal m_dma_new_addr_rd : std_logic;
signal m_dma_new_addr_wr : std_logic;
signal m_dma_new_rd_len : std_logic;
signal m_mac_rx_off : std_logic;
signal m_mac_tx_off : std_logic;
signal rx_aclr : std_logic;
signal rx_rd_clk : std_logic;
signal rx_rd_empty : std_logic;
signal rx_rd_full : std_logic;
signal rx_rd_req : std_logic;
signal rx_wr_clk : std_logic;
signal rx_wr_empty : std_logic;
signal rx_wr_full : std_logic;
signal rx_wr_req : std_logic;
signal rx_wr_req_s : std_logic;
signal tx_aclr : std_logic;
signal tx_rd_clk : std_logic;
signal tx_rd_empty : std_logic;
signal tx_rd_empty_s : std_logic;
signal tx_rd_empty_s_l : std_logic;
signal tx_rd_full : std_logic;
signal tx_rd_req : std_logic;
signal tx_rd_req_s : std_logic;
signal tx_rd_sel_word : std_logic;
signal tx_wr_clk : std_logic;
signal tx_wr_empty : std_logic;
signal tx_wr_full : std_logic;
signal tx_wr_req : std_logic;
signal dma_addr_trans : std_logic_vector (dma_highadr_g downto 1);
signal dma_rd_len_trans : std_logic_vector (11 downto 0);
signal rd_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rx_rd_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal rx_wr_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal tx_rd_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal tx_wr_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal wr_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal wr_data_s : std_logic_vector (fifo_data_width_g/2-1 downto 0);
begin
---- Component instantiations ----
THE_DMA_HANDLER : dma_handler
generic map (
dma_highadr_g => dma_highadr_g,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_ack_rd => dma_ack_rd,
dma_ack_wr => dma_ack_wr,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_addr_out => dma_addr_trans( dma_highadr_g downto 1 ),
dma_clk => dma_clk,
dma_new_addr_rd => dma_new_addr_rd,
dma_new_addr_wr => dma_new_addr_wr,
dma_new_len => dma_new_rd_len,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_rd_len_out => dma_rd_len_trans,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_rd,
dma_req_wr => dma_req_wr,
dma_wr_err => dma_wr_err,
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst,
rx_aclr => rx_aclr,
rx_wr_clk => rx_wr_clk,
rx_wr_empty => rx_wr_empty,
rx_wr_full => rx_wr_full,
rx_wr_req => rx_wr_req,
rx_wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_rd_clk => tx_rd_clk,
tx_rd_empty => tx_rd_empty,
tx_rd_full => tx_rd_full,
tx_rd_req => tx_rd_req,
tx_rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
THE_MASTER_HANDLER : master_handler
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
m_burst_wr_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount_width_g,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_addr_in => dma_addr_trans( dma_highadr_g downto 1 ),
dma_len_rd => dma_rd_len_trans,
dma_new_addr_rd => m_dma_new_addr_rd,
dma_new_addr_wr => m_dma_new_addr_wr,
dma_new_len_rd => m_dma_new_rd_len,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( fifo_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
mac_rx_off => m_mac_rx_off,
mac_tx_off => m_mac_tx_off,
rst => rst,
rx_rd_clk => rx_rd_clk,
rx_rd_empty => rx_rd_empty,
rx_rd_full => rx_rd_full,
rx_rd_req => rx_rd_req,
rx_rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_aclr => tx_aclr,
tx_wr_clk => tx_wr_clk,
tx_wr_empty => tx_wr_empty,
tx_wr_full => tx_wr_full,
tx_wr_req => tx_wr_req,
tx_wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
rx_rd_clk <= m_clk;
tx_rd_clk <= dma_clk;
rx_wr_clk <= dma_clk;
tx_wr_clk <= m_clk;
sync1 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_tx_off,
dataSrc => mac_tx_off,
rstDst => rst,
rstSrc => rst
);
sync2 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_mac_rx_off,
dataSrc => mac_rx_off,
rstDst => rst,
rstSrc => rst
);
---- Generate statements ----
gen16bitFifo : if fifo_data_width_g = 16 generate
begin
txFifoGen : if gen_tx_fifo_g generate
begin
TX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty_s,
rd_full => tx_rd_full,
rd_req => tx_rd_req,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_empty_proc :
process(tx_aclr, tx_rd_clk)
begin
if tx_aclr = '1' then
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end process;
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
end generate txFifoGen;
rxFifoGen : if gen_rx_fifo_g generate
begin
RX_FIFO_16 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
end generate rxFifoGen;
--
wr_data <= dma_dout;
dma_din <= rd_data;
end generate gen16bitFifo;
genRxAddrSync : if gen_rx_fifo_g generate
begin
sync4 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_wr,
dataSrc => dma_new_addr_wr,
rstDst => rst,
rstSrc => rst
);
end generate genRxAddrSync;
genTxAddrSync : if gen_tx_fifo_g generate
begin
sync5 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_addr_rd,
dataSrc => dma_new_addr_rd,
rstDst => rst,
rstSrc => rst
);
sync6 : slow2fastSync
port map(
clkDst => m_clk,
clkSrc => dma_clk,
dataDst => m_dma_new_rd_len,
dataSrc => dma_new_rd_len,
rstDst => rst,
rstSrc => rst
);
end generate genTxAddrSync;
gen32bitFifo : if fifo_data_width_g = 32 generate
begin
txFifoGen32 : if gen_tx_fifo_g generate
begin
TX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => tx_fifo_word_size_c,
fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
aclr => tx_aclr,
rd_clk => tx_rd_clk,
rd_data => rd_data( fifo_data_width_g-1 downto 0 ),
rd_empty => tx_rd_empty_s,
rd_full => tx_rd_full,
rd_req => tx_rd_req_s,
rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => tx_wr_clk,
wr_data => m_readdata( fifo_data_width_g-1 downto 0 ),
wr_empty => tx_wr_empty,
wr_full => tx_wr_full,
wr_req => tx_wr_req,
wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
tx_rd_proc :
process (tx_rd_clk, rst)
begin
if rst = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_sel_word = '0' then
tx_rd_sel_word <= '1';
else
tx_rd_sel_word <= '0';
--workaround...
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end if;
end process;
tx_rd_req_s <= tx_rd_req when tx_rd_sel_word = '0' else '0';
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
dma_din <= rd_data(15 downto 0) when tx_rd_sel_word = '1' else
rd_data(31 downto 16);
end generate txFifoGen32;
rxFifoGen32 : if gen_rx_fifo_g generate
begin
RX_FIFO_32 : OpenMAC_DMAFifo
generic map (
fifo_data_width_g => fifo_data_width_g,
fifo_word_size_g => rx_fifo_word_size_c,
fifo_word_size_log2_g => rx_fifo_word_size_log2_c
)
port map(
aclr => rx_aclr,
rd_clk => rx_rd_clk,
rd_data => m_writedata( fifo_data_width_g-1 downto 0 ),
rd_empty => rx_rd_empty,
rd_full => rx_rd_full,
rd_req => rx_rd_req,
rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
wr_clk => rx_wr_clk,
wr_data => wr_data( fifo_data_width_g-1 downto 0 ),
wr_empty => rx_wr_empty,
wr_full => rx_wr_full,
wr_req => rx_wr_req_s,
wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 )
);
rx_wr_proc :
process (rx_wr_clk, rst)
variable toggle : std_logic;
begin
if rst = '1' then
wr_data_s <= (others => '0');
toggle := '0';
rx_wr_req_s <= '0';
elsif rising_edge(rx_wr_clk) then
rx_wr_req_s <= '0';
if mac_rx_off = '1' then
toggle := '0';
elsif rx_wr_req = '1' then
if toggle = '0' then
--capture data
wr_data_s <= dma_dout;
toggle := '1';
else
rx_wr_req_s <= '1';
toggle := '0';
end if;
end if;
end if;
end process;
wr_data <= dma_dout & wr_data_s;
end generate rxFifoGen32;
end generate gen32bitFifo;
end strct;
| gpl-2.0 | af7b7ea5d119ba000941b852b339d533 | 0.568303 | 3.069966 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb2/vhdl_source/usb_io_bank.vhd | 5 | 8,681 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb_io_bank is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : in unsigned(7 downto 0);
io_write : in std_logic;
io_read : in std_logic;
io_wdata : in std_logic_vector(15 downto 0);
io_rdata : out std_logic_vector(15 downto 0);
stall : out std_logic;
-- Memory controller and buffer
mem_ready : in std_logic;
transferred : in unsigned(10 downto 0);
-- Register access
reg_read : out std_logic := '0';
reg_write : out std_logic := '0';
reg_ack : in std_logic;
reg_addr : out std_logic_vector(5 downto 0) := (others => '0');
reg_wdata : out std_logic_vector(7 downto 0) := X"00";
reg_rdata : in std_logic_vector(7 downto 0);
status : in std_logic_vector(7 downto 0);
-- I/O pins from RX
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
rx_valid_token : in std_logic;
rx_valid_handsh : in std_logic;
rx_valid_packet : in std_logic;
rx_error : in std_logic;
-- I/O pins to TX
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
tx_send_token : out std_logic;
tx_send_handsh : out std_logic;
tx_send_data : out std_logic;
tx_length : out unsigned(10 downto 0);
tx_no_data : out std_logic;
tx_chirp_enable : out std_logic;
tx_chirp_level : out std_logic;
tx_chirp_end : out std_logic;
tx_chirp_start : out std_logic;
tx_ack : in std_logic );
end entity;
architecture gideon of usb_io_bank is
signal pulse_in : std_logic_vector(15 downto 0) := (others => '0');
signal pulse_out : std_logic_vector(15 downto 0) := (others => '0');
signal latched : std_logic_vector(15 downto 0) := (others => '0');
signal level_out : std_logic_vector(15 downto 0) := (others => '0');
signal frame_div : integer range 0 to 65535;
signal frame_cnt : unsigned(13 downto 0) := (others => '0');
signal stall_i : std_logic := '0';
signal ulpi_access : std_logic;
signal tx_chirp_start_i : std_logic;
signal tx_chirp_end_i : std_logic;
signal filter_cnt : unsigned(7 downto 0);
signal filter_st1 : std_logic;
signal reset_filter : std_logic;
begin
pulse_in(0) <= rx_error;
pulse_in(1) <= rx_valid_token;
pulse_in(2) <= rx_valid_handsh;
pulse_in(3) <= rx_valid_packet;
pulse_in(4) <= rx_valid_packet or rx_valid_handsh or rx_valid_token or rx_error;
pulse_in(7) <= tx_ack; -- tx ack resets lower half of output pulses
tx_no_data <= level_out(0);
tx_send_token <= pulse_out(0);
tx_send_handsh <= pulse_out(1);
tx_send_data <= pulse_out(2);
tx_chirp_level <= level_out(5);
tx_chirp_start <= tx_chirp_start_i;
tx_chirp_end <= tx_chirp_end_i;
tx_chirp_start_i <= pulse_out(8);
tx_chirp_end_i <= pulse_out(9);
reset_filter <= pulse_out(14);
pulse_in(14) <= filter_st1;
pulse_in(13) <= '1' when (status(5 downto 4) = "10") else '0';
process(clock)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
if rising_edge(clock) then
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
if tx_ack = '1' then
pulse_out(7 downto 0) <= (others => '0');
end if;
pulse_out(15 downto 8) <= X"00";
pulse_in(15) <= '0';
if frame_div = 0 then
frame_div <= 7499; -- microframes
pulse_in(15) <= '1';
frame_cnt <= frame_cnt + 1;
else
frame_div <= frame_div - 1;
end if;
if tx_chirp_start_i = '1' then
tx_chirp_enable <= '1';
elsif tx_chirp_end_i = '1' then
tx_chirp_enable <= '0';
end if;
filter_st1 <= '0';
if reset_filter = '1' then
filter_cnt <= (others => '0');
elsif status(1) = '0' then
filter_cnt <= (others => '0');
else
filter_cnt <= filter_cnt + 1;
if filter_cnt = 255 and latched(14)='0' then
filter_st1 <= '1';
end if;
end if;
if reg_ack='1' then
reg_write <= '0';
reg_read <= '0';
stall_i <= '0';
end if;
if io_write='1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
case adhi is
when X"0" =>
case adlo(3 downto 0) is
when X"0" =>
tx_pid <= io_wdata(tx_pid'range);
when X"1" =>
tx_token <= io_wdata(tx_token'range);
when X"2" =>
tx_length <= unsigned(io_wdata(tx_length'range));
when others =>
null;
end case;
when X"1" =>
pulse_out(to_integer(adlo)) <= '1';
when X"2" =>
latched(to_integer(adlo)) <= '0';
when X"4" =>
level_out(to_integer(adlo)) <= '0';
when X"5" =>
level_out(to_integer(adlo)) <= '1';
when X"C"|X"D"|X"E"|X"F" =>
reg_wdata <= io_wdata(7 downto 0);
reg_write <= '1';
stall_i <= '1';
when others =>
null;
end case;
end if;
if io_read = '1' then
reg_addr <= std_logic_vector(io_addr(5 downto 0));
if io_addr(7 downto 6) = "10" then
reg_read <= '1';
stall_i <= '1';
end if;
end if;
for i in latched'range loop
if pulse_in(i)='1' then
latched(i) <= '1';
end if;
end loop;
if reset='1' then
tx_pid <= (others => '0');
tx_token <= (others => '0');
tx_length <= (others => '0');
latched <= (others => '0');
level_out <= (others => '0');
reg_read <= '0';
reg_write <= '0';
stall_i <= '0';
tx_chirp_enable <= '0';
end if;
end if;
end process;
ulpi_access <= io_addr(7);
stall <= ((stall_i or io_read or io_write) and ulpi_access) and not reg_ack; -- stall right away, and continue right away also when the data is returned
process(latched, level_out, rx_pid, rx_token, reg_rdata, io_addr)
variable adlo : unsigned(3 downto 0);
variable adhi : unsigned(7 downto 4);
begin
io_rdata <= (others => '0');
adlo := io_addr(3 downto 0);
adhi := io_addr(7 downto 4);
case adhi is
when X"2" =>
io_rdata(15) <= latched(to_integer(adlo));
when X"3" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= X"000" & rx_pid;
when X"1" =>
io_rdata <= "00000" & rx_token;
when X"2" =>
io_rdata <= X"00" & status;
when X"3" =>
io_rdata <= "00000" & std_logic_vector(transferred);
when others =>
null;
end case;
when X"6" =>
case adlo(3 downto 0) is
when X"0" =>
io_rdata <= "00000" & std_logic_vector(frame_cnt(13 downto 3));
when others =>
null;
end case;
when X"7" =>
io_rdata(15) <= mem_ready;
when X"8"|X"9"|X"A"|X"B" =>
io_rdata <= X"00" & reg_rdata;
when others =>
null;
end case;
end process;
end architecture;
| gpl-3.0 | 3449d6e9ef0cf2fedf2d11f239465ef4 | 0.440041 | 3.670613 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/rom/example_design/rom_prod.vhd | 1 | 9,871 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: rom_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : rom.mif
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rom_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END rom_prod;
ARCHITECTURE xilinx OF rom_prod IS
COMPONENT rom_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : rom_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| mit | 3c229da45d753cdc95b83bf37b4b715f | 0.493162 | 3.830423 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op988_4.vhdl | 1 | 5,741 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net8,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 988ee518a3fb87eeda90cf9f7c79c711 | 0.574987 | 3.106602 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/6502/vhdl_source/shifter.vhd | 3 | 1,946 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity shifter is
port (
operation : in std_logic_vector(2 downto 0);
enable : in std_logic := '1'; -- instruction(1)
c_in : in std_logic;
n_in : in std_logic;
z_in : in std_logic;
data_in : in std_logic_vector(7 downto 0);
c_out : out std_logic;
n_out : out std_logic;
z_out : out std_logic;
data_out : out std_logic_vector(7 downto 0) := X"00");
end shifter;
architecture gideon of shifter is
signal data_out_i : std_logic_vector(7 downto 0) := X"00";
signal zero : std_logic := '0';
signal oper4 : std_logic_vector(3 downto 0) := X"0";
begin
-- ASL $nn ROL $nn LSR $nn ROR $nn STX $nn LDX $nn DEC $nn INC $nn
with operation select data_out_i <=
data_in(6 downto 0) & '0' when "000",
data_in(6 downto 0) & c_in when "001",
'0' & data_in(7 downto 1) when "010",
c_in & data_in(7 downto 1) when "011",
data_in - 1 when "110",
data_in + 1 when "111",
data_in when others;
zero <= '1' when data_out_i = X"00" else '0';
oper4 <= enable & operation;
with oper4 select c_out <=
data_in(7) when "1000" | "1001",
data_in(0) when "1010" | "1011",
c_in when others;
with oper4 select z_out <=
zero when "1000" | "1001" | "1010" | "1011" | "1101" | "1110" | "1111",
z_in when others;
with oper4 select n_out <=
data_out_i(7) when "1000" | "1001" | "1010" | "1011" | "1101" | "1110" | "1111",
n_in when others;
data_out <= data_out_i when enable='1' else data_in;
end gideon; | gpl-3.0 | 156da6a5c448031e043442008c6e9a2d | 0.477903 | 3.200658 | false | false | false | false |
tirfil/VhdI2CSlave | vhdl/i2cdemo.vhd | 1 | 2,478 | --###############################
--# Project Name : I2C Slave
--# File : i2cdemo.vhd
--# Project : ic2 slave + Single port RAM 256 * 8 (ALTERA compatible)
--# Engineer : Philippe THIRION
--# Modification History
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
entity I2CDEMO is
port(
MCLK : in std_logic;
nRST : in std_logic;
SCL : inout std_logic;
SDA : inout std_logic
);
end I2CDEMO;
architecture rtl of I2CDEMO is
-- COMPONENTS --
component I2CSLAVE
generic( DEVICE: std_logic_vector(7 downto 0));
port(
MCLK : in std_logic;
nRST : in std_logic;
SDA_IN : in std_logic;
SCL_IN : in std_logic;
SDA_OUT : out std_logic;
SCL_OUT : out std_logic;
ADDRESS : out std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
WR : out std_logic;
RD : out std_logic
);
end component;
component sp256x8
port(
address : in std_logic_vector(7 downto 0);
clock : in std_logic;
data : in std_logic_vector(7 downto 0);
wren : in std_logic;
q : out std_logic_vector(7 downto 0)
);
end component;
-- SIGNALS --
signal SDA_IN : std_logic;
signal SCL_IN : std_logic;
signal SDA_OUT : std_logic;
signal SCL_OUT : std_logic;
signal ADDRESS : std_logic_vector(7 downto 0);
signal DATA_OUT : std_logic_vector(7 downto 0);
signal DATA_IN : std_logic_vector(7 downto 0);
signal WR : std_logic;
signal RD : std_logic;
signal q : std_logic_vector(7 downto 0);
signal BUFFER8 : std_logic_vector(7 downto 0);
begin
-- PORT MAP --
I_RAM : sp256x8
port map (
address => ADDRESS,
clock => MCLK,
data => DATA_OUT,
wren => WR,
q => q
);
I_I2CITF : I2CSLAVE
generic map (DEVICE => x"38")
port map (
MCLK => MCLK,
nRST => nRST,
SDA_IN => SDA_IN,
SCL_IN => SCL_IN,
SDA_OUT => SDA_OUT,
SCL_OUT => SCL_OUT,
ADDRESS => ADDRESS,
DATA_OUT => DATA_OUT,
DATA_IN => DATA_IN,
WR => WR,
RD => RD
);
B8 : process(MCLK,nRST)
begin
if (nRST = '0') then
BUFFER8 <= (others => '0');
elsif (MCLK'event and MCLK='1') then
if (RD = '1') then
BUFFER8 <= q;
end if;
end if;
end process B8;
DATA_IN <= BUFFER8;
-- open drain PAD pull up 1.5K needed
SCL <= 'Z' when SCL_OUT='1' else '0';
SCL_IN <= to_UX01(SCL);
SDA <= 'Z' when SDA_OUT='1' else '0';
SDA_IN <= to_UX01(SDA);
end rtl;
| gpl-3.0 | b705c780399127c45249fea463e8c9f0 | 0.58071 | 2.475524 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_source/c1541_drive.vhd | 4 | 10,338 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity c1541_drive is
generic (
g_audio_tag : std_logic_vector(7 downto 0) := X"01";
g_floppy_tag : std_logic_vector(7 downto 0) := X"02";
g_cpu_tag : std_logic_vector(7 downto 0) := X"04";
g_audio : boolean := true;
g_audio_div : integer := 2222; -- 22500 Hz (from 50 MHz)
g_audio_base : unsigned(27 downto 0) := X"0030000";
g_ram_base : unsigned(27 downto 0) := X"0060000" );
port (
clock : in std_logic;
reset : in std_logic;
drive_stop : in std_logic;
-- slave port on io bus
io_req : in t_io_req;
io_resp : out t_io_resp;
-- master port on memory bus
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
-- serial bus pins
atn_o : out std_logic; -- open drain
atn_i : in std_logic;
clk_o : out std_logic; -- open drain
clk_i : in std_logic;
data_o : out std_logic; -- open drain
data_i : in std_logic;
iec_reset_n : in std_logic;
c64_reset_n : in std_logic;
-- LED
act_led_n : out std_logic;
motor_led_n : out std_logic;
dirty_led_n : out std_logic;
-- audio out
audio_sample : out signed(12 downto 0) );
end c1541_drive;
architecture structural of c1541_drive is
signal cpu_clock_en : std_logic;
signal drv_clock_en : std_logic;
signal iec_reset_o : std_logic;
signal param_write : std_logic;
signal param_ram_en : std_logic;
signal param_addr : std_logic_vector(10 downto 0);
signal param_wdata : std_logic_vector(7 downto 0);
signal param_rdata : std_logic_vector(7 downto 0);
signal do_track_out : std_logic;
signal do_track_in : std_logic;
signal do_head_bang : std_logic;
signal en_hum : std_logic;
signal en_slip : std_logic;
signal use_c64_reset : std_logic;
signal floppy_inserted : std_logic := '0';
signal bank_is_ram : std_logic_vector(7 downto 0);
signal power : std_logic;
signal motor_on : std_logic;
signal mode : std_logic;
signal step : std_logic_vector(1 downto 0) := "00";
signal soe : std_logic;
signal rate_ctrl : std_logic_vector(1 downto 0);
signal byte_ready : std_logic;
signal sync : std_logic;
signal track : std_logic_vector(6 downto 0);
signal track_is_0 : std_logic;
signal drive_address : std_logic_vector(1 downto 0) := "00";
signal write_prot_n : std_logic := '1';
signal drv_reset : std_logic := '1';
signal disk_rdata : std_logic_vector(7 downto 0);
signal disk_wdata : std_logic_vector(7 downto 0);
signal drive_stop_i : std_logic;
signal stop_on_freeze : std_logic;
signal mem_req_cpu : t_mem_req;
signal mem_resp_cpu : t_mem_resp;
signal mem_req_flop : t_mem_req;
signal mem_resp_flop : t_mem_resp;
signal mem_req_snd : t_mem_req := c_mem_req_init;
signal mem_resp_snd : t_mem_resp;
signal count : unsigned(7 downto 0) := X"00";
signal led_intensity : unsigned(1 downto 0);
begin
drive_stop_i <= drive_stop and stop_on_freeze;
i_timing: entity work.c1541_timing
port map (
clock => clock,
reset => reset,
use_c64_reset=> use_c64_reset,
c64_reset_n => c64_reset_n,
iec_reset_n => iec_reset_n,
iec_reset_o => iec_reset_o,
drive_stop => drive_stop_i,
drv_clock_en => drv_clock_en, -- 1/12.5 (4 MHz)
cpu_clock_en => cpu_clock_en ); -- 1/50 (1 MHz)
i_cpu: entity work.cpu_part_1541
generic map (
g_tag => g_cpu_tag,
g_ram_base => g_ram_base )
port map (
clock => clock,
clock_en => cpu_clock_en,
reset => drv_reset,
-- serial bus pins
atn_o => atn_o, -- open drain
atn_i => atn_i,
clk_o => clk_o, -- open drain
clk_i => clk_i,
data_o => data_o, -- open drain
data_i => data_i,
-- trace data
cpu_pc => open, --cpu_pc_1541,
-- configuration
bank_is_ram => bank_is_ram,
-- memory interface
mem_req => mem_req_cpu,
mem_resp => mem_resp_cpu,
-- drive pins
power => power,
drive_address => drive_address,
write_prot_n => write_prot_n,
motor_on => motor_on,
mode => mode,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
track_is_0 => track_is_0,
drv_rdata => disk_rdata,
drv_wdata => disk_wdata,
-- other
act_led => act_led_n );
i_flop: entity work.floppy
generic map (
g_tag => g_floppy_tag )
port map (
sys_clock => clock,
drv_clock_en => drv_clock_en, -- resulting in 4 MHz
drv_reset => drv_reset,
-- signals from MOS 6522 VIA
motor_on => motor_on,
mode => mode,
write_prot_n => write_prot_n,
step => step,
soe => soe,
rate_ctrl => rate_ctrl,
byte_ready => byte_ready,
sync => sync,
read_data => disk_rdata,
write_data => disk_wdata,
track => track,
track_is_0 => track_is_0,
---
cpu_write => param_write,
cpu_ram_en => param_ram_en,
cpu_addr => param_addr,
cpu_wdata => param_wdata,
cpu_rdata => param_rdata,
---
floppy_inserted => floppy_inserted,
do_track_out => do_track_out,
do_track_in => do_track_in,
do_head_bang => do_head_bang,
en_hum => en_hum,
en_slip => en_slip,
---
mem_req => mem_req_flop,
mem_resp => mem_resp_flop );
r_snd: if g_audio generate
i_snd: entity work.floppy_sound
generic map (
g_tag => g_audio_tag,
rate_div => g_audio_div, -- 22050 Hz
sound_base => g_audio_base(27 downto 16),
motor_hum_addr => X"0000",
flop_slip_addr => X"1200",
track_in_addr => X"2400",
track_out_addr => X"2C00",
head_bang_addr => X"3480",
motor_len => 4410,
track_in_len => X"0800", -- ~100 ms;
track_out_len => X"0880", -- ~100 ms;
head_bang_len => X"0880" ) -- ~100 ms;
port map (
clock => clock, -- 50 MHz
reset => drv_reset,
do_trk_out => do_track_out,
do_trk_in => do_track_in,
do_head_bang => do_head_bang,
en_hum => en_hum,
en_slip => en_slip,
-- memory interface
mem_req => mem_req_snd,
mem_resp => mem_resp_snd,
-- audio
sample_out => audio_sample );
end generate;
i_regs: entity work.drive_registers
generic map (
g_audio_base => g_audio_base,
g_ram_base => g_ram_base )
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
param_write => param_write,
param_ram_en => param_ram_en,
param_addr => param_addr,
param_wdata => param_wdata,
param_rdata => param_rdata,
iec_reset_o => iec_reset_o,
use_c64_reset => use_c64_reset,
power => power,
drv_reset => drv_reset,
drive_address => drive_address,
floppy_inserted => floppy_inserted,
write_prot_n => write_prot_n,
bank_is_ram => bank_is_ram,
dirty_led_n => dirty_led_n,
stop_on_freeze => stop_on_freeze,
track => track,
mode => mode,
motor_on => motor_on );
-- memory arbitration
i_arb: entity work.mem_bus_arbiter_pri
generic map (
g_ports => 3,
g_registered => false )
port map (
clock => clock,
reset => reset,
reqs(0) => mem_req_flop,
reqs(1) => mem_req_cpu,
reqs(2) => mem_req_snd,
resps(0) => mem_resp_flop,
resps(1) => mem_resp_cpu,
resps(2) => mem_resp_snd,
req => mem_req,
resp => mem_resp );
process(clock)
variable led_int : unsigned(7 downto 0);
begin
if rising_edge(clock) then
count <= count + 1;
if count=X"00" then
motor_led_n <= '0'; -- on
end if;
led_int := led_intensity & led_intensity & led_intensity & led_intensity;
if count=led_int then
motor_led_n <= '1'; -- off
end if;
end if;
end process;
led_intensity <= "00" when power='0' else
"01" when floppy_inserted='0' else
"10" when motor_on='0' else
"11";
end architecture;
| gpl-3.0 | fb38951e5323a47aeac2d33c29d73fd0 | 0.449603 | 3.567288 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op336_4.vhdl | 1 | 5,276 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | fe12f35608bf200adee431e8353a0574 | 0.575815 | 3.125592 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op944_2.vhdl | 2 | 3,738 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => out1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => gnd
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net3
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net3,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 61215076da66df6b18230c0450a55960 | 0.590423 | 3.310895 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v6.vhd | 5 | 19,323 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 2), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v6 is
generic (
g_simulation : boolean := false;
g_read_fifo : boolean := false;
q_tcko_data : time := 100 ps;
A_Width : integer := 13;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_2x : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic := '0';
is_idle : out std_logic;
-- clk_4x : in std_logic := '0';
-- dummy : out std_logic;
req : in t_mem_burst_16_req;
resp : out t_mem_burst_16_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic := '0';
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_BA : out std_logic_vector(1 downto 0);
SDRAM_A : out std_logic_vector(A_Width-1 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v6;
architecture Gideon of ext_mem_ctrl_v6 is
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", "010" ), -- auto precharge
( X"002B", "000" ), -- mode register, burstlen=8, writelen=8, CAS lat = 2, interleaved
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ), -- auto refresh
( X"0000", "100" ) );
type t_ints is array(natural range <>) of integer;
constant c_delays : t_ints(0 to 15) := (
2, 4, 2, 3, -- R2R (other row&other bank, other row, other bank, same row+bank)
4, 5, 4, 5, -- R2W
2, 5, 2, 3, -- W2R
2, 4, 2, 3 );-- W2W
type t_state is (boot, init, idle, sd_cas );
signal state : t_state;
signal sdram_d_o : std_logic_vector(SDRAM_DQ'range) := (others => '1');
signal sdram_d_t : std_logic_vector(SDRAM_DQ'range) := (others => '1');
signal wdata_tri : std_logic_vector(8 downto 0) := (others => '1');
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal mem_a_i : std_logic_vector(SDRAM_A'range) := (others => '0');
signal mem_ba_i : std_logic_vector(SDRAM_BA'range) := (others => '0');
signal cs_n_i : std_logic := '1';
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal do_refresh_d : std_logic := '0';
signal trigger_refresh : std_logic := '0';
signal not_clock : std_logic;
signal not_clock_2x : std_logic;
signal rdata_lo : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_hi : std_logic_vector(7 downto 0) := (others => '0');
signal rdata_hi_d : std_logic_vector(7 downto 0) := (others => '0');
signal wdata : std_logic_vector(17 downto 0) := (others => '0');
signal wdata_i : std_logic_vector(17 downto 0) := (others => '0');
signal wdata_av : std_logic;
signal fifo_wdata_in : std_logic_vector(17 downto 0);
signal wdqm : std_logic_vector(1 downto 0);
signal dqm_override : std_logic := '1';
-- signal refr_delay : integer range 0 to 7;
signal next_delay : integer range 0 to 7;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal rack : std_logic;
signal dack : std_logic_vector(5 downto 0) := "000000";
signal burst_start : std_logic_vector(5 downto 0) := "000000";
signal dnext : std_logic_vector(3 downto 0) := "0000";
signal last_bank : std_logic_vector(1 downto 0) := "10";
signal addr_bank : std_logic_vector(1 downto 0);
signal same_bank : std_logic;
signal last_row : std_logic_vector(12 downto 0) := "0101011010101";
signal addr_row : std_logic_vector(12 downto 0);
signal same_row : std_logic;
signal addr_column : std_logic_vector(9 downto 0);
signal next_activate : std_logic;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of SDRAM_CKE : signal is "false";
attribute iob of SDRAM_A : signal is "true";
attribute iob of SDRAM_BA : signal is "true";
attribute iob of SDRAM_RASn : signal is "true";
attribute iob of SDRAM_CASn : signal is "true";
attribute iob of SDRAM_WEn : signal is "true";
constant c_address_width : integer := req.address'length;
constant c_data_width : integer := req.data'length;
signal cmd_fifo_data_in : std_logic_vector(c_address_width downto 0);
signal cmd_fifo_data_out : std_logic_vector(c_address_width downto 0);
signal rwn_fifo : std_logic;
signal rwn_i : std_logic := '1';
signal tag_fifo : std_logic_vector(7 downto 0);
signal address_fifo : std_logic_vector(c_address_width-1 downto 0);
signal cmd_af : std_logic;
signal cmd_av : std_logic;
signal rdata_af : std_logic := '0'; -- forced low for when there is no fifo
signal push_cmd : std_logic;
signal push_read_cmd : std_logic;
signal crazy_index_slv : std_logic_vector(3 downto 0);
signal crazy_index : integer range 0 to 15;
signal sampled_dq : std_logic_vector(7 downto 0);
begin
is_idle <= '1' when state = idle else '0';
req_i <= cmd_av and not do_refresh_d;
push_cmd <= req.request and not cmd_af;
push_read_cmd <= push_cmd and req.read_writen;
resp.ready <= not cmd_af;
cmd_fifo_data_in <= req.read_writen & std_logic_vector(req.address);
address_fifo <= cmd_fifo_data_out(address_fifo'range);
rwn_fifo <= cmd_fifo_data_out(address_fifo'length);
addr_bank <= address_fifo(14 downto 13);
addr_row <= address_fifo(24 downto 15) & address_fifo(12 downto 10);
addr_column <= address_fifo( 9 downto 0);
i_command_fifo: entity work.srl_fifo
generic map (
Width => c_address_width + 1,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => rack,
PutElement => push_cmd,
FlushFifo => '0',
DataIn => cmd_fifo_data_in,
DataOut => cmd_fifo_data_out,
SpaceInFifo => open,
AlmostFull => cmd_af,
DataInFifo => cmd_av );
i_tag_fifo: entity work.srl_fifo
generic map (
Width => 8,
Depth => 15,
Threshold => 3)
port map (
clock => clock,
reset => reset,
GetElement => burst_start(1),
PutElement => push_read_cmd,
FlushFifo => '0',
DataIn => req.request_tag,
DataOut => tag_fifo,
SpaceInFifo => open,
AlmostFull => open,
DataInFifo => open );
r_read_fifo: if g_read_fifo generate
i_read_fifo: entity work.srl_fifo
generic map (
Width => c_data_width,
Depth => 15,
Threshold => 6 )
port map (
clock => clock,
reset => reset,
GetElement => req.data_pop,
PutElement => dack(0),
FlushFifo => '0',
DataIn(15 downto 8) => rdata_lo,
DataIn(7 downto 0) => rdata_hi,
DataOut => resp.data,
SpaceInFifo => open,
AlmostFull => rdata_af,
DataInFifo => resp.rdata_av );
end generate;
r_read_direct: if not g_read_fifo generate
resp.data <= rdata_lo & rdata_hi;
resp.rdata_av <= dack(0);
end generate;
fifo_wdata_in <= req.byte_en & req.data;
wdqm <= (others => '1') when dqm_override='1' else
(others => '0') when dnext(0)='0' else not wdata(17 downto 16);
i_write_fifo: entity work.SRL_fifo
generic map (
Width => (c_data_width*9)/8,
Depth => 15,
Threshold => 6 )
port map (
clock => clock,
reset => reset,
GetElement => dnext(0),
PutElement => req.data_push,
FlushFifo => '0',
DataIn => fifo_wdata_in,
DataOut => wdata_i,
SpaceInFifo => open,
AlmostFull => resp.wdata_full,
DataInFifo => wdata_av );
wdata <= wdata_i after 1 ns;
same_row <= '1' when addr_row = last_row else '0';
same_bank <= '1' when addr_bank = last_bank else '0';
crazy_index_slv <= not rwn_i & not rwn_fifo & same_row & same_bank;
crazy_index <= to_integer(unsigned(crazy_index_slv));
trigger_refresh <= do_refresh_d and not (inhibit_d or inhibit);
process(clock)
procedure send_refresh_cmd is
begin
if next_delay = 0 then
do_refresh <= '0';
do_refresh_d <= '0';
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
next_delay <= 3;
end if;
end procedure;
procedure accept_req is
begin
rwn_i <= rwn_fifo;
col_addr <= addr_column;
last_bank <= addr_bank;
last_row <= addr_row;
mem_a_i(addr_row'range) <= addr_row;
mem_ba_i <= addr_bank;
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
delay <= 0;
state <= sd_cas;
end procedure;
procedure issue_read_or_write is
begin
mem_a_i(9 downto 0) <= col_addr;
do_refresh_d <= do_refresh;
if req_i='0' or do_refresh='1' then
if rwn_i='0' then
next_delay <= 5;
else
next_delay <= 4;
end if;
mem_a_i(10) <= '1'; -- auto precharge
next_activate <= '1';
else
next_delay <= c_delays(crazy_index);
mem_a_i(10) <= not (same_row and same_bank); -- do not AP when we'll continue in same row
next_activate <= not (same_row and same_bank); -- only activate next time if we also AP.
end if;
if delay=0 then
if rwn_i='0' then
if wdata_av='1' then
wdata_tri(7 downto 0) <= (others => '0') after 1 ns;
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '0';
dnext <= "1111" after 1 ns;
state <= idle;
end if;
else
if rdata_af='0' then
cs_n_i <= '0' after 1 ns;
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1';
dack(dack'high downto dack'high-3) <= (others => '1');
burst_start(2) <= '1';
state <= idle;
end if;
end if;
end if;
end procedure;
begin
if rising_edge(clock) then
inhibit_d <= inhibit;
rdata_hi_d <= rdata_hi;
cs_n_i <= '1' after 1 ns;
SDRAM_CKE <= enable_sdram;
SDRAM_RASn <= '1';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1';
if burst_start(1)='1' then
resp.data_tag <= tag_fifo;
end if;
if next_delay /= 0 then
next_delay <= next_delay - 1;
end if;
if delay /= 0 then
delay <= delay - 1;
end if;
wdata_tri <= "11" & wdata_tri(wdata_tri'high downto 2) after 1 ns;
dack <= '0' & dack(dack'high downto 1);
burst_start <= '0' & burst_start(burst_start'high downto 1);
dnext <= '0' & dnext(dnext'high downto 1) after 1 ns;
case state is
when boot =>
enable_sdram <= '1';
if g_simulation then
state <= init;
elsif refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
mem_ba_i <= (others => '0'); -- for DDR and such, maybe the upper 2/3 bits
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if next_delay = 0 then
next_delay <= 7;
cs_n_i <= '0' after 1 ns;
if init_cnt = c_init_array'high then
state <= idle;
dqm_override <= '0';
else
init_cnt <= init_cnt + 1;
end if;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if trigger_refresh='1' then
send_refresh_cmd;
elsif inhibit='0' then
if req_i='1' then
if next_activate='1' and next_delay=0 then
accept_req;
elsif next_activate='0' and next_delay=1 then
rwn_i <= rwn_fifo;
col_addr <= addr_column;
state <= sd_cas;
end if;
else
do_refresh_d <= do_refresh;
end if;
end if;
when sd_cas =>
issue_read_or_write;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
resp.data_tag <= (others => '0');
dqm_override <= '1';
state <= boot;
wdata_tri <= (others => '0');
delay <= 0;
next_delay <= 0;
do_refresh <= '0';
do_refresh_d <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
next_activate <= '1';
rwn_i <= '1';
end if;
end if;
end process;
-- Generate rack; the signal that indicates that a request is going to be issued
-- and thus taken from the command fifo.
process(state, trigger_refresh, inhibit, req_i, next_delay, next_activate)
begin
rack <= '0';
case state is
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if trigger_refresh='1' then
null;
elsif inhibit='0' and req_i='1' then
if next_activate='1' and next_delay = 0 then
rack <= '1';
elsif next_activate='0' and next_delay = 1 then
rack <= '1';
end if;
end if;
when others =>
null;
end case;
end process;
SDRAM_A <= mem_a_i;
SDRAM_BA <= mem_ba_i;
not_clock_2x <= not clk_2x;
not_clock <= not clock;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_2x,
C1 => not_clock_2x,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
r_data: for i in 0 to 7 generate
i_dout: entity work.my_ioddr
port map (
pin => SDRAM_DQ(i),
clock => clock,
D0 => wdata(8+i),
D1 => wdata(i),
T0 => wdata_tri(1),
T1 => wdata_tri(0),
Q0 => rdata_hi(i),
Q1 => rdata_lo(i) );
end generate;
select_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
CE => '1',
C0 => clock,
C1 => not_clock,
D0 => '1',
D1 => cs_n_i,
Q => SDRAM_CSn,
R => '0',
S => '0' );
i_dqm_out: ODDR2
generic map (
DDR_ALIGNMENT => "NONE",
SRTYPE => "SYNC" )
port map (
Q => SDRAM_DQM,
C0 => clock,
C1 => not_clock,
CE => '1',
D0 => wdqm(1),
D1 => wdqm(0),
R => '0',
S => '0' );
end Gideon;
| gpl-3.0 | 6e1798a771fef5cac8333868fce70b8f | 0.45583 | 3.742592 | false | false | false | false |
multiple1902/xjtu_comp-org-lab | modules/decoder/decoder.vhdl | 1 | 1,478 | -- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
entity decoder is
port (op : in std_logic_vector(3 downto 0);
clk : in std_logic;
result : out std_logic_vector(15 downto 0) -- no semicolon here!
);
end decoder;
architecture behv of decoder is
begin
process(op)
begin
case op is
when "0000" => result <= "0000000000000001";
when "0001" => result <= "0000000000000010";
when "0010" => result <= "0000000000000100";
when "0011" => result <= "0000000000001000";
when "0100" => result <= "0000000000010000";
when "0101" => result <= "0000000000100000";
when "0110" => result <= "0000000001000000";
-- unused
-- when "0111" => result <= "0000000010000000";
when "1000" => result <= "0000000100000000";
when "1001" => result <= "0000001000000000";
when "1010" => result <= "0000010000000000";
when "1011" => result <= "0000100000000000";
-- unused
-- when "1100" => result <= "0001000000000000";
-- when "1101" => result <= "0010000000000000";
-- when "1110" => result <= "0100000000000000";
-- when "1111" => result <= "1000000000000000";
when others =>
result <= "0000000000000000";
end case;
end process;
end behv;
| gpl-3.0 | 4affe47a66fd199afea14e1557c16c4a | 0.547361 | 4.478788 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sigma_delta_dac/vhdl_sim/sine_osc_tb.vhd | 5 | 931 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sine_osc_tb is
end sine_osc_tb;
architecture tb of sine_osc_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal sine : signed(15 downto 0);
signal cosine : signed(15 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
osc: entity work.sine_osc
port map (
clock => clock,
reset => reset,
sine => sine,
cosine => cosine );
process
variable n: time;
variable p: integer;
begin
wait until reset='0';
n := now;
while true loop
wait until sine(15)='1';
p := (now - n) / 20 ns;
n := now;
report "Period: " & integer'image(p) & " samples" severity note;
end loop;
end process;
end tb; | gpl-3.0 | 1926125a646dfdd2b65957511b5126a8 | 0.514501 | 3.724 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_source/host_sequencer.vhd | 1 | 16,329 | -------------------------------------------------------------------------------
-- Title : host_sequencer
-- Author : Gideon Zweijtzer
-------------------------------------------------------------------------------
-- Description: This block generates the traffic on the downstream USB port.
-- This block has knowledge about the speeds, the USB frames,
-- and generates traffic within the right time within the frame.
-- The data interface of this block is a BRAM interface. This
-- block implements the three-time retry as well.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_pkg.all;
use work.usb_cmd_pkg.all;
entity host_sequencer is
generic (
g_buffer_depth_bits : natural := 11 ); -- 2K
port (
clock : in std_logic;
reset : in std_logic;
-- Access to buffer memory
buf_address : out unsigned(g_buffer_depth_bits-1 downto 0);
buf_en : out std_logic;
buf_we : out std_logic;
buf_rdata : in std_logic_vector(7 downto 0);
buf_wdata : out std_logic_vector(7 downto 0);
-- mode selection
sof_enable : in std_logic;
sof_tick : out std_logic;
speed : in std_logic_vector(1 downto 0);
frame_count : out unsigned(15 downto 0);
-- low level command interface
usb_cmd_req : in t_usb_cmd_req;
usb_cmd_resp : out t_usb_cmd_resp;
-- I/O to interface block
usb_rx : in t_usb_rx;
usb_tx_req : out t_usb_tx_req;
usb_tx_resp : in t_usb_tx_resp );
end entity;
architecture rtl of host_sequencer is
-- length identifiers to ram address counters
signal tx_length : unsigned(9 downto 0);
signal tx_no_data : std_logic;
signal receive_en : std_logic := '0';
signal rx_length : unsigned(9 downto 0);
signal rx_no_data : std_logic;
signal send_packet_cmd : std_logic;
signal usb_tx_req_i : t_usb_tx_req;
signal valid_packet_received : std_logic;
signal data_toggle_received : std_logic := '0';
signal data_transmission_done : std_logic := '0';
begin
b_bram_control: block
signal buffer_addr_i : unsigned(9 downto 0) := (others => '1'); -- was undefined
type t_state is (idle, prefetch, transmit_msg, wait_tx_done);
signal state : t_state;
signal transmit_en : std_logic := '0';
signal tx_last_i : std_logic;
signal tx_data_valid : std_logic;
signal tx_send_packet : std_logic;
signal buffer_index : unsigned(1 downto 0);
begin
buffer_index <= usb_cmd_req.buffer_index;
buf_address <= buffer_index & buffer_addr_i(8 downto 0);
buf_we <= usb_rx.data_valid and receive_en;
buf_wdata <= usb_rx.data;
buf_en <= receive_en or transmit_en;
transmit_en <= '1' when (state = prefetch) or
((state = transmit_msg) and (usb_tx_resp.data_wait='0'))
else '0';
tx_data_valid <= '1' when (state = transmit_msg) and (usb_tx_resp.data_wait='0')
else '0';
tx_last_i <= '1' when (buffer_addr_i = tx_length) else '0';
process(clock)
begin
if rising_edge(clock) then
if usb_rx.data_start = '1' or send_packet_cmd = '1' then
buffer_addr_i <= (others => '0');
rx_no_data <= '1';
elsif (receive_en = '1' and usb_rx.data_valid = '1') or
((transmit_en = '1') and not (tx_last_i='1' and tx_data_valid='1')) then
buffer_addr_i <= buffer_addr_i + 1;
rx_no_data <= '0';
end if;
valid_packet_received <= '0';
data_transmission_done <= '0';
if usb_rx.valid_packet = '1' and receive_en='1' then
rx_length <= buffer_addr_i;
valid_packet_received <= '1';
data_toggle_received <= get_togglebit(usb_rx.pid);
end if;
case state is
when idle =>
if send_packet_cmd = '1' then
state <= prefetch;
end if;
when prefetch =>
tx_send_packet <= '1';
state <= transmit_msg;
when transmit_msg =>
if tx_send_packet = '0' and tx_no_data = '1' then
state <= wait_tx_done;
elsif tx_last_i = '1' and tx_data_valid = '1' then
state <= wait_tx_done;
end if;
when wait_tx_done =>
if usb_tx_resp.busy = '0' then
data_transmission_done <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if usb_tx_resp.request_ack = '1' then
tx_send_packet <= '0';
end if;
if reset='1' then
state <= idle;
buffer_addr_i <= (others => '0');
tx_send_packet <= '0';
end if;
end if;
end process;
usb_tx_req_i.data <= buf_rdata;
usb_tx_req_i.data_valid <= tx_data_valid;
usb_tx_req_i.data_last <= tx_last_i when transmit_en='1' else '0';
usb_tx_req_i.send_packet <= tx_send_packet;
usb_tx_req_i.no_data <= tx_no_data;
end block;
usb_tx_req <= usb_tx_req_i;
b_replay: block
type t_state is (idle, wait_sof, wait_split_done, do_token, wait_token_done, do_data, wait_tx_done, wait_device_response, wait_handshake_done );
signal state : t_state;
signal timeout : std_logic;
signal start_timer : std_logic;
signal cmd_done : std_logic;
signal frame_div : integer range 0 to 8191;
signal frame_cnt : unsigned(15 downto 0) := (others => '0');
signal do_sof : std_logic;
signal sof_guard : std_logic := '0';
signal start_split_active : boolean;
signal complete_split_active : boolean;
begin
start_split_active <= (usb_cmd_req.do_split = '1') and (usb_cmd_req.split_sc = '0') and (speed = "10");
complete_split_active <= (usb_cmd_req.do_split = '1') and (usb_cmd_req.split_sc = '1') and (speed = "10");
process(clock)
begin
if rising_edge(clock) then
send_packet_cmd <= '0';
if frame_div = 800 then -- the last ~10% is unused for new transactions (test)
sof_guard <= '1';
end if;
if frame_div = 0 then
frame_div <= 7499; -- microframes
do_sof <= sof_enable;
sof_guard <= '0';
frame_cnt <= frame_cnt + 1;
else
frame_div <= frame_div - 1;
end if;
cmd_done <= '0';
sof_tick <= '0';
case state is
when idle =>
receive_en <= '0';
if do_sof='1' then
sof_tick <= '1';
do_sof <= '0';
usb_tx_req_i.pid <= c_pid_sof;
usb_tx_req_i.token.device_addr <= std_logic_vector(frame_cnt(9 downto 3));
usb_tx_req_i.token.endpoint_addr <= std_logic_vector(frame_cnt(13 downto 10));
case speed is
when "00" => -- low speed
if frame_cnt(2 downto 0) = "000" then
usb_tx_req_i.send_handsh <= '1';
state <= wait_sof;
end if;
when "01" => -- full speed
if frame_cnt(2 downto 0) = "000" then
usb_tx_req_i.send_token <= '1';
state <= wait_sof;
end if;
when "10" => -- high speed
usb_tx_req_i.send_token <= '1';
state <= wait_sof;
when others =>
null;
end case;
elsif sof_guard = '0' and usb_cmd_req.request = '1' and cmd_done = '0' then
-- default response
usb_cmd_resp.no_data <= '1';
usb_cmd_resp.data_length <= (others => '0');
usb_tx_req_i.split_token.e <= '0';
usb_tx_req_i.split_token.et <= usb_cmd_req.split_et;
usb_tx_req_i.split_token.sc <= usb_cmd_req.split_sc;
usb_tx_req_i.split_token.s <= usb_cmd_req.split_sp;
usb_tx_req_i.split_token.hub_address <= std_logic_vector(usb_cmd_req.split_hub_addr);
usb_tx_req_i.split_token.port_address <= "000" & std_logic_vector(usb_cmd_req.split_port_addr);
usb_tx_req_i.token.device_addr <= std_logic_vector(usb_cmd_req.device_addr);
usb_tx_req_i.token.endpoint_addr <= std_logic_vector(usb_cmd_req.endp_addr);
if usb_cmd_req.do_split = '1' then
usb_tx_req_i.pid <= c_pid_split;
usb_tx_req_i.send_split <= '1';
state <= wait_split_done;
else
state <= do_token;
end if;
end if;
when wait_sof =>
if usb_tx_resp.request_ack = '1' then
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_handsh <= '0';
usb_tx_req_i.send_split <= '0';
state <= idle;
end if;
when wait_split_done =>
if usb_tx_resp.request_ack = '1' then
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_handsh <= '0';
usb_tx_req_i.send_split <= '0';
state <= do_token;
end if;
when do_token =>
usb_tx_req_i.send_token <= '1';
state <= wait_token_done;
case usb_cmd_req.command is
when setup =>
usb_tx_req_i.pid <= c_pid_setup;
when in_request =>
usb_tx_req_i.pid <= c_pid_in;
when out_data =>
usb_tx_req_i.pid <= c_pid_out;
when others =>
usb_tx_req_i.pid <= c_pid_ping;
end case;
when wait_token_done =>
if usb_tx_resp.request_ack = '1' then
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_handsh <= '0';
usb_tx_req_i.send_split <= '0';
state <= do_data;
end if;
when do_data =>
case usb_cmd_req.command is
when setup | out_data =>
if usb_cmd_req.do_data = '1' then
send_packet_cmd <= '1';
tx_no_data <= usb_cmd_req.no_data;
tx_length <= usb_cmd_req.data_length;
if usb_cmd_req.togglebit='0' then
usb_tx_req_i.pid <= c_pid_data0;
else
usb_tx_req_i.pid <= c_pid_data1;
end if;
state <= wait_tx_done;
else
state <= wait_device_response;
end if;
when in_request =>
receive_en <= usb_cmd_req.do_data;
state <= wait_device_response;
when others =>
state <= wait_device_response;
end case;
when wait_tx_done =>
if data_transmission_done = '1' then
state <= wait_device_response;
end if;
when wait_device_response =>
usb_tx_req_i.pid <= c_pid_ack;
if usb_rx.valid_handsh = '1' then
usb_cmd_resp.result <= encode_result(usb_rx.pid);
cmd_done <= '1';
state <= idle;
elsif usb_rx.error='1' or timeout='1' then
usb_cmd_resp.result <= res_error;
cmd_done <= '1';
state <= idle;
elsif valid_packet_received = '1' then -- woohoo!
usb_cmd_resp.result <= res_data;
usb_cmd_resp.no_data <= rx_no_data;
usb_cmd_resp.data_length <= rx_length;
usb_cmd_resp.togglebit <= data_toggle_received;
-- we send an ack to the device. Thank you!
if complete_split_active and usb_cmd_req.split_et(0)='1' then
cmd_done <= '1';
state <= idle;
else
usb_tx_req_i.send_handsh <= '1';
state <= wait_handshake_done;
end if;
end if;
when wait_handshake_done =>
if usb_tx_resp.request_ack = '1' then
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_handsh <= '0';
usb_tx_req_i.send_split <= '0';
cmd_done <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
usb_tx_req_i.pid <= X"0";
usb_tx_req_i.send_token <= '0';
usb_tx_req_i.send_split <= '0';
usb_tx_req_i.send_handsh <= '0';
do_sof <= '0';
end if;
end if;
end process;
usb_cmd_resp.done <= cmd_done;
frame_count <= frame_cnt;
start_timer <= usb_tx_resp.busy or usb_rx.receiving;
i_timer: entity work.timer
generic map (
g_width => 10 )
port map (
clock => clock,
reset => reset,
start => start_timer,
start_value => to_unsigned(767, 10),
timeout => timeout );
end block;
end architecture;
| gpl-3.0 | 12b01448978334e960d8f72bdcd98345 | 0.39684 | 4.299368 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC_Ethernet.vhd | 3 | 39,343 | -------------------------------------------------------------------------------
-- Entity : openMAC_Ethernet
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the top level of openMAC.
-- It instantiates openMAC, openHUB, openFILTER and other components for the
-- MAC-layer.
--
-------------------------------------------------------------------------------
--
-- 2011-07-26 V0.01 zelenkaj First version
-- 2011-10-11 V0.02 zelenkaj ack for pkt was clocked by clk50
-- 2011-10-13 V0.03 zelenkaj changed names of instances
-- 2011-11-07 V0.04 zelenkaj added big/little endian consideration
-- minor changes in SMI core generation
-- 2011-11-28 V0.05 zelenkaj Added DMA observer
-- 2011-11-29 V0.06 zelenkaj waitrequest for mac_reg is gen. once
-- tx_off / rx_off is derived in openMAC
-- 2011-11-30 V0.07 zelenkaj Added generic for DMA observer
-- Fixed generic assignments for DMA master
-- 2011-12-02 V0.08 zelenkaj Added Dma Req Overflow
-- 2011-12-05 V0.09 zelenkaj Reduced Dma Req overflow vector
-- 2012-01-26 V0.10 zelenkaj Revised SMI to use one SMI with two phys
-- 2012-03-21 V0.20 zelenkaj redesigned endian conversion
-- 2012-04-17 V0.21 zelenkaj Added forwarding of DMA read length
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity openmac_ethernet is
generic(
genSmiIO : boolean := true;
gNumSmi : integer := 2;
gen2ndCmpTimer_g : boolean := false;
simulate : boolean := false;
dma_highadr_g : integer := 31;
m_data_width_g : integer := 16;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_fifo_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
endian_g : string := "little";
genPhyActLed_g : boolean := false;
gen_dma_observer_g : boolean := true;
useIntPktBuf_g : boolean := false;
useRxIntPktBuf_g : boolean := false;
iPktBufSize_g : integer := 1024;
iPktBufSizeLog2_g : integer := 10;
genHub_g : boolean := false;
useRmii_g : boolean := true
);
port(
clk : in std_logic;
clkx2 : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
phy0_rx_dv : in std_logic;
phy0_rx_err : in std_logic;
phy0_smi_dio_I : in std_logic;
phy1_rx_dv : in std_logic;
phy1_rx_err : in std_logic;
phy1_smi_dio_I : in std_logic;
phyMii0_rx_clk : in std_logic;
phyMii0_rx_dv : in std_logic;
phyMii0_rx_err : in std_logic;
phyMii0_tx_clk : in std_logic;
phyMii1_rx_clk : in std_logic;
phyMii1_rx_dv : in std_logic;
phyMii1_rx_err : in std_logic;
phyMii1_tx_clk : in std_logic;
phy_smi_dio_I : in std_logic;
pkt_chipselect : in std_logic;
pkt_clk : in std_logic;
pkt_read : in std_logic;
pkt_write : in std_logic;
rst : in std_logic;
s_chipselect : in std_logic;
s_read : in std_logic;
s_write : in std_logic;
t_chipselect : in std_logic;
t_read : in std_logic;
t_write : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
phy0_rx_dat : in std_logic_vector(1 downto 0);
phy1_rx_dat : in std_logic_vector(1 downto 0);
phyMii0_rx_dat : in std_logic_vector(3 downto 0);
phyMii1_rx_dat : in std_logic_vector(3 downto 0);
pkt_address : in std_logic_vector(iPktBufSizeLog2_g-3 downto 0) := (others => '0');
pkt_byteenable : in std_logic_vector(3 downto 0);
pkt_writedata : in std_logic_vector(31 downto 0);
s_address : in std_logic_vector(11 downto 0);
s_byteenable : in std_logic_vector(1 downto 0);
s_writedata : in std_logic_vector(15 downto 0);
t_address : in std_logic_vector(1 downto 0);
t_byteenable : in std_logic_vector(3 downto 0);
t_writedata : in std_logic_vector(31 downto 0);
act_led : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
mac_rx_irq : out std_logic;
mac_tx_irq : out std_logic;
phy0_rst_n : out std_logic;
phy0_smi_clk : out std_logic;
phy0_smi_dio_O : out std_logic;
phy0_smi_dio_T : out std_logic;
phy0_tx_en : out std_logic;
phy1_rst_n : out std_logic;
phy1_smi_clk : out std_logic;
phy1_smi_dio_O : out std_logic;
phy1_smi_dio_T : out std_logic;
phy1_tx_en : out std_logic;
phyMii0_tx_en : out std_logic;
phyMii1_tx_en : out std_logic;
phy_rst_n : out std_logic;
phy_smi_clk : out std_logic;
phy_smi_dio_O : out std_logic;
phy_smi_dio_T : out std_logic;
pkt_waitrequest : out std_logic;
s_irq : out std_logic;
s_waitrequest : out std_logic;
t_irq : out std_logic;
t_tog : out std_logic;
t_waitrequest : out std_logic;
m_address : out std_logic_vector(29 downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0);
phy0_tx_dat : out std_logic_vector(1 downto 0);
phy1_tx_dat : out std_logic_vector(1 downto 0);
phyMii0_tx_dat : out std_logic_vector(3 downto 0);
phyMii1_tx_dat : out std_logic_vector(3 downto 0);
pkt_readdata : out std_logic_vector(31 downto 0);
s_readdata : out std_logic_vector(15 downto 0);
t_readdata : out std_logic_vector(31 downto 0);
phy0_smi_dio : inout std_logic := '1';
phy1_smi_dio : inout std_logic := '1';
phy_smi_dio : inout std_logic := '1'
);
end openmac_ethernet;
architecture rtl of openmac_ethernet is
---- Component declarations -----
component addr_decoder
generic(
addrWidth_g : integer := 32;
baseaddr_g : integer := 4096;
highaddr_g : integer := 8191
);
port (
addr : in std_logic_vector(addrWidth_g-1 downto 0);
selin : in std_logic;
selout : out std_logic
);
end component;
component openFILTER
generic(
bypassFilter : boolean := false
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvIn : in std_logic;
RxErr : in std_logic := '0';
TxDatIn : in std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
nCheckShortFrames : in std_logic := '0';
RxDatOut : out std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
TxEnOut : out std_logic
);
end component;
component OpenHUB
generic(
Ports : integer := 3
);
port (
Clk : in std_logic;
Rst : in std_logic;
RxDat0 : in std_logic_vector(Ports downto 1);
RxDat1 : in std_logic_vector(Ports downto 1);
RxDv : in std_logic_vector(Ports downto 1);
TransmitMask : in std_logic_vector(Ports downto 1) := (others => '1');
internPort : in integer range 1 to ports := 1;
ReceivePort : out integer range 0 to ports;
TxDat0 : out std_logic_vector(Ports downto 1);
TxDat1 : out std_logic_vector(Ports downto 1);
TxEn : out std_logic_vector(Ports downto 1)
);
end component;
component OpenMAC
generic(
HighAdr : integer := 16;
Simulate : boolean := false;
Timer : boolean := false;
TxDel : boolean := false;
TxSyncOn : boolean := false
);
port (
Clk : in std_logic;
Dma_Ack : in std_logic;
Dma_Din : in std_logic_vector(15 downto 0);
Hub_Rx : in std_logic_vector(1 downto 0) := "00";
Rst : in std_logic;
S_Adr : in std_logic_vector(10 downto 1);
S_Din : in std_logic_vector(15 downto 0);
S_nBe : in std_logic_vector(1 downto 0);
Sel_Cont : in std_logic := '0';
Sel_Ram : in std_logic := '0';
rCrs_Dv : in std_logic;
rRx_Dat : in std_logic_vector(1 downto 0);
s_nWr : in std_logic := '0';
Dma_Addr : out std_logic_vector(HighAdr downto 1);
Dma_Dout : out std_logic_vector(15 downto 0);
Dma_Rd_Done : out std_logic;
Dma_Rd_Len : out std_logic_vector(11 downto 0);
Dma_Req : out std_logic;
Dma_Req_Overflow : out std_logic;
Dma_Rw : out std_logic;
Dma_Wr_Done : out std_logic;
Mac_Zeit : out std_logic_vector(31 downto 0);
S_Dout : out std_logic_vector(15 downto 0);
nRx_Int : out std_logic;
nTx_BegInt : out std_logic;
nTx_Int : out std_logic;
rTx_Dat : out std_logic_vector(1 downto 0);
rTx_En : out std_logic
);
end component;
component openMAC_cmp
generic(
gen2ndCmpTimer_g : boolean := false;
mac_time_width_g : integer := 32
);
port (
addr : in std_logic_vector(1 downto 0);
clk : in std_logic;
din : in std_logic_vector(31 downto 0);
mac_time : in std_logic_vector(mac_time_width_g-1 downto 0);
rst : in std_logic;
wr : in std_logic;
dout : out std_logic_vector(31 downto 0);
irq : out std_logic;
toggle : out std_logic
);
end component;
component openMAC_DMAmaster
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_g : integer := 32;
simulate : boolean := false;
tx_fifo_word_size_g : integer := 32
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end component;
component OpenMAC_DPRpackets
generic(
memSizeLOG2_g : integer := 10;
memSize_g : integer := 1024
);
port (
address_a : in std_logic_vector(memSizeLOG2_g-2 downto 0);
address_b : in std_logic_vector(memSizeLOG2_g-3 downto 0);
byteena_a : in std_logic_vector(1 downto 0) := (others => '1');
byteena_b : in std_logic_vector(3 downto 0) := (others => '1');
clock_a : in std_logic := '1';
clock_b : in std_logic;
data_a : in std_logic_vector(15 downto 0);
data_b : in std_logic_vector(31 downto 0);
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
wren_a : in std_logic := '0';
wren_b : in std_logic := '0';
q_a : out std_logic_vector(15 downto 0);
q_b : out std_logic_vector(31 downto 0)
);
end component;
component OpenMAC_MII
port (
Addr : in std_logic_vector(2 downto 0);
Clk : in std_logic;
Data_In : in std_logic_vector(15 downto 0);
Mii_Di : in std_logic;
Rst : in std_logic;
Sel : in std_logic;
nBe : in std_logic_vector(1 downto 0);
nWr : in std_logic;
Data_Out : out std_logic_vector(15 downto 0);
Mii_Clk : out std_logic;
Mii_Do : out std_logic;
Mii_Doe : out std_logic;
nResetOut : out std_logic
);
end component;
component OpenMAC_phyAct
generic(
iBlinkFreq_g : integer := 6
);
port (
clk : in std_logic;
rst : in std_logic;
rx_dv : in std_logic;
tx_en : in std_logic;
act_led : out std_logic
);
end component;
component req_ack
generic(
ack_delay_g : integer := 1;
zero_delay_g : boolean := false
);
port (
clk : in std_logic;
enable : in std_logic;
rst : in std_logic;
ack : out std_logic
);
end component;
component rmii2mii
port (
clk50 : in std_logic;
mRxClk : in std_logic;
mRxDat : in std_logic_vector(3 downto 0);
mRxDv : in std_logic;
mRxEr : in std_logic;
mTxClk : in std_logic;
rTxDat : in std_logic_vector(1 downto 0);
rTxEn : in std_logic;
rst : in std_logic;
mTxDat : out std_logic_vector(3 downto 0);
mTxEn : out std_logic;
rRxDat : out std_logic_vector(1 downto 0);
rRxDv : out std_logic;
rRxEr : out std_logic
);
end component;
---- Architecture declarations -----
--constants for packet dma master
constant gen_tx_fifo_c : boolean := not useIntPktBuf_g;
constant gen_rx_fifo_c : boolean := not(useIntPktBuf_g and useRxIntPktBuf_g);
constant fifo_data_width_c : integer := m_data_width_g;
constant rx_fifo_word_size_c : integer := m_rx_fifo_size_g; --set value power of 2
constant tx_fifo_word_size_c : integer := m_tx_fifo_size_g; --set value power of 2
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
---- Signal declarations used on the diagram ----
signal cmp_rd : std_logic;
signal cmp_rd_ack : std_logic;
signal cmp_wr : std_logic;
signal cmp_wr_ack : std_logic;
signal dmaErr_sel : std_logic;
signal dma_ack : std_logic;
signal dma_ack_rd_mst : std_logic;
signal dma_ack_read : std_logic;
signal dma_ack_rw : std_logic;
signal dma_ack_write : std_logic;
signal dma_rd_err : std_logic;
signal dma_req : std_logic;
signal dma_req_overflow : std_logic;
signal dma_req_read : std_logic;
signal dma_req_write : std_logic;
signal dma_rw : std_logic;
signal dma_wr_err : std_logic;
signal flt0_rx_dv : std_logic;
signal flt0_tx_en : std_logic;
signal flt1_rx_dv : std_logic;
signal flt1_tx_en : std_logic;
signal hub_intern_port : integer;
signal hub_rx_port : integer;
signal irqTable_sel : std_logic;
signal mac_rx_dv : std_logic;
signal mac_rx_irq_s : std_logic;
signal mac_rx_irq_s_n : std_logic;
signal mac_rx_off : std_logic;
signal mac_selcont : std_logic;
signal mac_selfilter : std_logic;
signal mac_selram : std_logic;
signal mac_tx_en : std_logic;
signal mac_tx_irq_s : std_logic;
signal mac_tx_irq_s_n : std_logic;
signal mac_tx_off : std_logic;
signal mac_write : std_logic;
signal mac_write_n : std_logic;
signal phy0_rx_dv_s : std_logic;
signal phy0_rx_err_s : std_logic;
signal phy0_tx_en_s : std_logic;
signal phy1_rx_dv_s : std_logic;
signal phy1_rx_err_s : std_logic;
signal phy1_tx_en_s : std_logic;
signal pkt_read_ack : std_logic;
signal pkt_write_ack : std_logic;
signal read_a : std_logic;
signal read_b : std_logic;
signal smi_clk : std_logic;
signal smi_di_s : std_logic;
signal smi_doe_s : std_logic;
signal smi_doe_s_n : std_logic;
signal smi_do_s : std_logic;
signal smi_rst_n : std_logic;
signal smi_sel : std_logic;
signal smi_write : std_logic;
signal smi_write_n : std_logic;
signal s_rd : std_logic;
signal s_rd_ack : std_logic;
signal s_wr : std_logic;
signal s_wr_ack : std_logic;
signal toggle : std_logic;
signal VCC : std_logic;
signal write_a : std_logic;
signal write_b : std_logic;
signal dma_addr : std_logic_vector (dma_highadr_g downto 1);
signal dma_addr_s : std_logic_vector (iPktBufSizeLog2_g-1 downto 1);
signal dma_be : std_logic_vector (1 downto 0);
signal dma_din : std_logic_vector (15 downto 0);
signal dma_din_mst : std_logic_vector (15 downto 0);
signal dma_din_s : std_logic_vector (15 downto 0);
signal dma_dout : std_logic_vector (15 downto 0);
signal dma_dout_s : std_logic_vector (15 downto 0);
signal dma_rd_len : std_logic_vector (11 downto 0);
signal flt0_rx_dat : std_logic_vector (1 downto 0);
signal flt0_tx_dat : std_logic_vector (1 downto 0);
signal flt1_rx_dat : std_logic_vector (1 downto 0);
signal flt1_tx_dat : std_logic_vector (1 downto 0);
signal hub_rx : std_logic_vector (1 downto 0);
signal hub_rx_dat0 : std_logic_vector (3 downto 1);
signal hub_rx_dat1 : std_logic_vector (3 downto 1);
signal hub_rx_dv : std_logic_vector (3 downto 1);
signal hub_tx_dat0 : std_logic_vector (3 downto 1);
signal hub_tx_dat1 : std_logic_vector (3 downto 1);
signal hub_tx_en : std_logic_vector (3 downto 1);
signal hub_tx_msk : std_logic_vector (3 downto 1);
signal irqTable : std_logic_vector (15 downto 0);
signal mac_addr : std_logic_vector (10 downto 1);
signal mac_be : std_logic_vector (1 downto 0);
signal mac_be_n : std_logic_vector (1 downto 0);
signal mac_din : std_logic_vector (15 downto 0);
signal mac_dout : std_logic_vector (15 downto 0);
signal mac_rx_dat : std_logic_vector (1 downto 0);
signal mac_time : std_logic_vector (31 downto 0);
signal mac_tx_dat : std_logic_vector (1 downto 0);
signal phy0_rx_dat_s : std_logic_vector (1 downto 0);
signal phy0_tx_dat_s : std_logic_vector (1 downto 0);
signal phy1_rx_dat_s : std_logic_vector (1 downto 0);
signal phy1_tx_dat_s : std_logic_vector (1 downto 0);
signal smi_addr : std_logic_vector (2 downto 0);
signal smi_be : std_logic_vector (1 downto 0);
signal smi_be_n : std_logic_vector (1 downto 0);
signal smi_din : std_logic_vector (15 downto 0);
signal smi_dout : std_logic_vector (15 downto 0);
signal s_address_s : std_logic_vector (s_address'length downto 0);
signal t_readdata_s : std_logic_vector (31 downto 0);
signal t_writedata_s : std_logic_vector (31 downto 0);
begin
---- User Signal Assignments ----
--endian conversion
t_writedata_s <= t_writedata(7 downto 0) & t_writedata(15 downto 8) &
t_writedata(23 downto 16) & t_writedata(31 downto 24) when endian_g = "big" else
t_writedata;
t_readdata <= t_readdata_s(7 downto 0) & t_readdata_s(15 downto 8) &
t_readdata_s(23 downto 16) & t_readdata_s(31 downto 24) when endian_g = "big" else
t_readdata_s;
--assign address bus and be to openMA
mac_addr <= s_address(9 downto 0);
mac_be <= s_byteenable;
--convert word into byte addresses
s_address_s <= s_address & '0';
smi_addr <= s_address(2 downto 0);
smi_be <= s_byteenable;
--assign output data to readdata
s_readdata <=
mac_dout when (mac_selram = '1' or mac_selcont = '1') and endian_g = "little" else
mac_dout when (mac_selram = '1' or mac_selcont = '1') and endian_g = "big" and s_byteenable /= "11" else
mac_dout(7 downto 0) & mac_dout(15 downto 8) when (mac_selram = '1' or mac_selcont = '1') and endian_g = "big" else --and s_byteenable = "11"
smi_dout when smi_sel = '1' and endian_g = "little" else
smi_dout when smi_sel = '1' and endian_g = "big" and s_byteenable /= "11" else
smi_dout(7 downto 0) & smi_dout(15 downto 8) when smi_sel = '1' and endian_g = "big" else --and s_byteenable = "11"
irqTable when irqTable_sel = '1' and endian_g = "little" else
irqTable(7 downto 0) & irqTable(15 downto 8) when irqTable_sel = '1' and endian_g = "big" else
(8 => dma_rd_err, 0 => dma_wr_err, others => '0') when dmaErr_sel = '1' and endian_g = "little" else
(8 => dma_rd_err, 0 => dma_wr_err, others => '0') when dmaErr_sel = '1' and endian_g = "big" else
(others => '0');
--assign writedata to input data
mac_din <= s_writedata when endian_g = "little" or (endian_g = "big" and s_byteenable /= "11") else
s_writedata(7 downto 0) & s_writedata(15 downto 8); --when endian_g = "big" and s_byteenable = "11"
smi_din <= s_writedata when endian_g = "little" or (endian_g = "big" and s_byteenable /= "11") else
s_writedata(7 downto 0) & s_writedata(15 downto 8); --when endian_g = "big" and s_byteenable = "11"
---- Component instantiations ----
THE_MAC_TIME_CMP : openMAC_cmp
generic map (
gen2ndCmpTimer_g => gen2ndCmpTimer_g,
mac_time_width_g => 32
)
port map(
addr => t_address,
clk => clk,
din => t_writedata_s,
dout => t_readdata_s,
irq => t_irq,
mac_time => mac_time( 31 downto 0 ),
rst => rst,
toggle => toggle,
wr => cmp_wr
);
THE_OPENMAC : OpenMAC
generic map (
HighAdr => dma_highadr_g,
Simulate => simulate,
Timer => true,
TxDel => true,
TxSyncOn => true
)
port map(
Clk => clk,
Dma_Ack => dma_ack,
Dma_Addr => dma_addr( dma_highadr_g downto 1 ),
Dma_Din => dma_din,
Dma_Dout => dma_dout,
Dma_Rd_Done => mac_tx_off,
Dma_Rd_Len => dma_rd_len,
Dma_Req => dma_req,
Dma_Req_Overflow => dma_req_overflow,
Dma_Rw => dma_rw,
Dma_Wr_Done => mac_rx_off,
Hub_Rx => hub_rx,
Mac_Zeit => mac_time,
Rst => rst,
S_Adr => mac_addr,
S_Din => mac_din,
S_Dout => mac_dout,
S_nBe => mac_be_n,
Sel_Cont => mac_selcont,
Sel_Ram => mac_selram,
nRx_Int => mac_rx_irq_s_n,
nTx_Int => mac_tx_irq_s_n,
rCrs_Dv => mac_rx_dv,
rRx_Dat => mac_rx_dat,
rTx_Dat => mac_tx_dat,
rTx_En => mac_tx_en,
s_nWr => mac_write_n
);
THE_PHY_MGMT : OpenMAC_MII
port map(
Addr => smi_addr,
Clk => clk,
Data_In => smi_din,
Data_Out => smi_dout,
Mii_Clk => smi_clk,
Mii_Di => smi_di_s,
Mii_Do => smi_do_s,
Mii_Doe => smi_doe_s_n,
Rst => rst,
Sel => smi_sel,
nBe => smi_be_n,
nResetOut => smi_rst_n,
nWr => smi_write_n
);
mac_rx_irq_s <= not(mac_rx_irq_s_n);
s_irq <= mac_tx_irq_s or mac_rx_irq_s;
mac_write_n <= not(mac_write);
mac_be_n(1) <= not(mac_be(1));
mac_be_n(0) <= not(mac_be(0));
smi_doe_s <= not(smi_doe_s_n);
smi_write_n <= not(smi_write);
smi_be_n(1) <= not(smi_be(1));
smi_be_n(0) <= not(smi_be(0));
s_wr <= s_write and s_chipselect;
irqTable(0) <= mac_tx_irq_s;
irqTable(1) <= mac_rx_irq_s;
mac_write <= s_write;
smi_write <= s_write;
cmp_wr <= t_write and t_chipselect;
dma_req_write <= not(dma_rw) and dma_req;
dma_ack <= dma_ack_write or dma_ack_read;
s_rd <= s_read and s_chipselect;
dma_req_read <= dma_rw and dma_req;
t_waitrequest <= not(cmp_wr_ack or cmp_rd_ack);
cmp_rd <= t_read and t_chipselect;
s_waitrequest <= not(s_rd_ack or s_wr_ack);
mac_tx_irq_s <= not(mac_tx_irq_s_n);
addrdec0 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0000#,
highaddr_g => 16#03FF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selcont
);
addrdec1 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0FFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selram
);
addrdec2 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#0800#,
highaddr_g => 16#0BFF#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => mac_selfilter
);
addrdec3 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1000#,
highaddr_g => 16#100F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => smi_sel
);
addrdec4 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1010#,
highaddr_g => 16#101F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => irqTable_sel
);
addrdec5 : addr_decoder
generic map (
addrWidth_g => s_address'length+1,
baseaddr_g => 16#1020#,
highaddr_g => 16#102F#
)
port map(
addr => s_address_s( s_address'length downto 0 ),
selin => s_chipselect,
selout => dmaErr_sel
);
regack0 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => s_wr_ack,
clk => clk,
enable => s_wr,
rst => rst
);
regack1 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => s_rd_ack,
clk => clk,
enable => s_rd,
rst => rst
);
regack2 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => false
)
port map(
ack => cmp_rd_ack,
clk => clk,
enable => cmp_rd,
rst => rst
);
regack3 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => cmp_wr_ack,
clk => clk,
enable => cmp_wr,
rst => rst
);
---- Power , ground assignment ----
VCC <= VCC_CONSTANT;
dma_be(1) <= VCC;
dma_be(0) <= VCC;
---- Terminal assignment ----
-- Output\buffer terminals
mac_rx_irq <= mac_rx_irq_s;
mac_tx_irq <= mac_tx_irq_s;
t_tog <= toggle;
---- Generate statements ----
genPhyActLed : if genPhyActLed_g generate
begin
THE_PHY_ACT : OpenMAC_phyAct
generic map (
iBlinkFreq_g => 6
)
port map(
act_led => act_led,
clk => clk,
rst => rst,
rx_dv => mac_rx_dv,
tx_en => mac_tx_en
);
end generate genPhyActLed;
genHub : if genHub_g generate
begin
THE_OPENFILTER0 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => flt0_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => flt0_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => flt0_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => flt0_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENFILTER1 : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy1_rx_dat_s,
RxDatOut => flt1_rx_dat,
RxDvIn => phy1_rx_dv_s,
RxDvOut => flt1_rx_dv,
RxErr => phy1_rx_err_s,
TxDatIn => flt1_tx_dat,
TxDatOut => phy1_tx_dat_s,
TxEnIn => flt1_tx_en,
TxEnOut => phy1_tx_en_s,
nCheckShortFrames => VCC
);
THE_OPENHUB : OpenHUB
generic map (
Ports => 3
)
port map(
Clk => clk,
ReceivePort => hub_rx_port,
Rst => rst,
RxDat0 => hub_rx_dat0( 3 downto 1 ),
RxDat1 => hub_rx_dat1( 3 downto 1 ),
RxDv => hub_rx_dv( 3 downto 1 ),
TransmitMask => hub_tx_msk( 3 downto 1 ),
TxDat0 => hub_tx_dat0( 3 downto 1 ),
TxDat1 => hub_tx_dat1( 3 downto 1 ),
TxEn => hub_tx_en( 3 downto 1 ),
internPort => hub_intern_port
);
--mac tx to hub rx
hub_rx_dv(1) <= mac_tx_en;
hub_rx_dat0(1) <= mac_tx_dat(0);
hub_rx_dat1(1) <= mac_tx_dat(1);
--hub tx to mac rx
mac_rx_dv <= hub_tx_en(1);
mac_rx_dat(0) <= hub_tx_dat0(1);
mac_rx_dat(1) <= hub_tx_dat1(1);
--filter 0 to hub rx
hub_rx_dv(2) <= flt0_rx_dv;
hub_rx_dat0(2) <= flt0_rx_dat(0);
hub_rx_dat1(2) <= flt0_rx_dat(1);
--hub tx to filter 0
flt0_tx_en <= hub_tx_en(2);
flt0_tx_dat(0) <= hub_tx_dat0(2);
flt0_tx_dat(1) <= hub_tx_dat1(2);
--filter 1 to hub rx
hub_rx_dv(3) <= flt1_rx_dv;
hub_rx_dat0(3) <= flt1_rx_dat(0);
hub_rx_dat1(3) <= flt1_rx_dat(1);
--hub tx to filter 1
flt1_tx_en <= hub_tx_en(3);
flt1_tx_dat(0) <= hub_tx_dat0(3);
flt1_tx_dat(1) <= hub_tx_dat1(3);
--convert to std_logic_vector
hub_rx <= conv_std_logic_vector(hub_rx_port,hub_rx'length);
--set intern port
hub_intern_port <= 1;
--set tx mask
hub_tx_msk <= (others => '1');
end generate genHub;
genRmii2Mii0 : if not useRmii_g generate
begin
THE_MII2RMII0 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii0_rx_clk,
mRxDat => phyMii0_rx_dat,
mRxDv => phyMii0_rx_dv,
mRxEr => phyMii0_rx_err,
mTxClk => phyMii0_tx_clk,
mTxDat => phyMii0_tx_dat,
mTxEn => phyMii0_tx_en,
rRxDat => phy0_rx_dat_s,
rRxDv => phy0_rx_dv_s,
rRxEr => phy0_rx_err_s,
rTxDat => phy0_tx_dat_s,
rTxEn => phy0_tx_en_s,
rst => rst
);
end generate genRmii2Mii0;
genRmii2Mii1 : if not useRmii_g and genHub_g generate
begin
THE_MII2RMII1 : rmii2mii
port map(
clk50 => clk,
mRxClk => phyMii1_rx_clk,
mRxDat => phyMii1_rx_dat,
mRxDv => phyMii1_rx_dv,
mRxEr => phyMii1_rx_err,
mTxClk => phyMii1_tx_clk,
mTxDat => phyMii1_tx_dat,
mTxEn => phyMii1_tx_en,
rRxDat => phy1_rx_dat_s,
rRxDv => phy1_rx_dv_s,
rRxEr => phy1_rx_err_s,
rTxDat => phy1_tx_dat_s,
rTxEn => phy1_tx_en_s,
rst => rst
);
end generate genRmii2Mii1;
genRmii100MegFFs : if useRmii_g generate
begin
latchRxSignals :
process (clk, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_rx_dv_s <= '0';
phy0_rx_err_s <= '0';
phy0_rx_dat_s <= (others => '0');
phy1_rx_dv_s <= '0';
phy1_rx_err_s <= '0';
phy1_rx_dat_s <= (others => '0');
elsif clk = '1' and clk'event then
phy0_rx_dv_s <= phy0_rx_dv;
phy0_rx_err_s <= phy0_rx_err;
phy0_rx_dat_s <= phy0_rx_dat;
phy1_rx_dv_s <= phy1_rx_dv;
phy1_rx_err_s <= phy1_rx_err;
phy1_rx_dat_s <= phy1_rx_dat;
end if;
end process;
latchTxSignals :
process (clkx2, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
begin
if rst = '1' then
phy0_tx_en <= '0';
phy0_tx_dat <= (others => '0');
phy1_tx_en <= '0';
phy1_tx_dat <= (others => '0');
elsif clkx2 = '0' and clkx2'event then
phy0_tx_en <= phy0_tx_en_s;
phy0_tx_dat <= phy0_tx_dat_s;
phy1_tx_en <= phy1_tx_en_s;
phy1_tx_dat <= phy1_tx_dat_s;
end if;
end process;
end generate genRmii100MegFFs;
genOneFilter : if genHub_g = false generate
begin
THE_OPENFILTER : openFILTER
generic map (
bypassFilter => not useRmii_g
)
port map(
Clk => clk,
Rst => rst,
RxDatIn => phy0_rx_dat_s,
RxDatOut => mac_rx_dat,
RxDvIn => phy0_rx_dv_s,
RxDvOut => mac_rx_dv,
RxErr => phy0_rx_err_s,
TxDatIn => mac_tx_dat,
TxDatOut => phy0_tx_dat_s,
TxEnIn => mac_tx_en,
TxEnOut => phy0_tx_en_s,
nCheckShortFrames => VCC
);
end generate genOneFilter;
genPktBuf : if useIntPktBuf_g = TRUE generate
begin
g5 : if useRxIntPktBuf_g = TRUE generate
begin
dma_ack_write <= dma_ack_rw;
end generate g5;
THE_MAC_PKT_BUF : OpenMAC_DPRpackets
generic map (
memSizeLOG2_g => iPktBufSizeLog2_g,
memSize_g => iPktBufSize_g
)
port map(
address_a => dma_addr_s( iPktBufSizeLog2_g-1 downto 1 ),
address_b => pkt_address( iPktBufSizeLog2_g-3 downto 0 ),
byteena_a => dma_be,
byteena_b => pkt_byteenable,
clock_a => clk,
clock_b => pkt_clk,
data_a => dma_dout_s,
data_b => pkt_writedata,
q_a => dma_din_s,
q_b => pkt_readdata,
rden_a => read_a,
rden_b => read_b,
wren_a => write_a,
wren_b => write_b
);
read_b <= pkt_read and pkt_chipselect;
write_b <= pkt_write and pkt_chipselect;
read_a <= dma_req_read;
dma_ack_read <= dma_ack_rw;
pkt_waitrequest <= not(pkt_write_ack or pkt_read_ack);
regack4 : req_ack
generic map (
ack_delay_g => 1,
zero_delay_g => true
)
port map(
ack => pkt_write_ack,
clk => pkt_clk,
enable => write_b,
rst => rst
);
regack5 : req_ack
generic map (
ack_delay_g => 2,
zero_delay_g => false
)
port map(
ack => pkt_read_ack,
clk => pkt_clk,
enable => read_b,
rst => rst
);
--endian conversion
dma_dout_s <= dma_dout;
dma_din <= dma_din_s;
dma_addr_s(iPktBufSizeLog2_g-1 downto 1) <= dma_addr(iPktBufSizeLog2_g-1 downto 1);
--write DPR from port A only if RX data is written to DPR
write_a <= dma_req_write when useRxIntPktBuf_g = TRUE else '0';
genAck :
process (clk, rst)
-- Section above this comment may be overwritten according to
-- "Update sensitivity list automatically" option status
-- declarations
begin
if rst = '1' then
dma_ack_rw <= '0';
elsif clk = '1' and clk'event then
if dma_req = '1' and dma_ack_rw = '0' then
dma_ack_rw <= '1';
else
dma_ack_rw <= '0';
end if;
end if;
end process;
end generate genPktBuf;
genDmaMaster : if not useIntPktBuf_g or (useIntPktBuf_g and not useRxIntPktBuf_g) generate
begin
genReadDmaMaster : if not useIntPktBuf_g generate
begin
dma_ack_read <= dma_ack_rd_mst;
U69_array: for U69_array_index in 0 to (dma_din'length - 1) generate
U69_array :
dma_din(U69_array_index+dma_din'Low) <= dma_din_mst(U69_array_index+dma_din_mst'Low);
end generate;
end generate genReadDmaMaster;
THE_MAC_DMA_MASTER : openMAC_DMAmaster
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_c,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_c,
gen_tx_fifo_g => gen_tx_fifo_c,
m_burstcount_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount'length,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_g => rx_fifo_word_size_c,
simulate => simulate,
tx_fifo_word_size_g => tx_fifo_word_size_c
)
port map(
dma_ack_rd => dma_ack_rd_mst,
dma_ack_wr => dma_ack_write,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_clk => clk,
dma_din => dma_din_mst,
dma_dout => dma_dout,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_read,
dma_req_wr => dma_req_write,
dma_wr_err => dma_wr_err,
m_address => m_address( 29 downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( m_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( m_data_width_g-1 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( m_data_width_g-1 downto 0 ),
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst
);
end generate genDmaMaster;
genOneSmi : if gNumSmi = 1 or not genHub_g generate
begin
genOneTriStateBuf : if genSmiIO generate
begin
smi_di_s <= phy_smi_dio;
phy_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
end generate genOneTriStateBuf;
dontGenOneTriStateBuf : if not genSmiIO generate
begin
smi_di_s <= phy_smi_dio_I;
phy_smi_dio_O <= smi_do_s;
phy_smi_dio_T <= smi_doe_s_n;
end generate dontGenOneTriStateBuf;
phy_rst_n <= smi_rst_n;
phy_smi_clk <= smi_clk;
end generate genOneSmi;
genTwoSmi : if gNumSmi = 2 and genHub_g generate
begin
genTwoTriStateBuf : if genSmiIO generate
begin
phy0_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
phy1_smi_dio <= smi_do_s when smi_doe_s='1' else 'Z';
smi_di_s <= phy0_smi_dio and phy1_smi_dio;
end generate genTwoTriStateBuf;
dontGenTwoTriStateBuf : if not genSmiIO generate
begin
phy1_smi_dio_T <= smi_doe_s_n;
smi_di_s <= phy0_smi_dio_I and phy1_smi_dio_I;
phy0_smi_dio_T <= smi_doe_s_n;
phy1_smi_dio_O <= smi_do_s;
phy0_smi_dio_O <= smi_do_s;
end generate dontGenTwoTriStateBuf;
phy0_smi_clk <= smi_clk;
phy0_rst_n <= smi_rst_n;
phy1_smi_clk <= smi_clk;
phy1_rst_n <= smi_rst_n;
end generate genTwoSmi;
end rtl;
| gpl-2.0 | 80745978b07a8c87a5a40f78b4ef4368 | 0.586585 | 3.094219 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/sid_mapper.vhd | 4 | 6,185 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2011 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.slot_bus_pkg.all;
use work.sid_io_regs_pkg.all;
entity sid_mapper is
port (
clock : in std_logic;
reset : in std_logic;
slot_req : in t_slot_req;
slot_resp : out t_slot_resp;
control : in t_sid_control;
sid_addr : out unsigned(7 downto 0);
sid_wren : out std_logic;
sid_wdata : out std_logic_vector(7 downto 0);
sid_rdata : in std_logic_vector(7 downto 0) );
end sid_mapper;
architecture mapping of sid_mapper is
signal sid_wren_l : std_logic;
signal sid_wren_r : std_logic;
signal sid_wren_d : std_logic;
signal sid_addr_l : unsigned(7 downto 0);
signal sid_addr_r : unsigned(7 downto 0);
signal sid_addr_d : unsigned(7 downto 0);
signal sid_wdata_l : std_logic_vector(7 downto 0);
signal sid_wdata_d : std_logic_vector(7 downto 0);
begin
slot_resp.data <= sid_rdata;
sid_wren <= sid_wren_l or sid_wren_d;
sid_addr <= sid_addr_d when sid_wren_d='1' else sid_addr_l;
sid_wdata <= sid_wdata_l; -- should work, but it's not neat!
process(clock)
begin
if rising_edge(clock) then
sid_wren_l <= '0';
sid_wren_r <= '0';
sid_wren_d <= sid_wren_r;
sid_addr_d <= sid_addr_r;
sid_wdata_l <= slot_req.data;
sid_wdata_d <= sid_wdata_l;
if slot_req.io_write='1' then
sid_addr_l <= slot_req.io_address(7 downto 0);
sid_addr_r <= slot_req.io_address(7 downto 0);
else
sid_addr_l <= slot_req.bus_address(7 downto 0);
sid_addr_r <= slot_req.bus_address(7 downto 0);
end if;
-- check for left channel access
if control.enable_left='1' then
if slot_req.bus_write='1' then
if control.snoop_left='1' and slot_req.bus_address(15 downto 12)=X"D" then
if control.extend_left='1' then
if slot_req.bus_address(11 downto 7)=control.base_left(11 downto 7) then
sid_addr_l(7) <= '0';
sid_wren_l <= '1';
end if;
else -- just 3 voices
if slot_req.bus_address(11 downto 5)=control.base_left(11 downto 5) then
sid_wren_l <= '1';
sid_addr_l(7 downto 5) <= "000"; -- truncated address
end if;
end if;
end if;
elsif slot_req.io_write='1' then
if control.snoop_left='0' then
if control.extend_left='1' and slot_req.io_address(8 downto 7)=control.base_left(8 downto 7) then
sid_addr_l(7) <= '0';
sid_wren_l <= '1';
elsif control.extend_left='0' and slot_req.io_address(8 downto 5)=control.base_left(8 downto 5) then
sid_addr_l(7 downto 5) <= "000";
sid_wren_l <= '1';
end if;
end if;
end if;
end if;
-- check for right channel access
if control.enable_right='1' then
if slot_req.bus_write='1' then
if control.snoop_right='1' and slot_req.bus_address(15 downto 12)=X"D" then
if control.extend_right='1' then
if slot_req.bus_address(11 downto 7)=control.base_right(11 downto 7) then
sid_addr_r(7) <= '1';
sid_wren_r <= '1';
end if;
else -- just 3 voices
if slot_req.bus_address(11 downto 5)=control.base_right(11 downto 5) then
sid_wren_r <= '1';
sid_addr_r(7 downto 5) <= "100"; -- truncated address
end if;
end if;
end if;
elsif slot_req.io_write='1' then
if control.snoop_right='0' then
if control.extend_right='1' and slot_req.io_address(8 downto 7)=control.base_right(8 downto 7) then
sid_addr_r(7) <= '1';
sid_wren_r <= '1';
elsif control.extend_right='0' and slot_req.io_address(8 downto 5)=control.base_right(8 downto 5) then
sid_addr_r(7 downto 5) <= "100";
sid_wren_r <= '1';
end if;
end if;
end if;
end if;
end if;
end process;
slot_resp.irq <= '0';
slot_resp.reg_output <= '0';
end mapping;
-- Mapping options are as follows:
-- STD $D400-$D41F: Snoop='1' Base=$40. Extend='0' (bit 11...5 are significant)
-- STD $D500-$D51F: Snoop='1' Base=$50. Extend='0'
-- STD $DE00-$DE1F: Snoop='0' Base=$E0. Extend='0' (bit 8...5 are significant)
-- STD $DF00-$DF1F: Snoop='0' Base=$F0. Extend='0'
-- EXT $DF80-$DFFF: Snoop='0' Base=$F8. Extend='1' (bit 8...7 are significant)
-- EXT $D600-$D67F: Snoop='1' Base=$60. Extend='1' (bit 11..7 are significant)
-- .. etc
| gpl-3.0 | 2929e9be6b2bffa4307e7d0496c0b02d | 0.456589 | 3.853583 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/pdi_spi.vhd | 3 | 10,898 | ------------------------------------------------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-31 V0.01 zelenkaj First version
-- 2010-11-23 V0.02 zelenkaj Added write/read sequence feature (WRSQ and RDSQ)
-- 2010-11-29 V0.03 zelenkaj Added endian generic
-- 2011-01-10 V0.04 zelenkaj Added wake up feature
-- 2011-02-28 V0.05 zelenkaj Added inversion of wake up command
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_spi is
generic (
spiSize_g : integer := 8;
cpol_g : boolean := false;
cpha_g : boolean := false;
spiBigEnd_g : boolean := false
);
port (
-- SPI
spi_clk : in std_logic;
spi_sel : in std_logic;
spi_miso : out std_logic;
spi_mosi : in std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0)
);
end entity pdi_spi;
architecture rtl of pdi_spi is
--wake up command
constant cmdWakeUp : std_logic_vector(7 downto 0) := x"03"; --0b00000011
constant cmdWakeUp1 : std_logic_vector(7 downto 0) := x"0A"; --0b00001010
constant cmdWakeUp2 : std_logic_vector(7 downto 0) := x"0C"; --0b00001100
constant cmdWakeUp3 : std_logic_vector(7 downto 0) := x"0F"; --0b00001111
--spi frame constants
constant cmdHighaddr_c : std_logic_vector(2 downto 0) := "100";
constant cmdMidaddr_c : std_logic_vector(2 downto 0) := "101";
constant cmdWr_c : std_logic_vector(2 downto 0) := "110";
constant cmdRd_c : std_logic_vector(2 downto 0) := "111";
constant cmdWRSQ_c : std_logic_vector(2 downto 0) := "001";
constant cmdRDSQ_c : std_logic_vector(2 downto 0) := "010";
constant cmdLowaddr_c : std_logic_vector(2 downto 0) := "011";
constant cmdIdle_c : std_logic_vector(2 downto 0) := "000";
--pdi_spi control signals
type fsm_t is (reset, reset1, reset2, reset3, idle, decode, waitwr, waitrd, wr, rd);
signal fsm : fsm_t;
signal addrReg : std_logic_vector(ap_address'left+2 downto 0);
signal cmd : std_logic_vector(2 downto 0);
signal highPriorLoad : std_logic;
signal highPriorLoadVal : std_logic_vector(spiSize_g-1 downto 0);
--spi core signals
signal clk : std_logic;
signal rst : std_logic;
signal din : std_logic_vector(spiSize_g-1 downto 0);
signal load : std_logic;
signal dout : std_logic_vector(spiSize_g-1 downto 0);
signal valid : std_logic;
--
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
begin
clk <= ap_clk;
rst <= ap_reset;
ap_chipselect <= '1' when fsm = wr or fsm = rd or fsm = waitrd else '0';
ap_write <= '1' when fsm = wr else '0';
ap_read <= '1' when fsm = waitrd or fsm = rd else '0';
ap_address <= addrReg(addrReg'left downto 2);
ap_byteenable <= ap_byteenable_s;
ap_byteenable_s <= --little endian
"0001" when addrReg(1 downto 0) = "00" and spiBigEnd_g = false else
"0010" when addrReg(1 downto 0) = "01" and spiBigEnd_g = false else
"0100" when addrReg(1 downto 0) = "10" and spiBigEnd_g = false else
"1000" when addrReg(1 downto 0) = "11" and spiBigEnd_g = false else
--big endian
--"0001" when addrReg(1 downto 0) = "11" and spiBigEnd_g = true else
--"0010" when addrReg(1 downto 0) = "10" and spiBigEnd_g = true else
--"0100" when addrReg(1 downto 0) = "01" and spiBigEnd_g = true else
--"1000" when addrReg(1 downto 0) = "00" and spiBigEnd_g = true else
"0000";
ap_writedata <= (dout & dout & dout & dout);
din <= highPriorLoadVal when highPriorLoad = '1' else --load value that was just received
ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
load <= '1' when highPriorLoad = '1' else --load value that was just received
'1' when fsm = rd else --load data from pdi to spi shift register
'0';
cmd <= dout(dout'left downto dout'left-2); --get cmd pattern
highPriorLoadVal <= not dout; --create inverse of received pattern
thePdiSpiFsm : process(clk, rst)
variable timeout : integer range 0 to 3;
variable writes : integer range 0 to 32;
variable reads : integer range 0 to 32;
begin
if rst = '1' then
fsm <= reset;
timeout := 0;
writes := 0; reads := 0;
addrReg <= (others => '0');
highPriorLoad <= '0';
elsif clk = '1' and clk'event then
--default assignment
highPriorLoad <= '0';
case fsm is
when reset =>
fsm <= reset;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp then
--wake up command (1/4) received
fsm <= reset1;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset1 =>
fsm <= reset1;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp1 then
--wake up command (2/4) sequence was correctly decoded!
fsm <= reset2;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset2 =>
fsm <= reset2;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp2 then
--wake up command (3/4) sequence was correctly decoded!
fsm <= reset3;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when reset3 =>
fsm <= reset3;
if valid = '1' then
--load inverse pattern of received pattern
highPriorLoad <= '1';
if dout = cmdWakeUp3 then
--wake up command (4/4) sequence was correctly decoded!
fsm <= idle;
else
--wake up command not decoded correctly
fsm <= reset;
end if;
end if;
when idle =>
if writes /= 0 then
fsm <= waitwr;
elsif reads /= 0 and valid = '1' then
fsm <= waitrd;
elsif valid = '1' then
fsm <= decode;
else
fsm <= idle;
end if;
when decode =>
fsm <= idle; --default
case cmd is
when cmdHighaddr_c =>
addrReg(addrReg'left downto addrReg'left-4) <= dout(spiSize_g-4 downto 0);
when cmdMidaddr_c =>
addrReg(addrReg'left-5 downto addrReg'left-9) <= dout(spiSize_g-4 downto 0);
when cmdLowaddr_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
when cmdWr_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
fsm <= waitwr;
writes := 1;
when cmdRd_c =>
addrReg(addrReg'left-10 downto 0) <= dout(spiSize_g-4 downto 0);
fsm <= waitrd;
reads := 1;
when cmdWRSQ_c =>
fsm <= waitwr;
writes := conv_integer(dout(spiSize_g-4 downto 0)) + 1; --BYTES byte are written
when cmdRDSQ_c =>
fsm <= waitrd;
reads := conv_integer(dout(spiSize_g-4 downto 0)) + 1; --BYTES byte are read
when cmdIdle_c =>
--don't interpret the command, inverse pattern and goto idle
when others =>
--error, goto idle
end case;
when waitwr =>
--wait for data from spi master
if valid = '1' then
fsm <= wr;
else
fsm <= waitwr;
end if;
when waitrd =>
--spi master wants to read
--wait for dpr to read
if timeout = 3 then
fsm <= rd;
timeout := 0;
else
timeout := timeout + 1;
fsm <= waitrd;
end if;
when wr =>
fsm <= idle;
writes := writes - 1;
addrReg <= addrReg + 1;
when rd =>
fsm <= idle;
reads := reads - 1;
addrReg <= addrReg + 1;
end case;
end if;
end process;
theSpiCore : entity work.spi
generic map (
frameSize_g => spiSize_g,
cpol_g => cpol_g,
cpha_g => cpha_g
)
port map (
-- Control Interface
clk => clk,
rst => rst,
din => din,
load => load,
dout => dout,
valid => valid,
-- SPI
sck => spi_clk,
ss => spi_sel,
miso => spi_miso,
mosi => spi_mosi
);
end architecture rtl;
| gpl-2.0 | bc2b78192d4c0702df9dbc6cb3d9ea4f | 0.586897 | 3.353231 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb2/vhdl_sim/usb_harness_nano.vhd | 1 | 4,314 | --------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_harness
-- Date:2015-02-14
-- Author: Gideon
-- Description: Harness for USB Host Controller with memory controller
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity usb_harness_nano is
port (
clocks_stopped : in boolean := false );
end entity;
architecture arch of usb_harness_nano is
signal sys_clock : std_logic := '1';
signal sys_clock_2x : std_logic := '1';
signal sys_reset : std_logic;
signal clock : std_logic := '0';
signal reset : std_logic;
signal sys_io_req : t_io_req;
signal sys_io_resp : t_io_resp;
signal sys_mem_req : t_mem_req_32;
signal sys_mem_resp : t_mem_resp_32;
signal ulpi_nxt : std_logic;
signal ulpi_stp : std_logic;
signal ulpi_dir : std_logic;
signal ulpi_data : std_logic_vector(7 downto 0);
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
begin
sys_clock <= not sys_clock after 10 ns when not clocks_stopped;
sys_clock_2x <= not sys_clock_2x after 5 ns when not clocks_stopped;
sys_reset <= '1', '0' after 50 ns;
clock <= not clock after 8.333 ns when not clocks_stopped;
reset <= '1', '0' after 250 ns;
i_io_bus_bfm: entity work.io_bus_bfm
generic map (
g_name => "io" )
port map (
clock => sys_clock,
req => sys_io_req,
resp => sys_io_resp );
i_host: entity work.usb_host_nano
generic map (
g_simulation => true )
port map (
clock => clock,
reset => reset,
ulpi_nxt => ulpi_nxt,
ulpi_dir => ulpi_dir,
ulpi_stp => ulpi_stp,
ulpi_data => ulpi_data,
sys_clock => sys_clock,
sys_reset => sys_reset,
sys_mem_req => sys_mem_req,
sys_mem_resp=> sys_mem_resp,
sys_io_req => sys_io_req,
sys_io_resp => sys_io_resp );
i_ulpi_phy: entity work.ulpi_master_bfm
generic map (
g_given_name => "device" )
port map (
clock => clock,
reset => reset,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_dir => ulpi_dir,
ulpi_data => ulpi_data );
i_device: entity work.usb_device_model;
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => true )
port map (
clock => sys_clock,
clk_2x => sys_clock_2x,
reset => sys_reset,
inhibit => '0',
is_idle => open,
req => sys_mem_req,
resp => sys_mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
ram: entity work.dram_8
generic map(
g_cas_latency => 3,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2
)
port map(
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A,
BA => SDRAM_BA,
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_DQ
);
end arch;
| gpl-3.0 | 1030ffc0352c74c2621c48168acc0460 | 0.486324 | 3.493117 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_sim/harness_v5.vhd | 4 | 16,287 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.mem_bus_pkg.all;
use work.cart_slot_pkg.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.command_if_pkg.all;
entity harness_v5 is
end harness_v5;
architecture tb of harness_v5 is
constant c_uart_divisor : natural := 434;
signal PHI2 : std_logic := '0';
signal RSTn : std_logic := 'H';
signal DOTCLK : std_logic := '1';
signal BUFFER_ENn : std_logic := '1';
signal BA : std_logic := '0';
signal DMAn : std_logic := '1';
signal EXROMn : std_logic;
signal GAMEn : std_logic;
signal ROMHn : std_logic := '1';
signal ROMLn : std_logic := '1';
signal IO1n : std_logic := '1';
signal IO2n : std_logic := '1';
signal IRQn : std_logic := '1';
signal NMIn : std_logic := '1';
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_DQM : std_logic;
signal LB_ADDR : std_logic_vector(14 downto 0);
signal LB_DATA : std_logic_vector(7 downto 0) := X"00";
signal logic_SDRAM_CSn : std_logic;
signal logic_SDRAM_RASn : std_logic;
signal logic_SDRAM_CASn : std_logic;
signal logic_SDRAM_WEn : std_logic;
signal logic_SDRAM_CKE : std_logic;
signal logic_SDRAM_CLK : std_logic;
signal logic_SDRAM_DQM : std_logic;
signal logic_LB_ADDR : std_logic_vector(14 downto 0);
signal PWM_OUT : std_logic_vector(1 downto 0);
signal IEC_ATN : std_logic := '1';
signal IEC_DATA : std_logic := '1';
signal IEC_CLOCK : std_logic := '1';
signal IEC_RESET : std_logic := '1';
signal IEC_SRQ_IN : std_logic := '1';
signal DISK_ACTn : std_logic; -- activity LED
signal CART_LEDn : std_logic;
signal SDACT_LEDn : std_logic;
signal MOTOR_LEDn : std_logic;
signal UART_TXD : std_logic;
signal UART_RXD : std_logic := '1';
signal SD_SSn : std_logic;
signal SD_CLK : std_logic;
signal SD_MOSI : std_logic;
signal SD_MISO : std_logic := '1';
signal SD_WP : std_logic := '1';
signal SD_CARDDETn : std_logic := '1';
signal BUTTON : std_logic_vector(2 downto 0) := "000";
signal SLOT_ADDR : std_logic_vector(15 downto 0);
signal SLOT_DATA : std_logic_vector(7 downto 0);
signal RWn : std_logic := '1';
signal CAS_MOTOR : std_logic := '1';
signal CAS_SENSE : std_logic := '0';
signal CAS_READ : std_logic := '0';
signal CAS_WRITE : std_logic := '0';
signal RTC_CS : std_logic;
signal RTC_SCK : std_logic;
signal RTC_MOSI : std_logic;
signal RTC_MISO : std_logic := '1';
signal FLASH_CSn : std_logic;
signal FLASH_SCK : std_logic;
signal FLASH_MOSI : std_logic;
signal FLASH_MISO : std_logic := '1';
signal ULPI_CLOCK : std_logic := '0';
signal ULPI_RESET : std_logic := '0';
signal ULPI_NXT : std_logic := '0';
signal ULPI_STP : std_logic;
signal ULPI_DIR : std_logic := '0';
signal ULPI_DATA : std_logic_vector(7 downto 0) := (others => 'H');
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic := '0';
signal sys_shifted : std_logic := '0';
signal rx_char : std_logic_vector(7 downto 0);
signal rx_char_d : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal tx_char : std_logic_vector(7 downto 0) := X"00";
signal tx_done : std_logic;
signal do_tx : std_logic := '0';
shared variable dram : h_mem_object;
shared variable ram : h_mem_object;
-- shared variable rom : h_mem_object;
-- shared variable bram : h_mem_object;
-- memory controller interconnect
signal memctrl_inhibit : std_logic := '0';
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal mem_req_cached : t_mem_burst_req;
signal mem_resp_cached : t_mem_burst_resp;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
-- cache monitoring
signal hit_count : unsigned(31 downto 0);
signal miss_count : unsigned(31 downto 0);
signal hit_ratio : real := 0.0;
begin
mut: entity work.ultimate_logic
generic map (
g_simulation => true,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => true,
g_hardware_gcr => true,
g_cartridge => true,
g_command_intf => true,
g_stereo_sid => true,
g_ram_expansion => true,
g_extended_reu => true,
g_hardware_iec => true,
g_iec_prog_tim => true,
g_c2n_streamer => true,
g_c2n_recorder => true,
g_drive_sound => true,
g_rtc_chip => true,
g_rtc_timer => true,
g_usb_host => true,
g_spi_flash => true )
port map (
sys_clock => sys_clock,
sys_reset => sys_reset,
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- io bus for simulation
sim_io_req => io_req,
sim_io_resp => io_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_CLOCK => ULPI_CLOCK,
ULPI_RESET => ULPI_RESET,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Buttons
BUTTON => BUTTON );
i_cache: entity work.dm_cache
port map (
clock => sys_clock,
reset => sys_reset,
client_req => mem_req,
client_resp => mem_resp,
mem_req => mem_req_cached,
mem_resp => mem_resp_cached,
hit_count => hit_count,
miss_count => miss_count );
hit_ratio <= real(to_integer(hit_count)) / real(to_integer(miss_count) + to_integer(hit_count) + 1);
i_memctrl: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => '0', --memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req_cached,
resp => mem_resp_cached,
SDRAM_CSn => logic_SDRAM_CSn,
SDRAM_RASn => logic_SDRAM_RASn,
SDRAM_CASn => logic_SDRAM_CASn,
SDRAM_WEn => logic_SDRAM_WEn,
SDRAM_CKE => logic_SDRAM_CKE,
SDRAM_CLK => logic_SDRAM_CLK,
MEM_A => logic_LB_ADDR,
MEM_D => LB_DATA );
-- clock to out.. for data it is inside of the memory controller, because it's bidirectional
SDRAM_CSn <= transport logic_SDRAM_CSn after 4.9 ns;
SDRAM_RASn <= transport logic_SDRAM_RASn after 4.9 ns;
SDRAM_CASn <= transport logic_SDRAM_CASn after 4.9 ns;
SDRAM_WEn <= transport logic_SDRAM_WEn after 4.9 ns;
SDRAM_CKE <= transport logic_SDRAM_CKE after 4.9 ns;
SDRAM_CLK <= transport logic_SDRAM_CLK after 4.9 ns;
LB_ADDR <= transport logic_LB_ADDR after 4.9 ns;
sys_clock <= not sys_clock after 10 ns; -- 50 MHz
sys_reset <= '1', '0' after 100 ns;
sys_shifted <= transport sys_clock after 15 ns; -- 270 degrees
ULPI_CLOCK <= not ULPI_CLOCK after 8.333 ns; -- 60 MHz
ULPI_RESET <= '1', '0' after 100 ns;
PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz
RSTn <= '0', 'H' after 6 us, '0' after 100 us, 'H' after 105 us;
i_ulpi_phy: entity work.ulpi_phy_bfm
generic map (
g_rx_interval => 100000 )
port map (
clock => ULPI_CLOCK,
reset => ULPI_RESET,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp );
process
begin
bind_mem_model("intram", ram);
bind_mem_model("dram", dram);
load_memory("../../software/1st_boot/result/1st_boot.bin", ram, X"00000000");
-- 1st boot will try to load the 2nd bootloader and application from flash. In simulation this is a cumbersome
-- process. It would work with a good model of the serial spi flash, but since it is not included in the public
-- archive, you need to create a special boot image that just jumps to 0x20000 and load the application here to dram:
load_memory("../../software/ultimate/result/ultimate.bin", dram, X"00020000");
wait;
end process;
SLOT_DATA <= (others => 'H');
ROMHn <= '1';
ROMLn <= not PHI2 after 50 ns;
IO1n <= '1';
IO2n <= '1';
process
begin
SLOT_ADDR <= X"D400";
RWn <= '1';
while true loop
wait until PHI2 = '0';
--SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1);
SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1);
RWn <= '1';
wait until PHI2 = '0';
RWn <= '0';
end loop;
end process;
process
begin
BA <= '1';
for i in 0 to 100 loop
wait until PHI2='0';
end loop;
BA <= '0';
for i in 0 to 10 loop
wait until PHI2='0';
end loop;
end process;
dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => LB_ADDR(12 downto 0),
BA => LB_ADDR(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => LB_DATA);
i_rx: entity work.rx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
rxd => UART_TXD,
rxchar => rx_char,
rx_ack => rx_ack );
i_tx: entity work.tx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
dotx => do_tx,
txchar => tx_char,
done => tx_done,
txd => UART_RXD );
process(sys_clock)
begin
if rising_edge(sys_clock) then
if rx_ack='1' then
rx_char_d <= rx_char;
end if;
end if;
end process;
-- procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
-- procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
-- procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
-- procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
-- constant c_cart_c64_mode : unsigned(3 downto 0) := X"0";
-- constant c_cart_c64_stop : unsigned(3 downto 0) := X"1";
-- constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2";
-- constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3";
-- constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4";
-- constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5";
-- constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6";
-- constant c_cart_reu_enable : unsigned(3 downto 0) := X"8";
-- constant c_cart_reu_size : unsigned(3 downto 0) := X"9";
-- constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A";
-- constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F";
process
variable io : p_io_bus_bfm_object;
begin
wait until sys_reset='0';
wait until sys_clock='1';
bind_io_bus_bfm("io_bfm", io);
io_write(io, X"40000" + c_cart_c64_mode, X"04"); -- reset
io_write(io, X"40000" + c_cart_cartridge_type, X"06"); -- retro
io_write(io, X"40000" + c_cart_c64_mode, X"08"); -- unreset
io_write(io, X"44000" + c_cif_io_slot_base, X"7E");
io_write(io, X"44000" + c_cif_io_slot_enable, X"01");
wait for 6 us;
wait until sys_clock='1';
io_write(io, X"42002", X"42");
wait;
end process;
process
procedure send_char(i: std_logic_vector(7 downto 0)) is
begin
if tx_done /= '1' then
wait until tx_done = '1';
end if;
wait until sys_clock='1';
tx_char <= i;
do_tx <= '1';
wait until tx_done = '0';
wait until sys_clock='1';
do_tx <= '0';
end procedure;
procedure send_string(i : string) is
variable b : std_logic_vector(7 downto 0);
begin
for n in i'range loop
b := std_logic_vector(to_unsigned(character'pos(i(n)), 8));
send_char(b);
end loop;
send_char(X"0d");
send_char(X"0a");
end procedure;
begin
wait for 2 ms;
--send_string("wd 4005000 12345678");
send_string("run");
-- send_string("m 100000");
-- send_string("w 400000F 4");
wait;
end process;
-- check timing data
process(PHI2)
begin
if falling_edge(PHI2) then
assert SLOT_DATA'last_event >= 189 ns
report "Timing error on C64 bus."
severity error;
end if;
end process;
end tb;
| gpl-3.0 | c8b09e83bdcf8518cd76ecebe7b56735 | 0.509977 | 3.356068 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/fpga_mem_test_v6.vhd | 5 | 2,933 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity fpga_mem_test_v6 is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(14 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
MOTOR_LEDn : out std_logic;
ACT_LEDn : out std_logic );
end fpga_mem_test_v6;
architecture tb of fpga_mem_test_v6 is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_burst_16_req := c_mem_burst_16_req_init;
signal resp : t_mem_burst_16_resp;
signal okay : std_logic;
begin
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_checker: entity work.ext_mem_test_v6
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
okay => ACT_LEDn );
i_mem_ctrl: entity work.ext_mem_ctrl_v6
generic map (
q_tcko_data => 5 ns,
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_A(14 downto 13),
SDRAM_A => SDRAM_A(12 downto 0),
SDRAM_DQ => SDRAM_DQ );
MOTOR_LEDn <= 'Z';
end;
| gpl-3.0 | a15d2990f105d030de9e03bab8157a9a | 0.437777 | 3.675439 | false | false | false | false |
Sourangsu/RAM-Arbiter-VHDL-Code | RAM_ARBITER_NEW.vhd | 1 | 8,703 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------------------------------------------------------------
-- Entity for ARBITER
-------------------------------------------------------------------------
entity RAM_ARBITER_NEW is
generic
(
-------------------------------------------------------------------------
-- Generics for scalability
-------------------------------------------------------------------------
G_ADDR_WIDTH: integer := 4;
G_DATA_WIDTH: integer := 8;
G_REGISTERED_DATA: integer :=0
-- G_ADDR_WIDTH = Number of bits required to address the ram
-- G_DATA_WIDTH = Number of bits in a data
-- G_REGISTERED_DATA =1 for registered data in output 0 for nonregistered
-------------------------------------------------------------------------
);
port
(
-------------------------------------------------------------------------
-- General Inputs & output
-------------------------------------------------------------------------
RST_N: in std_logic;
CLOCK: in std_logic;
RST_DONE: out std_logic;
-------------------------------------------------------------------------
-- Inputs from --------client1--------------
-------------------------------------------------------------------------
RD_EN_C1: in std_logic; --read enb--
WR_EN_C1: in std_logic; --write enb--
RDADDR_C1: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--read addr---
WRADDR_C1: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--write addr--
WRDATA_C1: in std_logic_vector(G_DATA_WIDTH-1 downto 0);--data in----
-------------------------------------------------------------------------
-- Inputs from --------client2--------------
-------------------------------------------------------------------------
DATAIN_C2: in std_logic_vector(G_DATA_WIDTH-1 downto 0);--input data--
REQUEST_C2: in std_logic; --request to access memory--
RD_NOT_WRITE_C2: in std_logic; --if '0' then write or read--
ADDR_C2: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--addr for rd or wr--
-------------------------------------------------------------------------
-- Output from --------client1--------------
-------------------------------------------------------------------------
RDDATA_C1: out std_logic_vector(G_DATA_WIDTH-1 downto 0);--data out--
-------------------------------------------------------------------------
-- Output from --------client2--------------
-------------------------------------------------------------------------
DATAOUT_C2: out std_logic_vector(G_DATA_WIDTH-1 downto 0);--out data--
ACK_C2: out std_logic); --acknowlwdgement--
end RAM_ARBITER_NEW;
-------------------------------------------------------------------------
Architecture RTL of RAM_ARBITER_NEW is
signal WR_DATA: std_logic_vector(G_DATA_WIDTH-1 downto 0);-- temp WR data --
signal RD_DATA1: std_logic_vector(G_DATA_WIDTH-1 downto 0);-- temp RD data --
signal WR_ADDR:std_logic_vector(G_ADDR_WIDTH-1 downto 0); ---temp write address----
signal RD_ADDR:std_logic_vector(G_ADDR_WIDTH-1 downto 0); ---temp read address-----
signal RD_EN:std_logic;
signal WR_EN:std_logic;
component RAM is
generic
(
-------------------------------------------------------------------------
-- Generics for scalability
-------------------------------------------------------------------------
G_ADDR_WIDTH: integer;
G_DATA_WIDTH: integer
-- G_ADDR_WIDTH = Number of bits required to address the ram
-- G_DATA_WIDTH = Number of bits in a data
-------------------------------------------------------------------------
);
port
(
-------------------------------------------------------------------------
-- RAM Inputs
-------------------------------------------------------------------------
CLOCK: in std_logic;
RST_N: in std_logic;
RD_EN: in std_logic; --read enb--
WR_EN: in std_logic; --write enb--
RD_ADDR: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--read addr---
WR_ADDR: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--write addr--
WR_DATA: in std_logic_vector(G_DATA_WIDTH-1 downto 0);--data input----
RD_DATA: out std_logic_vector(G_DATA_WIDTH-1 downto 0) --data output--
);
end component;
COMPONENT ARBITER_NEW is
generic
(
-------------------------------------------------------------------------
-- Generics for scalability
-------------------------------------------------------------------------
G_ADDR_WIDTH: integer;
G_DATA_WIDTH: integer;
G_REGISTERED_DATA: integer
-- G_ADDR_WIDTH = Number of bits required to address the ram
-- G_DATA_WIDTH = Number of bits in a data
-- G_REGISTERED_DATA =1 for registered data in output 0 for nonregistered
-------------------------------------------------------------------------
);
port
(
-------------------------------------------------------------------------
-- General Inputs & output
-------------------------------------------------------------------------
RST_N: in std_logic;
CLOCK: in std_logic;
RST_DONE: out std_logic;
-------------------------------------------------------------------------
-- Inputs from --------client1--------------
-------------------------------------------------------------------------
RD_EN_C1: in std_logic; --read enb--
WR_EN_C1: in std_logic; --write enb--
RDADDR_C1: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--read addr---
WRADDR_C1: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--write addr--
WRDATA_C1: in std_logic_vector(G_DATA_WIDTH-1 downto 0);--data in----
-------------------------------------------------------------------------
-- Inputs from --------client2--------------
-------------------------------------------------------------------------
DATAIN_C2: in std_logic_vector(G_DATA_WIDTH-1 downto 0);--input data--
REQUEST_C2: in std_logic; --request to access memory--
RD_NOT_WRITE_C2: in std_logic; --if '0' then write or read--
ADDR_C2: in std_logic_vector(G_ADDR_WIDTH-1 downto 0);--addr for rd or wr--
-------------------------------------------------------------------------
-- Output from --------client1--------------
-------------------------------------------------------------------------
RDDATA_C1: out std_logic_vector(G_DATA_WIDTH-1 downto 0);--data out--
-------------------------------------------------------------------------
-- Output from --------client2--------------
-------------------------------------------------------------------------
DATAOUT_C2: out std_logic_vector(G_DATA_WIDTH-1 downto 0);--out data--
ACK_C2: out std_logic; --acknowlwdgement--
RD_EN: out std_logic;
WR_EN: out std_logic;
WR_ADDR: out std_logic_vector(G_ADDR_WIDTH-1 downto 0);
RD_ADDR: out std_logic_vector(G_ADDR_WIDTH-1 downto 0);
WR_DATA: out std_logic_vector(G_DATA_WIDTH-1 downto 0);
RD_DATA: in std_logic_vector(G_DATA_WIDTH-1 downto 0));
end COMPONENT;
begin
RAMCLIENT:RAM
GENERIC MAP(G_ADDR_WIDTH,G_DATA_WIDTH)
PORT MAP(CLOCK => CLOCK,
RST_N => RST_N,
RD_EN => RD_EN,
WR_EN => WR_EN,
RD_ADDR=> RD_ADDR,
WR_ADDR=> WR_ADDR,
WR_DATA=> WR_DATA,
RD_DATA=> RD_DATA1);
ARBITERCLIENT:ARBITER_NEW
GENERIC MAP(G_ADDR_WIDTH,G_DATA_WIDTH,G_REGISTERED_DATA)
PORT MAP(RST_N => RST_N,
CLOCK => CLOCK,
RST_DONE => RST_DONE,
RD_EN_C1 => RD_EN_C1,
WR_EN_C1 => WR_EN_C1,
RDADDR_C1 => RDADDR_C1,
WRADDR_C1 => WRADDR_C1,
WRDATA_C1 => WRDATA_C1,
REQUEST_C2 => REQUEST_C2,
RD_NOT_WRITE_C2=> RD_NOT_WRITE_C2,
ADDR_C2 => ADDR_C2,
DATAIN_C2 => DATAIN_C2,
RD_EN => RD_EN,
WR_EN => WR_EN,
RD_ADDR => RD_ADDR,
WR_ADDR => WR_ADDR,
WR_DATA => WR_DATA,
RD_DATA => RD_DATA1,
DATAOUT_C2 => DATAOUT_C2,
ACK_C2 => ACK_C2,
RDDATA_C1 => RDDATA_C1);
end RTL;
| bsd-3-clause | bc15b2c74fa80a195146feb17d0b59de | 0.383776 | 4.344983 | false | false | false | false |
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