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chrismasters/fpga-notes | sdramcontroller/tester.vhd | 1 | 5,333 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity tester is
port (
clk : IN std_logic;
MEM_Clk : OUT std_logic;
MEM_Cke : OUT std_logic;
MEM_CS : OUT std_logic;
nWE : OUT std_logic;
nCAS : OUT std_logic;
nRAS : OUT std_logic;
DQML : OUT std_logic;
DQMH : OUT std_logic;
BA : OUT std_logic_vector(1 downto 0);
ADDR : OUT std_logic_vector(12 downto 0);
DATA : INOUT std_logic_vector(15 downto 0);
A : OUT std_logic_vector(15 downto 0);
reset : IN std_logic;
up : IN std_logic
);
end tester;
architecture Behavioral of tester is
COMPONENT sdramcontroller PORT (
clk : IN std_logic;
addr : IN std_logic_vector(15 downto 0);
cmd : IN std_logic_vector(1 downto 0);
dataIn : IN std_logic_vector(7 downto 0);
dataOut : OUT std_logic_vector(7 downto 0);
chipDATA : INOUT std_logic_vector(15 downto 0);
ready : OUT std_logic;
--chipClk : OUT std_logic;
--chipCke : OUT std_logic;
chipCS : OUT std_logic;
chipWE : OUT std_logic;
chipCAS : OUT std_logic;
chipRAS : OUT std_logic;
chipDQML : OUT std_logic;
chipDQMH : OUT std_logic;
chipBA : OUT std_logic_vector(1 downto 0);
chipADDR : OUT std_logic_vector(11 downto 0)
);
END COMPONENT;
component clks port (
CLK_IN1 : in std_logic;
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic
);
end component;
signal xaddr : std_logic_vector(15 downto 0);
signal xcmd : std_logic_vector(1 downto 0);
signal xdataIn : std_logic_vector(7 downto 0);
signal xdataOut : std_logic_vector(7 downto 0);
signal ready : std_logic;
signal clk133out : std_logic;
signal clk133 : std_logic;
signal clk133inv : std_logic;
signal stopClock : std_logic;
signal holdClockLow : std_logic;
signal holdClockHigh : std_logic;
signal nextLights : std_logic_vector(3 downto 0);
signal waitCounter : std_logic_vector (31 downto 0) := (others => '0');
type stateType is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal currentState : stateType := s0;
begin
ODDR2_inst : ODDR2
generic map(
DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
INIT => '0', -- Sets initial state of the Q output to '0' or '1'
SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
port map (
Q => clk133out, -- 1-bit output data
C0 => clk133, -- 1-bit clock input
C1 => clk133inv, -- 1-bit clock input
CE => stopClock, -- 1-bit clock enable input
D0 => '0', -- 1-bit data input (associated with C0)
D1 => '1', -- 1-bit data input (associated with C1)
R => holdClockLow, -- 1-bit reset input
S => holdClockHigh -- 1-bit set input
);
iClocks : clks port map (
CLK_IN1 => clk,
CLK_OUT1 => clk133,
CLK_OUT2 => clk133inv
);
MEM_Clk <= clk133out;
MEM_Cke <= '1';
iSdram: sdramcontroller PORT MAP(
clk => clk133,
addr => xaddr,
dataIn => xdataIn,
dataOut => xdataOut,
cmd => xcmd,
ready => ready,
--chipClk => MEM_Clk,
--chipCke => MEM_Cke,
chipCS => MEM_CS,
chipWE => nWE,
chipCAS => nCAS,
chipRAS => nRAS,
chipDQML => DQML,
chipDQMH => DQMH,
chipBA => BA,
chipADDR => ADDR(11 downto 0),
chipDATA => DATA
);
main:
process (clk133, reset, up)
begin
if (reset = '1') then
currentState <= s0;
end if;
if (rising_edge(clk133inv)) then
case (currentState) is
when s0 =>
A(4) <= '1';
A(5) <= '1';
A(6) <= '1';
A(7) <= '0';
if (ready = '1') then
currentState <= s1;
end if;
nextLights <= "0000";
when s1 =>
if (waitCounter = "00001111111111111111111111111111") then
currentState <= s2;
waitCounter <= (others => '0');
else
waitCounter <= waitCounter + 1;
end if;
when s2 =>
-- write
xaddr <= "0000000000000111";
xcmd <= "11";
xdataIn <= "00000000";
xdataIn(3 downto 0) <= nextLights;
currentState <= s3;
when s3 =>
if (waitCounter = 2) then
xcmd <= "00";
waitCounter <= (others => '0');
currentState <= s4;
else
waitCounter <= waitCounter + 1;
end if;
when s4 =>
-- wait
if (ready = '1') then
waitCounter <= (others => '0');
currentState <= s5;
else
waitCounter <= waitCounter + 1;
end if;
when s5 =>
xaddr <= "0000000000000111";
xcmd <= "01";
currentState <= s6;
when s6 =>
if (waitCounter = 2) then
xcmd <= "00";
waitCounter <= (others => '0');
currentState <= s7;
else
waitCounter <= waitCounter + 1;
end if;
when s7 =>
-- wait
if (ready = '1') then
currentState <= s8;
waitCounter <= (others => '0');
else
A(4) <= '0';
A(5) <= '0';
A(6) <= '0';
A(7) <= '0';
waitCounter <= waitCounter + 1;
end if;
when s8 =>
-- read and set LEDs
A(4)<=xdataOut(0);
A(5)<=xdataOut(1);
A(6)<=xdataOut(2);
A(7)<=xdataOut(3);
currentState <= s9;
when s9 =>
if (waitCounter = "00000000111111111111111111111111") then
currentState <= s2;
nextLights <= nextLights + 1;
waitCounter <= (others => '0');
else
waitCounter <= waitCounter + 1;
end if;
end case;
end if;
end process main;
end Behavioral;
| mit | 0adb693d4439a0b39d9a42073b35eab9 | 0.586162 | 2.959489 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_pack-p.vhd | 2 | 2,496 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
--
-- $Id: tb_pack-p.vhd,v 1.2 2005/03/08 22:06:39 arniml Exp $
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package tb_pack is
function calc_crc(payload : in std_logic_vector) return std_logic_vector;
function calc_crc(payload : in unsigned) return unsigned;
function to_string(value : in integer) return string;
end tb_pack;
package body tb_pack is
function calc_crc(payload : in std_logic_vector) return std_logic_vector is
variable crc_v : std_logic_vector(6 downto 0);
variable temp_v : std_logic;
begin
crc_v := (others => '0');
for i in payload'high downto payload'low loop
temp_v := payload(i) xor crc_v(6);
crc_v(6 downto 4) := crc_v(5 downto 3);
crc_v(3) := crc_v(2) xor temp_v;
crc_v(2 downto 1) := crc_v(1 downto 0);
crc_v(0) := temp_v;
end loop;
return crc_v;
end calc_crc;
function calc_crc(payload : in unsigned) return unsigned is
begin
return unsigned(calc_crc(std_logic_vector(payload)));
end calc_crc;
function to_string(value : in integer) return string is
variable str: string (11 downto 1);
variable val: integer := value;
variable digit: natural;
variable index: natural := 0;
begin
-- Taken from:
-- textio package body. This file is part of GHDL.
-- Copyright (C) 2002 Tristan Gingold.
-- Note: the absolute value of VAL cannot be directly taken, since
-- it may be greather that the maximum value of an INTEGER.
loop
-- LRM93 7.2.6
-- (A rem B) has the sign of A and an absolute value less then
-- the absoulte value of B.
digit := abs (val rem 10);
val := val / 10;
index := index + 1;
str (index) := character'val(48 + digit);
exit when val = 0;
end loop;
if value < 0 then
index := index + 1;
str(index) := '-';
end if;
return str;
end to_string;
end tb_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: tb_pack-p.vhd,v $
-- Revision 1.2 2005/03/08 22:06:39 arniml
-- added integer->string conversion function
--
-- Revision 1.1 2005/02/08 21:09:20 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 5f11a65abecc6d7e659166525253d38b | 0.54367 | 3.670588 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op983_10.vhdl | 1 | 5,996 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net1
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias2,
S => net7
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net7,
G => net3,
S => vdd
);
subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net8
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias2,
S => net9
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net4,
S => vdd
);
subnet0_subnet4_m3 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => vdd
);
subnet0_subnet4_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net10
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net5,
G => net5,
S => gnd
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net5,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net11
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net11,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | c7d2fc23c151e45a25eefd613e7a0b70 | 0.577885 | 3.127804 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/lpm_counter1.vhd | 1 | 4,361 | -- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: lpm_counter1.vhd
-- Megafunction Name(s):
-- lpm_counter
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_counter1 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cnt_en : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END lpm_counter1;
ARCHITECTURE SYN OF lpm_counter1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
cnt_en : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(9 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 10
)
PORT MAP (
aclr => aclr,
clock => clock,
cnt_en => cnt_en,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASETV NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "1"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "0"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "0"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "0"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSETV NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: nBit NUMERIC "10"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "10"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cnt_en 0 0 0 0 INPUT NODEFVAL cnt_en
-- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL q[9..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 10 0 @q 0 0 10 0
-- Retrieval info: CONNECT: @cnt_en 0 0 0 0 cnt_en 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_counter1_inst.vhd TRUE
| gpl-2.0 | de28834e6df327dafa4e4f3487585169 | 0.648246 | 3.643275 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_sim/tb_adsr.vhd | 5 | 1,510 | -------------------------------------------------------------------------------
-- Date $Date: 2005/04/12 19:09:27 $
-- Author $Author: Gideon $
-- Revision $Revision: 1.1 $
-- Log $Log: oscillator.vhd,v $
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity tb_adsr is
end tb_adsr;
architecture tb of tb_adsr is
signal clk : std_logic := '0';
signal reset : std_logic;
signal gate : std_logic;
signal attack : std_logic_vector(3 downto 0);
signal decay : std_logic_vector(3 downto 0);
signal sustain : std_logic_vector(3 downto 0);
signal release : std_logic_vector(3 downto 0);
signal env_out : std_logic_vector(7 downto 0);
signal env_state: std_logic_vector(1 downto 0);
begin
clk <= not clk after 500 ns;
mut: entity work.adsr
port map(
clk => clk,
reset => reset,
gate => gate,
attack => X"5",
decay => X"7",
sustain => X"A",
release => X"5",
env_state=> env_state,
env_out => env_out );
reset <= '1', '0' after 20 us;
process
begin
gate <= '0';
wait for 100 us;
gate <= '1';
wait for 150 ms;
gate <= '0';
wait;
end process;
end tb;
| gpl-3.0 | 76bf9d6c065aea5eaba0a22f5854e81d | 0.455629 | 3.765586 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op986_9.vhdl | 1 | 5,009 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net6,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net5,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net6,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias2,
S => net3
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 1b361359c3faa63470ac17d8f55bf5b6 | 0.580954 | 3.180317 | false | false | false | false |
chrismasters/fpga-space-invaders | project/ipcore_dir/ram/simulation/bmg_stim_gen.vhd | 1 | 7,564 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(8,8);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(9 DOWNTO 0) <= WRITE_ADDR(9 DOWNTO 0);
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| mit | 940c56f07ce58f892b5cc0801fb3a095 | 0.557774 | 3.772569 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/IntermediateBufferConv.vhd | 1 | 2,819 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_F8MKfI
-- /___/ /\ Timestamp : 04/05/2014 20:58:17
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use work.RetinaParameters.ALL;
entity IntermediateBufferConv is
port ( clk : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_VERT_CONV_BW-1 downto 0);
rst : in std_logic;
enableOut : out std_logic;
outputData : out T_INPUT_HORIZONTAL_CONVOLUTION
);
end IntermediateBufferConv;
architecture BEHAVIORAL of IntermediateBufferConv is
signal outputArray: T_INPUT_HORIZONTAL_CONVOLUTION := (others => (others => '0'));
signal enables: std_logic_vector(KERNEL_SIZE-2 downto 0);
signal counter1: integer range 0 to (KERNEL_SIZE*NUMBER_OF_SCALES)-1 := 0;
signal counter2: integer range 0 to (NUMBER_OF_SCALES-1) := 0;
component IntermediateFifoConv is
port ( clk : in std_logic;
rst : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_VERT_CONV_BW-1 downto 0);
enableOut : out std_logic;
outputData : out std_logic_vector (OUT_VERT_CONV_BW-1 downto 0)
);
end component;
begin
fifo0: IntermediateFifoConv
port map(
clk => clk,
rst => rst,
enableIn => enableIn,
inputValue => inputValue,
enableOut => enables(0),
outputData => outputArray(1)
);
gfifo: for i in 1 to KERNEL_SIZE-2 generate
fifoX: IntermediateFifoConv
port map(
clk => clk,
rst => rst,
enableIn => enables(i-1),
inputValue => outputArray(i),
enableOut => enables(i),
outputData => outputArray(i+1)
);
end generate gfifo;
proceso1: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
--outputArray <= (others => (others => '0'));
counter1 <= 0;
counter2 <= 0;
enableOut <= '0';
else
if enableIn = '1' then
outputArray(0) <= inputValue;
if counter1 = (KERNEL_SIZE*NUMBER_OF_SCALES)-1 then
-------WORKS ONLY FOR NUMBER_OF_SCALES > 2 ???????
if counter2 = NUMBER_OF_SCALES-1 then
counter2 <= 0;
counter1 <= 0;
else
counter2 <= counter2+1;
end if;
enableOut <= '1';
else
counter1 <= counter1 +1;
enableOut <= '0';
end if;
else
enableOut <= '0';
end if;
end if;
end if;--end if rising_edge(clk)
end process proceso1;
outputData <= outputArray;
end BEHAVIORAL;
| gpl-3.0 | 9758261e0df0ea5383de1de36eaf8e51 | 0.568996 | 3.149721 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/iec_interface/vhdl_source/s3_iec.vhd | 5 | 6,091 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity s3_iec is
port (
clk_66 : in std_logic;
switch : in std_logic_vector(5 downto 0);
--
leds : out std_logic_vector(7 downto 0);
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
txd : out std_logic;
rxd : in std_logic;
--
iec_atn : inout std_logic;
iec_data : inout std_logic;
iec_clock : inout std_logic;
iec_reset : in std_logic );
end s3_iec;
architecture structural of s3_iec is
signal reset_in : std_logic;
signal atn_o, atn_i : std_logic;
signal clk_o, clk_i : std_logic;
signal data_o, data_i : std_logic;
signal error : std_logic_vector(1 downto 0);
signal send_byte : std_logic;
signal send_data : std_logic_vector(7 downto 0);
signal send_last : std_logic;
signal send_busy : std_logic;
signal recv_dav : std_logic;
signal recv_data : std_logic_vector(7 downto 0);
signal recv_last : std_logic;
signal recv_attention : std_logic;
signal do_tx : std_logic;
signal tx_done : std_logic;
signal txchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal test_vector : std_logic_vector(6 downto 0);
signal test_vector_d : std_logic_vector(6 downto 0);
signal test_trigger : std_logic;
type t_state is (start, idle, tx2, tx3);
signal state : t_state;
begin
reset_in <= iec_reset xor switch(1);
leds(0) <= error(0) or error(1);
leds(1) <= reset_in;
leds(2) <= not iec_atn;
leds(3) <= iec_data;
leds(4) <= iec_clock;
leds(5) <= not atn_o;
leds(6) <= clk_o;
leds(7) <= data_o;
iec_atn <= '0' when atn_o='0' else 'Z'; -- open drain
iec_clock <= '0' when clk_o='0' else 'Z'; -- open drain
iec_data <= '0' when data_o='0' else 'Z'; -- open drain
atn_i <= iec_atn;
clk_i <= iec_clock;
data_i <= iec_data;
disp_seg2(0) <= recv_attention;
disp_seg2(1) <= recv_last;
disp_seg2(2) <= test_trigger;
disp_seg2(7 downto 3) <= (others => '0');
iec: entity work.iec_interface
generic map (
tick_div => 333 )
port map (
clock => clk_66,
reset => reset_in,
iec_atn_i => atn_i,
iec_atn_o => atn_o,
iec_clk_i => clk_i,
iec_clk_o => clk_o,
iec_data_i => data_i,
iec_data_o => data_o,
state_out => disp_seg1,
talker => switch(0),
error => error,
send_byte => send_byte,
send_data => send_data,
send_last => send_last,
send_attention => '0',
send_busy => send_busy,
recv_dav => recv_dav,
recv_data => recv_data,
recv_last => recv_last,
recv_attention => recv_attention );
my_tx: entity work.tx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
dotx => do_tx,
txchar => txchar,
txd => txd,
done => tx_done );
my_rx: entity work.rx
generic map (579)
port map (
clk => clk_66,
reset => reset_in,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
send_byte <= rx_ack;
send_data <= rxchar;
send_last <= '0';
test_trigger <= '1' when (test_vector /= test_vector_d) else '0';
process(clk_66)
function to_hex(i : std_logic_vector(3 downto 0)) return std_logic_vector is
begin
case i is
when X"0"|X"1"|X"2"|X"3"|X"4"|X"5"|X"6"|X"7"|X"8"|X"9" =>
return X"3" & i;
when X"A" => return X"41";
when X"B" => return X"42";
when X"C" => return X"43";
when X"D" => return X"44";
when X"E" => return X"45";
when X"F" => return X"46";
when others => return X"3F";
end case;
end function;
begin
if rising_edge(clk_66) then
do_tx <= '0';
test_vector <= reset_in & atn_i & clk_i & data_i & atn_o & clk_o & data_o;
test_vector_d <= test_vector;
case state is
when start =>
txchar <= X"2D";
do_tx <= '1';
state <= idle;
when idle =>
if recv_dav='1' then
txchar <= to_hex(recv_data(7 downto 4));
do_tx <= '1';
state <= tx2;
end if;
when tx2 =>
if tx_done = '1' and do_tx='0' then
txchar <= to_hex(recv_data(3 downto 0));
do_tx <= '1';
state <= tx3;
end if;
when tx3 =>
if tx_done = '1' and do_tx='0' then
txchar <= "001000" & recv_last & recv_attention; -- !=atn @=end #=end atn
do_tx <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset_in='1' then
txchar <= X"00";
do_tx <= '0';
state <= start;
end if;
end if;
end process;
end structural;
| gpl-3.0 | 552f8a6d0b509a2101e16b4feadfbc5c | 0.42571 | 3.614837 | false | false | false | false |
chrismasters/fpga-space-invaders | project/i8080opcodes.vhd | 1 | 16,757 | -- created based on http://neil.franklin.ch/Info_Texts/Instruction_Set_8080
-- 20|30: unused in 8080, RIM and SIM only in 8085
-- 40|49|52|5B|64|6D|7F: are all NOPs
-- 76: would be MOV M,M (3 cycle NOP) but used for HLT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
package opcodes is
constant opcNOP : std_logic_vector(7 downto 0) := X"00";
constant opcLXI_B : std_logic_vector(7 downto 0) := X"01"; -- nnnn
constant opcSTAX_B : std_logic_vector(7 downto 0) := X"02";
constant opcINX_B : std_logic_vector(7 downto 0) := X"03";
constant opcINR_B : std_logic_vector(7 downto 0) := X"04";
constant opcDCR_B : std_logic_vector(7 downto 0) := X"05";
constant opcMVI_B : std_logic_vector(7 downto 0) := X"06"; -- nn
constant opcRLC : std_logic_vector(7 downto 0) := X"07";
constant opcDAD_B : std_logic_vector(7 downto 0) := X"09";
constant opcLDAX_B : std_logic_vector(7 downto 0) := X"0A";
constant opcDCX_B : std_logic_vector(7 downto 0) := X"0B";
constant opcINR_C : std_logic_vector(7 downto 0) := X"0C";
constant opcDCR_C : std_logic_vector(7 downto 0) := X"0D";
constant opcMVI_C : std_logic_vector(7 downto 0) := X"0E"; -- nn
constant opcRRC : std_logic_vector(7 downto 0) := X"0F";
constant opcLXI_D : std_logic_vector(7 downto 0) := X"11"; -- nnnn
constant opcSTAX_D : std_logic_vector(7 downto 0) := X"12";
constant opcINX_D : std_logic_vector(7 downto 0) := X"13";
constant opcINR_D : std_logic_vector(7 downto 0) := X"14";
constant opcDCR_D : std_logic_vector(7 downto 0) := X"15";
constant opcMVI_D : std_logic_vector(7 downto 0) := X"16"; -- nn
constant opcRAL : std_logic_vector(7 downto 0) := X"17";
constant opcDAD_D : std_logic_vector(7 downto 0) := X"19";
constant opcLDAX_D : std_logic_vector(7 downto 0) := X"1A";
constant opcDCX_D : std_logic_vector(7 downto 0) := X"1B";
constant opcINR_E : std_logic_vector(7 downto 0) := X"1C";
constant opcDCR_E : std_logic_vector(7 downto 0) := X"1D";
constant opcMVI_E : std_logic_vector(7 downto 0) := X"1E"; -- nn
constant opcRAR : std_logic_vector(7 downto 0) := X"1F";
constant opcRIM : std_logic_vector(7 downto 0) := X"20";
constant opcLXI_H : std_logic_vector(7 downto 0) := X"21"; -- nnnn
constant opcSHLD : std_logic_vector(7 downto 0) := X"22"; -- nnnn
constant opcINX_H : std_logic_vector(7 downto 0) := X"23";
constant opcINR_H : std_logic_vector(7 downto 0) := X"24";
constant opcDCR_H : std_logic_vector(7 downto 0) := X"25";
constant opcMVI_H : std_logic_vector(7 downto 0) := X"26"; -- nn
constant opcDAA : std_logic_vector(7 downto 0) := X"27";
constant opcDAD_H : std_logic_vector(7 downto 0) := X"29";
constant opcLHLD : std_logic_vector(7 downto 0) := X"2A"; -- nnnn
constant opcDCX_H : std_logic_vector(7 downto 0) := X"2B";
constant opcINR_L : std_logic_vector(7 downto 0) := X"2C";
constant opcDCR_L : std_logic_vector(7 downto 0) := X"2D";
constant opcMVI_L : std_logic_vector(7 downto 0) := X"2E"; -- nn
constant opcCMA : std_logic_vector(7 downto 0) := X"2F";
constant opcSIM : std_logic_vector(7 downto 0) := X"30";
constant opcLXI_SP : std_logic_vector(7 downto 0) := X"31"; -- nnnn
constant opcSTA : std_logic_vector(7 downto 0) := X"32"; -- nnnn
constant opcINX_SP : std_logic_vector(7 downto 0) := X"33";
constant opcINR_M : std_logic_vector(7 downto 0) := X"34";
constant opcDCR_M : std_logic_vector(7 downto 0) := X"35";
constant opcMVI_M : std_logic_vector(7 downto 0) := X"36"; -- nn
constant opcSTC : std_logic_vector(7 downto 0) := X"37";
constant opcDAD_SP : std_logic_vector(7 downto 0) := X"39";
constant opcLDA : std_logic_vector(7 downto 0) := X"3A"; -- nnnn
constant opcDCX_SP : std_logic_vector(7 downto 0) := X"3B";
constant opcINR_A : std_logic_vector(7 downto 0) := X"3C";
constant opcDCR_A : std_logic_vector(7 downto 0) := X"3D";
constant opcMVI_A : std_logic_vector(7 downto 0) := X"3E"; -- nn
constant opcCMC : std_logic_vector(7 downto 0) := X"3F";
constant opcMOV_B_B : std_logic_vector(7 downto 0) := X"40";
constant opcMOV_B_C : std_logic_vector(7 downto 0) := X"41";
constant opcMOV_B_D : std_logic_vector(7 downto 0) := X"42";
constant opcMOV_B_E : std_logic_vector(7 downto 0) := X"43";
constant opcMOV_B_H : std_logic_vector(7 downto 0) := X"44";
constant opcMOV_B_L : std_logic_vector(7 downto 0) := X"45";
constant opcMOV_B_M : std_logic_vector(7 downto 0) := X"46";
constant opcMOV_B_A : std_logic_vector(7 downto 0) := X"47";
constant opcMOV_C_B : std_logic_vector(7 downto 0) := X"48";
constant opcMOV_C_C : std_logic_vector(7 downto 0) := X"49";
constant opcMOV_C_D : std_logic_vector(7 downto 0) := X"4A";
constant opcMOV_C_E : std_logic_vector(7 downto 0) := X"4B";
constant opcMOV_C_H : std_logic_vector(7 downto 0) := X"4C";
constant opcMOV_C_L : std_logic_vector(7 downto 0) := X"4D";
constant opcMOV_C_M : std_logic_vector(7 downto 0) := X"4E";
constant opcMOV_C_A : std_logic_vector(7 downto 0) := X"4F";
constant opcMOV_D_B : std_logic_vector(7 downto 0) := X"50";
constant opcMOV_D_C : std_logic_vector(7 downto 0) := X"51";
constant opcMOV_D_D : std_logic_vector(7 downto 0) := X"52";
constant opcMOV_D_E : std_logic_vector(7 downto 0) := X"53";
constant opcMOV_D_H : std_logic_vector(7 downto 0) := X"54";
constant opcMOV_D_L : std_logic_vector(7 downto 0) := X"55";
constant opcMOV_D_M : std_logic_vector(7 downto 0) := X"56";
constant opcMOV_D_A : std_logic_vector(7 downto 0) := X"57";
constant opcMOV_E_B : std_logic_vector(7 downto 0) := X"58";
constant opcMOV_E_C : std_logic_vector(7 downto 0) := X"59";
constant opcMOV_E_D : std_logic_vector(7 downto 0) := X"5A";
constant opcMOV_E_E : std_logic_vector(7 downto 0) := X"5B";
constant opcMOV_E_H : std_logic_vector(7 downto 0) := X"5C";
constant opcMOV_E_L : std_logic_vector(7 downto 0) := X"5D";
constant opcMOV_E_M : std_logic_vector(7 downto 0) := X"5E";
constant opcMOV_E_A : std_logic_vector(7 downto 0) := X"5F";
constant opcMOV_H_B : std_logic_vector(7 downto 0) := X"60";
constant opcMOV_H_C : std_logic_vector(7 downto 0) := X"61";
constant opcMOV_H_D : std_logic_vector(7 downto 0) := X"62";
constant opcMOV_H_E : std_logic_vector(7 downto 0) := X"63";
constant opcMOV_H_H : std_logic_vector(7 downto 0) := X"64";
constant opcMOV_H_L : std_logic_vector(7 downto 0) := X"65";
constant opcMOV_H_M : std_logic_vector(7 downto 0) := X"66";
constant opcMOV_H_A : std_logic_vector(7 downto 0) := X"67";
constant opcMOV_L_B : std_logic_vector(7 downto 0) := X"68";
constant opcMOV_L_C : std_logic_vector(7 downto 0) := X"69";
constant opcMOV_L_D : std_logic_vector(7 downto 0) := X"6A";
constant opcMOV_L_E : std_logic_vector(7 downto 0) := X"6B";
constant opcMOV_L_H : std_logic_vector(7 downto 0) := X"6C";
constant opcMOV_L_L : std_logic_vector(7 downto 0) := X"6D";
constant opcMOV_L_M : std_logic_vector(7 downto 0) := X"6E";
constant opcMOV_L_A : std_logic_vector(7 downto 0) := X"6F";
constant opcMOV_M_B : std_logic_vector(7 downto 0) := X"70";
constant opcMOV_M_C : std_logic_vector(7 downto 0) := X"71";
constant opcMOV_M_D : std_logic_vector(7 downto 0) := X"72";
constant opcMOV_M_E : std_logic_vector(7 downto 0) := X"73";
constant opcMOV_M_H : std_logic_vector(7 downto 0) := X"74";
constant opcMOV_M_L : std_logic_vector(7 downto 0) := X"75";
constant opcHLT : std_logic_vector(7 downto 0) := X"76";
constant opcMOV_M_A : std_logic_vector(7 downto 0) := X"77";
constant opcMOV_A_B : std_logic_vector(7 downto 0) := X"78";
constant opcMOV_A_C : std_logic_vector(7 downto 0) := X"79";
constant opcMOV_A_D : std_logic_vector(7 downto 0) := X"7A";
constant opcMOV_A_E : std_logic_vector(7 downto 0) := X"7B";
constant opcMOV_A_H : std_logic_vector(7 downto 0) := X"7C";
constant opcMOV_A_L : std_logic_vector(7 downto 0) := X"7D";
constant opcMOV_A_M : std_logic_vector(7 downto 0) := X"7E";
constant opcMOV_A_A : std_logic_vector(7 downto 0) := X"7F";
constant opcADD_B : std_logic_vector(7 downto 0) := X"80";
constant opcADD_C : std_logic_vector(7 downto 0) := X"81";
constant opcADD_D : std_logic_vector(7 downto 0) := X"82";
constant opcADD_E : std_logic_vector(7 downto 0) := X"83";
constant opcADD_H : std_logic_vector(7 downto 0) := X"84";
constant opcADD_L : std_logic_vector(7 downto 0) := X"85";
constant opcADD_M : std_logic_vector(7 downto 0) := X"86";
constant opcADD_A : std_logic_vector(7 downto 0) := X"87";
constant opcADC_B : std_logic_vector(7 downto 0) := X"88";
constant opcADC_C : std_logic_vector(7 downto 0) := X"89";
constant opcADC_D : std_logic_vector(7 downto 0) := X"8A";
constant opcADC_E : std_logic_vector(7 downto 0) := X"8B";
constant opcADC_H : std_logic_vector(7 downto 0) := X"8C";
constant opcADC_L : std_logic_vector(7 downto 0) := X"8D";
constant opcADC_M : std_logic_vector(7 downto 0) := X"8E";
constant opcADC_A : std_logic_vector(7 downto 0) := X"8F";
constant opcSUB_B : std_logic_vector(7 downto 0) := X"90";
constant opcSUB_C : std_logic_vector(7 downto 0) := X"91";
constant opcSUB_D : std_logic_vector(7 downto 0) := X"92";
constant opcSUB_E : std_logic_vector(7 downto 0) := X"93";
constant opcSUB_H : std_logic_vector(7 downto 0) := X"94";
constant opcSUB_L : std_logic_vector(7 downto 0) := X"95";
constant opcSUB_M : std_logic_vector(7 downto 0) := X"96";
constant opcSUB_A : std_logic_vector(7 downto 0) := X"97";
constant opcSBB_B : std_logic_vector(7 downto 0) := X"98";
constant opcSBB_C : std_logic_vector(7 downto 0) := X"99";
constant opcSBB_D : std_logic_vector(7 downto 0) := X"9A";
constant opcSBB_E : std_logic_vector(7 downto 0) := X"9B";
constant opcSBB_H : std_logic_vector(7 downto 0) := X"9C";
constant opcSBB_L : std_logic_vector(7 downto 0) := X"9D";
constant opcSBB_M : std_logic_vector(7 downto 0) := X"9E";
constant opcSBB_A : std_logic_vector(7 downto 0) := X"9F";
constant opcANA_B : std_logic_vector(7 downto 0) := X"A0";
constant opcANA_C : std_logic_vector(7 downto 0) := X"A1";
constant opcANA_D : std_logic_vector(7 downto 0) := X"A2";
constant opcANA_E : std_logic_vector(7 downto 0) := X"A3";
constant opcANA_H : std_logic_vector(7 downto 0) := X"A4";
constant opcANA_L : std_logic_vector(7 downto 0) := X"A5";
constant opcANA_M : std_logic_vector(7 downto 0) := X"A6";
constant opcANA_A : std_logic_vector(7 downto 0) := X"A7";
constant opcXRA_B : std_logic_vector(7 downto 0) := X"A8";
constant opcXRA_C : std_logic_vector(7 downto 0) := X"A9";
constant opcXRA_D : std_logic_vector(7 downto 0) := X"AA";
constant opcXRA_E : std_logic_vector(7 downto 0) := X"AB";
constant opcXRA_H : std_logic_vector(7 downto 0) := X"AC";
constant opcXRA_L : std_logic_vector(7 downto 0) := X"AD";
constant opcXRA_M : std_logic_vector(7 downto 0) := X"AE";
constant opcXRA_A : std_logic_vector(7 downto 0) := X"AF";
constant opcORA_B : std_logic_vector(7 downto 0) := X"B0";
constant opcORA_C : std_logic_vector(7 downto 0) := X"B1";
constant opcORA_D : std_logic_vector(7 downto 0) := X"B2";
constant opcORA_E : std_logic_vector(7 downto 0) := X"B3";
constant opcORA_H : std_logic_vector(7 downto 0) := X"B4";
constant opcORA_L : std_logic_vector(7 downto 0) := X"B5";
constant opcORA_M : std_logic_vector(7 downto 0) := X"B6";
constant opcORA_A : std_logic_vector(7 downto 0) := X"B7";
constant opcCMP_B : std_logic_vector(7 downto 0) := X"B8";
constant opcCMP_C : std_logic_vector(7 downto 0) := X"B9";
constant opcCMP_D : std_logic_vector(7 downto 0) := X"BA";
constant opcCMP_E : std_logic_vector(7 downto 0) := X"BB";
constant opcCMP_H : std_logic_vector(7 downto 0) := X"BC";
constant opcCMP_L : std_logic_vector(7 downto 0) := X"BD";
constant opcCMP_M : std_logic_vector(7 downto 0) := X"BE";
constant opcCMP_A : std_logic_vector(7 downto 0) := X"BF";
constant opcRNZ : std_logic_vector(7 downto 0) := X"C0";
constant opcPOP_B : std_logic_vector(7 downto 0) := X"C1";
constant opcJNZ : std_logic_vector(7 downto 0) := X"C2"; -- nnnn
constant opcJMP : std_logic_vector(7 downto 0) := X"C3"; -- nnnn
constant opcCNZ : std_logic_vector(7 downto 0) := X"C4"; -- nnnn
constant opcPUSH_B : std_logic_vector(7 downto 0) := X"C5";
constant opcADI : std_logic_vector(7 downto 0) := X"C6"; -- nn
constant opcRST_0 : std_logic_vector(7 downto 0) := X"C7";
constant opcRZ : std_logic_vector(7 downto 0) := X"C8";
constant opcRET : std_logic_vector(7 downto 0) := X"C9";
constant opcJZ : std_logic_vector(7 downto 0) := X"CA"; -- nnnn
constant opcCZ : std_logic_vector(7 downto 0) := X"CC"; -- nnnn
constant opcCALL : std_logic_vector(7 downto 0) := X"CD"; -- nnnn
constant opcACI : std_logic_vector(7 downto 0) := X"CE"; -- nn
constant opcRST_1 : std_logic_vector(7 downto 0) := X"CF";
constant opcRNC : std_logic_vector(7 downto 0) := X"D0";
constant opcPOP_D : std_logic_vector(7 downto 0) := X"D1";
constant opcJNC : std_logic_vector(7 downto 0) := X"D2"; -- nnnn
constant opcOUT : std_logic_vector(7 downto 0) := X"D3"; -- nn
constant opcCNC : std_logic_vector(7 downto 0) := X"D4"; -- nnnn
constant opcPUSH_D : std_logic_vector(7 downto 0) := X"D5";
constant opcSUI : std_logic_vector(7 downto 0) := X"D6"; -- nn
constant opcRST_2 : std_logic_vector(7 downto 0) := X"D7";
constant opcRC : std_logic_vector(7 downto 0) := X"D8";
constant opcJC : std_logic_vector(7 downto 0) := X"DA"; -- nnnn
constant opcIN : std_logic_vector(7 downto 0) := X"DB"; -- nn
constant opcCC : std_logic_vector(7 downto 0) := X"DC"; -- nnnn
constant opcSBI : std_logic_vector(7 downto 0) := X"DE"; -- nn
constant opcRST_3 : std_logic_vector(7 downto 0) := X"DF";
constant opcRPO : std_logic_vector(7 downto 0) := X"E0";
constant opcPOP_H : std_logic_vector(7 downto 0) := X"E1";
constant opcJPO : std_logic_vector(7 downto 0) := X"E2"; -- nnnn
constant opcXTHL : std_logic_vector(7 downto 0) := X"E3";
constant opcCPO : std_logic_vector(7 downto 0) := X"E4"; -- nnnn
constant opcPUSH_H : std_logic_vector(7 downto 0) := X"E5";
constant opcANI : std_logic_vector(7 downto 0) := X"E6"; -- nn
constant opcRST_4 : std_logic_vector(7 downto 0) := X"E7";
constant opcRPE : std_logic_vector(7 downto 0) := X"E8";
constant opcPCHL : std_logic_vector(7 downto 0) := X"E9";
constant opcJPE : std_logic_vector(7 downto 0) := X"EA"; -- nnnn
constant opcXCHG : std_logic_vector(7 downto 0) := X"EB";
constant opcCPE : std_logic_vector(7 downto 0) := X"EC"; -- nnnn
constant opcXRI : std_logic_vector(7 downto 0) := X"EE"; -- nn
constant opcRST_5 : std_logic_vector(7 downto 0) := X"EF";
constant opcRP : std_logic_vector(7 downto 0) := X"F0";
constant opcPOP_PSW : std_logic_vector(7 downto 0) := X"F1";
constant opcJP : std_logic_vector(7 downto 0) := X"F2"; -- nnnn
constant opcDI : std_logic_vector(7 downto 0) := X"F3";
constant opcCP : std_logic_vector(7 downto 0) := X"F4"; -- nnnn
constant opcPUSH_PSW : std_logic_vector(7 downto 0) := X"F5";
constant opcORI : std_logic_vector(7 downto 0) := X"F6"; -- nn
constant opcRST_6 : std_logic_vector(7 downto 0) := X"F7";
constant opcRM : std_logic_vector(7 downto 0) := X"F8";
constant opcSPHL : std_logic_vector(7 downto 0) := X"F9";
constant opcJM : std_logic_vector(7 downto 0) := X"FA"; -- nnnn
constant opcEI : std_logic_vector(7 downto 0) := X"FB";
constant opcCM : std_logic_vector(7 downto 0) := X"FC"; -- nnnn
constant opcCPI : std_logic_vector(7 downto 0) := X"FE"; -- nn
constant opcRST_7 : std_logic_vector(7 downto 0) := X"FF";
end opcodes;
package body opcodes is
end opcodes; | mit | 0a6378237646f6b25265b5ba1af39d18 | 0.612341 | 2.532417 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/lpm_dff0.vhd | 1 | 4,183 | -- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff0.vhd
-- Megafunction Name(s):
-- lpm_ff
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff0 IS
PORT
(
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
enable : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END lpm_dff0;
ARCHITECTURE SYN OF lpm_dff0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
enable : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 32
)
PORT MAP (
enable => enable,
aclr => aclr,
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASETV NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "1"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSETV NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "32"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-- Retrieval info: USED_PORT: enable 0 0 0 0 INPUT NODEFVAL enable
-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
-- Retrieval info: CONNECT: @enable 0 0 0 0 enable 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff0_inst.vhd TRUE
| gpl-2.0 | a0c87db9a5d99447ed33e2befa66d462 | 0.638059 | 3.581336 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op334_0sk1_0.vhdl | 1 | 5,607 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 2.94e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 2.94e-05,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => W_0,
W_0init => 7.635e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => Wcasc_2,
Wcasc_2init => 7.215e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => Wcasc_2,
Wcasc_2init => 7.215e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias3,
S => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.29e-05,
W => Wcm_1,
Wcm_1init => 4.67e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.29e-05,
W => Wcmout_1,
Wcmout_1init => 4.975e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => (pfak)*(WBias),
WBiasinit => 3.55e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.05e-06,
W => (pfak)*(WBias),
WBiasinit => 3.55e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.05e-06,
W => WBias,
WBiasinit => 3.55e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => WBias,
WBiasinit => 3.55e-06
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => WBias,
WBiasinit => 3.55e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.05e-06,
W => WBias,
WBiasinit => 3.55e-06
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 25b78f2a1b8b370ddab6502b36aa20b0 | 0.590869 | 3.012896 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op336_2sk1_0.vhdl | 1 | 7,586 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.8e-06,
W => Wdiff_0,
Wdiff_0init => 9.05e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.8e-06,
W => Wdiff_0,
Wdiff_0init => 9.05e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.6e-06,
W => W_0,
W_0init => 6.1e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.8e-06,
W => Wdiff_0,
Wdiff_0init => 9.05e-06,
scope => private
)
port map(
D => net6,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.8e-06,
W => Wdiff_0,
Wdiff_0init => 9.05e-06,
scope => private
)
port map(
D => net6,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 6.8e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 7.55e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 6.8e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 7.55e-06,
scope => private
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 6.8e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 7.55e-06,
scope => private
)
port map(
D => net2,
G => net6,
S => vdd
);
subnet0_subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 6.8e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 7.55e-06,
scope => private
)
port map(
D => net3,
G => net6,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 5.4e-06,
W => Wsrc_2,
Wsrc_2init => 1.65e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc_2,
Lsrc_2init => 5.4e-06,
W => Wsrc_2,
Wsrc_2init => 1.65e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Csrc_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.3e-06,
W => Wcm_1,
Wcm_1init => 2.3e-06,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 2.3e-06,
W => Wcmcout_1,
Wcmcout_1init => 5.535e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 2.6e-06,
W => (pfak)*(WBias),
WBiasinit => 1.85e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.6e-06,
W => (pfak)*(WBias),
WBiasinit => 1.85e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.6e-06,
W => WBias,
WBiasinit => 1.85e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.6e-06,
W => WBias,
WBiasinit => 1.85e-05
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.6e-06,
W => WBias,
WBiasinit => 1.85e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.6e-06,
W => WBias,
WBiasinit => 1.85e-05
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net8,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net8,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net8,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 082b6150207134e84ddf9e949cc86d7e | 0.581202 | 2.862642 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/coregen/fifo_xlnx_2Kx36_2clk.vhd | 2 | 5,892 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2007 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file fifo_xlnx_2Kx36_2clk.vhd when simulating
-- the core, fifo_xlnx_2Kx36_2clk. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY fifo_xlnx_2Kx36_2clk IS
port (
din: IN std_logic_VECTOR(35 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(35 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
rd_data_count: OUT std_logic_VECTOR(11 downto 0);
wr_data_count: OUT std_logic_VECTOR(11 downto 0));
END fifo_xlnx_2Kx36_2clk;
ARCHITECTURE fifo_xlnx_2Kx36_2clk_a OF fifo_xlnx_2Kx36_2clk IS
-- synthesis translate_off
component wrapped_fifo_xlnx_2Kx36_2clk
port (
din: IN std_logic_VECTOR(35 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(35 downto 0);
empty: OUT std_logic;
full: OUT std_logic;
rd_data_count: OUT std_logic_VECTOR(11 downto 0);
wr_data_count: OUT std_logic_VECTOR(11 downto 0));
end component;
-- Configuration specification
for all : wrapped_fifo_xlnx_2Kx36_2clk use entity XilinxCoreLib.fifo_generator_v4_3(behavioral)
generic map(
c_has_int_clk => 0,
c_rd_freq => 1,
c_wr_response_latency => 1,
c_has_srst => 0,
c_has_rd_data_count => 1,
c_din_width => 36,
c_has_wr_data_count => 1,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan3",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 0,
c_dout_width => 36,
c_msgon_val => 1,
c_rd_depth => 2048,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 12,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 11,
c_use_fwft_data_count => 1,
c_has_almost_empty => 0,
c_rd_data_count_width => 12,
c_enable_rlocs => 0,
c_wr_pntr_width => 11,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 12,
c_preload_regs => 1,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 2046,
c_wr_depth => 2048,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_thresh_assert_val => 4,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 2047,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "2kx18",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fifo_xlnx_2Kx36_2clk
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count);
-- synthesis translate_on
END fifo_xlnx_2Kx36_2clk_a;
| gpl-2.0 | 405c5d844786c655b34f63f69a55ff4e | 0.570774 | 3.361095 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/zpu_exec.vhd | 5 | 25,864 | ------------------------------------------------------------------------------
---- ----
---- ZPU Exec ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has a third (8-bit) port for ----
---- fetching instructions. This modification reduces the LUT size by ----
---- approximately 10% and increases the performance with 21%. ----
---- Needs external dual ported memory, plus single cycle external ----
---- program memory. It also requires a different linker script to ----
---- place the text segment on a logically different address to stick to ----
---- the single-, flat memory model programming paradigm. ----
---- ----
---- To Do: ----
---- Add a 'ready' for the external code memory ----
---- More thorough testing, cleanup code a bit more ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_exec(Behave) (Entity and architecture) ----
---- File name: zpu_exec.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_exec is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- BRAM (data, bss and stack)
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- BRAM (text)
c_addr_o : out unsigned(g_prog_size-1 downto 0) := (others => '0'); -- BRAM code address
c_i : in unsigned(c_opcode_width-1 downto 0);
-- Memory mapped I/O
mem_busy_i : in std_logic;
data_i : in unsigned(31 downto 0);
data_o : out unsigned(31 downto 0);
addr_o : out unsigned(g_addr_size-1 downto 0);
write_en_o : out std_logic;
read_en_o : out std_logic);
end entity zpu_exec;
architecture Behave of zpu_exec is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant SP_START_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant SP_START : unsigned(g_stack_size-1 downto 2):=
SP_START_1(g_stack_size-1 downto 2);
constant IO_BIT : integer:=g_addr_size-1; -- Address bit to determine this is an I/O
-- Program counter
signal pc_r : unsigned(c_max_addr_bit downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=SP_START;
signal idim_r : std_logic:='0';
-- BRAM (text, some data, bss and stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
-- We also use the B port to fetch instructions.
signal b_we_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal posted_wr_a : std_logic;
-- State machine.
type state_t is (st_fetch, st_write_io_done, st_execute, st_add, st_or,
st_and, st_store, st_read_io, st_write_io,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_resync;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_i;
c_addr_o <= pc_r(g_prog_size-1 downto 0);
-- c_addr_o(g_prog_size-1 downto 2) <= pc_r(g_prog_size-1 downto 2);
-- c_addr_o(1 downto 0) <= not pc_r(1 downto 0); -- fix big endianess
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
d_opcode <= dec_emulate;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
end process decode_control;
data_o <= b_i;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
write_en_o <= '0';
read_en_o <= '0';
dbg_o.b_inst <= '0';
posted_wr_a <= '0';
if reset_i='1' then
state <= st_resync;
sp_r <= SP_START;
pc_r <= (others => '0');
idim_r <= '0';
a_addr_r <= (others => '0');
b_addr_r <= (others => '0');
a_we_r <= '0';
b_we_r <= '0';
a_r <= (others => '0');
b_r <= (others => '0');
in_irq_r <= '0';
addr_r <= (others => '0');
else -- reset_i/='1'
a_we_r <= '0';
b_we_r <= '0';
-- This saves LUTs, by explicitly declaring that the
-- a_o can be left at whatever value if a_we_r is
-- not set.
a_r <= (others => g_dont_care);
b_r <= (others => g_dont_care);
sp_offset:=(others => g_dont_care);
a_addr_r <= (others => g_dont_care);
b_addr_r <= (others => g_dont_care);
addr_r <= a_i(g_addr_size-1 downto 0);
d_opcode_r <= d_opcode;
opcode_r <= opcode;
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_execute =>
state <= st_fetch;
-- At this point:
-- b_i contains opcode word
-- a_i contains top of stack
pc_r <= pc_r+1;
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_addr_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, c_max_addr_bit+1); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_resync;
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
posted_wr_a <= '1';
state <= st_resync;
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => g_dont_care);
a_r(c_max_addr_bit downto 0) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
a_addr_r <= sp_r;
b_addr_r <= sp_r+sp_offset;
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_resync;
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_load =>
-- Push([Pop()])
if a_i(IO_BIT)='1' then
addr_r <= a_i(g_addr_size-1 downto 0);
read_en_o <= '1';
state <= st_read_io;
else
a_addr_r <= a_i(a_addr_r'range);
posted_wr_a <= '1';
state <= st_resync;
end if;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
b_addr_r <= sp_r+1;
sp_r <= sp_r+1;
if a_i(IO_BIT)='1' then
state <= st_write_io;
else
state <= st_store;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_resync;
when dec_nop =>
-- Default, keep addressing to of the stack (A)
a_addr_r <= sp_r;
when others =>
null;
end case;
when st_read_io =>
-- Wait until memory I/O isn't busy
a_addr_r <= sp_r;
a_r <= data_i;
if mem_busy_i='0' then
state <= st_fetch;
a_we_r <= '1';
end if;
when st_write_io =>
-- [A]=B
sp_r <= sp_r+1;
write_en_o <= '1';
addr_r <= a_i(g_addr_size-1 downto 0);
state <= st_write_io_done;
when st_write_io_done =>
-- Wait until memory I/O isn't busy
if mem_busy_i='0' then
state <= st_resync;
end if;
when st_fetch =>
-- We need to resync. During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_we_r <= posted_wr_a;
a_r <= a_i;
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_decode;
when st_decode =>
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt;
end if;
-- during the st_execute cycle we'll be fetching SP+1
a_addr_r <= sp_r;
b_addr_r <= sp_r+1;
state <= st_execute;
when st_store =>
sp_r <= sp_r+1;
a_we_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_resync;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
end if; -- else reset_i/='1'
end if; -- rising_edge(clk_i)
end process opcode_control;
addr_o <= addr_r;
end architecture Behave; -- Entity: zpu_exec
| gpl-3.0 | f5f048651aea65af1c43495b4449985e | 0.317198 | 4.899413 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/pulse_stretch/vhdl_source/pulse_stretch.vhd | 5 | 696 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_stretch is
generic (
g_duration : natural := 200 );
port (
clock : in std_logic;
reset : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic );
end;
architecture rtl of pulse_stretch is
signal count : natural range 0 to g_duration-1;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
pulse_out <= '0';
count <= 0;
elsif pulse_in='1' then
pulse_out <= '1';
count <= g_duration-1;
elsif count = 0 then
pulse_out <= '0';
else
count <= count - 1;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 1dff09f3a8714b5396950ac397ee283b | 0.596264 | 2.740157 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/lpm_add_sub1.vhd | 1 | 4,562 | -- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: lpm_add_sub1.vhd
-- Megafunction Name(s):
-- lpm_add_sub
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_add_sub1 IS
PORT
(
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
cout : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_add_sub1;
ARCHITECTURE SYN OF lpm_add_sub1 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
cout : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
result <= sub_wire1(7 DOWNTO 0);
lpm_add_sub_component : lpm_add_sub
GENERIC MAP (
lpm_direction => "ADD",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
lpm_type => "LPM_ADD_SUB",
lpm_width => 8
)
PORT MAP (
dataa => dataa,
datab => datab,
cout => sub_wire0,
result => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: Function NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "0"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: dataa 0 0 8 0 INPUT NODEFVAL dataa[7..0]
-- Retrieval info: USED_PORT: datab 0 0 8 0 INPUT NODEFVAL datab[7..0]
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL result[7..0]
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: CONNECT: @dataa 0 0 8 0 dataa 0 0 8 0
-- Retrieval info: CONNECT: @datab 0 0 8 0 datab 0 0 8 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub1_inst.vhd TRUE
| gpl-2.0 | 678d9279b15d24d25d5b454ee6b09a38 | 0.651688 | 3.555729 | false | false | false | false |
chrismasters/fpga-notes | sdramcontroller/ipcore_dir/clks/simulation/clks_tb.vhd | 1 | 6,147 | -- file: clks_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clks_tb is
end clks_tb;
architecture test of clks_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.250 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bits of the sampling counters
signal COUNT : std_logic_vector(2 downto 1);
signal COUNTER_RESET : std_logic := '0';
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(2 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component clks_exdes
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(2 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic_vector(2 downto 1)
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
COUNTER_RESET <= '1';
wait for (PER1*20);
COUNTER_RESET <= '0';
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clks_exdes
generic map (
TCQ => TCQ)
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
| mit | 419806279013e437c0acc466604d0463 | 0.63836 | 4.289602 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_bfm/slot_bus_master_bfm.vhd | 5 | 2,373 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
use work.slot_bus_master_bfm_pkg.all;
entity slot_bus_master_bfm is
generic (
g_name : string );
port (
clock : in std_logic;
req : out t_slot_req;
resp : in t_slot_resp );
end slot_bus_master_bfm;
architecture bfm of slot_bus_master_bfm is
shared variable this : p_slot_bus_master_bfm_object := null;
signal bound : boolean := false;
type t_state is (idle, exec);
signal state : t_state := idle;
signal delay : integer := 0;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_slot_bus_master_bfm(g_name, this);
bound <= true;
wait;
end process;
process(clock)
begin
if rising_edge(clock) then
req.bus_write <= '0';
req.io_read <= '0';
req.io_write <= '0';
this.irq_pending := (resp.irq = '1');
case state is
when idle =>
req <= c_slot_req_init;
if bound then
delay <= 3;
if this.command /= e_slot_none then
req.io_address <= this.address;
req.bus_address <= this.address;
req.data <= this.data;
end if;
case this.command is
when e_slot_io_read =>
state <= exec;
when e_slot_io_write =>
state <= exec;
when e_slot_bus_read =>
state <= exec;
when e_slot_bus_write =>
req.bus_write <= '1';
state <= exec;
when others =>
null;
end case;
end if;
when exec =>
if delay=0 then
case this.command is
when e_slot_io_read =>
req.io_read <= '1';
when e_slot_io_write =>
req.io_write <= '1';
when others =>
null;
end case;
if resp.reg_output='1' then
this.data := resp.data;
else
this.data := (others => 'X');
end if;
this.command := e_slot_none;
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
end if;
end process;
end bfm;
| gpl-3.0 | d51932f751f20150816efbdbff0f7572 | 0.494311 | 3.43913 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op966_12.vhdl | 1 | 6,799 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias3,
S => net7
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias3,
S => net9
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net9,
G => net2,
S => gnd
);
subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net10,
G => net2,
S => gnd
);
subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias3,
S => net10
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net5,
G => net3,
S => vdd
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net4,
G => net4,
S => vdd
);
subnet0_subnet4_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net4,
S => vdd
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net11
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net11,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net12,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net12
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 16099bea2e5cd5398b0ecac9cc967bcb | 0.57332 | 3.083447 | false | false | false | false |
KB777/1541UltimateII | fpga/fpga_top/ultimate_fpga/vhdl_sim/harness_logic_32.vhd | 1 | 14,049 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.cart_slot_pkg.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.command_if_pkg.all;
library std;
use std.textio.all;
entity harness_logic_32 is
end entity;
architecture tb of harness_logic_32 is
constant c_uart_divisor : natural := 50;
signal PHI2 : std_logic := '0';
signal RSTn : std_logic := 'H';
signal DOTCLK : std_logic := '1';
signal BUFFER_ENn : std_logic := '1';
signal BA : std_logic := '0';
signal DMAn : std_logic := '1';
signal EXROMn : std_logic;
signal GAMEn : std_logic;
signal ROMHn : std_logic := '1';
signal ROMLn : std_logic := '1';
signal IO1n : std_logic := '1';
signal IO2n : std_logic := '1';
signal IRQn : std_logic := '1';
signal NMIn : std_logic := '1';
signal PWM_OUT : std_logic_vector(1 downto 0);
signal IEC_ATN : std_logic := '1';
signal IEC_DATA : std_logic := '1';
signal IEC_CLOCK : std_logic := '1';
signal IEC_RESET : std_logic := '1';
signal IEC_SRQ_IN : std_logic := '1';
signal iec_atn_o : std_logic := '1';
signal iec_data_o : std_logic := '1';
signal iec_clock_o : std_logic := '1';
signal iec_reset_o : std_logic := '1';
signal iec_srq_o : std_logic := '1';
signal DISK_ACTn : std_logic; -- activity LED
signal CART_LEDn : std_logic;
signal SDACT_LEDn : std_logic;
signal MOTOR_LEDn : std_logic;
signal UART_TXD : std_logic;
signal UART_RXD : std_logic := '1';
signal SD_SSn : std_logic;
signal SD_CLK : std_logic;
signal SD_MOSI : std_logic;
signal SD_MISO : std_logic := '1';
signal SD_WP : std_logic := '1';
signal SD_CARDDETn : std_logic := '1';
signal SD_DATA : std_logic_vector(2 downto 1) := "HH";
signal BUTTON : std_logic_vector(2 downto 0) := "000";
signal SLOT_ADDR : std_logic_vector(15 downto 0);
signal SLOT_DATA : std_logic_vector(7 downto 0);
signal RWn : std_logic := '1';
signal CAS_MOTOR : std_logic := '1';
signal CAS_SENSE : std_logic := '0';
signal CAS_READ : std_logic := '0';
signal CAS_WRITE : std_logic := '0';
signal RTC_CS : std_logic;
signal RTC_SCK : std_logic;
signal RTC_MOSI : std_logic;
signal RTC_MISO : std_logic := '1';
signal FLASH_CSn : std_logic;
signal FLASH_SCK : std_logic;
signal FLASH_MOSI : std_logic;
signal FLASH_MISO : std_logic := '1';
signal ULPI_CLOCK : std_logic := '0';
signal ULPI_RESET : std_logic := '0';
signal ULPI_NXT : std_logic := '0';
signal ULPI_STP : std_logic;
signal ULPI_DIR : std_logic := '0';
signal ULPI_DATA : std_logic_vector(7 downto 0) := (others => 'H');
signal sys_clock : std_logic := '1';
signal sys_reset : std_logic := '1';
signal sys_clock_2x : std_logic := '1';
signal rx_char : std_logic_vector(7 downto 0);
signal rx_char_d : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal tx_char : std_logic_vector(7 downto 0) := X"00";
signal tx_done : std_logic;
signal do_tx : std_logic := '0';
-- memory controller interconnect
signal mem_inhibit : std_logic := '0';
signal mem_req : t_mem_req_32;
signal mem_resp : t_mem_resp_32;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal CLOCK_50 : std_logic := '0';
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal SDRAM_A : std_logic_vector(12 downto 0);
signal SDRAM_BA : std_logic_vector(1 downto 0);
signal SDRAM_DQ : std_logic_vector(7 downto 0) := (others => 'Z');
begin
sys_clock <= not sys_clock after 10 ns;
sys_clock_2x <= not sys_clock_2x after 5 ns;
sys_reset <= '1', '0' after 100 ns;
mut: entity work.ultimate_logic_32
generic map (
g_version => X"02",
g_simulation => true,
g_clock_freq => 50_000_000,
g_baud_rate => 1_000_000,
g_timer_rate => 200_000,
g_boot_rom => false,
g_video_overlay => false,
g_icap => false,
g_uart => true,
g_drive_1541 => true,
g_drive_1541_2 => false,
g_hardware_gcr => true,
g_cartridge => true,
g_command_intf => true,
g_stereo_sid => false,
g_ram_expansion => true,
g_extended_reu => false,
g_hardware_iec => false,
g_iec_prog_tim => false,
g_c2n_streamer => false,
g_c2n_recorder => false,
g_drive_sound => true,
g_rtc_chip => false,
g_rtc_timer => false,
g_usb_host => false,
g_usb_host2 => true,
g_spi_flash => true,
g_vic_copper => false,
g_sampler => false,
g_profiler => true,
g_analyzer => false )
port map (
sys_clock => sys_clock,
sys_reset => sys_reset,
ulpi_clock => ulpi_clock,
ulpi_reset => ulpi_reset,
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
mem_inhibit => mem_inhibit,
mem_req => mem_req,
mem_resp => mem_resp,
PWM_OUT => PWM_OUT,
iec_reset_i => IEC_RESET,
iec_atn_i => IEC_ATN,
iec_data_i => IEC_DATA,
iec_clock_i => IEC_CLOCK,
iec_srq_i => IEC_SRQ_IN,
iec_reset_o => iec_reset_o,
iec_atn_o => iec_atn_o,
iec_data_o => iec_data_o,
iec_clock_o => iec_clock_o,
iec_srq_o => iec_srq_o,
BUTTON => BUTTON,
DISK_ACTn => DISK_ACTn,
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
SD_DATA => SD_DATA,
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
sim_io_req => io_req,
sim_io_resp => io_resp );
i_mem_ctrl: entity work.ext_mem_ctrl_v5
generic map (
g_simulation => false )
port map (
clock => sys_clock,
clk_2x => sys_clock_2x,
reset => sys_reset,
inhibit => mem_inhibit,
is_idle => open,
req => mem_req,
resp => mem_resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_BA,
SDRAM_A => SDRAM_A,
SDRAM_DQ => SDRAM_DQ );
ULPI_CLOCK <= not ULPI_CLOCK after 8.333 ns; -- 60 MHz
ULPI_RESET <= '1', '0' after 100 ns;
PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz
RSTn <= '0', 'H' after 6 us, '0' after 100 us, 'H' after 105 us;
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp );
SLOT_DATA <= (others => 'H');
ROMHn <= '1';
ROMLn <= not PHI2 after 50 ns;
IO1n <= '1';
IO2n <= '1';
process
begin
SLOT_ADDR <= X"7F00";
RWn <= '1';
while true loop
wait until PHI2 = '0';
--SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1);
SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1);
RWn <= '1';
wait until PHI2 = '0';
RWn <= '0';
end loop;
end process;
process
begin
BA <= '1';
for i in 0 to 100 loop
wait until PHI2='0';
end loop;
BA <= '0';
for i in 0 to 10 loop
wait until PHI2='0';
end loop;
end process;
ram: entity work.dram_8
generic map(
g_cas_latency => 3,
g_burst_len_r => 4,
g_burst_len_w => 4,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2
)
port map(
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => SDRAM_A,
BA => SDRAM_BA,
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => SDRAM_DQ
);
-- i_ulpi_phy: entity work.ulpi_master_bfm
-- generic map (
-- g_given_name => "device" )
--
-- port map (
-- clock => ULPI_CLOCK,
-- reset => ULPI_RESET,
-- ulpi_nxt => ulpi_nxt,
-- ulpi_stp => ulpi_stp,
-- ulpi_dir => ulpi_dir,
-- ulpi_data => ulpi_data );
--
-- i_device: entity work.usb_device_model;
i_rx: entity work.rx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
rxd => UART_TXD,
rxchar => rx_char,
rx_ack => rx_ack );
i_tx: entity work.tx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
dotx => do_tx,
txchar => tx_char,
done => tx_done,
txd => UART_RXD );
process(sys_clock)
variable s : line;
variable char : character;
begin
if rising_edge(sys_clock) then
if rx_ack='1' then
rx_char_d <= rx_char;
char := character'val(to_integer(unsigned(rx_char)));
if rx_char = X"0D" then
-- Ignore character 13
elsif rx_char = X"0A" then
-- Writeline on character 10 (newline)
writeline(output, s);
else
-- Write to buffer
write(s, char);
end if;
end if;
if mem_resp.rack = '1' and mem_req.address < 16 then
report "Access to address " & integer'image(to_integer(mem_req.address)) severity error;
end if;
end if;
end process;
process
variable io : p_io_bus_bfm_object;
begin
wait until sys_reset='0';
wait until sys_clock='1';
bind_io_bus_bfm("io_bfm", io);
io_write(io, X"40000" + c_cart_c64_mode, X"04"); -- reset
io_write(io, X"40000" + c_cart_cartridge_type, X"06"); -- retro
io_write(io, X"40000" + c_cart_c64_mode, X"08"); -- unreset
io_write(io, X"44000" + c_cif_io_slot_base, X"7E");
io_write(io, X"44000" + c_cif_io_slot_enable, X"01");
wait for 6 us;
wait until sys_clock='1';
--io_write(io, X"42002", X"42");
wait;
end process;
process
procedure send_char(i: std_logic_vector(7 downto 0)) is
begin
if tx_done /= '1' then
wait until tx_done = '1';
end if;
wait until sys_clock='1';
tx_char <= i;
do_tx <= '1';
wait until tx_done = '0';
wait until sys_clock='1';
do_tx <= '0';
end procedure;
procedure send_string(i : string) is
variable b : std_logic_vector(7 downto 0);
begin
for n in i'range loop
b := std_logic_vector(to_unsigned(character'pos(i(n)), 8));
send_char(b);
end loop;
send_char(X"0d");
send_char(X"0a");
end procedure;
begin
wait for 2 ms;
--send_string("wd 4005000 12345678");
send_string("run");
-- send_string("m 100000");
-- send_string("w 400000F 4");
wait;
end process;
-- check timing data
process(PHI2)
begin
if falling_edge(PHI2) then
assert SLOT_DATA'last_event >= 189 ns
report "Timing error on C64 bus."
severity error;
end if;
end process;
end tb;
| gpl-3.0 | 4462be2e9fe16c0779ca49320113e358 | 0.468432 | 3.364224 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op334_4sk1_0.vhdl | 1 | 6,139 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 2.855e-05,
scope => private
)
port map(
D => net2,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7e-07,
W => Wdiff_0,
Wdiff_0init => 2.855e-05,
scope => private
)
port map(
D => net3,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => W_0,
W_0init => 7.65e-05
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => Wcasc_2,
Wcasc_2init => 5.075e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias3,
S => net2
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => Wcasc_2,
Wcasc_2init => 5.075e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias3,
S => net3
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 3.76e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias2,
S => net6
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.65e-06,
W => Wcm_1,
Wcm_1init => 4.26e-05,
scope => private
)
port map(
D => net6,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 4.65e-06,
W => Wcmout_1,
Wcmout_1init => 4.625e-05,
scope => private
)
port map(
D => net7,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 3.76e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net7
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => (pfak)*(WBias),
WBiasinit => 1.39e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 4.8e-06,
W => (pfak)*(WBias),
WBiasinit => 1.39e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 4.8e-06,
W => WBias,
WBiasinit => 1.39e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => WBias,
WBiasinit => 1.39e-05
)
port map(
D => vbias2,
G => vbias3,
S => net8
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => WBias,
WBiasinit => 1.39e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 4.8e-06,
W => WBias,
WBiasinit => 1.39e-05
)
port map(
D => net8,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net9,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net9,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net9,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 3633d9701b47287df1eb731c566fa8fd | 0.588858 | 2.972881 | false | false | false | false |
KB777/1541UltimateII | fpga/cpu_unit/mblite/hw/core/decode.vhd | 1 | 19,605 | ----------------------------------------------------------------------------------------------
--
-- Input file : decode.vhd
-- Design name : decode
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : This combined register file and decoder uses three Dual Port
-- read after write Random Access Memory components. Every clock
-- cycle three data values can be read (ra, rb and rd) and one value
-- can be stored.
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
entity decode is generic
(
G_INTERRUPT : boolean := CFG_INTERRUPT;
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL;
G_SUPPORT_SPR: boolean := true;
G_DEBUG : boolean := CFG_DEBUG
);
port
(
decode_o : out decode_out_type;
gprf_o : out gprf_out_type;
decode_i : in decode_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end decode;
architecture arch of decode is
type decode_reg_type is record
instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
immediate : std_logic_vector(15 downto 0);
is_immediate : std_logic;
interrupt : std_logic;
delay_interrupt : std_logic;
block_interrupt : std_logic;
end record;
signal r, rin : decode_out_type;
signal reg, regin : decode_reg_type;
signal wb_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
decode_o.imm <= r.imm;
decode_o.ctrl_ex <= r.ctrl_ex;
decode_o.ctrl_mem <= r.ctrl_mem;
decode_o.ctrl_wrb <= r.ctrl_wrb;
decode_o.reg_a <= r.reg_a;
decode_o.reg_b <= r.reg_b;
decode_o.hazard <= r.hazard;
decode_o.program_counter <= r.program_counter;
decode_o.fwd_dec_result <= r.fwd_dec_result;
decode_o.fwd_dec <= r.fwd_dec;
decode_o.int_ack <= r.int_ack;
decode_comb: process(decode_i,decode_i.ctrl_wrb,
decode_i.ctrl_mem_wrb,
decode_i.instruction,
decode_i.inst_valid,
decode_i.ctrl_mem_wrb.transfer_size,
r,r.ctrl_ex,r.ctrl_mem,
r.ctrl_mem.transfer_size,r.ctrl_wrb,
r.ctrl_wrb.reg_d,
r.fwd_dec,reg)
variable v : decode_out_type;
variable v_reg : decode_reg_type;
variable opcode : std_logic_vector(5 downto 0);
variable instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
variable program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
v_reg := reg;
v.int_ack := '0';
-- Default register values (NOP)
v_reg.immediate := (others => '0');
v_reg.is_immediate := '0';
v_reg.program_counter := decode_i.program_counter;
v_reg.instruction := decode_i.instruction;
if decode_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(decode_i.mem_result, decode_i.ctrl_mem_wrb.transfer_size, decode_i.alu_result(1 downto 0));
else
mem_result := decode_i.alu_result;
end if;
wb_dat_d <= mem_result;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '0';
end if;
if CFG_REG_FWD_WRB = true then
v.fwd_dec_result := mem_result;
v.fwd_dec := decode_i.ctrl_wrb;
else
v.fwd_dec_result := (others => '0');
v.fwd_dec.reg_d := (others => '0');
v.fwd_dec.reg_write := '0';
end if;
if decode_i.inst_valid = '0' then
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
-- not a hazard, just a nop
elsif (not decode_i.flush_id and r.ctrl_mem.mem_read and (compare(decode_i.instruction(20 downto 16), r.ctrl_wrb.reg_d) or compare(decode_i.instruction(15 downto 11), r.ctrl_wrb.reg_d))) = '1' then
-- A hazard occurred on register a or b
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
v.hazard := '1';
elsif CFG_MEM_FWD_WRB = false and (not decode_i.flush_id and r.ctrl_mem.mem_read and compare(decode_i.instruction(25 downto 21), r.ctrl_wrb.reg_d)) = '1' then
-- A hazard occurred on register d
-- set current instruction and program counter to 0
instruction := (others => '0');
program_counter := (others => '0');
v.hazard := '1';
elsif r.hazard = '1' then
-- Recover from hazard. Insert latched instruction
instruction := reg.instruction;
program_counter := reg.program_counter;
v.hazard := '0';
else
instruction := decode_i.instruction;
program_counter := decode_i.program_counter;
v.hazard := '0';
end if;
v.program_counter := program_counter;
opcode := instruction(31 downto 26);
v.ctrl_wrb.reg_d := instruction(25 downto 21);
v.reg_a := instruction(20 downto 16);
v.reg_b := instruction(15 downto 11);
-- SET IMM value
if reg.is_immediate = '1' then
v.imm := reg.immediate & instruction(15 downto 0);
else
v.imm := sign_extend(instruction(15 downto 0), instruction(15), 32);
end if;
-- Register if an interrupt occurs
if G_INTERRUPT = true then
if decode_i.interrupt_enable = '1' and decode_i.interrupt = '1' and reg.block_interrupt = '0' then
v_reg.interrupt := '1';
end if;
if decode_i.interrupt_enable = '0' then
v_reg.block_interrupt := '0';
end if;
end if;
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
v.ctrl_ex.operation := "00";
v.ctrl_ex.carry := CARRY_ZERO;
v.ctrl_ex.carry_keep := CARRY_KEEP;
v.ctrl_ex.delay := '0';
v.ctrl_ex.branch_cond := NOP;
v.ctrl_ex.msr_op := NOP;
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.transfer_size := WORD;
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
if G_INTERRUPT = true and (reg.interrupt = '1' and reg.delay_interrupt = '0' and decode_i.flush_id = '0' and v.hazard = '0' and r.ctrl_ex.delay = '0' and reg.is_immediate = '0') then
-- IF an interrupt occured
-- AND the current instruction is not a branch or return instruction,
-- AND the current instruction is not in a delay slot,
-- AND this is instruction is not preceded by an IMM instruction, than handle the interrupt.
v_reg.interrupt := '0';
v_reg.block_interrupt := '1'; -- because interrupt enable is cleared in exec, we block here any new interrupts until MSR_I bit is cleared.
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.int_ack := '1';
v.imm := X"00000010";
v.ctrl_wrb.reg_d := "01110"; -- link register is r14
v.ctrl_wrb.reg_write := '1';
v.ctrl_ex.msr_op := MSR_CLR_I;
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA; -- will read 0 because reg_a = 0
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
elsif (decode_i.flush_id or v.hazard) = '1' then
-- clearing these registers is not necessary, but facilitates debugging.
-- On the other hand performance improves when disabled.
if G_DEBUG = true then
v.program_counter := (others => '0');
v.ctrl_wrb.reg_d := (others => '0');
v.reg_a := (others => '0');
v.reg_b := (others => '0');
v.imm := (others => '0');
end if;
elsif is_zero(opcode(5 downto 4)) = '1' then
-- ADD, SUBTRACT OR COMPARE
-- Alu operation
v.ctrl_ex.alu_op := ALU_ADD;
-- Source operand A
if opcode(0) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_NOT_REGA;
else
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
end if;
-- Source operand B
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
-- Pass modifier for CMP and CMPU
if (compare(opcode, "000101") = '1') then
v.ctrl_ex.operation := instruction(1 downto 0);
end if;
-- Carry
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ONE;
when others => v.ctrl_ex.carry := CARRY_ALU;
end case;
-- Carry keep
if opcode(2) = '1' then
v.ctrl_ex.carry_keep := CARRY_KEEP;
else
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif (compare(opcode(5 downto 2), "1000") or compare(opcode(5 downto 2), "1010")) = '1' then
-- OR, AND, XOR, ANDN
-- ORI, ANDI, XORI, ANDNI
case opcode(1 downto 0) is
when "00" => v.ctrl_ex.alu_op := ALU_OR;
when "10" => v.ctrl_ex.alu_op := ALU_XOR;
when others => v.ctrl_ex.alu_op := ALU_AND;
end case;
if opcode(3) = '1' and compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_IMM;
elsif opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
elsif opcode(3) = '0' and compare(opcode(1 downto 0), "11") = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_NOT_REGB;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif compare(opcode, "101100") = '1' then
-- IMM instruction
v_reg.immediate := instruction(15 downto 0);
v_reg.is_immediate := '1';
elsif compare(opcode, "100100") = '1' then
-- SHIFT, SIGN EXTEND
if compare(instruction(6 downto 5), "11") = '1' then
if instruction(0) = '1' then
v.ctrl_ex.alu_op:= ALU_SEXT16;
else
v.ctrl_ex.alu_op:= ALU_SEXT8;
end if;
else
v.ctrl_ex.alu_op:= ALU_SHIFT;
v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
case instruction(6 downto 5) is
when "10" => v.ctrl_ex.carry := CARRY_ZERO;
when "01" => v.ctrl_ex.carry := CARRY_ALU;
when others => v.ctrl_ex.carry := CARRY_ARITH;
end case;
end if;
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
elsif (compare(opcode, "100110") or compare(opcode, "101110")) = '1' then
-- BRANCH UNCONDITIONAL
v.ctrl_ex.branch_cond := BNC;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_ex.delay := instruction(20);
-- Link: WRITE THE CURRENT PC TO REGISTER D. In the MEM stage, a multiplexer decides that PC is being written in case of a branch.
if instruction(18) = '1' then
-- Flag writeback
v.ctrl_wrb.reg_write := '1';
end if;
if instruction(19) = '1' then
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
v.reg_a := (others => '0'); -- select register 0 to emulate 0.
else
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
end if;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
elsif (compare(opcode, "100111") or compare(opcode, "101111")) = '1' then
-- BRANCH CONDITIONAL
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_PC;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
case v.ctrl_wrb.reg_d(2 downto 0) is
when "000" => v.ctrl_ex.branch_cond := BEQ;
when "001" => v.ctrl_ex.branch_cond := BNE;
when "010" => v.ctrl_ex.branch_cond := BLT;
when "011" => v.ctrl_ex.branch_cond := BLE;
when "100" => v.ctrl_ex.branch_cond := BGT;
when others => v.ctrl_ex.branch_cond := BGE;
end case;
if G_INTERRUPT = true then
v_reg.delay_interrupt := '1';
end if;
v.ctrl_ex.delay := v.ctrl_wrb.reg_d(4);
elsif compare(opcode, "101101") = '1' then
-- RETURN
v.ctrl_ex.branch_cond := BNC;
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
v.ctrl_ex.delay := '1';
if G_INTERRUPT = true then
if v.ctrl_wrb.reg_d(0) = '1' then
v.ctrl_ex.msr_op := MSR_SET_I;
end if;
v_reg.delay_interrupt := '1';
end if;
elsif compare(opcode(5 downto 4), "11") = '1' then
-- SW, LW
v.ctrl_ex.alu_op := ALU_ADD;
v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_ex.carry := CARRY_ZERO;
if opcode(2) = '1' then
-- Store
v.ctrl_mem.mem_write := '1';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
else
-- Load
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '1';
v.ctrl_wrb.reg_write := '1';
end if;
case opcode(1 downto 0) is
when "00" => v.ctrl_mem.transfer_size := BYTE;
when "01" => v.ctrl_mem.transfer_size := HALFWORD;
when others => v.ctrl_mem.transfer_size := WORD;
end case;
v.ctrl_ex.delay := '0';
elsif G_USE_HW_MUL = true and (compare(opcode, "010000") or compare(opcode, "011000")) = '1' then
v.ctrl_ex.alu_op := ALU_MUL;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_wrb.reg_write := '1';
elsif G_USE_BARREL = true and (compare(opcode, "010001") or compare(opcode, "011001")) = '1' then
v.ctrl_ex.alu_op := ALU_BS;
if opcode(3) = '1' then
v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
else
v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
end if;
v.ctrl_wrb.reg_write := '1';
elsif G_SUPPORT_SPR and opcode = "100101" then
if instruction(15 downto 14) = "11" then -- MTS, SPR[Sd] := Ra
v.ctrl_ex.msr_op := LOAD_MSR; -- Ra will be written to the status bits
elsif instruction(15 downto 14) = "10" then -- MFS, Rd := SPR[Sd]
v.ctrl_wrb.reg_write := '1';
v.ctrl_ex.alu_src_a := ALU_SRC_SPR;
v.ctrl_ex.alu_op := ALU_SEXT16; -- does not use B
else -- 00 (MSRSET/MSRCLR) and 01 -> illegal
v.ctrl_ex.alu_src_a := ALU_SRC_SPR;
v.ctrl_ex.alu_op := ALU_SEXT16; -- does not use B
v.ctrl_wrb.reg_write := '1';
if instruction(16)='0' then -- SET
v.ctrl_ex.msr_op := MSR_SET;
else -- CLR
v.ctrl_ex.msr_op := MSR_CLR;
end if;
end if;
else
-- UNKNOWN OPCODE
null;
end if;
rin <= v;
regin <= v_reg;
end process;
decode_seq: process(clk_i)
procedure proc_reset_decode is
begin
r.reg_a <= (others => '0');
r.reg_b <= (others => '0');
r.imm <= (others => '0');
r.program_counter <= (others => '0');
r.hazard <= '0';
r.ctrl_ex.alu_op <= ALU_ADD;
r.ctrl_ex.alu_src_a <= ALU_SRC_REGA;
r.ctrl_ex.alu_src_b <= ALU_SRC_REGB;
r.ctrl_ex.operation <= "00";
r.ctrl_ex.carry <= CARRY_ZERO;
r.ctrl_ex.carry_keep <= CARRY_NOT_KEEP;
r.ctrl_ex.delay <= '0';
r.ctrl_ex.branch_cond <= NOP;
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_mem.mem_read <= '0';
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
r.fwd_dec_result <= (others => '0');
r.fwd_dec.reg_d <= (others => '0');
r.fwd_dec.reg_write <= '0';
reg.instruction <= (others => '0');
reg.program_counter <= (others => '0');
reg.immediate <= (others => '0');
reg.is_immediate <= '0';
reg.interrupt <= '0';
reg.delay_interrupt <= '0';
reg.block_interrupt <= '0';
end procedure proc_reset_decode;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_reset_decode;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
gprf0 : gprf port map
(
gprf_o => gprf_o,
gprf_i.adr_a_i => rin.reg_a,
gprf_i.adr_b_i => rin.reg_b,
gprf_i.adr_d_i => rin.ctrl_wrb.reg_d,
gprf_i.dat_w_i => wb_dat_d,
gprf_i.adr_w_i => decode_i.ctrl_wrb.reg_d,
gprf_i.wre_i => decode_i.ctrl_wrb.reg_write,
ena_i => ena_i,
clk_i => clk_i
);
end arch;
| gpl-3.0 | d6ab0a5ef5eab0cf8274787a57664e73 | 0.47442 | 3.585406 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/spi/vhdl_source/spi_peripheral.vhd | 5 | 3,591 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity spi_peripheral is
generic (
g_fixed_rate : boolean := false;
g_init_rate : integer := 500;
g_crc : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_addr : in std_logic_vector(1 downto 0);
bus_wdata : in std_logic_vector(7 downto 0);
bus_rdata : out std_logic_vector(7 downto 0);
SPI_SSn : out std_logic;
SPI_CLK : out std_logic;
SPI_MOSI : out std_logic;
SPI_MISO : in std_logic );
end spi_peripheral;
architecture gideon of spi_peripheral is
signal do_send : std_logic;
signal force_ss : std_logic := '0';
signal level_ss : std_logic := '0';
signal busy : std_logic;
signal rate : std_logic_vector(8 downto 0) := std_logic_vector(to_unsigned(g_init_rate, 9));
signal rdata : std_logic_vector(7 downto 0);
signal wdata : std_logic_vector(7 downto 0);
signal clear_crc : std_logic;
signal crc_out : std_logic_vector(7 downto 0);
begin
spi1: entity work.spi
generic map (
g_crc => g_crc )
port map (
clock => clock,
reset => reset,
do_send => do_send,
clear_crc => clear_crc,
force_ss => force_ss,
level_ss => level_ss,
busy => busy,
rate => rate,
cpol => '0',
cpha => '0',
wdata => wdata,
rdata => rdata,
crc_out => crc_out,
SPI_SSn => SPI_SSn,
SPI_CLK => SPI_CLK,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO );
process(clock)
begin
if rising_edge(clock) then
do_send <= '0';
clear_crc <= '0';
if bus_select='1' and bus_write='1' then
case bus_addr is
when "00" =>
do_send <= '1';
wdata <= bus_wdata;
when "01" =>
if not g_fixed_rate then
rate(7 downto 0) <= bus_wdata;
rate(8) <= bus_wdata(7);
end if;
when "10" =>
force_ss <= bus_wdata(0);
level_ss <= bus_wdata(1);
when "11" =>
clear_crc <= '1';
when others =>
null;
end case;
end if;
if reset='1' then
rate <= std_logic_vector(to_unsigned(g_init_rate, 9));
force_ss <= '0';
level_ss <= '1';
wdata <= (others => '0');
end if;
end if;
end process;
with bus_addr select bus_rdata <=
rdata when "00",
rate(7 downto 0) when "01",
busy & "00000" & level_ss & force_ss when "10",
crc_out when "11",
X"FF" when others;
end gideon;
| gpl-3.0 | 87eb23c5c797a9e2d56f102ac629c8c0 | 0.391534 | 4.137097 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/tb_AddressGenerator.vhd | 1 | 4,049 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:37:23 11/26/2013
-- Design Name:
-- Module Name: /media/DATA42/Projects/ComputerVision/RetinaDescriptors/tb_AddressGenerator.vhd
-- Project Name: RetinaDescriptors
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: AddressGenerator
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.RetinaParameters.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_AddressGenerator IS
END tb_AddressGenerator;
ARCHITECTURE behavior OF tb_AddressGenerator IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT AddressGenerator
PORT(
clk : IN std_logic;
en : IN std_logic;
rst : IN std_logic;
coord_x : IN std_logic_vector(KPT_COORD_BW-1 downto 0);
coord_y : IN std_logic_vector(KPT_COORD_BW-1 downto 0);
image_base_addr : IN std_logic_vector(31 downto 0);
mem_addr : OUT std_logic_vector(31 downto 0);
out_en : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal en : std_logic := '0';
signal rst : std_logic := '0';
signal coord_x : std_logic_vector(KPT_COORD_BW-1 downto 0) := (others => '0');
signal coord_y : std_logic_vector(KPT_COORD_BW-1 downto 0) := (others => '0');
signal image_base_addr : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal mem_addr : std_logic_vector(31 downto 0);
signal out_en : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: AddressGenerator PORT MAP (
clk => clk,
en => en,
rst => rst,
coord_x => coord_x,
coord_y => coord_y,
image_base_addr => image_base_addr,
mem_addr => mem_addr,
out_en => out_en
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
rst <= '1';
wait for 100 ns;
rst <= '0';
wait for clk_period*10;
coord_x <= "0001000000";
coord_y <= "0001000001";
image_base_addr <= "00000000000000000000000000000000";
en <= '1';
-- insert stimulus here
wait;
end process;
END;
| gpl-3.0 | d76e0826aebff43788b2accbe50d40de | 0.631514 | 3.742144 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/c2n_record/vhdl_source/c2n_record.vhd | 3 | 8,197 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity c2n_record is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
phi2_tick : in std_logic;
c64_stopped : in std_logic;
pull_sense : out std_logic;
c2n_motor : in std_logic;
c2n_sense : in std_logic;
c2n_read : in std_logic;
c2n_write : in std_logic );
end c2n_record;
architecture gideon of c2n_record is
signal stream_en : std_logic;
signal mode : std_logic_vector(1 downto 0);
signal sel : std_logic;
signal read_s : std_logic;
signal read_c : std_logic;
signal read_d : std_logic;
signal read_event : std_logic;
signal enabled : std_logic;
signal counter : unsigned(23 downto 0);
signal diff : unsigned(23 downto 0);
signal remain : unsigned(2 downto 0);
signal error : std_logic;
signal irq_en : std_logic;
signal status : std_logic_vector(7 downto 0);
signal fifo_din : std_logic_vector(7 downto 0);
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal fifo_flush : std_logic;
signal fifo_write : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 63;
type t_state is (idle, listen, encode, multi1, multi2, multi3);
signal state : t_state;
signal state_enc : std_logic_vector(1 downto 0);
attribute register_duplication : string;
attribute register_duplication of stream_en : signal is "no";
attribute register_duplication of read_c : signal is "no";
begin
pull_sense <= sel and enabled;
filt: entity work.spike_filter generic map (10) port map(clock, read_s, read_c);
process(clock)
variable v_diff : unsigned(10 downto 0);
begin
if rising_edge(clock) then
if fifo_full='1' and enabled='1' then
error <= '1';
end if;
-- signal capture
stream_en <= c2n_sense and enabled and c2n_motor;
read_s <= (c2n_read and not sel) or (c2n_write and sel);
read_d <= read_c;
case mode is
when "00" =>
read_event <= read_c and not read_d; -- rising edge
when "01" =>
read_event <= not read_c and read_d; -- falling edge
when others =>
read_event <= read_c xor read_d; -- both edges
end case;
-- filter for false pulses
-- if counter(23 downto 4) = X"00000" then
-- read_event <= '0';
-- end if;
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1'; -- ack for fifo write as well.
if req.address(11)='0' then
enabled <= req.data(0);
if req.data(0)='0' and enabled='1' then -- getting disabled
read_event <= '1'; -- why??
end if;
if req.data(1)='1' then
error <= '0';
end if;
fifo_flush <= req.data(2);
mode <= req.data(5 downto 4);
sel <= req.data(6);
irq_en <= req.data(7);
end if;
elsif req.read='1' then
resp.ack <= '1';
if req.address(11)='0' then
resp.data <= status;
else
resp.data <= fifo_dout;
end if;
end if;
resp.irq <= irq_en and fifo_almostfull;
-- listening process
if stream_en='1' then
if phi2_tick='1' then
counter <= counter + 1;
end if;
else
counter <= (others => '0');
end if;
fifo_write <= '0';
case state is
when idle =>
if stream_en='1' then
state <= listen;
end if;
when listen =>
if read_event='1' then
diff <= counter;
if phi2_tick='1' then
counter <= to_unsigned(1, counter'length);
else
counter <= to_unsigned(0, counter'length);
end if;
state <= encode;
elsif enabled='0' then
state <= idle;
end if;
when encode =>
fifo_write <= '1';
if diff > 2040 then
fifo_din <= X"00";
state <= multi1;
else
v_diff := diff(10 downto 0) + remain;
if v_diff(10 downto 3) = X"00" then
fifo_din <= X"01";
else
fifo_din <= std_logic_vector(v_diff(10 downto 3));
end if;
remain <= v_diff(2 downto 0);
state <= listen;
end if;
when multi1 =>
fifo_din <= std_logic_vector(diff(7 downto 0));
fifo_write <= '1';
state <= multi2;
when multi2 =>
fifo_din <= std_logic_vector(diff(15 downto 8));
fifo_write <= '1';
state <= multi3;
when multi3 =>
fifo_din <= std_logic_vector(diff(23 downto 16));
fifo_write <= '1';
state <= listen;
when others =>
null;
end case;
if reset='1' then
fifo_din <= (others => '0');
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
mode <= "00";
sel <= '0';
remain <= "000";
irq_en <= '0';
end if;
end if;
end process;
fifo_read <= '1' when req.read='1' and req.address(11)='1' else '0';
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 512,
g_storage => "block",
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => fifo_din,
dout => fifo_dout,
flush => fifo_flush,
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= state_enc(0);
status(5) <= state_enc(1);
status(6) <= stream_en;
status(7) <= not fifo_empty;
with state select state_enc <=
"00" when idle,
"01" when multi1,
"01" when multi2,
"01" when multi3,
"10" when listen,
"11" when others;
end gideon;
| gpl-3.0 | a1a0eceb5ebe2800bbfac2866b6b7c93 | 0.412956 | 4.273723 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl_v4.vhd | 5 | 9,586 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM (no burst)
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v4 is
generic (
g_simulation : boolean := false;
A_Width : integer := 15;
SDRAM_WakeupTime : integer := 40; -- refresh periods
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in t_mem_req;
resp : out t_mem_resp;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_D : inout std_logic_vector(7 downto 0) := (others => 'Z'));
end ext_mem_ctrl_v4;
-- ADDR: 25 24 23 ...
-- 0 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl_v4 is
type t_init is record
addr : std_logic_vector(15 downto 0);
cmd : std_logic_vector(2 downto 0); -- we-cas-ras
end record;
type t_init_array is array(natural range <>) of t_init;
constant c_init_array : t_init_array(0 to 7) := (
( X"0400", "010" ), -- auto precharge
( X"0220", "000" ), -- mode register, burstlen=1, writelen=1, CAS lat = 2
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ), -- auto refresh
( X"0000", "001" ) );
type t_state is (boot, init, idle, sd_cas, sd_wait);
signal state : t_state;
signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sram_d_t : std_logic := '0';
signal delay : integer range 0 to 15;
signal inhibit_d : std_logic;
signal rwn_i : std_logic;
signal tag : std_logic_vector(req.tag'range);
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal reg_out : integer range 0 to 3 := 0;
signal rdata_i : std_logic_vector(7 downto 0) := (others => '0');
signal dout_sel : std_logic := '0';
signal refr_delay : integer range 0 to 3;
signal boot_cnt : integer range 0 to SDRAM_WakeupTime-1 := SDRAM_WakeupTime-1;
signal init_cnt : integer range 0 to c_init_array'high;
signal enable_sdram : std_logic := '1';
signal req_i : std_logic;
signal dack : std_logic;
signal rack : std_logic;
signal rack_tag : std_logic_vector(req.tag'range);
signal dack_tag : std_logic_vector(req.tag'range);
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of rdata_i : signal is "true"; -- the general memctrl/rdata must be packed in IOB
attribute iob of SDRAM_CKE : signal is "false";
begin
is_idle <= '1' when state = idle else '0';
req_i <= req.request;
resp.data <= rdata_i;
resp.rack <= rack;
resp.rack_tag <= rack_tag;
resp.dack_tag <= dack_tag;
process(clock)
procedure send_refresh_cmd is
begin
do_refresh <= '0';
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
refr_delay <= 3;
end procedure;
procedure accept_req is
begin
rack <= '1';
rack_tag <= req.tag;
tag <= req.tag;
rwn_i <= req.read_writen;
sram_d_t <= '0'; --not req.read_writen;
sram_d_o <= req.data;
mem_a_i(12 downto 0) <= std_logic_vector(req.address(24 downto 12)); -- 13 row bits
mem_a_i(14 downto 13) <= std_logic_vector(req.address(11 downto 10)); -- 2 bank bits
col_addr <= std_logic_vector(req.address( 9 downto 0)); -- 10 column bits
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
sram_d_t <= '0'; -- no data yet
delay <= 1;
state <= sd_cas;
end procedure;
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
dout_sel <= '0';
inhibit_d <= inhibit;
rdata_i <= MEM_D; -- clock in
SDRAM_CSn <= '1';
SDRAM_CKE <= enable_sdram;
if refr_delay /= 0 then
refr_delay <= refr_delay - 1;
end if;
case state is
when boot =>
enable_sdram <= '1';
if refresh_cnt = 0 then
boot_cnt <= boot_cnt - 1;
if boot_cnt = 1 then
state <= init;
end if;
elsif g_simulation then
state <= idle;
end if;
when init =>
mem_a_i <= c_init_array(init_cnt).addr(mem_a_i'range);
SDRAM_RASn <= c_init_array(init_cnt).cmd(0);
SDRAM_CASn <= c_init_array(init_cnt).cmd(1);
SDRAM_WEn <= c_init_array(init_cnt).cmd(2);
if delay = 0 then
delay <= 7;
SDRAM_CSn <= '0';
if init_cnt = c_init_array'high then
state <= idle;
else
init_cnt <= init_cnt + 1;
end if;
else
delay <= delay - 1;
end if;
when idle =>
-- first cycle after inhibit goes 0, do not do refresh
-- this enables putting cartridge images in sdram
if do_refresh='1' and not (inhibit_d='1' or inhibit='1') then
send_refresh_cmd;
elsif inhibit='0' then
if req_i='1' and refr_delay = 0 then
accept_req;
end if;
end if;
when sd_cas =>
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
sram_d_t <= not rwn_i; -- enable for writes
if delay = 0 then
-- read or write with auto precharge
SDRAM_CSn <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= rwn_i;
if rwn_i='0' then -- write
delay <= 2;
else
delay <= 2;
end if;
state <= sd_wait;
else
delay <= delay - 1;
end if;
when sd_wait =>
sram_d_t <= '0';
if delay=0 then
if rwn_i = '1' then -- read
dack <= '1';
dack_tag <= tag;
end if;
state <= idle;
else
delay <= delay - 1;
end if;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= '1';
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= boot;
sram_d_t <= '0';
delay <= 0;
tag <= (others => '0');
do_refresh <= '0';
boot_cnt <= SDRAM_WakeupTime-1;
init_cnt <= 0;
enable_sdram <= '1';
end if;
end if;
end process;
MEM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
MEM_A <= mem_a_i;
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
end Gideon;
| gpl-3.0 | 7bb5daf04cdf781117dc986bc81219ac | 0.433549 | 3.820646 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op336_0.vhdl | 1 | 5,416 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net3
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 5da0850eae7351d4e262c925ccda6942 | 0.575517 | 3.114434 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/axi_powerlink_v1_00_a/hdl/vhdl/axi_powerlink.vhd | 1 | 84,136 | -------------------------------------------------------------------------------
-- Entity : axi_powerlink
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
-- Design unit header --
--
-- This is the toplevel file for using the POWERLINK IP-Core
-- with Xilinx AXI.
--
-------------------------------------------------------------------------------
--
-- 2012-01-12 V0.01 zelenkaj First version
-- 2012-01-26 V0.02 zelenkaj Added number of SMI generic feature
-- 2012-01-27 V0.10 zelenkaj Incremented PdiRev
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_master_burst_v1_00_a;
use axi_master_burst_v1_00_a.axi_master_burst;
-- standard libraries declarations
library UNISIM;
use UNISIM.vcomponents.all;
-- pragma synthesis_off
library IEEE;
use IEEE.vital_timing.all;
-- pragma synthesis_on
-- other libraries declarations
library AXI_LITE_IPIF_V1_01_A;
library AXI_MASTER_BURST_V1_00_A;
entity axi_powerlink is
generic(
-- general
C_GEN_PDI : boolean := false;
C_GEN_PAR_IF : boolean := false;
C_GEN_SPI_IF : boolean := false;
C_GEN_AXI_BUS_IF : boolean := false;
C_GEN_SIMPLE_IO : boolean := false;
-- openMAC
C_MAC_PKT_SIZE : integer := 1024;
C_MAC_PKT_SIZE_LOG2 : integer := 10;
C_MAC_RX_BUFFERS : integer := 16;
C_USE_RMII : boolean := false;
C_TX_INT_PKT : boolean := false;
C_RX_INT_PKT : boolean := false;
C_USE_2ND_PHY : boolean := true;
C_NUM_SMI : integer range 1 to 2 := 2;
--pdi
C_PDI_GEN_ASYNC_BUF_0 : boolean := true;
C_PDI_ASYNC_BUF_0 : integer := 50;
C_PDI_GEN_ASYNC_BUF_1 : boolean := true;
C_PDI_ASYNC_BUF_1 : integer := 50;
C_PDI_GEN_LED : boolean := false;
C_PDI_GEN_TIME_SYNC : boolean := true;
C_PDI_GEN_SECOND_TIMER : boolean := false;
C_PDI_GEN_EVENT : boolean := true;
--global pdi and mac
C_NUM_RPDO : integer := 3;
C_RPDO_0_BUF_SIZE : integer := 100;
C_RPDO_1_BUF_SIZE : integer := 100;
C_RPDO_2_BUF_SIZE : integer := 100;
C_NUM_TPDO : integer := 1;
C_TPDO_BUF_SIZE : integer := 100;
-- pap
C_PAP_DATA_WIDTH : integer := 16;
--C_PAP_BIG_END : boolean := false;
C_PAP_LOW_ACT : boolean := false;
-- spi
C_SPI_CPOL : boolean := false;
C_SPI_CPHA : boolean := false;
--C_SPI_BIG_END : boolean := false;
-- simpleIO
C_PIO_VAL_LENGTH : integer := 50;
-- debug
C_OBSERVER_ENABLE : boolean := false;
-- clock stabiliser
C_INSTANCE_ODDR2 : boolean := false;
-- PDI AP AXI Slave
C_S_AXI_PDI_AP_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_PDI_AP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_S_AXI_PDI_AP_DATA_WIDTH : integer := 32;
C_S_AXI_PDI_AP_ADDR_WIDTH : integer := 32;
C_S_AXI_PDI_AP_USE_WSTRB : integer := 1;
C_S_AXI_PDI_AP_DPHASE_TIMEOUT : integer := 8;
-- PDI AP AXI Slave
C_S_AXI_SMP_PCP_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_SMP_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_S_AXI_SMP_PCP_DATA_WIDTH : integer := 32;
C_S_AXI_SMP_PCP_ADDR_WIDTH : integer := 32;
C_S_AXI_SMP_PCP_USE_WSTRB : integer := 1;
C_S_AXI_SMP_PCP_DPHASE_TIMEOUT : integer := 8;
-- PDI PCP AXI Slave
C_S_AXI_PDI_PCP_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_PDI_PCP_HIGHADDR : std_logic_vector := X"000FFFFF";
C_S_AXI_PDI_PCP_DATA_WIDTH : integer := 32;
C_S_AXI_PDI_PCP_ADDR_WIDTH : integer := 32;
C_S_AXI_PDI_PCP_USE_WSTRB : integer := 1;
C_S_AXI_PDI_PCP_DPHASE_TIMEOUT : integer := 8;
-- openMAC DMA AXI Master
C_M_AXI_MAC_DMA_ADDR_WIDTH : INTEGER := 32;
C_M_AXI_MAC_DMA_DATA_WIDTH : INTEGER := 32;
C_M_AXI_MAC_DMA_NATIVE_DWIDTH : INTEGER := 32;
C_M_AXI_MAC_DMA_LENGTH_WIDTH : INTEGER := 12;
C_M_AXI_MAC_DMA_MAX_BURST_LEN : INTEGER := 16;
C_MAC_DMA_BURST_SIZE_RX : INTEGER := 8; --in bytes
C_MAC_DMA_BURST_SIZE_TX : INTEGER := 8; --in bytes
C_MAC_DMA_FIFO_SIZE_RX : INTEGER := 32; --in bytes
C_MAC_DMA_FIFO_SIZE_TX : INTEGER := 32; --in bytes
-- openMAC PKT AXI Slave
C_S_AXI_MAC_PKT_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_MAC_PKT_HIGHADDR : std_logic_vector := X"000FFFFF";
C_S_AXI_MAC_PKT_DATA_WIDTH : integer := 32;
C_S_AXI_MAC_PKT_ADDR_WIDTH : integer := 32;
C_S_AXI_MAC_PKT_USE_WSTRB : integer := 1;
C_S_AXI_MAC_PKT_DPHASE_TIMEOUT : integer := 8;
-- openMAC REG AXI Slave
--- MAC_REG
C_S_AXI_MAC_REG_RNG0_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_MAC_REG_RNG0_HIGHADDR : std_logic_vector := X"0000FFFF";
--- MAC_CMP
C_S_AXI_MAC_REG_RNG1_BASEADDR : std_logic_vector := X"00000000";
C_S_AXI_MAC_REG_RNG1_HIGHADDR : std_logic_vector := X"0000FFFF";
C_S_AXI_MAC_REG_DATA_WIDTH : integer := 32;
C_S_AXI_MAC_REG_ADDR_WIDTH : integer := 32;
C_S_AXI_MAC_REG_USE_WSTRB : integer := 1;
C_S_AXI_MAC_REG_DPHASE_TIMEOUT : integer := 8;
C_S_AXI_MAC_REG_ACLK_FREQ_HZ : integer := 20 --clock frequency in Hz
);
port(
M_AXI_MAC_DMA_aclk : in std_logic;
M_AXI_MAC_DMA_aresetn : in std_logic;
M_AXI_MAC_DMA_arready : in std_logic;
M_AXI_MAC_DMA_awready : in std_logic;
M_AXI_MAC_DMA_bvalid : in std_logic;
M_AXI_MAC_DMA_rlast : in std_logic;
M_AXI_MAC_DMA_rvalid : in std_logic;
M_AXI_MAC_DMA_wready : in std_logic;
S_AXI_MAC_PKT_ACLK : in std_logic;
S_AXI_MAC_PKT_ARESETN : in std_logic;
S_AXI_MAC_PKT_ARVALID : in std_logic;
S_AXI_MAC_PKT_AWVALID : in std_logic;
S_AXI_MAC_PKT_BREADY : in std_logic;
S_AXI_MAC_PKT_RREADY : in std_logic;
S_AXI_MAC_PKT_WVALID : in std_logic;
S_AXI_MAC_REG_ACLK : in std_logic;
S_AXI_MAC_REG_ARESETN : in std_logic;
S_AXI_MAC_REG_ARVALID : in std_logic;
S_AXI_MAC_REG_AWVALID : in std_logic;
S_AXI_MAC_REG_BREADY : in std_logic;
S_AXI_MAC_REG_RREADY : in std_logic;
S_AXI_MAC_REG_WVALID : in std_logic;
S_AXI_PDI_AP_ACLK : in std_logic;
S_AXI_PDI_AP_ARESETN : in std_logic;
S_AXI_PDI_AP_ARVALID : in std_logic;
S_AXI_PDI_AP_AWVALID : in std_logic;
S_AXI_PDI_AP_BREADY : in std_logic;
S_AXI_PDI_AP_RREADY : in std_logic;
S_AXI_PDI_AP_WVALID : in std_logic;
S_AXI_PDI_PCP_ACLK : in std_logic;
S_AXI_PDI_PCP_ARESETN : in std_logic;
S_AXI_PDI_PCP_ARVALID : in std_logic;
S_AXI_PDI_PCP_AWVALID : in std_logic;
S_AXI_PDI_PCP_BREADY : in std_logic;
S_AXI_PDI_PCP_RREADY : in std_logic;
S_AXI_PDI_PCP_WVALID : in std_logic;
S_AXI_SMP_PCP_ACLK : in std_logic;
S_AXI_SMP_PCP_ARESETN : in std_logic;
S_AXI_SMP_PCP_ARVALID : in std_logic;
S_AXI_SMP_PCP_AWVALID : in std_logic;
S_AXI_SMP_PCP_BREADY : in std_logic;
S_AXI_SMP_PCP_RREADY : in std_logic;
S_AXI_SMP_PCP_WVALID : in std_logic;
clk100 : in std_logic;
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic;
phy0_link : in std_logic;
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic;
phy1_link : in std_logic;
phyMii0_RxClk : in std_logic;
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic;
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
M_AXI_MAC_DMA_bresp : in std_logic_vector(1 downto 0);
M_AXI_MAC_DMA_rdata : in std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
M_AXI_MAC_DMA_rresp : in std_logic_vector(1 downto 0);
S_AXI_MAC_PKT_ARADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
S_AXI_MAC_PKT_AWADDR : in std_logic_vector(C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
S_AXI_MAC_PKT_WDATA : in std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
S_AXI_MAC_PKT_WSTRB : in std_logic_vector((C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0);
S_AXI_MAC_REG_ARADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
S_AXI_MAC_REG_AWADDR : in std_logic_vector(C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
S_AXI_MAC_REG_WDATA : in std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
S_AXI_MAC_REG_WSTRB : in std_logic_vector((C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0);
S_AXI_PDI_AP_ARADDR : in std_logic_vector(C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0);
S_AXI_PDI_AP_AWADDR : in std_logic_vector(C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0);
S_AXI_PDI_AP_WDATA : in std_logic_vector(C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0);
S_AXI_PDI_AP_WSTRB : in std_logic_vector((C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0);
S_AXI_PDI_PCP_ARADDR : in std_logic_vector(C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0);
S_AXI_PDI_PCP_AWADDR : in std_logic_vector(C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0);
S_AXI_PDI_PCP_WDATA : in std_logic_vector(C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0);
S_AXI_PDI_PCP_WSTRB : in std_logic_vector((C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0);
S_AXI_SMP_PCP_ARADDR : in std_logic_vector(C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0);
S_AXI_SMP_PCP_AWADDR : in std_logic_vector(C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0);
S_AXI_SMP_PCP_WDATA : in std_logic_vector(C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0);
S_AXI_SMP_PCP_WSTRB : in std_logic_vector((C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_be_n : in std_logic_vector(C_PAP_DATA_WIDTH/8-1 downto 0);
pap_data_I : in std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy1_RxDat : in std_logic_vector(1 downto 0);
phyMii0_RxDat : in std_logic_vector(3 downto 0);
phyMii1_RxDat : in std_logic_vector(3 downto 0);
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0);
M_AXI_MAC_DMA_arvalid : out std_logic;
M_AXI_MAC_DMA_awvalid : out std_logic;
M_AXI_MAC_DMA_bready : out std_logic;
M_AXI_MAC_DMA_md_error : out std_logic;
M_AXI_MAC_DMA_rready : out std_logic;
M_AXI_MAC_DMA_wlast : out std_logic;
M_AXI_MAC_DMA_wvalid : out std_logic;
S_AXI_MAC_PKT_ARREADY : out std_logic;
S_AXI_MAC_PKT_AWREADY : out std_logic;
S_AXI_MAC_PKT_BVALID : out std_logic;
S_AXI_MAC_PKT_RVALID : out std_logic;
S_AXI_MAC_PKT_WREADY : out std_logic;
S_AXI_MAC_REG_ARREADY : out std_logic;
S_AXI_MAC_REG_AWREADY : out std_logic;
S_AXI_MAC_REG_BVALID : out std_logic;
S_AXI_MAC_REG_RVALID : out std_logic;
S_AXI_MAC_REG_WREADY : out std_logic;
S_AXI_PDI_AP_ARREADY : out std_logic;
S_AXI_PDI_AP_AWREADY : out std_logic;
S_AXI_PDI_AP_BVALID : out std_logic;
S_AXI_PDI_AP_RVALID : out std_logic;
S_AXI_PDI_AP_WREADY : out std_logic;
S_AXI_PDI_PCP_ARREADY : out std_logic;
S_AXI_PDI_PCP_AWREADY : out std_logic;
S_AXI_PDI_PCP_BVALID : out std_logic;
S_AXI_PDI_PCP_RVALID : out std_logic;
S_AXI_PDI_PCP_WREADY : out std_logic;
S_AXI_SMP_PCP_ARREADY : out std_logic;
S_AXI_SMP_PCP_AWREADY : out std_logic;
S_AXI_SMP_PCP_BVALID : out std_logic;
S_AXI_SMP_PCP_RVALID : out std_logic;
S_AXI_SMP_PCP_WREADY : out std_logic;
ap_asyncIrq : out std_logic;
ap_asyncIrq_n : out std_logic;
ap_syncIrq : out std_logic;
ap_syncIrq_n : out std_logic;
led_error : out std_logic;
led_status : out std_logic;
mac_irq : out std_logic;
pap_ack : out std_logic;
pap_ack_n : out std_logic;
pap_data_T : out std_logic;
phy0_Rst_n : out std_logic;
phy0_SMIClk : out std_logic;
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxEn : out std_logic;
phy0_clk : out std_logic;
phy1_Rst_n : out std_logic;
phy1_SMIClk : out std_logic;
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxEn : out std_logic;
phy1_clk : out std_logic;
phyMii0_TxEn : out std_logic;
phyMii0_TxEr : out std_logic;
phyMii1_TxEn : out std_logic;
phyMii1_TxEr : out std_logic;
phy_Rst_n : out std_logic;
phy_SMIClk : out std_logic;
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic;
spi_miso : out std_logic;
tcp_irq : out std_logic;
M_AXI_MAC_DMA_araddr : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
M_AXI_MAC_DMA_arburst : out std_logic_vector(1 downto 0);
M_AXI_MAC_DMA_arcache : out std_logic_vector(3 downto 0);
M_AXI_MAC_DMA_arlen : out std_logic_vector(7 downto 0);
M_AXI_MAC_DMA_arprot : out std_logic_vector(2 downto 0);
M_AXI_MAC_DMA_arsize : out std_logic_vector(2 downto 0);
M_AXI_MAC_DMA_awaddr : out std_logic_vector(C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
M_AXI_MAC_DMA_awburst : out std_logic_vector(1 downto 0);
M_AXI_MAC_DMA_awcache : out std_logic_vector(3 downto 0);
M_AXI_MAC_DMA_awlen : out std_logic_vector(7 downto 0);
M_AXI_MAC_DMA_awprot : out std_logic_vector(2 downto 0);
M_AXI_MAC_DMA_awsize : out std_logic_vector(2 downto 0);
M_AXI_MAC_DMA_wdata : out std_logic_vector(C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0);
M_AXI_MAC_DMA_wstrb : out std_logic_vector((C_M_AXI_MAC_DMA_DATA_WIDTH/8)-1 downto 0);
S_AXI_MAC_PKT_BRESP : out std_logic_vector(1 downto 0);
S_AXI_MAC_PKT_RDATA : out std_logic_vector(C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
S_AXI_MAC_PKT_RRESP : out std_logic_vector(1 downto 0);
S_AXI_MAC_REG_BRESP : out std_logic_vector(1 downto 0);
S_AXI_MAC_REG_RDATA : out std_logic_vector(C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
S_AXI_MAC_REG_RRESP : out std_logic_vector(1 downto 0);
S_AXI_PDI_AP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_PDI_AP_RDATA : out std_logic_vector(C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0);
S_AXI_PDI_AP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_PDI_PCP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_PDI_PCP_RDATA : out std_logic_vector(C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0);
S_AXI_PDI_PCP_RRESP : out std_logic_vector(1 downto 0);
S_AXI_SMP_PCP_BRESP : out std_logic_vector(1 downto 0);
S_AXI_SMP_PCP_RDATA : out std_logic_vector(C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0);
S_AXI_SMP_PCP_RRESP : out std_logic_vector(1 downto 0);
led_gpo : out std_logic_vector(7 downto 0);
led_opt : out std_logic_vector(1 downto 0);
led_phyAct : out std_logic_vector(1 downto 0);
led_phyLink : out std_logic_vector(1 downto 0);
pap_data_O : out std_logic_vector(C_PAP_DATA_WIDTH-1 downto 0);
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
phy0_TxDat : out std_logic_vector(1 downto 0);
phy1_TxDat : out std_logic_vector(1 downto 0);
phyMii0_TxDat : out std_logic_vector(3 downto 0);
phyMii1_TxDat : out std_logic_vector(3 downto 0);
pio_portOutValid : out std_logic_vector(3 downto 0);
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
test_port : out std_logic_vector(255 downto 0) := (others => '0')
);
-- Entity declarations --
-- Click here to add additional declarations --
attribute SIGIS : string;
-- Entity attributes --
attribute SIGIS of M_AXI_MAC_DMA_aclk : signal is "Clk";
attribute SIGIS of M_AXI_MAC_DMA_aresetn : signal is "Rst";
attribute SIGIS of S_AXI_MAC_PKT_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_MAC_PKT_ARESETN : signal is "Rst";
attribute SIGIS of S_AXI_MAC_REG_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_MAC_REG_ARESETN : signal is "Rst";
attribute SIGIS of S_AXI_PDI_AP_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_PDI_AP_ARESETN : signal is "Rst";
attribute SIGIS of S_AXI_PDI_PCP_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_PDI_PCP_ARESETN : signal is "Rst";
attribute SIGIS of S_AXI_SMP_PCP_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_SMP_PCP_ARESETN : signal is "Rst";
attribute SIGIS of clk100 : signal is "Clk";
attribute SIGIS of phy0_clk : signal is "Clk";
attribute SIGIS of phy1_clk : signal is "Clk";
end axi_powerlink;
architecture struct of axi_powerlink is
---- Architecture declarations -----
function get_max( a, b : integer) return integer is
begin
if a < b then
return b;
else
return a;
end if;
end get_max;
---- Component declarations -----
component ipif_master_handler
generic(
C_MAC_DMA_IPIF_AWIDTH : integer := 32;
C_MAC_DMA_IPIF_NATIVE_DWIDTH : integer := 32;
dma_highadr_g : integer := 31;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4
);
port (
Bus2MAC_DMA_MstRd_d : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
Bus2MAC_DMA_MstRd_eof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_rem : in std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
Bus2MAC_DMA_MstRd_sof_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstRd_src_rdy_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_dsc_n : in std_logic := '1';
Bus2MAC_DMA_MstWr_dst_rdy_n : in std_logic := '1';
Bus2MAC_DMA_Mst_CmdAck : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmd_Timeout : in std_logic := '0';
Bus2MAC_DMA_Mst_Cmplt : in std_logic := '0';
Bus2MAC_DMA_Mst_Error : in std_logic := '0';
Bus2MAC_DMA_Mst_Rearbitrate : in std_logic := '0';
MAC_DMA_CLK : in std_logic;
MAC_DMA_Rst : in std_logic;
m_address : in std_logic_vector(dma_highadr_g downto 0);
m_burstcount : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : in std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : in std_logic_vector(3 downto 0);
m_read : in std_logic := '0';
m_write : in std_logic := '0';
m_writedata : in std_logic_vector(31 downto 0);
MAC_DMA2Bus_MstRd_Req : out std_logic := '0';
MAC_DMA2Bus_MstRd_dst_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstRd_dst_rdy_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_Req : out std_logic := '0';
MAC_DMA2Bus_MstWr_d : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH-1 downto 0);
MAC_DMA2Bus_MstWr_eof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_rem : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_MstWr_sof_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_dsc_n : out std_logic := '1';
MAC_DMA2Bus_MstWr_src_rdy_n : out std_logic := '1';
MAC_DMA2Bus_Mst_Addr : out std_logic_vector(C_MAC_DMA_IPIF_AWIDTH-1 downto 0);
MAC_DMA2Bus_Mst_BE : out std_logic_vector(C_MAC_DMA_IPIF_NATIVE_DWIDTH/8-1 downto 0);
MAC_DMA2Bus_Mst_Length : out std_logic_vector(11 downto 0);
MAC_DMA2Bus_Mst_Lock : out std_logic := '0';
MAC_DMA2Bus_Mst_Reset : out std_logic := '0';
MAC_DMA2Bus_Mst_Type : out std_logic := '0';
m_clk : out std_logic;
m_readdata : out std_logic_vector(31 downto 0);
m_readdatavalid : out std_logic := '0';
m_waitrequest : out std_logic := '1'
);
end component;
component openMAC_16to32conv
generic(
bus_address_width : integer := 10;
gEndian : string := "little"
);
port (
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_byteenable : in std_logic_vector(3 downto 0);
bus_read : in std_logic;
bus_select : in std_logic;
bus_write : in std_logic;
bus_writedata : in std_logic_vector(31 downto 0);
clk : in std_logic;
rst : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_waitrequest : in std_logic;
bus_ack_rd : out std_logic;
bus_ack_wr : out std_logic;
bus_readdata : out std_logic_vector(31 downto 0);
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_chipselect : out std_logic;
s_read : out std_logic;
s_write : out std_logic;
s_writedata : out std_logic_vector(15 downto 0)
);
end component;
component powerlink
generic(
Simulate : boolean := false;
endian_g : string := "little";
gNumSmi : integer range 1 to 2 := 2;
genABuf1_g : boolean := true;
genABuf2_g : boolean := true;
genEvent_g : boolean := false;
genInternalAp_g : boolean := true;
genIoBuf_g : boolean := true;
genLedGadget_g : boolean := false;
genOnePdiClkDomain_g : boolean := false;
genPdi_g : boolean := true;
genSimpleIO_g : boolean := false;
genSmiIO : boolean := true;
genSpiAp_g : boolean := false;
genTimeSync_g : boolean := false;
gen_dma_observer_g : boolean := true;
iAsyBuf1Size_g : integer := 100;
iAsyBuf2Size_g : integer := 100;
iBufSizeLOG2_g : integer := 10;
iBufSize_g : integer := 1024;
iPdiRev_g : integer := 21930;
iRpdo0BufSize_g : integer := 100;
iRpdo1BufSize_g : integer := 100;
iRpdo2BufSize_g : integer := 100;
iRpdos_g : integer := 3;
iTpdoBufSize_g : integer := 100;
iTpdos_g : integer := 1;
m_burstcount_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_data_width_g : integer := 16;
m_rx_burst_size_g : integer := 16;
m_rx_fifo_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
m_tx_fifo_size_g : integer := 16;
papBigEnd_g : boolean := false;
papDataWidth_g : integer := 8;
papLowAct_g : boolean := false;
pioValLen_g : integer := 50;
spiBigEnd_g : boolean := false;
spiCPHA_g : boolean := false;
spiCPOL_g : boolean := false;
use2ndCmpTimer_g : boolean := true;
use2ndPhy_g : boolean := true;
useIntPacketBuf_g : boolean := true;
useRmii_g : boolean := true;
useRxIntPacketBuf_g : boolean := true
);
port (
ap_address : in std_logic_vector(12 downto 0);
ap_byteenable : in std_logic_vector(3 downto 0);
ap_chipselect : in std_logic;
ap_read : in std_logic;
ap_write : in std_logic;
ap_writedata : in std_logic_vector(31 downto 0);
clk50 : in std_logic;
clkAp : in std_logic;
clkEth : in std_logic;
clkPcp : in std_logic;
m_clk : in std_logic;
m_readdata : in std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
m_readdatavalid : in std_logic := '0';
m_waitrequest : in std_logic;
mac_address : in std_logic_vector(11 downto 0);
mac_byteenable : in std_logic_vector(1 downto 0);
mac_chipselect : in std_logic;
mac_read : in std_logic;
mac_write : in std_logic;
mac_writedata : in std_logic_vector(15 downto 0);
mbf_address : in std_logic_vector(ibufsizelog2_g-3 downto 0);
mbf_byteenable : in std_logic_vector(3 downto 0);
mbf_chipselect : in std_logic;
mbf_read : in std_logic;
mbf_write : in std_logic;
mbf_writedata : in std_logic_vector(31 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_be_n : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_cs : in std_logic;
pap_cs_n : in std_logic;
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_rd : in std_logic;
pap_rd_n : in std_logic;
pap_wr : in std_logic;
pap_wr_n : in std_logic;
pcp_address : in std_logic_vector(12 downto 0);
pcp_byteenable : in std_logic_vector(3 downto 0);
pcp_chipselect : in std_logic;
pcp_read : in std_logic;
pcp_write : in std_logic;
pcp_writedata : in std_logic_vector(31 downto 0);
phy0_RxDat : in std_logic_vector(1 downto 0);
phy0_RxDv : in std_logic;
phy0_RxErr : in std_logic;
phy0_SMIDat_I : in std_logic := '1';
phy0_link : in std_logic := '0';
phy1_RxDat : in std_logic_vector(1 downto 0) := (others => '0');
phy1_RxDv : in std_logic;
phy1_RxErr : in std_logic;
phy1_SMIDat_I : in std_logic := '1';
phy1_link : in std_logic := '0';
phyMii0_RxClk : in std_logic;
phyMii0_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii0_RxDv : in std_logic;
phyMii0_RxEr : in std_logic;
phyMii0_TxClk : in std_logic;
phyMii1_RxClk : in std_logic;
phyMii1_RxDat : in std_logic_vector(3 downto 0) := (others => '0');
phyMii1_RxDv : in std_logic;
phyMii1_RxEr : in std_logic;
phyMii1_TxClk : in std_logic;
phy_SMIDat_I : in std_logic := '1';
pio_pconfig : in std_logic_vector(3 downto 0);
pio_portInLatch : in std_logic_vector(3 downto 0);
pio_portio_I : in std_logic_vector(31 downto 0) := (others => '0');
pkt_clk : in std_logic;
rst : in std_logic;
rstAp : in std_logic;
rstPcp : in std_logic;
smp_address : in std_logic;
smp_byteenable : in std_logic_vector(3 downto 0);
smp_read : in std_logic;
smp_write : in std_logic;
smp_writedata : in std_logic_vector(31 downto 0);
spi_clk : in std_logic;
spi_mosi : in std_logic;
spi_sel_n : in std_logic;
tcp_address : in std_logic_vector(1 downto 0);
tcp_byteenable : in std_logic_vector(3 downto 0);
tcp_chipselect : in std_logic;
tcp_read : in std_logic;
tcp_write : in std_logic;
tcp_writedata : in std_logic_vector(31 downto 0);
ap_asyncIrq : out std_logic := '0';
ap_asyncIrq_n : out std_logic := '1';
ap_irq : out std_logic := '0';
ap_irq_n : out std_logic := '1';
ap_readdata : out std_logic_vector(31 downto 0) := (others => '0');
ap_syncIrq : out std_logic := '0';
ap_syncIrq_n : out std_logic := '1';
ap_waitrequest : out std_logic;
led_error : out std_logic := '0';
led_gpo : out std_logic_vector(7 downto 0) := (others => '0');
led_opt : out std_logic_vector(1 downto 0) := (others => '0');
led_phyAct : out std_logic_vector(1 downto 0) := (others => '0');
led_phyLink : out std_logic_vector(1 downto 0) := (others => '0');
led_status : out std_logic := '0';
m_address : out std_logic_vector(29 downto 0) := (others => '0');
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(m_data_width_g/8-1 downto 0) := (others => '0');
m_read : out std_logic := '0';
m_write : out std_logic := '0';
m_writedata : out std_logic_vector(m_data_width_g-1 downto 0) := (others => '0');
mac_irq : out std_logic := '0';
mac_readdata : out std_logic_vector(15 downto 0) := (others => '0');
mac_waitrequest : out std_logic;
mbf_readdata : out std_logic_vector(31 downto 0) := (others => '0');
mbf_waitrequest : out std_logic;
pap_ack : out std_logic := '0';
pap_ack_n : out std_logic := '1';
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0);
pcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
pcp_waitrequest : out std_logic;
phy0_Rst_n : out std_logic := '1';
phy0_SMIClk : out std_logic := '0';
phy0_SMIDat_O : out std_logic;
phy0_SMIDat_T : out std_logic;
phy0_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy0_TxEn : out std_logic := '0';
phy1_Rst_n : out std_logic := '1';
phy1_SMIClk : out std_logic := '0';
phy1_SMIDat_O : out std_logic;
phy1_SMIDat_T : out std_logic;
phy1_TxDat : out std_logic_vector(1 downto 0) := (others => '0');
phy1_TxEn : out std_logic := '0';
phyMii0_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii0_TxEn : out std_logic := '0';
phyMii0_TxEr : out std_logic := '0';
phyMii1_TxDat : out std_logic_vector(3 downto 0) := (others => '0');
phyMii1_TxEn : out std_logic := '0';
phyMii1_TxEr : out std_logic := '0';
phy_Rst_n : out std_logic := '1';
phy_SMIClk : out std_logic := '0';
phy_SMIDat_O : out std_logic;
phy_SMIDat_T : out std_logic;
pio_operational : out std_logic := '0';
pio_portOutValid : out std_logic_vector(3 downto 0) := (others => '0');
pio_portio_O : out std_logic_vector(31 downto 0);
pio_portio_T : out std_logic_vector(31 downto 0);
smp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
smp_waitrequest : out std_logic;
spi_miso : out std_logic := '0';
tcp_irq : out std_logic := '0';
tcp_readdata : out std_logic_vector(31 downto 0) := (others => '0');
tcp_waitrequest : out std_logic;
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_gpio : inout std_logic_vector(1 downto 0) := (others => '0');
phy0_SMIDat : inout std_logic := '1';
phy1_SMIDat : inout std_logic := '1';
phy_SMIDat : inout std_logic := '1';
pio_portio : inout std_logic_vector(31 downto 0) := (others => '0')
);
end component;
component axi_lite_ipif
generic(
C_ARD_ADDR_RANGE_ARRAY : slv64_array_type := (X"0000_0000_7000_0000",X"0000_0000_7000_00FF",X"0000_0000_7000_0100",X"0000_0000_7000_01FF");
C_ARD_NUM_CE_ARRAY : integer_array_type := (4,12);
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_FAMILY : string := "virtex6";
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0) := X"000001FF";
C_USE_WSTRB : integer := 0
);
port (
IP2Bus_Data : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
IP2Bus_Error : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_WrAck : in std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARESETN : in std_logic;
S_AXI_ARVALID : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
Bus2IP_Addr : out std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
Bus2IP_BE : out std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
Bus2IP_CS : out std_logic_vector((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
Bus2IP_Clk : out std_logic;
Bus2IP_Data : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_RdCE : out std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
Bus2IP_Resetn : out std_logic;
Bus2IP_WrCE : out std_logic_vector(calc_num_ce(C_ARD_NUM_CE_ARRAY)-1 downto 0);
S_AXI_ARREADY : out std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic
);
end component;
component axi_master_burst
generic(
C_ADDR_PIPE_DEPTH : integer range 1 to 14 := 1;
C_FAMILY : string := "virtex6";
C_LENGTH_WIDTH : integer range 12 to 20 := 12;
C_MAX_BURST_LEN : integer range 16 to 256 := 16;
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
C_M_AXI_DATA_WIDTH : integer range 32 to 256 := 32;
C_NATIVE_DATA_WIDTH : integer range 32 to 128 := 32
);
port (
ip2bus_mst_addr : in std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
ip2bus_mst_be : in std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
ip2bus_mst_length : in std_logic_vector(C_LENGTH_WIDTH-1 downto 0);
ip2bus_mst_lock : in std_logic;
ip2bus_mst_reset : in std_logic;
ip2bus_mst_type : in std_logic;
ip2bus_mstrd_dst_dsc_n : in std_logic;
ip2bus_mstrd_dst_rdy_n : in std_logic;
ip2bus_mstrd_req : in std_logic;
ip2bus_mstwr_d : in std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
ip2bus_mstwr_eof_n : in std_logic;
ip2bus_mstwr_rem : in std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
ip2bus_mstwr_req : in std_logic;
ip2bus_mstwr_sof_n : in std_logic;
ip2bus_mstwr_src_dsc_n : in std_logic;
ip2bus_mstwr_src_rdy_n : in std_logic;
m_axi_aclk : in std_logic;
m_axi_aresetn : in std_logic;
m_axi_arready : in std_logic;
m_axi_awready : in std_logic;
m_axi_bresp : in std_logic_vector(1 downto 0);
m_axi_bvalid : in std_logic;
m_axi_rdata : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
m_axi_rlast : in std_logic;
m_axi_rresp : in std_logic_vector(1 downto 0);
m_axi_rvalid : in std_logic;
m_axi_wready : in std_logic;
bus2ip_mst_cmd_timeout : out std_logic;
bus2ip_mst_cmdack : out std_logic;
bus2ip_mst_cmplt : out std_logic;
bus2ip_mst_error : out std_logic;
bus2ip_mst_rearbitrate : out std_logic;
bus2ip_mstrd_d : out std_logic_vector(C_NATIVE_DATA_WIDTH-1 downto 0);
bus2ip_mstrd_eof_n : out std_logic;
bus2ip_mstrd_rem : out std_logic_vector((C_NATIVE_DATA_WIDTH/8)-1 downto 0);
bus2ip_mstrd_sof_n : out std_logic;
bus2ip_mstrd_src_dsc_n : out std_logic;
bus2ip_mstrd_src_rdy_n : out std_logic;
bus2ip_mstwr_dst_dsc_n : out std_logic;
bus2ip_mstwr_dst_rdy_n : out std_logic;
m_axi_araddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
m_axi_arburst : out std_logic_vector(1 downto 0);
m_axi_arcache : out std_logic_vector(3 downto 0);
m_axi_arlen : out std_logic_vector(7 downto 0);
m_axi_arprot : out std_logic_vector(2 downto 0);
m_axi_arsize : out std_logic_vector(2 downto 0);
m_axi_arvalid : out std_logic;
m_axi_awaddr : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
m_axi_awburst : out std_logic_vector(1 downto 0);
m_axi_awcache : out std_logic_vector(3 downto 0);
m_axi_awlen : out std_logic_vector(7 downto 0);
m_axi_awprot : out std_logic_vector(2 downto 0);
m_axi_awsize : out std_logic_vector(2 downto 0);
m_axi_awvalid : out std_logic;
m_axi_bready : out std_logic;
m_axi_rready : out std_logic;
m_axi_wdata : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
m_axi_wlast : out std_logic;
m_axi_wstrb : out std_logic_vector((C_M_AXI_DATA_WIDTH/8)-1 downto 0);
m_axi_wvalid : out std_logic;
md_error : out std_logic
);
end component;
---- Architecture declarations -----
constant C_FAMILY : string := "spartan6";
constant C_ADDR_PAD_ZERO : std_logic_vector(31 downto 0) := (others => '0');
-- openMAC REG PLB Slave
constant C_MAC_REG_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG0_BASEADDR;
constant C_MAC_REG_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG0_HIGHADDR;
constant C_MAC_REG_MINSIZE : std_logic_vector(31 downto 0) := conv_std_logic_vector(get_max(conv_integer(C_S_AXI_MAC_REG_RNG0_HIGHADDR), conv_integer(C_S_AXI_MAC_REG_RNG1_HIGHADDR)), 32);
-- openMAC CMP PLB Slave
constant C_MAC_CMP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG1_BASEADDR;
constant C_MAC_CMP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_REG_RNG1_HIGHADDR;
-- openMAC PKT PLB Slave
constant C_MAC_PKT_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_PKT_BASEADDR;
constant C_MAC_PKT_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_MAC_PKT_HIGHADDR;
constant C_MAC_PKT_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_MAC_PKT_HIGHADDR;
-- SimpleIO Slave
constant C_SMP_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_SMP_PCP_BASEADDR;
constant C_SMP_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_SMP_PCP_HIGHADDR;
constant C_SMP_PCP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_SMP_PCP_HIGHADDR;
-- PDI PCP Slave
constant C_PDI_PCP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_PCP_BASEADDR;
constant C_PDI_PCP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_PCP_HIGHADDR;
constant C_PDI_PCP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_PDI_PCP_HIGHADDR;
-- AP PCP Slave
constant C_PDI_AP_BASE : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_AP_BASEADDR;
constant C_PDI_AP_HIGH : std_logic_vector(63 downto 0) := C_ADDR_PAD_ZERO & C_S_AXI_PDI_AP_HIGHADDR;
constant C_PDI_AP_MINSIZE : std_logic_vector(31 downto 0) := C_S_AXI_PDI_AP_HIGHADDR;
-- POWERLINK IP-core
constant C_MAC_PKT_EN : boolean := C_TX_INT_PKT or C_RX_INT_PKT;
constant C_MAC_PKT_RX_EN : boolean := C_RX_INT_PKT;
constant C_DMA_EN : boolean := not C_TX_INT_PKT or not C_RX_INT_PKT;
constant C_PKT_BUF_EN : boolean := C_MAC_PKT_EN;
constant C_M_BURSTCOUNT_WIDTH : integer := integer(ceil(log2(real(get_max(C_MAC_DMA_BURST_SIZE_RX,C_MAC_DMA_BURST_SIZE_TX)/4)))) + 1; --in dwords
constant C_M_FIFO_SIZE_RX : integer := C_MAC_DMA_FIFO_SIZE_RX/4; --in dwords
constant C_M_FIFO_SIZE_TX : integer := C_MAC_DMA_FIFO_SIZE_TX/4; --in dwords
---- Constants -----
constant VCC_CONSTANT : std_logic := '1';
constant GND_CONSTANT : std_logic := '0';
---- Signal declarations used on the diagram ----
signal ap_chipselect : std_logic;
signal ap_read : std_logic;
signal ap_waitrequest : std_logic;
signal ap_write : std_logic;
signal bus2MAC_DMA_mstrd_eof_n : std_logic;
signal bus2MAC_DMA_mstrd_sof_n : std_logic;
signal bus2MAC_DMA_mstrd_src_dsc_n : std_logic;
signal bus2MAC_DMA_mstrd_src_rdy_n : std_logic;
signal bus2MAC_DMA_mstwr_dst_dsc_n : std_logic;
signal bus2MAC_DMA_mstwr_dst_rdy_n : std_logic;
signal bus2MAC_DMA_mst_cmdack : std_logic;
signal bus2MAC_DMA_mst_cmd_timeout : std_logic;
signal bus2MAC_DMA_mst_cmplt : std_logic;
signal bus2MAC_DMA_mst_error : std_logic;
signal bus2MAC_DMA_mst_rearbitrate : std_logic;
signal Bus2MAC_PKT_Clk : std_logic;
signal Bus2MAC_PKT_Reset : std_logic := '0';
signal Bus2MAC_PKT_Resetn : std_logic;
signal Bus2MAC_PKT_RNW : std_logic;
signal Bus2MAC_REG_Clk : std_logic;
signal Bus2MAC_REG_Reset : std_logic := '0';
signal Bus2MAC_REG_Resetn : std_logic;
signal Bus2MAC_REG_RNW : std_logic;
signal Bus2MAC_REG_RNW_n : std_logic;
signal Bus2PDI_AP_Clk : std_logic;
signal Bus2PDI_AP_Reset : std_logic := '0';
signal Bus2PDI_AP_Resetn : std_logic;
signal Bus2PDI_AP_RNW : std_logic;
signal Bus2PDI_PCP_Clk : std_logic;
signal Bus2PDI_PCP_Reset : std_logic := '0';
signal Bus2PDI_PCP_Resetn : std_logic;
signal Bus2PDI_PCP_RNW : std_logic;
signal Bus2SMP_PCP_Clk : std_logic;
signal Bus2SMP_PCP_Reset : std_logic := '0';
signal Bus2SMP_PCP_Resetn : std_logic;
signal Bus2SMP_PCP_RNW : std_logic;
signal clk50 : std_logic;
signal clkAp : std_logic;
signal clkPcp : std_logic;
signal GND : std_logic;
signal IP2Bus_Error_s : std_logic;
signal IP2Bus_RdAck_s : std_logic;
signal IP2Bus_WrAck_s : std_logic;
signal mac_chipselect : std_logic;
signal MAC_CMP2Bus_Error : std_logic;
signal MAC_CMP2Bus_RdAck : std_logic;
signal MAC_CMP2Bus_WrAck : std_logic;
signal MAC_DMA2bus_mstrd_dst_dsc_n : std_logic;
signal MAC_DMA2bus_mstrd_dst_rdy_n : std_logic;
signal MAC_DMA2bus_mstrd_req : std_logic;
signal MAC_DMA2bus_mstwr_eof_n : std_logic;
signal MAC_DMA2bus_mstwr_req : std_logic;
signal MAC_DMA2bus_mstwr_sof_n : std_logic;
signal MAC_DMA2bus_mstwr_src_dsc_n : std_logic;
signal MAC_DMA2bus_mstwr_src_rdy_n : std_logic;
signal MAC_DMA2bus_mst_lock : std_logic;
signal MAC_DMA2bus_mst_reset : std_logic;
signal MAC_DMA2bus_mst_type : std_logic;
signal MAC_DMA_areset : std_logic;
signal mac_irq_s : std_logic;
signal MAC_PKT2Bus_Error : std_logic;
signal MAC_PKT2Bus_RdAck : std_logic;
signal MAC_PKT2Bus_WrAck : std_logic;
signal mac_read : std_logic;
signal MAC_REG2Bus_Error : std_logic;
signal MAC_REG2Bus_RdAck : std_logic;
signal MAC_REG2Bus_WrAck : std_logic;
signal mac_waitrequest : std_logic;
signal mac_write : std_logic;
signal mbf_chipselect : std_logic;
signal mbf_read : std_logic;
signal mbf_waitrequest : std_logic;
signal mbf_write : std_logic;
signal m_clk : std_logic;
signal m_read : std_logic;
signal m_readdatavalid : std_logic;
signal m_waitrequest : std_logic;
signal m_write : std_logic;
signal NET38418 : std_ulogic;
signal NET38470 : std_ulogic;
signal pcp_chipselect : std_logic;
signal pcp_read : std_logic;
signal pcp_waitrequest : std_logic;
signal pcp_write : std_logic;
signal PDI_AP2Bus_Error : std_logic;
signal PDI_AP2Bus_RdAck : std_logic;
signal PDI_AP2Bus_WrAck : std_logic;
signal PDI_PCP2Bus_Error : std_logic;
signal PDI_PCP2Bus_RdAck : std_logic;
signal PDI_PCP2Bus_WrAck : std_logic;
signal pkt_clk : std_logic;
signal rst : std_logic := '0';
signal rstAp : std_logic := '0';
signal rstPcp : std_logic := '0';
signal smp_address : std_logic;
signal smp_chipselect : std_logic;
signal SMP_PCP2Bus_Error : std_logic;
signal SMP_PCP2Bus_RdAck : std_logic;
signal SMP_PCP2Bus_WrAck : std_logic;
signal smp_read : std_logic;
signal smp_waitrequest : std_logic;
signal smp_write : std_logic;
signal tcp_chipselect : std_logic;
signal tcp_irq_s : std_logic;
signal tcp_read : std_logic;
signal tcp_waitrequest : std_logic;
signal tcp_write : std_logic;
signal VCC : std_logic;
signal ap_address : std_logic_vector (12 downto 0);
signal ap_byteenable : std_logic_vector (3 downto 0);
signal ap_readdata : std_logic_vector (31 downto 0);
signal ap_writedata : std_logic_vector (31 downto 0);
signal bus2MAC_DMA_mstrd_d : std_logic_vector (C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0);
signal bus2MAC_DMA_mstrd_rem : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0);
signal Bus2MAC_PKT_Addr : std_logic_vector (C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0);
signal Bus2MAC_PKT_BE : std_logic_vector ((C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0);
signal Bus2MAC_PKT_CS : std_logic_vector (0 downto 0);
signal Bus2MAC_PKT_Data : std_logic_vector (C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
signal Bus2MAC_REG_Addr : std_logic_vector (C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
signal Bus2MAC_REG_BE : std_logic_vector ((C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0);
signal Bus2MAC_REG_CS : std_logic_vector (1 downto 0);
signal Bus2MAC_REG_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal Bus2PDI_AP_Addr : std_logic_vector (C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0);
signal Bus2PDI_AP_BE : std_logic_vector ((C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0);
signal Bus2PDI_AP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_AP_Data : std_logic_vector (C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0);
signal Bus2PDI_PCP_Addr : std_logic_vector (C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0);
signal Bus2PDI_PCP_BE : std_logic_vector ((C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0);
signal Bus2PDI_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2PDI_PCP_Data : std_logic_vector (C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0);
signal Bus2SMP_PCP_Addr : std_logic_vector (C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0);
signal Bus2SMP_PCP_BE : std_logic_vector ((C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0);
signal Bus2SMP_PCP_CS : std_logic_vector (0 downto 0);
signal Bus2SMP_PCP_Data : std_logic_vector (C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0);
signal IP2Bus_Data_s : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal mac_address : std_logic_vector (11 downto 0);
signal mac_address_full : std_logic_vector (C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0);
signal mac_byteenable : std_logic_vector (1 downto 0);
signal MAC_CMP2Bus_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal MAC_DMA2Bus_MstWr_d : std_logic_vector (C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0);
signal MAC_DMA2bus_mstwr_rem : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0);
signal MAC_DMA2bus_mst_addr : std_logic_vector (C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0);
signal MAC_DMA2bus_mst_be : std_logic_vector ((C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0);
signal MAC_DMA2bus_mst_length : std_logic_vector (C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0);
signal MAC_PKT2Bus_Data : std_logic_vector (C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0);
signal mac_readdata : std_logic_vector (15 downto 0);
signal MAC_REG2Bus_Data : std_logic_vector (C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0);
signal mac_writedata : std_logic_vector (15 downto 0);
signal mbf_address : std_logic_vector (C_MAC_PKT_SIZE_LOG2-3 downto 0);
signal mbf_byteenable : std_logic_vector (3 downto 0);
signal mbf_readdata : std_logic_vector (31 downto 0);
signal mbf_writedata : std_logic_vector (31 downto 0);
signal m_address : std_logic_vector (29 downto 0);
signal m_burstcount : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_burstcounter : std_logic_vector (C_M_BURSTCOUNT_WIDTH-1 downto 0);
signal m_byteenable : std_logic_vector (3 downto 0);
signal m_readdata : std_logic_vector (31 downto 0);
signal m_writedata : std_logic_vector (31 downto 0);
signal pcp_address : std_logic_vector (12 downto 0);
signal pcp_byteenable : std_logic_vector (3 downto 0);
signal pcp_readdata : std_logic_vector (31 downto 0);
signal pcp_writedata : std_logic_vector (31 downto 0);
signal PDI_AP2Bus_Data : std_logic_vector (C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0);
signal PDI_PCP2Bus_Data : std_logic_vector (C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0);
signal smp_byteenable : std_logic_vector (3 downto 0);
signal SMP_PCP2Bus_Data : std_logic_vector (C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0);
signal smp_readdata : std_logic_vector (31 downto 0);
signal smp_writedata : std_logic_vector (31 downto 0);
signal tcp_address : std_logic_vector (1 downto 0);
signal tcp_byteenable : std_logic_vector (3 downto 0);
signal tcp_readdata : std_logic_vector (31 downto 0);
signal tcp_writedata : std_logic_vector (31 downto 0);
begin
---- User Signal Assignments ----
-- connect mac reg with mac cmp or reg output signals
with Bus2MAC_REG_CS select
IP2Bus_Data_s <= MAC_CMP2Bus_Data when "01",
MAC_REG2Bus_Data when others; --"10" and others are decoded to MAC_REG
IP2Bus_WrAck_s <= MAC_REG2Bus_WrAck or MAC_CMP2Bus_WrAck;
IP2Bus_RdAck_s <= MAC_REG2Bus_RdAck or MAC_CMP2Bus_RdAck;
IP2Bus_Error_s <= MAC_REG2Bus_Error or MAC_CMP2Bus_Error;
mac_address <= mac_address_full(mac_address'range);
--mac_cmp assignments
---cmp_clk <= Bus2MAC_CMP_Clk;
tcp_writedata <= Bus2MAC_REG_Data;
tcp_read <= Bus2MAC_REG_RNW;
tcp_write <= not Bus2MAC_REG_RNW;
tcp_chipselect <= Bus2MAC_REG_CS(0);
tcp_byteenable <= Bus2MAC_REG_BE;
tcp_address <= Bus2MAC_REG_Addr(3 downto 2);
MAC_CMP2Bus_Data <= tcp_readdata;
MAC_CMP2Bus_RdAck <= tcp_chipselect and tcp_read and not tcp_waitrequest;
MAC_CMP2Bus_WrAck <= tcp_chipselect and tcp_write and not tcp_waitrequest;
MAC_CMP2Bus_Error <= '0';
--mac_pkt assignments
pkt_clk <= Bus2MAC_PKT_Clk;
Bus2MAC_PKT_Reset <= not Bus2MAC_PKT_Resetn;
mbf_writedata <= Bus2MAC_PKT_Data;
-- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
-- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
mbf_read <= Bus2MAC_PKT_RNW;
mbf_write <= not Bus2MAC_PKT_RNW;
mbf_chipselect <= Bus2MAC_PKT_CS(0);
mbf_byteenable <= Bus2MAC_PKT_BE;
mbf_address <= Bus2MAC_PKT_Addr(C_MAC_PKT_SIZE_LOG2-1 downto 2);
MAC_PKT2Bus_Data <= mbf_readdata;
MAC_PKT2Bus_RdAck <= mbf_chipselect and mbf_read and not mbf_waitrequest;
MAC_PKT2Bus_WrAck <= mbf_chipselect and mbf_write and not mbf_waitrequest;
MAC_PKT2Bus_Error <= '0';
--test_port
--test_port(181 downto 179) <= mac_chipselect & mac_write & mac_read;
--test_port(178) <= mac_waitrequest;
--test_port(177 downto 176) <= mac_byteenable;
--
--test_port(171 downto 160) <= mac_address;
--test_port(159 downto 144) <= mac_writedata;
--test_port(143 downto 128) <= mac_readdata;
--
--test_port(104 downto 102) <= Bus2MAC_REG_CS & Bus2MAC_REG_RNW;
--test_port(101 downto 100) <= IP2Bus_WrAck_s & IP2Bus_RdAck_s;
--test_port(99 downto 96) <= Bus2MAC_REG_BE;
--
--test_port(95 downto 64) <= Bus2MAC_REG_Addr;
--test_port(63 downto 32) <= Bus2MAC_REG_Data;
--test_port(31 downto 0) <= IP2Bus_Data_s;
test_port(255 downto 251) <= m_read & m_write & m_waitrequest & m_readdatavalid & MAC_DMA2Bus_Mst_Type;
test_port(244 downto 240) <= MAC_DMA2Bus_MstWr_Req & MAC_DMA2Bus_MstWr_sof_n & MAC_DMA2Bus_MstWr_eof_n & MAC_DMA2Bus_MstWr_src_rdy_n & Bus2MAC_DMA_MstWr_dst_rdy_n;
test_port(234 downto 230) <= MAC_DMA2Bus_MstRd_Req & Bus2MAC_DMA_MstRd_sof_n & Bus2MAC_DMA_MstRd_eof_n & Bus2MAC_DMA_MstRd_src_rdy_n & MAC_DMA2Bus_MstRd_dst_rdy_n;
test_port(142 downto 140) <= Bus2MAC_DMA_Mst_Cmplt & Bus2MAC_DMA_Mst_Error & Bus2MAC_DMA_Mst_Cmd_Timeout;
test_port(MAC_DMA2Bus_Mst_Length'length+120-1 downto 120) <= MAC_DMA2Bus_Mst_Length;
test_port(m_burstcount'length+110-1 downto 110) <= m_burstcount;
test_port(m_burstcounter'length+96-1 downto 96) <= m_burstcounter;
test_port(95 downto 64) <= "00" & m_address;
test_port(63 downto 32) <= m_writedata;
test_port(31 downto 0) <= m_readdata;
---- Component instantiations ----
MAC_REG_16to32 : openMAC_16to32conv
generic map (
bus_address_width => C_S_AXI_MAC_REG_ADDR_WIDTH,
gEndian => "little"
)
port map(
bus_ack_rd => MAC_REG2Bus_RdAck,
bus_ack_wr => MAC_REG2Bus_WrAck,
bus_address => Bus2MAC_REG_Addr( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
bus_byteenable => Bus2MAC_REG_BE( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ),
bus_read => Bus2MAC_REG_RNW,
bus_readdata => MAC_REG2Bus_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
bus_select => Bus2MAC_REG_CS(1),
bus_write => Bus2MAC_REG_RNW_n,
bus_writedata => Bus2MAC_REG_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
clk => Bus2MAC_REG_Clk,
rst => Bus2MAC_REG_Reset,
s_address => mac_address_full( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
s_byteenable => mac_byteenable,
s_chipselect => mac_chipselect,
s_read => mac_read,
s_readdata => mac_readdata,
s_waitrequest => mac_waitrequest,
s_write => mac_write,
s_writedata => mac_writedata
);
MAC_REG_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_REG_BASE,C_MAC_REG_HIGH,C_MAC_CMP_BASE,C_MAC_CMP_HIGH),
C_ARD_NUM_CE_ARRAY => (1,1),
C_DPHASE_TIMEOUT => C_S_AXI_MAC_REG_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_REG_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_REG_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_MAC_REG_MINSIZE,
C_USE_WSTRB => C_S_AXI_MAC_REG_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2MAC_REG_Addr( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_REG_BE( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_REG_CS( 1 downto 0 ),
Bus2IP_Clk => Bus2MAC_REG_Clk,
Bus2IP_Data => Bus2MAC_REG_Data( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_REG_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2MAC_REG_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => IP2Bus_Data_s( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => IP2Bus_Error_s,
IP2Bus_RdAck => IP2Bus_RdAck_s,
IP2Bus_WrAck => IP2Bus_WrAck_s,
S_AXI_ACLK => S_AXI_MAC_REG_ACLK,
S_AXI_ARADDR => S_AXI_MAC_REG_ARADDR( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_MAC_REG_ARESETN,
S_AXI_ARREADY => S_AXI_MAC_REG_ARREADY,
S_AXI_ARVALID => S_AXI_MAC_REG_ARVALID,
S_AXI_AWADDR => S_AXI_MAC_REG_AWADDR( C_S_AXI_MAC_REG_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_MAC_REG_AWREADY,
S_AXI_AWVALID => S_AXI_MAC_REG_AWVALID,
S_AXI_BREADY => S_AXI_MAC_REG_BREADY,
S_AXI_BRESP => S_AXI_MAC_REG_BRESP,
S_AXI_BVALID => S_AXI_MAC_REG_BVALID,
S_AXI_RDATA => S_AXI_MAC_REG_RDATA( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_MAC_REG_RREADY,
S_AXI_RRESP => S_AXI_MAC_REG_RRESP,
S_AXI_RVALID => S_AXI_MAC_REG_RVALID,
S_AXI_WDATA => S_AXI_MAC_REG_WDATA( C_S_AXI_MAC_REG_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_MAC_REG_WREADY,
S_AXI_WSTRB => S_AXI_MAC_REG_WSTRB( (C_S_AXI_MAC_REG_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_MAC_REG_WVALID
);
THE_POWERLINK_IP_CORE : powerlink
generic map (
Simulate => false,
endian_g => "little",
gNumSmi => C_NUM_SMI,
genABuf1_g => C_PDI_GEN_ASYNC_BUF_0,
genABuf2_g => C_PDI_GEN_ASYNC_BUF_1,
genEvent_g => C_PDI_GEN_EVENT,
genInternalAp_g => C_GEN_AXI_BUS_IF,
genIoBuf_g => false,
genLedGadget_g => C_PDI_GEN_LED,
genOnePdiClkDomain_g => false,
genPdi_g => C_GEN_PDI,
genSimpleIO_g => C_GEN_SIMPLE_IO,
genSmiIO => false,
genSpiAp_g => C_GEN_SPI_IF,
genTimeSync_g => C_PDI_GEN_TIME_SYNC,
gen_dma_observer_g => C_OBSERVER_ENABLE,
iAsyBuf1Size_g => C_PDI_ASYNC_BUF_0,
iAsyBuf2Size_g => C_PDI_ASYNC_BUF_1,
iBufSizeLOG2_g => C_MAC_PKT_SIZE_LOG2,
iBufSize_g => C_MAC_PKT_SIZE,
iPdiRev_g => 2,
iRpdo0BufSize_g => C_RPDO_0_BUF_SIZE,
iRpdo1BufSize_g => C_RPDO_1_BUF_SIZE,
iRpdo2BufSize_g => C_RPDO_2_BUF_SIZE,
iRpdos_g => C_NUM_RPDO,
iTpdoBufSize_g => C_TPDO_BUF_SIZE,
iTpdos_g => C_NUM_TPDO,
m_burstcount_const_g => true,
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH,
m_data_width_g => 32,
m_rx_burst_size_g => C_MAC_DMA_BURST_SIZE_RX/4,
m_rx_fifo_size_g => C_M_FIFO_SIZE_RX,
m_tx_burst_size_g => C_MAC_DMA_BURST_SIZE_TX/4,
m_tx_fifo_size_g => C_M_FIFO_SIZE_TX,
papBigEnd_g => false,
papDataWidth_g => C_PAP_DATA_WIDTH,
papLowAct_g => C_PAP_LOW_ACT,
pioValLen_g => C_PIO_VAL_LENGTH,
spiBigEnd_g => false,
spiCPHA_g => C_SPI_CPHA,
spiCPOL_g => C_SPI_CPOL,
use2ndCmpTimer_g => C_PDI_GEN_SECOND_TIMER,
use2ndPhy_g => C_USE_2ND_PHY,
useIntPacketBuf_g => C_MAC_PKT_EN,
useRmii_g => C_USE_RMII,
useRxIntPacketBuf_g => C_MAC_PKT_RX_EN
)
port map(
ap_address => ap_address,
ap_asyncIrq => ap_asyncIrq,
ap_asyncIrq_n => ap_asyncIrq_n,
ap_byteenable => ap_byteenable,
ap_chipselect => ap_chipselect,
ap_irq => open,
ap_irq_n => open,
ap_read => ap_read,
ap_readdata => ap_readdata,
ap_syncIrq => ap_syncIrq,
ap_syncIrq_n => ap_syncIrq_n,
ap_waitrequest => ap_waitrequest,
ap_write => ap_write,
ap_writedata => ap_writedata,
clk50 => clk50,
clkAp => clkAp,
clkEth => clk100,
clkPcp => clkPcp,
led_error => led_error,
led_gpo => led_gpo,
led_opt => led_opt,
led_phyAct => led_phyAct,
led_phyLink => led_phyLink,
led_status => led_status,
m_address => m_address,
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable( 3 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata( 31 downto 0 ),
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata( 31 downto 0 ),
mac_address => mac_address,
mac_byteenable => mac_byteenable,
mac_chipselect => mac_chipselect,
mac_irq => mac_irq_s,
mac_read => mac_read,
mac_readdata => mac_readdata,
mac_waitrequest => mac_waitrequest,
mac_write => mac_write,
mac_writedata => mac_writedata,
mbf_address => mbf_address( C_MAC_PKT_SIZE_LOG2-3 downto 0 ),
mbf_byteenable => mbf_byteenable,
mbf_chipselect => mbf_chipselect,
mbf_read => mbf_read,
mbf_readdata => mbf_readdata,
mbf_waitrequest => mbf_waitrequest,
mbf_write => mbf_write,
mbf_writedata => mbf_writedata,
pap_ack => pap_ack,
pap_ack_n => pap_ack_n,
pap_addr => pap_addr,
pap_be => pap_be( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_be_n => pap_be_n( C_PAP_DATA_WIDTH/8-1 downto 0 ),
pap_cs => pap_cs,
pap_cs_n => pap_cs_n,
pap_data => open,
pap_data_I => pap_data_I( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_O => pap_data_O( C_PAP_DATA_WIDTH-1 downto 0 ),
pap_data_T => pap_data_T,
pap_gpio => open,
pap_gpio_I => pap_gpio_I,
pap_gpio_O => pap_gpio_O,
pap_gpio_T => pap_gpio_T,
pap_rd => pap_rd,
pap_rd_n => pap_rd_n,
pap_wr => pap_wr,
pap_wr_n => pap_wr_n,
pcp_address => pcp_address,
pcp_byteenable => pcp_byteenable,
pcp_chipselect => pcp_chipselect,
pcp_read => pcp_read,
pcp_readdata => pcp_readdata,
pcp_waitrequest => pcp_waitrequest,
pcp_write => pcp_write,
pcp_writedata => pcp_writedata,
phy0_Rst_n => phy0_Rst_n,
phy0_RxDat => phy0_RxDat,
phy0_RxDv => phy0_RxDv,
phy0_RxErr => phy0_RxErr,
phy0_SMIClk => phy0_SMIClk,
phy0_SMIDat => open,
phy0_SMIDat_I => phy0_SMIDat_I,
phy0_SMIDat_O => phy0_SMIDat_O,
phy0_SMIDat_T => phy0_SMIDat_T,
phy0_TxDat => phy0_TxDat,
phy0_TxEn => phy0_TxEn,
phy0_link => phy0_link,
phy1_Rst_n => phy1_Rst_n,
phy1_RxDat => phy1_RxDat,
phy1_RxDv => phy1_RxDv,
phy1_RxErr => phy1_RxErr,
phy1_SMIClk => phy1_SMIClk,
phy1_SMIDat => open,
phy1_SMIDat_I => phy1_SMIDat_I,
phy1_SMIDat_O => phy1_SMIDat_O,
phy1_SMIDat_T => phy1_SMIDat_T,
phy1_TxDat => phy1_TxDat,
phy1_TxEn => phy1_TxEn,
phy1_link => phy1_link,
phyMii0_RxClk => phyMii0_RxClk,
phyMii0_RxDat => phyMii0_RxDat,
phyMii0_RxDv => phyMii0_RxDv,
phyMii0_RxEr => phyMii0_RxEr,
phyMii0_TxClk => phyMii0_TxClk,
phyMii0_TxDat => phyMii0_TxDat,
phyMii0_TxEn => phyMii0_TxEn,
phyMii0_TxEr => phyMii0_TxEr,
phyMii1_RxClk => phyMii1_RxClk,
phyMii1_RxDat => phyMii1_RxDat,
phyMii1_RxDv => phyMii1_RxDv,
phyMii1_RxEr => phyMii1_RxEr,
phyMii1_TxClk => phyMii1_TxClk,
phyMii1_TxDat => phyMii1_TxDat,
phyMii1_TxEn => phyMii1_TxEn,
phyMii1_TxEr => phyMii1_TxEr,
phy_Rst_n => phy_Rst_n,
phy_SMIClk => phy_SMIClk,
phy_SMIDat => open,
phy_SMIDat_I => phy_SMIDat_I,
phy_SMIDat_O => phy_SMIDat_O,
phy_SMIDat_T => phy_SMIDat_T,
pio_operational => pio_operational,
pio_pconfig => pio_pconfig,
pio_portInLatch => pio_portInLatch,
pio_portOutValid => pio_portOutValid,
pio_portio => open,
pio_portio_I => pio_portio_I,
pio_portio_O => pio_portio_O,
pio_portio_T => pio_portio_T,
pkt_clk => pkt_clk,
rst => rst,
rstAp => rstAp,
rstPcp => rstPcp,
smp_address => smp_address,
smp_byteenable => smp_byteenable,
smp_read => smp_read,
smp_readdata => smp_readdata,
smp_waitrequest => smp_waitrequest,
smp_write => smp_write,
smp_writedata => smp_writedata,
spi_clk => spi_clk,
spi_miso => spi_miso,
spi_mosi => spi_mosi,
spi_sel_n => spi_sel_n,
tcp_address => tcp_address,
tcp_byteenable => tcp_byteenable,
tcp_chipselect => tcp_chipselect,
tcp_irq => tcp_irq_s,
tcp_read => tcp_read,
tcp_readdata => tcp_readdata,
tcp_waitrequest => tcp_waitrequest,
tcp_write => tcp_write,
tcp_writedata => tcp_writedata
);
MAC_DMA_areset <= not(M_AXI_MAC_DMA_aresetn);
Bus2MAC_REG_RNW_n <= not(Bus2MAC_REG_RNW);
clk50 <= Bus2MAC_REG_Clk;
Bus2MAC_REG_Reset <= not(Bus2MAC_REG_Resetn);
rstPcp <= Bus2SMP_PCP_Reset or Bus2PDI_PCP_Reset or Bus2MAC_PKT_Reset;
rstAp <= Bus2PDI_AP_Reset;
rst <= Bus2MAC_REG_Reset;
---- Power , ground assignment ----
GND <= GND_CONSTANT;
VCC <= VCC_CONSTANT;
MAC_REG2Bus_Error <= GND;
---- Terminal assignment ----
-- Output\buffer terminals
mac_irq <= mac_irq_s;
tcp_irq <= tcp_irq_s;
---- Generate statements ----
genMacDmaPlbBurst : if C_DMA_EN = TRUE generate
begin
MAC_DMA_AXI_BURST_MASTER : axi_master_burst
generic map (
C_ADDR_PIPE_DEPTH => 1,
C_FAMILY => C_FAMILY,
C_LENGTH_WIDTH => C_M_AXI_MAC_DMA_LENGTH_WIDTH,
C_MAX_BURST_LEN => C_M_AXI_MAC_DMA_MAX_BURST_LEN,
C_M_AXI_ADDR_WIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH,
C_M_AXI_DATA_WIDTH => C_M_AXI_MAC_DMA_DATA_WIDTH,
C_NATIVE_DATA_WIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH
)
port map(
bus2ip_mst_cmd_timeout => bus2MAC_DMA_mst_cmd_timeout,
bus2ip_mst_cmdack => bus2MAC_DMA_mst_cmdack,
bus2ip_mst_cmplt => bus2MAC_DMA_mst_cmplt,
bus2ip_mst_error => bus2MAC_DMA_mst_error,
bus2ip_mst_rearbitrate => bus2MAC_DMA_mst_rearbitrate,
bus2ip_mstrd_d => bus2MAC_DMA_mstrd_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ),
bus2ip_mstrd_eof_n => bus2MAC_DMA_mstrd_eof_n,
bus2ip_mstrd_rem => bus2MAC_DMA_mstrd_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
bus2ip_mstrd_sof_n => bus2MAC_DMA_mstrd_sof_n,
bus2ip_mstrd_src_dsc_n => bus2MAC_DMA_mstrd_src_dsc_n,
bus2ip_mstrd_src_rdy_n => bus2MAC_DMA_mstrd_src_rdy_n,
bus2ip_mstwr_dst_dsc_n => bus2MAC_DMA_mstwr_dst_dsc_n,
bus2ip_mstwr_dst_rdy_n => bus2MAC_DMA_mstwr_dst_rdy_n,
ip2bus_mst_addr => MAC_DMA2bus_mst_addr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ),
ip2bus_mst_be => MAC_DMA2bus_mst_be( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
ip2bus_mst_length => MAC_DMA2bus_mst_length( C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0 ),
ip2bus_mst_lock => MAC_DMA2bus_mst_lock,
ip2bus_mst_reset => MAC_DMA2bus_mst_reset,
ip2bus_mst_type => MAC_DMA2bus_mst_type,
ip2bus_mstrd_dst_dsc_n => MAC_DMA2bus_mstrd_dst_dsc_n,
ip2bus_mstrd_dst_rdy_n => MAC_DMA2bus_mstrd_dst_rdy_n,
ip2bus_mstrd_req => MAC_DMA2bus_mstrd_req,
ip2bus_mstwr_d => MAC_DMA2bus_mstwr_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ),
ip2bus_mstwr_eof_n => MAC_DMA2bus_mstwr_eof_n,
ip2bus_mstwr_rem => MAC_DMA2bus_mstwr_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
ip2bus_mstwr_req => MAC_DMA2bus_mstwr_req,
ip2bus_mstwr_sof_n => MAC_DMA2bus_mstwr_sof_n,
ip2bus_mstwr_src_dsc_n => MAC_DMA2bus_mstwr_src_dsc_n,
ip2bus_mstwr_src_rdy_n => MAC_DMA2bus_mstwr_src_rdy_n,
m_axi_aclk => M_AXI_MAC_DMA_aclk,
m_axi_araddr => M_AXI_MAC_DMA_araddr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ),
m_axi_arburst => M_AXI_MAC_DMA_arburst,
m_axi_arcache => M_AXI_MAC_DMA_arcache,
m_axi_aresetn => M_AXI_MAC_DMA_aresetn,
m_axi_arlen => M_AXI_MAC_DMA_arlen,
m_axi_arprot => M_AXI_MAC_DMA_arprot,
m_axi_arready => M_AXI_MAC_DMA_arready,
m_axi_arsize => M_AXI_MAC_DMA_arsize,
m_axi_arvalid => M_AXI_MAC_DMA_arvalid,
m_axi_awaddr => M_AXI_MAC_DMA_awaddr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ),
m_axi_awburst => M_AXI_MAC_DMA_awburst,
m_axi_awcache => M_AXI_MAC_DMA_awcache,
m_axi_awlen => M_AXI_MAC_DMA_awlen,
m_axi_awprot => M_AXI_MAC_DMA_awprot,
m_axi_awready => M_AXI_MAC_DMA_awready,
m_axi_awsize => M_AXI_MAC_DMA_awsize,
m_axi_awvalid => M_AXI_MAC_DMA_awvalid,
m_axi_bready => M_AXI_MAC_DMA_bready,
m_axi_bresp => M_AXI_MAC_DMA_bresp,
m_axi_bvalid => M_AXI_MAC_DMA_bvalid,
m_axi_rdata => M_AXI_MAC_DMA_rdata( C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0 ),
m_axi_rlast => M_AXI_MAC_DMA_rlast,
m_axi_rready => M_AXI_MAC_DMA_rready,
m_axi_rresp => M_AXI_MAC_DMA_rresp,
m_axi_rvalid => M_AXI_MAC_DMA_rvalid,
m_axi_wdata => M_AXI_MAC_DMA_wdata( C_M_AXI_MAC_DMA_DATA_WIDTH-1 downto 0 ),
m_axi_wlast => M_AXI_MAC_DMA_wlast,
m_axi_wready => M_AXI_MAC_DMA_wready,
m_axi_wstrb => M_AXI_MAC_DMA_wstrb( (C_M_AXI_MAC_DMA_DATA_WIDTH/8)-1 downto 0 ),
m_axi_wvalid => M_AXI_MAC_DMA_wvalid,
md_error => M_AXI_MAC_DMA_md_error
);
end generate genMacDmaPlbBurst;
genThePlbMaster : if C_DMA_EN = TRUE generate
begin
THE_IPIF_MASTER_HANDLER : ipif_master_handler
generic map (
C_MAC_DMA_IPIF_AWIDTH => C_M_AXI_MAC_DMA_ADDR_WIDTH,
C_MAC_DMA_IPIF_NATIVE_DWIDTH => C_M_AXI_MAC_DMA_NATIVE_DWIDTH,
dma_highadr_g => m_address'high,
gen_rx_fifo_g => not C_RX_INT_PKT,
gen_tx_fifo_g => not C_TX_INT_PKT,
m_burstcount_width_g => C_M_BURSTCOUNT_WIDTH
)
port map(
Bus2MAC_DMA_MstRd_d => bus2MAC_DMA_mstrd_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ),
Bus2MAC_DMA_MstRd_eof_n => bus2MAC_DMA_mstrd_eof_n,
Bus2MAC_DMA_MstRd_rem => bus2MAC_DMA_mstrd_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
Bus2MAC_DMA_MstRd_sof_n => bus2MAC_DMA_mstrd_sof_n,
Bus2MAC_DMA_MstRd_src_dsc_n => bus2MAC_DMA_mstrd_src_dsc_n,
Bus2MAC_DMA_MstRd_src_rdy_n => bus2MAC_DMA_mstrd_src_rdy_n,
Bus2MAC_DMA_MstWr_dst_dsc_n => bus2MAC_DMA_mstwr_dst_dsc_n,
Bus2MAC_DMA_MstWr_dst_rdy_n => bus2MAC_DMA_mstwr_dst_rdy_n,
Bus2MAC_DMA_Mst_CmdAck => bus2MAC_DMA_mst_cmdack,
Bus2MAC_DMA_Mst_Cmd_Timeout => bus2MAC_DMA_mst_cmd_timeout,
Bus2MAC_DMA_Mst_Cmplt => bus2MAC_DMA_mst_cmplt,
Bus2MAC_DMA_Mst_Error => bus2MAC_DMA_mst_error,
Bus2MAC_DMA_Mst_Rearbitrate => bus2MAC_DMA_mst_rearbitrate,
MAC_DMA2Bus_MstRd_Req => MAC_DMA2bus_mstrd_req,
MAC_DMA2Bus_MstRd_dst_dsc_n => MAC_DMA2bus_mstrd_dst_dsc_n,
MAC_DMA2Bus_MstRd_dst_rdy_n => MAC_DMA2bus_mstrd_dst_rdy_n,
MAC_DMA2Bus_MstWr_Req => MAC_DMA2bus_mstwr_req,
MAC_DMA2Bus_MstWr_d => MAC_DMA2Bus_MstWr_d( C_M_AXI_MAC_DMA_NATIVE_DWIDTH-1 downto 0 ),
MAC_DMA2Bus_MstWr_eof_n => MAC_DMA2bus_mstwr_eof_n,
MAC_DMA2Bus_MstWr_rem => MAC_DMA2bus_mstwr_rem( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
MAC_DMA2Bus_MstWr_sof_n => MAC_DMA2bus_mstwr_sof_n,
MAC_DMA2Bus_MstWr_src_dsc_n => MAC_DMA2bus_mstwr_src_dsc_n,
MAC_DMA2Bus_MstWr_src_rdy_n => MAC_DMA2bus_mstwr_src_rdy_n,
MAC_DMA2Bus_Mst_Addr => MAC_DMA2bus_mst_addr( C_M_AXI_MAC_DMA_ADDR_WIDTH-1 downto 0 ),
MAC_DMA2Bus_Mst_BE => MAC_DMA2bus_mst_be( (C_M_AXI_MAC_DMA_NATIVE_DWIDTH/8)-1 downto 0 ),
MAC_DMA2Bus_Mst_Length => MAC_DMA2bus_mst_length( C_M_AXI_MAC_DMA_LENGTH_WIDTH-1 downto 0 ),
MAC_DMA2Bus_Mst_Lock => MAC_DMA2bus_mst_lock,
MAC_DMA2Bus_Mst_Reset => MAC_DMA2bus_mst_reset,
MAC_DMA2Bus_Mst_Type => MAC_DMA2bus_mst_type,
MAC_DMA_CLK => M_AXI_MAC_DMA_aclk,
MAC_DMA_Rst => MAC_DMA_areset,
m_address => m_address( 29 downto 0 ),
m_burstcount => m_burstcount( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_burstcounter => m_burstcounter( C_M_BURSTCOUNT_WIDTH-1 downto 0 ),
m_byteenable => m_byteenable,
m_clk => m_clk,
m_read => m_read,
m_readdata => m_readdata,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
m_writedata => m_writedata
);
end generate genThePlbMaster;
genMacPktPLbSingleSlave : if C_PKT_BUF_EN generate
begin
MAC_PKT_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_MAC_PKT_BASE,C_MAC_PKT_HIGH),
C_ARD_NUM_CE_ARRAY => (0=>1),
C_DPHASE_TIMEOUT => C_S_AXI_MAC_PKT_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_MAC_PKT_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_MAC_PKT_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_MAC_PKT_MINSIZE,
C_USE_WSTRB => C_S_AXI_MAC_PKT_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2MAC_PKT_Addr( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2MAC_PKT_BE( (C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2MAC_PKT_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2MAC_PKT_Clk,
Bus2IP_Data => Bus2MAC_PKT_Data( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2MAC_PKT_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2MAC_PKT_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => MAC_PKT2Bus_Data( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => MAC_PKT2Bus_Error,
IP2Bus_RdAck => MAC_PKT2Bus_RdAck,
IP2Bus_WrAck => MAC_PKT2Bus_WrAck,
S_AXI_ACLK => S_AXI_MAC_PKT_ACLK,
S_AXI_ARADDR => S_AXI_MAC_PKT_ARADDR( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_MAC_PKT_ARESETN,
S_AXI_ARREADY => S_AXI_MAC_PKT_ARREADY,
S_AXI_ARVALID => S_AXI_MAC_PKT_ARVALID,
S_AXI_AWADDR => S_AXI_MAC_PKT_AWADDR( C_S_AXI_MAC_PKT_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_MAC_PKT_AWREADY,
S_AXI_AWVALID => S_AXI_MAC_PKT_AWVALID,
S_AXI_BREADY => S_AXI_MAC_PKT_BREADY,
S_AXI_BRESP => S_AXI_MAC_PKT_BRESP,
S_AXI_BVALID => S_AXI_MAC_PKT_BVALID,
S_AXI_RDATA => S_AXI_MAC_PKT_RDATA( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_MAC_PKT_RREADY,
S_AXI_RRESP => S_AXI_MAC_PKT_RRESP,
S_AXI_RVALID => S_AXI_MAC_PKT_RVALID,
S_AXI_WDATA => S_AXI_MAC_PKT_WDATA( C_S_AXI_MAC_PKT_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_MAC_PKT_WREADY,
S_AXI_WSTRB => S_AXI_MAC_PKT_WSTRB( (C_S_AXI_MAC_PKT_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_MAC_PKT_WVALID
);
end generate genMacPktPLbSingleSlave;
genPdiPcp : if (C_GEN_PDI) generate
begin
PDI_PCP_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_PCP_BASE,C_PDI_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0=>1),
C_DPHASE_TIMEOUT => C_S_AXI_PDI_PCP_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_PDI_PCP_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_PDI_PCP_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_PDI_PCP_MINSIZE,
C_USE_WSTRB => C_S_AXI_PDI_PCP_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2PDI_PCP_Addr( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_PCP_BE( (C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_PCP_Clk,
Bus2IP_Data => Bus2PDI_PCP_Data( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_PCP_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2PDI_PCP_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => PDI_PCP2Bus_Data( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => PDI_PCP2Bus_Error,
IP2Bus_RdAck => PDI_PCP2Bus_RdAck,
IP2Bus_WrAck => PDI_PCP2Bus_WrAck,
S_AXI_ACLK => S_AXI_PDI_PCP_ACLK,
S_AXI_ARADDR => S_AXI_PDI_PCP_ARADDR( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_PDI_PCP_ARESETN,
S_AXI_ARREADY => S_AXI_PDI_PCP_ARREADY,
S_AXI_ARVALID => S_AXI_PDI_PCP_ARVALID,
S_AXI_AWADDR => S_AXI_PDI_PCP_AWADDR( C_S_AXI_PDI_PCP_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_PDI_PCP_AWREADY,
S_AXI_AWVALID => S_AXI_PDI_PCP_AWVALID,
S_AXI_BREADY => S_AXI_PDI_PCP_BREADY,
S_AXI_BRESP => S_AXI_PDI_PCP_BRESP,
S_AXI_BVALID => S_AXI_PDI_PCP_BVALID,
S_AXI_RDATA => S_AXI_PDI_PCP_RDATA( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_PDI_PCP_RREADY,
S_AXI_RRESP => S_AXI_PDI_PCP_RRESP,
S_AXI_RVALID => S_AXI_PDI_PCP_RVALID,
S_AXI_WDATA => S_AXI_PDI_PCP_WDATA( C_S_AXI_PDI_PCP_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_PDI_PCP_WREADY,
S_AXI_WSTRB => S_AXI_PDI_PCP_WSTRB( (C_S_AXI_PDI_PCP_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_PDI_PCP_WVALID
);
end generate genPdiPcp;
genPcpPdiLink : if C_GEN_PDI generate
begin
--pdi_pcp assignments
clkPcp <= Bus2PDI_PCP_Clk;
Bus2PDI_PCP_Reset <= not Bus2PDI_PCP_Resetn;
pcp_writedata <= Bus2PDI_PCP_Data;
-- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
-- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
pcp_read <= Bus2PDI_PCP_RNW;
pcp_write <= not Bus2PDI_PCP_RNW;
pcp_chipselect <= Bus2PDI_PCP_CS(0);
pcp_byteenable <= Bus2PDI_PCP_BE;
pcp_address <= Bus2PDI_PCP_Addr(14 downto 2);
PDI_PCP2Bus_Data <= pcp_readdata;
PDI_PCP2Bus_RdAck <= pcp_chipselect and pcp_read and not pcp_waitrequest;
PDI_PCP2Bus_WrAck <= pcp_chipselect and pcp_write and not pcp_waitrequest;
PDI_PCP2Bus_Error <= '0';
end generate genPcpPdiLink;
genPdiAp : if (C_GEN_AXI_BUS_IF) generate
begin
PDI_AP_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_PDI_AP_BASE,C_PDI_AP_HIGH),
C_ARD_NUM_CE_ARRAY => (0=>1),
C_DPHASE_TIMEOUT => C_S_AXI_PDI_AP_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_PDI_AP_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_PDI_AP_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_PDI_AP_MINSIZE,
C_USE_WSTRB => C_S_AXI_PDI_AP_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2PDI_AP_Addr( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2PDI_AP_BE( (C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2PDI_AP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2PDI_AP_Clk,
Bus2IP_Data => Bus2PDI_AP_Data( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2PDI_AP_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2PDI_AP_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => PDI_AP2Bus_Data( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => PDI_AP2Bus_Error,
IP2Bus_RdAck => PDI_AP2Bus_RdAck,
IP2Bus_WrAck => PDI_AP2Bus_WrAck,
S_AXI_ACLK => S_AXI_PDI_AP_ACLK,
S_AXI_ARADDR => S_AXI_PDI_AP_ARADDR( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_PDI_AP_ARESETN,
S_AXI_ARREADY => S_AXI_PDI_AP_ARREADY,
S_AXI_ARVALID => S_AXI_PDI_AP_ARVALID,
S_AXI_AWADDR => S_AXI_PDI_AP_AWADDR( C_S_AXI_PDI_AP_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_PDI_AP_AWREADY,
S_AXI_AWVALID => S_AXI_PDI_AP_AWVALID,
S_AXI_BREADY => S_AXI_PDI_AP_BREADY,
S_AXI_BRESP => S_AXI_PDI_AP_BRESP,
S_AXI_BVALID => S_AXI_PDI_AP_BVALID,
S_AXI_RDATA => S_AXI_PDI_AP_RDATA( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_PDI_AP_RREADY,
S_AXI_RRESP => S_AXI_PDI_AP_RRESP,
S_AXI_RVALID => S_AXI_PDI_AP_RVALID,
S_AXI_WDATA => S_AXI_PDI_AP_WDATA( C_S_AXI_PDI_AP_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_PDI_AP_WREADY,
S_AXI_WSTRB => S_AXI_PDI_AP_WSTRB( (C_S_AXI_PDI_AP_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_PDI_AP_WVALID
);
end generate genPdiAp;
genApPdiLink : if C_GEN_PDI generate
begin
--ap_pcp assignments
clkAp <= Bus2PDI_AP_Clk;
Bus2PDI_AP_Reset <= not Bus2PDI_AP_Resetn;
ap_writedata <= Bus2PDI_AP_Data;
-- Bus2MAC_PKT_Data(7 downto 0) & Bus2MAC_PKT_Data(15 downto 8) &
-- Bus2MAC_PKT_Data(23 downto 16) & Bus2MAC_PKT_Data(31 downto 24);
ap_read <= Bus2PDI_AP_RNW;
ap_write <= not Bus2PDI_AP_RNW;
ap_chipselect <= Bus2PDI_AP_CS(0);
ap_byteenable <= Bus2PDI_AP_BE;
ap_address <= Bus2PDI_AP_Addr(14 downto 2);
PDI_AP2Bus_Data <= ap_readdata;
PDI_AP2Bus_RdAck <= ap_chipselect and ap_read and not ap_waitrequest;
PDI_AP2Bus_WrAck <= ap_chipselect and ap_write and not ap_waitrequest;
PDI_AP2Bus_Error <= '0';
end generate genApPdiLink;
genSmpIo : if (C_GEN_SIMPLE_IO) generate
begin
SMP_IO_AXI_SINGLE_SLAVE : axi_lite_ipif
generic map (
C_ARD_ADDR_RANGE_ARRAY => (C_SMP_PCP_BASE,C_SMP_PCP_HIGH),
C_ARD_NUM_CE_ARRAY => (0=>1),
C_DPHASE_TIMEOUT => C_S_AXI_SMP_PCP_DPHASE_TIMEOUT,
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_SMP_PCP_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_SMP_PCP_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_SMP_PCP_MINSIZE,
C_USE_WSTRB => C_S_AXI_SMP_PCP_USE_WSTRB
)
port map(
Bus2IP_Addr => Bus2SMP_PCP_Addr( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ),
Bus2IP_BE => Bus2SMP_PCP_BE( (C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0 ),
Bus2IP_CS => Bus2SMP_PCP_CS( 0 downto 0 ),
Bus2IP_Clk => Bus2SMP_PCP_Clk,
Bus2IP_Data => Bus2SMP_PCP_Data( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ),
Bus2IP_RNW => Bus2SMP_PCP_RNW,
Bus2IP_RdCE => open,
Bus2IP_Resetn => Bus2SMP_PCP_Resetn,
Bus2IP_WrCE => open,
IP2Bus_Data => SMP_PCP2Bus_Data( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ),
IP2Bus_Error => SMP_PCP2Bus_Error,
IP2Bus_RdAck => SMP_PCP2Bus_RdAck,
IP2Bus_WrAck => SMP_PCP2Bus_WrAck,
S_AXI_ACLK => S_AXI_SMP_PCP_ACLK,
S_AXI_ARADDR => S_AXI_SMP_PCP_ARADDR( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ),
S_AXI_ARESETN => S_AXI_SMP_PCP_ARESETN,
S_AXI_ARREADY => S_AXI_SMP_PCP_ARREADY,
S_AXI_ARVALID => S_AXI_SMP_PCP_ARVALID,
S_AXI_AWADDR => S_AXI_SMP_PCP_AWADDR( C_S_AXI_SMP_PCP_ADDR_WIDTH-1 downto 0 ),
S_AXI_AWREADY => S_AXI_SMP_PCP_AWREADY,
S_AXI_AWVALID => S_AXI_SMP_PCP_AWVALID,
S_AXI_BREADY => S_AXI_SMP_PCP_BREADY,
S_AXI_BRESP => S_AXI_SMP_PCP_BRESP,
S_AXI_BVALID => S_AXI_SMP_PCP_BVALID,
S_AXI_RDATA => S_AXI_SMP_PCP_RDATA( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ),
S_AXI_RREADY => S_AXI_SMP_PCP_RREADY,
S_AXI_RRESP => S_AXI_SMP_PCP_RRESP,
S_AXI_RVALID => S_AXI_SMP_PCP_RVALID,
S_AXI_WDATA => S_AXI_SMP_PCP_WDATA( C_S_AXI_SMP_PCP_DATA_WIDTH-1 downto 0 ),
S_AXI_WREADY => S_AXI_SMP_PCP_WREADY,
S_AXI_WSTRB => S_AXI_SMP_PCP_WSTRB( (C_S_AXI_SMP_PCP_DATA_WIDTH/8)-1 downto 0 ),
S_AXI_WVALID => S_AXI_SMP_PCP_WVALID
);
end generate genSmpIo;
genSimpleIoSignals : if C_GEN_SIMPLE_IO generate
begin
--SMP_PCP assignments
clkPcp <= Bus2SMP_PCP_Clk;
Bus2SMP_PCP_Reset <= not Bus2SMP_PCP_Resetn;
smp_writedata <= Bus2SMP_PCP_Data;
smp_read <= Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_write <= not Bus2SMP_PCP_RNW and Bus2SMP_PCP_CS(0);
smp_chipselect <= Bus2SMP_PCP_CS(0);
smp_byteenable <= Bus2SMP_PCP_BE;
smp_address <= Bus2SMP_PCP_Addr(2);
SMP_PCP2Bus_Data <= smp_readdata;
SMP_PCP2Bus_RdAck <= smp_chipselect and smp_read and not smp_waitrequest;
SMP_PCP2Bus_WrAck <= smp_chipselect and smp_write and not smp_waitrequest;
SMP_PCP2Bus_Error <= '0';
end generate genSimpleIoSignals;
oddr2_0 : if not C_INSTANCE_ODDR2 generate
begin
phy0_clk <= clk50;
phy1_clk <= clk50;
end generate oddr2_0;
oddr2_1 : if C_INSTANCE_ODDR2 generate
begin
U10 : ODDR2
port map(
C0 => clk50,
C1 => NET38418,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy0_clk,
R => GND,
S => GND
);
U11 : ODDR2
port map(
C0 => clk50,
C1 => NET38470,
CE => VCC,
D0 => VCC,
D1 => GND,
Q => phy1_clk,
R => GND,
S => GND
);
NET38470 <= not(clk50);
NET38418 <= not(clk50);
end generate oddr2_1;
end struct;
| gpl-2.0 | 926f65c12980ecc27a8daad5946104bf | 0.618511 | 2.880482 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op332_17sk1_0.vhdl | 1 | 7,860 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.95e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 7.5e-07,
W => Wdiff_0,
Wdiff_0init => 1.95e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.35e-06,
W => W_0,
W_0init => 3.2e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.35e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 7.73e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net2,
G => vbias2,
S => net6
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcm_2,
Wcm_2init => 4e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcmout_2,
Wcmout_2init => 3.52e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net7,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.35e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 7.73e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias2,
S => net7
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.35e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 7.73e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcm_2,
Wcm_2init => 4e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 3.5e-07,
W => Wcmout_2,
Wcmout_2init => 3.52e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net9,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.35e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 7.73e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias2,
S => net9
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.35e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 7.53e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias3,
S => net10
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.65e-06,
W => Wcm_1,
Wcm_1init => 1.52e-05,
scope => private
)
port map(
D => net10,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 1.65e-06,
W => Wcmout_1,
Wcmout_1init => 6.965e-05,
scope => private
)
port map(
D => net11,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.35e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 7.53e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net11
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.35e-06,
W => (pfak)*(WBias),
WBiasinit => 6.2e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.35e-06,
W => (pfak)*(WBias),
WBiasinit => 6.2e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.35e-06,
W => WBias,
WBiasinit => 6.2e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.35e-06,
W => WBias,
WBiasinit => 6.2e-06
)
port map(
D => vbias2,
G => vbias3,
S => net12
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.35e-06,
W => WBias,
WBiasinit => 6.2e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.35e-06,
W => WBias,
WBiasinit => 6.2e-06
)
port map(
D => net12,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net13,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net13,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net13,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 0d6f499319e332bcca5e028f1d10716b | 0.582697 | 2.888644 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/zpu_8bit.vhd | 5 | 28,407 | ------------------------------------------------------------------------------
---- ----
---- ZPU 8-bit version ----
---- ----
---- http://www.opencores.org/ ----
---- ----
---- Description: ----
---- ZPU is a 32 bits small stack cpu. This is a modified version of ----
---- the zpu_small implementation. This one has only one 8-bit external ----
---- memory port, which is used for I/O, instruction fetch and data ----
---- accesses. It is intended to interface with existing 8-bit systems, ----
---- while maintaining the large addressing range and 32-bit programming ----
---- model. The 32-bit stack remains "internal" in the ZPU. ----
---- ----
---- This version is about the same size as zpu_small from zealot, ----
---- but performs 25% better at the same clock speed, given that the ----
---- external memory bus can operate with 0 wait states. The performance ----
---- increase is due to the fact that most instructions only require 3 ----
---- clock cycles instead of 4. ----
---- ----
---- Author: ----
---- - Øyvind Harboe, oyvind.harboe zylin.com [zpu concept] ----
---- - Salvador E. Tropea, salvador inti.gob.ar [zealot] ----
---- - Gideon Zweijtzer, gideon.zweijtzer technolution.eu [this] ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com> ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2009 Gideon N. Zweijtzer <Technolution.NL> ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zpu_8bit(Behave) (Entity and architecture) ----
---- File name: zpu_8bit.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: work ----
---- Dependencies: ieee.std_logic_1164 ----
---- ieee.numeric_std ----
---- work.zpupkg ----
---- Target FPGA: Spartan 3E (XC3S500E-4-PQG208) ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Xilinx Release 10.1.03i - xst K.39 ----
---- Simulation tools: Modelsim ----
---- Text editor: UltraEdit 11.00a+ ----
---- ----
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.zpupkg.all;
entity zpu_8bit is
generic(
g_addr_size : integer := 16; -- Total address space width (incl. I/O)
g_stack_size : integer := 12; -- Memory (stack+data) width
g_prog_size : integer := 14; -- Program size
g_dont_care : std_logic := '-'); -- Value used to fill the unsused bits, can be '-' or '0'
port(
clk_i : in std_logic; -- System Clock
reset_i : in std_logic; -- Synchronous Reset
interrupt_i : in std_logic; -- Interrupt
break_o : out std_logic; -- Breakpoint opcode executed
-- synthesis translate_off
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- synthesis translate_on
-- BRAM (stack ONLY)
a_en_o : out std_logic;
a_we_o : out std_logic; -- BRAM A port Write Enable
a_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM A Address
a_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM A port
a_i : in unsigned(31 downto 0); -- Data from BRAM A port
b_en_o : out std_logic;
b_we_o : out std_logic; -- BRAM B port Write Enable
b_addr_o : out unsigned(g_stack_size-1 downto 2):=(others => '0'); -- BRAM B Address
b_o : out unsigned(31 downto 0):=(others => '0'); -- Data to BRAM B port
b_i : in unsigned(31 downto 0); -- Data from BRAM B port
-- memory port for text, bss, data
c_req_o : out std_logic; -- request output
c_inst_o : out std_logic; -- indicates request is for opcode (program data)
c_we_o : out std_logic; -- write
c_addr_o : out unsigned(g_addr_size-1 downto 0) := (others => '0');
c_rack_i : in std_logic; -- request acknowledge
c_dack_i : in std_logic; -- data acknowledge (read only)
c_data_i : in unsigned(c_opcode_width-1 downto 0);
c_data_o : out unsigned(c_opcode_width-1 downto 0) );
end entity zpu_8bit;
architecture Behave of zpu_8bit is
constant c_max_addr_bit : integer:=g_addr_size-1;
-- Stack Pointer initial value: BRAM size-8
constant c_sp_start_1 : unsigned(g_addr_size-1 downto 0):=to_unsigned((2**g_stack_size)-8, g_addr_size);
constant c_sp_start : unsigned(g_stack_size-1 downto 2):=
c_sp_start_1(g_stack_size-1 downto 2);
-- Program counter
signal pc_r : unsigned(g_prog_size-1 downto 0):=(others => '0');
-- Stack pointer
signal sp_r : unsigned(g_stack_size-1 downto 2):=c_sp_start;
signal idim_r : std_logic:='0';
-- BRAM (stack)
-- a_r is a register for the top of the stack [SP]
-- Note: as this is a stack CPU this is a very important register.
signal a_we_r : std_logic:='0';
signal a_en_r : std_logic:='0';
signal a_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal a_r : unsigned(31 downto 0):=(others => '0');
-- b_r is a register for the next value in the stack [SP+1]
signal b_we_r : std_logic:='0';
signal b_en_r : std_logic:='0';
signal b_addr_r : unsigned(g_stack_size-1 downto 2):=(others => '0');
signal b_r : unsigned(31 downto 0):=(others => '0');
signal c_we_r : std_logic := '0';
signal c_req_r : std_logic := '0';
signal c_mux_r : std_logic := '0';
signal c_mux_d : std_logic := '0';
signal byte_req_cnt : unsigned(1 downto 0) := "00";
signal byte_ack_cnt : unsigned(1 downto 0) := "00";
signal posted_wr_a : std_logic := '0';
-- State machine.
type state_t is (st_fetch, st_execute, st_add, st_or,
st_and, st_store, st_read_mem, st_write_mem,
st_add_sp, st_decode, st_resync);
signal state : state_t:=st_fetch;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "one-hot";
-- Decoded Opcode
type decode_t is (dec_nop, dec_im, dec_load_sp, dec_store_sp, dec_add_sp,
dec_emulate, dec_break, dec_push_sp, dec_pop_pc, dec_add,
dec_or, dec_and, dec_load, dec_not, dec_flip, dec_store,
dec_pop_sp, dec_interrupt, dec_storeb, dec_loadb);
signal d_opcode_r : decode_t;
signal d_opcode : decode_t;
signal opcode : unsigned(c_opcode_width-1 downto 0); -- Decoded
signal opcode_r : unsigned(c_opcode_width-1 downto 0); -- Registered
-- IRQ flag
signal in_irq_r : std_logic:='0';
-- I/O space address
signal addr_r : unsigned(g_addr_size-1 downto 0):=(others => '0');
begin
a_en_o <= a_en_r;
b_en_o <= b_en_r;
c_req_o <= '1' when state = st_fetch else c_req_r;
-- Dual ported memory interface
a_we_o <= a_we_r;
a_addr_o <= a_addr_r(g_stack_size-1 downto 2);
a_o <= a_r;
b_we_o <= b_we_r;
b_addr_o <= b_addr_r(g_stack_size-1 downto 2);
b_o <= b_r;
opcode <= c_data_i;
c_addr_o <= resize(pc_r, g_addr_size) when c_mux_r = '0'
else addr_r;
c_we_o <= c_we_r;
-------------------------
-- Instruction Decoder --
-------------------------
-- Note: We use a separate memory port to fetch opcodes.
decode_control:
process(opcode)
begin
-- synthesis translate_off
if opcode(0)='Z' then
d_opcode <= dec_nop;
else
-- synthesis translate_on
if (opcode(7 downto 7)=OPCODE_IM) then
d_opcode <= dec_im;
elsif (opcode(7 downto 5)=OPCODE_STORESP) then
d_opcode <= dec_store_sp;
elsif (opcode(7 downto 5)=OPCODE_LOADSP) then
d_opcode <= dec_load_sp;
elsif (opcode(7 downto 5)=OPCODE_EMULATE) then
-- if opcode(5 downto 0) = OPCODE_LOADB then
-- d_opcode <= dec_loadb;
-- elsif opcode(5 downto 0) = OPCODE_STOREB then
-- d_opcode <= dec_storeb;
-- else
d_opcode <= dec_emulate;
-- end if;
elsif (opcode(7 downto 4)=OPCODE_ADDSP) then
d_opcode <= dec_add_sp;
else -- OPCODE_SHORT
case opcode(3 downto 0) is
when OPCODE_BREAK =>
d_opcode <= dec_break;
when OPCODE_PUSHSP =>
d_opcode <= dec_push_sp;
when OPCODE_POPPC =>
d_opcode <= dec_pop_pc;
when OPCODE_ADD =>
d_opcode <= dec_add;
when OPCODE_OR =>
d_opcode <= dec_or;
when OPCODE_AND =>
d_opcode <= dec_and;
when OPCODE_LOAD =>
d_opcode <= dec_load;
when OPCODE_NOT =>
d_opcode <= dec_not;
when OPCODE_FLIP =>
d_opcode <= dec_flip;
when OPCODE_STORE =>
d_opcode <= dec_store;
when OPCODE_POPSP =>
d_opcode <= dec_pop_sp;
when others => -- OPCODE_NOP and others
d_opcode <= dec_nop;
end case;
end if;
-- synthesis translate_off
end if;
-- synthesis translate_on
end process decode_control;
opcode_control:
process (clk_i)
variable sp_offset : unsigned(4 downto 0);
begin
if rising_edge(clk_i) then
break_o <= '0';
-- synthesis translate_off
dbg_o.b_inst <= '0';
-- synthesis translate_on
posted_wr_a <= '0';
c_we_r <= '0';
c_mux_d <= c_mux_r;
d_opcode_r <= d_opcode;
opcode_r <= opcode;
a_we_r <= '0';
b_we_r <= '0';
a_en_r <= '0';
b_en_r <= '0';
a_r <= (others => g_dont_care); -- output register
b_r <= (others => g_dont_care);
a_addr_r <= (others => g_dont_care);
b_addr_r <= (others => g_dont_care);
addr_r(g_addr_size-1 downto 2) <= a_i(g_addr_size-1 downto 2);
if interrupt_i='0' then
in_irq_r <= '0'; -- no longer in an interrupt
end if;
case state is
when st_fetch =>
-- During this cycle
-- we'll fetch the opcode @ pc and thus it will
-- be available for st_execute in the next cycle
-- At this point a_i contains the value that is from the top of the stack
-- or that was fetched from the stack with an offset (loadsp)
a_r <= a_i;
if c_rack_i='1' then -- our request for instr has been seen
-- by default, we need the two values of the stack, so we'll fetch them as well
a_we_r <= posted_wr_a;
a_addr_r <= sp_r;
a_en_r <= '1';
b_addr_r <= sp_r+1;
b_en_r <= '1';
state <= st_decode;
else
posted_wr_a <= posted_wr_a; -- hold
end if;
when st_decode =>
if c_dack_i='1' then
if interrupt_i='1' and in_irq_r='0' and idim_r='0' then
-- We got an interrupt, execute interrupt instead of next instruction
in_irq_r <= '1';
d_opcode_r <= dec_interrupt; -- override
end if;
state <= st_execute;
end if;
when st_execute =>
state <= st_fetch;
-- At this point:
-- a_i contains top of stack, b_i contains next-to-top of stack
pc_r <= pc_r+1; -- increment by default
-- synthesis translate_off
-- Debug info (Trace)
dbg_o.b_inst <= '1';
dbg_o.pc <= (others => '0');
dbg_o.pc(g_prog_size-1 downto 0) <= pc_r;
dbg_o.opcode <= opcode_r;
dbg_o.sp <= (others => '0');
dbg_o.sp(g_stack_size-1 downto 2) <= sp_r;
dbg_o.stk_a <= a_i;
dbg_o.stk_b <= b_i;
-- synthesis translate_on
-- During the next cycle we'll be reading the next opcode
sp_offset(4):=not opcode_r(4);
sp_offset(3 downto 0):=opcode_r(3 downto 0);
idim_r <= '0';
--------------------
-- Execution Unit --
--------------------
case d_opcode_r is
when dec_interrupt =>
-- Not a real instruction, but an interrupt
-- Push(PC); PC=32
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_r <= (others => g_dont_care);
a_r(pc_r'range) <= pc_r;
-- Jump to ISR
pc_r <= to_unsigned(32, pc_r'length); -- interrupt address
--report "ZPU jumped to interrupt!" severity note;
when dec_im =>
idim_r <= '1';
a_we_r <= '1';
a_en_r <= '1';
if idim_r='0' then
-- First IM
-- Push the 7 bits (extending the sign)
sp_r <= sp_r-1;
a_addr_r <= sp_r-1;
a_r <= unsigned(resize(signed(opcode_r(6 downto 0)),32));
else
-- Next IMs, shift the word and put the new value in the lower
-- bits
a_addr_r <= sp_r;
a_r(31 downto 7) <= a_i(24 downto 0);
a_r(6 downto 0) <= opcode_r(6 downto 0);
end if;
when dec_store_sp =>
-- [SP+Offset]=Pop()
b_we_r <= '1';
b_en_r <= '1';
b_addr_r <= sp_r+sp_offset;
b_r <= a_i;
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_load_sp =>
-- Push([SP+Offset])
sp_r <= sp_r-1;
a_addr_r <= sp_r+sp_offset;
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync; -- extra delay to fetch from A
when dec_emulate =>
-- Push(PC+1), PC=Opcode[4:0]*32
sp_r <= sp_r-1;
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= sp_r-1;
a_r <= (others => '0'); -- could be changed to don't care
a_r(pc_r'range) <= pc_r+1;
-- Jump to NUM*32
-- The emulate address is:
-- 98 7654 3210
-- 0000 00aa aaa0 0000
pc_r <= (others => '0');
pc_r(9 downto 5) <= opcode_r(4 downto 0);
when dec_add_sp =>
-- Push(Pop()+[SP+Offset])
b_addr_r <= sp_r+sp_offset;
b_en_r <= '1';
state <= st_add_sp;
when dec_break =>
--report "Break instruction encountered" severity failure;
break_o <= '1';
when dec_push_sp =>
-- Push(SP)
sp_r <= sp_r-1;
a_we_r <= '1';
a_addr_r <= sp_r-1;
a_en_r <= '1';
a_r <= (others => '0');
a_r(sp_r'range) <= sp_r;
a_r(31) <= '1'; -- Mark this address as a stack address
when dec_pop_pc =>
-- Pop(PC)
pc_r <= a_i(pc_r'range);
sp_r <= sp_r+1;
state <= st_fetch; -- was resync
when dec_add =>
-- Push(Pop()+Pop())
sp_r <= sp_r+1;
state <= st_add;
when dec_or =>
-- Push(Pop() or Pop())
sp_r <= sp_r+1;
state <= st_or;
when dec_and =>
-- Push(Pop() and Pop())
sp_r <= sp_r+1;
state <= st_and;
when dec_not =>
-- Push(not(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= not a_i;
when dec_flip =>
-- Push(flip(Pop()))
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
for i in 0 to 31 loop
a_r(i) <= a_i(31-i);
end loop;
-- when dec_loadb =>
-- addr_r <= a_i(g_addr_size-1 downto 0);
--
-- assert a_i(31)='0'
-- report "LoadB only works from external memory!"
-- severity error;
--
-- c_req_r <= '1';
-- c_mux_r <= '1';
-- byte_req_cnt <= "00"; -- 1 byte
-- byte_cnt_d <= "11";
-- state <= st_read_mem;
when dec_load =>
-- Push([Pop()])
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31)='1' then -- stack
a_addr_r <= a_i(a_addr_r'range);
a_en_r <= '1';
posted_wr_a <= '1';
state <= st_resync;
else
c_req_r <= '1'; -- output memory request
c_mux_r <= '1'; -- output correct address
state <= st_read_mem;
a_r <= (others => '0'); -- necessary for one byte reads!
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
byte_ack_cnt <= "00";
else
byte_req_cnt <= "11"; -- 4 bytes
byte_ack_cnt <= "11";
end if;
end if;
when dec_store =>
-- a=Pop(), b=Pop(), [a]=b
sp_r <= sp_r+1;
addr_r(1 downto 0) <= a_i(1 downto 0);
if a_i(31) = '1' then
state <= st_store;
else
state <= st_write_mem;
if a_i(c_max_addr_bit)='1' then
byte_req_cnt <= "00"; -- 1 byte
else
byte_req_cnt <= "11"; -- 4 bytes
end if;
end if;
when dec_pop_sp =>
-- SP=Pop()
sp_r <= a_i(g_stack_size-1 downto 2);
state <= st_fetch; -- was resync
when others => -- includes 'nop'
null;
end case;
when st_store =>
sp_r <= sp_r+1; -- for a store we need to pop 2!
a_we_r <= '1';
a_en_r <= '1';
a_addr_r <= a_i(g_stack_size-1 downto 2);
a_r <= b_i;
state <= st_fetch; -- was resync
when st_read_mem =>
-- BIG ENDIAN
a_r <= a_r; -- stay put, as we are filling it byte by byte!
if c_dack_i = '1' then
byte_ack_cnt <= byte_ack_cnt - 1;
case byte_ack_cnt is
when "00" =>
a_r(7 downto 0) <= c_data_i;
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
state <= st_fetch;
when "01" =>
a_r(15 downto 8) <= c_data_i;
when "10" =>
a_r(23 downto 16) <= c_data_i;
when others => -- 11
a_r(31 downto 24) <= c_data_i;
end case;
end if;
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
c_req_r <= '0';
c_mux_r <= '0';
end if;
end if;
when st_write_mem =>
c_req_r <= '1';
c_mux_r <= '1';
c_we_r <= '1';
-- Note: Output data is muxed outside of this process
if c_rack_i='1' then
addr_r(1 downto 0) <= addr_r(1 downto 0) + 1;
byte_req_cnt <= byte_req_cnt - 1;
if byte_req_cnt = "00" then
sp_r <= sp_r+1; -- add another to sp.
c_mux_r <= '0';
c_req_r <= '0';
c_we_r <= '0';
state <= st_fetch; -- was resync
end if;
end if;
when st_add_sp =>
state <= st_add;
when st_add =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i+b_i;
state <= st_fetch;
when st_or =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i or b_i;
state <= st_fetch;
when st_and =>
a_addr_r <= sp_r;
a_we_r <= '1';
a_en_r <= '1';
a_r <= a_i and b_i;
state <= st_fetch;
when st_resync =>
a_addr_r <= sp_r;
state <= st_fetch;
posted_wr_a <= posted_wr_a; -- keep
when others =>
null;
end case;
if reset_i='1' then
state <= st_fetch;
sp_r <= c_sp_start;
pc_r <= (others => '0');
idim_r <= '0';
in_irq_r <= '0';
c_mux_r <= '0';
end if;
end if; -- rising_edge(clk_i)
end process opcode_control;
p_outmux: process(byte_req_cnt, b_i)
begin
case byte_req_cnt is
when "00" =>
c_data_o <= b_i(7 downto 0);
when "01" =>
c_data_o <= b_i(15 downto 8);
when "10" =>
c_data_o <= b_i(23 downto 16);
when others => -- 11
c_data_o <= b_i(31 downto 24);
end case;
end process;
end architecture Behave; -- Entity: zpu_8bit
| gpl-3.0 | 254c4d8ea4453cf52c1c51aab69dee65 | 0.345091 | 4.387181 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/nano_cpu/vhdl_source/nano.vhd | 3 | 6,323 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.nano_cpu_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity nano is
port (
clock : in std_logic;
reset : in std_logic;
-- i/o interface
io_addr : out unsigned(7 downto 0);
io_write : out std_logic;
io_read : out std_logic;
io_wdata : out std_logic_vector(15 downto 0);
io_rdata : in std_logic_vector(15 downto 0);
stall : in std_logic;
-- system interface (to write code into the nano)
sys_clock : in std_logic := '0';
sys_reset : in std_logic := '0';
sys_io_req : in t_io_req := c_io_req_init;
sys_io_resp : out t_io_resp );
end entity;
architecture structural of nano is
signal sys_enable : std_logic;
-- instruction/data ram
signal ram_addr : std_logic_vector(9 downto 0);
signal ram_en : std_logic;
signal ram_we : std_logic;
signal ram_wdata : std_logic_vector(15 downto 0);
signal ram_rdata : std_logic_vector(15 downto 0);
signal sys_io_req_bram : t_io_req;
signal sys_io_resp_bram : t_io_resp;
signal sys_io_req_regs : t_io_req;
signal sys_io_resp_regs : t_io_resp;
signal sys_core_reset : std_logic;
signal usb_reset_tig : std_logic;
signal usb_core_reset : std_logic;
signal bram_reset : std_logic;
signal bram_data : std_logic_vector(7 downto 0);
begin
i_split: entity work.io_bus_splitter
generic map (
g_range_lo => 12,
g_range_hi => 12,
g_ports => 2 )
port map (
clock => sys_clock,
req => sys_io_req,
resp => sys_io_resp,
reqs(0) => sys_io_req_bram, -- 4080000
reqs(1) => sys_io_req_regs, -- 4081000
resps(0) => sys_io_resp_bram,
resps(1) => sys_io_resp_regs );
i_core: entity work.nano_cpu
port map (
clock => clock,
reset => usb_core_reset,
-- instruction/data ram
ram_addr => ram_addr,
ram_en => ram_en,
ram_we => ram_we,
ram_wdata => ram_wdata,
ram_rdata => ram_rdata,
-- i/o interface
io_addr => io_addr,
io_write => io_write,
io_read => io_read,
io_wdata => io_wdata,
io_rdata => io_rdata,
stall => stall );
i_buf_ram: RAMB16_S9_S18
generic map (
INIT_00 => X"096CE011A0CA095CC00F29596893E8210968C00F295C6893E93FA0CA0963E947",
INIT_01 => X"E9340964E05CE9340894E9340965E8DAC01E295A6832E821089AA0C40974A0CA",
INIT_02 => X"D0356824B800A027D82A6827B800C822809559580895A02FD822682F8095E020",
INIT_03 => X"E02AA011A0000959B8000957E033A020D83A6820A024B8000958E850D82E682F",
INIT_04 => X"C856295D808E4958088EE05051590894A02FD856682FE02AA010A001088FA000",
INIT_05 => X"0BF2C0840BF0E845B800E9340966A02DD85B682DE82AA010A000095BA0016860",
INIT_06 => X"0BF4E082C079516BC074516AC06F51690BF0808F0BF183F50957A0700BF3A071",
INIT_07 => X"D87E687483F5A0726833811FE8C4E082E934E8A0E8850BF4E082E934E89CE885",
INIT_08 => X"00000000B800A050B800D8896874A040A073C08C8090E05C83F00957E934091F",
INIT_09 => X"E0A6095AE8400962004B15E00050004000450046000000000000000000000008",
INIT_0A => X"C0BE6822C8BEE82EE82AA012A00259580890A000E0A6195A295E0891E8400958",
INIT_0B => X"49580892B8000958C8BE5163B8000959C8BA5160B800095AC8B651596830A022",
INIT_0C => X"C8D85161E0D20957E83CC8CE515A0830C8D9E82EE840095FE0B8C0BC515A8092",
INIT_0D => X"8094095AC0E1515E296F6832E0BEE0B6B8000959B800095AC8D65093095EE83C",
INIT_0E => X"0894A02EA01E80950976A0C4097280940958E0E980940957C0E729596832B800",
INIT_0F => X"B800A0C48900810049670894C8F1809559580895A02FD8F1682FD101682EC117",
INIT_10 => X"A055C114809559580895C90959580975A0458095089BA018A045809409590000",
INIT_11 => X"0000E0FAC917809559580895A02FD917682F8095095AA019E107C91159580975",
INIT_12 => X"0BFDB800894683FE297149580BFE8146496D0BFEB800C926E920B8003BFE0BFF",
INIT_13 => X"0957B80083FD297749580BFD91460945814649700BFD8145B8003BFC29774958",
INIT_14 => X"0969A07183F30973A07083F2096E83F4096200000000B80083FF83FE83FD83FC",
INIT_15 => X"000900080007000600050003000200010000B800A0720963809B809A095B83F0",
INIT_16 => X"0038123403B000260023002200210FA00096001300120011000E000D000B000A",
INIT_17 => X"00000000000000000000000000000000007F007802EE006156780050003F0330",
INIT_3F => X"FF00000000000000000000000000000000000000000000000000000000000000"
)
port map (
CLKB => clock,
SSRB => reset,
ENB => ram_en,
WEB => ram_we,
ADDRB => ram_addr,
DIB => ram_wdata,
DIPB => "00",
DOB => ram_rdata,
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_enable,
WEA => sys_io_req_bram.write,
ADDRA => std_logic_vector(sys_io_req_bram.address(10 downto 0)),
DIA => sys_io_req_bram.data,
DIPA => "0",
DOA => bram_data );
sys_enable <= sys_io_req_bram.write or sys_io_req_bram.read;
bram_reset <= not sys_enable;
sys_io_resp_bram.data <= bram_data when sys_io_resp_bram.ack = '1' else X"00";
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_io_resp_bram.ack <= sys_enable;
sys_io_resp_regs <= c_io_resp_init;
sys_io_resp_regs.ack <= sys_io_req_regs.write or sys_io_req_regs.read;
if sys_io_req_regs.write = '1' then -- any address
sys_core_reset <= not sys_io_req_regs.data(0);
end if;
if sys_reset = '1' then
sys_core_reset <= '1';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
usb_reset_tig <= sys_core_reset;
usb_core_reset <= usb_reset_tig;
end if;
end process;
end architecture;
| gpl-3.0 | 2ba5750498245ae0a9f2e5ff85bfd830 | 0.609204 | 2.932746 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/openMAC.vhd | 3 | 51,934 | ------------------------------------------------------------------------------------------------------------------------
-- OpenMAC
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: Used DPR is specific to Altera/Xilinx. Use one of the following files:
-- OpenMAC_DPR_Altera.vhd
-- OpenMAC_DPR_Xilinx.vhd
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- V0.00-0.30 First generation.
-- 2009-08-07 V0.31 Converted to official version.
-- 2010-04-12 V0.40 zelenkaj Added Auto-Response Delay functionality (TxDel)
-- 2010-06-28 V0.41 zelenkaj Bug Fix: exit sDel if Tx_Off, set Tx_Del_Run without Ipg consideration
-- 2010-08-02 V0.42 zelenkaj Added Timer triggered TX functionality (TxSyncOn)
-- 2011-01-25 V0.43 zelenkaj Changed IPG preload value from 900ns to 960ns
-- 2011-11-28 V0.44 zelenkaj Changed reset level to high-active
-- Clean up
-- Added Dma qualifiers (Rd/Wr done)
-- 2011-12-02 V0.45 zelenkaj Added Dma Request Overflow
-- 2011-12-05 V0.46 zelenkaj Minor change of constants (logic level)
-- 2011-12-23 V0.47 zelenkaj Improvement of Dma Request Overflow determination
-- 2012-02-23 V0.48 zelenkaj Bug Fix: Dma Req Overflow generation faulty in case of hot plugging
-- 2012-03-20 V0.50 zelenkaj Converted openMAC to little endian
-- 2012-04-12 V0.51 zelenkaj Bug Fix: Dma Req Overflow generation faulty for read
-- 2012-04-17 V0.52 zelenkaj Added forwarding of DMA read length for efficient DMA reads
-- Added collision handling for Tx_Sync to avoid 80 sec waits
-- 2012-05-03 V0.53 zelenkaj Bug Fix: Dma_Wr_Done pulse is generated after last Dma_Req
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY OpenMAC IS
GENERIC( HighAdr : IN integer := 16;
Timer : IN boolean := false;
TxSyncOn : IN boolean := false;
TxDel : IN boolean := false;
Simulate : IN boolean := false
);
PORT ( Rst, Clk : IN std_logic;
-- Processor
s_nWr, Sel_Ram, Sel_Cont : IN std_logic := '0';
S_nBe : IN std_logic_vector( 1 DOWNTO 0);
S_Adr : IN std_logic_vector(10 DOWNTO 1);
S_Din : IN std_logic_vector(15 DOWNTO 0);
S_Dout : OUT std_logic_vector(15 DOWNTO 0);
nTx_Int, nRx_Int : OUT std_logic;
nTx_BegInt : OUT std_logic;
-- DMA
Dma_Rd_Done : OUT std_logic;
Dma_Wr_Done : OUT std_logic;
Dma_Req, Dma_Rw : OUT std_logic;
Dma_Ack : IN std_logic;
Dma_Req_Overflow : OUT std_logic;
Dma_Rd_Len : OUT std_logic_vector(11 downto 0);
Dma_Addr : OUT std_logic_vector(HighAdr DOWNTO 1);
Dma_Dout : OUT std_logic_vector(15 DOWNTO 0);
Dma_Din : IN std_logic_vector(15 DOWNTO 0);
-- RMII
rRx_Dat : IN std_logic_vector( 1 DOWNTO 0);
rCrs_Dv : IN std_logic;
rTx_Dat : OUT std_logic_vector( 1 DOWNTO 0);
rTx_En : OUT std_logic;
Hub_Rx : IN std_logic_vector( 1 DOWNTO 0) := "00";
Mac_Zeit : OUT std_logic_vector(31 DOWNTO 0)
);
END ENTITY OpenMAC;
ARCHITECTURE struct OF OpenMAC IS
CONSTANT cInactivated : std_logic := '0';
CONSTANT cActivated : std_logic := '1';
SIGNAL Rx_Dv : std_logic;
SIGNAL R_Req : std_logic;
SIGNAL Auto_Desc : std_logic_vector( 3 DOWNTO 0);
SIGNAL Zeit : std_logic_vector(31 DOWNTO 0);
SIGNAL Tx_Dma_Req, Rx_Dma_Req : std_logic;
SIGNAL Tx_Dma_Ack, Rx_Dma_Ack : std_logic;
SIGNAL Tx_Ram_Dat, Rx_Ram_Dat : std_logic_vector(15 DOWNTO 0);
SIGNAL Tx_Dma_Len : std_logic_vector(11 DOWNTO 0);
SIGNAL Tx_Reg, Rx_Reg : std_logic_vector(15 DOWNTO 0);
SIGNAL Dma_Tx_Addr, Dma_Rx_Addr : std_logic_vector(Dma_Addr'RANGE);
SIGNAL Dma_Req_s, Dma_Rw_s : std_logic;
SIGNAL halfDuplex : std_logic; -- cActivated ... MAC in half-duplex mode
SIGNAL Tx_Active : std_logic; -- cActivated ... TX = Data or CRC
SIGNAL Tx_Dma_Very1stOverflow : std_logic; -- cActivated ... very first TX DMA overflow
SIGNAL Tx_Col : std_logic;
SIGNAL Sel_Tx_Ram, Sel_Tx_Reg : std_logic;
SIGNAL Tx_LatchH, Tx_LatchL : std_logic_vector( 7 DOWNTO 0);
BEGIN
S_Dout <= Tx_Ram_Dat WHEN Sel_Ram = '1' AND Sel_Tx_Ram = '1' ELSE
Rx_Ram_Dat WHEN Sel_Ram = '1' ELSE
Tx_Reg WHEN Sel_Cont = '1' AND Sel_Tx_Reg = '1' ELSE
Rx_Reg;
Mac_Zeit <= Zeit;
Dma_Rd_Len <= Tx_Dma_Len + 4;
b_DmaObserver : block
signal dmaObserverCounter, dmaObserverCounterNext : std_logic_vector(2 downto 0);
constant cDmaObserverCounterHalf : std_logic_vector(dmaObserverCounter'range) := "110"; --every 8th cycle
constant cDmaObserverCounterFull : std_logic_vector(dmaObserverCounter'range) := "010"; --every 4th cycle
begin
process(Clk, Rst)
begin
if Rst = '1' then
dmaObserverCounter <= (others => cInactivated);
elsif rising_edge(Clk) then
dmaObserverCounter <= dmaObserverCounterNext;
end if;
end process;
Dma_Req_Overflow <= --very first TX Dma transfer
Dma_Req_s when Tx_Dma_Very1stOverflow = cActivated and Tx_Active = cInactivated else
--RX Dma transfers and TX Dma transfers without the very first
Dma_Req_s when dmaObserverCounterNext = cDmaObserverCounterHalf and halfDuplex = cActivated else
Dma_Req_s when dmaObserverCounterNext = cDmaObserverCounterFull and halfDuplex = cInactivated else
cInactivated;
dmaObserverCounterNext <= --increment counter if DMA Read req (TX) during data and crc
dmaObserverCounter + 1 when Dma_Req_s = cActivated and Dma_Rw_s = cActivated
and Tx_Active = cActivated else
--increment counter if DMA Write req (RX)
dmaObserverCounter + 1 when Dma_Req_s = cActivated and Dma_Rw_s = cInactivated else
(others => cInactivated); --reset DmaObserverCounter if no Dma_Req
end block;
b_Dma: BLOCK
SIGNAL Rx_Dma, Tx_Dma : std_logic;
BEGIN
Dma_Req <= Dma_Req_s;
Dma_Req_s <= '1' WHEN (Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0') OR Rx_Dma_Req = '1' ELSE '0';
Dma_Rw <= Dma_Rw_s;
Dma_Rw_s <= '1' WHEN (Rx_Dma = '0' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0') OR Tx_Dma = '1' ELSE '0';
Dma_Addr <= Dma_Tx_Addr WHEN (Rx_Dma = '0' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0') OR Tx_Dma = '1' ELSE Dma_Rx_Addr;
Rx_Dma_Ack <= '1' WHEN Rx_Dma = '1' AND Dma_Ack = '1' ELSE '0';
pDmaArb: PROCESS( Clk, Rst ) IS
BEGIN
IF Rst = '1' THEN
Rx_Dma <= '0'; Tx_Dma <= '0'; Tx_Dma_Ack <= '0';
Tx_LatchH <= (OTHERS => '0'); Tx_LatchL <= (OTHERS => '0');
Zeit <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Timer THEN
Zeit <= Zeit + 1;
END IF;
Sel_Tx_Ram <= s_Adr(8);
Sel_Tx_Reg <= NOT s_Adr(3);
IF Dma_Ack = '0' THEN
IF Rx_Dma = '0' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0' THEN Tx_Dma <= '1';
ELSIF Tx_Dma = '0' AND Rx_Dma_Req = '1' THEN Rx_Dma <= '1';
END IF;
ELSE
IF Rx_Dma = '1' AND Tx_Dma_Req = '1' AND Tx_Dma_Ack = '0' THEN Tx_Dma <= '1'; Rx_Dma <= '0';
ELSIF Tx_Dma = '1' AND Rx_Dma_Req = '1' THEN Tx_Dma <= '0'; Rx_Dma <= '1';
ELSE Tx_Dma <= '0'; Rx_Dma <= '0';
END IF;
END IF;
IF Tx_Dma = '1' AND Dma_Ack = '1' THEN Tx_Dma_Ack <= '1';
ELSE Tx_Dma_Ack <= '0';
END IF;
IF Tx_Dma_Ack = '1' THEN Tx_LatchL <= Dma_Din(15 DOWNTO 8);
Tx_LatchH <= Dma_Din( 7 DOWNTO 0);
END IF;
END IF;
END PROCESS pDmaArb;
END BLOCK b_Dma;
b_Full_Tx: BLOCK
TYPE MACTX_TYPE IS ( R_Idl, R_Bop, R_Pre, R_Txd, R_Crc, R_Col, R_Jam );
SIGNAL Sm_Tx : MACTX_TYPE;
SIGNAL Start_Tx, ClrCol, Tx_On : std_logic;
SIGNAL Dibl_Cnt : std_logic_vector( 1 DOWNTO 0);
SIGNAL F_End, Was_Col, Block_Col : std_logic;
SIGNAL Ipg_Cnt, Tx_Timer : std_logic_vector( 7 DOWNTO 0);
ALIAS Ipg : std_logic IS Ipg_Cnt(7);
ALIAS Tx_Time : std_logic IS Tx_Timer(7);
SIGNAL Tx_Ipg : std_logic_vector( 5 DOWNTO 0);
SIGNAL Tx_Count : std_logic_vector(11 DOWNTO 0);
SIGNAL Tx_En, F_Val, Tx_Half : std_logic;
SIGNAL Tx_Sr, F_TxB : std_logic_vector( 7 DOWNTO 0);
SIGNAL Crc : std_logic_vector(31 DOWNTO 0);
SIGNAL CrcDin, Tx_Dat : std_logic_vector( 1 DOWNTO 0);
SIGNAL Col_Cnt : std_logic_vector( 3 DOWNTO 0);
SIGNAL Auto_Coll : std_logic;
SIGNAL Rnd_Num : std_logic_vector( 9 DOWNTO 0);
SIGNAL Retry_Cnt : std_logic_vector( 9 DOWNTO 0);
SIGNAL Max_Retry : std_logic_vector( 3 DOWNTO 0);
BEGIN
rTx_En <= Tx_En;
rTx_Dat <= Tx_Dat;
halfDuplex <= Tx_Half;
Tx_Active <= cActivated when Sm_Tx = R_Txd or Sm_Tx = R_Crc else cInactivated;
pTxSm: PROCESS ( Clk, Rst ) IS
BEGIN
IF Rst = '1' THEN
Sm_Tx <= R_Idl;
ELSIF rising_edge( Clk ) THEN
IF Sm_Tx = R_Idl OR Sm_Tx = R_Bop OR Dibl_Cnt = "11" THEN
CASE Sm_Tx IS
WHEN R_Idl => IF Start_Tx = '1'
AND (Tx_Half = '0' OR Rx_Dv = '0')
AND Ipg = '0' THEN Sm_Tx <= R_Bop; END IF;
WHEN R_Bop => Sm_Tx <= R_Pre;
WHEN R_Pre => IF Tx_Time = '1' THEN Sm_Tx <= R_Txd; END IF;
WHEN R_Txd => IF Was_Col = '1' THEN Sm_Tx <= R_Col;
ELSIF Tx_Count = 0 THEN Sm_Tx <= R_Crc; END IF;
WHEN R_Col => Sm_Tx <= R_Jam;
WHEN R_Jam => IF Tx_Time = '1' THEN Sm_Tx <= R_Idl;
END IF;
WHEN R_Crc => IF Was_Col = '1' THEN Sm_Tx <= R_Col;
ELSIF Tx_Time = '1' THEN Sm_Tx <= R_Idl; END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END PROCESS pTxSm;
pTxCtl: PROCESS ( Clk, Rst ) IS
VARIABLE Preload : std_logic_vector(Tx_Timer'RANGE);
VARIABLE Load : std_logic;
BEGIN
IF Rst = '1' THEN
Tx_Dat <= "00"; Tx_En <= '0'; Dibl_Cnt <= "00"; F_End <= '0'; F_Val <= '0'; Tx_Col <= '0'; Was_Col <= '0'; Block_Col <= '0';
Ipg_Cnt <= (OTHERS => '0'); Tx_Timer <= (OTHERS => '0'); Tx_Sr <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Sm_Tx = R_Bop THEN Dibl_Cnt <= "00";
ELSE Dibl_Cnt <= Dibl_Cnt + 1;
END IF;
IF Tx_En = '1' THEN Ipg_Cnt <= "1" & conv_std_logic_vector( 44, 7);
ELSIF Rx_Dv = '1' AND Tx_Half = '1' THEN Ipg_Cnt <= "10" & Tx_Ipg;
ELSIF Ipg = '1' THEN Ipg_Cnt <= Ipg_Cnt - 1;
END IF;
IF Dibl_Cnt = "11" AND Sm_Tx = R_Crc AND Tx_Time = '1' THEN F_End <= '1';
ELSIF Dibl_Cnt = "11" AND Sm_Tx = R_Col THEN
IF Col_Cnt = (Max_Retry - 1) THEN F_End <= '1';
ELSIF Col_Cnt < x"E" THEN Tx_Col <= '1';
ELSE F_End <= '1';
END IF;
ELSE F_End <= '0';
Tx_Col <= '0';
END IF;
IF Tx_Half = '1' AND Rx_Dv = '1'
AND (Sm_Tx = R_Pre OR Sm_Tx = R_Txd) THEN Was_Col <= '1';
ELSIF Sm_Tx = R_Col THEN Was_Col <= '0';
END IF;
IF Sm_Tx = R_Col THEN Block_Col <= '1';
ELSIF Auto_Coll = '1' THEN Block_Col <= '0';
ELSIF Retry_Cnt = 0 THEN Block_Col <= '0';
END IF;
IF Dibl_Cnt = "10" AND Sm_Tx = R_Pre AND Tx_Time = '1' THEN F_Val <= '1';
ELSIF Dibl_Cnt = "10" AND Sm_Tx = R_Txd THEN F_Val <= '1';
ELSE F_Val <= '0';
END IF;
Load := '0';
IF Sm_Tx = R_Bop THEN Preload := x"06"; Load := '1';
ELSIF Sm_Tx = R_Txd THEN Preload := x"02"; Load := '1';
ELSIF Sm_Tx = R_Col THEN Preload := x"01"; Load := '1';
ELSIF Tx_Time = '1' THEN Preload := x"3e"; Load := '1';
END IF;
IF Dibl_Cnt = "11" OR Sm_Tx = R_Bop THEN
IF Load = '1' THEN Tx_Timer <= Preload;
ELSE Tx_Timer <= Tx_Timer - 1;
END IF;
END IF;
IF F_Val = '1' THEN Tx_Sr <= F_TxB;
ELSE Tx_Sr <= "00" & Tx_Sr(7 DOWNTO 2);
END IF;
IF Sm_Tx = R_Pre THEN Tx_En <= '1';
ELSIF Sm_Tx = R_Idl OR (Sm_Tx = R_Jam AND Tx_Time = '1') THEN Tx_En <= '0';
END IF;
IF Sm_Tx = R_Pre AND Tx_Time = '1' AND Dibl_Cnt = "11" THEN Tx_Dat <= "11";
ELSIF Sm_Tx = R_Pre THEN Tx_Dat <= "01";
ELSIF Sm_Tx = R_Txd THEN Tx_Dat <= CrcDin;
ELSIF Sm_Tx = R_Crc THEN Tx_Dat <= NOT Crc(30) & NOT Crc(31);
ELSIF Sm_Tx = R_Col OR Sm_Tx = R_Jam THEN Tx_Dat <= "11";
ELSE Tx_Dat <= "00";
END IF;
END IF;
END PROCESS pTxCtl;
pBackDel: PROCESS ( Clk, Rst ) IS
BEGIN
IF Rst = '1' THEN
Rnd_Num <= (OTHERS => '0');
Col_Cnt <= (OTHERS => '0');
Retry_Cnt <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
Rnd_Num <= Rnd_Num(8 DOWNTO 0) & (Rnd_Num(9) XOR NOT Rnd_Num(2));
IF ClrCol = '1' THEN Col_Cnt <= x"0";
ELSIF Dibl_Cnt = "11" AND Sm_Tx = R_Col THEN Col_Cnt <= Col_Cnt + 1;
END IF;
IF Dibl_Cnt = "11" THEN
IF Tx_On = '0' OR Auto_Coll = '1' THEN Retry_Cnt <= (OTHERS => '0');
ELSIF Sm_Tx = R_Col THEN
FOR i IN 0 TO 9 LOOP
IF Col_Cnt >= i THEN Retry_Cnt(i) <= Rnd_Num(i);
ELSE Retry_Cnt(i) <= '0';
END IF;
END LOOP;
ELSIF Sm_Tx /= R_Jam AND Tx_Time = '1' AND Retry_Cnt /= 0 THEN Retry_Cnt <= Retry_Cnt - 1;
END IF;
END IF;
END IF;
END PROCESS pBackDel;
CrcDin <= Tx_Sr(1 DOWNTO 0);
Calc: PROCESS ( Clk, Crc, CrcDin ) IS
VARIABLE H : std_logic_vector(1 DOWNTO 0);
BEGIN
H(0) := Crc(31) XOR CrcDin(0);
H(1) := Crc(30) XOR CrcDin(1);
IF rising_edge( Clk ) THEN
IF Sm_Tx = R_Pre THEN Crc <= x"FFFFFFFF";
ELSIF Sm_Tx = R_Crc THEN Crc <= Crc(29 DOWNTO 0) & "00";
ELSE
Crc( 0) <= H(1);
Crc( 1) <= H(0) XOR H(1);
Crc( 2) <= Crc( 0) XOR H(0) XOR H(1);
Crc( 3) <= Crc( 1) XOR H(0) ;
Crc( 4) <= Crc( 2) XOR H(1);
Crc( 5) <= Crc( 3) XOR H(0) XOR H(1);
Crc( 6) <= Crc( 4) XOR H(0) ;
Crc( 7) <= Crc( 5) XOR H(1);
Crc( 8) <= Crc( 6) XOR H(0) XOR H(1);
Crc( 9) <= Crc( 7) XOR H(0) ;
Crc(10) <= Crc( 8) XOR H(1);
Crc(11) <= Crc( 9) XOR H(0) XOR H(1);
Crc(12) <= Crc(10) XOR H(0) XOR H(1);
Crc(13) <= Crc(11) XOR H(0) ;
Crc(14) <= Crc(12) ;
Crc(15) <= Crc(13) ;
Crc(16) <= Crc(14) XOR H(1);
Crc(17) <= Crc(15) XOR H(0) ;
Crc(18) <= Crc(16) ;
Crc(19) <= Crc(17) ;
Crc(20) <= Crc(18) ;
Crc(21) <= Crc(19) ;
Crc(22) <= Crc(20) XOR H(1);
Crc(23) <= Crc(21) XOR H(0) XOR H(1);
Crc(24) <= Crc(22) XOR H(0) ;
Crc(25) <= Crc(23) ;
Crc(26) <= Crc(24) XOR H(1);
Crc(27) <= Crc(25) XOR H(0) ;
Crc(28) <= Crc(26) ;
Crc(29) <= Crc(27) ;
Crc(30) <= Crc(28) ;
Crc(31) <= Crc(29) ;
END IF;
END IF;
END PROCESS Calc;
bTxDesc: BLOCK
TYPE sDESC IS (sIdle, sLen, sTimL, sTimH, sAdrH, sAdrL, sReq, sBegL, sBegH, sDel, sData, sStat, sColl );
SIGNAL Dsm, Tx_Dsm_Next : sDESC;
SIGNAL DescRam_Out, DescRam_In : std_logic_vector(15 DOWNTO 0);
ALIAS TX_LEN : std_logic_vector(11 DOWNTO 0) IS DescRam_Out(11 DOWNTO 0);
ALIAS TX_OWN : std_logic IS DescRam_Out( 8);
ALIAS TX_LAST : std_logic IS DescRam_Out( 9);
ALIAS TX_READY : std_logic IS DescRam_Out(10);
ALIAS TX_BEGDEL : std_logic IS DescRam_Out(12);
ALIAS TX_BEGON : std_logic IS DescRam_Out(13);
ALIAS TX_TIME : std_logic IS DescRam_Out(14);
ALIAS TX_RETRY : std_logic_vector( 3 DOWNTO 0) IS DescRam_Out(3 DOWNTO 0);
SIGNAL Ram_Be : std_logic_vector( 1 DOWNTO 0);
SIGNAL Ram_Wr, Desc_We : std_logic;
SIGNAL Desc_Addr : std_logic_vector( 7 DOWNTO 0);
SIGNAL DescIdx : std_logic_vector( 2 DOWNTO 0);
SIGNAL Last_Desc : std_logic;
SIGNAL ZeitL : std_logic_vector(15 DOWNTO 0);
SIGNAL Tx_Ie, Tx_Wait : std_logic;
SIGNAL Tx_BegInt, Tx_BegSet, Tx_Early : std_logic;
SIGNAL Tx_Del : std_logic;
SIGNAL Ext_Tx, Ext_Ack : std_logic;
SIGNAL Tx_Desc, Tx_Desc_One, Ext_Desc : std_logic_vector( 3 DOWNTO 0);
SIGNAL Tx_Icnt : std_logic_vector( 4 DOWNTO 0);
SIGNAL Tx_SoftInt : std_logic;
SIGNAL Sel_TxH, Sel_TxL, H_Byte : std_logic;
SIGNAL Tx_Buf : std_logic_vector( 7 DOWNTO 0);
SIGNAL Tx_Idle, TxInt, Tx_Beg, Tx_Sync : std_logic;
SIGNAL Tx_Ident : std_logic_vector( 1 DOWNTO 0);
SIGNAL Tx_Cmp_High : std_logic_vector(15 downto 0);
SIGNAL Start_TxS : std_logic;
SIGNAL Tx_Dma_Out : std_logic;
SIGNAL Tx_Del_Cnt : std_logic_vector(32 downto 0);
ALIAS Tx_Del_End : std_logic is Tx_Del_Cnt(Tx_Del_Cnt'high);
SIGNAL Tx_Del_Run : std_logic;
signal Tx_Done : std_logic;
BEGIN
Dma_Rd_Done <= Tx_Done;
Tx_Done <= '1' when Dsm = sStat or Dsm = sColl else '0';
Tx_Dma_Very1stOverflow <= cActivated when Dibl_Cnt = "01" and Sm_Tx = R_Pre and Tx_Timer(7) = '1' else cInactivated;
Ram_Wr <= '1' WHEN s_nWr = '0' AND Sel_Ram = '1' AND s_Adr(10) = '1' ELSE '0';
Ram_Be(1) <= '1' WHEN s_nWr = '1' OR s_nBE(1) = '0' ELSE '0';
Ram_Be(0) <= '1' WHEN s_nWr = '1' OR s_nBE(0) = '0' ELSE '0';
DescIdx <= "000" WHEN Desc_We = '0' AND Tx_Dsm_Next = sIdle ELSE
"000" WHEN Desc_We = '1' AND Dsm = sIdle ELSE
"001" WHEN Desc_We = '0' AND Tx_Dsm_Next = sLen ELSE
"001" WHEN Desc_We = '1' AND Dsm = sLen ELSE
"010" WHEN Desc_We = '0' AND Tx_Dsm_Next = sAdrH ELSE
"010" WHEN Desc_We = '1' AND Dsm = sAdrH ELSE
"011" WHEN Desc_We = '0' AND Tx_Dsm_Next = sAdrL ELSE
"011" WHEN Desc_We = '1' AND Dsm = sAdrL ELSE
"100" WHEN Desc_We = '0' AND Tx_Dsm_Next = sBegH ELSE
"100" WHEN Desc_We = '1' AND Dsm = sBegH ELSE
"101" WHEN Desc_We = '0' AND Tx_Dsm_Next = sBegL ELSE
"101" WHEN Desc_We = '1' AND Dsm = sBegL ELSE
"110" WHEN Desc_We = '0' AND Tx_Dsm_Next = sTimH ELSE
"110" WHEN Desc_We = '1' AND Dsm = sTimH ELSE
"111" WHEN Desc_We = '0' AND Tx_Dsm_Next = sTimL ELSE
"111" WHEN Desc_We = '1' AND Dsm = sTimL ELSE
"111" WHEN Desc_We = '0' AND Tx_Dsm_Next = sData ELSE
"111" WHEN Desc_We = '1' AND Dsm = sData ELSE
"000";
Desc_We <= '1' WHEN Dsm = sTimL OR Dsm = sTimH OR Dsm = sStat ELSE '0';
Desc_Addr <= '1' & Tx_Desc & DescIdx WHEN Ext_Tx = '0' ELSE
'1' & Ext_Desc & DescIdx;
gTxTime: IF Timer GENERATE
DescRam_In <= Zeit(15 DOWNTO 0) WHEN Dsm = sTimH ELSE
ZeitL WHEN Dsm = sTimL ELSE
x"000" & "01" & Tx_Ident WHEN Dsm = sBegL ELSE
Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt;
END GENERATE;
gnTxTime: IF NOT Timer GENERATE
DescRam_In <= x"000" & "01" & Tx_Ident WHEN Dsm = sBegL ELSE
Tx_Dma_Out & Tx_Sync & "00" & "0100" & "00" & "0" & "0" & Col_Cnt;
END GENERATE;
RamH: ENTITY work.Dpr_16_16
GENERIC MAP(Simulate => Simulate)
PORT MAP ( CLKA => Clk, CLKB => Clk,
EnA => cActivated, Enb => cActivated,
BEA => Ram_Be,
WEA => Ram_Wr, WEB => Desc_We,
ADDRA => s_Adr(8 DOWNTO 1), ADDRB => Desc_Addr,
DIA => s_Din, DIB => DescRam_In,
DOA => Tx_Ram_Dat, DOB => DescRam_Out
);
ASSERT NOT( TxSyncOn AND NOT Timer )
REPORT "TxSyncOn needs Timer!"
severity failure;
pTxSm: PROCESS( Rst, Clk, Dsm,
Tx_On, TX_OWN, Retry_Cnt, Ext_Tx, Tx_Wait,
Tx_Sync, Sm_Tx, F_End, Tx_Col, Ext_Ack, Tx_Del, Tx_Beg )
BEGIN
Tx_Dsm_Next <= Dsm;
CASE Dsm IS
WHEN sIdle => IF Tx_On = '1' AND TX_OWN = '1' AND Retry_Cnt = 0 THEN
IF (Ext_Tx = '1' AND Ext_Ack = '0') OR Tx_Wait = '0' THEN
Tx_Dsm_Next <= sAdrH; --sLen;
END IF;
END IF;
WHEN sLen => IF Tx_Sync = '0' THEN Tx_Dsm_Next <= sReq; --sAdrH;
ELSE Tx_Dsm_Next <= sBegH;
END IF;
WHEN sBegH => Tx_Dsm_Next <= sBegL;
WHEN sBegL => IF Tx_On = '0' THEN Tx_Dsm_Next <= sIdle;
ELSIF Tx_Sync = '0' THEN
if Tx_Del = '1' then Tx_Dsm_Next <= sDel;
elsIF Sm_Tx = R_Pre THEN
Tx_Dsm_Next <= sTimH;
END IF;
ELSIF Tx_Sync = '1' and Tx_Beg = '1' and Tx_Half = '1' and rCrs_Dv = '1' THEN
Tx_Dsm_Next <= sColl;
ELSIF Tx_Beg = '1' THEN Tx_Dsm_Next <= sReq;
END IF;
WHEN sDel => IF Tx_On = '0' THEN Tx_Dsm_Next <= sIdle; --avoid FSM hang
ELSIF Tx_Del_End = '1' THEN Tx_Dsm_Next <= sTimH;
END IF;
WHEN sAdrH => Tx_Dsm_Next <= sAdrL;
WHEN sAdrL => Tx_Dsm_Next <= sLen; --sReq;
--leaving sAdrL and entering sReq leads to the very first Tx_Dma_Req
-- this enables early dma req at the beginning of IPG (auto-resp)
WHEN sReq => IF Tx_On = '0' THEN Tx_Dsm_Next <= sIdle;
elsif Tx_Del = '1' then Tx_Dsm_Next <= sBegH;
ELSIF Tx_Sync = '0' THEN Tx_Dsm_Next <= sBegL;
ELSIF Sm_Tx = R_Bop THEN Tx_Dsm_Next <= sTimH;
END IF;
WHEN sTimH => Tx_Dsm_Next <= sTimL;
WHEN sTimL => Tx_Dsm_Next <= sData;
WHEN sData => IF F_End = '1' THEN Tx_Dsm_Next <= sStat;
ELSIF Tx_Col = '1' THEN Tx_Dsm_Next <= sColl;
END IF;
WHEN sStat => Tx_Dsm_Next <= sIdle;
WHEN sColl => if sm_tx = r_idl then
if Tx_Sync = '1' then Tx_Dsm_Next <= sStat;
else Tx_Dsm_Next <= sIdle;
end if;
end if;
WHEN OTHERS =>
END CASE;
IF Rst = '1' THEN Dsm <= sIdle;
ELSIF rising_edge( Clk ) THEN Dsm <= Tx_Dsm_Next;
END IF;
END PROCESS pTxSm;
pTxControl: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Last_Desc <= '0'; Start_TxS <= '0'; Tx_Dma_Req <= '0'; H_Byte <= '0';
Tx_Beg <= '0'; Tx_BegSet <= '0'; Tx_Early <= '0'; Auto_Coll <= '0'; Tx_Dma_Out <= '0';
Ext_Tx <= '0'; Ext_Ack <= '0'; ClrCol <= '0'; Ext_Desc <= (OTHERS => '0'); Tx_Sync <= '0'; Max_Retry <= (others => '0');
ZeitL <= (OTHERS => '0'); Tx_Count <= (OTHERS => '0'); Tx_Ident <= "00";
Dma_Tx_Addr <= (OTHERS => '0'); Tx_Cmp_High <= (others => '0');
Tx_Del_Run <= '0';
Tx_Del <= '0'; Tx_Del_Cnt <= (others => '0'); Tx_Dma_Len <= (others => '0');
ELSIF rising_edge( Clk ) THEN
IF TxSyncOn = true THEN
IF Tx_Sync = '1' AND Dsm = sBegL AND (DescRam_Out & Tx_Cmp_High ) = Zeit THEN Tx_Beg <= '1';
ELSE Tx_Beg <= '0';
END IF;
END IF;
IF Dsm = sStat AND Desc_We = '1' THEN ClrCol <= '1';
ELSE ClrCol <= '0';
END IF;
IF Timer THEN
IF Dsm = sTimH THEN ZeitL <= Zeit(31 DOWNTO 16);
END IF;
END IF;
IF Ext_Ack = '0' AND R_Req = '1' THEN Ext_Desc <= Auto_Desc;
Ext_Ack <= '1';
ELSIF Ext_Tx = '1' OR Tx_On = '0' THEN Ext_Ack <= '0';
END IF;
IF Dsm = sIdle AND Ext_Ack = '1' THEN Ext_Tx <= '1';
ELSIF Dsm = sStat OR Tx_Col = '1' OR Tx_On = '0' THEN Ext_Tx <= '0';
END IF;
IF (F_End = '1' OR Tx_On = '0'
OR (Tx_Col = '1' AND Ext_Tx = '1' )
OR dsm = sColl ) THEN Start_TxS <= '0';
Auto_Coll <= Auto_Coll OR (Tx_Col AND Ext_Tx);
ELSIF Dsm = sReq and Tx_Del = '0' THEN Start_TxS <= '1';
ELSIF Dsm = sDel and Tx_Del_End = '1' THEN Start_TxS <= '1';
ELSIF Sm_Tx = R_Idl THEN Auto_Coll <= '0';
END IF;
IF Dsm = sIdle THEN Last_Desc <= TX_LAST;
END IF;
IF Dsm = sLen THEN Tx_Count <= TX_LEN; Tx_Dma_Len <= TX_LEN; --add CRC
ELSIF F_Val = '1' THEN Tx_Count <= Tx_Count - 1;
END IF;
IF Dsm = sBegH THEN Tx_Cmp_High <= DescRam_Out;
END IF;
IF Dsm = sIdle AND Tx_On = '1' AND TX_OWN = '1' AND Retry_Cnt = 0 THEN
IF Ext_Tx = '1' OR Tx_Wait = '0' THEN
IF TxSyncOn THEN Tx_Sync <= TX_TIME;
ELSE Tx_Sync <= '0';
END IF;
Max_Retry <= TX_RETRY;
Tx_Early <= TX_BEGON;
IF TxDel = true THEN Tx_Del <= TX_BEGDEL;
END IF;
END IF;
ELSIF Dsm = sTimH THEN Tx_BegSet <= Tx_Early;
ELSIF Dsm = sTimL THEN Tx_BegSet <= '0';
ELSIF Dsm = sIdle THEN Tx_Del <= '0';
END IF;
if TxDel = true and Tx_Del = '1' then
if Dsm = sBegH then Tx_Del_Cnt(Tx_Del_Cnt'high) <= '0';
Tx_Del_Cnt(15 downto 0) <= DescRam_Out;
elsif Dsm = sBegL then Tx_Del_Cnt(31 downto 16) <= DescRam_Out;
elsif Dsm = sDel and Tx_Del_Run = '1' then Tx_Del_Cnt <= Tx_Del_Cnt - 1;
end if;
if Tx_Del_Run = '0' and Dsm = sDel then Tx_Del_Run <= '1'; --don't consider Ipg
elsif Tx_Del_End = '1' then Tx_Del_Run <= '0';
end if;
end if;
IF Dsm = sAdrL THEN --Dma_Tx_Addr(15 DOWNTO 1) <= DescRam_Out(15 DOWNTO 1);
Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) <= DescRam_Out(Dma_Addr'high-16 DOWNTO 0);
Tx_Ident <= DescRam_Out(15 DOWNTO 14);
ELSIF Tx_Dma_Ack = '1' THEN Dma_Tx_Addr(15 DOWNTO 1) <= Dma_Tx_Addr(15 DOWNTO 1) + 1;
END IF;
IF Dsm = sAdrH THEN Dma_Tx_Addr(15 DOWNTO 1) <= DescRam_Out(15 DOWNTO 1);
-- Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) <= DescRam_Out(Dma_Addr'high-16 DOWNTO 0);
-- Tx_Ident <= DescRam_Out(15 DOWNTO 14);
ELSIF Tx_Dma_Ack = '1' AND Dma_Tx_Addr(15 DOWNTO 1) = x"FFF" & "111" THEN
Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) <= Dma_Tx_Addr(Dma_Addr'high DOWNTO 16) + 1;
END IF;
IF DSM = sAdrL
OR (F_Val = '1' AND H_Byte = '0') THEN Tx_Dma_Req <= '1';
ELSIF Tx_Dma_Ack = '1' THEN Tx_Dma_Req <= '0';
END IF;
IF Sm_Tx = R_Bop THEN H_Byte <= '0';
ELSIF F_Val = '1' THEN H_Byte <= NOT H_Byte;
END IF;
IF F_Val = '1' THEN Tx_Buf <= Tx_LatchL;
END IF;
if H_Byte = '0' and F_Val = '1' and Tx_Dma_Req = '1' then Tx_Dma_Out <= '1';
elsif Sm_Tx = R_Bop then Tx_Dma_Out <= '0';
end if;
END IF;
END PROCESS pTxControl;
Start_Tx <= '1' WHEN Start_TxS = '1' AND Block_Col = '0' ELSE
'1' WHEN not TxDel and not TxSyncOn and R_Req = '1' ELSE
'0';
F_TxB <= Tx_LatchH WHEN H_Byte = '0' ELSE
Tx_Buf;
nTx_Int <= '1' WHEN (Tx_Icnt = 0 AND Tx_SoftInt = '0') OR Tx_Ie = '0' ELSE '0';
Tx_Idle <= '1' WHEN Sm_Tx = R_Idl AND Dsm = sIdle ELSE '0';
Tx_Reg(15 DOWNTO 4) <= Tx_Ie & Tx_SoftInt & Tx_Half & Tx_Wait & (Tx_Icnt(4) OR Tx_Icnt(3)) & Tx_Icnt(2 DOWNTO 0)
& Tx_On & Tx_BegInt & Tx_Idle & "0" ;
Tx_Reg( 3 DOWNTO 0) <= Tx_Desc;
Sel_TxH <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '0' AND Ram_Be(1) = '1' ELSE '0';
Sel_TxL <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '0' AND Ram_Be(0) = '1' ELSE '0';
Tx_Desc <= Tx_Desc_One;
Tx_SoftInt <= '0';
pTxRegs: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Tx_On <= '0'; Tx_Ie <= '0'; Tx_Half <= '0'; Tx_Wait <= '0'; nTx_BegInt <= '0';
Tx_Desc_One <= (OTHERS => '0');
Tx_Icnt <= (OTHERS => '0'); TxInt <= '0'; Tx_BegInt <= '0';
Tx_Ipg <= conv_std_logic_vector( 42, 6);
ELSIF rising_edge( Clk ) THEN
IF Sel_TxL = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_On <= S_Din( 7);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din( 7) = '1' THEN Tx_On <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din( 7) = '1' THEN Tx_On <= '0';
END IF;
END IF;
IF Tx_BegSet = '1' AND Tx_Ie = '1' THEN Tx_BegInt <= '1';
ELSIF Sel_TxL = '1' AND s_Adr(2 DOWNTO 1) = "01" AND S_Din( 6) = '1' THEN Tx_BegInt <= '1';
ELSIF Sel_TxL = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din( 6) = '1' THEN Tx_BegInt <= '0';
END IF;
nTx_BegInt <= NOT Tx_BegInt;
IF Sel_TxL = '1' AND s_Adr(2 DOWNTO 1) = "11" THEN Tx_Desc_One <= S_Din( 3 DOWNTO 0);
ELSIF Dsm = sStat AND Ext_Tx = '0' THEN
IF Last_Desc = '1' THEN Tx_Desc_One <= x"0";
ELSE Tx_Desc_One <= Tx_Desc + 1;
END IF;
END IF;
IF Sel_TxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_Ie <= S_Din(15);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(15) = '1' THEN Tx_Ie <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(15) = '1' THEN Tx_Ie <= '0';
END IF;
END IF;
IF Sel_TxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_Half <= S_Din(13);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(13) = '1' THEN Tx_Half <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(13) = '1' THEN Tx_Half <= '0';
END IF;
END IF;
IF Sel_TxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Tx_Wait <= S_Din(12);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(12) = '1' THEN Tx_Wait <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(12) = '1' THEN Tx_Wait <= '0';
END IF;
END IF;
IF Sel_TxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "11" AND S_Din(14) = '1' THEN Tx_Ipg <= S_Din(13 DOWNTO 8);
END IF;
END IF;
IF Tx_Ie = '1' AND Dsm = sStat AND Desc_We = '1' THEN TxInt <= '1';
ELSE TxInt <= '0';
END IF;
IF Sel_TxH = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din(8) = '1'
AND Tx_Icnt /= 0 THEN Tx_Icnt <= Tx_Icnt - NOT TxInt;
ELSIF TxInt = '1' AND Tx_Icnt /= "11111" THEN Tx_Icnt <= Tx_Icnt + 1;
END IF;
END IF;
END PROCESS pTxRegs;
END BLOCK bTxDesc;
END BLOCK b_Full_Tx;
b_Full_Rx: BLOCK
TYPE MACRX_TYPE IS ( R_Idl, R_Sof, R_Rxd );
SIGNAL Sm_Rx : MACRX_TYPE;
SIGNAL Rx_Dat, Rx_DatL : std_logic_vector( 1 DOWNTO 0);
SIGNAL Tx_Timer : std_logic_vector( 7 DOWNTO 0);
SIGNAL Dibl_Cnt : std_logic_vector( 1 DOWNTO 0);
SIGNAL Crc, nCrc : std_logic_vector(31 DOWNTO 0);
SIGNAL CrcDin : std_logic_vector( 1 DOWNTO 0);
SIGNAL F_Err, P_Err, N_Err, A_Err : std_logic;
SIGNAL F_End, F_Val, Rx_Beg : std_logic;
SIGNAL Rx_Sr : std_logic_vector( 7 DOWNTO 0);
SIGNAL nCrc_Ok, Crc_Ok : std_logic;
SIGNAL WrDescStat : std_logic;
SIGNAL PreCount : std_logic_vector( 4 DOWNTO 0);
SIGNAL PreBeg, PreErr : std_logic;
SIGNAL Rx_DvL : std_logic;
SIGNAL Diag : std_logic;
BEGIN
Rx_Beg <= '1' WHEN Rx_Dv = '1' AND Sm_Rx = R_SOF AND Rx_Dat = "11" ELSE '0';
nCrc_Ok <= '1' WHEN nCrc = x"C704DD7B" ELSE '0';
rxsm: PROCESS ( Clk, Rst ) IS
BEGIN
IF Rst = '1' THEN
Sm_Rx <= R_Idl;
ELSIF rising_edge( Clk ) THEN
IF Sm_Rx = R_Idl OR Sm_Rx = R_Rxd OR Sm_Rx = R_Sof OR Dibl_Cnt = "11" THEN
CASE Sm_Rx IS
WHEN R_Idl => IF Rx_Dv = '1' THEN Sm_Rx <= R_Sof; END IF;
WHEN R_Sof => IF Rx_Dat = "11" THEN Sm_Rx <= R_Rxd;
ELSIF Rx_Dv = '0' THEN Sm_Rx <= R_Idl; END IF;
WHEN R_Rxd => IF Rx_Dv = '0' THEN Sm_Rx <= R_Idl; END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END PROCESS rxsm;
pRxCtl: PROCESS ( Clk, Rst ) IS
VARIABLE Preload : std_logic_vector(Tx_Timer'RANGE);
VARIABLE Load : std_logic;
BEGIN
IF Rst = '1' THEN
Rx_DatL <= "00"; Rx_Dat <= "00"; Rx_Dv <= '0'; Dibl_Cnt <= "00"; PreCount <= (OTHERS => '0');
F_End <= '0'; F_Err <= '0'; F_Val <= '0'; Crc_Ok <= '0';
A_Err <= '0'; N_Err <= '0'; P_Err <= '0'; PreBeg <= '0'; PreErr <= '0';
ELSIF rising_edge( Clk ) THEN
Rx_DatL <= rRx_Dat;
Rx_Dat <= Rx_DatL;
IF Rx_Dv = '0' AND rCrs_Dv = '1' THEN Rx_Dv <= '1';
ELSIF Rx_Dv = '1' AND rCrs_Dv = '0' AND Dibl_Cnt(0) = '1' THEN Rx_Dv <= '0';
END IF;
IF Rx_Beg = '1' THEN Dibl_Cnt <= "00";
ELSE Dibl_Cnt <= Dibl_Cnt + 1;
END IF;
Crc_Ok <= nCrc_Ok;
IF (Sm_Rx = R_Rxd AND Rx_Dv = '0') THEN F_End <= '1';
F_Err <= NOT Crc_Ok;
ELSE F_End <= '0';
END IF;
IF Dibl_Cnt = "11" AND Sm_Rx = R_Rxd THEN F_Val <= '1';
ELSE F_Val <= '0';
END IF;
IF WrDescStat = '1' THEN A_Err <= '0';
ELSIF F_End = '1' AND Dibl_Cnt /= 1 THEN A_Err <= '1';
END IF;
IF Rx_Dv = '0' OR Rx_Dat(0) = '0' THEN PreCount <= (OTHERS => '1');
ELSE PreCount <= PreCount - 1;
END IF;
IF Rx_Dv = '0' THEN PreBeg <= '0';
ELSIF Rx_Dat = "01" THEN PreBeg <= '1';
END IF;
IF WrDescStat = '1' THEN N_Err <= '0';
ELSIF Sm_Rx = R_Sof AND Rx_Dv = '0' THEN N_Err <= '1';
END IF;
IF Rx_DvL = '0' THEN PreErr <= '0';
ELSIF PreBeg = '0' AND (Rx_Dat = "10" OR Rx_Dat = "11") THEN PreErr <= '1';
ELSIF PreBeg = '1' AND (Rx_Dat = "10" OR Rx_Dat = "00") THEN PreErr <= '1';
END IF;
IF WrDescStat = '1' THEN P_Err <= '0';
ELSIF Rx_Beg = '1' AND PreErr = '1' THEN P_Err <= '1';
ELSIF Rx_Beg = '1' AND PreCount /= 0 THEN P_Err <= '1';
END IF;
Rx_Sr <= Rx_Dat(1) & Rx_Dat(0) & Rx_Sr(7 DOWNTO 2);
Rx_DvL <= Rx_Dv;
END IF;
END PROCESS pRxCtl;
CrcDin <= Rx_Dat;
Calc: PROCESS ( Clk, Crc, nCrc, CrcDin, Sm_Rx ) IS
VARIABLE H : std_logic_vector(1 DOWNTO 0);
BEGIN
H(0) := Crc(31) XOR CrcDin(0);
H(1) := Crc(30) XOR CrcDin(1);
IF Sm_Rx = R_Sof THEN nCrc <= x"FFFFFFFF";
ELSE
nCrc( 0) <= H(1);
nCrc( 1) <= H(0) XOR H(1);
nCrc( 2) <= Crc( 0) XOR H(0) XOR H(1);
nCrc( 3) <= Crc( 1) XOR H(0) ;
nCrc( 4) <= Crc( 2) XOR H(1);
nCrc( 5) <= Crc( 3) XOR H(0) XOR H(1);
nCrc( 6) <= Crc( 4) XOR H(0) ;
nCrc( 7) <= Crc( 5) XOR H(1);
nCrc( 8) <= Crc( 6) XOR H(0) XOR H(1);
nCrc( 9) <= Crc( 7) XOR H(0) ;
nCrc(10) <= Crc( 8) XOR H(1);
nCrc(11) <= Crc( 9) XOR H(0) XOR H(1);
nCrc(12) <= Crc(10) XOR H(0) XOR H(1);
nCrc(13) <= Crc(11) XOR H(0) ;
nCrc(14) <= Crc(12) ;
nCrc(15) <= Crc(13) ;
nCrc(16) <= Crc(14) XOR H(1);
nCrc(17) <= Crc(15) XOR H(0) ;
nCrc(18) <= Crc(16) ;
nCrc(19) <= Crc(17) ;
nCrc(20) <= Crc(18) ;
nCrc(21) <= Crc(19) ;
nCrc(22) <= Crc(20) XOR H(1);
nCrc(23) <= Crc(21) XOR H(0) XOR H(1);
nCrc(24) <= Crc(22) XOR H(0) ;
nCrc(25) <= Crc(23) ;
nCrc(26) <= Crc(24) XOR H(1);
nCrc(27) <= Crc(25) XOR H(0) ;
nCrc(28) <= Crc(26) ;
nCrc(29) <= Crc(27) ;
nCrc(30) <= Crc(28) ;
nCrc(31) <= Crc(29) ;
END IF;
IF rising_edge( Clk ) THEN
Crc <= nCrc;
END IF;
END PROCESS Calc;
bRxDesc: BLOCK
TYPE sDESC IS (sIdle, sLen, sTimL, sTimH, sAdrH, sAdrL, sData, sOdd, sStat, sLenW );
SIGNAL Dsm, Rx_Dsm_Next : sDESC;
SIGNAL Rx_Buf, Rx_LatchH, Rx_LatchL : std_logic_vector( 7 DOWNTO 0);
SIGNAL Rx_Ovr : std_logic;
SIGNAL DescRam_Out, DescRam_In : std_logic_vector(15 DOWNTO 0);
ALIAS RX_LEN : std_logic_vector(11 DOWNTO 0) IS DescRam_Out(11 DOWNTO 0);
ALIAS RX_OWN : std_logic IS DescRam_Out( 8);
ALIAS RX_LAST : std_logic IS DescRam_Out( 9);
SIGNAL Ram_Be : std_logic_vector( 1 DOWNTO 0);
SIGNAL Ram_Wr, Desc_We : std_logic;
SIGNAL Desc_Addr : std_logic_vector( 7 DOWNTO 0);
SIGNAL ZeitL : std_logic_vector(15 DOWNTO 0);
SIGNAL Rx_On, Rx_Ie, Sel_RxH, Sel_RxL : std_logic;
SIGNAL Rx_Desc, Match_Desc : std_logic_vector( 3 DOWNTO 0);
SIGNAL Rx_Icnt : std_logic_vector( 4 DOWNTO 0);
SIGNAL Rx_Lost, Last_Desc, Answer_Tx : std_logic;
SIGNAL DescIdx : std_logic_vector( 2 DOWNTO 0);
SIGNAL Rx_Count, Rx_Limit : std_logic_vector(11 DOWNTO 0);
SIGNAL Match, Filt_Cmp : std_logic;
SIGNAL Rx_Idle, RxInt : std_logic;
SIGNAL Hub_Rx_L : std_logic_vector( 1 DOWNTO 0);
SIGNAL Rx_Dma_Out : std_logic;
signal Rx_Done : std_logic;
BEGIN
process(rst, clk)
variable doPulse : std_logic;
begin
if rst = cActivated then
Rx_Done <= cInactivated;
doPulse := cInactivated;
elsif rising_edge(clk) then
Rx_Done <= cInactivated;
if Dsm /= sIdle and Rx_Dsm_Next = sIdle then
-- RX is done
doPulse := cActivated;
end if;
if doPulse = cActivated and Rx_Dma_Req = cInactivated and Rx_Count = 0 then
-- RX is done and there is no dma request
Rx_Done <= cActivated;
doPulse := cInactivated;
end if;
end if;
end process;
Dma_Wr_Done <= Rx_Done;
WrDescStat <= '1' WHEN Dsm = sStat ELSE '0';
Ram_Wr <= '1' WHEN s_nWr = '0' AND Sel_Ram = '1' AND s_Adr(10) = '1' ELSE '0';
Ram_Be(1) <= '1' WHEN s_nWr = '1' OR s_nBE(1) = '0' ELSE '0';
Ram_Be(0) <= '1' WHEN s_nWr = '1' OR s_nBE(0) = '0' ELSE '0';
DescIdx <= "001" WHEN Desc_We = '0' AND (Rx_Dsm_Next = sLen OR Rx_Dsm_Next = sLenW) ELSE
"001" WHEN Desc_We = '1' AND (Dsm = sLen OR Dsm = sLenW) ELSE
"010" WHEN Desc_We = '0' AND Rx_Dsm_Next = sAdrH ELSE
"010" WHEN Desc_We = '1' AND Dsm = sAdrH ELSE
"011" WHEN Desc_We = '0' AND Rx_Dsm_Next = sAdrL ELSE
"011" WHEN Desc_We = '1' AND Dsm = sAdrL ELSE
"110" WHEN Desc_We = '0' AND Rx_Dsm_Next = sTimH ELSE
"110" WHEN Desc_We = '1' AND Dsm = sTimH ELSE
"111" WHEN Desc_We = '0' AND Rx_Dsm_Next = sTimL ELSE
"111" WHEN Desc_We = '1' AND Dsm = sTimL ELSE
"000";
Desc_We <= '1' WHEN Dsm = sTimL OR Dsm = sTimH ELSE
'1' WHEN (Dsm = sLenW OR Dsm = sStat) AND Match = '1' ELSE '0';
Desc_Addr <= "0" & Rx_Desc & DescIdx;
gRxTime: IF timer GENERATE
DescRam_In <= Zeit(15 DOWNTO 0) WHEN Dsm = sTimH ELSE
ZeitL WHEN Dsm = sTimL ELSE
x"0" & Rx_Count WHEN Dsm = sLenW ELSE
Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err;
END GENERATE;
ngRxTime: IF NOT timer GENERATE
DescRam_In <= x"0" & Rx_Count WHEN Dsm = sLenW ELSE
Rx_Dma_Out & '0' & "0" & A_Err & Hub_Rx_L & "00" & Match_Desc & N_Err & P_Err & Rx_Ovr & F_Err;
END GENERATE;
RxRam: ENTITY work.Dpr_16_16
GENERIC MAP(Simulate => Simulate)
PORT MAP ( CLKA => Clk, CLKB => Clk,
EnA => cActivated, Enb => cActivated,
BEA => Ram_Be,
WEA => Ram_Wr, WEB => Desc_We,
ADDRA => s_Adr(8 DOWNTO 1), ADDRB => Desc_Addr,
DIA => s_Din, DIB => DescRam_In,
DOA => Rx_Ram_Dat, DOB => DescRam_Out
);
pRxSm: PROCESS( Rst, Clk, Dsm,
Rx_Beg, Rx_On, RX_OWN, F_End, F_Err, Diag, Rx_Count )
BEGIN
Rx_Dsm_Next <= Dsm;
CASE Dsm IS
WHEN sIdle => IF Rx_Beg = '1' AND Rx_On = '1' AND RX_OWN = '1' THEN
Rx_Dsm_Next <= sLen;
END IF;
WHEN sLen => Rx_Dsm_Next <= sAdrH;
WHEN sAdrH => Rx_Dsm_Next <= sAdrL;
WHEN sAdrL => Rx_Dsm_Next <= sTimH;
WHEN sTimH => Rx_Dsm_Next <= sTimL;
WHEN sTimL => Rx_Dsm_Next <= sData;
WHEN sData => IF F_End = '1' THEN
IF F_Err = '0'
OR Diag = '1' THEN Rx_Dsm_Next <= sStat;
ELSE Rx_Dsm_Next <= sIdle;
END IF;
END IF;
WHEN sStat => Rx_Dsm_Next <= sLenW;
WHEN sLenW => IF Rx_Count(0) = '0' THEN
Rx_Dsm_Next <= sIdle;
ELSE Rx_Dsm_Next <= sOdd;
END IF;
WHEN sOdd => Rx_Dsm_Next <= sIdle;
WHEN OTHERS =>
END CASE;
IF Rst = '1' THEN Dsm <= sIdle;
ELSIF rising_edge( Clk ) THEN Dsm <= Rx_Dsm_Next;
END IF;
END PROCESS pRxSm;
pRxControl: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Rx_Ovr <= '0'; Rx_Dma_Req <= '0'; Last_Desc <= '0'; Rx_Dma_Out <= '0';
Rx_Count <= (OTHERS => '0');
Rx_Buf <= (OTHERS => '0'); Rx_LatchL <= (OTHERS => '0'); Rx_LatchH <= (OTHERS => '0');
Dma_Rx_Addr <= (OTHERS => '0');
ELSIF rising_edge( Clk ) THEN
IF Timer THEN
IF Dsm = sTimH THEN ZeitL <= Zeit(31 DOWNTO 16);
END IF;
END IF;
IF Dsm = sIdle THEN Rx_Count <= (OTHERS => '0');
Last_Desc <= RX_LAST;
ELSIF F_Val = '1' THEN Rx_Count <= Rx_Count + 1;
END IF;
IF Dsm = sLen THEN Rx_Limit <= RX_LEN;
Hub_Rx_L <= Hub_Rx;
END IF;
IF F_Val = '1' THEN Rx_Buf <= Rx_Sr;
END IF;
IF (F_Val = '1' AND Rx_Count(0) = '1') OR Dsm = sStat THEN Rx_LatchH <= Rx_Buf;
Rx_LatchL <= Rx_Sr;
IF Rx_Dma_Req = '1' AND Sm_Rx /= R_Idl THEN Rx_Dma_Out <= '1';
END IF;
ELSIF Dsm = sLen THEN Rx_Dma_Out <= '0';
END IF;
IF Dsm = sLen THEN Rx_Ovr <= '0';
ELSIF F_Val = '1' AND Rx_Limit = Rx_Count THEN Rx_Ovr <= '1';
END IF;
IF Dsm = sAdrL THEN --Dma_Rx_Addr(15 DOWNTO 1) <= DescRam_Out(15 DOWNTO 1);
Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) <= DescRam_Out(Dma_Addr'high-16 DOWNTO 0);
ELSIF Rx_Dma_Ack = '1' THEN Dma_Rx_Addr(15 DOWNTO 1) <= Dma_Rx_Addr(15 DOWNTO 1) + 1;
END IF;
IF Dsm = sAdrH THEN Dma_Rx_Addr(15 DOWNTO 1) <= DescRam_Out(15 DOWNTO 1);
--Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) <= DescRam_Out(Dma_Addr'high-16 DOWNTO 0);
ELSIF Rx_Dma_Ack = '1' AND Dma_Rx_Addr(15 DOWNTO 1) = x"FFF" & "111" THEN
Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) <= Dma_Rx_Addr(Dma_Addr'high DOWNTO 16) + 1;
END IF;
IF Filt_Cmp = '0' AND Match ='0' THEN Rx_Dma_Req <= '0';
ELSIF (Dsm = sOdd AND Rx_Ovr = '0')
OR (Dsm = sData AND Rx_Ovr = '0' AND F_Val = '1' AND Rx_Count(0) = '1') THEN Rx_Dma_Req <= '1';
ELSIF Rx_Dma_Ack = '1' THEN Rx_Dma_Req <= '0';
END IF;
END IF;
END PROCESS pRxControl;
Dma_Dout <= Rx_LatchL & Rx_LatchH; --Rx_LatchH & Rx_LatchL;
nRx_Int <= '1' WHEN Rx_Icnt = 0 OR Rx_Ie = '0' ELSE '0';
Rx_Idle <= '1' WHEN Sm_Rx = R_Idl ELSE '0';
Rx_Reg(15 DOWNTO 4) <= Rx_Ie & '0' & "0" & '0' & (Rx_Icnt(4) OR Rx_Icnt(3)) & Rx_Icnt(2 DOWNTO 0)
& Rx_On & "0" & Rx_Idle & Rx_Lost;
Rx_Reg( 3 DOWNTO 0) <= Rx_Desc;
bFilter: BLOCK
SIGNAL Ram_Addr : std_logic_vector( 7 DOWNTO 0);
SIGNAL Ram_BeH, Ram_BeL : std_logic_vector( 1 DOWNTO 0);
SIGNAL Ram_Wr : std_logic;
SIGNAL Filter_Addr : std_logic_vector( 6 DOWNTO 0);
SIGNAL Filter_Out_H, Filter_Out_L : std_logic_vector(31 DOWNTO 0);
ALIAS DIRON_0 : std_logic IS Filter_Out_H( 11);
ALIAS DIRON_1 : std_logic IS Filter_Out_H( 27);
ALIAS DIRON_2 : std_logic IS Filter_Out_L( 11);
ALIAS DIRON_3 : std_logic IS Filter_Out_L( 27);
ALIAS TX_0 : std_logic IS Filter_Out_H( 7);
ALIAS TX_1 : std_logic IS Filter_Out_H(23);
ALIAS TX_2 : std_logic IS Filter_Out_L( 7);
ALIAS TX_3 : std_logic IS Filter_Out_L(23);
ALIAS ON_0 : std_logic IS Filter_Out_H( 6);
ALIAS ON_1 : std_logic IS Filter_Out_H(22);
ALIAS ON_2 : std_logic IS Filter_Out_L( 6);
ALIAS ON_3 : std_logic IS Filter_Out_L(22);
ALIAS DESC_0 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_H( 3 DOWNTO 0);
ALIAS DESC_1 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_H(19 DOWNTO 16);
ALIAS DESC_2 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_L( 3 DOWNTO 0);
ALIAS DESC_3 : std_logic_vector( 3 DOWNTO 0) IS Filter_Out_L(19 DOWNTO 16);
SIGNAL Byte_Cnt : std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
SIGNAL Erg0, Erg1, Erg2, Erg3 : std_logic_vector( 7 DOWNTO 0);
SIGNAL Mat_Reg : std_logic_vector(15 DOWNTO 0);
SIGNAL Filt_Idx : std_logic_vector( 1 DOWNTO 0);
SIGNAL Mat_Sel : std_logic_vector( 3 DOWNTO 0);
SIGNAL M_Prio : std_logic_vector( 2 DOWNTO 0);
ALIAS Found : std_logic IS M_Prio(2);
BEGIN
Ram_Addr <= s_Adr(9 DOWNTO 8) & s_Adr(5 DOWNTO 1) & s_Adr(6);
Ram_Wr <= '1' WHEN s_nWr = '0' AND Sel_Ram = '1' AND s_Adr(10) = '0' ELSE '0';
Ram_BeH(1) <= '1' WHEN s_nWr = '1' OR (s_nBE(1) = '0' AND s_Adr( 7) = '0') ELSE '0';
Ram_BeH(0) <= '1' WHEN s_nWr = '1' OR (s_nBE(0) = '0' AND s_Adr( 7) = '0') ELSE '0';
Ram_BeL(1) <= '1' WHEN s_nWr = '1' OR (s_nBE(1) = '0' AND s_Adr( 7) = '1') ELSE '0';
Ram_BeL(0) <= '1' WHEN s_nWr = '1' OR (s_nBE(0) = '0' AND s_Adr( 7) = '1') ELSE '0';
Filter_Addr <= Dibl_Cnt & Byte_Cnt;
FiltRamH: ENTITY work.Dpr_16_32
GENERIC MAP(Simulate => Simulate)
PORT MAP ( CLKA => Clk, CLKB => Clk,
EnA => cActivated, EnB => cActivated,
BEA => Ram_BeH,
WEA => Ram_Wr,
ADDRA => Ram_Addr, ADDRB => Filter_Addr,
DIA => s_Din, DOB => Filter_Out_H
);
FiltRamL: ENTITY work.Dpr_16_32
GENERIC MAP(Simulate => Simulate)
PORT MAP ( CLKA => Clk, CLKB => Clk,
EnA => cActivated, EnB => cActivated,
BEA => Ram_BeL,
WEA => Ram_Wr,
ADDRA => Ram_Addr, ADDRB => Filter_Addr,
DIA => s_Din, DOB => Filter_Out_L
);
Erg0 <= (Rx_Buf XOR Filter_Out_H( 7 DOWNTO 0)) AND Filter_Out_H(15 DOWNTO 8);
Erg1 <= (Rx_Buf XOR Filter_Out_H(23 DOWNTO 16)) AND Filter_Out_H(31 DOWNTO 24);
Erg2 <= (Rx_Buf XOR Filter_Out_L( 7 DOWNTO 0)) AND Filter_Out_L(15 DOWNTO 8);
Erg3 <= (Rx_Buf XOR Filter_Out_L(23 DOWNTO 16)) AND Filter_Out_L(31 DOWNTO 24);
genMatSel: FOR i IN 0 TO 3 GENERATE
Mat_Sel(i) <= Mat_Reg( 0 + i) WHEN Filt_Idx = "00" ELSE
Mat_Reg( 4 + i) WHEN Filt_Idx = "01" ELSE
Mat_Reg( 8 + i) WHEN Filt_Idx = "10" ELSE
Mat_Reg(12 + i); -- WHEN Filt_Idx = "11";
END GENERATE;
M_Prio <= "000" WHEN Filt_Cmp = '0' OR Match = '1' ELSE
"100" WHEN Mat_Sel(0) = '1' AND On_0 = '1' AND (DIRON_0 = '0') ELSE
"101" WHEN Mat_Sel(1) = '1' AND On_1 = '1' AND (DIRON_1 = '0') ELSE
"110" WHEN Mat_Sel(2) = '1' AND On_2 = '1' AND (DIRON_2 = '0') ELSE
"111" WHEN Mat_Sel(3) = '1' AND On_3 = '1' AND (DIRON_3 = '0') ELSE
"000";
pFilter: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Filt_Idx <= "00"; Match <= '0';
Filt_Cmp <= '0'; Mat_Reg <= (OTHERS => '0'); Byte_Cnt <= (OTHERS =>'0');
Match_Desc <= (OTHERS => '0');Auto_Desc <= (OTHERS =>'0'); Answer_Tx <= '0';
ELSIF rising_edge( Clk ) THEN
Filt_Idx <= Dibl_Cnt;
IF Dibl_Cnt = "11" AND Rx_Count(5) = '0' THEN Byte_Cnt <= Rx_Count(Byte_Cnt'RANGE);
END IF;
IF Dsm = sTiml THEN Filt_Cmp <= '1';
ELSIF Rx_Dv = '0' OR (F_Val = '1' AND Rx_Count(5) = '1') THEN Filt_Cmp <= '0';
END IF;
IF Dsm = sTimL THEN Mat_Reg <= (OTHERS => '1');
ELSE
FOR i IN 0 TO 3 LOOP
IF Erg0 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 0) <= '0'; END IF;
IF Erg1 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 1) <= '0'; END IF;
IF Erg2 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 2) <= '0'; END IF;
IF Erg3 /= 0 AND conv_integer(Filt_Idx) = i THEN Mat_Reg(4*i + 3) <= '0'; END IF;
END LOOP;
END IF;
IF Dsm = sTimL THEN Match <= '0';
ELSIF Found = '1' THEN Match <= '1'; Match_Desc <= Filt_Idx & M_Prio(1 DOWNTO 0);
IF M_Prio(1 DOWNTO 0) = "00" THEN Answer_Tx <= TX_0; Auto_Desc <= DESC_0;
ELSIF M_Prio(1 DOWNTO 0) = "01" THEN Answer_Tx <= TX_1; Auto_Desc <= DESC_1;
ELSIF M_Prio(1 DOWNTO 0) = "10" THEN Answer_Tx <= TX_2; Auto_Desc <= DESC_2;
ELSIF M_Prio(1 DOWNTO 0) = "11" THEN Answer_Tx <= TX_3; Auto_Desc <= DESC_3;
END IF;
ELSIF F_End = '1' THEN Answer_Tx <= '0';
END IF;
END IF;
END PROCESS pFilter;
R_Req <= Answer_Tx WHEN F_End = '1' AND F_Err = '0' ELSE '0';
END BLOCK bFilter;
Sel_RxH <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '1' AND s_nBe(1) = '0' ELSE '0';
Sel_RxL <= '1' WHEN s_nWr = '0' AND Sel_Cont = '1' AND s_Adr(3) = '1' AND s_nBe(0) = '0' ELSE '0';
pRxRegs: PROCESS( Rst, Clk )
BEGIN
IF Rst = '1' THEN
Rx_Desc <= (OTHERS => '0'); Rx_On <= '0';
Rx_Ie <= '0'; Rx_Lost <= '0'; Rx_Icnt <= (OTHERS => '0'); RxInt <= '0'; Diag <= '0';
ELSIF rising_edge( Clk ) THEN
IF Sel_RxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Rx_Ie <= S_Din(15);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(15) = '1' THEN Rx_Ie <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(15) = '1' THEN Rx_Ie <= '0';
END IF;
END IF;
IF Sel_RxH = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Diag <= S_Din(12);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din(12) = '1' THEN Diag <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din(12) = '1' THEN Diag <= '0';
END IF;
END IF;
IF Sel_RxL = '1' THEN
IF s_Adr(2 DOWNTO 1) = "00" THEN Rx_On <= S_Din( 7);
ELSIF s_Adr(2 DOWNTO 1) = "01" AND S_Din( 7) = '1' THEN Rx_On <= '1';
ELSIF s_Adr(2 DOWNTO 1) = "10" AND S_Din( 7) = '1' THEN Rx_On <= '0';
END IF;
END IF;
IF Rx_Beg = '1' AND (RX_OWN = '0' OR Rx_On = '0') THEN Rx_Lost <= '1';
ELSIF Sel_RxL = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din( 4) = '1' THEN Rx_Lost <= '0';
END IF;
IF Sel_RxL = '1' AND s_Adr(2 DOWNTO 1) = "11" THEN Rx_Desc <= S_Din( 3 DOWNTO 0);
ELSIF Dsm = sLenW AND Desc_We = '1' THEN
IF Last_Desc = '1' THEN Rx_Desc <= x"0";
ELSE Rx_Desc <= Rx_Desc + 1;
END IF;
END IF;
IF Rx_Ie = '1' AND Desc_We = '1' AND Dsm = sStat THEN RxInt <= '1';
ELSE RxInt <= '0';
END IF;
IF Sel_RxH = '1' AND s_Adr(2 DOWNTO 1) = "10" AND S_Din(8) = '1'
AND Rx_Icnt /= 0 THEN Rx_Icnt <= Rx_Icnt - NOT RxInt;
ELSIF RxInt = '1' AND Rx_Icnt /= "11111" THEN Rx_Icnt <= Rx_Icnt + 1;
END IF;
END IF;
END PROCESS pRxRegs;
END BLOCK bRxDesc;
END BLOCK b_Full_Rx;
END ARCHITECTURE struct; | gpl-2.0 | 565268f355511e9aa1398d2b9621e913 | 0.530134 | 2.549033 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/uart_lite/vhdl_source/rx.vhd | 4 | 2,641 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Serial Receiver: 115200/8N1
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-- Created : Wed Apr 28, 2004
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity rx is
generic (clks_per_bit : integer := 434); -- 115k2 @ 50 MHz
port (
clk : in std_logic;
reset : in std_logic;
rxd : in std_logic;
rxchar : out std_logic_vector(7 downto 0);
rx_ack : out std_logic );
end rx;
architecture gideon of rx is
signal bitcnt : integer range 0 to 8;
signal bitvec : std_logic_vector(8 downto 0);
signal timer : integer range 0 to clks_per_bit;
type state_t is (Idle, StartBit, Receiving);
signal state : state_t;
signal rxd_c : std_logic;
begin
process(clk, reset)
begin
if clk'event and clk='1' then
rxd_c <= rxd;
rx_ack <= '0';
case state is
when Idle =>
if rxd_c = '0' then
timer <= (clks_per_bit / 2) - 1;
state <= startbit;
end if;
when StartBit =>
if rxd_c = '1' then
state <= Idle;
elsif timer = 0 then
timer <= clks_per_bit - 1;
state <= receiving;
bitcnt <= 8;
else
timer <= timer - 1;
end if;
when Receiving =>
if timer=0 then
timer <= clks_per_bit - 1;
bitvec <= rxd_c & bitvec(8 downto 1);
if bitcnt = 0 then
state <= Idle;
rx_ack <= '1';
else
bitcnt <= bitcnt - 1;
end if;
else
timer <= timer - 1;
end if;
end case;
end if;
if reset='1' then
state <= Idle;
bitcnt <= 0;
timer <= 0;
bitvec <= (others => '0');
end if;
end process;
rxchar <= bitvec(7 downto 0);
end gideon;
| gpl-3.0 | 798e87385f796752f7884e483931645a | 0.364635 | 4.775769 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/uart_lite/vhdl_sim/tb_rx.vhd | 5 | 2,848 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Testbench for Serial receiver: 115200/8N1
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-- Created : Wed Apr 28, 2004
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.conversion_pkg.all;
entity tb_rx is
end tb_rx;
architecture tb of tb_rx is
component tx is
generic (clks_per_bit : integer := 434);
port (
clk : in std_logic;
reset : in std_logic;
dotx : in std_logic;
txchar : in std_logic_vector(7 downto 0);
txd : out std_logic;
done : out std_logic );
end component;
component rx is
generic (clks_per_bit : integer := 434);
port (
clk : in std_logic;
reset : in std_logic;
rxd : in std_logic;
rxchar : out std_logic_vector(7 downto 0);
rx_ack : out std_logic );
end component;
signal clk : std_logic;
signal reset : std_logic;
signal dotx : std_logic;
signal txchar : std_logic_vector(7 downto 0);
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal txd : std_logic;
signal done : std_logic;
constant teststring : string := "Gideon is gek";
begin
ck: process
begin
clk <= '0'; wait for 10 ns;
clk <= '1'; wait for 10 ns;
end process;
test: process
begin
reset <= '1';
dotx <= '0';
txchar <= (others => '0');
wait for 80 ns;
reset <= '0';
wait until clk='1';
for i in teststring'range loop
txchar <= CharToStd(teststring(i));
dotx <= '1';
wait until clk='1';
dotx <= '0';
wait until clk='1';
while done='0' loop
wait until clk='1';
end loop;
end loop;
wait;
end process;
my_tx: tx
generic map (20)
port map (
clk => clk,
reset => reset,
dotx => dotx,
txchar => txchar,
txd => txd,
done => done );
my_rx: rx
generic map (20)
port map (
clk => clk,
reset => reset,
rxd => txd,
rxchar => rxchar,
rx_ack => rx_ack );
end tb;
| gpl-3.0 | 4718ce1928d7ca606b0eb77d75676263 | 0.415028 | 4.213018 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_source/ulpi_host.vhd | 3 | 27,625 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity ulpi_host is
port (
clock : in std_logic;
reset : in std_logic;
-- Descriptor RAM interface
descr_addr : out std_logic_vector(8 downto 0);
descr_rdata : in std_logic_vector(31 downto 0);
descr_wdata : out std_logic_vector(31 downto 0);
descr_en : out std_logic;
descr_we : out std_logic;
-- Buffer RAM interface
buf_addr : out std_logic_vector(10 downto 0);
buf_rdata : in std_logic_vector(7 downto 0);
buf_wdata : out std_logic_vector(7 downto 0);
buf_en : out std_logic;
buf_we : out std_logic;
-- Transmit Path Interface
tx_busy : in std_logic;
tx_ack : in std_logic;
-- Interface to send tokens and handshakes
send_token : out std_logic;
send_handsh : out std_logic;
tx_pid : out std_logic_vector(3 downto 0);
tx_token : out std_logic_vector(10 downto 0);
-- Interface to send data packets
send_data : out std_logic;
no_data : out std_logic;
user_data : out std_logic_vector(7 downto 0);
user_last : out std_logic;
user_valid : out std_logic;
user_next : in std_logic;
-- Interface to bus initialization unit
reset_done : in std_logic;
sof_enable : in std_logic;
scan_enable : in std_logic := '1';
speed : in std_logic_vector(1 downto 0);
abort : in std_logic;
-- Receive Path Interface
rx_pid : in std_logic_vector(3 downto 0);
rx_token : in std_logic_vector(10 downto 0);
valid_token : in std_logic;
valid_handsh : in std_logic;
valid_packet : in std_logic;
data_valid : in std_logic;
data_start : in std_logic;
data_out : in std_logic_vector(7 downto 0);
rx_error : in std_logic );
end ulpi_host;
architecture functional of ulpi_host is
signal frame_div : integer range 0 to 65535;
signal frame_cnt : unsigned(13 downto 0) := (others => '0');
signal do_sof : std_logic;
constant c_max_transaction : integer := 31;
constant c_max_pipe : integer := 31;
constant c_timeout_val : integer := 7167;
constant c_transaction_offset : unsigned(8 downto 6) := "001";
signal transaction_pntr : integer range 0 to c_max_transaction;
signal descr_addr_i : unsigned(8 downto 0); -- could be temporarily pipe addr
type t_state is (startup, idle, wait4start, scan_transactions, get_pipe,
handle_trans, setup_token, bulk_token, send_data_packet, get_status,
wait_for_ack, receive_data, send_ack, update_pipe, update_trans, do_ping );
signal state : t_state;
signal substate : integer range 0 to 7;
signal trans_in : t_transaction;
signal pipe_in : t_pipe;
signal trans_cnt : unsigned(10 downto 0);
signal trans_len : unsigned(10 downto 0);
signal buf_addr_i : unsigned(10 downto 0);
-- signal speed : std_logic_vector(1 downto 0) := "11";
signal no_data_i : boolean;
signal abort_reg : std_logic;
signal tx_put : std_logic;
signal tx_last : std_logic;
signal need_ping : std_logic;
signal fifo_data_in : std_logic_vector(7 downto 0);
signal tx_almost_full : std_logic;
signal link_busy : std_logic;
signal timeout : boolean;
signal timeout_cnt : integer range 0 to c_timeout_val;
signal first_transfer : boolean;
signal terminate : std_logic;
attribute fsm_encoding : string;
attribute fsm_encoding of state : signal is "sequential";
-- attribute keep : string;
-- attribute keep of timeout : signal is "true";
signal debug_count : integer range 0 to 1023 := 0;
signal debug_error : std_logic := '0';
begin
descr_addr <= std_logic_vector(descr_addr_i);
buf_addr <= std_logic_vector(buf_addr_i);
no_data <= '1' when no_data_i else '0';
buf_wdata <= data_out; -- should be rx_data
buf_we <= '1' when (state = receive_data) and (data_valid = '1') else '0';
p_protocol: process(clock)
procedure next_transaction is
begin
if terminate='1' then
terminate <= '0';
state <= idle;
elsif transaction_pntr = c_max_transaction then
transaction_pntr <= 0;
state <= idle; -- wait for next sof before rescan
else
transaction_pntr <= transaction_pntr + 1;
substate <= 0;
state <= scan_transactions;
end if;
end procedure;
function min(a, b: unsigned) return unsigned is
begin
if a < b then
return a;
else
return b;
end if;
end function;
variable trans_temp : t_transaction;
variable len : unsigned(trans_temp.transfer_length'range);
begin
if rising_edge(clock) then
descr_en <= '0';
descr_we <= '0';
tx_put <= '0';
if abort='1' then
abort_reg <= '1';
end if;
-- default counter
if substate /= 3 then
substate <= substate + 1;
end if;
if timeout_cnt /= 0 then
timeout_cnt <= timeout_cnt - 1;
if timeout_cnt = 1 then
timeout <= false;--true;
end if;
end if;
case state is
when startup =>
tx_pid <= c_pid_reserved;
do_sof <= '0';
frame_div <= 7499;
if reset_done='1' then
state <= idle;
if speed = "10" then
need_ping <= '1';
end if;
end if;
when idle =>
abort_reg <= '0';
if do_sof='1' then
do_sof <= '0';
tx_token <= std_logic_vector(frame_cnt(13 downto 3));
tx_pid <= c_pid_sof;
if speed = "00" then
send_handsh <= '1';
else
send_token <= '1';
end if;
if speed(1)='1' then
frame_cnt <= frame_cnt + 1;
else
frame_cnt <= frame_cnt + 8;
end if;
state <= wait4start;
end if;
when wait4start =>
if tx_ack='1' then
send_token <= '0';
send_handsh <= '0';
send_data <= '0'; -- redundant - will not come here
substate <= 0;
if scan_enable='1' then
state <= scan_transactions;
else
state <= idle;
end if;
end if;
when scan_transactions =>
case substate is
when 0 =>
descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr,
descr_addr_i'length-c_transaction_offset'length);
descr_en <= '1';
when 2 =>
trans_temp := data_to_t_transaction(descr_rdata);
trans_in <= trans_temp;
substate <= 0;
if trans_temp.state = busy then
state <= get_pipe;
else -- go for next, unless we are at the end of the list
next_transaction;
end if;
when others =>
null;
end case;
when get_pipe =>
case substate is
when 0 =>
descr_addr_i <= (others => '0');
descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer;
descr_en <= '1';
when 2 =>
pipe_in <= data_to_t_pipe(descr_rdata);
first_transfer <= true;
state <= handle_trans; ---
when others =>
null;
end case;
when handle_trans => -- both pipe and transaction records are now valid
abort_reg <= '0';
substate <= 0;
if do_sof='1' and link_busy='0' then
state <= idle;
elsif pipe_in.state /= initialized then -- can we use the pipe?
trans_in.state <= error;
state <= update_trans;
else -- yes we can
timeout <= false;
timeout_cnt <= c_timeout_val;
link_busy <= trans_in.link_to_next;
case trans_in.transaction_type is
when control =>
-- a control out sequence exists of a setup token
-- and then a data0 packet, which should be followed by
-- an ack from the device. The next phase of the transaction
-- could be either in or out, and defines whether it is a
-- control read or a control write.
-- By choice, control transfers are implemented using
-- two transactions, which are executed in guaranteed
-- sequence.
-- In this way, each stage has its own buffer.
-- Note, the first pipe should be of type OUT, although it is not
-- checked.
tx_pid <= c_pid_setup;
tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
send_token <= '1';
state <= setup_token;
when bulk | interrupt =>
tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
state <= bulk_token;
send_token <= '1';
timeout <= false;
timeout_cnt <= c_timeout_val;
if pipe_in.direction = dir_in then
tx_pid <= c_pid_in;
else
-- if need_ping='1' then
-- tx_pid <= c_pid_ping;
-- state <= do_ping;
-- else
tx_pid <= c_pid_out;
-- end if;
end if;
if pipe_in.control='1' and first_transfer then
pipe_in.data_toggle <= '1'; -- start with data 1
end if;
first_transfer <= false;
when others => -- not yet supported
trans_in.state <= error;
state <= update_trans;
end case;
end if;
when setup_token =>
if tx_ack='1' then
send_token <= '0';
tx_pid <= c_pid_data0; -- send setup data immediately
send_data <= '1';
buf_en <= '1';
substate <= 0;
state <= send_data_packet;
end if;
-- prepare buffer
buf_addr_i <= trans_in.buffer_address;
trans_len <= trans_in.transfer_length; -- not cut up
trans_cnt <= trans_in.transfer_length; -- not cut up
no_data_i <= (trans_in.transfer_length = 0);
when do_ping =>
if tx_ack='1' then
send_token <= '0';
end if;
-- wait for ack/nack or nyet.
if rx_error='1' then
trans_in.state <= error;
state <= update_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_handsh='1' then -- maybe an ack?
if rx_pid = c_pid_ack then
tx_pid <= c_pid_out;
send_token <= '1';
state <= bulk_token;
elsif rx_pid = c_pid_stall then
pipe_in.state <= stalled;
trans_in.state <= error;
state <= update_pipe;
elsif (rx_pid = c_pid_nak) or (rx_pid = c_pid_nyet) then
state <= handle_trans;
end if; -- all other pids are just ignored
elsif timeout then
state <= handle_trans;
end if;
when bulk_token =>
if tx_ack='1' then
send_token <= '0';
if pipe_in.direction = dir_out then
if pipe_in.data_toggle = '0' then
tx_pid <= c_pid_data0;
else
tx_pid <= c_pid_data1;
end if;
send_data <= '1';
buf_en <= '1';
substate <= 0;
state <= send_data_packet;
else -- input
timeout <= false;
timeout_cnt <= c_timeout_val;
state <= receive_data;
buf_en <= '1';
end if;
end if;
-- prepare buffer
buf_addr_i <= trans_in.buffer_address;
if pipe_in.direction = dir_out then
len := min(trans_in.transfer_length, pipe_in.max_transfer);
trans_len <= len; -- possibly cut up
trans_cnt <= len;
no_data_i <= (trans_in.transfer_length = 0);
else
trans_len <= (others => '0');
end if;
when send_data_packet =>
case substate is
when 0 =>
if tx_ack='1' then
send_data <= '0';
if no_data_i then
substate <= 2;
end if;
else
substate <= 0;
end if;
when 1 =>
substate <= 1; -- stay!
if tx_almost_full='0' then
tx_put <= '1';
buf_addr_i <= buf_addr_i + 1;
trans_cnt <= trans_cnt - 1;
if trans_cnt = 1 then
tx_last <= '1';
substate <= 2;
buf_en <= '0';
else
tx_last <= '0';
end if;
end if;
when 2 =>
if tx_busy='1' then
substate <= 2;
else
state <= wait_for_ack;
timeout <= false;
timeout_cnt <= c_timeout_val;
end if;
when others =>
null;
end case;
when wait_for_ack =>
if rx_error='1' then
trans_in.state <= error;
state <= update_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_handsh='1' then -- maybe an ack?
if (rx_pid = c_pid_ack) or (rx_pid = c_pid_nyet) then
if rx_pid = c_pid_nyet then
need_ping <= '1';
else
need_ping <= '0';
end if;
if trans_in.transfer_length = trans_len then
trans_in.state <= done;
if pipe_in.control='1' and trans_in.transaction_type = bulk then
state <= get_status;
substate <= 0;
else
state <= update_pipe;
end if;
else
trans_in.state <= busy;
state <= handle_trans;
end if;
trans_in.buffer_address <= buf_addr_i; -- store back
trans_in.transfer_length <= trans_in.transfer_length - trans_len;
pipe_in.data_toggle <= not pipe_in.data_toggle;
elsif rx_pid = c_pid_stall then
pipe_in.state <= stalled;
trans_in.state <= error;
state <= update_pipe;
elsif rx_pid = c_pid_nak then
terminate <= '0'; --link_busy; -- if control packet, then don't continue with next transaction!
state <= update_trans;
-- state <= handle_trans; -- just retry and retry, no matter what kind of packet it is, don't send SOF!
end if; -- all other pids are just ignored
-- elsif do_sof='1' then
-- state <= idle; -- test
elsif timeout then
pipe_in.timeout <= '1';
trans_in.state <= error;
state <= update_pipe;
-- state <= handle_trans; -- try again
end if;
when get_status =>
case substate is
when 0 =>
send_token <= '1';
tx_pid <= c_pid_in;
when 1 =>
if tx_ack='1' then
send_token <= '0';
timeout_cnt <= c_timeout_val;
timeout <= false;
else
substate <= 1; -- wait
end if;
when 2 =>
if valid_packet='1' or valid_handsh='1' then
state <= update_pipe; -- end transaction
elsif rx_error='1' or timeout then
trans_in.state <= error;
state <= update_pipe; -- end transaction
else
substate <= 2; -- wait
end if;
when others =>
null;
end case;
when receive_data =>
if data_valid = '1' then
timeout <= false;
timeout_cnt <= 0; -- does not occur anymore
buf_addr_i <= buf_addr_i + 1;
trans_len <= trans_len + 1;
end if;
--------------------------------------------------------------------
if rx_error = '1' or debug_error='1' then
-- go back to send the in token again
buf_en <= '0';
state <= handle_trans;
elsif abort_reg='1' then
pipe_in.state <= aborted;
state <= update_pipe;
abort_reg <= '0';
elsif valid_packet='1' then
buf_en <= '0';
trans_in.buffer_address <= buf_addr_i - 2; -- cut off CRC
trans_in.transfer_length <= trans_in.transfer_length - (trans_len - 2);
if ((trans_len - 2) >= trans_in.transfer_length) or
((trans_len - 2) < pipe_in.max_transfer) then
trans_in.state <= done;
else
trans_in.state <= busy;
end if;
state <= send_ack;
substate <= 0;
elsif valid_handsh='1' then
buf_en <= '0';
if rx_pid = c_pid_nak then
if pipe_in.control='1' then
state <= idle; -- retry on next sof, do not go to the next transaction
else
state <= update_trans; -- is not updated, but is the standard path to go to the next transact.
end if;
elsif rx_pid = c_pid_stall then
trans_in.state <= error;
pipe_in.state <= stalled;
state <= update_pipe;
end if;
elsif timeout then -- device doesn't answer, could it have missed my in token?
buf_en <= '0';
state <= handle_trans;
end if;
when send_ack =>
case substate is
when 0 =>
send_handsh <= '1';
tx_pid <= c_pid_ack;
when 1 =>
if tx_ack='0' then
substate <= 1; -- stay here.
else
send_handsh <= '0';
state <= update_trans;
-- if (pipe_in.control='0') and (trans_in.state = done) then
-- state <= update_trans;
-- elsif (pipe_in.control='1') and (trans_len = 2) then -- no data, thus status already received
-- state <= update_trans;
-- else
-- null;
-- -- substate <= 2;
-- end if;
end if;
-- when 2 => -- send status back (no data packet)
-- tx_pid <= c_pid_out;
-- tx_token <= pipe_in.device_endpoint & pipe_in.device_address;
-- send_token <= '1';
-- when 3 => -- wait until token was sent
-- if tx_ack='0' then
-- substate <= 3;
-- else
-- send_token <= '0';
-- no_data_i <= true;
-- send_data <= '1';
-- tx_pid <= c_pid_data1;
-- end if;
-- when 4 => -- wait until no data packet was processed
-- if tx_ack='0' then
-- substate <= 4;
-- else
-- send_data <= '0';
-- state <= update_trans;
-- end if;
when others =>
null;
end case;
when update_pipe =>
descr_addr_i <= (others => '0');
descr_addr_i(trans_in.pipe_pointer'range) <= trans_in.pipe_pointer;
descr_en <= '1';
descr_we <= '1';
descr_wdata <= t_pipe_to_data(pipe_in);
state <= update_trans;
when update_trans =>
descr_addr_i <= c_transaction_offset & to_unsigned(transaction_pntr,
descr_addr_i'length-c_transaction_offset'length);
descr_wdata <= t_transaction_to_data(trans_in);
descr_en <= '1';
descr_we <= '1';
next_transaction;
when others =>
null;
end case;
---------------------------------------------------
-- DEBUG
---------------------------------------------------
-- if state /= receive_data then
-- debug_count <= 0;
-- debug_error <= '0';
-- elsif debug_count = 1023 then
-- debug_error <= '1';
-- else
-- debug_count <= debug_count + 1;
-- end if;
---------------------------------------------------
if frame_div = 0 then
do_sof <= sof_enable;
if speed(1)='1' then
frame_div <= 7499; -- microframes
else
frame_div <= 59999; -- 1 ms frames
end if;
else
frame_div <= frame_div - 1;
end if;
if reset_done='0' then
state <= startup;
end if;
if speed /= "10" then -- If not high speed, then we force no ping
need_ping <= '0';
end if;
if reset = '1' then
abort_reg <= '0';
buf_en <= '0';
buf_addr_i <= (others => '0');
trans_len <= (others => '0');
trans_cnt <= (others => '0');
link_busy <= '0';
state <= startup;
do_sof <= '0';
frame_div <= 7499;
frame_cnt <= (others => '0');
send_token <= '0';
send_data <= '0';
send_handsh <= '0';
need_ping <= '0';
terminate <= '0';
end if;
end if;
end process;
-- Decoupling of ulpi tx bus and our generation of data
-- to meet timing of "next" signal
-- fifo_data_in <= reset_data when (state = startup) else buf_rdata;
fifo_data_in <= buf_rdata;
i_srl_tx: entity work.srl_fifo
generic map (
Width => 9,
Depth => 15,
Threshold => 10 )
port map (
clock => clock,
reset => reset,
GetElement => user_next,
PutElement => tx_put,
FlushFifo => '0',
DataIn(7 downto 0) => fifo_data_in,
DataIn(8) => tx_last,
DataOut(7 downto 0) => user_data,
DataOut(8) => user_last,
SpaceInFifo => open,
AlmostFull => tx_almost_full,
DataInFifo => user_valid );
end functional;
| gpl-3.0 | 9698f175c14fc626af49ec30f3b8d786 | 0.389321 | 4.702928 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/memory/vhdl_source/dpram_rdw.vhd | 5 | 4,658 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.tl_file_io_pkg.all;
entity dpram_rdw is
generic (
g_rdw_check : boolean := true;
g_width_bits : positive := 8;
g_depth_bits : positive := 10;
g_init_value : std_logic_vector := X"22";
g_init_file : string := "none";
g_init_width : integer := 1;
g_init_offset : integer := 0;
g_storage : string := "auto" -- can also be "block" or "distributed"
);
port (
clock : in std_logic;
a_address : in unsigned(g_depth_bits-1 downto 0);
a_rdata : out std_logic_vector(g_width_bits-1 downto 0);
a_en : in std_logic := '1';
b_address : in unsigned(g_depth_bits-1 downto 0);
b_rdata : out std_logic_vector(g_width_bits-1 downto 0);
b_wdata : in std_logic_vector(g_width_bits-1 downto 0) := (others => '0');
b_en : in std_logic := '1';
b_we : in std_logic := '0' );
-- attribute keep_hierarchy : string;
-- attribute keep_hierarchy of dpram_rdw : entity is "yes";
end entity;
architecture xilinx of dpram_rdw is
type t_ram is array(0 to 2**g_depth_bits-1) of std_logic_vector(g_width_bits-1 downto 0);
impure function read_file (filename : string; modulo : integer; offset : integer; ram_size : integer) return t_ram is
constant c_read_size : integer := (4 * modulo * ram_size) + offset;
variable mem : t_slv8_array(0 to c_read_size-1) := (others => (others => '0'));
variable result : t_ram := (others => g_init_value);
variable stat : file_open_status;
file myfile : text;
begin
if filename /= "none" then
file_open(stat, myfile, filename, read_mode);
assert (stat = open_ok)
report "Could not open file " & filename & " for reading."
severity failure;
read_hex_file_to_array(myfile, c_read_size, mem);
file_close(myfile);
if g_width_bits = 8 then
for i in 0 to ram_size-1 loop
result(i) := mem(i*modulo + offset);
end loop;
elsif g_width_bits = 16 then
for i in 0 to ram_size-1 loop
result(i)(15 downto 8) := mem(i*modulo*2 + offset);
result(i)( 7 downto 0) := mem(i*modulo*2 + offset + 1);
end loop;
elsif g_width_bits = 32 then
for i in 0 to ram_size-1 loop
result(i)(31 downto 24) := mem(i*modulo*4 + offset);
result(i)(23 downto 16) := mem(i*modulo*4 + offset + 1);
result(i)(15 downto 8) := mem(i*modulo*4 + offset + 2);
result(i)( 7 downto 0) := mem(i*modulo*4 + offset + 3);
end loop;
else
report "Unsupported width for initialization."
severity failure;
end if;
end if;
return result;
end function;
shared variable ram : t_ram := read_file(g_init_file, g_init_width, g_init_offset, 2**g_depth_bits);
-- shared variable ram : t_ram := (others => g_init_value);
signal a_rdata_i : std_logic_vector(a_rdata'range) := (others => '0');
signal b_wdata_d : std_logic_vector(b_wdata'range) := (others => '0');
signal rdw_hazzard : std_logic := '0';
-- Xilinx and Altera attributes
attribute ram_style : string;
attribute ram_style of ram : variable is g_storage;
begin
p_ports: process(clock)
begin
if rising_edge(clock) then
if a_en = '1' then
a_rdata_i <= ram(to_integer(a_address));
rdw_hazzard <= '0';
end if;
if b_en = '1' then
if b_we = '1' then
ram(to_integer(b_address)) := b_wdata;
if a_en='1' and (a_address = b_address) and g_rdw_check then
b_wdata_d <= b_wdata;
rdw_hazzard <= '1';
end if;
end if;
b_rdata <= ram(to_integer(b_address));
end if;
end if;
end process;
a_rdata <= a_rdata_i when rdw_hazzard='0' else b_wdata_d;
end architecture;
| gpl-3.0 | 79b525fbb7a6d4b4fcd176939319603d | 0.48948 | 3.682213 | false | false | false | false |
chrismasters/fpga-space-invaders | project/alu.vhd | 1 | 2,751 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity alu is
Port (
clk : in STD_LOGIC;
operandA : in STD_LOGIC_VECTOR (7 downto 0);
operandB : in STD_LOGIC_VECTOR (7 downto 0);
operatorSelect : in STD_LOGIC_VECTOR (2 downto 0);
carryIn : in STD_LOGIC;
carryOut : out STD_LOGIC;
zeroOut : out STD_LOGIC;
signOut : out STD_LOGIC;
parityOut : out STD_LOGIC;
auxCarryOut : out STD_LOGIC;
result : out STD_LOGIC_VECTOR (7 downto 0)
);
end alu;
architecture Behavioral of alu is
begin
procloop:
process (clk)
variable tempResult : std_logic_vector(8 downto 0);
begin
--if (rising_edge(clk)) then -- not sure this needs to be clocked really
if (falling_edge(clk)) then -- not sure this needs to be clocked really
auxCarryOut <= '0';
carryOut <= '0';
if (operatorSelect(2 downto 1) = "00") then -- add / add with carry
tempResult := std_logic_vector(signed(operandA(7) & operandA) + signed(operandB(7) & operandB));
--auxCarryOut <= (((operandA(3 downto 0) + operandB(3 downto 0)) >> 4 and 1
if ((operatorSelect(0) and carryIn) = '1') then
tempResult := std_logic_vector(signed(tempResult) + 1);
end if;
carryOut <= tempResult(8);
result <= tempResult(7 downto 0);
-- auxcar = (((opra[3:0]+oprb[3:0]) >> 4) & 1'b1) ? 1'b1 : 1'b0 ;
-- auxcar = (((opra[3:0]+oprb[3:0]+cin) >> 4) & 1'b1) ? 1'b1 : 1'b0;
auxCarryOut <= '0';
elsif (operatorSelect(2 downto 1) = "01") then -- sub / sub with borrow
tempResult := std_logic_vector(signed(operandA(7) & operandA) - signed(operandB(7) & operandB));
if ((operatorSelect(0) and carryIn) = '1') then
tempResult := std_logic_vector(signed(tempResult) - 1);
end if;
carryOut <= tempResult(8);
result <= tempResult(7 downto 0);
auxCarryOut <= '0';
elsif (operatorSelect = "100") then -- and
tempResult := "0" & (operandA and operandB);
result <= operandA and operandB;
elsif (operatorSelect = "101") then -- xor
tempResult := "0" & (operandA xor operandB);
result <= operandA xor operandB;
elsif (operatorSelect = "110") then -- or
tempResult := "0" & (operandA or operandB);
result <= operandA or operandB;
else -- "111" -- compare
tempResult := std_logic_vector(signed(operandA(7) & operandA) - signed(operandB(7) & operandB));
carryOut <= tempResult(8);
result <= operandA; --tempResult(7 downto 0);
auxCarryOut <= '0';
end if;
if (signed(tempResult) = 0) then
zeroOut <= '1';
else
zeroOut <= '0';
end if;
signOut <= tempResult(7);
parityOut <= not (tempResult(7) xor tempResult(6) xor tempResult(5) xor tempResult(4) xor tempResult(3) xor tempResult(2) xor tempResult(1) xor tempResult(0));
end if;
end process;
end Behavioral;
| mit | 1dc5902c3800370128c217b5eff856c7 | 0.647037 | 2.942246 | false | false | false | false |
gauravks/i210dummy | Examples/xilinx_microblaze/ipcore/powerlink/pcores/plb_powerlink_v1_00_a/hdl/vhdl/pdi_dpr_Xilinx.vhd | 2 | 3,626 | ------------------------------------------------------------------------------------------------------------------------
-- Process Data Interface (PDI) DPR for Xilinx
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-11-17 V0.01 zelenkaj First version
-- 2011-12-06 V0.02 zelenkaj Uses openMAC DPR implementation
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY pdi_dpr IS
GENERIC
(
NUM_WORDS : INTEGER := 1024;
LOG2_NUM_WORDS : INTEGER := 10
);
PORT
(
address_a : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (LOG2_NUM_WORDS-1 DOWNTO 0);
byteena_a : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
byteena_b : IN STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '1');
clock_a : IN STD_LOGIC := '1';
clock_b : IN STD_LOGIC ;
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END pdi_dpr;
architecture struct of pdi_dpr is
constant cActivated : std_logic := '1';
begin
abuseMacDpr : entity work.dc_dpr_be
generic map (
gDoInit => true,
WIDTH => data_a'length,
SIZE => NUM_WORDS,
ADDRWIDTH => LOG2_NUM_WORDS
)
port map (
clkA => clock_a, clkB => clock_b,
enA => cActivated, enB => cActivated,
addrA => address_a, addrB => address_b,
diA => data_a, diB => data_b,
doA => q_a, doB => q_b,
weA => wren_a, weB => wren_b,
beA => byteena_a, beB => byteena_b
);
end architecture struct;
| gpl-2.0 | 902b79842a65d944daedbbcecad98487 | 0.585218 | 3.808824 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op337_5.vhdl | 1 | 5,277 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => out1,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | bfbd56473b35163a09039a8d24526e52 | 0.575895 | 3.126185 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op951_5.vhdl | 1 | 5,525 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net1,
G => vbias3,
S => net5
);
subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net5,
G => net1,
S => gnd
);
subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net6,
G => net1,
S => gnd
);
subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => vbias3,
S => net6
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net2,
G => vbias3,
S => net7
);
subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net7,
G => net2,
S => gnd
);
subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net8,
G => net2,
S => gnd
);
subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | a9f816f62c46bc02a1a9ebc49807b36b | 0.578462 | 3.144565 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/debug/vhdl_source/logic_analyzer.vhd | 5 | 5,134 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
entity logic_analyzer is
generic (
g_timer_div : positive := 50;
g_change_width : positive := 16;
g_data_length : positive := 4 );
port (
clock : in std_logic;
reset : in std_logic;
ev_dav : in std_logic;
ev_data : in std_logic_vector(g_data_length*8-1 downto 0);
---
mem_req : out t_mem_req;
mem_resp : in t_mem_resp;
io_req : in t_io_req;
io_resp : out t_io_resp );
end logic_analyzer;
architecture gideon of logic_analyzer is
signal enable_log : std_logic;
signal ev_timer : integer range 0 to g_timer_div-1;
signal ev_tick : std_logic;
signal ev_data_c : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_data_d : std_logic_vector(g_data_length*8-1 downto 0);
signal ev_wdata : std_logic_vector((g_data_length+2)*8 -1 downto 0);
signal ev_addr : unsigned(23 downto 0);
signal stamp : unsigned(14 downto 0);
signal cnt : integer range 0 to g_data_length+1;
type t_state is (idle, writing);
signal state : t_state;
begin
process(clock)
begin
if rising_edge(clock) then
if ev_timer = 0 then
ev_tick <= '1';
ev_timer <= g_timer_div - 1;
else
ev_tick <= '0';
ev_timer <= ev_timer - 1;
end if;
if ev_tick = '1' then
if stamp /= 32766 then
stamp <= stamp + 1;
end if;
end if;
ev_data_c <= ev_data;
case state is
when idle =>
if enable_log = '1' then
if ev_dav='1' or ev_tick='1' then
if (ev_data_c(g_change_width-1 downto 0) /= ev_data_d(g_change_width-1 downto 0)) or (ev_dav = '1') then
ev_wdata <= ev_data_c & ev_dav & std_logic_vector(stamp);
stamp <= (others => '0');
cnt <= 0;
state <= writing;
end if;
if ev_tick='1' and ev_dav='0' then
ev_data_d <= ev_data_c;
end if;
end if;
end if;
when writing =>
mem_req.data <= ev_wdata(cnt*8+7 downto cnt*8);
mem_req.request <= '1';
if mem_resp.rack='1' and mem_resp.rack_tag=X"F0" then
ev_addr <= ev_addr + 1;
mem_req.request <= '0';
if (cnt = g_data_length+1) then
state <= idle;
else
cnt <= cnt + 1;
end if;
end if;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(2 downto 0) is
when "000" =>
io_resp.data <= std_logic_vector(ev_addr(7 downto 0));
when "001" =>
io_resp.data <= std_logic_vector(ev_addr(15 downto 8));
when "010" =>
io_resp.data <= std_logic_vector(ev_addr(23 downto 16));
when "011" =>
io_resp.data <= "00000001";
when "100" =>
io_resp.data <= std_logic_vector(to_unsigned(g_data_length+2, 8));
when others =>
null;
end case;
elsif io_req.write='1' then
io_resp.ack <= '1';
if io_req.data = X"33" then
ev_addr <= (others => '0');
ev_data_d <= (others => '0'); -- to trigger first entry
stamp <= (others => '0');
enable_log <= '1';
elsif io_req.data = X"44" then
enable_log <= '0';
end if;
end if;
if reset='1' then
state <= idle;
enable_log <= '0';
cnt <= 0;
ev_timer <= 0;
mem_req.request <= '0';
mem_req.data <= (others => '0');
ev_addr <= (others => '0');
stamp <= (others => '0');
ev_data_c <= (others => '0');
ev_data_d <= (others => '0');
end if;
end if;
end process;
mem_req.tag <= X"F0";
mem_req.address <= "01" & unsigned(ev_addr);
mem_req.read_writen <= '0'; -- write only
mem_req.size <= "00"; -- 1 byte at a time
end gideon;
| gpl-3.0 | 7e4a9de7bb3e84d870cae8248d11a991 | 0.404363 | 3.880574 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/sram_8bit32.vhd | 5 | 4,391 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Asynchronous SRAM Controller
-------------------------------------------------------------------------------
-- File : sram_8bit32.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access sram controller,
-- using an external 32-bit sram, and an internal 8 bit bus.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity sram_8bit32 is
generic (
tag_width : integer := 2;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1 ); -- recovery time (bus turnaround)
port (
clock : in std_logic := '0';
reset : in std_logic := '0';
req : in std_logic;
req_tag : in std_logic_vector(1 to tag_width) := (others => '0');
readwriten : in std_logic;
address : in std_logic_vector(19 downto 0);
rack : out std_logic;
dack : out std_logic;
rack_tag : out std_logic_vector(1 to tag_width);
dack_tag : out std_logic_vector(1 to tag_width);
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
--
SRAM_A : out std_logic_vector(17 downto 0);
SRAM_OEn : out std_logic;
SRAM_WEn : out std_logic;
SRAM_CSn : out std_logic;
SRAM_D : inout std_logic_vector(31 downto 0) := (others => 'Z');
SRAM_BEn : out std_logic_vector(3 downto 0) );
end sram_8bit32;
architecture mux of sram_8bit32 is
signal rdata_i : std_logic_vector(31 downto 0);
signal wdata_i : std_logic_vector(31 downto 0);
signal wdata_mask : std_logic_vector(3 downto 0);
signal a_low : std_logic_vector(1 downto 0);
signal rack_i : std_logic;
signal dack_i : std_logic;
begin
ctrl: entity work.simple_sram
generic map (
SRAM_Byte_Lanes => 4,
SRAM_Data_Width => 32,
SRAM_WR_ASU => SRAM_WR_ASU,
SRAM_WR_Pulse => SRAM_WR_Pulse,
SRAM_WR_Hold => SRAM_WR_Hold,
SRAM_RD_ASU => SRAM_RD_ASU,
SRAM_RD_Pulse => SRAM_RD_Pulse,
SRAM_RD_Hold => SRAM_RD_Hold,
SRAM_A_Width => 18 )
port map (
clock => clock,
reset => reset,
req => req,
req_tag => req_tag,
readwriten => readwriten,
address => address(19 downto 2),
rack => rack_i,
dack => dack_i,
rack_tag => rack_tag,
dack_tag => dack_tag,
wdata => wdata_i,
wdata_mask => wdata_mask,
rdata => rdata_i,
--
SRAM_A => SRAM_A,
SRAM_OEn => SRAM_OEn,
SRAM_WEn => SRAM_WEn,
SRAM_CSn => SRAM_CSn,
SRAM_D => SRAM_D,
SRAM_BEn => SRAM_BEn );
wdata_i <= wdata & wdata & wdata & wdata;
-- muxing:
process(clock)
variable hold : std_logic;
begin
if rising_edge(clock) then
if rack_i='1' then
hold := '1';
end if;
if dack_i='1' then
hold := '0';
end if;
if hold='0' then
a_low <= address(1 downto 0);
end if;
if reset='1' then
hold := '0';
a_low <= "00";
end if;
end if;
end process;
process(address)
begin
case address(1 downto 0) is
when "00" => wdata_mask <= "0001";
when "01" => wdata_mask <= "0010";
when "10" => wdata_mask <= "0100";
when "11" => wdata_mask <= "1000";
when others =>
wdata_mask <= "0000";
end case;
end process;
with a_low select rdata <=
rdata_i(07 downto 00) when "00",
rdata_i(15 downto 08) when "01",
rdata_i(23 downto 16) when "10",
rdata_i(31 downto 24) when others;
dack <= dack_i;
rack <= rack_i;
end mux;
| gpl-3.0 | 584f1d09d63d9d65c42b8b5cf9f404fb | 0.495104 | 3.247781 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_source/char_generator_slave.vhd | 4 | 5,630 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator
-------------------------------------------------------------------------------
-- File : char_generator_slave.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Character generator
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.char_generator_pkg.all;
entity char_generator_slave is
generic (
g_screen_size : natural := 11 );
port (
clock : in std_logic;
reset : in std_logic;
h_count : in unsigned(11 downto 0);
v_count : in unsigned(11 downto 0);
control : in t_chargen_control;
screen_addr : out unsigned(g_screen_size-1 downto 0);
screen_data : in std_logic_vector(7 downto 0);
color_data : in std_logic_vector(7 downto 0);
char_addr : out unsigned(10 downto 0);
char_data : in std_logic_vector(7 downto 0);
pixel_active : out std_logic;
pixel_opaque : out std_logic;
pixel_data : out unsigned(3 downto 0) );
end entity;
architecture gideon of char_generator_slave is
signal pointer : unsigned(g_screen_size-1 downto 0) := (others => '0');
signal char_x : unsigned(6 downto 0) := (others => '0');
signal char_y : unsigned(3 downto 0) := (others => '0');
signal char_y_d : unsigned(3 downto 0) := (others => '0');
signal pixel_count : unsigned(2 downto 0) := (others => '0');
signal remaining_lines : unsigned(5 downto 0) := (others => '0');
type t_state is (idle, active_line, draw);
signal state : t_state;
-- pipeline
signal color_data_d : std_logic_vector(7 downto 0);
signal active_d1 : std_logic;
signal pixel_sel_d1 : unsigned(2 downto 0);
signal active_d2 : std_logic;
signal pixel_sel_d2 : unsigned(2 downto 0);
begin
process(clock)
begin
if rising_edge(clock) then
active_d1 <= '0';
char_y_d <= char_y;
color_data_d <= color_data;
case state is
when idle =>
pointer <= control.pointer(pointer'range);
char_y <= (others => '0');
remaining_lines <= control.active_lines;
if v_count = control.y_on then
state <= active_line;
end if;
when active_line =>
char_x <= (others => '0');
pixel_count <= control.char_width;
if remaining_lines = 0 then
state <= idle;
elsif h_count = control.x_on then
state <= draw;
end if;
when draw =>
if pixel_count = 1 then
pixel_count <= control.char_width;
char_x <= char_x + 1;
if char_x = control.chars_per_line-1 then
state <= active_line;
char_x <= (others => '0');
if char_y = control.char_height-1 then
pointer <= pointer + control.chars_per_line;
char_y <= (others => '0');
remaining_lines <= remaining_lines - 1;
else
char_y <= char_y + 1;
end if;
end if;
else
pixel_count <= pixel_count - 1;
end if;
active_d1 <= '1';
when others =>
null;
end case;
-- pipeline forwards
pixel_sel_d1 <= pixel_count - 1;
pixel_sel_d2 <= pixel_sel_d1;
active_d2 <= active_d1;
-- pixel output
pixel_active <= active_d2;
if active_d2='1' then
if char_data(to_integer(pixel_sel_d2))='1' then
pixel_data <= unsigned(color_data_d(3 downto 0));
if color_data_d(3 downto 0) = control.transparent then
pixel_opaque <= '0';
else
pixel_opaque <= '1';
end if;
else
pixel_data <= unsigned(color_data_d(7 downto 4));
if color_data_d(7 downto 4) = control.transparent then
pixel_opaque <= '0';
else
pixel_opaque <= '1';
end if;
end if;
else
pixel_data <= (others => '0');
pixel_opaque <= '0';
end if;
if reset='1' then
state <= idle;
end if;
end if;
end process;
screen_addr <= pointer + char_x;
char_addr <= unsigned(screen_data) & char_y_d(2 downto 0) when char_y_d(3)='0' else
screen_data(7) & "0000000000";
end architecture;
| gpl-3.0 | 4549942a8d8ad0beb000f24bac90482a | 0.418117 | 4.401876 | false | false | false | false |
KB777/1541UltimateII | target/simulation/vhdl_bfm/bram_model_8sp.vhd | 5 | 2,053 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : BRAM model
-------------------------------------------------------------------------------
-- File : bram_model_8sp.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This simple BRAM model uses the flat memory model package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.tl_flat_memory_model_pkg.all;
entity bram_model_8sp is
generic (
g_given_name : string;
g_depth : positive := 18 );
port (
CLK : in std_logic;
SSR : in std_logic;
EN : in std_logic;
WE : in std_logic;
ADDR : in std_logic_vector(g_depth-1 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0) );
end bram_model_8sp;
architecture bfm of bram_model_8sp is
shared variable this : h_mem_object;
signal bound : boolean := false;
begin
bind: process
begin
register_mem_model(bram_model_8sp'path_name, g_given_name, this);
bound <= true;
wait;
end process;
process(CLK)
variable vaddr : std_logic_vector(31 downto 0) := (others => '0');
begin
if rising_edge(CLK) then
vaddr(g_depth-1 downto 0) := ADDR;
if EN='1' then
if bound then
DO <= read_memory_8(this, vaddr);
if WE='1' then
write_memory_8(this, vaddr, DI);
end if;
end if;
end if;
if SSR='1' then
DO <= (others => '0');
end if;
end if;
end process;
end bfm;
| gpl-3.0 | 27e078a185d7110e645fa079748e9421 | 0.425718 | 4.181263 | false | false | false | false |
multiple1902/xjtu_comp-org-lab | modules/alu/binary16.vhdl | 1 | 5,792 | -- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
package binary16 is
subtype binary16 is std_logic_vector(15 downto 0);
type binary16_ir is record -- the intermediate representation
sign: std_logic;
exponent: std_logic_vector(4 downto 0); -- offset-binary
significand: std_logic_vector(10 downto 0); -- no hidden bit, unsigned
end record;
function ieee754_binary16_iszero_ir(
i0: binary16_ir
) return boolean;
function ieee754_binary16_iszero(
i0: binary16
) return boolean;
constant ieee754_binary16_zero: std_logic_vector;
function ieee754_binary16_significand(
i0: binary16
) return std_logic_vector;
procedure ieee754_binary16_align(
variable i0, i1: inout binary16_ir
);
function ieee754_binary16_add(
i0, i1: binary16
) return binary16;
end;
package body binary16 is
function ieee754_binary16_getir(
i0: binary16
) return binary16_ir is
variable ret: binary16_ir;
begin
ret.sign := i0(15);
ret.exponent:=i0(14 downto 10);
if ieee754_binary16_iszero_ir(ret) then
ret.significand := "00000000000";
else
ret.significand(9 downto 0) := i0(9 downto 0);
ret.significand(10):='1';
end if;
return ret;
end;
function ieee754_binary16_getraw(
i0: binary16_ir
) return binary16 is
variable ret: binary16;
variable i0t: binary16_ir;
begin
i0t:=i0;
ret(15) := i0t.sign;
ret(14 downto 10) := i0t.exponent;
if ieee754_binary16_iszero_ir(i0t) then
ret(9 downto 0) := "0000000000";
else
while i0t.significand(9)/='1' and (ieee.std_logic_unsigned.">"(i0.exponent, "00010")) loop
-- no overflow
i0t.significand(10 downto 1) := i0t.significand(9 downto 0);
i0t.significand(0) := '0';
i0t.exponent := ieee.std_logic_unsigned."+"(i0t.exponent,1);
end loop;
ret(9 downto 0) := i0t.significand(9 downto 0);
end if;
return ret;
end;
function ieee754_binary16_iszero_ir(
i0: binary16_ir
) return boolean is
begin
return ieee.std_logic_unsigned."="(i0.exponent,"00000");
end;
function ieee754_binary16_iszero(
i0: binary16
) return boolean is
begin
return ieee.std_logic_unsigned."="(i0(14 downto 0),"000000000000000");
end;
constant ieee754_binary16_zero: std_logic_vector:="0000000000000000";
function ieee754_binary16_significand(
-- get the significand, or fraction
i0: binary16
) return std_logic_vector is
variable ret: std_logic_vector(11 downto 0);
-- 9 downto 0 : same as i0
-- 10 : 1 -- hidden bit
-- 11 : reserved
begin
ret(9 downto 0) := i0(9 downto 0);
ret(11 downto 10) := "01";
return(ret);
end;
procedure ieee754_binary16_align(
-- outputs may not be ieee754 qualified
variable i0, i1: inout binary16_ir
) is
begin
-- make the smaller one scale to the bigger one's exponent
while (ieee.std_logic_unsigned."<"(i0.exponent, i1.exponent)) and (ieee.std_logic_unsigned."<"(i0.exponent, "11111")) loop
-- no overflow
i0.significand(10 downto 1) := i0.significand(9 downto 0);
i0.significand(0) := '0';
i0.exponent := ieee.std_logic_unsigned."+"(i0.exponent,1);
end loop;
while (ieee.std_logic_unsigned."<"(i0.exponent, i1.exponent)) and (ieee.std_logic_unsigned."<"(i1.exponent, "11111")) loop
i0.significand(10 downto 1) := i0.significand(9 downto 0);
i1.significand(10 downto 1) := i1.significand(9 downto 0);
i1.significand(0) := '0';
i1.exponent := ieee.std_logic_unsigned."+"(i1.exponent,1);
end loop;
end;
function ieee754_binary16_add(
i0, i1: binary16
) return binary16 is
variable i0ir, i1ir: binary16_ir;
variable ret: binary16;
begin
i0ir := ieee754_binary16_getir(i0);
i1ir := ieee754_binary16_getir(i1);
-- Special Conditions Check
-- 1. if a1==0 and a2==0
-- result = 0
if ieee754_binary16_iszero(i0) and ieee754_binary16_iszero(i1) then
ret := ieee754_binary16_zero;
return ret;
end if;
-- 2. if a1==a2 but signs differ
-- ret = 0
if ieee.std_logic_unsigned."="(i0(14 downto 0),i1(14 downto 0)) and i0(15)/=i1(15) then
ret := ieee754_binary16_zero;
return ret;
end if;
-- 3. if a1==0 but a2<>0
-- ret = a1
if ieee754_binary16_iszero(i0) and not ieee754_binary16_iszero(i1) then
ret := i1;
return ret;
end if;
-- 4. if a1<>0 but a2==0
-- ret = a2
if not ieee754_binary16_iszero(i0) and ieee754_binary16_iszero(i1) then
ret := i0;
return ret;
end if;
-- No Special Conditions Matched
ieee754_binary16_align(i0ir, i1ir);
i0ir.significand := ieee.std_logic_unsigned."+"(i0ir.significand + i1ir.significand);
if i0ir.significand(10)='1' then
i0ir.exponent := ieee.std_logic_unsigned."-"(i0ir.exponent, 1);
i0ir.significand(9 downto 0):=i0ir.significand(10 downto 1);
i0ir.significand(10):='0';
end if;
end;
end package body;
| gpl-3.0 | a58c972b41ad54b3aa0a231b78c1aca9 | 0.571823 | 3.43128 | false | false | false | false |
daringer/schemmaker | testdata/hardest/circuit_op1.vhdl | 1 | 11,085 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity opfd is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal out2: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vref: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end opfd;
architecture simple of opfd is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "undef";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "undef";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "undef";
attribute SigDir of out2:terminal is "output";
attribute SigType of out2:terminal is "undef";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 6.75e-06,
W => Wdiff_0,
Wdiff_0init => 1.16e-05,
scope => private
)
port map(
D => net1,
G => in1,
S => net7
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 6.75e-06,
W => Wdiff_0,
Wdiff_0init => 1.16e-05,
scope => private
)
port map(
D => net2,
G => in2,
S => net7
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.2e-06,
W => W_0,
W_0init => 2.695e-05
)
port map(
D => net7,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 6.75e-06,
W => Wdiff_0,
Wdiff_0init => 1.16e-05,
scope => private
)
port map(
D => net8,
G => in1,
S => net7
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 6.75e-06,
W => Wdiff_0,
Wdiff_0init => 1.16e-05,
scope => private
)
port map(
D => net8,
G => in2,
S => net7
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.85e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1e-06,
scope => private
)
port map(
D => net8,
G => net8,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.85e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1e-06,
scope => private
)
port map(
D => net8,
G => net8,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.85e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1e-06,
scope => private
)
port map(
D => net1,
G => net8,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
Lcmdiffp_0init => 5.85e-06,
W => Wcmdiffp_0,
Wcmdiffp_0init => 1e-06,
scope => private
)
port map(
D => net2,
G => net8,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => L_2,
L_2init => 6.85e-06,
W => Wsrc_1,
Wsrc_1init => 2.365e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => L_3,
L_3init => 6.95e-06,
W => Wsrc_1,
Wsrc_1init => 2.365e-05,
scope => Wprivate,
symmetry_scope => sym_3
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7e-07,
W => Wcm_2,
Wcm_2init => 3.2e-06,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7e-07,
W => Wcmcout_2,
Wcmcout_2init => 2.235e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net5,
G => net3,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7e-07,
W => Wcm_2,
Wcm_2init => 3.2e-06,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7e-07,
W => Wcmcout_2,
Wcmcout_2init => 2.235e-05,
scope => private,
symmetry_scope => sym_4
)
port map(
D => net6,
G => net4,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcm_3,
Wcm_3init => 7.2e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcmout_3,
Wcmout_3init => 7.8e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net5,
S => vdd
);
subnet0_subnet6_m1 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcm_3,
Wcm_3init => 7.2e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net6,
S => vdd
);
subnet0_subnet6_m2 : entity pmos(behave)
generic map(
L => Lcm_3,
Lcm_3init => 3.5e-07,
W => Wcmout_3,
Wcmout_3init => 7.8e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out2,
G => net6,
S => vdd
);
subnet0_subnet7_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.2e-06,
W => Wcursrc_4,
Wcursrc_4init => 8.35e-06,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out1,
G => vbias4,
S => gnd
);
subnet0_subnet8_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.2e-06,
W => Wcursrc_4,
Wcursrc_4init => 8.35e-06,
scope => Wprivate,
symmetry_scope => sym_6
)
port map(
D => out2,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net9,
N => out1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 1e+07
)
port map(
P => net9,
N => out2
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net12,
N => vref
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => Ccmfb
)
port map(
P => net11,
N => net9
);
subnet1_subnet0_t1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7.2e-06,
W => W_1,
W_1init => 7.16e-05
)
port map(
D => net10,
G => vbias1,
S => vdd
);
subnet1_subnet0_t2 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 8.65e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 5.385e-05,
scope => private
)
port map(
D => net12,
G => vref,
S => net10
);
subnet1_subnet0_t3 : entity pmos(behave)
generic map(
L => Lcmdiff_0,
Lcmdiff_0init => 8.65e-06,
W => Wcmdiff_0,
Wcmdiff_0init => 5.385e-05,
scope => private
)
port map(
D => net11,
G => net9,
S => net10
);
subnet1_subnet0_t4 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 9.75e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1.3e-06,
scope => private
)
port map(
D => net11,
G => net11,
S => gnd
);
subnet1_subnet0_t5 : entity nmos(behave)
generic map(
L => Lcm_0,
Lcm_0init => 9.75e-06,
W => Wcmfbload_0,
Wcmfbload_0init => 1.3e-06,
scope => private
)
port map(
D => net12,
G => net11,
S => gnd
);
subnet1_subnet0_t6 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 1.45e-06,
W => Wcmbias_0,
Wcmbias_0init => 7.025e-05,
scope => private
)
port map(
D => out1,
G => net12,
S => gnd
);
subnet1_subnet0_t7 : entity nmos(behave)
generic map(
L => Lcmbias_0,
Lcmbias_0init => 1.45e-06,
W => Wcmbias_0,
Wcmbias_0init => 7.025e-05,
scope => private
)
port map(
D => out2,
G => net12,
S => gnd
);
subnet2_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 7.2e-06,
W => (pfak)*(WBias),
WBiasinit => 2.38e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet2_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7.2e-06,
W => (pfak)*(WBias),
WBiasinit => 2.38e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet2_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet2_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 7.2e-06,
W => WBias,
WBiasinit => 2.38e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet2_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.2e-06,
W => WBias,
WBiasinit => 2.38e-05
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet2_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.2e-06,
W => WBias,
WBiasinit => 2.38e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet2_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 7.2e-06,
W => WBias,
WBiasinit => 2.38e-05
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | fe9f0d83114cfebbd148f5d640b884d0 | 0.564637 | 2.790785 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/old/action_logic.vhd | 5 | 6,483 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity action_logic is
generic (
rom_base : std_logic_vector(27 downto 0) := X"1040000";
ram_base : std_logic_vector(27 downto 0) := X"0052000" );
port (
clock : in std_logic;
reset : in std_logic;
RSTn_in : in std_logic;
freeze_trig : in std_logic; -- goes '1' when the button has been pressed and we're waiting to enter the freezer
freeze_act : in std_logic; -- goes '1' when we need to switch in the cartridge for freeze mode
unfreeze : out std_logic; -- indicates the freeze logic to switch back to non-freeze mode.
cart_kill : in std_logic;
io_write : in std_logic;
io_addr : in std_logic_vector(8 downto 0);
io_data : in std_logic_vector(7 downto 0);
serve_enable : out std_logic; -- enables fetching bus address PHI2=1
serve_vic : out std_logic; -- enables doing so for PHI2=0
serve_rom : out std_logic; -- ROML or ROMH
serve_io1 : out std_logic; -- IO1n
serve_io2 : out std_logic; -- IO2n
allow_write : out std_logic;
slot_addr : in std_logic_vector(15 downto 0);
mem_addr : out std_logic_vector(25 downto 0);
-- debug
cart_mode : out std_logic_vector(7 downto 0);
irq_n : out std_logic;
nmi_n : out std_logic;
exrom_n : out std_logic;
game_n : out std_logic;
CART_LEDn : out std_logic );
end action_logic;
architecture gideon of action_logic is
signal reset_in : std_logic;
signal cart_ctrl : std_logic_vector(7 downto 0);
signal freeze_act_d : std_logic;
signal mode : std_logic_vector(2 downto 0);
signal cart_en : std_logic;
constant c_serve_rom : std_logic_vector(0 to 7) := "11011111";
constant c_serve_io2 : std_logic_vector(0 to 7) := "10101111";
begin
unfreeze <= cart_ctrl(6);
serve_enable <= cart_en;
process(clock)
begin
if rising_edge(clock) then
reset_in <= reset or not RSTn_in;
freeze_act_d <= freeze_act;
-- control register
if reset_in='1' or (freeze_act='1' and freeze_act_d='0') then -- either reset or freeze
cart_ctrl <= (others => '0');
elsif io_write='1' and io_addr(8 downto 1) = X"00" and cart_en='1' then -- IO1
cart_ctrl <= io_data;
end if;
-- Generate the cartridge mode
-- determine whether to serve io requests
if freeze_act='1' then
game_n <= '0';
exrom_n <= '1';
serve_io2 <= '0';
serve_rom <= '1';
else
game_n <= not mode(0);
exrom_n <= mode(1);
serve_io2 <= c_serve_io2(conv_integer(mode));
serve_rom <= c_serve_rom(conv_integer(mode));
end if;
if cart_kill='1' then
cart_ctrl(2) <= '1';
end if;
end if;
end process;
mode <= cart_ctrl(5) & cart_ctrl(1) & cart_ctrl(0);
cart_en <= not cart_ctrl(2);
CART_LEDn <= cart_ctrl(2);
irq_n <= not (freeze_trig or freeze_act);
nmi_n <= not (freeze_trig or freeze_act);
-- determine address
process(slot_addr, mode, cart_ctrl)
begin
allow_write <= '0';
if mode(2)='1' then
if slot_addr(13)='0' then
mem_addr <= ram_base(25 downto 13) & slot_addr(12 downto 0);
else
mem_addr <= rom_base(25 downto 15) & cart_ctrl(4 downto 3) & slot_addr(12 downto 0);
end if;
if slot_addr(15 downto 13)="100" or slot_addr(15 downto 8)=X"DF" then
allow_write <= '1';
end if;
else
mem_addr <= rom_base(25 downto 15) & cart_ctrl(4 downto 3) & slot_addr(12 downto 0);
end if;
end process;
cart_mode <= cart_ctrl;
serve_vic <= '0';
serve_io1 <= '0';
end gideon;
--Freeze:
--Always use ROM address, and respond to ROML/ROMH, but not to IO2n
--
--Non-freeze:
--
--Mode 0: Always use ROM address, let ROMLn and IO2n control the output
--Mode 1: Always use ROM address, let ROMLn (ROMhn?) but not IO2n control the output
--Mode 2: Always use ROM address, and let only IO2n control the output
--Mode 3: Always use ROM address, and let ROMLn / ROMHn, but not IO2n control the output
--
--Mode 4: Always use RAM address, and let ROMLn and IO2n control the output
--Mode 5: Use A13 to select between ROM/RAM (0=RAM, 1=ROM), let ROMLn/ROMHn and IO2n control the output (or write)
--Mode 6: Always use RAM address, let IO2n and ROMLn control the output
--Mode 7: Use A13 to select between ROM/RAM (0=RAM, 1=ROM), let ROMLn/ROMHn and IO2n control the output (or write)
--
--$0000-$1FFF: ROM --- 8K ROM|ROM --- 16K ROM|--- --- ----- |ROM --- UltiMax|--- --- 8K ROM|--- --- 16K ROM|--- --- ----- |--- --- UltiMax|
--$2000-$3FFF: ROM --- 8K ROM|ROM --- 16K ROM|--- --- ----- |ROM --- UltiMax|--- --- 8K ROM|--- --- 16K ROM|--- --- ----- |--- --- UltiMax|
--$4000-$5FFF: ROM --- 8K ROM|ROM --- 16K ROM|--- --- ----- |ROM --- UltiMax|--- --- 8K ROM|--- --- 16K ROM|--- --- ----- |--- --- UltiMax|
--$6000-$7FFF: ROM --- 8K ROM|ROM --- 16K ROM|--- --- ----- |ROM --- UltiMax|--- --- 8K ROM|--- --- 16K ROM|--- --- ----- |--- --- UltiMax|
--$8000-$9FFF: ROM --- 8K ROM|--- --- 16K ROM|--- --- ----- |ROM --- UltiMax|--- ram 8K ROM|--- ram 16K ROM|--- ram ----- |--- ram UltiMax|
--$A000-$BFFF: --- --- 8K ROM|ROM --- 16K ROM|--- --- ----- |--- --- UltiMax|--- --- 8K ROM|ROM --- 16K ROM|--- --- ----- |ROM --- UltiMax|
--$C000-$DFFF: --- --- 8K ROM|--- --- 16K ROM|--- --- ----- |--- --- UltiMax|--- --- 8K ROM|--- --- 16K ROM|--- --- ----- |--- --- UltiMax|
--$E000-$FFFF: --- --- 8K ROM|--- --- 16K ROM|--- --- ----- |ROM --- UltiMax|--- --- 8K ROM|--- --- 16K ROM|--- --- ----- |ROM --- UltiMax|
--
--$DF00-$DFFF: ROM --- 8K ROM|--- --- 16K ROM|ROM --- ----- |--- --- UltiMax|--- ram 8K ROM|--- ram 16K ROM|--- ram ----- |--- ram UltiMax| | gpl-3.0 | 612966313c8901b2cd2ac39f66ca3ffa | 0.506093 | 3.252885 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/cart_slot/vhdl_source/cart_slot_registers.vhd | 3 | 5,090 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.cart_slot_pkg.all;
entity cart_slot_registers is
generic (
g_rom_base : unsigned(27 downto 0) := X"0F80000";
g_ram_base : unsigned(27 downto 0) := X"0F70000";
g_ram_expansion : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_cart_control;
status : in t_cart_status );
end entity;
architecture rtl of cart_slot_registers is
signal control_i : t_cart_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
control_i.cartridge_kill <= '0';
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
if io_req.data(2)='1' then
control_i.c64_reset <= '1';
elsif io_req.data(3)='1' then
control_i.c64_reset <= '0';
else
control_i.c64_ultimax <= io_req.data(1);
control_i.c64_nmi <= io_req.data(4);
end if;
when c_cart_c64_stop =>
control_i.c64_stop <= io_req.data(0);
when c_cart_c64_stop_mode =>
control_i.c64_stop_mode <= io_req.data(1 downto 0);
when c_cart_cartridge_type =>
control_i.cartridge_type <= io_req.data(3 downto 0);
when c_cart_cartridge_kill =>
control_i.cartridge_kill <= '1';
when c_cart_kernal_enable =>
control_i.kernal_enable <= io_req.data(0);
when c_cart_reu_enable =>
control_i.reu_enable <= io_req.data(0);
when c_cart_reu_size =>
control_i.reu_size <= io_req.data(2 downto 0);
when c_cart_ethernet_enable =>
control_i.eth_enable <= io_req.data(0);
when c_cart_timing =>
control_i.timing_addr_valid <= unsigned(io_req.data(2 downto 0));
when c_cart_phi2_recover =>
control_i.phi2_edge_recover <= io_req.data(0);
when c_cart_swap_buttons =>
control_i.swap_buttons <= io_req.data(0);
when c_cart_sampler_enable =>
control_i.sampler_enable <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
io_resp.data(1) <= control_i.c64_ultimax;
io_resp.data(2) <= control_i.c64_reset;
io_resp.data(4) <= control_i.c64_nmi;
when c_cart_c64_stop =>
io_resp.data(0) <= control_i.c64_stop;
io_resp.data(1) <= status.c64_stopped;
when c_cart_c64_stop_mode =>
io_resp.data(1 downto 0) <= control_i.c64_stop_mode;
when c_cart_c64_clock_detect =>
io_resp.data(0) <= status.clock_detect;
when c_cart_cartridge_rom_base =>
io_resp.data <= std_logic_vector(g_rom_base(23 downto 16));
when c_cart_cartridge_type =>
io_resp.data(3 downto 0) <= control_i.cartridge_type;
when c_cart_kernal_enable =>
io_resp.data(0) <= control_i.kernal_enable;
when c_cart_reu_enable =>
io_resp.data(0) <= control_i.reu_enable;
when c_cart_reu_size =>
io_resp.data(2 downto 0) <= control_i.reu_size;
when c_cart_ethernet_enable =>
io_resp.data(0) <= control_i.eth_enable;
when c_cart_sampler_enable =>
io_resp.data(0) <= control_i.sampler_enable;
when c_cart_timing =>
io_resp.data(2 downto 0) <= std_logic_vector(control_i.timing_addr_valid);
when c_cart_phi2_recover =>
io_resp.data(0) <= control_i.phi2_edge_recover;
when c_cart_swap_buttons =>
io_resp.data(0) <= control_i.swap_buttons;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_cart_control_init;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | e887cdb655ff5ac04c17aba28d1a5d37 | 0.45501 | 3.609929 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/video/vhdl_source/char_generator_regs.vhd | 4 | 4,411 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Character Generator Registers
-------------------------------------------------------------------------------
-- File : char_generator_regs.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: Registers for the character generator
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.char_generator_pkg.all;
entity char_generator_regs is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
keyb_row : in std_logic_vector(7 downto 0);
keyb_col : inout std_logic_vector(7 downto 0);
control : out t_chargen_control );
end entity;
architecture gideon of char_generator_regs is
signal control_i : t_chargen_control := c_chargen_control_init;
begin
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_chargen_line_clocks_hi =>
control_i.clocks_per_line(10 downto 8) <= unsigned(io_req.data(2 downto 0));
when c_chargen_line_clocks_lo =>
control_i.clocks_per_line(7 downto 0) <= unsigned(io_req.data);
when c_chargen_char_width =>
control_i.char_width <= unsigned(io_req.data(2 downto 0));
when c_chargen_char_height =>
control_i.char_height <= unsigned(io_req.data(3 downto 0));
when c_chargen_chars_per_line =>
control_i.chars_per_line <= unsigned(io_req.data);
when c_chargen_active_lines =>
control_i.active_lines <= unsigned(io_req.data(5 downto 0));
when c_chargen_x_on_hi =>
control_i.x_on(11 downto 8) <= unsigned(io_req.data(3 downto 0));
when c_chargen_x_on_lo =>
control_i.x_on(7 downto 0) <= unsigned(io_req.data);
when c_chargen_y_on_hi =>
control_i.y_on(11 downto 8) <= unsigned(io_req.data(3 downto 0));
when c_chargen_y_on_lo =>
control_i.y_on(7 downto 0) <= unsigned(io_req.data);
when c_chargen_pointer_hi =>
control_i.pointer(14 downto 8) <= unsigned(io_req.data(6 downto 0));
when c_chargen_pointer_lo =>
control_i.pointer(7 downto 0) <= unsigned(io_req.data);
when c_chargen_perform_sync =>
control_i.perform_sync <= io_req.data(0);
when c_chargen_transparency =>
control_i.transparent <= io_req.data(3 downto 0);
control_i.overlay_on <= io_req.data(7);
when c_chargen_keyb_col =>
keyb_col <= io_req.data;
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_chargen_keyb_row =>
io_resp.data <= keyb_row;
when c_chargen_keyb_col =>
io_resp.data <= keyb_col;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_chargen_control_init;
keyb_col <= (others => '1');
end if;
end if;
end process;
control <= control_i;
end gideon;
| gpl-3.0 | 52caec926821f9eb716c67806e0e8808 | 0.428248 | 4.257722 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/1541/vhdl_bfm/iec_bus_bfm.vhd | 4 | 17,537 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library std;
use std.textio.all;
package iec_bus_bfm_pkg is
type t_iec_bus_bfm_object;
type p_iec_bus_bfm_object is access t_iec_bus_bfm_object;
type t_iec_status is (ok, no_devices, no_response, timeout, no_eoi_ack);
type t_iec_state is (idle, talker, listener);
type t_iec_command is (none, send_atn, send_msg, atn_to_listen);
type t_iec_data is array(natural range <>) of std_logic_vector(7 downto 0);
type t_iec_message is record
data : t_iec_data(0 to 256);
len : integer;
end record;
type t_iec_to_bfm is
record
command : t_iec_command;
end record;
type t_iec_from_bfm is
record
busy : boolean;
end record;
constant c_iec_to_bfm_init : t_iec_to_bfm := (
command => none );
constant c_iec_from_bfm_init : t_iec_from_bfm := (
busy => false );
type t_iec_bus_bfm_object is record
next_bfm : p_iec_bus_bfm_object;
name : string(1 to 256);
-- interface to the user
status : t_iec_status;
state : t_iec_state;
stopped : boolean;
sample_time : time;
-- buffer
msg_buf : t_iec_message;
-- internal to bfm
to_bfm : t_iec_to_bfm;
-- internal from bfm
from_bfm : t_iec_from_bfm;
end record;
constant c_atn_to_ckl : time := 5 us;
constant c_atn_resp_max : time := 1000 us;
constant c_non_eoi : time := 40 us;
constant c_clk_low : time := 50 us;
constant c_clk_high : time := 50 us;
constant c_frame_hs_max : time := 1000 us;
constant c_frame_release : time := 20 us;
constant c_byte_to_byte : time := 100 us;
constant c_eoi_min : time := 200 us;
constant c_eoi : time := 500 us; -- was 250
constant c_eoi_hold : time := 60 us;
constant c_tlkr_resp_dly : time := 60 us; -- max
constant c_talk_atn_rel : time := 30 us;
constant c_talk_atn_ack : time := 250 us; -- ?
------------------------------------------------------------------------------------
shared variable iec_bus_bfms : p_iec_bus_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_iec_bus_bfm(named : string; variable pntr: inout p_iec_bus_bfm_object);
procedure bind_iec_bus_bfm(named : string; variable pntr: inout p_iec_bus_bfm_object);
------------------------------------------------------------------------------------
procedure iec_stop(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_talk(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_listen(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_send_atn(variable bfm : inout p_iec_bus_bfm_object;
byte : std_logic_vector(7 downto 0));
procedure iec_turnaround(variable bfm : inout p_iec_bus_bfm_object);
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: t_iec_message);
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: string);
procedure iec_get_message(variable bfm : inout p_iec_bus_bfm_object;
variable msg : inout t_iec_message);
procedure iec_print_message(variable msg : inout t_iec_message);
end iec_bus_bfm_pkg;
package body iec_bus_bfm_pkg is
procedure register_iec_bus_bfm(named : string;
variable pntr : inout p_iec_bus_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_iec_bus_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
pntr.status := ok;
pntr.state := idle;
pntr.stopped := false; -- active;
pntr.sample_time := 1 us;
pntr.to_bfm := c_iec_to_bfm_init;
pntr.from_bfm := c_iec_from_bfm_init;
-- add this pointer to the head of the linked list
if iec_bus_bfms = null then -- first entry
iec_bus_bfms := pntr;
else -- insert new entry
pntr.next_bfm := iec_bus_bfms;
iec_bus_bfms := pntr;
end if;
end register_iec_bus_bfm;
procedure bind_iec_bus_bfm(named : string;
variable pntr : inout p_iec_bus_bfm_object) is
variable p : p_iec_bus_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := iec_bus_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_iec_bus_bfm;
------------------------------------------------------------------------------
procedure iec_stop(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.stopped := true;
end procedure;
procedure iec_talk(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.state := talker;
end procedure;
procedure iec_listen(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.state := listener;
end procedure;
procedure iec_send_atn(variable bfm : inout p_iec_bus_bfm_object;
byte : std_logic_vector(7 downto 0)) is
begin
bfm.msg_buf.data(0) := byte;
bfm.msg_buf.len := 1;
bfm.to_bfm.command := send_atn;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_turnaround(variable bfm : inout p_iec_bus_bfm_object) is
begin
bfm.to_bfm.command := atn_to_listen;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: t_iec_message) is
begin
bfm.msg_buf := msg;
bfm.to_bfm.command := send_msg;
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.from_bfm.busy loop
wait for bfm.sample_time;
end loop;
end procedure;
procedure iec_send_message(variable bfm : inout p_iec_bus_bfm_object;
msg: string) is
variable leng : integer;
begin
leng := msg'length;
for i in 1 to leng loop
bfm.msg_buf.data(i-1) := conv_std_logic_vector(character'pos(msg(i)), 8);
end loop;
bfm.msg_buf.len := leng;
iec_send_message(bfm, bfm.msg_buf);
end procedure;
procedure iec_get_message(variable bfm : inout p_iec_bus_bfm_object;
variable msg : inout t_iec_message) is
begin
wait for bfm.sample_time;
wait for bfm.sample_time;
while bfm.state = listener loop
wait for bfm.sample_time;
end loop;
msg := bfm.msg_buf;
end procedure;
procedure iec_print_message(variable msg : inout t_iec_message) is
variable L : line;
variable c : character;
begin
for i in 0 to msg.len-1 loop
c := character'val(conv_integer(msg.data(i)));
write(L, c);
end loop;
writeline(output, L);
end procedure;
end;
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith;
library work;
use work.iec_bus_bfm_pkg.all;
library std;
use std.textio.all;
entity iec_bus_bfm is
port (
iec_clock : inout std_logic;
iec_data : inout std_logic;
iec_atn : inout std_logic );
end iec_bus_bfm;
architecture bfm of iec_bus_bfm is
shared variable this : p_iec_bus_bfm_object := null;
signal bound : boolean := false;
signal clk_i : std_logic;
signal clk_o : std_logic;
signal data_i : std_logic;
signal data_o : std_logic;
signal atn_i : std_logic;
signal atn_o : std_logic;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_iec_bus_bfm(iec_bus_bfm'path_name, this);
bound <= true;
wait;
end process;
-- open collector logic
clk_i <= iec_clock and '1';
data_i <= iec_data and '1';
atn_i <= iec_atn and '1';
iec_clock <= '0' when clk_o='0' else 'H';
iec_data <= '0' when data_o='0' else 'H';
iec_atn <= '0' when atn_o='0' else 'H';
-- |<--------- Byte sent under attention (to devices) ------------>|
--
-- ___ ____ _____ _____
-- ATN |________________________________________________________|
-- : :
-- ___ ______ ________ ___ ___ ___ ___ ___ ___ ___ ___ :
-- CLK : |_____| |_| |_| |_| |_| |_| |_| |_| |_| |______________ _____
-- : : : : :
-- : Tat : :Th: Tne : : Tf : Tr :
-- ____ ________ : : :___________________________________:____:
-- DATA ___|\\\\\__:__| |__||__||__||__||__||__||__||__| |_________ _____
-- : 0 1 2 3 4 5 6 7 :
-- : LSB MSB :
-- : : :
-- : : Data Valid Listener: Data Accepted
-- : Listener READY-FOR-DATA
protocol: process
procedure do_send_atn is
begin
atn_o <= '0';
wait for c_atn_to_ckl;
clk_o <= '0';
if data_i='1' then
wait until data_i='0' for c_atn_resp_max;
end if;
if data_i='1' then
this.status := no_devices;
return;
end if;
clk_o <= '1';
wait until data_i='1'; -- for... (listener hold-off could be infinite)
wait for c_non_eoi;
for i in 0 to 7 loop
clk_o <= '0';
data_o <= this.msg_buf.data(0)(i);
wait for c_clk_low;
clk_o <= '1';
wait for c_clk_high;
end loop;
clk_o <= '0';
data_o <= '1';
wait until data_i='0' for c_frame_hs_max;
if data_i='1' then
this.status := no_response;
else
this.status := ok;
end if;
wait for c_frame_release;
atn_o <= '1';
end procedure;
procedure send_byte(byte : std_logic_vector(7 downto 0)) is
begin
clk_o <= '1';
wait until data_i='1'; -- for... (listener hold-off could be infinite)
wait for c_non_eoi;
for i in 0 to 7 loop
clk_o <= '0';
data_o <= byte(i);
wait for c_clk_low;
clk_o <= '1';
wait for c_clk_high;
end loop;
clk_o <= '0';
data_o <= '1';
wait until data_i='0' for c_frame_hs_max;
if data_i='1' then
this.status := no_response;
else
this.status := ok;
end if;
wait for c_byte_to_byte;
end procedure;
procedure end_handshake(byte : std_logic_vector(7 downto 0)) is
begin
clk_o <= '1';
wait until data_i='1'; -- for... (listener hold-off could be infinite)
-- wait for c_eoi;
-- data_o <= '0';
-- wait for c_eoi_hold;
-- data_o <= '1';
wait until data_i='0' for c_eoi; -- wait for 250 µs to see that listener has acked eoi
if data_i='1' then
this.status := no_eoi_ack;
return;
end if;
wait until data_i='1'; -- wait for listener to be ready again
wait for c_tlkr_resp_dly;
for i in 0 to 7 loop
clk_o <= '0';
data_o <= byte(i);
wait for c_clk_low;
clk_o <= '1';
wait for c_clk_high;
end loop;
clk_o <= '0';
data_o <= '1';
wait until data_i='0' for c_frame_hs_max;
if data_i='1' then
this.status := no_response;
else
this.status := ok;
end if;
end procedure;
procedure talk_atn_turnaround is
begin
wait for c_talk_atn_rel;
clk_o <= '1';
data_o <= '0';
wait for c_talk_atn_rel;
wait until clk_i = '0';
this.state := listener;
this.msg_buf.len := 0; -- clear buffer for incoming data
end procedure;
procedure receive_byte is
variable b : std_logic_vector(7 downto 0);
variable eoi : boolean;
variable c : character;
variable L : LINE;
begin
eoi := false;
if clk_i='0' then
wait until clk_i='1';
end if;
wait for c_clk_low; -- dummy
data_o <= '1';
-- check for end of message handshake (data pulses low after >200 µs for >60 µs)
wait until clk_i = '0' for c_eoi_min;
if clk_i='1' then -- eoi timeout
eoi := true;
-- ack eoi
data_o <= '0';
wait for c_eoi_hold;
data_o <= '1';
end if;
for i in 0 to 7 loop
wait until clk_i='1';
b(i) := data_i;
end loop;
-- c := character'val(conv_integer(b));
-- write(L, c);
-- writeline(output, L);
--
this.msg_buf.data(this.msg_buf.len) := b;
this.msg_buf.len := this.msg_buf.len + 1;
wait until clk_i='0';
if eoi then
this.state := idle;
data_o <= '1';
else
data_o <= '0';
end if;
end procedure;
begin
atn_o <= '1';
data_o <= '1';
clk_o <= '1';
wait until bound;
while not this.stopped loop
wait for this.sample_time;
case this.to_bfm.command is
when none =>
null;
when send_atn =>
this.from_bfm.busy := true;
do_send_atn;
this.from_bfm.busy := false;
when send_msg =>
this.from_bfm.busy := true;
if this.msg_buf.len > 1 then
L1: for i in 0 to this.msg_buf.len-2 loop
send_byte(this.msg_buf.data(i));
if this.status /= ok then
exit L1;
end if;
end loop;
end if;
assert this.status = ok
report "Sending data message failed."
severity error;
end_handshake(this.msg_buf.data(this.msg_buf.len-1));
assert this.status = ok
report "Sending data message failed (Last Byte)."
severity error;
this.from_bfm.busy := false;
when atn_to_listen =>
this.from_bfm.busy := true;
talk_atn_turnaround;
this.from_bfm.busy := false;
end case;
this.to_bfm.command := none;
if this.state = listener then
receive_byte;
end if;
end loop;
wait;
end process;
-- if in idle state, and atn_i becomes '0', then become device and listen
-- but that is only needed for devices... (not for the controller)
-- if listener (means that I am addressed), listen to all bytes
-- if end of message is detected, switch back to idle state.
end bfm;
| gpl-3.0 | 0155205827ec4c00f7fadcdeaa7ab21a | 0.446713 | 4.024094 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-mmc-a.vhd | 2 | 6,058 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Chip toplevel design with MMC feature set
--
-- $Id: chip-mmc-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture mmc of chip is
component spi_boot
generic (
width_set_sel_g : integer := 4;
width_bit_cnt_g : integer := 6;
width_img_cnt_g : integer := 2;
num_bits_per_img_g : integer := 18;
sd_init_g : integer := 0;
mmc_compat_clk_div_g : integer := 0;
width_mmc_clk_div_g : integer := 0;
reset_level_g : integer := 0
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0);
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
spi_en_outs_o : out std_logic;
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end component;
signal spi_clk_s : std_logic;
signal spi_cs_n_s : std_logic;
signal spi_data_out_s : std_logic;
signal spi_en_outs_s : std_logic;
signal set_sel_s : std_logic_vector(3 downto 0);
begin
set_sel_s <= not set_sel_n_i;
spi_boot_b : spi_boot
generic map (
width_set_sel_g => 4, -- 16 sets
width_bit_cnt_g => 12, -- 512 bytes per block
width_img_cnt_g => 2, -- 4 images
num_bits_per_img_g => 18, -- 256 kByte per image
sd_init_g => 0, -- no SD specific initialization
mmc_compat_clk_div_g => 13, -- MMC compat 400 kHz > 10 MHz / (13*2)
width_mmc_clk_div_g => 4 -- need 5 bits for MMC compat divider
)
port map (
clk_i => clk_i,
reset_i => reset_i,
set_sel_i => set_sel_s,
spi_clk_o => spi_clk_s,
spi_cs_n_o => spi_cs_n_s,
spi_data_in_i => spi_data_in_i,
spi_data_out_o => spi_data_out_s,
spi_en_outs_o => spi_en_outs_s,
start_i => start_i,
mode_i => mode_i,
config_n_o => config_n_o,
detached_o => detached_o,
cfg_init_n_i => cfg_init_n_i,
cfg_done_i => cfg_done_i,
dat_done_i => dat_done_i,
cfg_clk_o => cfg_clk_o,
cfg_dat_o => cfg_dat_o
);
-----------------------------------------------------------------------------
-- Three state drivers for SPI outputs.
-----------------------------------------------------------------------------
spi_clk_o <= spi_clk_s
when spi_en_outs_s = '1' else
'Z';
spi_cs_n_o <= spi_cs_n_s
when spi_en_outs_s = '1' else
'Z';
spi_data_out_o <= spi_data_out_s
when spi_en_outs_s = '1' else
'Z';
end mmc;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: chip-mmc-a.vhd,v $
-- Revision 1.6 2005/04/07 20:44:23 arniml
-- add new port detached_o
--
-- Revision 1.5 2005/03/09 19:48:34 arniml
-- invert level of set_sel input
--
-- Revision 1.4 2005/03/08 22:07:12 arniml
-- added set selection
--
-- Revision 1.3 2005/02/18 06:42:13 arniml
-- clarify wording for images
--
-- Revision 1.2 2005/02/16 18:54:39 arniml
-- added tri-state drivers for spi outputs
--
-- Revision 1.1 2005/02/08 20:41:32 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | ac28d575981884bd434dd0caf6266de2 | 0.538957 | 3.629718 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/lpm_divide0.vhd | 1 | 4,348 | -- megafunction wizard: %LPM_DIVIDE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_divide
-- ============================================================
-- File Name: lpm_divide0.vhd
-- Megafunction Name(s):
-- lpm_divide
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_divide0 IS
PORT
(
denom : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END lpm_divide0;
ARCHITECTURE SYN OF lpm_divide0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT lpm_divide
GENERIC (
lpm_drepresentation : STRING;
lpm_hint : STRING;
lpm_nrepresentation : STRING;
lpm_type : STRING;
lpm_widthd : NATURAL;
lpm_widthn : NATURAL
);
PORT (
denom : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
quotient <= sub_wire0(31 DOWNTO 0);
remain <= sub_wire1(9 DOWNTO 0);
lpm_divide_component : lpm_divide
GENERIC MAP (
lpm_drepresentation => "UNSIGNED",
lpm_hint => "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE",
lpm_nrepresentation => "UNSIGNED",
lpm_type => "LPM_DIVIDE",
lpm_widthd => 10,
lpm_widthn => 32
)
PORT MAP (
denom => denom,
numer => numer,
quotient => sub_wire0,
remain => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "6"
-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE"
-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "10"
-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
-- Retrieval info: USED_PORT: denom 0 0 10 0 INPUT NODEFVAL denom[9..0]
-- Retrieval info: USED_PORT: numer 0 0 32 0 INPUT NODEFVAL numer[31..0]
-- Retrieval info: USED_PORT: quotient 0 0 32 0 OUTPUT NODEFVAL quotient[31..0]
-- Retrieval info: USED_PORT: remain 0 0 10 0 OUTPUT NODEFVAL remain[9..0]
-- Retrieval info: CONNECT: @numer 0 0 32 0 numer 0 0 32 0
-- Retrieval info: CONNECT: @denom 0 0 10 0 denom 0 0 10 0
-- Retrieval info: CONNECT: quotient 0 0 32 0 @quotient 0 0 32 0
-- Retrieval info: CONNECT: remain 0 0 10 0 @remain 0 0 10 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divide0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divide0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divide0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divide0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divide0_inst.vhd TRUE
| gpl-2.0 | d5d8b1de339f8f9cdbb7d956eddd665b | 0.657314 | 3.647651 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_sim/tb_ulpi_tx.vhd | 3 | 5,761 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity tb_ulpi_tx is
end entity;
architecture tb of tb_ulpi_tx is
signal clock : std_logic := '0';
signal reset : std_logic;
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
signal tx_data : std_logic_vector(7 downto 0) := X"40";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '1';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_command : std_logic;
signal rx_register : std_logic;
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal status : std_logic_vector(7 downto 0);
signal busy : std_logic;
-- Interface to send tokens
signal send_handsh : std_logic := '0';
signal send_token : std_logic := '0';
signal pid : std_logic_vector(3 downto 0) := X"0";
signal token : std_logic_vector(10 downto 0) := (others => '0');
-- Interface to send data packets
signal send_data : std_logic := '0';
signal user_data : std_logic_vector(7 downto 0) := X"00";
signal user_last : std_logic := '0';
signal user_valid : std_logic := '0';
signal user_next : std_logic := '0';
-- Interface to read/write registers
signal read_reg : std_logic := '0';
signal write_reg : std_logic := '0';
signal address : std_logic_vector(5 downto 0) := (others => '0');
signal write_data : std_logic_vector(7 downto 0) := (others => '0');
signal read_data : std_logic_vector(7 downto 0) := (others => '0');
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
signal set : std_logic_vector(7 downto 0) := X"00";
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_tx: entity work.ulpi_tx
port map (
clock => clock,
reset => reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
rx_register => rx_register,
rx_data => rx_data,
-- Status
busy => busy,
-- Interface to send tokens
send_token => send_token,
send_handsh => send_handsh,
pid => pid,
token => token,
-- Interface to send data packets
send_data => send_data,
user_data => user_data,
user_last => user_last,
user_valid => user_valid,
user_next => user_next,
-- Interface to read/write registers
read_reg => read_reg,
write_reg => write_reg,
address => address,
write_data => write_data,
read_data => read_data );
i_bus: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_register => rx_register,
rx_last => rx_last,
rx_valid => rx_valid );
i_bfm: entity work.ulpi_phy_bfm
generic map (
g_rx_interval => 500 )
port map (
clock => clock,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
P_data: process(clock)
begin
if rising_edge(clock) then
if set /= X"00" then
user_data <= set;
elsif user_next='1' then
user_data <= std_logic_vector(unsigned(tx_data) + 1);
end if;
end if;
end process;
p_test: process
begin
wait until reset='0';
wait until clock='1';
write_data <= X"21";
address <= "010101";
write_reg <= '1';
wait until clock='1';
write_reg <= '0';
wait until busy='0';
wait until clock='1';
address <= "101010";
read_reg <= '1';
wait until clock='1';
read_reg <= '0';
wait until busy='0';
wait until clock='1';
pid <= c_pid_sof;
token <= "00101100011";
send_token <= '1';
wait until clock='1';
send_token <= '0';
wait until busy='0';
wait until clock='1';
send_data <= '1';
pid <= c_pid_data0;
wait until clock='1';
send_data <= '0';
wait until user_data = X"10";
user_last <= '1';
wait until clock = '1';
user_last <= '0';
wait until busy='0';
wait until clock='1';
pid <= c_pid_ack;
token <= "00101100011";
send_handsh <= '1';
wait until clock='1';
send_handsh <= '0';
wait;
end process;
end tb;
| gpl-3.0 | 2b626fef3f336d60d5996eb572a5848e | 0.470057 | 3.738482 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op956_4.vhdl | 2 | 5,277 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 8f822eb071f2f719e5e643c88aa941ff | 0.575895 | 3.126185 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op978_13.vhdl | 1 | 5,463 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net7
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net7,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net8,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net8
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net9
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net9,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | d5ce846f7508faed67cd4a4ce10d0c1d | 0.578071 | 3.145078 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/nano_cpu/vhdl_sim/usb_controller_tb.vhd | 5 | 2,518 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.mem_bus_pkg.all;
--use work.tl_string_util_pkg.all;
entity usb_controller_tb is
end usb_controller_tb;
architecture tb of usb_controller_tb is
signal clock_50 : std_logic := '0';
signal clock_60 : std_logic := '0';
signal reset : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
-- ULPI Interface
signal ULPI_DATA : std_logic_vector(7 downto 0);
signal ULPI_DIR : std_logic;
signal ULPI_NXT : std_logic;
signal ULPI_STP : std_logic;
-- LED interface
signal usb_busy : std_logic;
-- Memory interface
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp := c_mem_resp_init;
begin
clock_50 <= not clock_50 after 10 ns;
clock_60 <= not clock_60 after 8.3 ns;
reset <= '1', '0' after 100 ns;
i_io_bfm1: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock_50,
req => io_req,
resp => io_resp );
process
variable iom : p_io_bus_bfm_object;
variable stat : std_logic_vector(7 downto 0);
variable data : std_logic_vector(7 downto 0);
begin
wait for 1 us;
bind_io_bus_bfm("io_bfm", iom);
io_write(iom, X"1000", X"01"); -- enable core
wait;
end process;
i_phy: entity work.ulpi_phy_bfm
port map (
clock => clock_60,
reset => reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
i_mut: entity work.usb_controller
port map (
ulpi_clock => clock_60,
ulpi_reset => reset,
-- ULPI Interface
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
-- LED interface
usb_busy => usb_busy,
-- register interface bus
sys_clock => clock_50,
sys_reset => reset,
sys_mem_req => mem_req,
sys_mem_resp=> mem_resp,
sys_io_req => io_req,
sys_io_resp => io_resp );
end architecture;
| gpl-3.0 | ec75d0dd28a43036d0c591f641a539ac | 0.500794 | 3.458791 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_bfm/dma_bus_slave_bfm.vhd | 5 | 1,680 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_bus_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity dma_bus_slave_bfm is
generic (
g_name : string;
g_latency : positive := 2 );
port (
clock : in std_logic;
req : in t_dma_req;
resp : out t_dma_resp );
end dma_bus_slave_bfm;
architecture bfm of dma_bus_slave_bfm is
shared variable mem : h_mem_object;
signal bound : boolean := false;
signal pipe : t_dma_req_array(0 to g_latency-1) := (others => c_dma_req_init);
signal resp_i : t_dma_resp;
begin
-- this process registers this instance of the bfm to the server package
bind: process
begin
register_mem_model(dma_bus_slave_bfm'path_name, g_name, mem);
bound <= true;
wait;
end process;
resp <= resp_i;
process(clock)
begin
if rising_edge(clock) then
pipe(0 to g_latency-2) <= pipe(1 to g_latency-1);
pipe(g_latency-1) <= req;
if resp_i.rack='1' then
pipe(g_latency-1).request <= '0';
end if;
resp_i.data <= (others => '0');
resp_i.dack <= '0';
resp_i.rack <= '0';
if bound then
resp_i.rack <= req.request and not resp_i.rack;
if pipe(0).request='1' then
if pipe(0).read_writen='1' then
resp_i.data <= read_memory_8(mem, X"0000" & std_logic_vector(pipe(0).address));
resp_i.dack <= '1';
else
write_memory_8(mem, X"0000" & std_logic_vector(pipe(0).address), pipe(0).data);
end if;
end if;
end if;
end if;
end process;
end bfm;
| gpl-3.0 | 6b6e1d1390dbc2aab7ab50ba6762f903 | 0.566667 | 2.896552 | false | false | false | false |
tirfil/VhdI2CSlave | testbenches/tb_i2cdemo_long.vhd | 1 | 2,826 | --###############################
--# Project Name :
--# File :
--# Project :
--# Engineer :
--# Modification History
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
entity TB_I2CDEMO_LONG is
end TB_I2CDEMO_LONG;
architecture stimulus of TB_I2CDEMO_LONG is
-- COMPONENTS --
component I2CDEMO
port(
MCLK : in std_logic;
nRST : in std_logic;
SCL : inout std_logic;
SDA : inout std_logic
);
end component;
--
-- SIGNALS --
signal MCLK : std_logic;
signal nRST : std_logic;
signal SCL : std_logic;
signal SDA : std_logic;
--
signal RUNNING : std_logic := '1';
signal result : std_logic_vector(7 downto 0);
begin
-- PORT MAP --
I_I2CDEMO_0 : I2CDEMO
port map (
MCLK => MCLK,
nRST => nRST,
SCL => SCL,
SDA => SDA
);
--
CLOCK: process
begin
while (RUNNING = '1') loop
MCLK <= '1';
wait for 10 ns;
MCLK <= '0';
wait for 10 ns;
end loop;
wait;
end process CLOCK;
GO: process
procedure SendData(data : in std_logic_vector(7 downto 0)) is
variable d : std_logic_vector(7 downto 0);
begin
d := data;
SCL <= '0';
for i in 0 to 7 loop
if (d(7) = '1') then
SDA <= 'H';
else
SDA <= '0';
end if;
wait for 200 ns;
SCL <= 'H';
wait for 200 ns;
SCL <= '0';
d(7 downto 1) := d(6 downto 0);
wait for 200 ns;
end loop;
SDA <= 'H';
wait for 200 ns;
SCL <= 'H';
wait for 200 ns;
SCL <= '0';
wait for 200 ns;
end SendData;
procedure ReadData(nack: in std_logic) is
variable d: std_logic_vector(7 downto 0);
begin
SCL <= '0';
for i in 0 to 7 loop
d(7 downto 1) := d(6 downto 0);
wait for 200 ns;
SCL <= 'H';
d(0) := SDA;
wait for 200 ns;
SCL <= '0';
wait for 200 ns;
end loop;
SDA <= nack;
result <= d;
wait for 200 ns;
SCL <= 'H';
wait for 200 ns;
SCL <= '0';
wait for 200 ns;
SDA <= 'H';
end ReadData;
begin
result <= x"FF";
wait for 1 ns;
nRST <= '0';
SDA <= 'H';
SCL <= 'H';
wait for 1000 ns;
nRST <= '1';
SDA <= '0'; -- start
wait for 200 ns;
SendData(x"70"); -- 38 < 1 + write
SendData(x"FC"); -- address
SendData(x"20");
SendData(x"03");
SendData(x"19");
SendData(x"64");
SDA <= 'H';
wait for 200 ns;
SCL <= 'H';
wait for 200 ns;
SDA <= '0'; -- start2
wait for 200 ns;
SendData(x"70"); -- 38 < 1 + write
SendData(x"FC"); -- address
SDA <= 'H';
wait for 200 ns;
SCL <= 'H';
wait for 200 ns;
SDA <= '0'; -- start2
wait for 200 ns;
SendData(x"71"); -- 38 < 1 + read
ReadData('0'); -- ack
ReadData('0'); -- ack
ReadData('0'); -- ack
ReadData('1'); -- nack
SCL <= '1';
wait for 200 ns;
SDA <= '1'; -- stop
wait for 200 ns;
RUNNING <= '0';
wait;
end process GO;
end stimulus;
| gpl-3.0 | beced767dddba28fd200782b7266fa68 | 0.526893 | 2.626394 | false | false | false | false |
LMolr/switchone | src/switchone.vhd | 1 | 4,673 | library ieee;
use ieee.numeric_std.all;
library work;
package switchone_pkg is
end package;
use work.switchone_pkg.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SwitchOne is
generic(
PARAM_DELTA_ON : integer := 4;
PARAM_DELTA_ADJ : integer := 4;
PARAM_MAX_V : integer := 255;
PARAM_MIN_V : integer := 0;
PARAM_DEF_ON_V : integer := 127;
PARAM_ADJ_STEP : integer := 8
);
port(
IN_RST : in std_logic;
IN_CLK : in std_logic;
IN_BTN : in std_logic;
OUT_L : out std_logic;
OUT_V : out integer range PARAM_MIN_V to PARAM_MAX_V
);
end entity;
architecture A of SwitchOne is
type state_type is (SOff, TUp, SOn, TAdj, SAdj, AdjLck);
signal cur_state, nxt_state : state_type;
signal cur_t, nxt_t : integer range 0 to (PARAM_DELTA_ON + PARAM_DELTA_ADJ);
signal cur_v, nxt_v : integer range PARAM_MIN_V to PARAM_MAX_V;
signal cur_dir, nxt_dir : std_logic; -- 1 up, 0 down
begin
sync_state_update : process(IN_RST, IN_CLK) is
begin
if (IN_RST = '1') then
cur_state <= SOff;
cur_t <= 0;
cur_v <= PARAM_DEF_ON_V;
cur_dir <= '1';
elsif (rising_edge(IN_CLK)) then
cur_state <= nxt_state;
cur_t <= nxt_t;
cur_v <= nxt_v;
cur_dir <= nxt_dir;
end if;
end process;
state_fn : process(IN_BTN, cur_state, cur_t, cur_v, cur_dir) is
begin
-- defaults
nxt_state <= cur_state;
nxt_t <= cur_t;
nxt_v <= cur_v;
nxt_dir <= cur_dir;
case cur_state is
------------
when SOff =>
if (IN_BTN = '1') then
nxt_state <= TUp;
nxt_t <= cur_t + 1;
end if;
-----------
when TUp =>
if (IN_BTN = '1') then
if (cur_t = PARAM_DELTA_ON + PARAM_DELTA_ADJ) then
nxt_state <= SAdj;
nxt_t <= 0;
else
nxt_state <= TUp;
nxt_t <= cur_t + 1;
end if;
else
nxt_state <= SOn;
nxt_t <= 0;
end if;
-----------
when SOn =>
if (IN_BTN = '1') then
nxt_state <= TAdj;
nxt_t <= cur_t + 1;
else
nxt_state <= SOn;
nxt_t <= 0;
end if;
when TAdj =>
if (IN_BTN = '1') then
if (cur_t = PARAM_DELTA_ADJ) then
nxt_state <= SAdj;
nxt_t <= 0;
else
nxt_state <= TAdj;
nxt_t <= cur_t + 1;
end if;
else
nxt_state <= SOff;
nxt_t <= 0;
end if;
------------
when SAdj =>
if (IN_BTN = '1') then
nxt_state <= SAdj;
-- adjust V (brightness)
if (cur_dir = '1') then
-- V increase required
if (cur_v = PARAM_MAX_V) then
-- max reached : decrease V and invert direction
nxt_v <= PARAM_MAX_V - PARAM_ADJ_STEP;
nxt_dir <= '0';
-- lock adjust on max
nxt_state <= AdjLck;
elsif (cur_v >= PARAM_MAX_V - PARAM_ADJ_STEP) then
-- clamp V to max and invert
nxt_v <= PARAM_MAX_V;
nxt_dir <= '0';
-- lock adjust on max
nxt_state <= AdjLck;
else
-- increase V normally
nxt_v <= cur_v + PARAM_ADJ_STEP;
end if;
else
-- V decrease required
if (cur_v = PARAM_MIN_V) then
-- min reached : increase V and invert direction
nxt_v <= PARAM_MIN_V + PARAM_ADJ_STEP;
nxt_dir <= '1';
-- lock adjust on min
nxt_state <= AdjLck;
elsif (cur_v - PARAM_ADJ_STEP <= PARAM_MIN_V) then
-- clamp V to min and invert
nxt_v <= PARAM_MIN_V;
nxt_dir <= '1';
-- lock adjust on min
nxt_state <= AdjLck;
else
-- decrease V normally
nxt_v <= cur_v - PARAM_ADJ_STEP;
end if;
end if;
else
nxt_state <= SOn;
nxt_t <= 0;
-- invert V adjustment direction
nxt_dir <= NOT cur_dir;
end if;
--------------
when AdjLck =>
if (IN_BTN = '1') then
if (cur_t = PARAM_DELTA_ADJ) then
nxt_state <= SAdj;
nxt_t <= 0;
else
nxt_state <= AdjLck;
nxt_t <= cur_t + 1;
end if;
else
-- unlock
nxt_state <= SOn;
nxt_t <= 0;
end if;
--------------
when others =>
nxt_state <= SOff;
nxt_t <= 0;
nxt_v <= PARAM_DEF_ON_V;
end case;
end process;
-- out fns
out_fn : process(cur_state) is
begin
case cur_state is
when SOff =>
OUT_L <= '0';
when TUp =>
OUT_L <= '1';
when SOn =>
OUT_L <= '1';
when TAdj =>
OUT_L <= '1';
when SAdj =>
OUT_L <= '1';
when AdjLck =>
OUT_L <= '1';
when others =>
OUT_L <= '0';
end case;
end process;
OUT_V <= cur_v;
end architecture; | gpl-2.0 | 7fd63f3795657a990ec5baeb48a45155 | 0.501177 | 2.774941 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_sim/ext_mem_ctrl_v5_sdr_tb.vhd | 5 | 4,403 | -------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 2), externally 4x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity ext_mem_ctrl_v5_sdr_tb is
end ext_mem_ctrl_v5_sdr_tb;
architecture tb of ext_mem_ctrl_v5_sdr_tb is
signal clock : std_logic := '1';
signal clock_shifted : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic;
signal req : t_mem_burst_req;
signal resp : t_mem_burst_resp;
signal SDRAM_CLK : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CSn : std_logic := '1';
signal SDRAM_RASn : std_logic := '1';
signal SDRAM_CASn : std_logic := '1';
signal SDRAM_WEn : std_logic := '1';
signal SDRAM_DQM : std_logic := '0';
signal MEM_A : std_logic_vector(14 downto 0);
signal MEM_D : std_logic_vector(7 downto 0) := (others => 'Z');
signal logic_CLK : std_logic;
signal logic_CKE : std_logic;
signal logic_CSn : std_logic := '1';
signal logic_RASn : std_logic := '1';
signal logic_CASn : std_logic := '1';
signal logic_WEn : std_logic := '1';
signal logic_DQM : std_logic := '0';
signal Q : std_logic_vector(7 downto 0);
signal Qd : std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
clock_shifted <= transport clock after 15 ns; -- 270 degrees
reset <= '1', '0' after 100 ns;
i_mut: entity work.ext_mem_ctrl_v5_sdr
generic map (
g_simulation => true )
port map (
clock => clock,
clk_shifted => clock_shifted,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => logic_CLK,
SDRAM_CKE => logic_CKE,
SDRAM_CSn => logic_CSn,
SDRAM_RASn => logic_RASn,
SDRAM_CASn => logic_CASn,
SDRAM_WEn => logic_WEn,
SDRAM_DQM => logic_DQM,
MEM_A => MEM_A,
MEM_D => MEM_D );
SDRAM_CLK <= transport logic_CLK after 6 ns;
SDRAM_CKE <= transport logic_CKE after 6 ns;
SDRAM_CSn <= transport logic_CSn after 6 ns;
SDRAM_RASn <= transport logic_RASn after 6 ns;
SDRAM_CASn <= transport logic_CASn after 6 ns;
SDRAM_WEn <= transport logic_WEn after 6 ns;
SDRAM_DQM <= transport logic_DQM after 6 ns;
p_test: process
begin
req <= c_mem_burst_req_init;
wait until reset='0';
wait until clock='1';
req.read_writen <= '0'; -- write
-- req.read_writen <= '1'; -- read
req.request <= '1';
req.data_pop <= '1';
while true loop
wait until clock='1';
if resp.ready='1' then
req.address <= req.address + 4;
end if;
end loop;
wait;
end process;
p_read: process(SDRAM_CLK)
variable count : integer := 10;
begin
if rising_edge(SDRAM_CLK) then
if SDRAM_CSn='0' and SDRAM_RASn='1' and SDRAM_CASn='0' and SDRAM_WEn='1' then -- start read
count := 0;
end if;
case count is
when 0 =>
Q <= X"01";
when 1 =>
Q <= X"02";
when 2 =>
Q <= X"03";
when 3 =>
Q <= X"04";
when others =>
Q <= (others => 'Z');
end case;
Qd <= Q;
if Q(0)='Z' then
MEM_D <= Q after 3.6 ns;
else
MEM_D <= Q after 5.6 ns;
end if;
count := count + 1;
end if;
end process;
end;
| gpl-3.0 | 63d413e6837297b2fdb183c80630b33f | 0.459687 | 3.798965 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op972_9.vhdl | 1 | 5,009 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net6,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcursrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net1,
G => net5,
S => gnd
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => net6,
S => gnd
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net1,
G => vbias2,
S => net3
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net4,
G => net1,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net4
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net7
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net7,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 4d2b07dca003c113776a77b772267429 | 0.580954 | 3.180317 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/uart_lite/vhdl_source/tx.vhd | 4 | 2,804 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Serial Transmitter: 115200/8N1
-------------------------------------------------------------------------------
-- Author : Gideon Zweijtzer <[email protected]>
-- Created : Wed Apr 28, 2004
-------------------------------------------------------------------------------
-- Description: This module sends a character over a serial line
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tx is
generic (clks_per_bit : integer := 434); -- 115k2 @ 50 MHz
port (
clk : in std_logic;
reset : in std_logic;
dotx : in std_logic;
txchar : in std_logic_vector(7 downto 0);
cts : in std_logic := '1';
txd : out std_logic;
done : out std_logic );
end tx;
architecture gideon of tx is
signal bitcnt : integer range 0 to 9;
signal bitvec : std_logic_vector(8 downto 0);
signal timer : integer range 0 to clks_per_bit;
type state_t is (Idle, Waiting, Transmitting);
signal state : state_t;
signal cts_c : std_logic := '1';
begin
process(clk, reset)
begin
if rising_edge(clk) then
cts_c <= cts;
case state is
when Idle =>
if DoTx='1' then
if cts_c='1' then
state <= Transmitting;
else
state <= Waiting;
end if;
bitcnt <= 9;
bitvec <= not(txchar) & '1';
timer <= clks_per_bit - 1;
end if;
when Waiting =>
if cts_c='1' then
state <= Transmitting;
end if;
when Transmitting =>
if timer=0 then
timer <= clks_per_bit - 1;
if bitcnt = 0 then
state <= Idle;
else
bitcnt <= bitcnt - 1;
bitvec <= '0' & bitvec(8 downto 1);
end if;
else
timer <= timer - 1;
end if;
end case;
end if;
if reset='1' then
state <= Idle;
bitcnt <= 0;
timer <= 0;
bitvec <= (others => '0');
end if;
end process;
done <= '1' when state=Idle else '0';
txd <= not(bitvec(0));
end gideon;
| gpl-3.0 | 36efab545d033ad68086b87e706e7b61 | 0.373395 | 4.80137 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/zpu/vhdl_source/zpu_compare.vhd | 5 | 2,270 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- oper input can have the following values, producing the following results
-- 000 => false
-- 001 => a = b
-- 010 => false
-- 011 => a = b
-- 100 => a < b
-- 101 => a <= b
-- 110 => a < b (unsigned)
-- 111 => a <= b (unsigned)
entity zpu_compare is
port (
a : in unsigned(31 downto 0);
b : in unsigned(31 downto 0);
oper : in std_logic_vector(2 downto 0);
y : out boolean );
end zpu_compare;
architecture gideon of zpu_compare is
signal result : boolean;
signal equal : boolean;
signal ext_a : signed(32 downto 0);
signal ext_b : signed(32 downto 0);
begin
equal <= (a = b);
ext_a(32) <= not oper(1) and a(31); -- if oper(1) is 1, then we'll do an unsigned compare = signed compare with '0' in front.
ext_b(32) <= not oper(1) and b(31); -- if oper(1) is 0, when we'll do a signed compare = extended signed with sign bit.
ext_a(31 downto 0) <= signed(a);
ext_b(31 downto 0) <= signed(b);
result <= (ext_a < ext_b);
process(oper, result, equal)
variable r : boolean;
begin
r := false;
if oper(0)='1' then
r := r or equal;
end if;
if oper(2)='1' then
r := r or result;
end if;
y <= r;
end process;
end gideon;
-- constant OPCODE_LESSTHAN : unsigned(5 downto 0):=to_unsigned(36,6); -- 100100
-- constant OPCODE_LESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(37,6); -- 100101
-- constant OPCODE_ULESSTHAN : unsigned(5 downto 0):=to_unsigned(38,6); -- 100110
-- constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6); -- 100111
-- Note, the mapping is such, that for the opcodes above, the lower three bits of the opcode can be fed directly
-- into the compare unit.
-- constant OPCODE_EQ : unsigned(5 downto 0):=to_unsigned(46,6); -- 101110
-- constant OPCODE_NEQ : unsigned(5 downto 0):=to_unsigned(47,6); -- 101111
-- For these operations, the decoder must do extra work.
-- TODO: make a smarter mapping to support EQ and NEQ without external decoding.
| gpl-3.0 | 9b9b37af47a2dd17c430b40b7a5d6f3b | 0.580176 | 3.328446 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/tb_elem.vhd | 2 | 10,955 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Generic testbench element for a specific feature set
--
-- $Id: tb_elem.vhd,v 1.7 2005/04/07 20:43:36 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity tb_elem is
generic (
chip_type_g : string := "none";
has_sd_card_g : integer := 1
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
eos_o : out boolean
);
end tb_elem;
library ieee;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.spi_boot_pack.all;
use work.tb_pack.all;
architecture behav of tb_elem is
component chip
port (
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_n_i : in std_logic_vector(3 downto 0);
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end component;
component card
generic (
card_type_g : string := "none";
is_sd_card_g : integer := 1
);
port (
spi_clk_i : in std_logic;
spi_cs_n_i : in std_logic;
spi_data_i : in std_logic;
spi_data_o : out std_logic
);
end component;
signal reset_s : std_logic;
-- SPI interface signals
signal spi_clk_s : std_logic;
signal spi_data_to_card_s : std_logic;
signal spi_data_from_card_s : std_logic;
signal spi_cs_n_s : std_logic;
-- config related signals
signal start_s : std_logic;
signal mode_s : std_logic;
signal config_n_s : std_logic;
signal cfg_init_n_s : std_logic;
signal cfg_done_s : std_logic;
signal dat_done_s : std_logic;
signal cfg_clk_s : std_logic;
signal cfg_dat_s : std_logic;
signal data_s : unsigned(7 downto 0);
signal set_sel_n_s : std_logic_vector(3 downto 0);
constant verbose_c : boolean := false;
begin
-- weak pull-ups
spi_clk_s <= 'H';
spi_cs_n_s <= 'H';
spi_data_to_card_s <= 'H';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
dut_b : chip
port map (
clk_i => clk_i,
reset_i => reset_s,
set_sel_n_i => set_sel_n_s,
spi_clk_o => spi_clk_s,
spi_cs_n_o => spi_cs_n_s,
spi_data_in_i => spi_data_from_card_s,
spi_data_out_o => spi_data_to_card_s,
start_i => start_s,
mode_i => mode_s,
config_n_o => config_n_s,
detached_o => open,
cfg_init_n_i => cfg_init_n_s,
cfg_done_i => cfg_done_s,
dat_done_i => dat_done_s,
cfg_clk_o => cfg_clk_s,
cfg_dat_o => cfg_dat_s
);
card_b : card
generic map (
card_type_g => chip_type_g,
is_sd_card_g => has_sd_card_g
)
port map (
spi_clk_i => spi_clk_s,
spi_cs_n_i => spi_cs_n_s,
spi_data_i => spi_data_to_card_s,
spi_data_o => spi_data_from_card_s
);
-----------------------------------------------------------------------------
-- DUT Stimuli
--
stim: process
procedure rise_cfg_clk(num : integer) is
begin
for i in 1 to num loop
wait until cfg_clk_s'event and cfg_clk_s = '1';
end loop;
end rise_cfg_clk;
-- procedure fall_cfg_clk(num : integer) is
-- begin
-- for i in 1 to num loop
-- wait until cfg_clk_s'event and cfg_clk_s = '0';
-- end loop;
-- end fall_cfg_clk;
procedure rise_clk(num : integer) is
begin
for i in 1 to num loop
wait until clk_i'event and clk_i = '1';
end loop;
end rise_clk;
procedure read_check_byte(ref : unsigned(7 downto 0)) is
variable byte_v : unsigned(7 downto 0);
variable dump_line : line;
begin
for bit in 7 downto 0 loop
rise_cfg_clk(1);
byte_v(bit) := cfg_dat_s;
end loop;
data_s <= byte_v;
if byte_v /= ref then
write(dump_line, chip_type_g);
write(dump_line, string'(" at "));
write(dump_line, now);
write(dump_line, string'(": read_check_byte failed "));
write(dump_line, to_integer(byte_v));
write(dump_line, string'(" "));
write(dump_line, to_integer(ref));
writeline(output, dump_line);
end if;
end read_check_byte;
variable dump_line : line;
variable addr_v : unsigned(31 downto 0);
variable temp_v : unsigned( 7 downto 0);
variable set_sel_v : unsigned(3 downto 0);
begin
-- default assignments
-- these defaults show the required pull resistors
-- except start_i as this must be pulled high for automatic start
start_s <= '0';
mode_s <= '1';
cfg_init_n_s <= '1';
cfg_done_s <= '0';
dat_done_s <= '1';
data_s <= (others => '1');
addr_v := (others => '0');
eos_o <= false;
set_sel_n_s <= (others => '1');
reset_s <= '0';
-- loop through some sets
for set in 0 to 3 loop
set_sel_v := to_unsigned(set, 4);
addr_v(23 downto 20) := set_sel_v; -- must match num_bits_per_img_g
-- plus width_img_cnt_g
set_sel_n_s <= not std_logic_vector(set_sel_v);
assert not verbose_c
report chip_type_g & ": Processing set " & to_string(set)
severity note;
wait for 100 us;
reset_s <= '1';
assert not verbose_c
report chip_type_g & ": Requesting image 0"
severity note;
-- signal start
start_s <= '1';
mode_s <= '1';
cfg_done_s <= '0';
addr_v(19 downto 0) := (others => '0');
wait until config_n_s = '0';
-- run through configuration sequence
rise_clk(1);
cfg_init_n_s <= '0';
rise_clk(3);
cfg_init_n_s <= '1';
-- and receive 32 bytes from image 0
for i in 1 to 32 loop
temp_v := addr_v(0) & calc_crc(addr_v);
read_check_byte(temp_v);
addr_v := addr_v + 1;
end loop;
start_s <= '0';
cfg_done_s <= '1';
rise_clk(10);
assert not verbose_c
report chip_type_g & ": Requesting image 1"
severity note;
-- request next image
mode_s <= '0';
start_s <= '1';
addr_v(17 downto 0) := (others => '0');
addr_v(19 downto 18) := "01"; -- must match num_bits_per_img_g in chip-*-a.vhd
dat_done_s <= '0';
-- receive another 32 bytes from image 1
for i in 1 to 32 loop
temp_v := addr_v(0) & calc_crc(addr_v);
read_check_byte(temp_v);
addr_v := addr_v + 1;
end loop;
start_s <= '0';
dat_done_s <= '1';
rise_clk(10);
assert not verbose_c
report chip_type_g & ": Requesting image 2"
severity note;
-- request next image
mode_s <= '1';
start_s <= '1';
addr_v(17 downto 0) := (others => '0');
addr_v(19 downto 18) := "10"; -- must match num_bits_per_img_g in chip-*-a.vhd
wait until config_n_s = '0';
-- run through configuration sequence
rise_clk(1);
cfg_done_s <= '0';
cfg_init_n_s <= '0';
rise_clk(3);
cfg_init_n_s <= '1';
-- receive another 32 bytes from image 2
for i in 1 to 32 loop
temp_v := addr_v(0) & calc_crc(addr_v);
read_check_byte(temp_v);
addr_v := addr_v + 1;
end loop;
start_s <= '0';
cfg_done_s <= '1';
-- give dut a chance to stop current transfer
wait until spi_cs_n_s = '1';
rise_clk(10);
reset_s <= '0';
end loop;
eos_o <= true;
wait;
end process stim;
--
-----------------------------------------------------------------------------
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: tb_elem.vhd,v $
-- Revision 1.7 2005/04/07 20:43:36 arniml
-- add new port detached_o
--
-- Revision 1.6 2005/03/09 19:48:04 arniml
-- make verbosity level switchable
--
-- Revision 1.5 2005/03/08 22:06:21 arniml
-- added set selection
--
-- Revision 1.4 2005/02/17 18:59:23 arniml
-- clarify wording for images
--
-- Revision 1.3 2005/02/16 19:34:56 arniml
-- add weak pull-ups for SPI lines
--
-- Revision 1.2 2005/02/13 17:14:03 arniml
-- change dat_done handling
--
-- Revision 1.1 2005/02/08 21:09:20 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | 4cd9dea01b89e3e87e433ab2d5169898 | 0.538567 | 3.402174 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/zpu/core/zpupkg.vhd | 1 | 7,151 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
library work;
use work.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitIncIO-1;
constant ioBit : integer := maxAddrBit+1;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
component dualport_ram is
port (clk : in std_logic;
memAWriteEnable : in std_logic;
memAAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
memAWrite : in std_logic_vector(wordSize-1 downto 0);
memARead : out std_logic_vector(wordSize-1 downto 0);
memBWriteEnable : in std_logic;
memBAddr : in std_logic_vector(maxAddrBit downto minAddrBit);
memBWrite : in std_logic_vector(wordSize-1 downto 0);
memBRead : out std_logic_vector(wordSize-1 downto 0));
end component;
component dram is
port (clk : in std_logic;
areset : in std_logic;
mem_writeEnable : in std_logic;
mem_readEnable : in std_logic;
mem_addr : in std_logic_vector(maxAddrBit downto 0);
mem_write : in std_logic_vector(wordSize-1 downto 0);
mem_read : out std_logic_vector(wordSize-1 downto 0);
mem_busy : out std_logic;
mem_writeMask : in std_logic_vector(wordBytes-1 downto 0));
end component;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core is
port ( clk : in std_logic;
areset : in std_logic;
enable : in std_logic;
mem_req : out std_logic;
mem_we : out std_logic;
mem_ack : in std_logic;
mem_read : in std_logic_vector(wordSize-1 downto 0);
mem_write : out std_logic_vector(wordSize-1 downto 0);
out_mem_addr : out std_logic_vector(maxAddrBitIncIO downto 0);
mem_writeMask: out std_logic_vector(wordBytes-1 downto 0);
interrupt : in std_logic;
break : out std_logic;
zpu_status : out std_logic_vector(63 downto 0));
end component;
component timer is
port(
clk : in std_logic;
areset : in std_logic;
sample : in std_logic;
reset : in std_logic;
counter : out std_logic_vector(63 downto 0));
end component;
component zpuio is
port ( areset : in std_logic;
cpu_clk : in std_logic;
clk_status : in std_logic_vector(2 downto 0);
cpu_din : in std_logic_vector(15 downto 0);
cpu_a : in std_logic_vector(20 downto 0);
cpu_we : in std_logic_vector(1 downto 0);
cpu_re : in std_logic;
cpu_dout : inout std_logic_vector(15 downto 0));
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_Shiftleft: std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_PushInt : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_Compare : std_logic_vector(3 downto 0) := "1110";
constant OpCode_PopInt : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(36, 6);
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(37, 6);
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := conv_std_logic_vector(38, 6);
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := conv_std_logic_vector(39, 6);
constant OpCode_Swap : std_logic_vector(5 downto 0) := conv_std_logic_vector(40, 6);
constant OpCode_Mult : std_logic_vector(5 downto 0) := conv_std_logic_vector(41, 6);
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(42, 6);
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := conv_std_logic_vector(43, 6);
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := conv_std_logic_vector(44, 6);
constant OpCode_Call : std_logic_vector(5 downto 0) := conv_std_logic_vector(45, 6);
constant OpCode_Eq : std_logic_vector(5 downto 0) := conv_std_logic_vector(46, 6);
constant OpCode_Neq : std_logic_vector(5 downto 0) := conv_std_logic_vector(47, 6);
constant OpCode_Sub : std_logic_vector(5 downto 0) := conv_std_logic_vector(49, 6);
constant OpCode_Loadb : std_logic_vector(5 downto 0) := conv_std_logic_vector(51, 6);
constant OpCode_Storeb : std_logic_vector(5 downto 0) := conv_std_logic_vector(52, 6);
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(55, 6);
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := conv_std_logic_vector(56, 6);
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(57, 6);
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := conv_std_logic_vector(61, 6);
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := conv_std_logic_vector(62, 6);
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := conv_std_logic_vector(63, 6);
constant OpCode_Size : integer := 8;
end zpupkg;
| gpl-2.0 | e88c49310a07a9bb4e22b95399dc7dee | 0.662984 | 2.930738 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/altaccumulate0.vhd | 1 | 4,654 | -- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: altaccumulate0.vhd
-- Megafunction Name(s):
-- altaccumulate
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2006 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY altaccumulate0 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
cout : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END altaccumulate0;
ARCHITECTURE SYN OF altaccumulate0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT altaccumulate
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
width_in : NATURAL;
width_out : NATURAL
);
PORT (
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
result <= sub_wire1(15 DOWNTO 0);
altaccumulate_component : altaccumulate
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "altaccumulate",
width_in => 8,
width_out => 16
)
PORT MAP (
clken => clken,
aclr => aclr,
clock => clock,
data => data,
cout => sub_wire0,
result => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
-- Retrieval info: PRIVATE: CIN NUMERIC "0"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "1"
-- Retrieval info: PRIVATE: COUT NUMERIC "1"
-- Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "1"
-- Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_IN NUMERIC "8"
-- Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "16"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
-- Retrieval info: CONSTANT: WIDTH_IN NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "16"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altaccumulate0_inst.vhd TRUE
| gpl-2.0 | ed02e6dd0180661a4cc07eab80817d01 | 0.652772 | 3.711324 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sampler/vhdl_sim/sampler_tb.vhd | 4 | 4,560 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.sampler_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.tl_flat_memory_model_pkg.all;
entity sampler_tb is
end entity;
architecture tb of sampler_tb is
signal clock : std_logic := '0';
signal reset : std_logic;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal sample_L : signed(17 downto 0);
signal sample_R : signed(17 downto 0);
signal new_sample : std_logic;
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_dut: entity work.sampler
generic map (
g_num_voices => 8 )
port map (
clock => clock,
reset => reset,
io_req => io_req,
io_resp => io_resp,
mem_req => mem_req,
mem_resp => mem_resp,
sample_L => sample_L,
sample_R => sample_R,
new_sample => new_sample );
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => clock,
req => io_req,
resp => io_resp );
i_mem_bfm: entity work.mem_bus_slave_bfm
generic map (
g_name => "mem_bfm",
g_latency => 2 )
port map (
clock => clock,
req => mem_req,
resp => mem_resp );
test: process
variable io : p_io_bus_bfm_object;
variable mem : h_mem_object;
variable d : std_logic_vector(7 downto 0);
begin
wait until reset='0';
bind_io_bus_bfm("io_bfm", io);
bind_mem_model("mem_bfm", mem);
for i in 0 to 255 loop
d := std_logic_vector(to_signed(integer(127.0*sin(real(i) / 40.58451048843)), 8));
write_memory_8(mem, std_logic_vector(to_unsigned(16#1234500#+i, 32)), d);
end loop;
io_write(io, X"00" + c_sample_volume , X"3F");
io_write(io, X"00" + c_sample_pan , X"07");
io_write(io, X"00" + c_sample_start_addr_h , X"01");
io_write(io, X"00" + c_sample_start_addr_mh , X"23");
io_write(io, X"00" + c_sample_start_addr_ml , X"45");
io_write(io, X"00" + c_sample_start_addr_l , X"00");
io_write(io, X"00" + c_sample_length_h , X"00");
io_write(io, X"00" + c_sample_length_m , X"01");
io_write(io, X"00" + c_sample_length_l , X"00");
io_write(io, X"00" + c_sample_rate_h , X"00");
io_write(io, X"00" + c_sample_rate_l , X"18");
io_write(io, X"00" + c_sample_control , X"01");
io_write(io, X"10" + c_sample_volume , X"28");
io_write(io, X"10" + c_sample_pan , X"0F");
io_write(io, X"10" + c_sample_start_addr_h , X"01");
io_write(io, X"10" + c_sample_start_addr_mh , X"23");
io_write(io, X"10" + c_sample_start_addr_ml , X"45");
io_write(io, X"10" + c_sample_start_addr_l , X"00");
io_write(io, X"10" + c_sample_length_h , X"00");
io_write(io, X"10" + c_sample_length_m , X"01");
io_write(io, X"10" + c_sample_length_l , X"00");
io_write(io, X"10" + c_sample_rate_h , X"00");
io_write(io, X"10" + c_sample_rate_l , X"05");
io_write(io, X"10" + c_sample_control , X"03"); -- repeat on
io_write(io, X"20" + c_sample_volume , X"38");
io_write(io, X"20" + c_sample_pan , X"04");
io_write(io, X"20" + c_sample_start_addr_h , X"01");
io_write(io, X"20" + c_sample_start_addr_mh , X"23");
io_write(io, X"20" + c_sample_start_addr_ml , X"45");
io_write(io, X"20" + c_sample_start_addr_l , X"00");
io_write(io, X"20" + c_sample_length_h , X"00");
io_write(io, X"20" + c_sample_length_m , X"00");
io_write(io, X"20" + c_sample_length_l , X"80");
io_write(io, X"20" + c_sample_rate_h , X"00");
io_write(io, X"20" + c_sample_rate_l , X"09");
io_write(io, X"20" + c_sample_control , X"13"); -- repeat on, 16 bit
wait;
end process;
end architecture;
| gpl-3.0 | 6dac4314cd31ce41aa1b9710acda23eb | 0.482018 | 2.889734 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/ip/busses/vhdl_bfm/slot_bus_master_bfm_pkg.vhd | 5 | 5,996 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.slot_bus_pkg.all;
package slot_bus_master_bfm_pkg is
type t_slot_bus_master_bfm_object;
type p_slot_bus_master_bfm_object is access t_slot_bus_master_bfm_object;
type t_slot_bus_bfm_command is ( e_slot_none, e_slot_io_read, e_slot_bus_read,
e_slot_io_write, e_slot_bus_write );
type t_slot_bus_master_bfm_object is record
next_bfm : p_slot_bus_master_bfm_object;
name : string(1 to 256);
command : t_slot_bus_bfm_command;
poll_time : time;
address : unsigned(15 downto 0);
data : std_logic_vector(7 downto 0);
irq_pending : boolean;
end record;
------------------------------------------------------------------------------------
shared variable slot_bus_master_bfms : p_slot_bus_master_bfm_object := null;
------------------------------------------------------------------------------------
procedure register_slot_bus_master_bfm(named : string; variable pntr: inout p_slot_bus_master_bfm_object);
procedure bind_slot_bus_master_bfm(named : string; variable pntr: inout p_slot_bus_master_bfm_object);
------------------------------------------------------------------------------------
procedure slot_io_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure slot_io_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
procedure slot_bus_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
procedure slot_bus_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
procedure slot_wait_irq(variable m : inout p_slot_bus_master_bfm_object);
end slot_bus_master_bfm_pkg;
package body slot_bus_master_bfm_pkg is
procedure register_slot_bus_master_bfm(named : string;
variable pntr : inout p_slot_bus_master_bfm_object) is
begin
-- Allocate a new BFM object in memory
pntr := new t_slot_bus_master_bfm_object;
-- Initialize object
pntr.next_bfm := null;
pntr.name(named'range) := named;
-- add this pointer to the head of the linked list
if slot_bus_master_bfms = null then -- first entry
slot_bus_master_bfms := pntr;
else -- insert new entry
pntr.next_bfm := slot_bus_master_bfms;
slot_bus_master_bfms := pntr;
end if;
pntr.irq_pending := false;
pntr.poll_time := 10 ns;
end register_slot_bus_master_bfm;
procedure bind_slot_bus_master_bfm(named : string;
variable pntr : inout p_slot_bus_master_bfm_object) is
variable p : p_slot_bus_master_bfm_object;
begin
pntr := null;
wait for 1 ns; -- needed to make sure that binding takes place after registration
p := slot_bus_master_bfms; -- start at the root
L1: while p /= null loop
if p.name(named'range) = named then
pntr := p;
exit L1;
else
p := p.next_bfm;
end if;
end loop;
end bind_slot_bus_master_bfm;
------------------------------------------------------------------------------
procedure slot_bus_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_bus_read;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
data := m.data;
end procedure;
procedure slot_io_read(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : out std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_io_read;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
data := m.data;
end procedure;
procedure slot_bus_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_bus_write;
m.data := data;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
end procedure;
procedure slot_io_write(variable m : inout p_slot_bus_master_bfm_object; addr : unsigned;
data : std_logic_vector(7 downto 0)) is
variable a_i : unsigned(15 downto 0);
begin
a_i := (others => '0');
a_i(addr'length-1 downto 0) := addr;
m.address := a_i;
m.command := e_slot_io_write;
m.data := data;
while m.command /= e_slot_none loop
wait for m.poll_time;
end loop;
end procedure;
procedure slot_wait_irq(variable m : inout p_slot_bus_master_bfm_object) is
begin
while not m.irq_pending loop
wait for m.poll_time;
end loop;
end procedure;
end;
------------------------------------------------------------------------------
| gpl-3.0 | 082ddd6bc7e21e5714b84479316b9997 | 0.525851 | 3.811825 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/fpga_top/ultimate_fpga/vhdl_sim/harness_v4.vhd | 5 | 14,070 |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.tl_flat_memory_model_pkg.all;
use work.mem_bus_pkg.all;
use work.cart_slot_pkg.all;
use work.io_bus_pkg.all;
use work.io_bus_bfm_pkg.all;
use work.command_if_pkg.all;
entity harness_v4 is
end harness_v4;
architecture tb of harness_v4 is
constant c_uart_divisor : natural := 434;
signal PHI2 : std_logic := '0';
signal RSTn : std_logic := 'H';
signal DOTCLK : std_logic := '1';
signal BUFFER_ENn : std_logic := '1';
signal LB_ADDR : std_logic_vector(14 downto 0);
signal LB_DATA : std_logic_vector(7 downto 0) := X"00";
signal BA : std_logic := '0';
signal DMAn : std_logic := '1';
signal EXROMn : std_logic;
signal GAMEn : std_logic;
signal ROMHn : std_logic := '1';
signal ROMLn : std_logic := '1';
signal IO1n : std_logic := '1';
signal IO2n : std_logic := '1';
signal IRQn : std_logic := '1';
signal NMIn : std_logic := '1';
signal MEM_WEn : std_logic;
signal MEM_OEn : std_logic;
signal SDRAM_CSn : std_logic;
signal SDRAM_RASn : std_logic;
signal SDRAM_CASn : std_logic;
signal SDRAM_WEn : std_logic;
signal SDRAM_CKE : std_logic;
signal SDRAM_CLK : std_logic;
signal SDRAM_DQM : std_logic;
signal PWM_OUT : std_logic_vector(1 downto 0);
signal IEC_ATN : std_logic := '1';
signal IEC_DATA : std_logic := '1';
signal IEC_CLOCK : std_logic := '1';
signal IEC_RESET : std_logic := '1';
signal IEC_SRQ_IN : std_logic := '1';
signal DISK_ACTn : std_logic; -- activity LED
signal CART_LEDn : std_logic;
signal SDACT_LEDn : std_logic;
signal MOTOR_LEDn : std_logic;
signal UART_TXD : std_logic;
signal UART_RXD : std_logic := '1';
signal SD_SSn : std_logic;
signal SD_CLK : std_logic;
signal SD_MOSI : std_logic;
signal SD_MISO : std_logic := '1';
signal SD_WP : std_logic := '1';
signal SD_CARDDETn : std_logic := '1';
signal BUTTON : std_logic_vector(2 downto 0) := "000";
signal SLOT_ADDR : std_logic_vector(15 downto 0);
signal SLOT_DATA : std_logic_vector(7 downto 0);
signal RWn : std_logic := '1';
signal CAS_MOTOR : std_logic := '1';
signal CAS_SENSE : std_logic := '0';
signal CAS_READ : std_logic := '0';
signal CAS_WRITE : std_logic := '0';
signal RTC_CS : std_logic;
signal RTC_SCK : std_logic;
signal RTC_MOSI : std_logic;
signal RTC_MISO : std_logic := '1';
signal FLASH_CSn : std_logic;
signal FLASH_SCK : std_logic;
signal FLASH_MOSI : std_logic;
signal FLASH_MISO : std_logic := '1';
signal ULPI_CLOCK : std_logic := '0';
signal ULPI_RESET : std_logic := '0';
signal ULPI_NXT : std_logic := '0';
signal ULPI_STP : std_logic;
signal ULPI_DIR : std_logic := '0';
signal ULPI_DATA : std_logic_vector(7 downto 0) := (others => 'H');
signal sys_clock : std_logic := '0';
signal sys_reset : std_logic := '0';
signal sys_shifted : std_logic := '0';
signal rx_char : std_logic_vector(7 downto 0);
signal rx_char_d : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal tx_char : std_logic_vector(7 downto 0) := X"00";
signal tx_done : std_logic;
signal do_tx : std_logic := '0';
shared variable dram : h_mem_object;
shared variable ram : h_mem_object;
-- shared variable rom : h_mem_object;
-- shared variable bram : h_mem_object;
-- memory controller interconnect
signal memctrl_inhibit : std_logic;
signal mem_req : t_mem_req;
signal mem_resp : t_mem_resp;
signal io_req : t_io_req;
signal io_resp : t_io_resp;
begin
mut: entity work.ultimate_logic
generic map (
g_simulation => true )
port map (
sys_clock => sys_clock,
sys_reset => sys_reset,
PHI2 => PHI2,
DOTCLK => DOTCLK,
RSTn => RSTn,
BUFFER_ENn => BUFFER_ENn,
SLOT_ADDR => SLOT_ADDR,
SLOT_DATA => SLOT_DATA,
RWn => RWn,
BA => BA,
DMAn => DMAn,
EXROMn => EXROMn,
GAMEn => GAMEn,
ROMHn => ROMHn,
ROMLn => ROMLn,
IO1n => IO1n,
IO2n => IO2n,
IRQn => IRQn,
NMIn => NMIn,
-- local bus side
mem_inhibit => memctrl_inhibit,
--memctrl_idle => memctrl_idle,
mem_req => mem_req,
mem_resp => mem_resp,
-- io bus for simulation
sim_io_req => io_req,
sim_io_resp => io_resp,
-- PWM outputs (for audio)
PWM_OUT => PWM_OUT,
-- IEC bus
IEC_ATN => IEC_ATN,
IEC_DATA => IEC_DATA,
IEC_CLOCK => IEC_CLOCK,
IEC_RESET => IEC_RESET,
IEC_SRQ_IN => IEC_SRQ_IN,
DISK_ACTn => DISK_ACTn, -- activity LED
CART_LEDn => CART_LEDn,
SDACT_LEDn => SDACT_LEDn,
MOTOR_LEDn => MOTOR_LEDn,
-- Debug UART
UART_TXD => UART_TXD,
UART_RXD => UART_RXD,
-- SD Card Interface
SD_SSn => SD_SSn,
SD_CLK => SD_CLK,
SD_MOSI => SD_MOSI,
SD_MISO => SD_MISO,
SD_CARDDETn => SD_CARDDETn,
-- Cassette Interface
CAS_MOTOR => CAS_MOTOR,
CAS_SENSE => CAS_SENSE,
CAS_READ => CAS_READ,
CAS_WRITE => CAS_WRITE,
-- RTC Interface
RTC_CS => RTC_CS,
RTC_SCK => RTC_SCK,
RTC_MOSI => RTC_MOSI,
RTC_MISO => RTC_MISO,
-- Flash Interface
FLASH_CSn => FLASH_CSn,
FLASH_SCK => FLASH_SCK,
FLASH_MOSI => FLASH_MOSI,
FLASH_MISO => FLASH_MISO,
-- USB Interface (ULPI)
ULPI_CLOCK => ULPI_CLOCK,
ULPI_RESET => ULPI_RESET,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
ULPI_DIR => ULPI_DIR,
ULPI_DATA => ULPI_DATA,
-- Buttons
BUTTON => BUTTON );
i_memctrl: entity work.ext_mem_ctrl_v4
generic map (
g_simulation => true,
A_Width => 15 )
port map (
clock => sys_clock,
clk_shifted => sys_shifted,
reset => sys_reset,
inhibit => memctrl_inhibit,
is_idle => open, --memctrl_idle,
req => mem_req,
resp => mem_resp,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CLK => SDRAM_CLK,
MEM_A => LB_ADDR,
MEM_D => LB_DATA );
sys_clock <= not sys_clock after 10 ns; -- 50 MHz
sys_reset <= '1', '0' after 100 ns;
sys_shifted <= transport sys_clock after 3 ns;
ULPI_CLOCK <= not ULPI_CLOCK after 8.333 ns; -- 60 MHz
ULPI_RESET <= '1', '0' after 100 ns;
PHI2 <= not PHI2 after 507.5 ns; -- 0.98525 MHz
RSTn <= '0', 'H' after 6 us, '0' after 100 us, 'H' after 105 us;
i_ulpi_phy: entity work.ulpi_phy_bfm
generic map (
g_rx_interval => 100000 )
port map (
clock => ULPI_CLOCK,
reset => ULPI_RESET,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP );
i_io_bfm: entity work.io_bus_bfm
generic map (
g_name => "io_bfm" )
port map (
clock => sys_clock,
req => io_req,
resp => io_resp );
process
begin
bind_mem_model("intram", ram);
bind_mem_model("dram", dram);
load_memory("../../software/1st_boot/result/1st_boot.bin", ram, X"00000000");
-- 1st boot will try to load the 2nd bootloader and application from flash. In simulation this is a cumbersome
-- process. It would work with a good model of the serial spi flash, but since it is not included in the public
-- archive, you need to create a special boot image that just jumps to 0x20000 and load the application here to dram:
load_memory("../../software/ultimate/result/ultimate.bin", dram, X"00020000");
wait;
end process;
SLOT_DATA <= (others => 'H');
ROMHn <= '1';
ROMLn <= not PHI2 after 50 ns;
IO1n <= '1';
IO2n <= '1';
process
begin
SLOT_ADDR <= X"D400";
RWn <= '1';
while true loop
wait until PHI2 = '0';
--SLOT_ADDR(8 downto 0) <= std_logic_vector(unsigned(SLOT_ADDR(8 downto 0)) + 1);
SLOT_ADDR <= std_logic_vector(unsigned(SLOT_ADDR) + 1);
RWn <= '1';
wait until PHI2 = '0';
RWn <= '0';
end loop;
end process;
process
begin
BA <= '1';
for i in 0 to 100 loop
wait until PHI2='0';
end loop;
BA <= '0';
for i in 0 to 10 loop
wait until PHI2='0';
end loop;
end process;
dram_bfm: entity work.dram_model_8
generic map(
g_given_name => "dram",
g_cas_latency => 2,
g_burst_len_r => 1,
g_burst_len_w => 1,
g_column_bits => 10,
g_row_bits => 13,
g_bank_bits => 2 )
port map (
CLK => SDRAM_CLK,
CKE => SDRAM_CKE,
A => LB_ADDR(12 downto 0),
BA => LB_ADDR(14 downto 13),
CSn => SDRAM_CSn,
RASn => SDRAM_RASn,
CASn => SDRAM_CASn,
WEn => SDRAM_WEn,
DQM => SDRAM_DQM,
DQ => LB_DATA);
i_rx: entity work.rx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
rxd => UART_TXD,
rxchar => rx_char,
rx_ack => rx_ack );
i_tx: entity work.tx
generic map (c_uart_divisor)
port map (
clk => sys_clock,
reset => sys_reset,
dotx => do_tx,
txchar => tx_char,
done => tx_done,
txd => UART_RXD );
process(sys_clock)
begin
if rising_edge(sys_clock) then
if rx_ack='1' then
rx_char_d <= rx_char;
end if;
end if;
end process;
-- procedure register_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
-- procedure bind_io_bus_bfm(named : string; variable pntr: inout p_io_bus_bfm_object);
-- procedure io_read(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : out std_logic_vector(7 downto 0));
-- procedure io_write(variable io : inout p_io_bus_bfm_object; addr : unsigned; data : std_logic_vector(7 downto 0));
-- constant c_cart_c64_mode : unsigned(3 downto 0) := X"0";
-- constant c_cart_c64_stop : unsigned(3 downto 0) := X"1";
-- constant c_cart_c64_stop_mode : unsigned(3 downto 0) := X"2";
-- constant c_cart_c64_clock_detect : unsigned(3 downto 0) := X"3";
-- constant c_cart_cartridge_rom_base : unsigned(3 downto 0) := X"4";
-- constant c_cart_cartridge_type : unsigned(3 downto 0) := X"5";
-- constant c_cart_cartridge_kill : unsigned(3 downto 0) := X"6";
-- constant c_cart_reu_enable : unsigned(3 downto 0) := X"8";
-- constant c_cart_reu_size : unsigned(3 downto 0) := X"9";
-- constant c_cart_swap_buttons : unsigned(3 downto 0) := X"A";
-- constant c_cart_ethernet_enable : unsigned(3 downto 0) := X"F";
process
variable io : p_io_bus_bfm_object;
begin
wait until sys_reset='0';
wait until sys_clock='1';
bind_io_bus_bfm("io_bfm", io);
io_write(io, X"40000" + c_cart_c64_mode, X"04"); -- reset
io_write(io, X"40000" + c_cart_cartridge_type, X"06"); -- retro
io_write(io, X"40000" + c_cart_c64_mode, X"08"); -- unreset
io_write(io, X"44000" + c_cif_io_slot_base, X"7E");
io_write(io, X"44000" + c_cif_io_slot_enable, X"01");
wait for 6 us;
wait until sys_clock='1';
io_write(io, X"42002", X"42");
wait;
end process;
process
procedure send_char(i: std_logic_vector(7 downto 0)) is
begin
if tx_done /= '1' then
wait until tx_done = '1';
end if;
wait until sys_clock='1';
tx_char <= i;
do_tx <= '1';
wait until tx_done = '0';
wait until sys_clock='1';
do_tx <= '0';
end procedure;
procedure send_string(i : string) is
variable b : std_logic_vector(7 downto 0);
begin
for n in i'range loop
b := std_logic_vector(to_unsigned(character'pos(i(n)), 8));
send_char(b);
end loop;
send_char(X"0d");
send_char(X"0a");
end procedure;
begin
wait for 2 ms;
--send_string("wd 4005000 12345678");
send_string("run");
-- send_string("m 100000");
-- send_string("w 400000F 4");
wait;
end process;
-- check timing data
process(PHI2)
begin
if falling_edge(PHI2) then
assert SLOT_DATA'last_event >= 189 ns
report "Timing error on C64 bus."
severity error;
end if;
end process;
end tb;
| gpl-3.0 | 871b25df09c7015410dc8497315a2709 | 0.501777 | 3.362811 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/sid_top.vhd | 4 | 11,893 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity sid_top is
generic (
g_filter_div : natural := 221; -- for 50 MHz
g_num_voices : natural := 16 );
port (
clock : in std_logic;
reset : in std_logic;
addr : in unsigned(7 downto 0);
wren : in std_logic;
wdata : in std_logic_vector(7 downto 0);
rdata : out std_logic_vector(7 downto 0);
comb_wave_l : in std_logic := '0';
comb_wave_r : in std_logic := '0';
io_req_filt : in t_io_req := c_io_req_init;
io_resp_filt : out t_io_resp;
start_iter : in std_logic;
sample_left : out signed(17 downto 0);
sample_right : out signed(17 downto 0) );
end sid_top;
architecture structural of sid_top is
-- Voice index in pipe
signal voice_osc : unsigned(3 downto 0);
signal voice_wave : unsigned(3 downto 0);
signal voice_mul : unsigned(3 downto 0);
signal enable_osc : std_logic;
signal enable_wave : std_logic;
signal enable_mul : std_logic;
-- Oscillator parameters
signal freq : unsigned(15 downto 0);
signal test : std_logic;
signal sync : std_logic;
-- Wave map parameters
signal msb_other : std_logic;
signal comb_mode : std_logic;
signal ring_mod : std_logic;
signal wave_sel : std_logic_vector(3 downto 0);
signal sq_width : unsigned(11 downto 0);
-- ADSR parameters
signal gate : std_logic;
signal attack : std_logic_vector(3 downto 0);
signal decay : std_logic_vector(3 downto 0);
signal sustain : std_logic_vector(3 downto 0);
signal release : std_logic_vector(3 downto 0);
-- Filter enable
signal filter_en : std_logic;
-- globals
signal volume_l : unsigned(3 downto 0);
signal filter_co_l : unsigned(10 downto 0);
signal filter_res_l : unsigned(3 downto 0);
signal filter_ex_l : std_logic;
signal filter_hp_l : std_logic;
signal filter_bp_l : std_logic;
signal filter_lp_l : std_logic;
signal voice3_off_l : std_logic;
signal volume_r : unsigned(3 downto 0);
signal filter_co_r : unsigned(10 downto 0);
signal filter_res_r : unsigned(3 downto 0);
signal filter_ex_r : std_logic;
signal filter_hp_r : std_logic;
signal filter_bp_r : std_logic;
signal filter_lp_r : std_logic;
signal voice3_off_r : std_logic;
-- readback
signal osc3 : std_logic_vector(7 downto 0);
signal env3 : std_logic_vector(7 downto 0);
-- intermediate flags and signals
signal test_wave : std_logic;
signal osc_val : unsigned(23 downto 0);
signal carry_20 : std_logic;
signal enveloppe : unsigned(7 downto 0);
signal waveform : unsigned(11 downto 0);
signal valid_sum : std_logic;
signal valid_filt : std_logic;
signal valid_mix : std_logic;
signal filter_out_l: signed(17 downto 0) := (others => '0');
signal direct_out_l: signed(17 downto 0) := (others => '0');
signal high_pass_l : signed(17 downto 0) := (others => '0');
signal band_pass_l : signed(17 downto 0) := (others => '0');
signal low_pass_l : signed(17 downto 0) := (others => '0');
signal mixed_out_l : signed(17 downto 0) := (others => '0');
signal filter_out_r: signed(17 downto 0) := (others => '0');
signal direct_out_r: signed(17 downto 0) := (others => '0');
signal high_pass_r : signed(17 downto 0) := (others => '0');
signal band_pass_r : signed(17 downto 0) := (others => '0');
signal low_pass_r : signed(17 downto 0) := (others => '0');
signal mixed_out_r : signed(17 downto 0) := (others => '0');
begin
i_regs: entity work.sid_regs
port map (
clock => clock,
reset => reset,
addr => addr,
wren => wren,
wdata => wdata,
rdata => rdata,
comb_wave_l => comb_wave_l,
comb_wave_r => comb_wave_r,
---
voice_osc => voice_osc,
voice_wave => voice_wave,
voice_adsr => voice_wave,
voice_mul => voice_mul,
-- Oscillator parameters
freq => freq,
test => test,
sync => sync,
-- Wave map parameters
comb_mode => comb_mode,
ring_mod => ring_mod,
wave_sel => wave_sel,
sq_width => sq_width,
-- ADSR parameters
gate => gate,
attack => attack,
decay => decay,
sustain => sustain,
release => release,
-- mixer parameters
filter_en => filter_en,
-- globals
volume_l => volume_l,
filter_co_l => filter_co_l,
filter_res_l=> filter_res_l,
filter_ex_l => filter_ex_l,
filter_hp_l => filter_hp_l,
filter_bp_l => filter_bp_l,
filter_lp_l => filter_lp_l,
voice3_off_l=> voice3_off_l,
volume_r => volume_r,
filter_co_r => filter_co_r,
filter_res_r=> filter_res_r,
filter_ex_r => filter_ex_r,
filter_hp_r => filter_hp_r,
filter_bp_r => filter_bp_r,
filter_lp_r => filter_lp_r,
voice3_off_r=> voice3_off_r,
-- readback
osc3 => osc3,
env3 => env3 );
i_ctrl: entity work.sid_ctrl
generic map (
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
start_iter => start_iter,
voice_osc => voice_osc,
enable_osc => enable_osc );
osc: entity work.oscillator
generic map (g_num_voices)
port map (
clock => clock,
reset => reset,
voice_i => voice_osc,
voice_o => voice_wave,
enable_i => enable_osc,
enable_o => enable_wave,
freq => freq,
test => test,
sync => sync,
osc_val => osc_val,
test_o => test_wave,
carry_20 => carry_20,
msb_other => msb_other );
wmap: entity work.wave_map
generic map (
g_num_voices => g_num_voices,
g_sample_bits => 12 )
port map (
clock => clock,
reset => reset,
test => test_wave,
osc_val => osc_val,
carry_20 => carry_20,
msb_other => msb_other,
voice_i => voice_wave,
enable_i => enable_wave,
comb_mode => comb_mode,
wave_sel => wave_sel,
ring_mod => ring_mod,
sq_width => sq_width,
voice_o => voice_mul,
enable_o => enable_mul,
wave_out => waveform );
adsr: entity work.adsr_multi
generic map (
g_num_voices => g_num_voices )
port map (
clock => clock,
reset => reset,
voice_i => voice_wave,
enable_i => enable_wave,
voice_o => open,
enable_o => open,
gate => gate,
attack => attack,
decay => decay,
sustain => sustain,
release => release,
env_state=> open, -- for testing only
env_out => enveloppe );
sum: entity work.mult_acc(signed_wave)
port map (
clock => clock,
reset => reset,
voice_i => voice_mul,
enable_i => enable_mul,
voice3_off_l=> voice3_off_l,
voice3_off_r=> voice3_off_r,
enveloppe => enveloppe,
waveform => waveform,
filter_en => filter_en,
--
osc3 => osc3,
env3 => env3,
--
valid_out => valid_sum,
filter_out_L => filter_out_L,
filter_out_R => filter_out_R,
direct_out_L => direct_out_L,
direct_out_R => direct_out_R );
i_filt_left: entity work.sid_filter
generic map (
g_divider => g_filter_div )
port map (
clock => clock,
reset => reset,
io_req => io_req_filt,
io_resp => io_resp_filt,
filt_co => filter_co_l,
filt_res => filter_res_l,
valid_in => valid_sum,
input => filter_out_L,
high_pass => high_pass_L,
band_pass => band_pass_L,
low_pass => low_pass_L,
error_out => open,
valid_out => valid_filt );
-- Now we have to add the following signals together:
-- direct_out
-- high_pass (when filter_hp='1')
-- band_pass (when filter_bp='1')
-- low_pass (when filter_lp='1')
--
-- .. and apply the final volume control
mix: entity work.sid_mixer
port map (
clock => clock,
reset => reset,
valid_in => valid_filt,
direct_out => direct_out_L,
high_pass => high_pass_L,
band_pass => band_pass_L,
low_pass => low_pass_L,
filter_hp => filter_hp_l,
filter_bp => filter_bp_l,
filter_lp => filter_lp_l,
volume => volume_l,
mixed_out => mixed_out_L,
valid_out => valid_mix );
r_right_filter: if g_num_voices > 8 generate
i_filt: entity work.sid_filter
generic map (
g_divider => g_filter_div )
port map (
clock => clock,
reset => reset,
io_req => io_req_filt,
io_resp => open, -- write only
filt_co => filter_co_r,
filt_res => filter_res_r,
valid_in => valid_sum,
input => filter_out_R,
high_pass => high_pass_R,
band_pass => band_pass_R,
low_pass => low_pass_R,
error_out => open,
valid_out => open );
mix_right: entity work.sid_mixer
port map (
clock => clock,
reset => reset,
valid_in => valid_filt,
direct_out => direct_out_R,
high_pass => high_pass_R,
band_pass => band_pass_R,
low_pass => low_pass_R,
filter_hp => filter_hp_r,
filter_bp => filter_bp_r,
filter_lp => filter_lp_r,
volume => volume_r,
mixed_out => mixed_out_R,
valid_out => open );
end generate;
sample_left <= mixed_out_L;
sample_right <= mixed_out_R when g_num_voices > 8 else mixed_out_L;
end structural;
| gpl-3.0 | c9736a6adb8ca4464479a73be401f74e | 0.467166 | 3.749369 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op989_9.vhdl | 1 | 6,153 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vbias1: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in1,
S => net6
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net7,
G => in2,
S => net6
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net7,
G => net7,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net7,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net7,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias2,
S => net3
);
subnet0_subnet4_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias2,
S => net4
);
subnet0_subnet5_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias3,
S => net8
);
subnet0_subnet5_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net8,
G => net5,
S => gnd
);
subnet0_subnet5_m3 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net9,
G => net5,
S => gnd
);
subnet0_subnet5_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias3,
S => net9
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net10,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | 07e05fa8a9fc6890737b49185807e1b6 | 0.574516 | 3.088855 | false | false | false | false |
Charlesworth/Albot | Albot VHDL/altaccumulate0_inst.vhd | 1 | 185 | altaccumulate0_inst : altaccumulate0 PORT MAP (
aclr => aclr_sig,
clken => clken_sig,
clock => clock_sig,
data => data_sig,
cout => cout_sig,
result => result_sig
);
| gpl-2.0 | b21b6df0e72ee44580a8f7df7416413f | 0.610811 | 2.761194 | false | false | false | false |
nick1au/Home-Sec-SYS | System.vhd | 1 | 1,839 | Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Entity System is
Port(door: IN std_logic_vector(3 downto 0);
ARM, clock : IN std_logic;
ready, delay, SysArm, AlrOn: OUT std_logic);
end System;
Architecture Basic of System is
Type StateName is (sysoff, syson, alr);
signal Prest,NxtSt,sysoffnext,sysonnext,alrnext: StateName;
begin
sysoffnext <=syson when arm ='1' else sysoff;
sysonnext <= sysoff when arm ='1' else alr when door /="0000" else syson;
alrnext <= sysoff when arm ='1' else alr;
NxtSt <= sysoffnext when prest = sysoff else sysonnext when prest = syson else alrnext;
Prest <= NxtSt when Rising_edge(clock);
ready <= '1' when door = "0000" else '0';
SysArm <= '1' when NxtSt = syson OR NxtSt = alr else '0';
AlrOn <= '1' when nxtSt = alr else '0' when NxtSt = sysoff OR nxtSt = syson;
end Basic;
Architecture thelayed of System is
Component TenSecDelay is
Port (load, clock: in std_logic;
TC: out std_logic);
End Component TenSecDelay;
Type StateName is (sysoff, syson, alr);
signal Prest,NxtSt,sysoffnext,sysonnext,alrnext: StateName;
signal sload, sTC: std_logic;
begin
sysoffnext <=syson when arm ='1' else sysoff;
sysonnext <= sysoff when arm ='1' else alr when (door /="0000" AND sTC ='0') else syson;
alrnext <= sysoff when arm ='1' else alr;
NxtSt <= sysoffnext when prest = sysoff else sysonnext when prest = syson else alrnext;
Prest <= NxtSt when Rising_edge(clock);
ready <= '1' when door = "0000" else '0';
SysArm <= '1' when NxtSt = syson OR NxtSt = alr else '0';
AlrOn <= '1' when (prest = alr AND sTC ='0') else '0'; --when NxtSt = sysoff OR nxtSt = syson;
delay <= stc;
sload<= '1' when (prest = sysoff and nxtst = syson) OR (prest = syson AND door /="0000") else '0';
stage0: entity work.tensecdelay port map(load=>sload, clock=> clock, TC=>sTC);
end thelayed; | gpl-3.0 | 392353b3ec47d818d3dec1df09b55220 | 0.698749 | 2.807634 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/rtl/vhdl/chip-minimal-a.vhd | 2 | 6,046 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Chip toplevel design with minimal feature set
--
-- $Id: chip-minimal-a.vhd,v 1.6 2005/04/07 20:44:23 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture minimal of chip is
component spi_boot
generic (
width_set_sel_g : integer := 4;
width_bit_cnt_g : integer := 6;
width_img_cnt_g : integer := 2;
num_bits_per_img_g : integer := 18;
sd_init_g : integer := 0;
mmc_compat_clk_div_g : integer := 0;
width_mmc_clk_div_g : integer := 0;
reset_level_g : integer := 0
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
set_sel_i : in std_logic_vector(width_set_sel_g-1 downto 0);
spi_clk_o : out std_logic;
spi_cs_n_o : out std_logic;
spi_data_in_i : in std_logic;
spi_data_out_o : out std_logic;
spi_en_outs_o : out std_logic;
start_i : in std_logic;
mode_i : in std_logic;
config_n_o : out std_logic;
detached_o : out std_logic;
cfg_init_n_i : in std_logic;
cfg_done_i : in std_logic;
dat_done_i : in std_logic;
cfg_clk_o : out std_logic;
cfg_dat_o : out std_logic
);
end component;
signal spi_clk_s : std_logic;
signal spi_cs_n_s : std_logic;
signal spi_data_out_s : std_logic;
signal spi_en_outs_s : std_logic;
signal set_sel_s : std_logic_vector(3 downto 0);
begin
set_sel_s <= not set_sel_n_i;
spi_boot_b : spi_boot
generic map (
width_set_sel_g => 4, -- 16 sets
width_bit_cnt_g => 6, -- 8 bytes per block
width_img_cnt_g => 2, -- 4 images
num_bits_per_img_g => 18, -- 256 kByte per image
sd_init_g => 0, -- no SD specific initialization
mmc_compat_clk_div_g => 0, -- no MMC compatibility
width_mmc_clk_div_g => 0 -- no MMC compatibility
)
port map (
clk_i => clk_i,
reset_i => reset_i,
set_sel_i => set_sel_s,
spi_clk_o => spi_clk_s,
spi_cs_n_o => spi_cs_n_s,
spi_data_in_i => spi_data_in_i,
spi_data_out_o => spi_data_out_s,
spi_en_outs_o => spi_en_outs_s,
start_i => start_i,
mode_i => mode_i,
config_n_o => config_n_o,
detached_o => detached_o,
cfg_init_n_i => cfg_init_n_i,
cfg_done_i => cfg_done_i,
dat_done_i => dat_done_i,
cfg_clk_o => cfg_clk_o,
cfg_dat_o => cfg_dat_o
);
-----------------------------------------------------------------------------
-- Three state drivers for SPI outputs.
-----------------------------------------------------------------------------
spi_clk_o <= spi_clk_s
when spi_en_outs_s = '1' else
'Z';
spi_cs_n_o <= spi_cs_n_s
when spi_en_outs_s = '1' else
'Z';
spi_data_out_o <= spi_data_out_s
when spi_en_outs_s = '1' else
'Z';
end minimal;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: chip-minimal-a.vhd,v $
-- Revision 1.6 2005/04/07 20:44:23 arniml
-- add new port detached_o
--
-- Revision 1.5 2005/03/09 19:48:34 arniml
-- invert level of set_sel input
--
-- Revision 1.4 2005/03/08 22:07:12 arniml
-- added set selection
--
-- Revision 1.3 2005/02/18 06:42:12 arniml
-- clarify wording for images
--
-- Revision 1.2 2005/02/16 18:54:39 arniml
-- added tri-state drivers for spi outputs
--
-- Revision 1.1 2005/02/08 20:41:31 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | bb1e4c099b3e5a8a159e47c6692d8bee | 0.540192 | 3.653172 | false | false | false | false |
daringer/schemmaker | testdata/circuit_bi1_0op332_3.vhdl | 1 | 5,067 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net3,
G => net1,
S => vdd
);
subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => net3,
N => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcm_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
W => Wcmout_2,
scope => private,
symmetry_scope => sym_1
)
port map(
D => out1,
G => net2,
S => vdd
);
subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_1
)
port map(
P => out1,
N => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => gnd
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
W => Wcmcout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => gnd
);
subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net3
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net5
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net5,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | aeef436a8a4b4efd19623a018760caef | 0.579238 | 3.158978 | false | false | false | false |
KB777/1541UltimateII | fpga/io/uart_lite/vhdl_source/uart_peripheral_io.vhd | 1 | 5,172 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
entity uart_peripheral_io is
generic (
g_tx_fifo : boolean := true;
g_divisor : natural := 417 );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
irq : out std_logic;
txd : out std_logic;
rxd : in std_logic := '1';
rts : out std_logic;
cts : in std_logic := '1' );
end uart_peripheral_io;
architecture gideon of uart_peripheral_io is
signal dotx : std_logic;
signal done : std_logic;
signal rxchar : std_logic_vector(7 downto 0);
signal rx_ack : std_logic;
signal rxfifo_get : std_logic;
signal rxfifo_dout : std_logic_vector(7 downto 0);
signal rxfifo_full : std_logic;
signal rxfifo_dav : std_logic;
signal overflow : std_logic;
signal flags : std_logic_vector(7 downto 0);
signal imask : std_logic_vector(7 downto 6);
signal rdata_mux : std_logic_vector(7 downto 0);
signal txfifo_get : std_logic;
signal txfifo_put : std_logic;
signal txfifo_dout : std_logic_vector(7 downto 0);
signal txfifo_full : std_logic := '1';
signal txfifo_dav : std_logic;
signal dotx_d : std_logic;
signal txchar : std_logic_vector(7 downto 0);
constant c_uart_data : unsigned(1 downto 0) := "00";
constant c_uart_get : unsigned(1 downto 0) := "01";
constant c_uart_flags : unsigned(1 downto 0) := "10";
constant c_uart_imask : unsigned(1 downto 0) := "11";
begin
my_tx: entity work.tx
generic map (g_divisor)
port map (
clk => clock,
reset => reset,
dotx => dotx,
txchar => txchar,
cts => cts,
txd => txd,
done => done );
my_rx: entity work.rx
generic map (g_divisor)
port map (
clk => clock,
reset => reset,
rxd => rxd,
rxchar => rxchar,
rx_ack => rx_ack );
my_rxfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => rxfifo_get,
PutElement => rx_ack,
FlushFifo => '0',
DataIn => rxchar,
DataOut => rxfifo_dout,
SpaceInFifo => open,
AlmostFull => rxfifo_full,
DataInFifo => rxfifo_dav );
gentx: if g_tx_fifo generate
my_txfifo: entity work.srl_fifo
generic map (
Width => 8,
Threshold => 12 )
port map (
clock => clock,
reset => reset,
GetElement => txfifo_get,
PutElement => txfifo_put,
FlushFifo => '0',
DataIn => io_req.data,
DataOut => txfifo_dout,
SpaceInFifo => open,
AlmostFull => txfifo_full,
DataInFifo => txfifo_dav );
end generate;
process(clock)
begin
if rising_edge(clock) then
rxfifo_get <= '0';
dotx_d <= dotx;
txfifo_get <= dotx_d;
io_resp <= c_io_resp_init;
if rxfifo_full='1' and rx_ack='1' then
overflow <= '1';
end if;
txfifo_put <= '0';
if g_tx_fifo then
dotx <= txfifo_dav and done and not dotx;
txchar <= txfifo_dout;
else
dotx <= '0'; -- default, overridden with write
end if;
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(1 downto 0) is
when c_uart_data => -- dout
if not g_tx_fifo then
txchar <= io_req.data;
dotx <= '1';
else -- there is a fifo
txfifo_put <= '1';
end if;
when c_uart_get => -- din
rxfifo_get <= '1';
when c_uart_flags => -- clear flags
overflow <= overflow and not io_req.data(0);
when c_uart_imask => -- interrupt control
imask <= io_req.data(7 downto 6);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
io_resp.data <= rdata_mux;
end if;
if (flags(7 downto 6) and imask) /= "00" then
irq <= '1';
else
irq <= '0';
end if;
if reset='1' then
overflow <= '0';
imask <= (others => '0');
end if;
end if;
end process;
flags(0) <= overflow;
flags(1) <= '0';
flags(2) <= '0';
flags(3) <= '0';
flags(4) <= txfifo_full;
flags(5) <= rxfifo_full;
flags(6) <= done;
flags(7) <= rxfifo_dav;
rts <= not rxfifo_full;
with io_req.address(1 downto 0) select rdata_mux <=
rxfifo_dout when c_uart_data,
flags when c_uart_flags,
imask & "000000" when c_uart_imask,
X"00" when others;
end gideon;
| gpl-3.0 | 0cdeb3c0415e0600bda1936cd2d1c7d2 | 0.491686 | 3.384817 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op958_0.vhdl | 1 | 5,276 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net4
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net4
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net4,
G => vbias4,
S => gnd
);
subnet0_subnet0_m4 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in1,
S => net4
);
subnet0_subnet0_m5 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net5,
G => in2,
S => net4
);
subnet0_subnet0_m6 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m7 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net5,
G => net5,
S => vdd
);
subnet0_subnet0_m8 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net1,
G => net5,
S => vdd
);
subnet0_subnet0_m9 : entity pmos(behave)
generic map(
L => Lcmdiffp_0,
W => Wcmdiffp_0,
scope => private
)
port map(
D => net2,
G => net5,
S => vdd
);
subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => net1,
S => gnd
);
subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => Lsrc,
W => Wsrc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => out1,
G => net2,
S => gnd
);
subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net6,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | c1d1ee053350e10ca3c133149425c8b5 | 0.575815 | 3.125592 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/sid6581/vhdl_source/sid_trace.vhd | 5 | 6,482 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
use work.io_bus_pkg.all;
entity sid_trace is
generic (
g_mem_tag : std_logic_vector(7 downto 0) := X"CE" );
port (
clock : in std_logic;
reset : in std_logic;
addr : in unsigned(6 downto 0);
wren : in std_logic;
wdata : in std_logic_vector(7 downto 0);
phi2_tick : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
mem_req : out t_mem_req;
mem_resp : in t_mem_resp );
end entity;
architecture gideon of sid_trace is
type t_reg_bank is array(natural range <>) of std_logic_vector(7 downto 0);
signal reg_start : t_reg_bank(0 to 31) := (others => (others => '0'));
type t_state is (idle, trace, finish);
signal state : t_state;
type t_mem_state is (idle, do_req, wait_ack );
signal mem_state : t_mem_state;
signal address : unsigned(25 downto 0);
signal count : unsigned(23 downto 0);
signal fifo_din : std_logic_vector(38 downto 0);
signal fifo_dout : std_logic_vector(38 downto 0);
signal write_data : std_logic_vector(39 downto 0);
signal fifo_valid : std_logic;
signal fifo_pop : std_logic;
signal fifo_push : std_logic;
signal byte_count : integer range 0 to 7;
signal triggered : std_logic;
signal memory_full : std_logic;
begin
process(clock)
begin
if rising_edge(clock) then
case state is
when idle =>
count <= (others => '0');
if wren='1' then
reg_start(to_integer(addr(4 downto 0))) <= wdata;
end if;
if wren='1' and triggered='1' then
triggered <= '0';
state <= trace;
end if;
when trace =>
if wren='1' then
count <= to_unsigned(1, count'length);
elsif phi2_tick='1' then
count <= count + 1;
end if;
when finish =>
null;
when others =>
null;
end case;
io_resp <= c_io_resp_init;
if io_req.read='1' then
io_resp.ack <= '1';
if io_req.address(7)='0' then
io_resp.data <= reg_start(to_integer(io_req.address(4 downto 0)));
else
case io_req.address(1 downto 0) is
when "00" =>
io_resp.data <= std_logic_vector(address(7 downto 0));
when "01" =>
io_resp.data <= std_logic_vector(address(15 downto 8));
when "10" =>
io_resp.data <= std_logic_vector(address(23 downto 16));
when "11" =>
io_resp.data <= "000000" & std_logic_vector(address(25 downto 24));
when others =>
null;
end case;
end if;
elsif io_req.write='1' then
io_resp.ack <= '1';
if io_req.data = X"33" then
triggered <= '1';
elsif io_req.data = X"44" then
state <= finish;
elsif io_req.data = X"55" then
state <= idle;
end if;
end if;
if reset='1' then
triggered <= '0';
state <= idle;
end if;
end if;
end process;
fifo_din <= std_logic_vector(addr) & wdata & std_logic_vector(count);
fifo_push <= '1' when wren='1' and state = trace else '0';
write_data <= '0' & fifo_dout;
i_fifo: entity work.SRL_fifo
generic map ( Width => 39 )
port map (
clock => clock,
reset => reset,
GetElement => fifo_pop,
PutElement => fifo_push,
FlushFifo => '0',
DataIn => fifo_din,
DataOut => fifo_dout,
SpaceInFifo => open,
AlmostFull => open,
DataInFifo => fifo_valid );
process(clock)
begin
if rising_edge(clock) then
fifo_pop <= '0';
case mem_state is
when idle =>
if fifo_valid='1' and fifo_pop='0' and memory_full='0' then
byte_count <= 4;
mem_state <= do_req;
end if;
when do_req =>
mem_req.request <= '1';
mem_req.data <= write_data(byte_count*8+7 downto byte_count*8);
mem_state <= wait_ack;
when wait_ack =>
if mem_resp.rack='1' and mem_resp.rack_tag=g_mem_tag then
mem_req.request <= '0';
address <= address + 1;
if address = 33554431 then
memory_full <= '1';
end if;
if byte_count = 0 then
fifo_pop <= '1';
mem_state <= idle;
else
byte_count <= byte_count -1;
mem_state <= do_req;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
memory_full <= '0';
mem_req.data <= (others => '0');
mem_req.request <= '0';
mem_state <= idle;
address <= to_unsigned(16777216, address'length);
end if;
end if;
end process;
mem_req.address <= address;
mem_req.read_writen <= '0';
mem_req.tag <= g_mem_tag;
end gideon;
| gpl-3.0 | 02915674eda2bdf49fe1dc9b62c03961 | 0.434434 | 4.176546 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op332_5sk1_0.vhdl | 1 | 7,459 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal vbias1: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.55e-06,
W => Wdiff_0,
Wdiff_0init => 4.2e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.55e-06,
W => Wdiff_0,
Wdiff_0init => 4.2e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => W_0,
W_0init => 3.8e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 4.7e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net2,
G => vbias2,
S => net6
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 4.75e-06,
W => Wcm_2,
Wcm_2init => 9.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 4.75e-06,
W => Wcmout_2,
Wcmout_2init => 5.7e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net7,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 4.7e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias2,
S => net7
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 4.7e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net3,
G => vbias2,
S => net8
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 4.75e-06,
W => Wcm_2,
Wcm_2init => 9.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net8,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m3 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 4.75e-06,
W => Wcmout_2,
Wcmout_2init => 5.7e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net9,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 4.7e-05,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias2,
S => net9
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.35e-06,
W => Wcm_1,
Wcm_1init => 1.37e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.35e-06,
W => Wcmcout_1,
Wcmcout_1init => 5.025e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => (pfak)*(WBias),
WBiasinit => 7.25e-06
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.2e-06,
W => (pfak)*(WBias),
WBiasinit => 7.25e-06
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.2e-06,
W => WBias,
WBiasinit => 7.25e-06
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => WBias,
WBiasinit => 7.25e-06
)
port map(
D => vbias2,
G => vbias3,
S => net10
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => WBias,
WBiasinit => 7.25e-06
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.2e-06,
W => WBias,
WBiasinit => 7.25e-06
)
port map(
D => net10,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net11,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net11,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net11,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | 83c460ffb8455e747d3ad9eddc98ca92 | 0.582518 | 2.896699 | false | false | false | false |
daringer/schemmaker | testdata/new/circuit_bi1_0op960_17.vhdl | 1 | 6,411 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal vbias2: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias4: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net2,
G => in1,
S => net6
);
subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in2,
S => net6
);
subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net6,
G => vbias1,
S => vdd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net3,
G => vbias2,
S => net1
);
subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcasc_2,
scope => Wprivate,
symmetry_scope => sym_7
)
port map(
D => net4,
G => vbias2,
S => net2
);
subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net3,
G => vbias3,
S => net7
);
subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net7,
G => net3,
S => gnd
);
subnet0_subnet3_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet3_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net5,
G => vbias3,
S => net8
);
subnet0_subnet4_m1 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => net4,
G => vbias3,
S => net9
);
subnet0_subnet4_m2 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcm_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net9,
G => net4,
S => gnd
);
subnet0_subnet4_m3 : entity nmos(behave)
generic map(
L => Lcm_3,
W => Wcmout_3,
scope => private,
symmetry_scope => sym_8
)
port map(
D => net10,
G => net4,
S => gnd
);
subnet0_subnet4_m4 : entity nmos(behave)
generic map(
L => LBias,
W => Wcmcasc_3,
scope => Wprivate,
symmetry_scope => sym_8
)
port map(
D => out1,
G => vbias3,
S => net10
);
subnet0_subnet5_m1 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => net5,
G => vbias2,
S => net11
);
subnet0_subnet5_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net11,
G => net5,
S => vdd
);
subnet0_subnet5_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => net12,
G => net5,
S => vdd
);
subnet0_subnet5_m4 : entity pmos(behave)
generic map(
L => LBias,
W => Wcmcasc_1,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net12
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net13
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net13,
G => vbias4,
S => gnd
);
end simple;
| apache-2.0 | f4650d0a514c34d9a3b83523d0a9beed | 0.577445 | 3.110626 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/sampler/vhdl_source/sampler_accu.vhd | 5 | 2,960 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_pkg.all;
use work.mem_bus_pkg.all;
use work.sampler_pkg.all;
use work.my_math_pkg.all;
entity sampler_accu is
port (
clock : in std_logic;
reset : in std_logic;
first_chan : in std_logic;
sample_in : in signed(15 downto 0);
volume_in : in unsigned(5 downto 0);
pan_in : in unsigned(3 downto 0);
sample_L : out signed(17 downto 0);
sample_R : out signed(17 downto 0);
new_sample : out std_logic );
end entity;
architecture gideon of sampler_accu is
-- L R
-- 0000 = left 111 000
-- 0001 111 001
-- 0010 111 010
-- ...
-- 0111 = mid 111 111
-- 1000 = mid 111 111
-- ...
-- 1101 010 111
-- 1110 001 111
-- 1111 = right 000 111
signal pan_factor_L : signed(3 downto 0);
signal pan_factor_R : signed(3 downto 0);
signal sample_scaled : signed(16 downto 0);
signal first_scaled : std_logic;
signal accu_L : signed(20 downto 0);
signal accu_R : signed(20 downto 0);
signal current_L : signed(20 downto 0);
signal current_R : signed(20 downto 0);
attribute mult_style : string;
attribute mult_style of current_L : signal is "lut";
attribute mult_style of current_R : signal is "lut";
begin
--pan_factor_L <= "01000" when pan_in(3)='0' else "00" & signed(not(pan_in(2 downto 0)));
--pan_factor_R <= "01000" when pan_in(3)='1' else "00" & signed( pan_in(2 downto 0));
current_L <= sample_scaled * pan_factor_L;
current_R <= sample_scaled * pan_factor_R;
process(clock)
variable temp : signed(22 downto 0);
begin
if rising_edge(clock) then
-- stage 1
temp := sample_in * ('0' & signed(volume_in));
sample_scaled <= temp(21 downto 5);
first_scaled <= first_chan;
if pan_in(3)='0' then -- mostly left
pan_factor_L <= "0111";
pan_factor_R <= "0" & signed(pan_in(2 downto 0));
else -- mostly right
pan_factor_L <= "0" & signed(not pan_in(2 downto 0));
pan_factor_R <= "0111";
end if;
-- stage 2
if first_scaled='1' then
sample_L <= accu_L(accu_L'high downto accu_L'high-17);
sample_R <= accu_R(accu_R'high downto accu_R'high-17);
new_sample <= '1';
accu_L <= current_L;
accu_R <= current_R;
else
new_sample <= '0';
accu_L <= sum_limit(accu_L, current_L);
accu_R <= sum_limit(accu_R, current_R);
end if;
end if;
end process;
end architecture;
| gpl-3.0 | e464f2d0e850838bc59902edf0af3357 | 0.506081 | 3.418014 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/mem_ctrl/vhdl_source/ext_mem_ctrl.vhd | 5 | 14,613 | -------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 - Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : External Memory controller for SRAM / FLASH / SDRAM (no burst)
-------------------------------------------------------------------------------
-- File : ext_mem_ctrl.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single access memory controller.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity ext_mem_ctrl is
generic (
tag_width : integer := 2;
SRAM_Byte_Lanes : integer := 1;
SRAM_Data_Width : integer := 8;
SRAM_WR_ASU : integer := 0;
SRAM_WR_Pulse : integer := 1; -- 2 cycles in total
SRAM_WR_Hold : integer := 1;
SRAM_RD_ASU : integer := 0;
SRAM_RD_Pulse : integer := 1;
SRAM_RD_Hold : integer := 1; -- recovery time (bus turnaround)
FLASH_ASU : integer := 0;
FLASH_Pulse : integer := 3;
FLASH_Hold : integer := 1; -- bus turn around
A_Width : integer := 23;
SDRAM_Refr_period : integer := 375 );
port (
clock : in std_logic := '0';
clk_shifted : in std_logic := '0';
reset : in std_logic := '0';
inhibit : in std_logic;
is_idle : out std_logic;
req : in std_logic;
req_tag : in std_logic_vector(1 to tag_width) := (others => '0');
readwriten : in std_logic;
address : in std_logic_vector(25 downto 0); -- 64M Space
rack : out std_logic;
dack : out std_logic;
rack_tag : out std_logic_vector(1 to tag_width);
dack_tag : out std_logic_vector(1 to tag_width);
data_on_bus : out std_logic;
wdata : in std_logic_vector(SRAM_Data_Width-1 downto 0);
wdata_mask : in std_logic_vector(SRAM_Byte_Lanes-1 downto 0) := (others => '0');
rdata : out std_logic_vector(SRAM_Data_Width-1 downto 0);
io_rdata : in std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => '0');
dma_req : out std_logic;
dma_rwn : out std_logic;
dma_ok : in std_logic;
dma_ack : in std_logic := '0';
enable_refr : in std_logic := '0';
enable_sdram: in std_logic := '0';
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic;
SDRAM_RASn : out std_logic;
SDRAM_CASn : out std_logic;
SDRAM_WEn : out std_logic;
SRAM_CSn : out std_logic;
FLASH_CSn : out std_logic;
MEM_A : out std_logic_vector(A_Width-1 downto 0);
MEM_OEn : out std_logic;
MEM_WEn : out std_logic;
MEM_D : inout std_logic_vector(SRAM_Data_Width-1 downto 0) := (others => 'Z');
MEM_BEn : out std_logic_vector(SRAM_Byte_Lanes-1 downto 0) );
end ext_mem_ctrl;
-- ADDR: 25 24 23 ...
-- 0 0 0 ... SRAM
-- 0 0 1 ... C64 DMA
-- 0 1 0 ... Flash
-- 0 1 1 ... SDRAM command
-- 1 X X ... SDRAM (32MB)
architecture Gideon of ext_mem_ctrl is
type t_state is (idle, setup, pulse, hold, dma_access, recover, sd_cas, sd_wait);
signal state : t_state;
signal sram_d_o : std_logic_vector(MEM_D'range) := (others => '1');
signal sram_d_t : std_logic := '0';
signal delay : integer range 0 to 7;
signal rwn_i : std_logic;
signal tag : std_logic_vector(1 to tag_width);
signal memsel : std_logic_vector(1 downto 0);
signal mem_a_i : std_logic_vector(MEM_A'range) := (others => '0');
signal col_addr : std_logic_vector(9 downto 0) := (others => '0');
signal refresh_cnt : integer range 0 to SDRAM_Refr_period-1;
signal do_refresh : std_logic := '0';
signal not_clock : std_logic;
signal reg_out : integer range 0 to 3 := 0;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
-- attribute register_duplication : string;
-- attribute register_duplication of mem_a_i : signal is "no";
attribute iob : string;
attribute iob of rdata : signal is "true"; -- the general memctrl/rdata must be packed in IOB
begin
assert SRAM_WR_Hold > 0 report "Write hold time should be greater than 0." severity failure;
-- assert SRAM_RD_Hold > 0 report "Read hold time should be greater than 0 for bus turnaround." severity failure;
assert SRAM_WR_Pulse > 0 report "Write pulse time should be greater than 0." severity failure;
assert SRAM_RD_Pulse > 0 report "Read pulse time should be greater than 0." severity failure;
assert FLASH_Pulse > 0 report "Flash cmd pulse time should be greater than 0." severity failure;
assert FLASH_Hold > 0 report "Flash hold time should be greater than 0." severity failure;
is_idle <= '1' when state = idle else '0';
data_on_bus <= '1' when (state = pulse) and (delay = 2) and (tag(1)='1') else '0';
process(clock)
begin
if rising_edge(clock) then
rack <= '0';
dack <= '0';
rack_tag <= (others => '0');
dack_tag <= (others => '0');
if reg_out/=0 then
reg_out <= reg_out-1;
end if;
rdata <= MEM_D; -- clock in
SDRAM_CSn <= '1';
SDRAM_CKE <= enable_sdram;
case state is
when idle =>
if inhibit='0' then
dma_req <= '0';
if req='1' then
rack <= '1';
rack_tag <= req_tag;
tag <= req_tag;
rwn_i <= readwriten;
mem_a_i <= address(MEM_A'range);
memsel <= address(25 downto 24);
sram_d_t <= not readwriten;
sram_d_o <= wdata;
SRAM_CSn <= address(25) or address(24) or address(23); -- should be all '0' for CSn to become active
FLASH_CSn <= address(25) or not address(24) or address(23); -- '0' when A25..23 = 010
if address(25)='0' and do_refresh='1' then -- hidden refresh on dram
do_refresh <= '0';
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '0';
SDRAM_WEn <= '1'; -- Auto Refresh
end if;
if address(25)='1' then
mem_a_i(12 downto 0) <= address(24 downto 12); -- 13 row bits
mem_a_i(17 downto 16) <= address(11 downto 10); -- 2 bank bits
col_addr <= address( 9 downto 0); -- 10 column bits
SDRAM_CSn <= '0';
SDRAM_RASn <= '0';
SDRAM_CASn <= '1';
SDRAM_WEn <= '1'; -- Command = ACTIVE
sram_d_t <= '0'; -- no data yet
delay <= 1;
state <= sd_cas;
elsif address(24 downto 23)="10" then -- Flash
if FLASH_ASU=0 then
state <= pulse;
delay <= FLASH_Pulse;
else
delay <= FLASH_ASU;
state <= setup;
end if;
if readwriten='0' then -- write
MEM_BEn <= not wdata_mask;
MEM_WEn <= '0';
MEM_OEn <= '1';
else -- read
MEM_BEn <= (others => '0');
MEM_OEn <= '0';
MEM_WEn <= '1';
end if;
elsif address(24 downto 23)="11" then -- sdram command
SDRAM_CSn <= '0';
SDRAM_RASn <= address(13);
SDRAM_CASn <= address(14);
SDRAM_WEn <= address(15);
dack <= '1';
dack_tag <= req_tag;
state <= idle;
elsif address(24 downto 23)="01" then -- DMA
MEM_BEn <= (others => '1');
MEM_OEn <= '1';
MEM_WEn <= '1';
dma_req <= '1';
state <= dma_access;
sram_d_t <= '0';
else -- SRAM
if readwriten='0' then -- write
MEM_BEn <= not wdata_mask;
if SRAM_WR_ASU=0 then
state <= pulse;
MEM_WEn <= '0';
delay <= SRAM_WR_Pulse;
else
delay <= SRAM_WR_ASU;
state <= setup;
end if;
else -- read
MEM_BEn <= (others => '0');
MEM_OEn <= '0';
if SRAM_RD_ASU=0 then
state <= pulse;
delay <= SRAM_RD_Pulse;
else
delay <= SRAM_RD_ASU;
state <= setup;
end if;
end if;
end if;
end if;
else -- inhibit is active
dma_req <= '0';
sram_d_o <= io_rdata;
if dma_ok='1' then
sram_d_t <= '1';
reg_out <= 2;
end if;
if reg_out=2 then
dma_req <= '1';
elsif reg_out=1 then
sram_d_t <= '0';
end if;
end if;
when sd_cas =>
mem_a_i(10) <= '1'; -- auto precharge
mem_a_i(9 downto 0) <= col_addr;
if delay = 0 then
-- read or write with auto precharge
SDRAM_CSn <= '0';
SDRAM_RASn <= '1';
SDRAM_CASn <= '0';
SDRAM_WEn <= rwn_i;
if rwn_i='0' then -- write
sram_d_t <= '1';
end if;
delay <= 1;
state <= sd_wait;
else
delay <= delay - 1;
end if;
when sd_wait =>
sram_d_t <= '0';
if delay=0 then
dack <= '1';
dack_tag <= tag;
state <= idle;
else
delay <= delay - 1;
end if;
when setup =>
if delay = 1 then
state <= pulse;
if memsel(0)='0' then -- SRAM
if rwn_i='0' then
delay <= SRAM_WR_Pulse;
MEM_WEn <= '0';
else
delay <= SRAM_RD_Pulse;
MEM_OEn <= '0';
end if;
else
delay <= FLASH_Pulse;
if rwn_i='0' then
MEM_WEn <= '0';
else
MEM_OEn <= '0';
end if;
end if;
else
delay <= delay - 1;
end if;
when pulse =>
if delay = 1 then
MEM_OEn <= '1';
MEM_WEn <= '1';
dack <= '1';
dack_tag <= tag;
if memsel(0)='0' then -- SRAM
if rwn_i='0' and SRAM_WR_Hold > 0 then
delay <= SRAM_WR_Hold;
state <= hold;
elsif rwn_i='1' and SRAM_RD_Hold > 0 then
state <= hold;
delay <= SRAM_RD_Hold;
else
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '0';
state <= idle;
end if;
else -- Flash
if rwn_i='0' and FLASH_Hold > 0 then -- for writes, add hold cycles
delay <= FLASH_Hold;
state <= hold;
else
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '0';
state <= idle;
end if;
end if;
else
delay <= delay - 1;
end if;
when hold =>
if delay = 1 then
sram_d_t <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '0';
state <= idle;
else
delay <= delay - 1;
end if;
when dma_access =>
if dma_ok='1' then
sram_d_t <= not rwn_i;
end if;
if dma_ack='1' then
dma_req <= '0';
sram_d_t <= '0';
dack <= '1';
dack_tag <= tag;
state <= recover;
end if;
when recover =>
-- just a wait state to recover from glitches from disconnecting from the bus
state <= idle;
when others =>
null;
end case;
if refresh_cnt = SDRAM_Refr_period-1 then
do_refresh <= enable_refr;
refresh_cnt <= 0;
else
refresh_cnt <= refresh_cnt + 1;
end if;
if reset='1' then
state <= idle;
dma_req <= '0';
SRAM_CSn <= '1';
FLASH_CSn <= '0';
MEM_BEn <= (others => '1');
-- sram_d_o <= (others => '1');
sram_d_t <= '0';
MEM_OEn <= '1';
MEM_WEn <= '1';
delay <= 0;
tag <= (others => '0');
do_refresh <= '0';
end if;
end if;
end process;
dma_rwn <= rwn_i;
MEM_D <= sram_d_o when sram_d_t='1' else (others => 'Z');
MEM_A <= mem_a_i;
not_clock <= not clk_shifted;
clkout: FDDRRSE
port map (
CE => '1',
C0 => clk_shifted,
C1 => not_clock,
D0 => '0',
D1 => enable_sdram,
Q => SDRAM_CLK,
R => '0',
S => '0' );
end Gideon;
| gpl-3.0 | 99f1ed0b7a3e2f5a9925d04d5e32ed41 | 0.408198 | 3.822391 | false | false | false | false |
emabello42/FREAK-on-FPGA | embeddedretina_ise/PairSelector.vhd | 1 | 2,775 | --Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_I25VXL
-- /___/ /\ Timestamp : 04/06/2014 00:33:59
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity PairSelector is
port ( clk : in std_logic;
enableIn : in std_logic;
pointSet : in T_POINT_SET;
rst : in std_logic;
enableOut : out std_logic;
point1 : out std_logic_vector(OUT_HORIZ_CONV_BW-1 downto 0);
point2 : out std_logic_vector(OUT_HORIZ_CONV_BW-1 downto 0)
);
end PairSelector;
architecture BEHAVIORAL of PairSelector is
signal s_addr: integer range 0 to 511;
signal s_pointSetAux: T_POINT_SET;
signal s_enableAux: std_logic;
begin
load_points: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_pointSetAux <= (others => (others => '0'));
s_enableAux <= '0';
else
if enableIn = '1' then
for i in 0 to 511 loop
s_pointSetAux(i) <= pointSet(i);
end loop;
s_enableAux <= '1';
end if;
end if;
end if;
end process;
select_points: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
s_addr <= 0;
elsif s_enableAux = '1' then
point1 <= std_logic_vector(to_unsigned(ROM_PAIRS(s_addr)(0), point1'length));
point2 <= std_logic_vector(to_unsigned(ROM_PAIRS(s_addr)(1), point2'length));
end if;
enableOut <= s_enableAux;
end if;
end process;
end BEHAVIORAL;
| gpl-3.0 | bf5a312ec657eb49f57a6ae34e638187 | 0.606486 | 3.234266 | false | false | false | false |
scalable-networks/ext | uhd/fpga/usrp2/opencores/spi_boot/bench/vhdl/card.vhd | 2 | 12,497 | -------------------------------------------------------------------------------
--
-- SD/MMC Bootloader
-- Simple SD and MMC model
--
-- $Id: card.vhd,v 1.2 2005/02/13 17:06:22 arniml Exp $
--
-- Copyright (c) 2005, Arnim Laeuger ([email protected])
--
-- All rights reserved, see COPYING.
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/projects.cgi/web/spi_boot/overview
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity card is
generic (
card_type_g : string := "none";
is_sd_card_g : integer := 1
);
port (
spi_clk_i : in std_logic;
spi_cs_n_i : in std_logic;
spi_data_i : in std_logic;
spi_data_o : out std_logic
);
end card;
library ieee;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.tb_pack.all;
architecture behav of card is
signal power_on_n_s : std_logic;
signal soft_res_n_s : std_logic;
signal res_n_s : std_logic;
signal rx_s : std_logic_vector(47 downto 0);
signal set_spi_mode_s,
spi_mode_q : boolean;
signal set_idle_mode_s,
poll_idle_mode_s : boolean;
signal idle_mode_q : natural;
signal block_len_q,
block_len_s : unsigned(31 downto 0);
signal set_block_len_s : boolean;
signal new_read_addr_s,
read_addr_q : unsigned(31 downto 0);
signal set_read_addr_s,
inc_read_addr_s : boolean;
signal cmd_spi_data_s,
read_spi_data_s : std_logic;
signal start_read_s : boolean;
signal reading_s : boolean;
procedure rise_clk is
begin
wait until spi_clk_i'event and to_X01(spi_clk_i) = '1';
end rise_clk;
-- procedure rise_clk(num : natural) is
-- begin
-- for i in 1 to num loop
-- rise_clk;
-- end loop;
-- end rise_clk;
procedure fall_clk is
begin
wait until spi_clk_i'event and to_X01(spi_clk_i) = '0';
end fall_clk;
procedure fall_clk(num : natural) is
begin
for i in 1 to num loop
fall_clk;
end loop;
end fall_clk;
begin
res_n_s <= power_on_n_s and soft_res_n_s;
-----------------------------------------------------------------------------
-- Power on reset
-----------------------------------------------------------------------------
por: process
begin
power_on_n_s <= '0';
wait for 200 ns;
power_on_n_s <= '1';
wait;
end process por;
-----------------------------------------------------------------------------
--
ctrl: process
function check_crc(payload : in std_logic_vector(47 downto 0))
return boolean is
begin
return calc_crc(payload(47 downto 8)) = payload(7 downto 1);
end check_crc;
variable rx_v : std_logic_vector(47 downto 0);
variable cmd_v : std_logic_vector( 5 downto 0);
variable arg_v : std_logic_vector(31 downto 0);
variable crc_v : std_logic_vector( 6 downto 0);
variable wrong_v : std_logic;
variable read_data_v : boolean;
begin
rx_s <= (others => '0');
set_spi_mode_s <= false;
set_idle_mode_s <= false;
poll_idle_mode_s <= false;
cmd_spi_data_s <= '1';
soft_res_n_s <= '1';
set_block_len_s <= false;
block_len_s <= (others => '0');
new_read_addr_s <= (others => '0');
set_read_addr_s <= false;
start_read_s <= false;
read_data_v := false;
loop
rise_clk;
-- wait for startbit of command
while to_X01(spi_data_i) = '1' loop
rise_clk;
end loop;
rx_v(47) := '0';
-- read remaining 47 bits of command
for i in 46 downto 0 loop
rise_clk;
rx_v(i) := to_X01(spi_data_i);
end loop;
rx_s <= rx_v;
-- dissect received data
cmd_v := rx_v(45 downto 40);
arg_v := rx_v(39 downto 8);
crc_v := rx_v( 7 downto 1);
assert spi_mode_q or check_crc(payload => rx_v)
report "CRC mismatch"
severity error;
wrong_v := '0';
case cmd_v is
-- CMD0: GO_IDLE_STATE ------------------------------------------------
when "000000" =>
set_spi_mode_s <= true;
set_idle_mode_s <= true;
-- CMD1: SEND_OP_COND -------------------------------------------------
when "000001" =>
poll_idle_mode_s <= true;
-- CMD12: STOP_TRANSMISSION -------------------------------------------
when "001100" =>
start_read_s <= false;
read_data_v := false;
-- CMD16: SET_BLOCKLEN ------------------------------------------------
when "010000" =>
block_len_s <= unsigned(arg_v);
set_block_len_s <= true;
-- CMD18: READ_MULTIPLE_BLOCK -----------------------------------------
when "010010" =>
new_read_addr_s <= unsigned(arg_v);
set_read_addr_s <= true;
read_data_v := true;
-- CMD55: APPL_CMD ----------------------------------------------------
when "110111" =>
-- command only available for SD card
if is_sd_card_g /= 1 then
wrong_v := '1';
end if;
-- ACMD41: SEND_OP_COND -----------------------------------------------
when "101001" =>
-- command only available for SD card
if is_sd_card_g /= 1 then
wrong_v := '1';
else
poll_idle_mode_s <= true;
end if;
when others =>
wrong_v := '1';
null;
end case;
-- spend some time before removing control signals
fall_clk(2);
poll_idle_mode_s <= false;
set_idle_mode_s <= false;
fall_clk(6);
set_spi_mode_s <= false;
set_block_len_s <= false;
set_read_addr_s <= false;
if reading_s then
wait until not reading_s;
end if;
-- wait for a total two "bytes" before sending out response
for i in 1 to 8 loop
fall_clk;
end loop;
for i in 7 downto 0 loop
fall_clk;
case i is
when 2 =>
cmd_spi_data_s <= wrong_v;
when 0 =>
if idle_mode_q = 0 then
cmd_spi_data_s <= '0';
else
cmd_spi_data_s <= '1';
end if;
when others =>
cmd_spi_data_s <= '0';
end case;
end loop;
fall_clk;
cmd_spi_data_s <= '1';
-- transmit data if requested
start_read_s <= read_data_v;
end loop;
end process ctrl;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--
seq: process (res_n_s,
spi_clk_i,
set_spi_mode_s,
set_idle_mode_s,
poll_idle_mode_s,
set_block_len_s,
block_len_s)
begin
if res_n_s = '0' then
spi_mode_q <= false;
idle_mode_q <= 5;
block_len_q <= (others => '0');
read_addr_q <= (others => '0');
elsif spi_clk_i'event and spi_clk_i = '1' then
if set_spi_mode_s then
spi_mode_q <= true;
end if;
if set_idle_mode_s then
idle_mode_q <= 5;
elsif poll_idle_mode_s then
if idle_mode_q > 0 then
idle_mode_q <= idle_mode_q - 1;
end if;
end if;
if set_block_len_s then
block_len_q <= block_len_s;
end if;
if set_read_addr_s then
read_addr_q <= new_read_addr_s;
elsif inc_read_addr_s then
read_addr_q <= read_addr_q + 1;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--
read_block: process
variable t_v : unsigned(7 downto 0);
begin
-- default assignments
inc_read_addr_s <= false;
reading_s <= false;
read_spi_data_s <= '1';
loop
if not start_read_s then
wait until start_read_s;
end if;
reading_s <= true;
fall_clk(8); -- delay for one "byte"
-- send data token
fall_clk(7); -- 7 ones in a data token
read_spi_data_s <= '0';
-- send payload
payload: for i in 0 to to_integer(block_len_q)-1 loop
t_v := read_addr_q(0) & calc_crc(read_addr_q);
for bit in 7 downto 0 loop
fall_clk;
read_spi_data_s <= t_v(bit);
exit payload when not start_read_s;
end loop;
inc_read_addr_s <= true;
rise_clk;
inc_read_addr_s <= false;
wait for 10 ns;
end loop;
if start_read_s then
-- send crc
for i in 0 to 15 loop
fall_clk;
t_v := to_unsigned(i, 8);
read_spi_data_s <= t_v(0);
end loop;
fall_clk;
end if;
read_spi_data_s <= '1';
reading_s <= false;
-- loop for one "byte"
fall_clk(8);
end loop;
end process read_block;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
--
clk_check: process (spi_clk_i)
variable last_rising_v : time := 0 ns;
variable dump_line : line;
begin
if spi_clk_i'event and spi_clk_i = '1' then
if is_sd_card_g = 0 and card_type_g /= "Minimal Chip" and
idle_mode_q > 0 then
if now - last_rising_v < 2.5 us and last_rising_v > 0 ns then
write(dump_line, card_type_g);
write(dump_line, string'(" @ "));
write(dump_line, now);
write(dump_line, string'(": Last rising edge of SPI clock "));
write(dump_line, now - last_rising_v);
write(dump_line, string'(" ago."));
writeline(output, dump_line);
end if;
last_rising_v := now;
end if;
end if;
end process clk_check;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
spi_data_o <= cmd_spi_data_s and read_spi_data_s
when spi_cs_n_i = '0' else
'Z';
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: card.vhd,v $
-- Revision 1.2 2005/02/13 17:06:22 arniml
-- handle termination properly
--
-- Revision 1.1 2005/02/08 21:09:20 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
| gpl-2.0 | c69371355066486dde632e03fd89ed38 | 0.486757 | 3.836967 | false | false | false | false |
KB777/1541UltimateII | fpga/io/usb/vhdl_source/usb1_host_io.vhd | 2 | 15,415 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb1_pkg.all;
use work.io_bus_pkg.all;
use work.endianness_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity usb1_host_io is
generic (
g_simulation : boolean := false );
port (
ulpi_clock : in std_logic;
ulpi_reset : in std_logic;
-- ULPI Interface
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- LED interface
usb_busy : out std_logic;
-- register interface bus
sys_clock : in std_logic;
sys_reset : in std_logic;
sys_io_req : in t_io_req;
sys_io_resp : out t_io_resp );
end usb1_host_io;
architecture wrap of usb1_host_io is
signal descr_addr : std_logic_vector(8 downto 0);
signal descr_rdata : std_logic_vector(31 downto 0);
signal descr_wdata : std_logic_vector(31 downto 0);
signal descr_rdata_le : std_logic_vector(31 downto 0);
signal descr_wdata_le : std_logic_vector(31 downto 0);
signal descr_en : std_logic;
signal descr_we : std_logic;
signal buf_addr : std_logic_vector(10 downto 0);
signal buf_rdata : std_logic_vector(7 downto 0);
signal buf_wdata : std_logic_vector(7 downto 0);
signal buf_en : std_logic;
signal buf_we : std_logic;
signal tx_busy : std_logic;
signal tx_ack : std_logic;
signal send_token : std_logic;
signal send_handsh : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal tx_token : std_logic_vector(10 downto 0);
signal send_data : std_logic;
signal no_data : std_logic;
signal user_data : std_logic_vector(7 downto 0);
signal user_last : std_logic;
signal user_next : std_logic;
signal rx_pid : std_logic_vector(3 downto 0) := X"0";
signal rx_token : std_logic_vector(10 downto 0) := (others => '0');
signal valid_token : std_logic := '0';
signal valid_handsh : std_logic := '0';
signal valid_packet : std_logic := '0';
signal data_valid : std_logic := '0';
signal data_start : std_logic := '0';
signal data_out : std_logic_vector(7 downto 0) := X"12";
signal rx_error : std_logic := '0';
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0);
signal status : std_logic_vector(7 downto 0);
signal rx_last : std_logic;
signal rx_valid : std_logic;
signal rx_store : std_logic;
signal rx_register : std_logic;
signal reg_read : std_logic := '0';
signal reg_write : std_logic;
signal reg_ack : std_logic;
signal reg_addr : std_logic_vector(5 downto 0);
signal reg_wdata : std_logic_vector(7 downto 0);
signal send_reset_data : std_logic;
signal reset_last : std_logic;
signal reset_data : std_logic_vector(7 downto 0);
signal reset_done : std_logic;
signal sof_enable : std_logic;
signal scan_enable : std_logic;
signal speed : std_logic_vector(1 downto 0);
signal abort : std_logic;
signal sys_addr_i : std_logic_vector(sys_io_req.address'range);
signal sys_buf_en : std_logic;
signal sys_descr_en : std_logic;
signal sys_sel_d : std_logic_vector(2 downto 0);
signal sys_buf_rdata : std_logic_vector(7 downto 0);
signal sys_descr_rdata : std_logic_vector(7 downto 0);
signal sys_cmd_read : std_logic;
signal sys_cmd_write : std_logic;
signal sys_cmd_rdata : std_logic_vector(7 downto 0);
signal sys_cmd_full : std_logic;
signal sys_cmd_count : std_logic_vector(2 downto 0);
signal sys_resp_get : std_logic;
signal sys_resp_data : std_logic_vector(8 downto 0);
signal sys_resp_empty : std_logic;
signal cmd_get : std_logic;
signal cmd_empty : std_logic;
signal cmd_data : std_logic_vector(7 downto 0);
signal resp_put : std_logic;
signal resp_full : std_logic;
signal resp_data : std_logic_vector(8 downto 0);
begin
i_host: entity work.usb1_ulpi_host
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Descriptor RAM interface
descr_addr => descr_addr,
descr_rdata => descr_rdata,
descr_wdata => descr_wdata,
descr_en => descr_en,
descr_we => descr_we,
-- Buffer RAM interface
buf_addr => buf_addr,
buf_rdata => buf_rdata,
buf_wdata => buf_wdata,
buf_en => buf_en,
buf_we => buf_we,
-- Transmit Path Interface
tx_busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens and handshakes
send_token => send_token,
send_handsh => send_handsh,
tx_pid => tx_pid,
tx_token => tx_token,
-- Interface to send data packets
send_data => send_data,
no_data => no_data,
user_data => user_data,
user_last => user_last,
user_next => user_next,
-- Interface to bus reset unit
reset_done => reset_done,
sof_enable => sof_enable,
scan_enable => scan_enable,
speed => speed,
abort => abort,
-- Receive Path Interface
rx_pid => rx_pid,
rx_token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_valid => data_valid,
data_start => data_start,
data_out => data_out,
rx_error => rx_error );
i_descr_ram: RAMB16_S9_S36
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_descr_en,
WEA => sys_io_req.write,
ADDRA => sys_addr_i(10 downto 0),
DIA => sys_io_req.data,
DIPA => "0",
DOA => sys_descr_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => descr_en,
WEB => descr_we,
ADDRB => descr_addr,
DIB => descr_wdata_le,
DIPB => X"0",
DOB => descr_rdata_le );
descr_wdata_le <= byte_swap(descr_wdata);
descr_rdata <= byte_swap(descr_rdata_le);
i_buf_ram: RAMB16_S9_S9
port map (
CLKA => sys_clock,
SSRA => sys_reset,
ENA => sys_buf_en,
WEA => sys_io_req.write,
ADDRA => sys_addr_i(10 downto 0),
DIA => sys_io_req.data,
DIPA => "0",
DOA => sys_buf_rdata,
CLKB => ulpi_clock,
SSRB => ulpi_reset,
ENB => buf_en,
WEB => buf_we,
ADDRB => buf_addr(10 downto 0),
DIB => buf_wdata,
DIPB => "0",
DOB => buf_rdata );
i_tx: entity work.usb1_ulpi_tx
port map (
clock => ulpi_clock,
reset => ulpi_reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
-- Status
speed => speed,
status => status,
busy => tx_busy,
tx_ack => tx_ack,
-- Interface to send tokens
send_token => send_token,
send_handsh => send_handsh,
pid => tx_pid,
token => tx_token,
-- Interface to send data packets
send_data => send_data,
user_data => user_data,
user_last => user_last,
user_next => user_next,
-- Interface to read/write registers and reset packets
send_reset_data => send_reset_data,
reset_data => reset_data(0),
reset_last => reset_last );
i_rx: entity work.usb1_ulpi_rx
generic map (
g_allow_token => false )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => rx_pid,
token => rx_token,
valid_token => valid_token,
valid_handsh => valid_handsh,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => rx_error );
i_bus: entity work.usb1_ulpi_bus
port map (
clock => ulpi_clock,
reset => ulpi_reset,
ULPI_DATA => ULPI_DATA,
ULPI_DIR => ULPI_DIR,
ULPI_NXT => ULPI_NXT,
ULPI_STP => ULPI_STP,
status => status,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_addr,
reg_wdata => reg_wdata,
reg_ack => reg_ack,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_last => rx_last,
rx_register => rx_register,
rx_store => rx_store,
rx_valid => rx_valid );
i_reset: entity work.usb1_bus_reset
generic map (
g_simulation => g_simulation )
port map (
clock => ulpi_clock,
reset => ulpi_reset,
reset_done => reset_done,
sof_enable => sof_enable,
scan_enable => scan_enable,
speed => speed,
abort => abort,
-- Command / response interface
cmd_get => cmd_get,
cmd_empty => cmd_empty,
cmd_data => cmd_data,
resp_put => resp_put,
resp_full => resp_full,
resp_data => resp_data,
-- status
status => status,
usb_busy => usb_busy,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_rdata => rx_data,
reg_wdata => reg_wdata,
reg_address => reg_addr,
reg_ack => reg_ack,
-- interface to packet transmitter
send_packet => send_reset_data,
user_data => reset_data,
user_last => reset_last,
user_valid => open );
i_cmd_fifo: entity work.async_fifo
generic map (
g_data_width => 8,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 3,
g_storage => "distributed" )
port map (
-- write port signals (synchronized to write clock)
wr_clock => sys_clock,
wr_reset => sys_reset,
wr_en => sys_cmd_write,
wr_din => sys_io_req.data,
wr_flush => '0',
wr_count => sys_cmd_count,
wr_full => open,
wr_almost_full => sys_cmd_full,
wr_error => open,
wr_inhibit => open,
-- read port signals (synchronized to read clock)
rd_clock => ulpi_clock,
rd_reset => ulpi_reset,
rd_en => cmd_get,
rd_dout => cmd_data,
rd_count => open,
rd_empty => cmd_empty,
rd_almost_empty => open,
rd_error => open );
i_resp_fifo: entity work.async_fifo
generic map (
g_data_width => 9,
g_depth_bits => 3,
g_count_bits => 3,
g_threshold => 3,
g_storage => "distributed" )
port map (
-- write port signals (synchronized to write clock)
wr_clock => ulpi_clock,
wr_reset => ulpi_reset,
wr_en => resp_put,
wr_din => resp_data,
wr_flush => '0',
wr_count => open,
wr_full => resp_full,
wr_almost_full => open,
wr_error => open,
wr_inhibit => open,
-- read port signals (synchronized to read clock)
rd_clock => sys_clock,
rd_reset => sys_reset,
rd_en => sys_resp_get,
rd_dout => sys_resp_data,
rd_count => open,
rd_empty => sys_resp_empty,
rd_almost_empty => open,
rd_error => open );
-- BUS INTERFACE --
-- command / response output word generator
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_resp_get <= '0';
case sys_io_req.address(1 downto 0) is
when "00" =>
sys_cmd_rdata <= sys_resp_data(7 downto 0);
when "01" =>
sys_cmd_rdata <= not sys_resp_empty & "000000" & sys_resp_data(8);
when "10" =>
sys_cmd_rdata <= sys_cmd_full & "0000" & sys_cmd_count;
when "11" =>
sys_cmd_rdata <= X"00";
sys_resp_get <= sys_cmd_read; -- if reading, we'll pull one
when others =>
null;
end case;
end if;
end process;
sys_addr_i(sys_addr_i'high downto 0) <= std_logic_vector(sys_io_req.address(sys_addr_i'range));
sys_buf_en <= (sys_io_req.read or sys_io_req.write) and sys_io_req.address(12);
sys_descr_en <= (sys_io_req.read or sys_io_req.write) and not sys_io_req.address(12) and not sys_io_req.address(11);
sys_cmd_read <= sys_io_req.read and not sys_io_req.address(12) and sys_io_req.address(11);
sys_cmd_write <= sys_io_req.write and not sys_io_req.address(12) and sys_io_req.address(11);
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_io_resp.ack <= sys_io_req.read or sys_io_req.write;
sys_sel_d <= sys_io_req.read & std_logic_vector(sys_io_req.address(12 downto 11));
end if;
end process;
with sys_sel_d select sys_io_resp.data <=
sys_buf_rdata when "110" | "111",
sys_descr_rdata when "100",
sys_cmd_rdata when "101",
X"00" when others;
end wrap;
| gpl-3.0 | 99da6f3b5091dc8f0581af7ac670350f | 0.480765 | 3.620244 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_source/bus_reset.vhd | 3 | 13,020 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb_pkg.all;
entity bus_reset is
generic (
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
reset_done : out std_logic;
sof_enable : out std_logic;
scan_enable : out std_logic;
speed : out std_logic_vector(1 downto 0);
abort : out std_logic;
-- status
status : in std_logic_vector(7 downto 0);
usb_busy : out std_logic;
-- command response interface
cmd_empty : in std_logic;
cmd_data : in std_logic_vector(7 downto 0);
cmd_get : out std_logic;
resp_full : in std_logic;
resp_put : out std_logic;
resp_data : out std_logic_vector(8 downto 0);
-- register interface
reg_read : out std_logic;
reg_write : out std_logic;
reg_rdata : in std_logic_vector(7 downto 0);
reg_wdata : out std_logic_vector(7 downto 0);
reg_address : out std_logic_vector(5 downto 0);
reg_ack : in std_logic;
send_packet : out std_logic;
user_data : out std_logic_vector(7 downto 0);
user_last : out std_logic;
user_valid : out std_logic );
end bus_reset;
architecture functional of bus_reset is
type t_state is (idle, start_reset, set_se0, listen_chirp,
wait_chirp_end, setup_chirp, hub_chirp_k, hub_chirp_j,
reset_end, reset_finished,
user_reg_read, user_reg_write, user_write_2, send_resp );
type t_int_bool_array is array(boolean) of integer;
constant c_reset_times : t_int_bool_array := (false => 60000*15, true => 2097); -- 4194303
constant c_latest_chirp : t_int_bool_array := (false => 80000, true => 400); -- not used anymore, as we don't wait for the device chirp to end
constant c_stop_chirp : t_int_bool_array := (false => 20000, true => 100);
constant c_chirp_jk : t_int_bool_array := (false => 3000, true => 20);
constant c_filter_times : t_int_bool_array := (false => 255, true => 10);
signal state : t_state;
signal speed_i : std_logic_vector(1 downto 0);
signal low_speed : std_logic;
signal disable_hs : std_logic;
signal t0_expired : std_logic;
signal t2_expired : std_logic := '0';
signal timer_0 : integer range 0 to 4194303; -- ~ 70 ms
signal timer_1 : integer range 0 to 8191; -- ~ 136 us
signal timer_2 : integer range 0 to 31 := 31; -- 500 ns
signal stop_chirp : std_logic;
signal reset_done_i : std_logic;
signal latest_chirp_start : std_logic;
signal cmd_valid : std_logic;
signal cmd_get_i : std_logic;
signal debug : std_logic;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
begin
speed <= speed_i;
reset_done <= reset_done_i;
cmd_get <= cmd_get_i;
cmd_get_i <= '1' when cmd_empty='0' and cmd_valid='0' and (state=idle or state=user_reg_write)
else '0';
p_reset: process(clock)
begin
if rising_edge(clock) then
if timer_0 = 0 then
t0_expired <= '1';
else
timer_0 <= timer_0 - 1;
end if;
if timer_0 = c_stop_chirp(g_simulation) then
stop_chirp <= '1';
end if;
if timer_0 = c_latest_chirp(g_simulation) then
latest_chirp_start <= '1';
end if;
if timer_2 = 0 then
t2_expired <= '1';
else
timer_2 <= timer_2 - 1;
end if;
cmd_valid <= cmd_get_i;
resp_put <= '0';
abort <= '0';
case state is
when idle =>
reg_address <= cmd_data(5 downto 0);
if cmd_valid = '1' then
case cmd_data(7 downto 6) is
when "00" =>
debug <= '0';
case cmd_data(3 downto 0) is
when c_cmd_get_status =>
resp_data <= "0" & status;
state <= send_resp;
when c_cmd_get_done =>
resp_data <= X"00" & reset_done_i;
state <= send_resp;
when c_cmd_get_speed =>
resp_data <= "0000000" & speed_i;
state <= send_resp;
when c_cmd_do_reset_hs =>
disable_hs <= '0';
state <= start_reset;
when c_cmd_do_reset_fs =>
disable_hs <= '1';
state <= start_reset;
when c_cmd_disable_host =>
reset_done_i <= '0';
when c_cmd_abort =>
abort <= '1';
when c_cmd_sof_enable =>
sof_enable <= '1';
when c_cmd_sof_disable =>
sof_enable <= '0';
when c_cmd_set_busy =>
usb_busy <= '1';
when c_cmd_clear_busy =>
usb_busy <= '0';
when c_cmd_disable_scan =>
scan_enable <= '0';
when c_cmd_enable_scan =>
scan_enable <= '1';
when c_cmd_set_debug =>
debug <= '1';
when others =>
if debug='1' then
resp_data <= '0' & X"AB";
else
resp_data <= '0' & X"AA";
end if;
state <= send_resp;
end case;
when "11" =>
state <= user_reg_write;
when "10" =>
reg_read <= '1';
state <= user_reg_read;
when others =>
null;
end case;
end if;
when user_reg_read =>
if reg_ack = '1' then
reg_read <= '0';
resp_data <= "1" & reg_rdata;
state <= send_resp;
end if;
when user_reg_write =>
if cmd_valid = '1' then
reg_wdata <= cmd_data;
reg_write <= '1';
state <= user_write_2;
end if;
when user_write_2 =>
if reg_ack = '1' then
reg_write <= '0';
state <= idle;
end if;
when send_resp =>
if resp_full = '0' then
resp_put <= '1';
state <= idle;
end if;
when start_reset =>
timer_0 <= c_reset_times(g_simulation);
latest_chirp_start <= '0';
t0_expired <= '0';
stop_chirp <= '0';
reset_done_i <= '0';
low_speed <= '0';
if status(5 downto 2) /= "0011" then
speed_i <= "11"; -- not powered or rx active
state <= idle;
else
if status(1)='1' then
low_speed <= '1';
speed_i <= "00"; -- Low speed
else
speed_i <= "01"; -- assume FS
end if;
state <= set_se0;
end if;
when set_se0 =>
reg_address <= std_logic_vector(to_unsigned(4, reg_address'length));
reg_write <= '1';
reg_wdata <= X"50";
timer_1 <= c_filter_times(g_simulation); -- reset timer 1 (4.25 �s)
if reg_ack = '1' then
reg_write <= '0';
if low_speed='1' or disable_hs='1' then
state <= reset_end;
else
state <= listen_chirp;
end if;
end if;
when listen_chirp =>
if t0_expired='1' then
state <= reset_end; -- no chirp detected
elsif status(1)='0' then
timer_1 <= c_filter_times(g_simulation); -- reset timer
elsif timer_1 = 0 then -- chirp detected
speed_i <= "10"; -- HS!
state <= setup_chirp; -- Let's be RUDE and just send our chirp back -- wait_chirp_end;
timer_1 <= 2 * c_chirp_jk(g_simulation);
else
timer_1 <= timer_1 - 1;
end if;
when wait_chirp_end =>
if t0_expired='1' then
speed_i <= "11"; -- error
state <= reset_end;
elsif status(1)='0' then
if timer_1 = 0 then
if latest_chirp_start = '1' then
speed_i <= "11";
state <= reset_end;
else
state <= setup_chirp;
end if;
else
timer_1 <= timer_1 - 1;
end if;
else
timer_1 <= 2 * c_chirp_jk(g_simulation); -- reset timer
end if;
when setup_chirp =>
timer_1 <= c_chirp_jk(g_simulation);
send_packet <= '1';
state <= hub_chirp_k;
when hub_chirp_k =>
user_data <= X"00";
user_valid <= '1';
user_last <= '0';
send_packet <= '0';
if timer_1 = 0 then
if stop_chirp = '1' then
state <= reset_end;
user_last <= '1'; -- data is still 0
else
user_data <= X"FF";
state <= hub_chirp_j;
timer_1 <= c_chirp_jk(g_simulation);
end if;
else
timer_1 <= timer_1 - 1;
end if;
when hub_chirp_j =>
if timer_1 = 0 then
timer_1 <= c_chirp_jk(g_simulation);
user_data <= X"00";
state <= hub_chirp_k;
else
timer_1 <= timer_1 - 1;
end if;
when reset_end =>
user_valid <= '0';
user_last <= '0';
if t0_expired = '1' then
reg_address <= std_logic_vector(to_unsigned(4, reg_address'length));
reg_write <= '1';
reg_wdata <= map_speed(speed_i) or X"20"; -- reset bit set
state <= reset_finished;
end if;
when reset_finished =>
if reg_ack='1' then
reg_write <= '0';
reset_done_i <= '1';
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
disable_hs <= '0';
speed_i <= "11"; -- error or uninitialized
state <= idle;
reset_done_i <= '0';
sof_enable <= '0';
scan_enable <= '1';
user_data <= X"00";
user_last <= '0';
user_valid <= '0';
send_packet <= '0';
reg_read <= '0';
reg_write <= '0';
reg_wdata <= X"00";
reg_address <= (others => '0');
resp_data <= (others => '0');
timer_2 <= 31;
t2_expired <= '0';
low_speed <= '0';
stop_chirp <= '0';
latest_chirp_start <= '0';
usb_busy <= '0';
debug <= '0';
end if;
end if;
end process;
end functional;
| gpl-3.0 | b722614674de382869711890bda739e5 | 0.379628 | 4.334998 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/icap/vhdl_source/icap.vhd | 5 | 2,989 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.icap_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity icap is
generic (
g_fpga_type : std_logic_vector(7 downto 0) := X"3A" );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end icap;
architecture spartan_3a of icap is
type t_state is (idle, pulse, hold);
signal state : t_state;
signal icap_cen : std_logic := '1';
signal icap_data : std_logic_vector(0 to 7);
signal icap_clk : std_logic := '0';
function swap_bits(s : std_logic_vector) return std_logic_vector is
variable in_vec : std_logic_vector(s'length downto 1) := s;
variable out_vec : std_logic_vector(1 to s'length);
begin
for i in in_vec'range loop
out_vec(i) := in_vec(i);
end loop;
return out_vec;
end swap_bits;
begin
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
case state is
when idle =>
if io_req.write='1' then
case io_req.address(3 downto 0) is
when c_icap_pulse =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '0';
state <= pulse;
when c_icap_write =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '1';
state <= pulse;
when others =>
io_resp.ack <= '1';
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_icap_fpga_type =>
io_resp.data <= g_fpga_type;
when others =>
null;
end case;
end if;
when pulse =>
icap_clk <= '1';
state <= hold;
when hold =>
icap_clk <= '0';
io_resp.ack <= '1';
state <= idle;
when others =>
null;
end case;
if reset='1' then
state <= idle;
icap_data <= X"00";
icap_cen <= '1';
icap_clk <= '0';
end if;
end if;
end process;
i_icap: ICAP_SPARTAN3A
port map (
CLK => icap_clk,
CE => icap_cen,
WRITE => icap_cen,
I => icap_data,
O => open,
BUSY => open );
end architecture;
| gpl-3.0 | 364467ac3f21cc343d1e02dff707be49 | 0.411174 | 4.001339 | false | false | false | false |
daringer/schemmaker | testdata/harder/circuit_bi1_0op331_17sk1_0.vhdl | 1 | 7,874 | package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias1: electrical;
terminal vdd: electrical;
terminal gnd: electrical;
terminal vbias3: electrical;
terminal vbias2: electrical;
terminal vbias4: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
terminal net8: electrical;
terminal net9: electrical;
terminal net10: electrical;
terminal net11: electrical;
terminal net12: electrical;
terminal net13: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.6e-06,
W => Wdiff_0,
Wdiff_0init => 5.6e-05,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity pmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 4.6e-06,
W => Wdiff_0,
Wdiff_0init => 5.6e-05,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => W_0,
W_0init => 1.285e-05
)
port map(
D => net5,
G => vbias1,
S => vdd
);
subnet0_subnet0_subnet1_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 2.8e-06,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net2,
G => vbias3,
S => net6
);
subnet0_subnet0_subnet1_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.6e-06,
W => Wcm_2,
Wcm_2init => 1.45e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net6,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.6e-06,
W => Wcmout_2,
Wcmout_2init => 5.05e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net7,
G => net2,
S => gnd
);
subnet0_subnet0_subnet1_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 2.8e-06,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => out1,
G => vbias3,
S => net7
);
subnet0_subnet0_subnet2_m1 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 2.8e-06,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net3,
G => vbias3,
S => net8
);
subnet0_subnet0_subnet2_m2 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.6e-06,
W => Wcm_2,
Wcm_2init => 1.45e-06,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net8,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m3 : entity nmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.6e-06,
W => Wcmout_2,
Wcmout_2init => 5.05e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net9,
G => net3,
S => gnd
);
subnet0_subnet0_subnet2_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => Wcmcasc_2,
Wcmcasc_2init => 2.8e-06,
scope => Wprivate,
symmetry_scope => sym_5
)
port map(
D => net4,
G => vbias3,
S => net9
);
subnet0_subnet0_subnet3_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 4.175e-05,
scope => Wprivate
)
port map(
D => net4,
G => vbias2,
S => net10
);
subnet0_subnet0_subnet3_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.8e-06,
W => Wcm_1,
Wcm_1init => 2.535e-05,
scope => private
)
port map(
D => net10,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m3 : entity pmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 5.8e-06,
W => Wcmout_1,
Wcmout_1init => 4.13e-05,
scope => private
)
port map(
D => net11,
G => net4,
S => vdd
);
subnet0_subnet0_subnet3_m4 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => Wcmcasc_1,
Wcmcasc_1init => 4.175e-05,
scope => Wprivate
)
port map(
D => out1,
G => vbias2,
S => net11
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => (pfak)*(WBias),
WBiasinit => 3.385e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.65e-06,
W => (pfak)*(WBias),
WBiasinit => 3.385e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 1.65e-06,
W => WBias,
WBiasinit => 3.385e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => WBias,
WBiasinit => 3.385e-05
)
port map(
D => vbias2,
G => vbias3,
S => net12
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => WBias,
WBiasinit => 3.385e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 1.65e-06,
W => WBias,
WBiasinit => 3.385e-05
)
port map(
D => net12,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net13,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net13,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net13,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
| apache-2.0 | e8c449e51ad602939fb2119d14ddb361 | 0.583185 | 2.889541 | false | false | false | false |
KB777/1541UltimateII | legacy/2.6k/fpga/io/usb/vhdl_sim/tb_ulpi_rx.vhd | 3 | 3,139 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ulpi_rx is
end entity;
architecture tb of tb_ulpi_rx is
signal clock : std_logic := '0';
signal reset : std_logic;
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_last : std_logic := '0';
signal rx_valid : std_logic := '0';
signal rx_store : std_logic := '0';
signal pid : std_logic_vector(3 downto 0);
signal valid_token : std_logic;
signal token : std_logic_vector(10 downto 0);
signal valid_packet : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_valid : std_logic;
signal data_start : std_logic;
signal error : std_logic;
type t_std_logic_8_vector is array (natural range <>) of std_logic_vector(7 downto 0);
begin
clock <= not clock after 10 ns;
reset <= '1', '0' after 100 ns;
i_rx: entity work.ulpi_rx
port map (
clock => clock,
reset => reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
pid => pid,
valid_token => valid_token,
token => token,
valid_packet => valid_packet,
data_out => data_out,
data_valid => data_valid,
data_start => data_start,
error => error );
process
procedure packet(pkt : t_std_logic_8_vector) is
begin
for i in pkt'range loop
wait until clock='1';
rx_data <= pkt(i);
rx_valid <= '1';
rx_store <= '1';
if i = pkt'right then
rx_last <= '1';
else
rx_last <= '0';
end if;
end loop;
wait until clock='1';
rx_valid <= '0';
rx_last <= '0';
wait until clock='1';
wait until clock='1';
wait until clock='1';
end procedure packet;
begin
wait until reset='0';
wait until clock='1';
packet((X"A5", X"63", X"A9"));
packet((X"4B", X"00", X"00")); -- data1, length=0, crc = 0000
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- good crc
packet((X"C3", X"00", X"01", X"02", X"03", X"04", X"05", X"06",
X"07", X"08", X"09", X"03", X"0B", X"0C", X"0D", X"0E",
X"0F", X"10", X"19", X"44")); -- bad crc
packet((0=>X"D2")); -- good handshake
packet((0=>X"C3")); -- bad handshake (wrong pid data)
packet((0=>X"A5")); -- bad handshake (wrong pid token)
wait;
end process;
end tb;
| gpl-3.0 | 019dd89ad0c9de7e5cd77e6e33519f65 | 0.435489 | 3.542889 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/dds/xbip_dsp48_multadd_v3_0/hdl/xbip_dsp48_multadd_v3_0_pkg.vhd | 4 | 18,863 | `protect begin_protected
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| gpl-2.0 | 8c1619bf21ecdc4ce54bf0fe947a377b | 0.938557 | 1.865223 | false | false | false | false |
FlatTargetInk/UMD_RISC-16G5 | Lab2/Code/RPNCalc/RPN_toplevel.vhd | 1 | 4,722 | ----------------------------------------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Electrical and Computer Engineering
-- Engineers:
--
-- Create Date: 16:43:51 02/12/2016
-- Design Name:
-- Module Name: RPN_toplevel - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity RPN_toplevel is
Port (CLK : in STD_LOGIC;
BTN : in STD_LOGIC_VECTOR (3 downto 0);
SW : in STD_LOGIC_VECTOR (7 downto 0);
AN : out STD_LOGIC_VECTOR (3 downto 0);
SEG : out STD_LOGIC_VECTOR (7 downto 0));
end RPN_toplevel;
architecture Structural of RPN_toplevel is -- Structural changed from Behavioral
signal DBTN : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RA : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal RB : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal OPCODE : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RFLAGS : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal RESULT : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ENABLED : STD_LOGIC := '1';
signal DISABLED : STD_LOGIC := '0';
signal s2 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
signal s3 : STD_LOGIC_VECTOR (3 downto 0) := "0000";
-- ALU Stuff --
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
-- Debounce Units --
BTN_0: entity work.debounce
port map( CLK => CLK,
EN => ENABLED, -- Make This a 1 --
INPUT => BTN(0),
OUTPUT => DBTN(0));
BTN_1: entity work.debounce
port map( CLK => CLK,
EN => ENABLED, -- Make this a 1 --
INPUT => BTN(1),
OUTPUT => DBTN(1));
BTN_2: entity work.debounce
port map( CLK => CLK,
EN => ENABLED, -- Make this a 1
INPUT => BTN(2),
OUTPUT => DBTN(2));
BTN_3: entity work.debounce
port map( CLK => CLK,
EN => ENABLED, -- Make this a 1
INPUT => BTN(3),
OUTPUT => DBTN(3));
-- Action units --
UXCntl_Unit: entity work.UXCntl_Unit
port map(INPUT => SW,
CMD => DBTN,
VALA => RA,
VALB => RB,
OPCODE => OPCODE);
-- ALU Unit --
-- LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => RESULT, -- FORMERLY ALU_OUT
CCR_OUT => RFLAGS); -- FORMERLY CCR
-- Display Unit --
SSeg: entity work.SSegDriver
port map( CLK => CLK,
RST => DISABLED,
EN => ENABLED,
SEG_3 => RESULT(3 downto 0),
SEG_2 => RESULT(7 downto 4),
SEG_1 => s2,
SEG_0 => s3,
DP_CTRL => s3,
COL_EN => DISABLED,
SEG_OUT => SEG(6 downto 0),
DP_OUT => s2(1),
AN_OUT => AN(3 downto 0));
end Structural;
| gpl-3.0 | e7c9571cc854464818dd3e383261a4c4 | 0.480305 | 3.531788 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_1/part_1/top.vhd | 1 | 1,433 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 06.03.2014 15:08:57
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( gclk : in STD_LOGIC;
leds : out STD_LOGIC_VECTOR (7 downto 0));
end top;
architecture Behavioral of top is
signal timer: std_logic_vector(25 downto 0);
signal state: std_logic := '0';
begin
process(gclk) begin
if(gclk'event and gclk='1')then
if(timer < 50000000)then
timer <= timer +1;
else
timer <= (others=>'0');
leds <= (others=>state);
state <= not state;
end if;
end if;
end process;
end Behavioral;
| gpl-2.0 | 4fc58684e0198513c27a4fad67a00c27 | 0.575715 | 3.894022 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/floating_point_v7_0/hdl/flt_mult/flt_mult_round/flt_mult_round.vhd | 3 | 18,798 | `protect begin_protected
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| gpl-2.0 | a0a2d2cbb8b8881733918b8a29f7b5d5 | 0.938557 | 1.856959 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_2/part_4/ip/clk_video/clk_video_clk_wiz.vhd | 3 | 7,381 | -- file: clk_video_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_video_clk_wiz is
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_193MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_video_clk_wiz;
architecture xilinx of clk_video_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_100MHz_clk_video : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clk_video : std_logic;
signal clkfbout_buf_clk_video : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_193MHz_clk_video : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_bufg : BUFG
port map
(O => clk_100MHz_clk_video,
I => clk_100MHz);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 10.125,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 9.375,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clk_video,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_193MHz_clk_video,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clk_video,
CLKIN1 => clk_100MHz_clk_video,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clk_video,
I => clkfbout_clk_video);
clkout1_buf : BUFG
port map
(O => clk_193MHz,
I => clk_193MHz_clk_video);
end xilinx;
| gpl-2.0 | ca89b3e8db5cd866bfeddbf74d077826 | 0.572687 | 4.264009 | false | false | false | false |
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| gpl-2.0 | 6dad35d5196401a10036531f275ff435 | 0.927591 | 1.899241 | false | false | false | false |
keith-epidev/VHDL-lib | top/stereo_radio/ip/xfft/xbip_dsp48_wrapper_v3_0/hdl/xbip_dsp48a_wrapper_v3_0.vhd | 7 | 18,409 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11888)
`protect data_block
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`protect end_protected
| gpl-2.0 | d341b9ae8644126bb59c83e332a84973 | 0.940464 | 1.867228 | false | false | false | false |
notti/dis_se | testbench/tb_cpu.vhd | 1 | 17,957 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
use work.procedures.all;
entity tb_cpu is
end tb_cpu;
architecture behav of tb_cpu is
signal rst : std_logic := '1';
signal clk : std_logic := '0';
signal clk2x : std_logic := '0';
signal ena : std_logic := '0';
signal addra : t_data2 := (others => '0');
signal doa : t_data2 := (others => '0');
signal enb : std_logic := '0';
signal addrb : t_data2 := (others => '0');
signal dob : t_data2 := (others => '0');
signal web : std_logic_vector(1 downto 0) := (others => '0');
signal dib : t_data2 := (others => '0');
signal bbusy : std_logic := '0';
signal mem : t_data2_array(4095 downto 0) := (others => (others => '0'));
signal serial : t_data_array(1023 downto 0) :=
(0 => X"55",
1 => X"AA",
2 => X"00",
3 => X"00",
4 => X"1a",
5 => X"00",
6 => X"34",
7 => X"00",
8 => X"4b",
9 => X"00",
10 => X"5f",
11 => X"00",
12 => X"6e",
13 => X"00",
14 => X"79",
15 => X"00",
16 => X"7f",
17 => X"00",
18 => X"7f",
19 => X"00",
20 => X"79",
21 => X"00",
22 => X"6e",
23 => X"00",
24 => X"5f",
25 => X"00",
26 => X"4b",
27 => X"00",
28 => X"34",
29 => X"00",
30 => X"1a",
31 => X"00",
32 => X"00",
33 => X"00",
34 => X"e6",
35 => X"00",
36 => X"cc",
37 => X"00",
38 => X"b5",
39 => X"00",
40 => X"a1",
41 => X"00",
42 => X"92",
43 => X"00",
44 => X"87",
45 => X"00",
46 => X"81",
47 => X"00",
48 => X"81",
49 => X"00",
50 => X"87",
51 => X"00",
52 => X"92",
53 => X"00",
54 => X"a1",
55 => X"00",
56 => X"b5",
57 => X"00",
58 => X"cc",
59 => X"00",
60 => X"e6",
61 => X"00",
62 => X"00",
63 => X"00",
64 => X"1a",
65 => X"00",
66 => X"34",
67 => X"00",
68 => X"4b",
69 => X"00",
70 => X"5f",
71 => X"00",
72 => X"6e",
73 => X"00",
74 => X"79",
75 => X"00",
76 => X"7f",
77 => X"00",
78 => X"7f",
79 => X"00",
80 => X"79",
81 => X"00",
82 => X"6e",
83 => X"00",
84 => X"5f",
85 => X"00",
86 => X"4b",
87 => X"00",
88 => X"34",
89 => X"00",
90 => X"1a",
91 => X"00",
92 => X"00",
93 => X"00",
94 => X"e6",
95 => X"00",
96 => X"cc",
97 => X"00",
98 => X"b5",
99 => X"00",
100 => X"a1",
101 => X"00",
102 => X"92",
103 => X"00",
104 => X"87",
105 => X"00",
106 => X"81",
107 => X"00",
108 => X"81",
109 => X"00",
110 => X"87",
111 => X"00",
112 => X"92",
113 => X"00",
114 => X"a1",
115 => X"00",
116 => X"b5",
117 => X"00",
118 => X"cc",
119 => X"00",
120 => X"e6",
121 => X"00",
122 => X"00",
123 => X"00",
124 => X"1a",
125 => X"00",
126 => X"34",
127 => X"00",
128 => X"4b",
129 => X"00",
130 => X"5f",
131 => X"00",
132 => X"6e",
133 => X"00",
134 => X"79",
135 => X"00",
136 => X"7f",
137 => X"00",
138 => X"7f",
139 => X"00",
140 => X"79",
141 => X"00",
142 => X"6e",
143 => X"00",
144 => X"5f",
145 => X"00",
146 => X"4b",
147 => X"00",
148 => X"34",
149 => X"00",
150 => X"1a",
151 => X"00",
152 => X"00",
153 => X"00",
154 => X"e6",
155 => X"00",
156 => X"cc",
157 => X"00",
158 => X"b5",
159 => X"00",
160 => X"a1",
161 => X"00",
162 => X"92",
163 => X"00",
164 => X"87",
165 => X"00",
166 => X"81",
167 => X"00",
168 => X"81",
169 => X"00",
170 => X"87",
171 => X"00",
172 => X"92",
173 => X"00",
174 => X"a1",
175 => X"00",
176 => X"b5",
177 => X"00",
178 => X"cc",
179 => X"00",
180 => X"e6",
181 => X"00",
182 => X"00",
183 => X"00",
184 => X"1a",
185 => X"00",
186 => X"34",
187 => X"00",
188 => X"4b",
189 => X"00",
190 => X"5f",
191 => X"00",
192 => X"6e",
193 => X"00",
194 => X"79",
195 => X"00",
196 => X"7f",
197 => X"00",
198 => X"7f",
199 => X"00",
200 => X"79",
201 => X"00",
202 => X"6e",
203 => X"00",
204 => X"5f",
205 => X"00",
206 => X"4b",
207 => X"00",
208 => X"34",
209 => X"00",
210 => X"1a",
211 => X"00",
212 => X"00",
213 => X"00",
214 => X"e6",
215 => X"00",
216 => X"cc",
217 => X"00",
218 => X"b5",
219 => X"00",
220 => X"a1",
221 => X"00",
222 => X"92",
223 => X"00",
224 => X"87",
225 => X"00",
226 => X"81",
227 => X"00",
228 => X"81",
229 => X"00",
230 => X"87",
231 => X"00",
232 => X"92",
233 => X"00",
234 => X"a1",
235 => X"00",
236 => X"b5",
237 => X"00",
238 => X"cc",
239 => X"00",
240 => X"e6",
241 => X"00",
242 => X"00",
243 => X"00",
244 => X"1a",
245 => X"00",
246 => X"34",
247 => X"00",
248 => X"4b",
249 => X"00",
250 => X"5f",
251 => X"00",
252 => X"6e",
253 => X"00",
254 => X"79",
255 => X"00",
256 => X"7f",
257 => X"00",
258 => X"7f",
259 => X"00",
260 => X"79",
261 => X"00",
262 => X"6e",
263 => X"00",
264 => X"5f",
265 => X"00",
266 => X"4b",
267 => X"00",
268 => X"34",
269 => X"00",
270 => X"1a",
271 => X"00",
272 => X"00",
273 => X"00",
274 => X"e6",
275 => X"00",
276 => X"cc",
277 => X"00",
278 => X"b5",
279 => X"00",
280 => X"a1",
281 => X"00",
282 => X"92",
283 => X"00",
284 => X"87",
285 => X"00",
286 => X"81",
287 => X"00",
288 => X"81",
289 => X"00",
290 => X"87",
291 => X"00",
292 => X"92",
293 => X"00",
294 => X"a1",
295 => X"00",
296 => X"b5",
297 => X"00",
298 => X"cc",
299 => X"00",
300 => X"e6",
301 => X"00",
302 => X"00",
303 => X"00",
304 => X"1a",
305 => X"00",
306 => X"34",
307 => X"00",
308 => X"4b",
309 => X"00",
310 => X"5f",
311 => X"00",
312 => X"6e",
313 => X"00",
314 => X"79",
315 => X"00",
316 => X"7f",
317 => X"00",
318 => X"7f",
319 => X"00",
320 => X"79",
321 => X"00",
322 => X"6e",
323 => X"00",
324 => X"5f",
325 => X"00",
326 => X"4b",
327 => X"00",
328 => X"34",
329 => X"00",
330 => X"1a",
331 => X"00",
332 => X"00",
333 => X"00",
334 => X"e6",
335 => X"00",
336 => X"cc",
337 => X"00",
338 => X"b5",
339 => X"00",
340 => X"a1",
341 => X"00",
342 => X"92",
343 => X"00",
344 => X"87",
345 => X"00",
346 => X"81",
347 => X"00",
348 => X"81",
349 => X"00",
350 => X"87",
351 => X"00",
352 => X"92",
353 => X"00",
354 => X"a1",
355 => X"00",
356 => X"b5",
357 => X"00",
358 => X"cc",
359 => X"00",
360 => X"e6",
361 => X"00",
362 => X"00",
363 => X"00",
364 => X"1a",
365 => X"00",
366 => X"34",
367 => X"00",
368 => X"4b",
369 => X"00",
370 => X"5f",
371 => X"00",
372 => X"6e",
373 => X"00",
374 => X"79",
375 => X"00",
376 => X"7f",
377 => X"00",
378 => X"7f",
379 => X"00",
380 => X"79",
381 => X"00",
382 => X"6e",
383 => X"00",
384 => X"5f",
385 => X"00",
386 => X"4b",
387 => X"00",
388 => X"34",
389 => X"00",
390 => X"1a",
391 => X"00",
392 => X"00",
393 => X"00",
394 => X"e6",
395 => X"00",
396 => X"cc",
397 => X"00",
398 => X"b5",
399 => X"00",
400 => X"a1",
401 => X"00",
402 => X"92",
403 => X"00",
404 => X"87",
405 => X"00",
406 => X"81",
407 => X"00",
408 => X"81",
409 => X"00",
410 => X"87",
411 => X"00",
412 => X"92",
413 => X"00",
414 => X"a1",
415 => X"00",
416 => X"b5",
417 => X"00",
418 => X"cc",
419 => X"00",
420 => X"e6",
421 => X"00",
422 => X"00",
423 => X"00",
424 => X"1a",
425 => X"00",
426 => X"34",
427 => X"00",
428 => X"4b",
429 => X"00",
430 => X"5f",
431 => X"00",
432 => X"6e",
433 => X"00",
434 => X"79",
435 => X"00",
436 => X"7f",
437 => X"00",
438 => X"7f",
439 => X"00",
440 => X"79",
441 => X"00",
442 => X"6e",
443 => X"00",
444 => X"5f",
445 => X"00",
446 => X"4b",
447 => X"00",
448 => X"34",
449 => X"00",
450 => X"1a",
451 => X"00",
452 => X"00",
453 => X"00",
454 => X"e6",
455 => X"00",
456 => X"cc",
457 => X"00",
458 => X"b5",
459 => X"00",
460 => X"a1",
461 => X"00",
462 => X"92",
463 => X"00",
464 => X"87",
465 => X"00",
466 => X"81",
467 => X"00",
468 => X"81",
469 => X"00",
470 => X"87",
471 => X"00",
472 => X"92",
473 => X"00",
474 => X"a1",
475 => X"00",
476 => X"b5",
477 => X"00",
478 => X"cc",
479 => X"00",
480 => X"e6",
481 => X"00",
482 => X"00",
483 => X"00",
484 => X"1a",
485 => X"00",
486 => X"34",
487 => X"00",
488 => X"4b",
489 => X"00",
490 => X"5f",
491 => X"00",
492 => X"6e",
493 => X"00",
494 => X"79",
495 => X"00",
496 => X"7f",
497 => X"00",
498 => X"7f",
499 => X"00",
500 => X"79",
501 => X"00",
502 => X"6e",
503 => X"00",
504 => X"5f",
505 => X"00",
506 => X"4b",
507 => X"00",
508 => X"34",
509 => X"00",
510 => X"1a",
511 => X"00",
512 => X"00",
513 => X"00",
others => X"00");
procedure hex2slv(c : character; slv : out std_logic_vector(3 downto 0); good : out boolean) is
begin
good := true;
case c is
when 'A' to 'F' => slv := std_logic_vector(to_unsigned(character'pos(c) - character'pos('A') + 10, 4)); return;
when 'a' to 'f' => slv := std_logic_vector(to_unsigned(character'pos(c) - character'pos('a') + 10, 4)); return;
when '0' to '9' => slv := std_logic_vector(to_unsigned(character'pos(c) - character'pos('0'), 4)); return;
when others => good := false; return;
end case;
end procedure;
signal init : boolean := false;
begin
process
begin
clk <= '1';
clk2x <= '1';
wait for 5 ns;
clk2x <= '0';
wait for 5 ns;
clk <= '0';
clk2x <= '1';
wait for 5 ns;
clk2x <= '0';
wait for 5 ns;
end process;
process(clk)
file memfile : text;
variable fname : string(1 to 63) := "/home/notti/uni/master/dis_vertiefung/se/project/src/fft_mp.mem";
variable buf_in, buf_out : line;
variable f_status : FILE_OPEN_STATUS;
variable good: boolean := true;
variable o: character;
variable i: integer := 1;
variable val: std_logic_vector(15 downto 0);
variable r: boolean := true;
variable ok:boolean := false;
variable ser_out : integer;
begin
if rising_edge(clk) then
if rst = '1' and init = false then
file_open(f_status, memfile, fname, read_mode);
readline(memfile, buf_in);
for j in 0 to 4 loop
read(buf_in, o, good);
assert good report "memfile error" severity failure;
end loop;
i := 0;
loop
read(buf_in, o, good);
exit when not good;
assert o = ' ' report "memfile error: " & o severity failure;
for j in 0 to 3 loop
read(buf_in, o, good);
assert good report "memfile error" severity failure;
hex2slv(o, val((j+1)*4-1 downto j*4), good);
assert good report "memfile error" severity failure;
end loop;
mem(i) <= val;
i := i + 1;
end loop;
assert false report "read " & integer'image(i) & " tokens" severity note;
init <= true;
i := 0;
elsif rst = '0' then
if ena = '1' then
doa <= mem(to_integer(unsigned(addra)));
end if;
if enb = '1' then
if addrb = X"FFFF" then
if web = "00" then
if i = 514 then
assert false report "stop" severity failure;
end if;
dob <= serial(i) & serial(i);
i := i + 1;
else
if web(0) = '1' then
ser_out := to_integer(signed(dib(7 downto 0)));
else
ser_out := to_integer(signed(dib(15 downto 8)));
end if;
if not ok then
if ser_out = 49 then
ok := true;
else
assert false report "no ok received!" severity failure;
end if;
else
if r then
write(buf_out, ser_out);
write(buf_out, ',');
write(buf_out, ' ');
r := false;
else
write(buf_out, ser_out);
writeline(output, buf_out);
r := true;
end if;
end if;
end if;
else
dob <= mem(to_integer(unsigned(addrb)));
if web(1) = '1' then
mem(to_integer(unsigned(addrb)))(15 downto 8) <= dib(15 downto 8);
end if;
if web(0) = '1' then
mem(to_integer(unsigned(addrb)))(7 downto 0) <= dib(7 downto 0);
end if;
end if;
end if;
end if;
end if;
end process;
process
begin
wait for 61 ns;
rst <= '0';
wait for 20 ns;
end process;
asoc: entity work.cpu
port map(
rst => rst,
clk => clk,
clk2x => clk2x,
ena => ena,
addra => addra,
doa => doa,
enb => enb,
addrb => addrb,
dob => dob,
web => web,
dib => dib,
bbusy => bbusy
);
end behav;
| bsd-2-clause | 4aead2abbf2455635acb6f39cb707b26 | 0.309016 | 3.483414 | false | false | false | false |
fafaldo/ethernet | ethernet4b/MAC_destination.vhd | 1 | 1,585 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MAC_destination is
port( data_in : in std_logic_vector(7 downto 0);
enable : in std_logic;
reset : in std_logic;
clk : in std_logic;
destination_MAC : out std_logic_vector(47 downto 0)
);
end MAC_destination;
architecture Behavioral of MAC_destination is
signal address_counter : std_logic_vector(10 downto 0) := (others=>'0');
begin
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
address_counter <= (others=>'0');
elsif enable = '1' then
address_counter <= address_counter+1;
end if;
end if;
end process;
process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
destination_MAC <= (others=>'0');
elsif address_counter = 1 then
destination_MAC(47 downto 40) <= data_in;
elsif address_counter = 2 then
destination_MAC(39 downto 32) <= data_in;
elsif address_counter = 3 then
destination_MAC(31 downto 24) <= data_in;
elsif address_counter = 4 then
destination_MAC(23 downto 16) <= data_in;
elsif address_counter = 5 then
destination_MAC(15 downto 8) <= data_in;
elsif address_counter = 6 then
destination_MAC(7 downto 0) <= data_in;
end if;
end if;
end process;
end Behavioral; | apache-2.0 | 1c0a0face46d150aadbf98e9ddb540e7 | 0.690221 | 3.288382 | false | false | false | false |
keith-epidev/VHDL-lib | top/lab_5/part_1/ip/fft/xfft_v9_0/hdl/xfft_v9_0_fp.vhd | 2 | 84,613 | `protect begin_protected
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`protect end_protected
| gpl-2.0 | 17fcf20b7bb7e77b04a117de0a925419 | 0.952088 | 1.815262 | false | false | false | false |
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